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4389
Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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4389
Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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/**
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******************************************************************************
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* @file stm32_hal_legacy.h
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* @author MCD Application Team
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* @brief This file contains aliases definition for the STM32Cube HAL constants
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* macros and functions maintained for legacy purpose.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32_HAL_LEGACY
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#define STM32_HAL_LEGACY
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define AES_FLAG_RDERR CRYP_FLAG_RDERR
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#define AES_FLAG_WRERR CRYP_FLAG_WRERR
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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#if defined(STM32H7) || defined(STM32MP1)
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#define CRYP_DATATYPE_32B CRYP_NO_SWAP
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#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
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#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
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#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
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#endif /* STM32H7 || STM32MP1 */
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/**
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* @}
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*/
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/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
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#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
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#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
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#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
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#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
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#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
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#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
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#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
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#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
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#define REGULAR_GROUP ADC_REGULAR_GROUP
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#define INJECTED_GROUP ADC_INJECTED_GROUP
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#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
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#define AWD_EVENT ADC_AWD_EVENT
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#define AWD1_EVENT ADC_AWD1_EVENT
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#define AWD2_EVENT ADC_AWD2_EVENT
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#define AWD3_EVENT ADC_AWD3_EVENT
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#define OVR_EVENT ADC_OVR_EVENT
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#define JQOVF_EVENT ADC_JQOVF_EVENT
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#define ALL_CHANNELS ADC_ALL_CHANNELS
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#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
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#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
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#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
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#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
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#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
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#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
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#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
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#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
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#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
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#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
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#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
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#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
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#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
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#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
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#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
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#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
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#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
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#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
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#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
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#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
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#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
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#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
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#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
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#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
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#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
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#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
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#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
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#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
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#if defined(STM32H7)
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#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
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#endif /* STM32H7 */
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#if defined(STM32U5)
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#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
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#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
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#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
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#endif /* STM32U5 */
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#if defined(STM32H5)
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#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
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#endif /* STM32H5 */
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/**
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* @}
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*/
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/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
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/**
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* @}
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*/
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/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
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#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
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#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
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#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
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#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
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#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
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#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
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#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
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#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
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#if defined(STM32L0)
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#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
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input 1 for COMP1, LPTIM input 2 for COMP2 */
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#endif
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#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
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#if defined(STM32F373xC) || defined(STM32F378xx)
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#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
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#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
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#endif /* STM32F373xC || STM32F378xx */
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#if defined(STM32L0) || defined(STM32L4)
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#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
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#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
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#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
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#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
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#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
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#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
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#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
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#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
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#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
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#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
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#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
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#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
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#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
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#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
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#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
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#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
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#if defined(STM32L0)
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/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
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/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
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/* to the second dedicated IO (only for COMP2). */
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#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
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#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
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#else
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#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
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#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
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#endif
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#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
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#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
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#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
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#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
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/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
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/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
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#if defined(COMP_CSR_LOCK)
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#define COMP_FLAG_LOCK COMP_CSR_LOCK
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#elif defined(COMP_CSR_COMP1LOCK)
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#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
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#elif defined(COMP_CSR_COMPxLOCK)
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#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
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#endif
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#if defined(STM32L4)
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#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
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#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
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#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
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#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
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#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
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#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
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#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
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#endif
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#if defined(STM32L0)
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#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
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#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
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#else
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#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
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#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
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#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
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#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
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#endif
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#endif
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#if defined(STM32U5)
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#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
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#endif
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/**
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* @}
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*/
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/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
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#if defined(STM32U5)
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#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
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#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
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#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
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#endif /* STM32U5 */
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/**
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* @}
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*/
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/** @defgroup CRC_Aliases CRC API aliases
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* @{
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*/
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#if defined(STM32H5) || defined(STM32C0)
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#else
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#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
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inter STM32 series compatibility */
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#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
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inter STM32 series compatibility */
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#endif
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/**
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* @}
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*/
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/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
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#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
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/**
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* @}
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*/
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/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
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* @{
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*/
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#define DAC1_CHANNEL_1 DAC_CHANNEL_1
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#define DAC1_CHANNEL_2 DAC_CHANNEL_2
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#define DAC2_CHANNEL_1 DAC_CHANNEL_1
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#define DAC_WAVE_NONE 0x00000000U
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#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
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#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
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#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
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#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
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#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
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#if defined(STM32U5)
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#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
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#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
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#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
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#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
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#endif
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#if defined(STM32H5)
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#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
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#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
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#endif
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#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
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defined(STM32F4) || defined(STM32G4)
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#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
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#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
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#endif
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/**
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* @}
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*/
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/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
|
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* @{
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*/
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#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
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#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
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#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
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#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
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#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
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#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
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#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
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#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
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#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
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#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
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#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
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#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
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#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
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#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
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#define IS_HAL_REMAPDMA IS_DMA_REMAP
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#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
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#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
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||||
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||||
#if defined(STM32L4)
|
||||
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||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
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||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
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||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
|
||||
|
||||
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||
|
||||
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
|
||||
defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
|
||||
#endif
|
||||
|
||||
#endif /* STM32L4 */
|
||||
|
||||
#if defined(STM32G0)
|
||||
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
|
||||
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
|
||||
#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
|
||||
#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
|
||||
|
||||
#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
|
||||
#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
|
||||
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
|
||||
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
|
||||
|
||||
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
|
||||
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
|
||||
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
|
||||
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
|
||||
|
||||
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||
|
||||
#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
|
||||
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
|
||||
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
|
||||
|
||||
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
|
||||
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
|
||||
#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
|
||||
#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
|
||||
#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
|
||||
#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
|
||||
#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
|
||||
#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
|
||||
#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
|
||||
#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
|
||||
#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
|
||||
#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
|
||||
#define OBEX_PCROP OPTIONBYTE_PCROP
|
||||
#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
|
||||
#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
|
||||
#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
|
||||
#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
|
||||
#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
|
||||
#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
|
||||
#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
|
||||
#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
|
||||
#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
|
||||
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
|
||||
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
|
||||
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
|
||||
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7)
|
||||
#define PAGESIZE FLASH_PAGE_SIZE
|
||||
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */
|
||||
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
|
||||
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
|
||||
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
|
||||
#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
|
||||
#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
|
||||
#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
|
||||
#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
|
||||
#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
|
||||
#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
|
||||
#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
|
||||
#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
|
||||
#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
|
||||
#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
|
||||
#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
|
||||
#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
|
||||
#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
|
||||
#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
|
||||
#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
|
||||
#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
|
||||
#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
|
||||
#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
|
||||
#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
|
||||
#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
|
||||
#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
|
||||
#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
|
||||
#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
|
||||
#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
|
||||
#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
|
||||
#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
|
||||
#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
|
||||
#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
|
||||
#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
|
||||
#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
|
||||
#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
|
||||
#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
|
||||
#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
|
||||
#define OB_WDG_SW OB_IWDG_SW
|
||||
#define OB_WDG_HW OB_IWDG_HW
|
||||
#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
|
||||
#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
|
||||
#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
|
||||
#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
|
||||
#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
|
||||
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
|
||||
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
|
||||
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
|
||||
#if defined(STM32G0) || defined(STM32C0)
|
||||
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
|
||||
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
|
||||
#else
|
||||
#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
|
||||
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
|
||||
#endif
|
||||
#if defined(STM32H7)
|
||||
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
|
||||
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
|
||||
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
|
||||
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
||||
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
||||
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
||||
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
|
||||
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
|
||||
#endif /* STM32H7 */
|
||||
#if defined(STM32U5)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
|
||||
#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
|
||||
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
|
||||
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
|
||||
#endif /* STM32U5 */
|
||||
#if defined(STM32U0)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
|
||||
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_USER_nBOOT1 OB_USER_NBOOT1
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#endif /* STM32U0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
|
||||
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
|
||||
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
|
||||
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
|
||||
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
|
||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
|
||||
#if defined(STM32G4)
|
||||
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
|
||||
#endif /* STM32G4 */
|
||||
|
||||
#if defined(STM32U5)
|
||||
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
|
||||
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
|
||||
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
|
||||
#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
|
||||
#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
|
||||
#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
|
||||
#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
|
||||
|
||||
#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
|
||||
#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
|
||||
#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
|
||||
#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
|
||||
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
|
||||
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
|
||||
|
||||
#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
|
||||
#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
|
||||
#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
|
||||
#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
|
||||
|
||||
#define SYSCFG_ETH_MII SBS_ETH_MII
|
||||
#define SYSCFG_ETH_RMII SBS_ETH_RMII
|
||||
#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
|
||||
|
||||
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
|
||||
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
|
||||
#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
|
||||
|
||||
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
|
||||
|
||||
#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
|
||||
#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SYSCFG_SAU SBS_SAU
|
||||
#define SYSCFG_MPU_SEC SBS_MPU_SEC
|
||||
#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
|
||||
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
|
||||
#else
|
||||
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define SYSCFG_CLK SBS_CLK
|
||||
#define SYSCFG_CLASSB SBS_CLASSB
|
||||
#define SYSCFG_FPU SBS_FPU
|
||||
#define SYSCFG_ALL SBS_ALL
|
||||
|
||||
#define SYSCFG_SEC SBS_SEC
|
||||
#define SYSCFG_NSEC SBS_NSEC
|
||||
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
|
||||
|
||||
#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
|
||||
|
||||
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
|
||||
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
|
||||
|
||||
#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
|
||||
#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
|
||||
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
|
||||
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
|
||||
#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
|
||||
#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
|
||||
#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
|
||||
#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
|
||||
#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
|
||||
|
||||
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
|
||||
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
|
||||
#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
|
||||
#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
|
||||
#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
|
||||
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
|
||||
#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
|
||||
|
||||
#define HAL_SYSCFG_Lock HAL_SBS_Lock
|
||||
#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
|
||||
#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#endif /* STM32H5 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
|
||||
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
|
||||
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
|
||||
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
|
||||
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
|
||||
#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
|
||||
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
|
||||
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
|
||||
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
|
||||
#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
|
||||
#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define GET_GPIO_SOURCE GPIO_GET_INDEX
|
||||
#define GET_GPIO_INDEX GPIO_GET_INDEX
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
|
||||
#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
|
||||
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4)
|
||||
#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
|
||||
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
|
||||
#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
|
||||
#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
|
||||
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
|
||||
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
|
||||
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
|
||||
|
||||
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
|
||||
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
|
||||
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
|
||||
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
|
||||
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
|
||||
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
|
||||
STM32H757xx */
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
||||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
|
||||
defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
|
||||
|
||||
#if defined(STM32L1)
|
||||
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||
#endif /* STM32L1 */
|
||||
|
||||
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
|
||||
#endif /* STM32F0 || STM32F3 || STM32F1 */
|
||||
|
||||
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
|
||||
|
||||
#if defined(STM32U5) || defined(STM32H5)
|
||||
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
|
||||
#endif /* STM32U5 || STM32H5 */
|
||||
#if defined(STM32U5)
|
||||
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
|
||||
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32WBA)
|
||||
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
|
||||
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
|
||||
#endif /* STM32WBA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32U5)
|
||||
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
|
||||
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
|
||||
#endif /* STM32U5 */
|
||||
#if defined(STM32H5)
|
||||
#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
|
||||
#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
|
||||
#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
|
||||
#endif /* STM32H5 */
|
||||
#if defined(STM32H5) || defined(STM32U5)
|
||||
#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
|
||||
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
|
||||
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
|
||||
#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
|
||||
#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
|
||||
#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
|
||||
#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
|
||||
#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
|
||||
#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
|
||||
#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
|
||||
#endif /* STM32H5 || STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
|
||||
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
|
||||
|
||||
#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
|
||||
#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
|
||||
#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
|
||||
#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
|
||||
#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
|
||||
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
|
||||
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
|
||||
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
|
||||
|
||||
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
|
||||
#define HRTIMInterruptResquests HRTIMInterruptRequests
|
||||
#endif /* STM32F3 || STM32G4 || STM32H7 */
|
||||
|
||||
#if defined(STM32G4)
|
||||
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
|
||||
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
|
||||
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
|
||||
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
|
||||
#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
|
||||
#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
|
||||
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
|
||||
#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
|
||||
#endif /* STM32G4 */
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32F3)
|
||||
/** @brief Constants defining available sources associated to external events.
|
||||
*/
|
||||
#define HRTIM_EVENTSRC_1 (0x00000000U)
|
||||
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
|
||||
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
|
||||
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
|
||||
|
||||
/** @brief Constants defining the DLL calibration periods (in micro seconds)
|
||||
*/
|
||||
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
|
||||
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
|
||||
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
|
||||
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
|
||||
#endif /* STM32F3 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
|
||||
#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
|
||||
#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
|
||||
#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
|
||||
#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
|
||||
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
|
||||
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
|
||||
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
|
||||
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
|
||||
defined(STM32L1) || defined(STM32F7)
|
||||
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
|
||||
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
|
||||
#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define KR_KEY_RELOAD IWDG_KEY_RELOAD
|
||||
#define KR_KEY_ENABLE IWDG_KEY_ENABLE
|
||||
#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
|
||||
#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
|
||||
#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
|
||||
#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
|
||||
#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
|
||||
|
||||
#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
|
||||
#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
|
||||
#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
|
||||
|
||||
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
|
||||
#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
|
||||
|
||||
/* The following 3 definition have also been present in a temporary version of lptim.h */
|
||||
/* They need to be renamed also to the right name, just in case */
|
||||
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
|
||||
|
||||
|
||||
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
|
||||
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
|
||||
#define LPTIM_CHANNEL_ALL 0x00000000U
|
||||
#endif /* STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
|
||||
#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
|
||||
#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
|
||||
#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
|
||||
|
||||
#define NAND_AddressTypedef NAND_AddressTypeDef
|
||||
|
||||
#define __ARRAY_ADDRESS ARRAY_ADDRESS
|
||||
#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
|
||||
#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
|
||||
#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
|
||||
#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
|
||||
#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
|
||||
#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
|
||||
#define NOR_ERROR HAL_NOR_STATUS_ERROR
|
||||
#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
|
||||
|
||||
#define __NOR_WRITE NOR_WRITE
|
||||
#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
|
||||
#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
|
||||
#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
|
||||
#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
|
||||
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
|
||||
|
||||
#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
|
||||
#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
|
||||
|
||||
#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
|
||||
#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
|
||||
|
||||
#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
|
||||
#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
|
||||
|
||||
#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
|
||||
|
||||
#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
|
||||
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
|
||||
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
|
||||
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
|
||||
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4) || defined(STM32L5)
|
||||
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
|
||||
#elif defined(STM32G4)
|
||||
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define I2S_IT_TXE I2S_IT_TXP
|
||||
#define I2S_IT_RXNE I2S_IT_RXP
|
||||
|
||||
#define I2S_FLAG_TXE I2S_FLAG_TXP
|
||||
#define I2S_FLAG_RXNE I2S_FLAG_RXP
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Compact Flash-ATA registers description */
|
||||
#define CF_DATA ATA_DATA
|
||||
#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
|
||||
#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
|
||||
#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
|
||||
#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
|
||||
#define CF_CARD_HEAD ATA_CARD_HEAD
|
||||
#define CF_STATUS_CMD ATA_STATUS_CMD
|
||||
#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
|
||||
#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
|
||||
|
||||
/* Compact Flash-ATA commands */
|
||||
#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
|
||||
#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
|
||||
#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
|
||||
#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
|
||||
|
||||
#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
|
||||
#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
|
||||
#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
|
||||
#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
|
||||
#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FORMAT_BIN RTC_FORMAT_BIN
|
||||
#define FORMAT_BCD RTC_FORMAT_BCD
|
||||
|
||||
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
|
||||
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
|
||||
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
|
||||
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
|
||||
|
||||
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
|
||||
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
|
||||
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
|
||||
#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
|
||||
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
|
||||
|
||||
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
|
||||
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
|
||||
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
|
||||
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
|
||||
|
||||
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
|
||||
#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
|
||||
#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
|
||||
|
||||
#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
|
||||
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
||||
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
||||
|
||||
#if defined(STM32H5) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
|
||||
#endif /* STM32H5 || STM32H7RS */
|
||||
|
||||
#if defined(STM32WBA)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
|
||||
#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
|
||||
#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
|
||||
#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
|
||||
#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
|
||||
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
|
||||
#endif /* STM32WBA */
|
||||
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
|
||||
#endif /* STM32F7 */
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
|
||||
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
|
||||
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
|
||||
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
|
||||
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
|
||||
#endif /* STM32F7 || STM32H7 || STM32L0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
|
||||
#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
|
||||
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
|
||||
#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
|
||||
|
||||
#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
|
||||
#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
|
||||
|
||||
#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
|
||||
#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
|
||||
#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
|
||||
#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
|
||||
#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
|
||||
#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
|
||||
#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
|
||||
#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
|
||||
#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
|
||||
#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
|
||||
#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
|
||||
#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
|
||||
#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
|
||||
|
||||
#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
|
||||
#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
|
||||
|
||||
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
|
||||
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
|
||||
|
||||
#if defined(STM32H7)
|
||||
|
||||
#define SPI_FLAG_TXE SPI_FLAG_TXP
|
||||
#define SPI_FLAG_RXNE SPI_FLAG_RXP
|
||||
|
||||
#define SPI_IT_TXE SPI_IT_TXP
|
||||
#define SPI_IT_RXNE SPI_IT_RXP
|
||||
|
||||
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
|
||||
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
|
||||
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
|
||||
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
|
||||
#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
|
||||
|
||||
#define TIM_DMABase_CR1 TIM_DMABASE_CR1
|
||||
#define TIM_DMABase_CR2 TIM_DMABASE_CR2
|
||||
#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
|
||||
#define TIM_DMABase_DIER TIM_DMABASE_DIER
|
||||
#define TIM_DMABase_SR TIM_DMABASE_SR
|
||||
#define TIM_DMABase_EGR TIM_DMABASE_EGR
|
||||
#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
|
||||
#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
|
||||
#define TIM_DMABase_CCER TIM_DMABASE_CCER
|
||||
#define TIM_DMABase_CNT TIM_DMABASE_CNT
|
||||
#define TIM_DMABase_PSC TIM_DMABASE_PSC
|
||||
#define TIM_DMABase_ARR TIM_DMABASE_ARR
|
||||
#define TIM_DMABase_RCR TIM_DMABASE_RCR
|
||||
#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
|
||||
#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
|
||||
#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
|
||||
#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
|
||||
#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
|
||||
#define TIM_DMABase_DCR TIM_DMABASE_DCR
|
||||
#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
|
||||
#define TIM_DMABase_OR1 TIM_DMABASE_OR1
|
||||
#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
|
||||
#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
|
||||
#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
|
||||
#define TIM_DMABase_OR2 TIM_DMABASE_OR2
|
||||
#define TIM_DMABase_OR3 TIM_DMABASE_OR3
|
||||
#define TIM_DMABase_OR TIM_DMABASE_OR
|
||||
|
||||
#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
|
||||
#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
|
||||
#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
|
||||
#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
|
||||
#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
|
||||
#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
|
||||
#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
|
||||
#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
|
||||
#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
|
||||
|
||||
#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
|
||||
#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
|
||||
#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
|
||||
#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
|
||||
#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
|
||||
#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
|
||||
#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
|
||||
#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
|
||||
#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
|
||||
#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
|
||||
#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
|
||||
#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
|
||||
#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
|
||||
#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
|
||||
#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
|
||||
#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
|
||||
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
|
||||
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
|
||||
|
||||
#if defined(STM32L0)
|
||||
#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
|
||||
#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
|
||||
#endif
|
||||
|
||||
#if defined(STM32F3)
|
||||
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
|
||||
#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
|
||||
#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
|
||||
#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
|
||||
#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
|
||||
#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
|
||||
#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
|
||||
#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
|
||||
#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
|
||||
#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
|
||||
#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
|
||||
#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
|
||||
#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
|
||||
#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
|
||||
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
|
||||
#endif
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
|
||||
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
|
||||
#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
|
||||
#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
|
||||
#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
|
||||
#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
|
||||
|
||||
#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
|
||||
#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
|
||||
|
||||
#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
|
||||
#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
|
||||
#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
|
||||
#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
|
||||
|
||||
#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
|
||||
#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
|
||||
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
|
||||
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
|
||||
|
||||
#define __DIV_LPUART UART_DIV_LPUART
|
||||
|
||||
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
|
||||
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
|
||||
#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
|
||||
|
||||
#define USARTNACK_ENABLED USART_NACK_ENABLE
|
||||
#define USARTNACK_DISABLED USART_NACK_DISABLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define CFR_BASE WWDG_CFR_BASE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
|
||||
#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
|
||||
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
|
||||
#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
|
||||
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define VLAN_TAG ETH_VLAN_TAG
|
||||
#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
|
||||
#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
|
||||
#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
|
||||
#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
|
||||
#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
|
||||
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
|
||||
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
|
||||
|
||||
#define ETH_MMCCR 0x00000100U
|
||||
#define ETH_MMCRIR 0x00000104U
|
||||
#define ETH_MMCTIR 0x00000108U
|
||||
#define ETH_MMCRIMR 0x0000010CU
|
||||
#define ETH_MMCTIMR 0x00000110U
|
||||
#define ETH_MMCTGFSCCR 0x0000014CU
|
||||
#define ETH_MMCTGFMSCCR 0x00000150U
|
||||
#define ETH_MMCTGFCR 0x00000168U
|
||||
#define ETH_MMCRFCECR 0x00000194U
|
||||
#define ETH_MMCRFAECR 0x00000198U
|
||||
#define ETH_MMCRGUFCR 0x000001C4U
|
||||
|
||||
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
|
||||
the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
|
||||
MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
|
||||
or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
|
||||
of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
|
||||
transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
|
||||
frame for transmission */
|
||||
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
|
||||
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
|
||||
de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
|
||||
activate threshold */
|
||||
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
|
||||
#if defined(STM32F1)
|
||||
#else
|
||||
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
|
||||
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
|
||||
(or time-stamp) */
|
||||
#endif
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
|
||||
status */
|
||||
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
|
||||
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
|
||||
|
||||
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
|
||||
#define DCMI_IT_OVF DCMI_IT_OVR
|
||||
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
|
||||
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
|
||||
|
||||
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
|
||||
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
|
||||
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|
||||
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|
||||
|| defined(STM32H7)
|
||||
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
|
||||
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
|
||||
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
|
||||
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
|
||||
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
|
||||
|
||||
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
|
||||
#define CM_RGB888 DMA2D_INPUT_RGB888
|
||||
#define CM_RGB565 DMA2D_INPUT_RGB565
|
||||
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
|
||||
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
|
||||
#define CM_L8 DMA2D_INPUT_L8
|
||||
#define CM_AL44 DMA2D_INPUT_AL44
|
||||
#define CM_AL88 DMA2D_INPUT_AL88
|
||||
#define CM_L4 DMA2D_INPUT_L4
|
||||
#define CM_A8 DMA2D_INPUT_A8
|
||||
#define CM_A4 DMA2D_INPUT_A4
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
|
||||
|
||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|
||||
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|
||||
|| defined(STM32H7) || defined(STM32U5)
|
||||
/** @defgroup DMA2D_Aliases DMA2D API Aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
|
||||
for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32U5)
|
||||
#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
|
||||
#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
|
||||
#endif /* STM32U5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if !defined(STM32F2)
|
||||
/** @defgroup HASH_alias HASH API alias
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
|
||||
/**
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F2 */
|
||||
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
|
||||
#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
|
||||
#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
|
||||
#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
|
||||
#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
|
||||
#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
|
||||
|
||||
/*HASH Algorithm Selection*/
|
||||
|
||||
#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
|
||||
#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
|
||||
#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
|
||||
#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
|
||||
|
||||
#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
|
||||
#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
|
||||
|
||||
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
|
||||
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
|
||||
|
||||
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
|
||||
|
||||
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
|
||||
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
|
||||
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
|
||||
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
|
||||
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
|
||||
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
|
||||
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
|
||||
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
|
||||
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
|
||||
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
|
||||
|
||||
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
|
||||
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
|
||||
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
|
||||
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
|
||||
|
||||
#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
|
||||
#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
|
||||
#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
|
||||
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
|
||||
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
|
||||
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
|
||||
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
|
||||
HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
|
||||
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
|
||||
#if defined(STM32L0)
|
||||
#else
|
||||
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
|
||||
#endif
|
||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
|
||||
HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
|
||||
defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
|
||||
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
|
||||
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
|
||||
#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
|
||||
#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
|
||||
#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
|
||||
#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
|
||||
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
|
||||
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
|
||||
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
|
||||
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
|
||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
|
||||
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
|
||||
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
|
||||
defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
|
||||
defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
|
||||
STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
|
||||
defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
|
||||
#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
|
||||
#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
|
||||
#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
|
||||
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
|
||||
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
|
||||
#endif /* STM32F4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32G0)
|
||||
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
|
||||
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
|
||||
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
|
||||
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
|
||||
#endif
|
||||
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
|
||||
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
|
||||
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
|
||||
#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
|
||||
#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
|
||||
#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
|
||||
#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
|
||||
#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
|
||||
#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
|
||||
#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
|
||||
#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
|
||||
#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
|
||||
#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
|
||||
#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
|
||||
#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
|
||||
#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
|
||||
|
||||
#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
|
||||
#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
|
||||
#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
|
||||
#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
|
||||
#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
|
||||
#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
|
||||
#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
|
||||
|
||||
#define CR_OFFSET_BB PWR_CR_OFFSET_BB
|
||||
#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
|
||||
#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
|
||||
#define CR_PMODE_BB CR_VOS_BB
|
||||
|
||||
#define DBP_BitNumber DBP_BIT_NUMBER
|
||||
#define PVDE_BitNumber PVDE_BIT_NUMBER
|
||||
#define PMODE_BitNumber PMODE_BIT_NUMBER
|
||||
#define EWUP_BitNumber EWUP_BIT_NUMBER
|
||||
#define FPDS_BitNumber FPDS_BIT_NUMBER
|
||||
#define ODEN_BitNumber ODEN_BIT_NUMBER
|
||||
#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
|
||||
#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
|
||||
#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
|
||||
#define BRE_BitNumber BRE_BIT_NUMBER
|
||||
|
||||
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
|
||||
|
||||
#if defined (STM32U5)
|
||||
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
|
||||
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
|
||||
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
|
||||
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
|
||||
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
|
||||
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
|
||||
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
|
||||
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
|
||||
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
|
||||
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
|
||||
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
|
||||
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
|
||||
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
|
||||
|
||||
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
|
||||
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
|
||||
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
|
||||
|
||||
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
|
||||
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
|
||||
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
|
||||
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
|
||||
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
|
||||
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
|
||||
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
|
||||
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
|
||||
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
|
||||
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
|
||||
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
|
||||
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
|
||||
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
|
||||
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
|
||||
|
||||
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
|
||||
|
||||
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
|
||||
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
|
||||
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
|
||||
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
|
||||
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
|
||||
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
|
||||
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
|
||||
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
|
||||
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
|
||||
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
|
||||
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
|
||||
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
|
||||
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
|
||||
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
|
||||
|
||||
#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
|
||||
#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
|
||||
#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
|
||||
#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
|
||||
#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
|
||||
#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
|
||||
#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
|
||||
#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
|
||||
#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
|
||||
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
|
||||
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
|
||||
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
|
||||
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
|
||||
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
|
||||
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
|
||||
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
|
||||
#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
|
||||
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
|
||||
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
|
||||
|
||||
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
|
||||
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
|
||||
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
|
||||
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
|
||||
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
|
||||
#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
|
||||
|
||||
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
|
||||
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
|
||||
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
|
||||
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
|
||||
#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
|
||||
#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
|
||||
#define HAL_TIM_DMAError TIM_DMAError
|
||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
|
||||
defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
|
||||
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
|
||||
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
|
||||
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
|
||||
#define HAL_LTDC_Relaod HAL_LTDC_Reload
|
||||
#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
|
||||
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define AES_IT_CC CRYP_IT_CC
|
||||
#define AES_IT_ERR CRYP_IT_ERR
|
||||
#define AES_FLAG_CCF CRYP_FLAG_CCF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
|
||||
#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
|
||||
#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
|
||||
#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
|
||||
#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
|
||||
#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
|
||||
#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
|
||||
#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
|
||||
#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
|
||||
#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
|
||||
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
|
||||
#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
|
||||
#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
|
||||
|
||||
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
|
||||
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
|
||||
#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
|
||||
#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
|
||||
#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __ADC_ENABLE __HAL_ADC_ENABLE
|
||||
#define __ADC_DISABLE __HAL_ADC_DISABLE
|
||||
#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
|
||||
#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
|
||||
#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
|
||||
#define __ADC_IS_ENABLED ADC_IS_ENABLE
|
||||
#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
|
||||
#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
|
||||
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
|
||||
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
|
||||
#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
|
||||
#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
|
||||
#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
|
||||
|
||||
#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
|
||||
#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
|
||||
#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
|
||||
#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
|
||||
#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
|
||||
#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
|
||||
#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
|
||||
#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
|
||||
#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
|
||||
#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
|
||||
#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
|
||||
#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
|
||||
#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
|
||||
#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
|
||||
#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
|
||||
#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
|
||||
#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
|
||||
#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
|
||||
#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
|
||||
#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
|
||||
|
||||
#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
|
||||
#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
|
||||
#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
|
||||
#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
|
||||
#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
|
||||
#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
|
||||
#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
|
||||
#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
|
||||
#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
|
||||
#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
|
||||
|
||||
#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
|
||||
#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
|
||||
#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
|
||||
#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
|
||||
#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
|
||||
#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
|
||||
#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
|
||||
#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
|
||||
|
||||
#define __HAL_ADC_SQR1 ADC_SQR1
|
||||
#define __HAL_ADC_SMPR1 ADC_SMPR1
|
||||
#define __HAL_ADC_SMPR2 ADC_SMPR2
|
||||
#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
|
||||
#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
|
||||
#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
|
||||
#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
|
||||
#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
|
||||
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
|
||||
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
|
||||
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
|
||||
#define __HAL_ADC_JSQR ADC_JSQR
|
||||
|
||||
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
|
||||
#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
|
||||
#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
|
||||
#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
|
||||
#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
|
||||
#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
|
||||
#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
|
||||
#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
|
||||
#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
|
||||
#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
|
||||
#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
|
||||
#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
|
||||
#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
|
||||
#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
|
||||
#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
|
||||
#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
|
||||
#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
|
||||
#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
|
||||
#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
|
||||
#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
|
||||
#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
|
||||
#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
|
||||
#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
|
||||
#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
|
||||
#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
|
||||
#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
|
||||
|
||||
#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
|
||||
#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
|
||||
#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
|
||||
#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
|
||||
#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
|
||||
#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
|
||||
#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
|
||||
#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
|
||||
#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
|
||||
#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
|
||||
#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
|
||||
#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
|
||||
#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
|
||||
#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
|
||||
|
||||
|
||||
#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
|
||||
#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
|
||||
#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
|
||||
#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
|
||||
#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
|
||||
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
|
||||
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
|
||||
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||
#else
|
||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||
#endif /* STM32H7 */
|
||||
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
|
||||
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
|
||||
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
|
||||
#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
|
||||
#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
|
||||
#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
|
||||
#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
|
||||
#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
|
||||
#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
|
||||
#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
|
||||
#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
|
||||
#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F3)
|
||||
#define COMP_START __HAL_COMP_ENABLE
|
||||
#define COMP_STOP __HAL_COMP_DISABLE
|
||||
#define COMP_LOCK __HAL_COMP_LOCK
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
|
||||
defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
#endif
|
||||
#if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP6_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
#endif
|
||||
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP7_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP7_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP7_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
|
||||
#endif
|
||||
#if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
|
||||
#endif
|
||||
#else
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
|
||||
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
|
||||
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
|
||||
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
|
||||
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
|
||||
#endif
|
||||
|
||||
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4)
|
||||
/* Note: On these STM32 families, the only argument of this macro */
|
||||
/* is COMP_FLAG_LOCK. */
|
||||
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
|
||||
/* argument. */
|
||||
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4)
|
||||
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
|
||||
((WAVE) == DAC_WAVE_NOISE)|| \
|
||||
((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_WRPAREA IS_OB_WRPAREA
|
||||
#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
|
||||
#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
|
||||
#define IS_TYPEERASE IS_FLASH_TYPEERASE
|
||||
#define IS_NBSECTORS IS_FLASH_NBSECTORS
|
||||
#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
|
||||
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
|
||||
#if defined(STM32F1)
|
||||
#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
|
||||
#else
|
||||
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
|
||||
#endif /* STM32F1 */
|
||||
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
|
||||
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
|
||||
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
|
||||
#define __HAL_I2C_SPEED I2C_SPEED
|
||||
#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
|
||||
#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
|
||||
#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
|
||||
#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
|
||||
#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
|
||||
#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
|
||||
#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
|
||||
#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
|
||||
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __IRDA_DISABLE __HAL_IRDA_DISABLE
|
||||
#define __IRDA_ENABLE __HAL_IRDA_ENABLE
|
||||
|
||||
#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
|
||||
#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
|
||||
#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
|
||||
#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
|
||||
|
||||
#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
|
||||
#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
|
||||
#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
|
||||
#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
|
||||
#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
|
||||
#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
|
||||
#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
|
||||
#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
|
||||
#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
|
||||
#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
|
||||
#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
|
||||
#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
|
||||
#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
|
||||
#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
|
||||
#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
|
||||
#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
|
||||
#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
|
||||
#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
|
||||
#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
|
||||
#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
|
||||
#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
|
||||
#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
|
||||
#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
|
||||
#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
|
||||
#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
|
||||
#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
|
||||
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
|
||||
HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
|
||||
HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
|
||||
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
|
||||
#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
|
||||
#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
|
||||
#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
|
||||
|
||||
#if defined (STM32F4)
|
||||
#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
|
||||
#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
|
||||
#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
|
||||
#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
|
||||
#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
|
||||
#else
|
||||
#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
|
||||
#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
|
||||
#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
|
||||
#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
|
||||
#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
|
||||
#endif /* STM32F4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
|
||||
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
|
||||
|
||||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
|
||||
HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
|
||||
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
|
||||
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
|
||||
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
|
||||
#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
|
||||
#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
|
||||
#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
|
||||
#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
|
||||
#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
|
||||
#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
|
||||
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
|
||||
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
|
||||
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
|
||||
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
|
||||
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
|
||||
#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
|
||||
#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
|
||||
#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
|
||||
#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
|
||||
#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
|
||||
#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
|
||||
#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
|
||||
#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
|
||||
#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
|
||||
#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
|
||||
#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
|
||||
#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
|
||||
#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
|
||||
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
|
||||
#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
|
||||
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
|
||||
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
|
||||
#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
|
||||
#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
|
||||
#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
|
||||
#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
|
||||
#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
|
||||
#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
|
||||
#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
|
||||
#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
|
||||
#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
|
||||
#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
|
||||
#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
|
||||
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
|
||||
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
|
||||
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
|
||||
#if defined(STM32C0)
|
||||
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
|
||||
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
|
||||
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
|
||||
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
|
||||
#endif /* STM32C0 */
|
||||
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
|
||||
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
|
||||
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
|
||||
#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
|
||||
#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
|
||||
#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
|
||||
#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
|
||||
#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
|
||||
#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
|
||||
#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
|
||||
#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
|
||||
#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
|
||||
#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
|
||||
#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
|
||||
#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
|
||||
#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
|
||||
#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
|
||||
#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
|
||||
#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
|
||||
#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
|
||||
#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
|
||||
#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
|
||||
#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
|
||||
#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
|
||||
#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
|
||||
#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
|
||||
#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
|
||||
#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
|
||||
#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
|
||||
#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
|
||||
#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
|
||||
#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
|
||||
#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
|
||||
#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
|
||||
#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
|
||||
#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
|
||||
#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
|
||||
#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
|
||||
#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
|
||||
#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
|
||||
#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
|
||||
#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
|
||||
#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
|
||||
#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
|
||||
#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
|
||||
#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
|
||||
#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
|
||||
#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
|
||||
#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
|
||||
#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
|
||||
#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
|
||||
#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
|
||||
#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
|
||||
#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
|
||||
#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
|
||||
#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
|
||||
#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
|
||||
#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
|
||||
#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
|
||||
#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
|
||||
#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
|
||||
#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
|
||||
#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
|
||||
#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
|
||||
#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
|
||||
#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
|
||||
#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
|
||||
#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
|
||||
#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
|
||||
#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
|
||||
#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
|
||||
#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
|
||||
#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
|
||||
#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
|
||||
#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
|
||||
#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
|
||||
#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
|
||||
#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
|
||||
#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
|
||||
#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
|
||||
#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
|
||||
#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
|
||||
#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
|
||||
#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
|
||||
#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
|
||||
#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
|
||||
#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
|
||||
#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
|
||||
#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
|
||||
#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
|
||||
#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
|
||||
#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
|
||||
#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
|
||||
#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
|
||||
#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
|
||||
#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
|
||||
#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
|
||||
#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
|
||||
#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
|
||||
#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
|
||||
#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
|
||||
#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
|
||||
#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
|
||||
#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
|
||||
#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
|
||||
#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
|
||||
#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
|
||||
#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
|
||||
#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
|
||||
#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
|
||||
#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
|
||||
#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
|
||||
#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
|
||||
#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
|
||||
#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
|
||||
#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
|
||||
#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
|
||||
#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
|
||||
#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
|
||||
#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
|
||||
#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
|
||||
#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
|
||||
#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
|
||||
#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
|
||||
#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
|
||||
#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
|
||||
#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
|
||||
#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
|
||||
#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
|
||||
#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
|
||||
#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
|
||||
#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
|
||||
#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
|
||||
#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
|
||||
#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
|
||||
#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
|
||||
#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
|
||||
#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
|
||||
#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
|
||||
#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
|
||||
#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
|
||||
#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
|
||||
#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
|
||||
#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
|
||||
#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
|
||||
#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
|
||||
#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
|
||||
#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
|
||||
#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
|
||||
#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
|
||||
#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
|
||||
#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
|
||||
#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
|
||||
#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
|
||||
#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
|
||||
#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
|
||||
#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
|
||||
#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
|
||||
#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
|
||||
#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
|
||||
#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
|
||||
#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
|
||||
#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
|
||||
#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
|
||||
#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
|
||||
#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
|
||||
#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
|
||||
#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
|
||||
#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
|
||||
#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
|
||||
#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
|
||||
#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
|
||||
#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
|
||||
#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
|
||||
#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
|
||||
#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
|
||||
#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
|
||||
#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
|
||||
#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
|
||||
#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
|
||||
#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
|
||||
#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
|
||||
#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
|
||||
#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
|
||||
#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
|
||||
#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
|
||||
#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
|
||||
#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
|
||||
#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
|
||||
#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
|
||||
#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
|
||||
#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
|
||||
#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
|
||||
#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
|
||||
#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
|
||||
#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
|
||||
#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
|
||||
#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
|
||||
#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
|
||||
#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
|
||||
#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
|
||||
#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
|
||||
#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
|
||||
#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
|
||||
#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
|
||||
#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
|
||||
#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
|
||||
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
|
||||
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
|
||||
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
|
||||
|
||||
#if defined(STM32WB)
|
||||
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
|
||||
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
|
||||
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
|
||||
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
|
||||
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
|
||||
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
|
||||
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
|
||||
#define QSPI_IRQHandler QUADSPI_IRQHandler
|
||||
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
|
||||
|
||||
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
|
||||
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
|
||||
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
|
||||
#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
|
||||
#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
|
||||
#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
|
||||
#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
|
||||
#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
|
||||
#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
|
||||
#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
|
||||
#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
|
||||
#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
|
||||
#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
|
||||
#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
|
||||
#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
|
||||
#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
|
||||
#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
|
||||
#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
|
||||
#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
|
||||
#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
|
||||
#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
|
||||
#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
|
||||
#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
|
||||
#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
|
||||
#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
|
||||
#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
|
||||
#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
|
||||
#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
|
||||
#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
|
||||
#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
|
||||
#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
|
||||
#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
|
||||
#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
|
||||
#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
|
||||
#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
|
||||
#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
|
||||
#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
|
||||
#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
|
||||
#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
|
||||
#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
|
||||
#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
|
||||
#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
|
||||
#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
|
||||
#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
|
||||
#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
|
||||
#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
|
||||
#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
|
||||
#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
|
||||
#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
|
||||
#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
|
||||
#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
|
||||
#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
|
||||
#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
|
||||
#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
|
||||
#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
|
||||
#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
|
||||
#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
|
||||
#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
|
||||
#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
|
||||
#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
|
||||
#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
|
||||
#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
|
||||
#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
|
||||
#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
|
||||
#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
|
||||
#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
|
||||
#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
|
||||
#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
|
||||
#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
|
||||
#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
|
||||
#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
|
||||
#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
|
||||
#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
|
||||
#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
|
||||
#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
|
||||
#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
|
||||
#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
|
||||
#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
|
||||
#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
|
||||
#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
|
||||
#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
|
||||
#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
|
||||
#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
|
||||
#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
|
||||
#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
|
||||
#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
|
||||
#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
|
||||
#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
|
||||
#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
|
||||
#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
|
||||
#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
|
||||
#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
|
||||
#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
|
||||
#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
|
||||
#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
|
||||
#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
|
||||
#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
|
||||
#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
|
||||
#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
|
||||
#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
|
||||
#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
|
||||
#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
|
||||
#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
|
||||
#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
|
||||
#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
|
||||
#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
|
||||
#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
|
||||
#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
|
||||
#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
|
||||
#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
|
||||
#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
|
||||
#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
|
||||
#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
|
||||
#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
|
||||
#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
|
||||
#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
|
||||
#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
|
||||
#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
|
||||
#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
|
||||
#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
|
||||
#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
|
||||
#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
|
||||
#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
|
||||
#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
|
||||
#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
|
||||
#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
|
||||
#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
|
||||
#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
|
||||
#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
|
||||
#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
|
||||
#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
|
||||
#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
|
||||
#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
|
||||
#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
|
||||
#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
|
||||
#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
|
||||
#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
|
||||
#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
|
||||
#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
|
||||
#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
|
||||
#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
|
||||
#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
|
||||
#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
|
||||
#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
|
||||
#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
|
||||
#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
|
||||
#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
|
||||
#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
|
||||
#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
|
||||
#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
|
||||
#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
|
||||
#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
|
||||
#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
|
||||
#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
|
||||
#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
|
||||
#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
|
||||
#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
|
||||
#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
|
||||
#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
|
||||
#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
|
||||
#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
|
||||
#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
|
||||
#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
|
||||
#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
|
||||
#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
|
||||
#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
|
||||
#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
|
||||
#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
|
||||
#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
|
||||
#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
|
||||
#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
|
||||
#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
|
||||
#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
|
||||
#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
|
||||
#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
|
||||
#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
|
||||
#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
|
||||
#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
|
||||
#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
|
||||
#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
|
||||
#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
|
||||
#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
|
||||
#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
|
||||
#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
|
||||
#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
|
||||
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
|
||||
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
|
||||
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
|
||||
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
|
||||
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
|
||||
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
|
||||
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
|
||||
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
|
||||
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
|
||||
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
|
||||
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
|
||||
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
|
||||
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
|
||||
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
|
||||
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
|
||||
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
|
||||
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
|
||||
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
|
||||
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
|
||||
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
|
||||
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
|
||||
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
|
||||
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
|
||||
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
|
||||
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
|
||||
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
|
||||
#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
|
||||
#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
|
||||
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
|
||||
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
|
||||
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
|
||||
#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
|
||||
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
|
||||
|
||||
#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
|
||||
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
|
||||
|
||||
|
||||
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
|
||||
#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
|
||||
#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
|
||||
#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
|
||||
#endif
|
||||
|
||||
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
|
||||
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
|
||||
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
|
||||
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
|
||||
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
|
||||
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
|
||||
|
||||
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
|
||||
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
|
||||
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
|
||||
#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
|
||||
#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
|
||||
#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
|
||||
#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
|
||||
#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
|
||||
#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
|
||||
#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
|
||||
#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
|
||||
#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
|
||||
#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
|
||||
#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
|
||||
#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
|
||||
#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
|
||||
#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
|
||||
#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
|
||||
#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
|
||||
#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
|
||||
|
||||
#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
|
||||
#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
|
||||
#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
|
||||
#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
|
||||
#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
|
||||
#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
|
||||
#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
|
||||
#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
|
||||
#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
|
||||
#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
|
||||
#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
|
||||
#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
|
||||
#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
|
||||
#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
|
||||
#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
|
||||
#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
|
||||
#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
|
||||
#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
|
||||
#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
|
||||
#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
|
||||
#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
|
||||
#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
|
||||
#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
|
||||
#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
|
||||
#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
|
||||
#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
|
||||
#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
|
||||
#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
|
||||
#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
|
||||
#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
|
||||
#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
|
||||
#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
|
||||
#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
|
||||
#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
|
||||
#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
|
||||
#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
|
||||
#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
|
||||
#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
|
||||
#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
|
||||
#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
|
||||
#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
|
||||
#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
|
||||
#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
|
||||
#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
|
||||
#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
|
||||
#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
|
||||
#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
|
||||
#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
|
||||
#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
|
||||
#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
|
||||
#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
|
||||
#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
|
||||
#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
|
||||
#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
|
||||
#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
|
||||
#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
|
||||
#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
|
||||
#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
|
||||
#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
|
||||
#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
|
||||
#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
|
||||
#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
|
||||
#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
|
||||
#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
|
||||
#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
|
||||
#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
|
||||
#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
|
||||
#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
|
||||
#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
|
||||
#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
|
||||
#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
|
||||
#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
|
||||
#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
|
||||
#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
|
||||
#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
|
||||
#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
|
||||
#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
|
||||
#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
|
||||
#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
|
||||
#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
|
||||
#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
|
||||
#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
|
||||
#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
|
||||
#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
|
||||
#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
|
||||
#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
|
||||
#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
|
||||
#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
|
||||
#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
|
||||
#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
|
||||
#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
|
||||
#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
|
||||
#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
|
||||
#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
|
||||
#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
|
||||
#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
|
||||
#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
|
||||
#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
|
||||
#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
|
||||
#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
|
||||
#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
|
||||
#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
|
||||
#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
|
||||
#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
|
||||
#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
|
||||
#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
|
||||
#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
|
||||
#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
|
||||
#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
|
||||
#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
|
||||
#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
|
||||
#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
|
||||
#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
|
||||
#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
|
||||
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
|
||||
#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
|
||||
#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
|
||||
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
|
||||
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
|
||||
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
|
||||
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
|
||||
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
|
||||
#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
|
||||
#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
|
||||
#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
|
||||
#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
|
||||
#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
|
||||
#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
|
||||
#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
|
||||
#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
|
||||
#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
|
||||
#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
|
||||
#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
|
||||
#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
|
||||
#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
|
||||
#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
|
||||
#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
|
||||
#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
|
||||
#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
|
||||
#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
|
||||
#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
|
||||
#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
|
||||
|
||||
/* alias define maintained for legacy */
|
||||
#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
|
||||
#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
|
||||
|
||||
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
|
||||
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
|
||||
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
|
||||
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
|
||||
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
|
||||
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
|
||||
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
|
||||
#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
|
||||
#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
|
||||
#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
|
||||
#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
|
||||
#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
|
||||
#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
|
||||
#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
|
||||
#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
|
||||
#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
|
||||
#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
|
||||
#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
|
||||
#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
|
||||
#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
|
||||
|
||||
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
|
||||
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
|
||||
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
|
||||
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
|
||||
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
|
||||
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
|
||||
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
|
||||
#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
|
||||
#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
|
||||
#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
|
||||
#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
|
||||
#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
|
||||
#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
|
||||
#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
|
||||
#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
|
||||
#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
|
||||
#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
|
||||
#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
|
||||
#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
|
||||
#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
|
||||
|
||||
#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
|
||||
#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
|
||||
#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
|
||||
#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
|
||||
#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
|
||||
#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
|
||||
#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
|
||||
#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
|
||||
#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
|
||||
#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
|
||||
#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
|
||||
#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
|
||||
#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
|
||||
#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
|
||||
#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
|
||||
#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
|
||||
#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
|
||||
#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
|
||||
#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
|
||||
#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
|
||||
#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
|
||||
#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
|
||||
#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
|
||||
#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
|
||||
#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
|
||||
#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
|
||||
#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
|
||||
#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
|
||||
#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
|
||||
#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
|
||||
#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
|
||||
#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
|
||||
#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
|
||||
#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
|
||||
#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
|
||||
#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
|
||||
#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
|
||||
#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
|
||||
#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
|
||||
#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
|
||||
#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
|
||||
#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
|
||||
#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
|
||||
#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
|
||||
#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
|
||||
#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
|
||||
#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
|
||||
#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
|
||||
#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
|
||||
#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
|
||||
#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
|
||||
#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
|
||||
#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
|
||||
#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
|
||||
#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
|
||||
#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
|
||||
#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
|
||||
#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
|
||||
#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
|
||||
#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
|
||||
#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
|
||||
#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
|
||||
#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
|
||||
#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
|
||||
#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
|
||||
#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
|
||||
#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
|
||||
#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
|
||||
#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
|
||||
#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
|
||||
#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
|
||||
#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
|
||||
#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
|
||||
#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
|
||||
#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
|
||||
#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
|
||||
#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
|
||||
#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
|
||||
#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
|
||||
#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
|
||||
#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
|
||||
#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
|
||||
#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
|
||||
#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
|
||||
#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
|
||||
#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
|
||||
#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
|
||||
#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
|
||||
#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
|
||||
#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
|
||||
#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
|
||||
#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
|
||||
#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
|
||||
#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
|
||||
#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
|
||||
#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
|
||||
#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
|
||||
#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
|
||||
#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
|
||||
#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
|
||||
#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
|
||||
#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
|
||||
#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
|
||||
#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
|
||||
#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
|
||||
#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
|
||||
#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
|
||||
#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
|
||||
#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
|
||||
#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
|
||||
#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
|
||||
#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
|
||||
#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
|
||||
#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
|
||||
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
|
||||
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
|
||||
|
||||
#if defined(STM32L1)
|
||||
#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
|
||||
#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
|
||||
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
|
||||
#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
|
||||
#endif /* STM32L1 */
|
||||
|
||||
#if defined(STM32F4)
|
||||
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
|
||||
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
|
||||
#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
|
||||
#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
|
||||
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
|
||||
#define Sdmmc1ClockSelection SdioClockSelection
|
||||
#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
|
||||
#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
|
||||
#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
|
||||
#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
|
||||
#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7) || defined(STM32L4)
|
||||
#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
|
||||
#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
|
||||
#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
|
||||
#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
|
||||
#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
|
||||
#define SdioClockSelection Sdmmc1ClockSelection
|
||||
#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
|
||||
#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
|
||||
#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
|
||||
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
|
||||
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
|
||||
#endif
|
||||
|
||||
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
|
||||
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
|
||||
|
||||
#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
|
||||
|
||||
#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
|
||||
#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
|
||||
#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
|
||||
#define IS_RCC_HCLK_DIV IS_RCC_PCLK
|
||||
#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
|
||||
|
||||
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
|
||||
|
||||
#define RCC_IT_CSSLSE RCC_IT_LSECSS
|
||||
#define RCC_IT_CSSHSE RCC_IT_CSS
|
||||
|
||||
#define RCC_PLLMUL_3 RCC_PLL_MUL3
|
||||
#define RCC_PLLMUL_4 RCC_PLL_MUL4
|
||||
#define RCC_PLLMUL_6 RCC_PLL_MUL6
|
||||
#define RCC_PLLMUL_8 RCC_PLL_MUL8
|
||||
#define RCC_PLLMUL_12 RCC_PLL_MUL12
|
||||
#define RCC_PLLMUL_16 RCC_PLL_MUL16
|
||||
#define RCC_PLLMUL_24 RCC_PLL_MUL24
|
||||
#define RCC_PLLMUL_32 RCC_PLL_MUL32
|
||||
#define RCC_PLLMUL_48 RCC_PLL_MUL48
|
||||
|
||||
#define RCC_PLLDIV_2 RCC_PLL_DIV2
|
||||
#define RCC_PLLDIV_3 RCC_PLL_DIV3
|
||||
#define RCC_PLLDIV_4 RCC_PLL_DIV4
|
||||
|
||||
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
|
||||
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
|
||||
#define RCC_MCO_NODIV RCC_MCODIV_1
|
||||
#define RCC_MCO_DIV1 RCC_MCODIV_1
|
||||
#define RCC_MCO_DIV2 RCC_MCODIV_2
|
||||
#define RCC_MCO_DIV4 RCC_MCODIV_4
|
||||
#define RCC_MCO_DIV8 RCC_MCODIV_8
|
||||
#define RCC_MCO_DIV16 RCC_MCODIV_16
|
||||
#define RCC_MCO_DIV32 RCC_MCODIV_32
|
||||
#define RCC_MCO_DIV64 RCC_MCODIV_64
|
||||
#define RCC_MCO_DIV128 RCC_MCODIV_128
|
||||
#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
|
||||
#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
|
||||
#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
|
||||
#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
|
||||
#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
|
||||
#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
|
||||
#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
|
||||
#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32U0)
|
||||
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
|
||||
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
#endif
|
||||
|
||||
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
|
||||
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
|
||||
#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
|
||||
#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
|
||||
#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
|
||||
#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
|
||||
#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
|
||||
#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
|
||||
|
||||
#define HSION_BitNumber RCC_HSION_BIT_NUMBER
|
||||
#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
|
||||
#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
|
||||
#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
|
||||
#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
|
||||
#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
|
||||
#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
|
||||
#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
|
||||
#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
|
||||
#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
|
||||
#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
|
||||
#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
|
||||
#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
|
||||
#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
|
||||
#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
|
||||
#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
|
||||
#define LSION_BitNumber RCC_LSION_BIT_NUMBER
|
||||
#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
|
||||
#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
|
||||
#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
|
||||
#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
|
||||
#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
|
||||
#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
|
||||
#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
|
||||
#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
|
||||
#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
|
||||
#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
|
||||
#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
|
||||
#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
|
||||
#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
|
||||
#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
|
||||
#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
|
||||
|
||||
#define CR_HSION_BB RCC_CR_HSION_BB
|
||||
#define CR_CSSON_BB RCC_CR_CSSON_BB
|
||||
#define CR_PLLON_BB RCC_CR_PLLON_BB
|
||||
#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
|
||||
#define CR_MSION_BB RCC_CR_MSION_BB
|
||||
#define CSR_LSION_BB RCC_CSR_LSION_BB
|
||||
#define CSR_LSEON_BB RCC_CSR_LSEON_BB
|
||||
#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
|
||||
#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
|
||||
#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
|
||||
#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
|
||||
#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
|
||||
#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
|
||||
#define CR_HSEON_BB RCC_CR_HSEON_BB
|
||||
#define CSR_RMVF_BB RCC_CSR_RMVF_BB
|
||||
#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
|
||||
#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
|
||||
|
||||
#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
|
||||
#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
|
||||
#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
|
||||
#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
|
||||
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
|
||||
|
||||
#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
|
||||
|
||||
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
|
||||
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
|
||||
|
||||
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
|
||||
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
|
||||
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
|
||||
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
|
||||
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
|
||||
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
|
||||
|
||||
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
|
||||
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
|
||||
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
|
||||
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
|
||||
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
|
||||
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
|
||||
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
|
||||
#define DfsdmClockSelection Dfsdm1ClockSelection
|
||||
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
|
||||
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
|
||||
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
|
||||
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
|
||||
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
|
||||
#if !defined(STM32U0)
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
|
||||
#endif
|
||||
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
|
||||
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
|
||||
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
|
||||
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
|
||||
#if defined(STM32U5)
|
||||
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
|
||||
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
|
||||
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
|
||||
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
|
||||
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
|
||||
#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
|
||||
#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
|
||||
#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
|
||||
#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
|
||||
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
|
||||
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
|
||||
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
|
||||
#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
|
||||
#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
|
||||
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
|
||||
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
|
||||
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
|
||||
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
|
||||
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
|
||||
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
|
||||
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
|
||||
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
|
||||
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
|
||||
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
|
||||
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
|
||||
#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
|
||||
#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
|
||||
#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
|
||||
#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
|
||||
#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
|
||||
#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
|
||||
#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
|
||||
#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
|
||||
#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
|
||||
#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
|
||||
|
||||
#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
|
||||
#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
|
||||
#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
|
||||
#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
|
||||
#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
|
||||
#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
|
||||
#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
|
||||
#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
|
||||
#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
|
||||
#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
|
||||
|
||||
#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
|
||||
#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
|
||||
#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
|
||||
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
|
||||
#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
|
||||
#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
|
||||
#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
|
||||
#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
|
||||
#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
|
||||
#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
|
||||
|
||||
#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
|
||||
#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
|
||||
#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
|
||||
#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
|
||||
#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
|
||||
#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
|
||||
#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
|
||||
#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
|
||||
|
||||
#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
|
||||
#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
|
||||
#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
|
||||
#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
|
||||
#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
|
||||
#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
|
||||
#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
|
||||
#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
|
||||
|
||||
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
|
||||
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
|
||||
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
|
||||
|
||||
#if defined (STM32F1)
|
||||
#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
|
||||
|
||||
#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
|
||||
|
||||
#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
|
||||
|
||||
#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
|
||||
|
||||
#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
|
||||
#else
|
||||
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
|
||||
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
|
||||
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
|
||||
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
|
||||
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
|
||||
defined (STM32H7) || \
|
||||
defined (STM32L0) || defined (STM32L1) || \
|
||||
defined (STM32WB)
|
||||
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
|
||||
#endif
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
|
||||
#define IS_TAMPER IS_RTC_TAMPER
|
||||
#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
|
||||
#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
|
||||
#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
|
||||
#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
|
||||
#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
|
||||
#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
|
||||
#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
|
||||
#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
|
||||
#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
|
||||
#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
|
||||
#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
|
||||
|
||||
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
|
||||
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
|
||||
|
||||
#if defined (STM32H5)
|
||||
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
|
||||
#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
|
||||
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
|
||||
|
||||
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
|
||||
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
|
||||
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
|
||||
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
|
||||
|
||||
#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
|
||||
#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
|
||||
#endif
|
||||
|
||||
#if defined(STM32F4) || defined(STM32F2)
|
||||
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
|
||||
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
|
||||
#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
|
||||
#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
|
||||
#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
|
||||
#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
|
||||
#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
|
||||
#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
|
||||
#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
|
||||
#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
|
||||
#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
|
||||
#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
|
||||
#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
|
||||
#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
|
||||
#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
|
||||
#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
|
||||
#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
|
||||
#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
|
||||
#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
|
||||
#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
|
||||
/* alias CMSIS */
|
||||
#define SDMMC1_IRQn SDIO_IRQn
|
||||
#define SDMMC1_IRQHandler SDIO_IRQHandler
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7) || defined(STM32L4)
|
||||
#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
|
||||
#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
|
||||
#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
|
||||
#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
|
||||
#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
|
||||
#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
|
||||
#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
|
||||
#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
|
||||
#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
|
||||
#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
|
||||
#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
|
||||
#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
|
||||
#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
|
||||
#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
|
||||
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
|
||||
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
|
||||
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
|
||||
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
|
||||
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
|
||||
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
|
||||
/* alias CMSIS for compatibilities */
|
||||
#define SDIO_IRQn SDMMC1_IRQn
|
||||
#define SDIO_IRQHandler SDMMC1_IRQHandler
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
|
||||
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
|
||||
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
|
||||
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
|
||||
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7) || defined(STM32L5)
|
||||
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
|
||||
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
|
||||
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
|
||||
#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
|
||||
#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
|
||||
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
|
||||
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
|
||||
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
|
||||
#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
|
||||
#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
|
||||
#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
|
||||
#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
|
||||
#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
|
||||
#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
|
||||
|
||||
#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
|
||||
#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
|
||||
|
||||
#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
|
||||
#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
|
||||
#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
|
||||
#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
|
||||
#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
|
||||
#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
|
||||
#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
|
||||
#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
|
||||
#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
|
||||
#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
|
||||
#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
|
||||
#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
|
||||
#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
|
||||
|
||||
#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
|
||||
|
||||
#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
|
||||
#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
|
||||
#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
|
||||
#define __USART_ENABLE __HAL_USART_ENABLE
|
||||
#define __USART_DISABLE __HAL_USART_DISABLE
|
||||
|
||||
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
|
||||
|
||||
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
|
||||
#define USART_OVERSAMPLING_16 0x00000000U
|
||||
#define USART_OVERSAMPLING_8 USART_CR1_OVER8
|
||||
|
||||
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
|
||||
((__SAMPLING__) == USART_OVERSAMPLING_8))
|
||||
#endif /* STM32F0 || STM32F3 || STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
|
||||
|
||||
#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
|
||||
#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
|
||||
#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
|
||||
#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
|
||||
#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
|
||||
#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
|
||||
#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
|
||||
#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
|
||||
#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
|
||||
#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
|
||||
#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
|
||||
|
||||
#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
|
||||
#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
|
||||
#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
|
||||
#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
|
||||
#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
|
||||
#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
|
||||
|
||||
#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
|
||||
#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
|
||||
#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
|
||||
#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
|
||||
#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
|
||||
#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
|
||||
|
||||
#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
|
||||
#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
|
||||
|
||||
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
|
||||
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
|
||||
#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
|
||||
|
||||
#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
|
||||
#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
|
||||
|
||||
#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
|
||||
|
||||
#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
|
||||
#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
|
||||
#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
|
||||
#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
|
||||
#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
|
||||
#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
|
||||
#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
|
||||
#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
|
||||
#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
|
||||
#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
|
||||
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
|
||||
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
|
||||
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
|
||||
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
|
||||
#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
|
||||
#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
|
||||
#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
|
||||
#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
|
||||
#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
|
||||
#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
|
||||
|
||||
#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
|
||||
#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
|
||||
#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_LTDC_LAYER LTDC_LAYER
|
||||
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
|
||||
#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
|
||||
#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
|
||||
#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
|
||||
#define SAI_STREOMODE SAI_STEREOMODE
|
||||
#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
|
||||
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
|
||||
#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
|
||||
#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
|
||||
#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
|
||||
#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
|
||||
#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
|
||||
#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
|
||||
#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32H7)
|
||||
#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
|
||||
#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
|
||||
#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
|
||||
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
|
||||
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
|
||||
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
|
||||
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
|
||||
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
|
||||
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
|
||||
#endif /* STM32L4 || STM32F4 || STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F7)
|
||||
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
|
||||
#endif /* STM32F7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32_HAL_LEGACY */
|
||||
|
||||
|
||||
55
Drivers/STM32G4xx_HAL_Driver/Inc/stm32_assert_template.h
Normal file
55
Drivers/STM32G4xx_HAL_Driver/Inc/stm32_assert_template.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32_assert.h
|
||||
* @author MCD Application Team
|
||||
* @brief STM32 assert template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32_assert.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32_ASSERT_H
|
||||
#define STM32_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32_ASSERT_H */
|
||||
|
||||
|
||||
630
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h
Normal file
630
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h
Normal file
@@ -0,0 +1,630 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_H
|
||||
#define STM32G4xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{
|
||||
*/
|
||||
#define HAL_TICK_FREQ_10HZ 100U
|
||||
#define HAL_TICK_FREQ_100HZ 10U
|
||||
#define HAL_TICK_FREQ_1KHZ 1U
|
||||
#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_BootMode Boot Mode
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_BOOT_MAINFLASH 0x00000000U
|
||||
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0
|
||||
|
||||
#if defined (FMC_BANK1)
|
||||
#define SYSCFG_BOOT_FMC SYSCFG_MEMMEMRMP_MODE_1
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)
|
||||
|
||||
#if defined (QUADSPI)
|
||||
#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
|
||||
#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
|
||||
#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
|
||||
#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
|
||||
#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
|
||||
#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
|
||||
#define SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(VREFBUF)
|
||||
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* VREFBUF */
|
||||
|
||||
/** @defgroup SYSCFG_flags_definition Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */
|
||||
#define SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY /*!< CCMSRAM busy by erase operation */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Fast-mode Plus driving capability on a specific GPIO
|
||||
*/
|
||||
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
|
||||
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
|
||||
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
|
||||
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
|
||||
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
|
||||
#endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
|
||||
#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
|
||||
#endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
|
||||
#endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
|
||||
#endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
|
||||
#endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
|
||||
#endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM20() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM20() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
|
||||
#endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_HRTIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_HRTIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
|
||||
#endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Main Flash memory mapped at 0x00000000.
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
|
||||
|
||||
/** @brief System Flash memory mapped at 0x00000000.
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
|
||||
|
||||
/** @brief Embedded SRAM mapped at 0x00000000.
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
|
||||
|
||||
#if defined (FMC_BANK1)
|
||||
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined (QUADSPI)
|
||||
/** @brief QUADSPI mapped at 0x00000000.
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/**
|
||||
* @brief Return the boot mode as configured by user.
|
||||
* @retval The boot mode as configured by user. The returned value can be one
|
||||
* of the following values:
|
||||
* @arg @ref SYSCFG_BOOT_MAINFLASH
|
||||
* @arg @ref SYSCFG_BOOT_SYSTEMFLASH
|
||||
* @arg @ref SYSCFG_BOOT_FMC (*)
|
||||
* @arg @ref SYSCFG_BOOT_QUADSPI (*)
|
||||
* @arg @ref SYSCFG_BOOT_SRAM
|
||||
* @note (*) availability depends on devices
|
||||
*/
|
||||
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
|
||||
|
||||
/** @brief CCMSRAM page write protection enable macro
|
||||
* @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP
|
||||
* @note write protection can only be disabled by a system reset
|
||||
* @retval None
|
||||
*/
|
||||
/* Legacy define */
|
||||
#define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
|
||||
#define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__) do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\
|
||||
SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\
|
||||
}while(0)
|
||||
|
||||
/** @brief CCMSRAM page write protection unlock prior to erase
|
||||
* @note Writing a wrong key reactivates the write protection
|
||||
*/
|
||||
#define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\
|
||||
SYSCFG->SKR = 0x53;\
|
||||
}while(0)
|
||||
|
||||
/** @brief CCMSRAM erase
|
||||
* @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase
|
||||
*/
|
||||
#define __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
|
||||
|
||||
/** @brief Floating Point Unit interrupt enable/disable macros
|
||||
* @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
|
||||
*/
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
|
||||
SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
|
||||
}while(0)
|
||||
|
||||
/** @brief SYSCFG Break ECC lock.
|
||||
* Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
|
||||
|
||||
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
|
||||
* Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
|
||||
|
||||
/** @brief SYSCFG Break PVD lock.
|
||||
* Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
|
||||
|
||||
/** @brief SYSCFG Break SRAM parity lock.
|
||||
* Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
|
||||
|
||||
/** @brief Check SYSCFG flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag
|
||||
* @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
|
||||
& (__FLAG__))!= 0U) ? 1U : 0U)
|
||||
|
||||
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
|
||||
*/
|
||||
#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
|
||||
|
||||
/** @brief Fast-mode Plus driving capability enable/disable macros
|
||||
* @param __FASTMODEPLUS__: This parameter can be a value of :
|
||||
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
|
||||
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
|
||||
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
|
||||
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
|
||||
*/
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
|
||||
|
||||
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
|
||||
((__CONFIG__) == SYSCFG_BREAK_PVD) || \
|
||||
((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \
|
||||
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
|
||||
|
||||
#if (CCMSRAM_SIZE == 0x00008000UL) /* STM32G4 devices with CCMSRAM_SIZE = 32 Kbytes */
|
||||
#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U)
|
||||
#elif (CCMSRAM_SIZE == 0x00005000UL) /* STM32G4 devices with CCMSRAM_SIZE = 20 Kbytes */
|
||||
#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FFFFFU))
|
||||
#elif (CCMSRAM_SIZE == 0x00004000UL) /* STM32G4 devices with CCMSRAM_SIZE = 16 Kbytes */
|
||||
#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x0000FFFFU))
|
||||
#elif (CCMSRAM_SIZE == 0x00002800UL) /* STM32G4 devices with CCMSRAM_SIZE = 10 Kbytes */
|
||||
#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
|
||||
#endif /* CCMSRAM_SIZE */
|
||||
|
||||
#if defined(VREFBUF)
|
||||
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
|
||||
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
|
||||
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2))
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
|
||||
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
|
||||
#endif /* VREFBUF */
|
||||
|
||||
#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
|
||||
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
|
||||
#elif defined(SYSCFG_FASTMODEPLUS_PB8)
|
||||
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
|
||||
#elif defined(SYSCFG_FASTMODEPLUS_PB9)
|
||||
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
|
||||
#else
|
||||
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
|
||||
#endif /* SYSCFG_FASTMODEPLUS_PB */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and Configuration functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
|
||||
uint32_t HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
uint32_t HAL_GetUIDw0(void);
|
||||
uint32_t HAL_GetUIDw1(void);
|
||||
uint32_t HAL_GetUIDw2(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DBGMCU Peripheral Control functions *****************************************/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables ---------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern uint32_t uwTickFreq;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SYSCFG Control functions ****************************************************/
|
||||
void HAL_SYSCFG_CCMSRAMErase(void);
|
||||
void HAL_SYSCFG_EnableMemorySwappingBank(void);
|
||||
void HAL_SYSCFG_DisableMemorySwappingBank(void);
|
||||
|
||||
#if defined(VREFBUF)
|
||||
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
|
||||
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
|
||||
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
|
||||
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
|
||||
void HAL_SYSCFG_DisableVREFBUF(void);
|
||||
#endif /* VREFBUF */
|
||||
|
||||
void HAL_SYSCFG_EnableIOSwitchBooster(void);
|
||||
void HAL_SYSCFG_DisableIOSwitchBooster(void);
|
||||
void HAL_SYSCFG_EnableIOSwitchVDD(void);
|
||||
void HAL_SYSCFG_DisableIOSwitchVDD(void);
|
||||
void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_H */
|
||||
|
||||
2318
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
Normal file
2318
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
Normal file
@@ -0,0 +1,2318 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ADC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_ADC_H
|
||||
#define STM32G4xx_HAL_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/* Include low level driver */
|
||||
#include "stm32g4xx_ll_adc.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Types ADC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC group regular oversampling structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Ratio; /*!< Configures the oversampling ratio.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
|
||||
|
||||
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
|
||||
|
||||
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
|
||||
|
||||
uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
|
||||
The oversampling is either temporary stopped or reset upon an injected
|
||||
sequence interruption.
|
||||
If oversampling is enabled on both regular and injected groups, this
|
||||
parameter is discarded and forced to setting
|
||||
"ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed
|
||||
during injection sequence).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
|
||||
|
||||
} ADC_OversamplingTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC instance and ADC group regular.
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
|
||||
* GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait.
|
||||
* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
|
||||
* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling,
|
||||
* SamplingMode.
|
||||
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled
|
||||
* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled
|
||||
* without conversion on going on group regular.
|
||||
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going
|
||||
* on groups regular and injected.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another
|
||||
* parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
|
||||
clock derived from system clock or PLL (Refer to reference manual for list of
|
||||
clocks available)) and clock prescaler.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
|
||||
Note: The ADC clock configuration is common to all ADC instances.
|
||||
Note: In case of usage of channels on injected group, ADC frequency should be
|
||||
lower than AHB clock frequency /4 for resolution 12 or 10 bits,
|
||||
AHB clock frequency /3 for resolution 8 bits,
|
||||
AHB clock frequency /2 for resolution 6 bits.
|
||||
Note: In case of synchronous clock mode based on HCLK/1, the configuration must
|
||||
be enabled only if the system clock has a 50% duty clock cycle (APB
|
||||
prescaler configured inside RCC must be bypassed and PCLK clock must have
|
||||
50% duty cycle). Refer to reference manual for details.
|
||||
Note: In case of usage of asynchronous clock, the selected clock must be
|
||||
preliminarily enabled at RCC top level.
|
||||
Note: This parameter can be modified only if all ADC instances are disabled. */
|
||||
|
||||
uint32_t Resolution; /*!< Configure the ADC resolution.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
|
||||
|
||||
uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
|
||||
Refer to reference manual for alignments formats versus resolutions.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
|
||||
|
||||
uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion
|
||||
data, based on following formula:
|
||||
DATA = DATA(raw) * (gain compensation coef) / 4096
|
||||
"2.12" bit format, unsigned: 2 bits exponents / 12 bits mantissa
|
||||
Gain step is 1/4096 = 0.000244
|
||||
Gain range is 0.0000 to 3.999756
|
||||
This parameter value can be
|
||||
0 Gain compensation will be disabled and coefficient set to 0
|
||||
1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified
|
||||
value
|
||||
Note: Gain compensation when enabled is applied to all channels. */
|
||||
|
||||
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
|
||||
This parameter can be associated to parameter 'DiscontinuousConvMode' to have
|
||||
main sequence subdivided in successive parts.
|
||||
If disabled: Conversion is performed in single mode (one channel converted, the
|
||||
one defined in rank 1). Parameters 'NbrOfConversion' and
|
||||
'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
|
||||
If enabled: Conversions are performed in sequence mode (multiple ranks defined
|
||||
by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each
|
||||
channel in sequencer). Scan direction is upward: from rank 1 to
|
||||
rank 'n'.
|
||||
This parameter can be a value of @ref ADC_Scan_mode */
|
||||
|
||||
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
|
||||
interruption: end of unitary conversion or end of sequence conversions.
|
||||
This parameter can be a value of @ref ADC_EOCSelection. */
|
||||
|
||||
FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
|
||||
previous conversion (for ADC group regular) or previous sequence (for ADC group
|
||||
injected) has been retrieved by user software, using function HAL_ADC_GetValue()
|
||||
or HAL_ADCEx_InjectedGetValue().
|
||||
This feature automatically adapts the frequency of ADC conversions triggers to
|
||||
the speed of the system that reads the data. Moreover, this avoids risk of
|
||||
overrun for low frequency applications.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
|
||||
HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
|
||||
flag (by CPU to free the IRQ pending event or by DMA).
|
||||
Auto wait will work but fort a very short time, discarding its intended
|
||||
benefit (except specific case of high load of CPU or DMA transfers which
|
||||
can justify usage of auto wait).
|
||||
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
|
||||
when ADC conversion data is needed:
|
||||
use HAL_ADC_PollForConversion() to ensure that conversion is completed and
|
||||
HAL_ADC_GetValue() to retrieve conversion result and trig another
|
||||
conversion start. (in case of usage of ADC group injected, use the
|
||||
equivalent functions HAL_ADCExInjected_Start(),
|
||||
HAL_ADCEx_InjectedGetValue(), ...). */
|
||||
|
||||
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
|
||||
or continuous mode for ADC group regular, after the first ADC conversion
|
||||
start trigger occurred (software start or external trigger). This parameter
|
||||
can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group
|
||||
sequencer.
|
||||
This parameter is dependent on ScanConvMode:
|
||||
- sequencer configured to fully configurable:
|
||||
Number of ranks in the scan sequence is configurable using this parameter.
|
||||
Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to
|
||||
parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
|
||||
Afterwards, when all needed sequencer ranks are set, parameter
|
||||
'NbrOfConversion' can be updated without modifying configuration of
|
||||
sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
|
||||
- sequencer configured to not fully configurable:
|
||||
Number of ranks in the scan sequence is defined by number of channels set in
|
||||
the sequence. This parameter is discarded.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 8.
|
||||
Note: This parameter must be modified when no conversion is on going on regular
|
||||
group (ADC disabled, or ADC enabled without continuous mode or external
|
||||
trigger that could launch a conversion). */
|
||||
|
||||
FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
|
||||
in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
|
||||
successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter
|
||||
'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled.
|
||||
If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: On this STM32 series, ADC group regular number of discontinuous
|
||||
ranks increment is fixed to one-by-one. */
|
||||
|
||||
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence
|
||||
of ADC group regular (parameter NbrOfConversion) will be subdivided.
|
||||
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
|
||||
|
||||
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion
|
||||
start.
|
||||
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
|
||||
is used instead.
|
||||
This parameter can be a value of @ref ADC_regular_external_trigger_source.
|
||||
Caution: external trigger source is common to all ADC instances. */
|
||||
|
||||
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start
|
||||
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
|
||||
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
|
||||
|
||||
uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion.
|
||||
This parameter can be a value of @ref ADC_regular_sampling_mode */
|
||||
|
||||
FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
|
||||
transfer stops when number of conversions is reached) or in continuous
|
||||
mode (DMA transfer unlimited, whatever number of conversions).
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: In continuous mode, DMA must be configured in circular mode.
|
||||
Otherwise an overrun will be triggered when DMA buffer maximum
|
||||
pointer is reached. */
|
||||
|
||||
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
|
||||
This parameter applies to ADC group regular only.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
|
||||
Note: In case of overrun set to data preserved and usage with programming model
|
||||
with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
|
||||
conversion flags, this induces the release of the preserved data. If
|
||||
needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
|
||||
placed in user program code (called before end of conversion flags clear)
|
||||
Note: Error reporting with respect to the conversion mode:
|
||||
- Usage with ADC conversion by polling for event or interruption: Error is
|
||||
reported only if overrun is set to data preserved. If overrun is set to
|
||||
data overwritten, user can willingly not read all the converted data,
|
||||
this is not considered as an erroneous case.
|
||||
- Usage with ADC conversion by DMA: Error is reported whatever overrun
|
||||
setting (DMA is expected to process all data from data register). */
|
||||
|
||||
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter can be modified only if there is no conversion is
|
||||
ongoing on ADC groups regular and injected */
|
||||
|
||||
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
|
||||
Caution: this setting overwrites the previous oversampling configuration
|
||||
if oversampling is already enabled. */
|
||||
|
||||
} ADC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC channel for regular group
|
||||
* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
|
||||
* - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion
|
||||
* on going on regular group.
|
||||
* - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on
|
||||
* regular and injected groups.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another
|
||||
* parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
|
||||
Note: Depending on devices and ADC instances, some channels may not be available
|
||||
on device package pins. Refer to device datasheet for channels
|
||||
availability. */
|
||||
|
||||
uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
|
||||
Note: to disable a channel or change order of conversion sequencer, rank
|
||||
containing a previous channel setting can be overwritten by the new channel
|
||||
setting (or parameter number of conversions adjusted) */
|
||||
|
||||
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time
|
||||
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
|
||||
8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
|
||||
Caution: This parameter applies to a channel that can be used into regular
|
||||
and/or injected group. It overwrites the last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...),
|
||||
sampling time constraints must be respected (sampling time can be adjusted
|
||||
in function of ADC clock frequency and sampling time setting).
|
||||
Refer to device datasheet for timings values. */
|
||||
|
||||
uint32_t SingleDiff; /*!< Select single-ended or differential input.
|
||||
In differential mode: Differential measurement is carried out between the
|
||||
selected channel 'i' (positive input) and channel 'i+1' (negative input).
|
||||
Only channel 'i' has to be configured, channel 'i+1' is configured automatically
|
||||
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
|
||||
Caution: This parameter applies to a channel that can be used in a regular
|
||||
and/or injected group.
|
||||
It overwrites the last setting.
|
||||
Note: Refer to Reference Manual to ensure the selected channel is available in
|
||||
differential mode.
|
||||
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is
|
||||
not usable separately.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start
|
||||
conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error
|
||||
reporting (as it can be the expected behavior in case of another parameter
|
||||
update on the fly) */
|
||||
|
||||
uint32_t OffsetNumber; /*!< Select the offset number
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
|
||||
Caution: Only one offset is allowed per channel. This parameter overwrites the
|
||||
last setting. */
|
||||
|
||||
uint32_t Offset; /*!< Define the offset to be applied on the raw converted data.
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
|
||||
must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
|
||||
0x3FF, 0xFF or 0x3F respectively.
|
||||
Note: This parameter must be modified when no conversion is on going on both
|
||||
regular and injected groups (ADC disabled, or ADC enabled without
|
||||
continuous mode or external trigger that could launch a conversion). */
|
||||
|
||||
uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive
|
||||
sign) from or to the raw converted data.
|
||||
This parameter can be a value of @ref ADCEx_OffsetSign.
|
||||
Note: This parameter must be modified when no conversion is on going on both
|
||||
regular and injected groups (ADC disabled, or ADC enabled without
|
||||
continuous mode or external trigger that could launch a conversion).*/
|
||||
FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
|
||||
This parameter value can be ENABLE or DISABLE.
|
||||
Note: This parameter must be modified when no conversion is on going on both
|
||||
regular and injected groups (ADC disabled, or ADC enabled without
|
||||
continuous mode or external trigger that could launch a conversion). */
|
||||
|
||||
} ADC_ChannelConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC analog watchdog
|
||||
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion
|
||||
on going on ADC groups regular and injected.
|
||||
* - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and
|
||||
injected groups.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
|
||||
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
|
||||
by setting parameter 'WatchdogMode')
|
||||
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
|
||||
of 'HAL_ADC_AnalogWDGConfig()' for each channel)
|
||||
This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
|
||||
|
||||
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
|
||||
For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
|
||||
channels, ADC groups regular and-or injected.
|
||||
For Analog Watchdog 2 and 3: Several channels can be monitored by applying
|
||||
successively the AWD init structure. Channels on ADC
|
||||
group regular and injected are not differentiated: Set
|
||||
value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1
|
||||
channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor
|
||||
all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no
|
||||
channel.
|
||||
This parameter can be a value of @ref ADC_analog_watchdog_mode. */
|
||||
|
||||
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
|
||||
For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
|
||||
is configured on single channel (only 1 channel can be
|
||||
monitored).
|
||||
For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
|
||||
call successively the function HAL_ADC_AnalogWDGConfig()
|
||||
for each channel to be added (or removed with value
|
||||
'ADC_ANALOGWATCHDOG_NONE').
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
|
||||
|
||||
FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
|
||||
number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
|
||||
respectively.
|
||||
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
|
||||
resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
|
||||
LSB are ignored.
|
||||
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
|
||||
impacted: the comparison of analog watchdog thresholds is done on
|
||||
oversampling final computation (after ratio and shift application):
|
||||
ADC data register bitfield [15:4] (12 most significant bits). */
|
||||
|
||||
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
|
||||
number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
|
||||
respectively.
|
||||
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
|
||||
resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
|
||||
LSB are ignored.
|
||||
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
|
||||
impacted: the comparison of analog watchdog thresholds is done on
|
||||
oversampling final computation (after ratio and shift application):
|
||||
ADC data register bitfield [15:4] (12 most significant bits).*/
|
||||
|
||||
uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider.
|
||||
Before setting flag or raising interrupt, analog watchdog can wait to have several
|
||||
consecutive out-of-window samples. This parameter allows to configure this number.
|
||||
This parameter only applies to Analog watchdog 1. For others, use value
|
||||
ADC_AWD_FILTERING_NONE.
|
||||
This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */
|
||||
} ADC_AnalogWDGConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC group injected contexts queue configuration
|
||||
* @note Structure intended to be used only through structure "ADC_HandleTypeDef"
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
|
||||
HAL_ADCEx_InjectedConfigChannel() call to finally initialize
|
||||
JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
|
||||
|
||||
uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
|
||||
} ADC_InjectionConfigTypeDef;
|
||||
|
||||
/** @defgroup ADC_States ADC States
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL ADC state machine: ADC states definition (bitfields)
|
||||
* @note ADC state machine is managed by bitfields, state must be compared
|
||||
* with bit by bit.
|
||||
* For example:
|
||||
* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
|
||||
* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
|
||||
*/
|
||||
/* States of ADC global scope */
|
||||
#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
|
||||
#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
|
||||
#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization,
|
||||
calibration, ...) */
|
||||
#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
|
||||
|
||||
/* States of ADC errors */
|
||||
#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
|
||||
|
||||
/* States of ADC group regular */
|
||||
#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur
|
||||
(either by continuous mode, external trigger, low power
|
||||
auto power-on (if feature available), multimode ADC master
|
||||
control (if feature available)) */
|
||||
#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
|
||||
#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
|
||||
#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag
|
||||
raised */
|
||||
|
||||
/* States of ADC group injected */
|
||||
#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur
|
||||
(either by auto-injection mode, external trigger, low
|
||||
power auto power-on (if feature available), multimode
|
||||
ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
|
||||
#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
|
||||
|
||||
/* States of ADC analog watchdogs */
|
||||
#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
|
||||
#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
|
||||
#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
|
||||
|
||||
/* States of ADC multi-mode */
|
||||
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC
|
||||
master (when feature available) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __ADC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
{
|
||||
ADC_TypeDef *Instance; /*!< Register base address */
|
||||
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular
|
||||
conversions setting */
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
|
||||
HAL_LockTypeDef Lock; /*!< ADC locking object */
|
||||
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
|
||||
__IO uint32_t ErrorCode; /*!< ADC Error code */
|
||||
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up
|
||||
structure */
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
|
||||
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer
|
||||
callback */
|
||||
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
|
||||
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
|
||||
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete
|
||||
callback */
|
||||
void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue
|
||||
overflow callback */
|
||||
void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
|
||||
void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
|
||||
void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
|
||||
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
} ADC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL ADC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
|
||||
HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
|
||||
HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
|
||||
HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
|
||||
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
|
||||
HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */
|
||||
HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
|
||||
HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
|
||||
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
|
||||
HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
|
||||
HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
|
||||
} HAL_ADC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL ADC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
|
||||
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants ADC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Error_Code ADC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
|
||||
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
|
||||
enable/disable, erroneous state, ...) */
|
||||
#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
|
||||
#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
|
||||
#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock
|
||||
without prescaler */
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock
|
||||
with prescaler division by 2 */
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock
|
||||
with prescaler division by 4 */
|
||||
#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without
|
||||
prescaler */
|
||||
#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler
|
||||
division by 2 */
|
||||
#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler
|
||||
division by 4 */
|
||||
#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler
|
||||
division by 6 */
|
||||
#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler
|
||||
division by 8 */
|
||||
#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler
|
||||
division by 10 */
|
||||
#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler
|
||||
division by 12 */
|
||||
#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler
|
||||
division by 16 */
|
||||
#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler
|
||||
division by 32 */
|
||||
#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler
|
||||
division by 64 */
|
||||
#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler
|
||||
division by 128 */
|
||||
#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler
|
||||
division by 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
|
||||
#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
|
||||
#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
|
||||
#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned
|
||||
(alignment on data register LSB bit 0)*/
|
||||
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned
|
||||
(alignment on data register MSB bit 15)*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
|
||||
#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
|
||||
* @{
|
||||
*/
|
||||
/* ADC group regular trigger sources for all ADC instances */
|
||||
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion
|
||||
trigger software start */
|
||||
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 TRGO2. */
|
||||
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 channel 2 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM1 channel 3 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM2 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM2 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM2 channel 2 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM2 channel 3 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM3 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM3 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM3 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM4 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM4 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM4 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM6 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM7 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM8 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM8 TRGO2. */
|
||||
#define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM8 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM15 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM20 TRGO. */
|
||||
#define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM20 TRGO2. */
|
||||
#define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM20 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM20 channel 2 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: TIM20 channel 3 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 1 event. */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 2 event. */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 3 event. */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 4 event. */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 5 event. */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 6 event. */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 7 event. */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 8 event. */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 9 event. */
|
||||
#define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 10 event. */
|
||||
#define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: external interrupt line 2. */
|
||||
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: external interrupt line 11. */
|
||||
#define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion
|
||||
trigger from external peripheral: LPTIMER OUT event. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger
|
||||
disabled (SW start)*/
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion
|
||||
trigger polarity set to rising edge */
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion
|
||||
trigger polarity set to falling edge */
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion
|
||||
trigger polarity set to both rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is
|
||||
defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
|
||||
#define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts
|
||||
immediately after end of conversion, and stops upon trigger event.
|
||||
Note: First conversion is using minimal sampling time
|
||||
(see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */
|
||||
#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled
|
||||
by trigger events:
|
||||
Trigger rising edge = start sampling
|
||||
Trigger falling edge = stop sampling and start conversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
|
||||
#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case
|
||||
of overrun: data preserved */
|
||||
#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case
|
||||
of overrun: data overwritten */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
|
||||
#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
|
||||
#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
|
||||
#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
|
||||
#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
|
||||
#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
|
||||
#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
|
||||
#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
|
||||
#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
|
||||
#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
|
||||
#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
|
||||
#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
|
||||
#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
|
||||
#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
|
||||
#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
|
||||
#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5
|
||||
ADC clock cycles. If selected, this sampling time replaces sampling time
|
||||
2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
|
||||
* @{
|
||||
*/
|
||||
/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
|
||||
/* all ADC instances (refer to Reference Manual). */
|
||||
#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */
|
||||
#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */
|
||||
#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */
|
||||
#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */
|
||||
#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */
|
||||
#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */
|
||||
#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */
|
||||
#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */
|
||||
#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */
|
||||
#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */
|
||||
#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */
|
||||
#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */
|
||||
#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */
|
||||
#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */
|
||||
#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */
|
||||
#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */
|
||||
#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */
|
||||
#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */
|
||||
#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */
|
||||
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal
|
||||
voltage reference. On this STM32 series, ADC channel available on all
|
||||
instances but ADC2. */
|
||||
#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< Internal channel Temperature sensor.
|
||||
On this STM32 series, ADC channel available only on ADC1 instance. */
|
||||
#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< Internal channel Temperature sensor.
|
||||
On this STM32 series, ADC channel available only on ADC5 instance.
|
||||
Refer to device datasheet for ADC5 availability */
|
||||
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage
|
||||
through a divider ladder of factor 1/3 to have channel voltage always below
|
||||
Vdda.
|
||||
On this STM32 series, ADC channel available on all Instances but ADC2 & ADC4.
|
||||
Refer to device datasheet for ADC4 availability */
|
||||
#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< Internal channel OPAMP1 output.
|
||||
On this STM32 series, ADC channel available only on ADC1 instance. */
|
||||
#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< Internal channel OPAMP2 output.
|
||||
On this STM32 series, ADC channel available only on ADC2 instance. */
|
||||
#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< Internal channel OPAMP3 output.
|
||||
On this STM32 series, ADC channel available only on ADC2 instance. */
|
||||
#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< Internal channel OPAMP3 output.
|
||||
On this STM32 series, ADC channel available only on ADC3 instance.
|
||||
Refer to device datasheet for ADC3 availability */
|
||||
#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< Internal channel OPAMP4 output.
|
||||
On this STM32 series, ADC channel available only on ADC5 instance.
|
||||
Refer to device datasheet for ADC5 availability */
|
||||
#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< Internal channel OPAMP5 output.
|
||||
On this STM32 series, ADC channel available only on ADC5 instance.
|
||||
Refer to device datasheet for ADC5 availability */
|
||||
#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< Internal channel OPAMP6 output.
|
||||
On this STM32 series, ADC channel available only on ADC4 instance.
|
||||
Refer to device datasheet for ADC4 availability */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
|
||||
#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
|
||||
#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC AWD no filtering, one
|
||||
out-of-window sample to raise flag or interrupt */
|
||||
#define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC AWD 2 consecutives
|
||||
out-of-window samples to raise flag or interrupt */
|
||||
#define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC AWD 3 consecutives
|
||||
out-of-window samples to raise flag or interrupt */
|
||||
#define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives
|
||||
out-of-window samples to raise flag or interrupt */
|
||||
#define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC AWD 5 consecutives
|
||||
out-of-window samples to raise flag or interrupt */
|
||||
#define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives
|
||||
out-of-window samples to raise flag or interrupt */
|
||||
#define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives
|
||||
out-of-window samples to raise flag or interrupt */
|
||||
#define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
|
||||
| ADC_TR1_AWDFILT_0)) /*!< ADC AWD 8 consecutives
|
||||
out-of-window samples to raise flag or interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular
|
||||
group single channel */
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an
|
||||
injected group single channel */
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\
|
||||
| ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular
|
||||
and injected groups single channel */
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular
|
||||
group all channels */
|
||||
#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected
|
||||
group all channels */
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular
|
||||
and injected groups all channels */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed
|
||||
* to result as the ADC oversampling conversion data (before potential shift)
|
||||
*/
|
||||
#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling
|
||||
* conversion data)
|
||||
*/
|
||||
#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */
|
||||
#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
|
||||
#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode:
|
||||
continuous mode (all conversions of OVS ratio are done from 1 trigger) */
|
||||
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode:
|
||||
discontinuous mode (each conversion of OVS ratio needs a trigger) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained
|
||||
during injection sequence */
|
||||
#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during
|
||||
injection sequence */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Event_type ADC Event type
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @note Analog watchdog 1 is available on all stm32 series
|
||||
* Analog watchdog 2 and 3 are not available on all series
|
||||
*/
|
||||
#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
|
||||
#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */
|
||||
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
|
||||
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
|
||||
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
|
||||
#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility
|
||||
with other STM32 devices having only one analog watchdog */
|
||||
|
||||
/** @defgroup ADC_interrupts_definition ADC interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
|
||||
#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
|
||||
#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
|
||||
#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
|
||||
#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
|
||||
#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
|
||||
#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
|
||||
#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
|
||||
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog
|
||||
watchdog) */
|
||||
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog
|
||||
watchdog) */
|
||||
#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition ADC flags definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
|
||||
#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
|
||||
#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
|
||||
#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
|
||||
#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
|
||||
#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
|
||||
#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
|
||||
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
|
||||
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Private_Macros ADC Private Macros
|
||||
* @{
|
||||
*/
|
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
||||
/* code of final user. */
|
||||
|
||||
/**
|
||||
* @brief Return resolution bits in CFGR register RES[1:0] field.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval Value of bitfield RES in CFGR register.
|
||||
*/
|
||||
#define ADC_GET_RESOLUTION(__HANDLE__) \
|
||||
(LL_ADC_GetResolution((__HANDLE__)->Instance))
|
||||
|
||||
/**
|
||||
* @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
|
||||
|
||||
/**
|
||||
* @brief Simultaneously clear and set specific bits of the handle State.
|
||||
* @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
|
||||
* the first parameter is the ADC handle State, the second parameter is the
|
||||
* bit field to clear, the third and last parameter is the bit field to set.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_STATE_CLR_SET MODIFY_REG
|
||||
|
||||
/**
|
||||
* @brief Verify that a given value is aligned with the ADC resolution range.
|
||||
* @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
|
||||
* @param __ADC_VALUE__ value checked against the resolution.
|
||||
* @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
|
||||
*/
|
||||
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
|
||||
((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
|
||||
|
||||
/**
|
||||
* @brief Verify the length of the scheduled regular conversions group.
|
||||
* @param __LENGTH__ number of programmed conversions.
|
||||
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions)
|
||||
* or RESET (__LENGTH__ is null or too large)
|
||||
*/
|
||||
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the number of scheduled regular conversions in discontinuous mode.
|
||||
* @param NUMBER number of scheduled regular conversions in discontinuous mode.
|
||||
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode)
|
||||
* or RESET (NUMBER is null or too large)
|
||||
*/
|
||||
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC clock setting.
|
||||
* @param __ADC_CLOCK__ programmed ADC clock.
|
||||
* @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC resolution setting.
|
||||
* @param __RESOLUTION__ programmed ADC resolution.
|
||||
* @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_6B) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
|
||||
* @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
|
||||
* @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_6B) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC converted data alignment.
|
||||
* @param __ALIGN__ programmed ADC converted data alignment.
|
||||
* @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
|
||||
((__ALIGN__) == ADC_DATAALIGN_LEFT) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC gain compensation.
|
||||
* @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
|
||||
* @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL)
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC scan mode.
|
||||
* @param __SCAN_MODE__ programmed ADC scan mode.
|
||||
* @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
|
||||
((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC edge trigger setting for regular group.
|
||||
* @param __EDGE__ programmed ADC edge trigger setting.
|
||||
* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC regular conversions external trigger.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __REGTRIG__ programmed ADC regular conversions external trigger.
|
||||
* @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
|
||||
*/
|
||||
#if defined(STM32G474xx) || defined(STM32G484xx)
|
||||
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
|
||||
((((__HANDLE__)->Instance == ADC1) || \
|
||||
((__HANDLE__)->Instance == ADC2)) && \
|
||||
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
|
||||
((((__HANDLE__)->Instance == ADC3) || \
|
||||
((__HANDLE__)->Instance == ADC4) || \
|
||||
((__HANDLE__)->Instance == ADC5)) && \
|
||||
(((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
|
||||
((__REGTRIG__) == ADC_SOFTWARE_START) )
|
||||
#elif defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
|
||||
((((__HANDLE__)->Instance == ADC1) || \
|
||||
((__HANDLE__)->Instance == ADC2)) && \
|
||||
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
|
||||
((((__HANDLE__)->Instance == ADC3) || \
|
||||
((__HANDLE__)->Instance == ADC4) || \
|
||||
((__HANDLE__)->Instance == ADC5)) && \
|
||||
(((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
|
||||
((__REGTRIG__) == ADC_SOFTWARE_START) )
|
||||
#elif defined(STM32G471xx)
|
||||
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
|
||||
((((__HANDLE__)->Instance == ADC1) || \
|
||||
((__HANDLE__)->Instance == ADC2)) && \
|
||||
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
|
||||
((((__HANDLE__)->Instance == ADC3)) && \
|
||||
(((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
|
||||
((__REGTRIG__) == ADC_SOFTWARE_START) )
|
||||
#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
|
||||
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
|
||||
((__REGTRIG__) == ADC_SOFTWARE_START) )
|
||||
#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
|
||||
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
|
||||
((((__HANDLE__)->Instance == ADC1) || \
|
||||
((__HANDLE__)->Instance == ADC2)) && \
|
||||
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
|
||||
(((__HANDLE__)->Instance == ADC3) && \
|
||||
(((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
|
||||
((__REGTRIG__) == ADC_SOFTWARE_START) )
|
||||
#endif /* STM32G4xx */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC regular conversions external trigger.
|
||||
* @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
|
||||
* @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \
|
||||
((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \
|
||||
((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC regular conversions check for converted data availability.
|
||||
* @param __EOC_SELECTION__ converted data availability check.
|
||||
* @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
|
||||
((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC regular conversions overrun handling.
|
||||
* @param __OVR__ ADC regular conversions overrun handling.
|
||||
* @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
|
||||
((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC conversions sampling time.
|
||||
* @param __TIME__ ADC conversions sampling time.
|
||||
* @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC regular channel setting.
|
||||
* @param __CHANNEL__ programmed ADC regular channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
|
||||
((__CHANNEL__) == ADC_REGULAR_RANK_16) )
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Private_Constants ADC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Fixed timeout values for ADC conversion (including sampling time) */
|
||||
/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */
|
||||
/* Maximum conversion time is 12.5 + Maximum sampling time */
|
||||
/* or 12.5 + 640.5 = 653 ADC clock cycles */
|
||||
/* Minimum ADC Clock frequency is 0.14 MHz */
|
||||
/* Maximum conversion time is */
|
||||
/* 653 / 0.14 MHz = 4.66 ms */
|
||||
#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */
|
||||
|
||||
/* Delay for temperature sensor stabilization time. */
|
||||
/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
|
||||
/* Unit: us */
|
||||
#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/* Macro for internal HAL driver usage, and possibly can be used into code of */
|
||||
/* final user. */
|
||||
|
||||
/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset ADC handle state.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
|
||||
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable ADC interrupt.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __INTERRUPT__ ADC Interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_IT_RDY ADC Ready interrupt source
|
||||
* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
|
||||
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
|
||||
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
|
||||
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
|
||||
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
|
||||
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
|
||||
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
|
||||
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
|
||||
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
|
||||
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable ADC interrupt.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __INTERRUPT__ ADC Interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_IT_RDY ADC Ready interrupt source
|
||||
* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
|
||||
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
|
||||
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
|
||||
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
|
||||
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
|
||||
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
|
||||
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
|
||||
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
|
||||
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
|
||||
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __INTERRUPT__ ADC interrupt source to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_IT_RDY ADC Ready interrupt source
|
||||
* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
|
||||
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
|
||||
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
|
||||
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
|
||||
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
|
||||
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
|
||||
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
|
||||
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
|
||||
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
|
||||
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified ADC flag is set or not.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __FLAG__ ADC flag
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_FLAG_RDY ADC Ready flag
|
||||
* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
|
||||
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
|
||||
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
|
||||
* @arg @ref ADC_FLAG_OVR ADC overrun flag
|
||||
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
|
||||
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
|
||||
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
|
||||
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
|
||||
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
|
||||
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
|
||||
* @retval State of flag (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified ADC flag.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __FLAG__ ADC flag
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_FLAG_RDY ADC Ready flag
|
||||
* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
|
||||
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
|
||||
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
|
||||
* @arg @ref ADC_FLAG_OVR ADC overrun flag
|
||||
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
|
||||
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
|
||||
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
|
||||
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
|
||||
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
|
||||
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
|
||||
* @retval None
|
||||
*/
|
||||
/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
|
||||
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((__HANDLE__)->Instance->ISR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Helper macro to get ADC channel number in decimal format
|
||||
* from literals ADC_CHANNEL_x.
|
||||
* @note Example:
|
||||
* __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
|
||||
* will return decimal number "4".
|
||||
* @note The input can be a value from functions where a channel
|
||||
* number is returned, either defined with number
|
||||
* or with bitfield (only one bit must be set).
|
||||
* @param __CHANNEL__ This parameter can be one of the following values:
|
||||
* @arg @ref ADC_CHANNEL_0
|
||||
* @arg @ref ADC_CHANNEL_1 (8)
|
||||
* @arg @ref ADC_CHANNEL_2 (8)
|
||||
* @arg @ref ADC_CHANNEL_3 (8)
|
||||
* @arg @ref ADC_CHANNEL_4 (8)
|
||||
* @arg @ref ADC_CHANNEL_5 (8)
|
||||
* @arg @ref ADC_CHANNEL_6
|
||||
* @arg @ref ADC_CHANNEL_7
|
||||
* @arg @ref ADC_CHANNEL_8
|
||||
* @arg @ref ADC_CHANNEL_9
|
||||
* @arg @ref ADC_CHANNEL_10
|
||||
* @arg @ref ADC_CHANNEL_11
|
||||
* @arg @ref ADC_CHANNEL_12
|
||||
* @arg @ref ADC_CHANNEL_13
|
||||
* @arg @ref ADC_CHANNEL_14
|
||||
* @arg @ref ADC_CHANNEL_15
|
||||
* @arg @ref ADC_CHANNEL_16
|
||||
* @arg @ref ADC_CHANNEL_17
|
||||
* @arg @ref ADC_CHANNEL_18
|
||||
* @arg @ref ADC_CHANNEL_VREFINT (7)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VBAT (6)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
|
||||
*
|
||||
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
|
||||
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
|
||||
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
|
||||
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
|
||||
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
|
||||
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
|
||||
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
|
||||
* On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
|
||||
* for more details.
|
||||
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
|
||||
* convert in 12-bit resolution.
|
||||
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
|
||||
* (fADC) to convert in 12-bit resolution.\n
|
||||
* @retval Value between Min_Data=0 and Max_Data=18
|
||||
*/
|
||||
#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
|
||||
__LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
|
||||
* from number in decimal format.
|
||||
* @note Example:
|
||||
* __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
|
||||
* will return a data equivalent to "ADC_CHANNEL_4".
|
||||
* @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref ADC_CHANNEL_0
|
||||
* @arg @ref ADC_CHANNEL_1 (8)
|
||||
* @arg @ref ADC_CHANNEL_2 (8)
|
||||
* @arg @ref ADC_CHANNEL_3 (8)
|
||||
* @arg @ref ADC_CHANNEL_4 (8)
|
||||
* @arg @ref ADC_CHANNEL_5 (8)
|
||||
* @arg @ref ADC_CHANNEL_6
|
||||
* @arg @ref ADC_CHANNEL_7
|
||||
* @arg @ref ADC_CHANNEL_8
|
||||
* @arg @ref ADC_CHANNEL_9
|
||||
* @arg @ref ADC_CHANNEL_10
|
||||
* @arg @ref ADC_CHANNEL_11
|
||||
* @arg @ref ADC_CHANNEL_12
|
||||
* @arg @ref ADC_CHANNEL_13
|
||||
* @arg @ref ADC_CHANNEL_14
|
||||
* @arg @ref ADC_CHANNEL_15
|
||||
* @arg @ref ADC_CHANNEL_16
|
||||
* @arg @ref ADC_CHANNEL_17
|
||||
* @arg @ref ADC_CHANNEL_18
|
||||
* @arg @ref ADC_CHANNEL_VREFINT (7)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VBAT (6)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
|
||||
*
|
||||
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
|
||||
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
|
||||
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
|
||||
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
|
||||
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
|
||||
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
|
||||
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
|
||||
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
|
||||
* more details.
|
||||
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC)
|
||||
* to convert in 12-bit resolution.
|
||||
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
|
||||
* (fADC) to convert in 12-bit resolution.\n
|
||||
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
|
||||
* comparison with internal channel parameter to be done
|
||||
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
|
||||
*/
|
||||
#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
|
||||
__LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to determine whether the selected channel
|
||||
* corresponds to literal definitions of driver.
|
||||
* @note The different literal definitions of ADC channels are:
|
||||
* - ADC internal channel:
|
||||
* ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
|
||||
* - ADC external channel (channel connected to a GPIO pin):
|
||||
* ADC_CHANNEL_1, ADC_CHANNEL_2, ...
|
||||
* @note The channel parameter must be a value defined from literal
|
||||
* definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
|
||||
* ADC_CHANNEL_TEMPSENSOR, ...),
|
||||
* ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
|
||||
* must not be a value from functions where a channel number is
|
||||
* returned from ADC registers,
|
||||
* because internal and external channels share the same channel
|
||||
* number in ADC registers. The differentiation is made only with
|
||||
* parameters definitions of driver.
|
||||
* @param __CHANNEL__ This parameter can be one of the following values:
|
||||
* @arg @ref ADC_CHANNEL_0
|
||||
* @arg @ref ADC_CHANNEL_1 (8)
|
||||
* @arg @ref ADC_CHANNEL_2 (8)
|
||||
* @arg @ref ADC_CHANNEL_3 (8)
|
||||
* @arg @ref ADC_CHANNEL_4 (8)
|
||||
* @arg @ref ADC_CHANNEL_5 (8)
|
||||
* @arg @ref ADC_CHANNEL_6
|
||||
* @arg @ref ADC_CHANNEL_7
|
||||
* @arg @ref ADC_CHANNEL_8
|
||||
* @arg @ref ADC_CHANNEL_9
|
||||
* @arg @ref ADC_CHANNEL_10
|
||||
* @arg @ref ADC_CHANNEL_11
|
||||
* @arg @ref ADC_CHANNEL_12
|
||||
* @arg @ref ADC_CHANNEL_13
|
||||
* @arg @ref ADC_CHANNEL_14
|
||||
* @arg @ref ADC_CHANNEL_15
|
||||
* @arg @ref ADC_CHANNEL_16
|
||||
* @arg @ref ADC_CHANNEL_17
|
||||
* @arg @ref ADC_CHANNEL_18
|
||||
* @arg @ref ADC_CHANNEL_VREFINT (7)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VBAT (6)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
|
||||
*
|
||||
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
|
||||
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
|
||||
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
|
||||
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
|
||||
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
|
||||
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
|
||||
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
|
||||
* On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
|
||||
* for more details.
|
||||
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
|
||||
* convert in 12-bit resolution.
|
||||
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
|
||||
* (fADC) to convert in 12-bit resolution.\n
|
||||
* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
|
||||
* connected to a GPIO pin).
|
||||
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
|
||||
*/
|
||||
#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
|
||||
__LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to convert a channel defined from parameter
|
||||
* definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
|
||||
* ADC_CHANNEL_TEMPSENSOR, ...),
|
||||
* to its equivalent parameter definition of a ADC external channel
|
||||
* (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
|
||||
* @note The channel parameter can be, additionally to a value
|
||||
* defined from parameter definition of a ADC internal channel
|
||||
* (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
|
||||
* a value defined from parameter definition of
|
||||
* ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
|
||||
* or a value from functions where a channel number is returned
|
||||
* from ADC registers.
|
||||
* @param __CHANNEL__ This parameter can be one of the following values:
|
||||
* @arg @ref ADC_CHANNEL_0
|
||||
* @arg @ref ADC_CHANNEL_1 (8)
|
||||
* @arg @ref ADC_CHANNEL_2 (8)
|
||||
* @arg @ref ADC_CHANNEL_3 (8)
|
||||
* @arg @ref ADC_CHANNEL_4 (8)
|
||||
* @arg @ref ADC_CHANNEL_5 (8)
|
||||
* @arg @ref ADC_CHANNEL_6
|
||||
* @arg @ref ADC_CHANNEL_7
|
||||
* @arg @ref ADC_CHANNEL_8
|
||||
* @arg @ref ADC_CHANNEL_9
|
||||
* @arg @ref ADC_CHANNEL_10
|
||||
* @arg @ref ADC_CHANNEL_11
|
||||
* @arg @ref ADC_CHANNEL_12
|
||||
* @arg @ref ADC_CHANNEL_13
|
||||
* @arg @ref ADC_CHANNEL_14
|
||||
* @arg @ref ADC_CHANNEL_15
|
||||
* @arg @ref ADC_CHANNEL_16
|
||||
* @arg @ref ADC_CHANNEL_17
|
||||
* @arg @ref ADC_CHANNEL_18
|
||||
* @arg @ref ADC_CHANNEL_VREFINT (7)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VBAT (6)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
|
||||
*
|
||||
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
|
||||
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
|
||||
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
|
||||
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
|
||||
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
|
||||
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
|
||||
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
|
||||
* On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
|
||||
* for more details.
|
||||
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
|
||||
* convert in 12-bit resolution.
|
||||
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
|
||||
* (fADC) to convert in 12-bit resolution.\n
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref ADC_CHANNEL_0
|
||||
* @arg @ref ADC_CHANNEL_1
|
||||
* @arg @ref ADC_CHANNEL_2
|
||||
* @arg @ref ADC_CHANNEL_3
|
||||
* @arg @ref ADC_CHANNEL_4
|
||||
* @arg @ref ADC_CHANNEL_5
|
||||
* @arg @ref ADC_CHANNEL_6
|
||||
* @arg @ref ADC_CHANNEL_7
|
||||
* @arg @ref ADC_CHANNEL_8
|
||||
* @arg @ref ADC_CHANNEL_9
|
||||
* @arg @ref ADC_CHANNEL_10
|
||||
* @arg @ref ADC_CHANNEL_11
|
||||
* @arg @ref ADC_CHANNEL_12
|
||||
* @arg @ref ADC_CHANNEL_13
|
||||
* @arg @ref ADC_CHANNEL_14
|
||||
* @arg @ref ADC_CHANNEL_15
|
||||
* @arg @ref ADC_CHANNEL_16
|
||||
* @arg @ref ADC_CHANNEL_17
|
||||
* @arg @ref ADC_CHANNEL_18
|
||||
*/
|
||||
#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
|
||||
__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to determine whether the internal channel
|
||||
* selected is available on the ADC instance selected.
|
||||
* @note The channel parameter must be a value defined from parameter
|
||||
* definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
|
||||
* ADC_CHANNEL_TEMPSENSOR, ...),
|
||||
* must not be a value defined from parameter definition of
|
||||
* ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
|
||||
* or a value from functions where a channel number is
|
||||
* returned from ADC registers,
|
||||
* because internal and external channels share the same channel
|
||||
* number in ADC registers. The differentiation is made only with
|
||||
* parameters definitions of driver.
|
||||
* @param __ADC_INSTANCE__ ADC instance
|
||||
* @param __CHANNEL__ This parameter can be one of the following values:
|
||||
* @arg @ref ADC_CHANNEL_VREFINT (7)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
|
||||
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VBAT (6)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
|
||||
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
|
||||
*
|
||||
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
|
||||
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
|
||||
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
|
||||
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
|
||||
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
|
||||
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
|
||||
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
|
||||
* On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
|
||||
* for more details.
|
||||
* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
|
||||
* Value "1" if the internal channel selected is available on the ADC instance selected.
|
||||
*/
|
||||
#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
|
||||
__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
|
||||
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
/**
|
||||
* @brief Helper macro to get the ADC multimode conversion data of ADC master
|
||||
* or ADC slave from raw value with both ADC conversion data concatenated.
|
||||
* @note This macro is intended to be used when multimode transfer by DMA
|
||||
* is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
|
||||
* In this case the transferred data need to processed with this macro
|
||||
* to separate the conversion data of ADC master and ADC slave.
|
||||
* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
|
||||
* @arg @ref LL_ADC_MULTI_MASTER
|
||||
* @arg @ref LL_ADC_MULTI_SLAVE
|
||||
* @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
|
||||
*/
|
||||
#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
|
||||
__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Helper macro to select the ADC common instance
|
||||
* to which is belonging the selected ADC instance.
|
||||
* @note ADC common register instance can be used for:
|
||||
* - Set parameters common to several ADC instances
|
||||
* - Multimode (for devices with several ADC instances)
|
||||
* Refer to functions having argument "ADCxy_COMMON" as parameter.
|
||||
* @param __ADCx__ ADC instance
|
||||
* @retval ADC common register instance
|
||||
*/
|
||||
#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
|
||||
__LL_ADC_COMMON_INSTANCE((__ADCx__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to check if all ADC instances sharing the same
|
||||
* ADC common instance are disabled.
|
||||
* @note This check is required by functions with setting conditioned to
|
||||
* ADC state:
|
||||
* All ADC instances of the ADC common group must be disabled.
|
||||
* Refer to functions having argument "ADCxy_COMMON" as parameter.
|
||||
* @note On devices with only 1 ADC common instance, parameter of this macro
|
||||
* is useless and can be ignored (parameter kept for compatibility
|
||||
* with devices featuring several ADC common instances).
|
||||
* @param __ADCXY_COMMON__ ADC common instance
|
||||
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
|
||||
* @retval Value "0" if all ADC instances sharing the same ADC common instance
|
||||
* are disabled.
|
||||
* Value "1" if at least one ADC instance sharing the same ADC common instance
|
||||
* is enabled.
|
||||
*/
|
||||
#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
|
||||
__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to define the ADC conversion data full-scale digital
|
||||
* value corresponding to the selected ADC resolution.
|
||||
* @note ADC conversion data full-scale corresponds to voltage range
|
||||
* determined by analog voltage references Vref+ and Vref-
|
||||
* (refer to reference manual).
|
||||
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
|
||||
* @arg @ref ADC_RESOLUTION_12B
|
||||
* @arg @ref ADC_RESOLUTION_10B
|
||||
* @arg @ref ADC_RESOLUTION_8B
|
||||
* @arg @ref ADC_RESOLUTION_6B
|
||||
* @retval ADC conversion data full-scale digital value
|
||||
*/
|
||||
#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
|
||||
__LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to convert the ADC conversion data from
|
||||
* a resolution to another resolution.
|
||||
* @param __DATA__ ADC conversion data to be converted
|
||||
* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_RESOLUTION_12B
|
||||
* @arg @ref ADC_RESOLUTION_10B
|
||||
* @arg @ref ADC_RESOLUTION_8B
|
||||
* @arg @ref ADC_RESOLUTION_6B
|
||||
* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_RESOLUTION_12B
|
||||
* @arg @ref ADC_RESOLUTION_10B
|
||||
* @arg @ref ADC_RESOLUTION_8B
|
||||
* @arg @ref ADC_RESOLUTION_6B
|
||||
* @retval ADC conversion data to the requested resolution
|
||||
*/
|
||||
#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
|
||||
__ADC_RESOLUTION_CURRENT__,\
|
||||
__ADC_RESOLUTION_TARGET__) \
|
||||
__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
|
||||
(__ADC_RESOLUTION_CURRENT__),\
|
||||
(__ADC_RESOLUTION_TARGET__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to calculate the voltage (unit: mVolt)
|
||||
* corresponding to a ADC conversion data (unit: digital value).
|
||||
* @note Analog reference voltage (Vref+) must be either known from
|
||||
* user board environment or can be calculated using ADC measurement
|
||||
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
|
||||
* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
|
||||
* (unit: digital value).
|
||||
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
|
||||
* @arg @ref ADC_RESOLUTION_12B
|
||||
* @arg @ref ADC_RESOLUTION_10B
|
||||
* @arg @ref ADC_RESOLUTION_8B
|
||||
* @arg @ref ADC_RESOLUTION_6B
|
||||
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
|
||||
*/
|
||||
#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
|
||||
__ADC_DATA__,\
|
||||
__ADC_RESOLUTION__) \
|
||||
__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
|
||||
(__ADC_DATA__),\
|
||||
(__ADC_RESOLUTION__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to calculate the voltage (unit: mVolt)
|
||||
* corresponding to a ADC conversion data (unit: digital value)
|
||||
* in differential ended mode.
|
||||
* @note Analog reference voltage (Vref+) must be either known from
|
||||
* user board environment or can be calculated using ADC measurement
|
||||
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
|
||||
* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
|
||||
* (unit: digital value).
|
||||
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
|
||||
* @arg @ref ADC_RESOLUTION_12B
|
||||
* @arg @ref ADC_RESOLUTION_10B
|
||||
* @arg @ref ADC_RESOLUTION_8B
|
||||
* @arg @ref ADC_RESOLUTION_6B
|
||||
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
|
||||
*/
|
||||
#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
|
||||
__ADC_DATA__,\
|
||||
__ADC_RESOLUTION__) \
|
||||
__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
|
||||
(__ADC_DATA__),\
|
||||
(__ADC_RESOLUTION__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to calculate analog reference voltage (Vref+)
|
||||
* (unit: mVolt) from ADC conversion data of internal voltage
|
||||
* reference VrefInt.
|
||||
* @note Computation is using VrefInt calibration value
|
||||
* stored in system memory for each device during production.
|
||||
* @note This voltage depends on user board environment: voltage level
|
||||
* connected to pin Vref+.
|
||||
* On devices with small package, the pin Vref+ is not present
|
||||
* and internally bonded to pin Vdda.
|
||||
* @note On this STM32 series, calibration data of internal voltage reference
|
||||
* VrefInt corresponds to a resolution of 12 bits,
|
||||
* this is the recommended ADC resolution to convert voltage of
|
||||
* internal voltage reference VrefInt.
|
||||
* Otherwise, this macro performs the processing to scale
|
||||
* ADC conversion data to 12 bits.
|
||||
* @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
|
||||
* of internal voltage reference VrefInt (unit: digital value).
|
||||
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
|
||||
* @arg @ref ADC_RESOLUTION_12B
|
||||
* @arg @ref ADC_RESOLUTION_10B
|
||||
* @arg @ref ADC_RESOLUTION_8B
|
||||
* @arg @ref ADC_RESOLUTION_6B
|
||||
* @retval Analog reference voltage (unit: mV)
|
||||
*/
|
||||
#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
|
||||
__ADC_RESOLUTION__) \
|
||||
__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
|
||||
(__ADC_RESOLUTION__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
|
||||
* from ADC conversion data of internal temperature sensor.
|
||||
* @note Computation is using temperature sensor calibration values
|
||||
* stored in system memory for each device during production.
|
||||
* @note Calculation formula:
|
||||
* Temperature = ((TS_ADC_DATA - TS_CAL1)
|
||||
* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
|
||||
* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
|
||||
* with TS_ADC_DATA = temperature sensor raw data measured by ADC
|
||||
* Avg_Slope = (TS_CAL2 - TS_CAL1)
|
||||
* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
|
||||
* TS_CAL1 = equivalent TS_ADC_DATA at temperature
|
||||
* TEMP_DEGC_CAL1 (calibrated in factory)
|
||||
* TS_CAL2 = equivalent TS_ADC_DATA at temperature
|
||||
* TEMP_DEGC_CAL2 (calibrated in factory)
|
||||
* Caution: Calculation relevancy under reserve that calibration
|
||||
* parameters are correct (address and data).
|
||||
* To calculate temperature using temperature sensor
|
||||
* datasheet typical values (generic values less, therefore
|
||||
* less accurate than calibrated values),
|
||||
* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
|
||||
* @note As calculation input, the analog reference voltage (Vref+) must be
|
||||
* defined as it impacts the ADC LSB equivalent voltage.
|
||||
* @note Analog reference voltage (Vref+) must be either known from
|
||||
* user board environment or can be calculated using ADC measurement
|
||||
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* @note On this STM32 series, calibration data of temperature sensor
|
||||
* corresponds to a resolution of 12 bits,
|
||||
* this is the recommended ADC resolution to convert voltage of
|
||||
* temperature sensor.
|
||||
* Otherwise, this macro performs the processing to scale
|
||||
* ADC conversion data to 12 bits.
|
||||
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
|
||||
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
|
||||
* temperature sensor (unit: digital value).
|
||||
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
|
||||
* sensor voltage has been measured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_RESOLUTION_12B
|
||||
* @arg @ref ADC_RESOLUTION_10B
|
||||
* @arg @ref ADC_RESOLUTION_8B
|
||||
* @arg @ref ADC_RESOLUTION_6B
|
||||
* @retval Temperature (unit: degree Celsius)
|
||||
*/
|
||||
#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
|
||||
__TEMPSENSOR_ADC_DATA__,\
|
||||
__ADC_RESOLUTION__) \
|
||||
__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
|
||||
(__TEMPSENSOR_ADC_DATA__),\
|
||||
(__ADC_RESOLUTION__))
|
||||
|
||||
/**
|
||||
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
|
||||
* from ADC conversion data of internal temperature sensor.
|
||||
* @note Computation is using temperature sensor typical values
|
||||
* (refer to device datasheet).
|
||||
* @note Calculation formula:
|
||||
* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
|
||||
* / Avg_Slope + CALx_TEMP
|
||||
* with TS_ADC_DATA = temperature sensor raw data measured by ADC
|
||||
* (unit: digital value)
|
||||
* Avg_Slope = temperature sensor slope
|
||||
* (unit: uV/Degree Celsius)
|
||||
* TS_TYP_CALx_VOLT = temperature sensor digital value at
|
||||
* temperature CALx_TEMP (unit: mV)
|
||||
* Caution: Calculation relevancy under reserve the temperature sensor
|
||||
* of the current device has characteristics in line with
|
||||
* datasheet typical values.
|
||||
* If temperature sensor calibration values are available on
|
||||
* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
|
||||
* temperature calculation will be more accurate using
|
||||
* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
|
||||
* @note As calculation input, the analog reference voltage (Vref+) must be
|
||||
* defined as it impacts the ADC LSB equivalent voltage.
|
||||
* @note Analog reference voltage (Vref+) must be either known from
|
||||
* user board environment or can be calculated using ADC measurement
|
||||
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
|
||||
* @note ADC measurement data must correspond to a resolution of 12bits
|
||||
* (full scale digital value 4095). If not the case, the data must be
|
||||
* preliminarily rescaled to an equivalent resolution of 12 bits.
|
||||
* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
|
||||
(unit: uV/DegCelsius).
|
||||
* On STM32G4, refer to device datasheet parameter "Avg_Slope".
|
||||
* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at
|
||||
temperature and Vref+ defined in parameters below) (unit: mV).
|
||||
* On STM32G4, refer to device datasheet parameter "V30"
|
||||
(corresponding to TS_CAL1).
|
||||
* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see
|
||||
parameter above) is corresponding (unit: mV)
|
||||
* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
|
||||
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
|
||||
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref ADC_RESOLUTION_12B
|
||||
* @arg @ref ADC_RESOLUTION_10B
|
||||
* @arg @ref ADC_RESOLUTION_8B
|
||||
* @arg @ref ADC_RESOLUTION_6B
|
||||
* @retval Temperature (unit: degree Celsius)
|
||||
*/
|
||||
#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
|
||||
__TEMPSENSOR_TYP_CALX_V__,\
|
||||
__TEMPSENSOR_CALX_TEMP__,\
|
||||
__VREFANALOG_VOLTAGE__,\
|
||||
__TEMPSENSOR_ADC_DATA__,\
|
||||
__ADC_RESOLUTION__) \
|
||||
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
|
||||
(__TEMPSENSOR_TYP_CALX_V__),\
|
||||
(__TEMPSENSOR_CALX_TEMP__),\
|
||||
(__VREFANALOG_VOLTAGE__),\
|
||||
(__TEMPSENSOR_ADC_DATA__),\
|
||||
(__ADC_RESOLUTION__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include ADC HAL Extended module */
|
||||
#include "stm32g4xx_hal_adc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
|
||||
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
|
||||
pADC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group2
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
|
||||
|
||||
/* Non-blocking mode: Interruption */
|
||||
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* Non-blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* ADC sampling control */
|
||||
HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
|
||||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc,
|
||||
const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions *************************************************/
|
||||
/** @addtogroup ADC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
|
||||
uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup ADC_Private_Functions ADC Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
|
||||
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
|
||||
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
|
||||
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
|
||||
void ADC_DMAError(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32G4xx_HAL_ADC_H */
|
||||
1570
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
Normal file
1570
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
Normal file
@@ -0,0 +1,1570 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_adc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ADC HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_ADC_EX_H
|
||||
#define STM32G4xx_HAL_ADC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Injected Conversion Oversampling structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Ratio; /*!< Configures the oversampling ratio.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
|
||||
|
||||
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
|
||||
} ADC_InjOversamplingTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
|
||||
* InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation
|
||||
* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
|
||||
* InjectedDiscontinuousConvMode,
|
||||
* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge,
|
||||
* InjecOversamplingMode, InjecOversampling.
|
||||
* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
|
||||
* 'InjectedSingleDiff')
|
||||
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled
|
||||
* without conversion on going on injected group.
|
||||
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign',
|
||||
* 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and
|
||||
* injected groups.
|
||||
* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
|
||||
* 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
|
||||
* on ADC groups regular and injected.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another
|
||||
* parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
|
||||
Note: Depending on devices and ADC instances, some channels may not be
|
||||
available on device package pins. Refer to device datasheet for
|
||||
channels availability. */
|
||||
|
||||
uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
|
||||
This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
|
||||
Note: to disable a channel or change order of conversion sequencer,
|
||||
rank containing a previous channel setting can be overwritten by
|
||||
the new channel setting (or parameter number of conversions
|
||||
adjusted) */
|
||||
|
||||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles.
|
||||
Conversion time is the addition of sampling time and processing time
|
||||
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
|
||||
8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
|
||||
Caution: This parameter applies to a channel that can be used in a
|
||||
regular and/or injected group. It overwrites the last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt, ...),
|
||||
sampling time constraints must be respected (sampling time can be
|
||||
adjusted in function of ADC clock frequency and sampling time
|
||||
setting). Refer to device datasheet for timings values. */
|
||||
|
||||
uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
|
||||
In differential mode: Differential measurement is between the selected
|
||||
channel 'i' (positive input) and channel 'i+1' (negative input).
|
||||
Only channel 'i' has to be configured, channel 'i+1' is configured
|
||||
automatically.
|
||||
This parameter must be a value of
|
||||
@ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
|
||||
Caution: This parameter applies to a channel that can be used in a
|
||||
regular and/or injected group. It overwrites the last setting.
|
||||
Note: Refer to Reference Manual to ensure the selected channel is
|
||||
available in differential mode.
|
||||
Note: When configuring a channel 'i' in differential mode, the channel
|
||||
'i+1' is not usable separately.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC
|
||||
start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error
|
||||
reporting (as it can be the expected behavior in case of another
|
||||
parameter update on the fly) */
|
||||
|
||||
uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
|
||||
Caution: Only one offset is allowed per channel. This parameter
|
||||
overwrites the last setting. */
|
||||
|
||||
uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data.
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this
|
||||
parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
|
||||
0x3FF, 0xFF or 0x3F respectively.
|
||||
Note: This parameter must be modified when no conversion is on going
|
||||
on both regular and injected groups (ADC disabled, or ADC enabled
|
||||
without continuous mode or external trigger that could launch a
|
||||
conversion). */
|
||||
|
||||
uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added
|
||||
(positive sign) from or to the raw converted data.
|
||||
This parameter can be a value of @ref ADCEx_OffsetSign.
|
||||
Note: This parameter must be modified when no conversion is on going
|
||||
on both regular and injected groups (ADC disabled, or ADC
|
||||
enabled without continuous mode or external trigger that could
|
||||
launch a conversion). */
|
||||
FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
|
||||
This parameter value can be ENABLE or DISABLE.
|
||||
Note: This parameter must be modified when no conversion is on going
|
||||
on both regular and injected groups (ADC disabled, or ADC enabled
|
||||
without continuous mode or external trigger that could launch a
|
||||
conversion). */
|
||||
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group
|
||||
injected sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter
|
||||
'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on
|
||||
injected group can impact the configuration of other channels previously
|
||||
set. */
|
||||
|
||||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected
|
||||
is performed in Complete-sequence/Discontinuous-sequence
|
||||
(main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter
|
||||
'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC
|
||||
start conversion or after ADC stop conversion).
|
||||
Note: For injected group, discontinuous mode converts the sequence
|
||||
channel by channel (discontinuous length fixed to 1 rank).
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the
|
||||
configuration of other channels previously set. */
|
||||
|
||||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion
|
||||
after regular one
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: To use Automatic injected conversion, discontinuous mode must
|
||||
be disabled ('DiscontinuousConvMode' and
|
||||
'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||
Note: To use Automatic injected conversion, injected group external
|
||||
triggers must be disabled ('ExternalTrigInjecConv' set to
|
||||
ADC_INJECTED_SOFTWARE_START)
|
||||
Note: In case of DMA used with regular group: if DMA configured in
|
||||
normal mode (single shot) JAUTO will be stopped upon DMA transfer
|
||||
complete.
|
||||
To maintain JAUTO always enabled, DMA must be configured in
|
||||
circular mode.
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
|
||||
on injected group can impact the configuration of other channels
|
||||
previously set. */
|
||||
|
||||
FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
If context queue is enabled, injected sequencer&channels configurations
|
||||
are queued on up to 2 contexts. If a
|
||||
new injected context is set when queue is full, error is triggered by
|
||||
interruption and through function
|
||||
'HAL_ADCEx_InjectedQueueOverflowCallback'.
|
||||
Caution: This feature request that the sequence is fully configured
|
||||
before injected conversion start.
|
||||
Therefore, configure channels with as many calls to
|
||||
HAL_ADCEx_InjectedConfigChannel() as the
|
||||
'InjectedNbrOfConversion' parameter.
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the
|
||||
configuration of other channels previously set.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC
|
||||
start conversion or after ADC stop conversion). */
|
||||
|
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of
|
||||
injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled
|
||||
and software trigger is used instead.
|
||||
This parameter can be a value of
|
||||
@ref ADC_injected_external_trigger_source.
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
|
||||
on injected group can impact the configuration of other channels
|
||||
previously set. */
|
||||
|
||||
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
|
||||
This parameter can be a value of @ref ADC_injected_external_trigger_edge.
|
||||
If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter
|
||||
is discarded.
|
||||
Caution: this setting impacts the entire injected group. Therefore,
|
||||
call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the
|
||||
configuration of other channels previously set. */
|
||||
|
||||
FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter can be modified only if there is no
|
||||
conversion is ongoing (both ADSTART and JADSTART cleared). */
|
||||
|
||||
ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
|
||||
Caution: this setting overwrites the previous oversampling
|
||||
configuration if oversampling already enabled.
|
||||
Note: This parameter can be modified only if there is no
|
||||
conversion is ongoing (both ADSTART and JADSTART cleared).*/
|
||||
} ADC_InjectionConfTypeDef;
|
||||
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
/**
|
||||
* @brief Structure definition of ADC multimode
|
||||
* @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state
|
||||
* (both Master and Slave ADCs).
|
||||
* Both Master and Slave ADCs must be disabled.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
|
||||
|
||||
uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
|
||||
selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel
|
||||
(one DMA channel for both ADC, DMA of ADC master).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
|
||||
|
||||
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
|
||||
Delay range depends on selected resolution:
|
||||
from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
|
||||
from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */
|
||||
} ADC_MultiModeTypeDef;
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
|
||||
* @{
|
||||
*/
|
||||
/* ADC group regular trigger sources for all ADC instances */
|
||||
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion
|
||||
trigger software start */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM1 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM1 TRGO2. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM1 channel 3 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM1 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM2 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM2 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM3 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM3 channel 1 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM3 channel 3 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM3 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM4 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM4 channel 3 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM4 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM6 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM7 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM8 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM8 TRGO2. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM8 channel 2 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM8 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM15 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM8 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM20 TRGO. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM20 TRGO2. */
|
||||
#define ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM20 channel 2 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: TIM20 channel 4 event (capture compare). */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 1 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 2 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 3 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 4 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 5 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 6 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 7 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 8 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 9 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: HRTIMER ADC trigger 10 event. */
|
||||
#define ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: external interrupt line 3. */
|
||||
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: external interrupt line 15. */
|
||||
#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion
|
||||
trigger from external peripheral: LPTIMER OUT event. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger
|
||||
disabled (SW start)*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger
|
||||
polarity set to rising edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger
|
||||
polarity set to falling edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger
|
||||
polarity set to both rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */
|
||||
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected
|
||||
ADC channel */
|
||||
#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which
|
||||
the offset programmed will be applied (independently of channel mapped
|
||||
on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which
|
||||
the offset programmed will be applied (independently of channel mapped
|
||||
on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which
|
||||
the offset programmed will be applied (independently of channel mapped
|
||||
on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which
|
||||
the offset programmed will be applied (independently of channel mapped
|
||||
on ADC group regular or group injected) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */
|
||||
#define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
|
||||
#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
|
||||
#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
|
||||
#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled
|
||||
(ADC independent mode) */
|
||||
#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular
|
||||
simultaneous */
|
||||
#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined
|
||||
group regular interleaved */
|
||||
#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group
|
||||
injected simultaneous */
|
||||
#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group
|
||||
injected alternate trigger. Works only with external triggers (not internal
|
||||
SW start) */
|
||||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined
|
||||
group regular simultaneous + group injected simultaneous */
|
||||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined
|
||||
group regular simultaneous + group injected alternate trigger */
|
||||
#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined
|
||||
group regular interleaved + group injected simultaneous */
|
||||
|
||||
/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own
|
||||
DMA channel */
|
||||
#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC,
|
||||
DMA of ADC master) for 12 and 10 bits resolution */
|
||||
#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC,
|
||||
DMA of ADC master) for 8 and 6 bits resolution */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two
|
||||
sampling phases: 1 ADC clock cycle */
|
||||
#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 2 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 3 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 4 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 5 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 6 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 7 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 8 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 9 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 10 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 11 ADC clock cycles */
|
||||
#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two
|
||||
sampling phases: 12 ADC clock cycles */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on
|
||||
all STM32 devices) */
|
||||
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on
|
||||
all STM32 devices) */
|
||||
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_CFGR_fields ADCx CFGR fields
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
|
||||
ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
|
||||
ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
|
||||
ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
|
||||
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
|
||||
ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
|
||||
* @{
|
||||
*/
|
||||
#if defined(ADC_SMPR1_SMPPLUS)
|
||||
#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
|
||||
ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
|
||||
ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
|
||||
ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
|
||||
#else
|
||||
#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
|
||||
ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
|
||||
ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
|
||||
ADC_SMPR1_SMP0)
|
||||
#endif /* ADC_SMPR1_SMPPLUS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
|
||||
* @{
|
||||
*/
|
||||
/* ADC_CFGR fields of parameters that can be updated when no conversion
|
||||
(neither regular nor injected) is on-going */
|
||||
#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Force ADC instance in multimode mode independent (multimode disable).
|
||||
* @note This macro must be used only in case of transition from multimode
|
||||
* to mode independent and in case of unknown previous state,
|
||||
* to ensure ADC configuration is in mode independent.
|
||||
* @note Standard way of multimode configuration change is done from
|
||||
* HAL ADC handle of ADC master using function
|
||||
* "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
|
||||
* Usage of this macro is not the Standard way of multimode
|
||||
* configuration and can lead to have HAL ADC handles status
|
||||
* misaligned. Usage of this macro must be limited to cases
|
||||
* mentioned above.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
|
||||
LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
||||
/* code of final user. */
|
||||
|
||||
/**
|
||||
* @brief Test if conversion trigger of injected group is software start
|
||||
* or external trigger.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (software start) or RESET (external trigger).
|
||||
*/
|
||||
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
|
||||
|
||||
/**
|
||||
* @brief Check whether or not ADC is independent.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @note When multimode feature is not available, the macro always returns SET.
|
||||
* @retval SET (ADC is independent) or RESET (ADC is not).
|
||||
*/
|
||||
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define ADC_IS_INDEPENDENT(__HANDLE__) \
|
||||
( ( ( ((__HANDLE__)->Instance) == ADC5) \
|
||||
)? \
|
||||
SET \
|
||||
: \
|
||||
RESET \
|
||||
)
|
||||
#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
|
||||
#define ADC_IS_INDEPENDENT(__HANDLE__) \
|
||||
( ( ( ((__HANDLE__)->Instance) == ADC3) \
|
||||
)? \
|
||||
SET \
|
||||
: \
|
||||
RESET \
|
||||
)
|
||||
#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
|
||||
#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
|
||||
#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
|
||||
|
||||
/**
|
||||
* @brief Set the selected injected Channel rank.
|
||||
* @param __CHANNELNB__ Channel number.
|
||||
* @param __RANKNB__ Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \
|
||||
((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
|
||||
<< ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
|
||||
|
||||
/**
|
||||
* @brief Configure ADC injected context queue
|
||||
* @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \
|
||||
((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC discontinuous conversion mode for injected group
|
||||
* @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \
|
||||
((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC discontinuous conversion mode for regular group
|
||||
* @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \
|
||||
((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the number of discontinuous conversions for regular group.
|
||||
* @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \
|
||||
(((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the ADC auto delay mode.
|
||||
* @param __AUTOWAIT__ Auto delay bit enable or disable.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC continuous conversion mode.
|
||||
* @param __CONTINUOUS_MODE__ Continuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the ADC DMA continuous request.
|
||||
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
|
||||
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
/**
|
||||
* @brief Configure the ADC DMA continuous request for ADC multimode.
|
||||
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Shift the offset with respect to the selected ADC resolution.
|
||||
* @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
|
||||
* If resolution 12 bits, no shift.
|
||||
* If resolution 10 bits, shift of 2 ranks on the left.
|
||||
* If resolution 8 bits, shift of 4 ranks on the left.
|
||||
* If resolution 6 bits, shift of 6 ranks on the left.
|
||||
* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __OFFSET__ Value to be shifted
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
|
||||
((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
|
||||
|
||||
/**
|
||||
* @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
|
||||
* @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
|
||||
* If resolution 12 bits, no shift.
|
||||
* If resolution 10 bits, shift of 2 ranks on the left.
|
||||
* If resolution 8 bits, shift of 4 ranks on the left.
|
||||
* If resolution 6 bits, shift of 6 ranks on the left.
|
||||
* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __THRESHOLD__ Value to be shifted
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
|
||||
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
|
||||
|
||||
/**
|
||||
* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
|
||||
* @note Thresholds have to be left-aligned on bit 7.
|
||||
* If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
|
||||
* If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
|
||||
* If resolution 8 bits, no shift.
|
||||
* If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __THRESHOLD__ Value to be shifted
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
|
||||
((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \
|
||||
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
|
||||
((__THRESHOLD__) << 2UL) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @brief Clear Common Control Register.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
|
||||
ADC_CCR_CKMODE | \
|
||||
ADC_CCR_PRESC | \
|
||||
ADC_CCR_VBATSEL | \
|
||||
ADC_CCR_VSENSESEL | \
|
||||
ADC_CCR_VREFEN | \
|
||||
ADC_CCR_MDMA | \
|
||||
ADC_CCR_DMACFG | \
|
||||
ADC_CCR_DELAY | \
|
||||
ADC_CCR_DUAL)
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
/**
|
||||
* @brief Set handle instance of the ADC slave associated to the ADC master.
|
||||
* @param __HANDLE_MASTER__ ADC master handle.
|
||||
* @param __HANDLE_SLAVE__ ADC slave handle.
|
||||
* @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is
|
||||
* set to NULL.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
|
||||
( ((__HANDLE_MASTER__)->Instance == ADC1) ? \
|
||||
((__HANDLE_SLAVE__)->Instance = ADC2) \
|
||||
: \
|
||||
((__HANDLE_MASTER__)->Instance == ADC3) ? \
|
||||
((__HANDLE_SLAVE__)->Instance = ADC4) \
|
||||
: \
|
||||
((__HANDLE_SLAVE__)->Instance = NULL) \
|
||||
)
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
/**
|
||||
* @brief Set handle instance of the ADC slave associated to the ADC master.
|
||||
* @param __HANDLE_MASTER__ ADC master handle.
|
||||
* @param __HANDLE_SLAVE__ ADC slave handle.
|
||||
* @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set
|
||||
* to NULL.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
|
||||
( ((__HANDLE_MASTER__)->Instance == ADC1) ? \
|
||||
((__HANDLE_SLAVE__)->Instance = ADC2) \
|
||||
: \
|
||||
((__HANDLE_SLAVE__)->Instance = NULL) \
|
||||
)
|
||||
#endif /* STM32G4xx */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the temperature sensor.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
|
||||
*/
|
||||
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \
|
||||
((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
|
||||
#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the battery voltage VBAT.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
|
||||
*/
|
||||
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
|
||||
((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
|
||||
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
|
||||
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
|
||||
#endif /* STM32G4xx */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
|
||||
*/
|
||||
#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
|
||||
|
||||
/**
|
||||
* @brief Verify the length of scheduled injected conversions group.
|
||||
* @param __LENGTH__ number of programmed conversions.
|
||||
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions)
|
||||
* or RESET (__LENGTH__ is null or too large)
|
||||
*/
|
||||
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
|
||||
|
||||
/**
|
||||
* @brief Calibration factor size verification (7 bits maximum).
|
||||
* @param __CALIBRATION_FACTOR__ Calibration factor value.
|
||||
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
|
||||
*/
|
||||
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC channel setting.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @param __CHANNEL__ programmed ADC channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15)) || \
|
||||
((((__HANDLE__)->Instance) == ADC1) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
|
||||
((((__HANDLE__)->Instance) == ADC2) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_17) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
|
||||
((((__HANDLE__)->Instance) == ADC3) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_16) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
|
||||
((((__HANDLE__)->Instance) == ADC4) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_16) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
|
||||
((((__HANDLE__)->Instance) == ADC5) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_16) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
|
||||
#elif defined(STM32G471xx)
|
||||
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15)) || \
|
||||
((((__HANDLE__)->Instance) == ADC1) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
|
||||
((((__HANDLE__)->Instance) == ADC2) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_17) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
|
||||
((((__HANDLE__)->Instance) == ADC3) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_16) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
|
||||
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15)) || \
|
||||
((((__HANDLE__)->Instance) == ADC1) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
|
||||
((((__HANDLE__)->Instance) == ADC2) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_17) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))))
|
||||
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15)) || \
|
||||
((((__HANDLE__)->Instance) == ADC1) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
|
||||
((((__HANDLE__)->Instance) == ADC2) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_17) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
|
||||
((((__HANDLE__)->Instance) == ADC3) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_16) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
|
||||
#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC channel setting in differential mode.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @param __CHANNEL__ programmed ADC channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14)) || \
|
||||
((((__HANDLE__)->Instance) == ADC1) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5))) || \
|
||||
((((__HANDLE__)->Instance) == ADC2) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13))) || \
|
||||
((((__HANDLE__)->Instance) == ADC3) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15))) || \
|
||||
((((__HANDLE__)->Instance) == ADC4) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15))) || \
|
||||
((((__HANDLE__)->Instance) == ADC5) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15))) )
|
||||
#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
|
||||
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14)) || \
|
||||
((((__HANDLE__)->Instance) == ADC2) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13))) || \
|
||||
((((__HANDLE__)->Instance) == ADC3) && \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15))) )
|
||||
#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
|
||||
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14)) || \
|
||||
((((__HANDLE__)->Instance) == ADC2) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13))) )
|
||||
#endif /* STM32G4xx */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC single-ended input or differential mode setting.
|
||||
* @param __SING_DIFF__ programmed channel setting.
|
||||
* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
|
||||
((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC offset management setting.
|
||||
* @param __OFFSET_NUMBER__ ADC offset management.
|
||||
* @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC offset sign setting.
|
||||
* @param __OFFSET_SIGN__ ADC offset sign.
|
||||
* @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
|
||||
((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC injected channel setting.
|
||||
* @param __CHANNEL__ programmed ADC injected channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
|
||||
((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
|
||||
((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
|
||||
((__CHANNEL__) == ADC_INJECTED_RANK_4) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC injected conversions external trigger.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @param __INJTRIG__ programmed ADC injected conversions external trigger.
|
||||
* @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
|
||||
*/
|
||||
#if defined(STM32G474xx) || defined(STM32G484xx)
|
||||
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
|
||||
((((__HANDLE__)->Instance == ADC1) || \
|
||||
((__HANDLE__)->Instance == ADC2)) && \
|
||||
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
|
||||
((((__HANDLE__)->Instance == ADC3) || \
|
||||
((__HANDLE__)->Instance == ADC4) || \
|
||||
((__HANDLE__)->Instance == ADC5)) && \
|
||||
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
|
||||
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
|
||||
#elif defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
|
||||
((((__HANDLE__)->Instance == ADC1) || \
|
||||
((__HANDLE__)->Instance == ADC2)) && \
|
||||
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
|
||||
((((__HANDLE__)->Instance == ADC3) || \
|
||||
((__HANDLE__)->Instance == ADC4) || \
|
||||
((__HANDLE__)->Instance == ADC5)) && \
|
||||
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
|
||||
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
|
||||
#elif defined(STM32G471xx)
|
||||
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
|
||||
((((__HANDLE__)->Instance == ADC1) || \
|
||||
((__HANDLE__)->Instance == ADC2)) && \
|
||||
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
|
||||
((((__HANDLE__)->Instance == ADC3)) && \
|
||||
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
|
||||
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
|
||||
#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
|
||||
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
|
||||
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
|
||||
#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
|
||||
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
|
||||
((((__HANDLE__)->Instance == ADC1) || \
|
||||
((__HANDLE__)->Instance == ADC2)) && \
|
||||
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
|
||||
(((__HANDLE__)->Instance == ADC3) && \
|
||||
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
|
||||
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
|
||||
#endif /* STM32G4xx */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC edge trigger setting for injected group.
|
||||
* @param __EDGE__ programmed ADC edge trigger setting.
|
||||
* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
|
||||
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
/**
|
||||
* @brief Verify the ADC multimode setting.
|
||||
* @param __MODE__ programmed ADC multimode setting.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
|
||||
((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
|
||||
((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
|
||||
((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
|
||||
((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
|
||||
((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
|
||||
((__MODE__) == ADC_DUALMODE_INTERL) || \
|
||||
((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC multimode DMA access setting.
|
||||
* @param __MODE__ programmed ADC multimode DMA access setting.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
|
||||
((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
|
||||
((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC multimode delay setting.
|
||||
* @param __DELAY__ programmed ADC multimode delay setting.
|
||||
* @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC analog watchdog setting.
|
||||
* @param __WATCHDOG__ programmed ADC analog watchdog setting.
|
||||
* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC analog watchdog mode setting.
|
||||
* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
|
||||
* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC analog watchdog filtering setting.
|
||||
* @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
|
||||
* @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \
|
||||
(((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \
|
||||
((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \
|
||||
((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \
|
||||
((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \
|
||||
((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \
|
||||
((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \
|
||||
((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \
|
||||
((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) )
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC conversion (regular or injected or both).
|
||||
* @param __CONVERSION__ ADC conversion group.
|
||||
* @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
|
||||
((__CONVERSION__) == ADC_INJECTED_GROUP) || \
|
||||
((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC event type.
|
||||
* @param __EVENT__ ADC event.
|
||||
* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD2_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD3_EVENT) || \
|
||||
((__EVENT__) == ADC_OVR_EVENT) || \
|
||||
((__EVENT__) == ADC_JQOVF_EVENT) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling ratio.
|
||||
* @param __RATIO__ programmed ADC oversampling ratio.
|
||||
* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling shift.
|
||||
* @param __SHIFT__ programmed ADC oversampling shift.
|
||||
* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling triggered mode.
|
||||
* @param __MODE__ programmed ADC oversampling triggered mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
|
||||
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
|
||||
* @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
|
||||
((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
|
||||
|
||||
/**
|
||||
* @brief Verify the DFSDM mode configuration.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
|
||||
* this reason, the input parameter is the ADC handle and not the configuration parameter
|
||||
* directly.
|
||||
* @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
|
||||
*/
|
||||
#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
|
||||
|
||||
/**
|
||||
* @brief Return the DFSDM configuration mode.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
|
||||
* For this reason, the input parameter is the ADC handle and not the configuration parameter
|
||||
* directly.
|
||||
* @retval DFSDM configuration mode
|
||||
*/
|
||||
#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
/* ADC calibration */
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
|
||||
uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
|
||||
uint32_t CalibrationFactor);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
|
||||
|
||||
/* Non-blocking mode: Interruption */
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
|
||||
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
/* ADC multimode */
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
|
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
|
||||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
|
||||
|
||||
/* ADC group regular conversions stop */
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
|
||||
const ADC_InjectionConfTypeDef *pConfigInjected);
|
||||
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
|
||||
const ADC_MultiModeTypeDef *pMultimode);
|
||||
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||
|
||||
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_ADC_EX_H */
|
||||
1404
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h
Normal file
1404
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h
Normal file
@@ -0,0 +1,1404 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_comp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of COMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_COMP_H
|
||||
#define STM32G4xx_HAL_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
#include "stm32g4xx_ll_exti.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Types COMP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
|
||||
This parameter can be a value of @ref COMP_InputPlus */
|
||||
|
||||
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
|
||||
This parameter can be a value of @ref COMP_InputMinus */
|
||||
|
||||
uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
|
||||
This parameter can be a value of @ref COMP_Hysteresis */
|
||||
|
||||
uint32_t OutputPol; /*!< Set comparator output polarity.
|
||||
This parameter can be a value of @ref COMP_OutputPolarity */
|
||||
|
||||
uint32_t BlankingSrce; /*!< Set comparator blanking source.
|
||||
This parameter can be a value of @ref COMP_BlankingSrce */
|
||||
|
||||
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
|
||||
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
|
||||
|
||||
} COMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL COMP state machine: HAL COMP states definition
|
||||
*/
|
||||
#define COMP_STATE_BITFIELD_LOCK (0x10U)
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */
|
||||
HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
|
||||
HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
|
||||
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
|
||||
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
|
||||
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
|
||||
} HAL_COMP_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief COMP Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __COMP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
{
|
||||
COMP_TypeDef *Instance; /*!< Register base address */
|
||||
COMP_InitTypeDef Init; /*!< COMP required parameters */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
|
||||
__IO uint32_t ErrorCode; /*!< COMP error code */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
|
||||
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
} COMP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL COMP Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
|
||||
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
|
||||
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
|
||||
} HAL_COMP_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL COMP Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
|
||||
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Constants COMP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Error_Code COMP Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
|
||||
* @{
|
||||
*/
|
||||
#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
|
||||
#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL) /*!< Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
|
||||
* @{
|
||||
*/
|
||||
#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
|
||||
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
|
||||
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
|
||||
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
|
||||
#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
|
||||
#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet */
|
||||
#define COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
|
||||
#define COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet */
|
||||
#define COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
|
||||
#define COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
|
||||
#define COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */
|
||||
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
|
||||
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Hysteresis COMP hysteresis
|
||||
* @{
|
||||
*/
|
||||
#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
|
||||
#define COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0) /*!< Hysteresis level 10mV */
|
||||
#define COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 ) /*!< Hysteresis level 20mV */
|
||||
#define COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 30mV */
|
||||
#define COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 ) /*!< Hysteresis level 40mV */
|
||||
#define COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0) /*!< Hysteresis level 50mV */
|
||||
#define COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 ) /*!< Hysteresis level 60mV */
|
||||
#define COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 70mV */
|
||||
#define COMP_HYSTERESIS_LOW COMP_HYSTERESIS_10MV /*!< Hysteresis level low */
|
||||
#define COMP_HYSTERESIS_MEDIUM COMP_HYSTERESIS_40MV /*!< Hysteresis level medium */
|
||||
#define COMP_HYSTERESIS_HIGH COMP_HYSTERESIS_70MV /*!< Hysteresis level high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPolarity COMP output Polarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
|
||||
#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_BlankingSrce COMP blanking source
|
||||
* @{
|
||||
*/
|
||||
#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!<Comparator output without blanking */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
|
||||
#define COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM20 OC5 (Common to all COMP instances) */
|
||||
#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM15 OC1 (Common to all COMP instances) */
|
||||
#define COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM4 OC3 (Common to all COMP instances) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel COMP Output Level
|
||||
* @{
|
||||
*/
|
||||
/* Note: Comparator output level values are fixed to "0" and "1", */
|
||||
/* corresponding COMP register bit is managed by HAL function to match */
|
||||
/* with these values (independently of bit position in register). */
|
||||
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the input plus is at a lower voltage than the input minus */
|
||||
#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the input plus is at a higher voltage than the input minus */
|
||||
#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
|
||||
* @{
|
||||
*/
|
||||
#define COMP_TRIGGERMODE_NONE (0x00000000UL) /*!< Comparator output triggering no External Interrupt Line */
|
||||
#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
|
||||
#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
|
||||
#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
|
||||
#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
|
||||
#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
|
||||
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Macros COMP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Handle_Management COMP Handle Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset COMP handle state.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
|
||||
|
||||
/**
|
||||
* @brief Lock the specified comparator configuration.
|
||||
* @note Using this macro induce HAL COMP handle state machine being no
|
||||
* more in line with COMP instance state.
|
||||
* To keep HAL COMP handle state machine updated, it is recommended
|
||||
* to use function "HAL_COMP_Lock')".
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified comparator is locked.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
|
||||
*/
|
||||
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exti_Management COMP external interrupt line management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP1 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP1 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP1 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP2 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP2 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP2 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP3 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP3 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP3 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP3 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP3 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
|
||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP3 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
|
||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3);\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP3 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP3 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP3 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP3 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP3 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP3 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP3 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP3)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP4 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP4 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP4 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP4 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP4 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
|
||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP4 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
|
||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4);\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP4 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP4 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP4 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP4 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP4 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP4 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP4 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4)
|
||||
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
/**
|
||||
* @brief Enable the COMP5 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP5 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP5 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP5 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP5 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
|
||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP5 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
|
||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5);\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP5 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP5 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP5 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP5 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP5 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP5 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP5 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP5)
|
||||
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
/**
|
||||
* @brief Enable the COMP6 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP6 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP6 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP6 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP6 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \
|
||||
LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP6 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6);\
|
||||
LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6);\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP6 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP6 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP6 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP6 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP6 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP6 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP6 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP6)
|
||||
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
/**
|
||||
* @brief Enable the COMP7 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP7 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP7 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP7 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP7 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \
|
||||
LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP7 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7);\
|
||||
LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7);\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP7 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP7 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP7 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP7 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP7 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP7 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP7 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP7)
|
||||
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Constants COMP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#define COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29) /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#define COMP_EXTI_LINE_COMP4 (LL_EXTI_LINE_30) /*!< EXTI line 30 connected to COMP4 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC)
|
||||
#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#define COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29) /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx || STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G491xx || STM32G4A1xx */
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define COMP_EXTI_LINE_COMP5 (LL_EXTI_LINE_31) /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#define COMP_EXTI_LINE_COMP6 (LL_EXTI_LINE_32) /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#define COMP_EXTI_LINE_COMP7 (LL_EXTI_LINE_33) /*!< EXTI line 33 connected to COMP7 output. Note: For COMPx instance availability, please refer to datasheet */
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */
|
||||
#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */
|
||||
#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */
|
||||
#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Macros COMP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Get the specified EXTI line for a comparator instance.
|
||||
* @param __INSTANCE__ specifies the COMP instance.
|
||||
* @retval value of @ref COMP_ExtiLine
|
||||
*/
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
|
||||
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
|
||||
:((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
|
||||
:((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 \
|
||||
:((__INSTANCE__) == COMP5) ? COMP_EXTI_LINE_COMP5 \
|
||||
:((__INSTANCE__) == COMP6) ? COMP_EXTI_LINE_COMP6 \
|
||||
: COMP_EXTI_LINE_COMP7)
|
||||
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
|
||||
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
|
||||
:((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
|
||||
: COMP_EXTI_LINE_COMP4)
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC)
|
||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
|
||||
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
|
||||
: COMP_EXTI_LINE_COMP3)
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
|
||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
|
||||
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
|
||||
(((__COMP_INSTANCE__) == COMP1) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP2) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP3) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP4) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP5) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP6) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP7) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \
|
||||
))
|
||||
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
|
||||
(((__COMP_INSTANCE__) == COMP1) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP2) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP3) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP4) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
|
||||
))
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC)
|
||||
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
|
||||
(((__COMP_INSTANCE__) == COMP1) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP2) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
|
||||
) || \
|
||||
(((__COMP_INSTANCE__) == COMP3) && \
|
||||
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
|
||||
))
|
||||
#endif
|
||||
|
||||
|
||||
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_10MV) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_20MV) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_30MV) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_40MV) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_50MV) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_60MV) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_70MV) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
|
||||
|
||||
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
|
||||
((__POL__) == COMP_OUTPUTPOL_INVERTED))
|
||||
|
||||
/* Note: Output blanking source depends on COMP instances */
|
||||
/* Better use IS_COMP_BLANKINGSRC_INSTANCE instead */
|
||||
/* Macro kept for compatibility with other STM32 series */
|
||||
#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
|
||||
)
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
|
||||
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
|
||||
((((__INSTANCE__) == COMP1) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP2) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP3) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP4) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP5) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP6) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP7) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7))) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
|
||||
)
|
||||
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
|
||||
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
|
||||
((((__INSTANCE__) == COMP1) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP2) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP3) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP4) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
|
||||
)
|
||||
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
|
||||
((((__INSTANCE__) == COMP1) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP2) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP3) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP4) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
|
||||
)
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC)
|
||||
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
|
||||
((((__INSTANCE__) == COMP1) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP2) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == COMP3) && \
|
||||
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
|
||||
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
|
||||
)
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
|
||||
|
||||
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
|
||||
|
||||
#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
|
||||
((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup COMP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
|
||||
pCOMP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup COMP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
/** @addtogroup COMP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp);
|
||||
/* Callback in interrupt mode */
|
||||
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions **************************************************/
|
||||
/** @addtogroup COMP_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_COMP_H */
|
||||
380
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_conf_template.h
Normal file
380
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_conf_template.h
Normal file
@@ -0,0 +1,380 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32g4xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_CONF_H
|
||||
#define STM32G4xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_COMP_MODULE_ENABLED
|
||||
#define HAL_CORDIC_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_FDCAN_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_FMAC_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_HRTIM_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_OPAMP_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_QSPI_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
|
||||
/* ########################## Register Callbacks selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules where register callback can be used
|
||||
*/
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG.
|
||||
* This internal oscillator is mainly dedicated to provide a high precision clock to
|
||||
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
|
||||
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
|
||||
* which is subject to manufacturing process variations.
|
||||
*/
|
||||
#if !defined (HSI48_VALUE)
|
||||
#define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz.
|
||||
The real value my vary depending on manufacturing process variations.*/
|
||||
#endif /* HSI48_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
/*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations in voltage and temperature.*/
|
||||
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S and SAI peripherals
|
||||
* This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE (48000UL) /*!< Value of the External clock source in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY (0x0FUL) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 0U
|
||||
#define INSTRUCTION_CACHE_ENABLE 1U
|
||||
#define DATA_CACHE_ENABLE 1U
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORDIC_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_cordic.h"
|
||||
#endif /* HAL_CORDIC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FDCAN_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_fdcan.h"
|
||||
#endif /* HAL_FDCAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FMAC_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_fmac.h"
|
||||
#endif /* HAL_FMAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HRTIM_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_hrtim.h"
|
||||
#endif /* HAL_HRTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_opamp.h"
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32g4xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_CONF_H */
|
||||
|
||||
|
||||
620
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h
Normal file
620
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h
Normal file
@@ -0,0 +1,620 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_cordic.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the CORDIC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_CORDIC_H
|
||||
#define STM32G4xx_HAL_CORDIC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
#if defined(CORDIC)
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Types CORDIC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CORDIC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CORDIC_STATE_RESET = 0x00U, /*!< CORDIC not yet initialized or disabled */
|
||||
HAL_CORDIC_STATE_READY = 0x01U, /*!< CORDIC initialized and ready for use */
|
||||
HAL_CORDIC_STATE_BUSY = 0x02U, /*!< CORDIC internal process is ongoing */
|
||||
HAL_CORDIC_STATE_ERROR = 0x03U /*!< CORDIC error state */
|
||||
} HAL_CORDIC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CORDIC Handle Structure definition
|
||||
*/
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
typedef struct __CORDIC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
{
|
||||
CORDIC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
const int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
|
||||
|
||||
int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */
|
||||
|
||||
uint32_t NbCalcToOrder; /*!< Remaining number of calculation to order */
|
||||
|
||||
uint32_t NbCalcToGet; /*!< Remaining number of calculation result to get */
|
||||
|
||||
uint32_t DMADirection; /*!< Direction of CORDIC DMA transfers */
|
||||
|
||||
DMA_HandleTypeDef *hdmaIn; /*!< CORDIC peripheral input data DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaOut; /*!< CORDIC peripheral output data DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CORDIC locking object */
|
||||
|
||||
__IO HAL_CORDIC_StateTypeDef State; /*!< CORDIC state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CORDIC peripheral error code
|
||||
This parameter can be a value of @ref CORDIC_Error_Code */
|
||||
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
void (* ErrorCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC error callback */
|
||||
void (* CalculateCpltCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC calculate complete callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
|
||||
|
||||
} CORDIC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CORDIC Config Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Function; /*!< Function
|
||||
This parameter can be a value of @ref CORDIC_Function */
|
||||
|
||||
uint32_t Scale; /*!< Scaling factor
|
||||
This parameter can be a value of @ref CORDIC_Scale */
|
||||
|
||||
uint32_t InSize; /*!< Width of input data
|
||||
This parameter can be a value of @ref CORDIC_In_Size */
|
||||
|
||||
uint32_t OutSize; /*!< Width of output data
|
||||
This parameter can be a value of @ref CORDIC_Out_Size */
|
||||
|
||||
uint32_t NbWrite; /*!< Number of 32-bit write expected for one calculation
|
||||
This parameter can be a value of @ref CORDIC_Nb_Write */
|
||||
|
||||
uint32_t NbRead; /*!< Number of 32-bit read expected after one calculation
|
||||
This parameter can be a value of @ref CORDIC_Nb_Read */
|
||||
|
||||
uint32_t Precision; /*!< Number of cycles for calculation
|
||||
This parameter can be a value of @ref CORDIC_Precision_In_Cycles_Number */
|
||||
|
||||
} CORDIC_ConfigTypeDef;
|
||||
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
/**
|
||||
* @brief HAL CORDIC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CORDIC_ERROR_CB_ID = 0x00U, /*!< CORDIC error callback ID */
|
||||
HAL_CORDIC_CALCULATE_CPLT_CB_ID = 0x01U, /*!< CORDIC calculate complete callback ID */
|
||||
|
||||
HAL_CORDIC_MSPINIT_CB_ID = 0x02U, /*!< CORDIC MspInit callback ID */
|
||||
HAL_CORDIC_MSPDEINIT_CB_ID = 0x03U, /*!< CORDIC MspDeInit callback ID */
|
||||
|
||||
} HAL_CORDIC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CORDIC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< pointer to a CORDIC callback function */
|
||||
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Error_Code CORDIC Error code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Wrong parameter error */
|
||||
#define HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U) /*!< Peripheral not ready */
|
||||
#define HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
|
||||
#define HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA error */
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Function CORDIC Function
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
|
||||
#define CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
|
||||
#define CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
|
||||
#define CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
|
||||
#define CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
|
||||
#define CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
|
||||
#define CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
|
||||
#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
|
||||
#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
|
||||
#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Precision_In_Cycles_Number CORDIC Precision in Cycles Number
|
||||
* @{
|
||||
*/
|
||||
/* Note: 1 cycle corresponds to 4 algorithm iterations */
|
||||
#define CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
|
||||
#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
|
||||
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
|
||||
#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
|
||||
#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
|
||||
#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
|
||||
#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
|
||||
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
|
||||
|CORDIC_CSR_PRECISION_0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Scale CORDIC Scaling factor
|
||||
* @{
|
||||
*/
|
||||
/* Scale factor value 'n' implies that the input data have been multiplied
|
||||
by a factor 2exp(-n), and/or the output data need to be multiplied by 2exp(n). */
|
||||
#define CORDIC_SCALE_0 (0x00000000U)
|
||||
#define CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
|
||||
#define CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
|
||||
#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
|
||||
#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
|
||||
#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Interrupts_Enable CORDIC Interrupts Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_DMAR DMA Read Request Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_DMAW DMA Write Request Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Nb_Write CORDIC Number of 32-bit write required for one calculation
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
|
||||
32-bit data input (Q1.31 format), or two 16-bit
|
||||
data input (Q1.15 format) packed in one 32 bits
|
||||
Data */
|
||||
#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
|
||||
(Q1.31 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Nb_Read CORDIC Number of 32-bit read required after one calculation
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
|
||||
32-bit data output (Q1.31 format), or two 16-bit
|
||||
data output (Q1.15 format) packed in one 32 bits
|
||||
Data */
|
||||
#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
|
||||
(Q1.31 format) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_In_Size CORDIC input data size
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
|
||||
#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Out_Size CORDIC Results Size
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
|
||||
#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_Flags CORDIC status flags
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORDIC_DMA_Direction CORDIC DMA direction
|
||||
* @{
|
||||
*/
|
||||
#define CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U) /*!< DMA direction : none */
|
||||
#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */
|
||||
#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */
|
||||
#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Exported_Macros CORDIC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CORDIC handle state.
|
||||
* @param __HANDLE__ CORDIC handle
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
|
||||
#endif /*USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the CORDIC interrupt when result is ready
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_IT_IEN Enable Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the CORDIC interrupt
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC Interrupt.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_IT_IEN Enable Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified CORDIC interrupt occurred or not.
|
||||
Dummy macro as no interrupt status flag.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC interrupt to check
|
||||
* @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
|
||||
*/
|
||||
#define __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
|
||||
|
||||
/** @brief Clear specified CORDIC interrupt status. Dummy macro as no
|
||||
interrupt status flag.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC interrupt to clear
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
|
||||
|
||||
/** @brief Check whether the specified CORDIC status flag is set or not.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __FLAG__ CORDIC flag to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
|
||||
* @retval SET (flag is set) or RESET (flag is reset)
|
||||
*/
|
||||
#define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear specified CORDIC status flag. Dummy macro as no
|
||||
flag can be cleared.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __FLAG__ CORDIC flag to clear
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
|
||||
|
||||
/** @brief Check whether the specified CORDIC interrupt is enabled or not.
|
||||
* @param __HANDLE__ CORDIC handle.
|
||||
* @param __INTERRUPT__ CORDIC interrupt to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CORDIC_IT_IEN Enable Interrupt
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORDIC_Private_Macros CORDIC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC function.
|
||||
* @param __FUNCTION__ Name of the function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == CORDIC_FUNCTION_COSINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_SINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_PHASE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_MODULUS) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_HSINE) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG) || \
|
||||
((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC precision.
|
||||
* @param __PRECISION__ CORDIC Precision in Cycles Number.
|
||||
* @retval SET (__PRECISION__ is a valid value) or RESET (__PRECISION__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_PRECISION(__PRECISION__) (((__PRECISION__) == CORDIC_PRECISION_1CYCLE) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_2CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_3CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_4CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_5CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_6CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_7CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_8CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_9CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \
|
||||
((__PRECISION__) == CORDIC_PRECISION_15CYCLES))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC scaling factor.
|
||||
* @param __SCALE__ Number of cycles for calculation, 1 cycle corresponding to 4 algorithm iterations.
|
||||
* @retval SET (__SCALE__ is a valid value) or RESET (__SCALE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_SCALE(__SCALE__) (((__SCALE__) == CORDIC_SCALE_0) || \
|
||||
((__SCALE__) == CORDIC_SCALE_1) || \
|
||||
((__SCALE__) == CORDIC_SCALE_2) || \
|
||||
((__SCALE__) == CORDIC_SCALE_3) || \
|
||||
((__SCALE__) == CORDIC_SCALE_4) || \
|
||||
((__SCALE__) == CORDIC_SCALE_5) || \
|
||||
((__SCALE__) == CORDIC_SCALE_6) || \
|
||||
((__SCALE__) == CORDIC_SCALE_7))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC number of 32-bits write expected for one calculation.
|
||||
* @param __NBWRITE__ Number of 32-bits write expected for one calculation.
|
||||
* @retval SET (__NBWRITE__ is a valid value) or RESET (__NBWRITE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_NBWRITE(__NBWRITE__) (((__NBWRITE__) == CORDIC_NBWRITE_1) || \
|
||||
((__NBWRITE__) == CORDIC_NBWRITE_2))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC number of 32-bits read expected after one calculation.
|
||||
* @param __NBREAD__ Number of 32-bits read expected after one calculation.
|
||||
* @retval SET (__NBREAD__ is a valid value) or RESET (__NBREAD__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_NBREAD(__NBREAD__) (((__NBREAD__) == CORDIC_NBREAD_1) || \
|
||||
((__NBREAD__) == CORDIC_NBREAD_2))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC input data size for one calculation.
|
||||
* @param __INSIZE__ input data size for one calculation.
|
||||
* @retval SET (__INSIZE__ is a valid value) or RESET (__INSIZE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_INSIZE(__INSIZE__) (((__INSIZE__) == CORDIC_INSIZE_32BITS) || \
|
||||
((__INSIZE__) == CORDIC_INSIZE_16BITS))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC output data size for one calculation.
|
||||
* @param __OUTSIZE__ output data size for one calculation.
|
||||
* @retval SET (__OUTSIZE__ is a valid value) or RESET (__OUTSIZE__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_OUTSIZE(__OUTSIZE__) (((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS) || \
|
||||
((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS))
|
||||
|
||||
/**
|
||||
* @brief Verify the CORDIC DMA transfer Direction.
|
||||
* @param __DMADIR__ DMA transfer direction.
|
||||
* @retval SET (__DMADIR__ is a valid value) or RESET (__DMADIR__ is invalid)
|
||||
*/
|
||||
#define IS_CORDIC_DMA_DIRECTION(__DMADIR__) (((__DMADIR__) == CORDIC_DMA_DIR_IN) || \
|
||||
((__DMADIR__) == CORDIC_DMA_DIR_OUT) || \
|
||||
((__DMADIR__) == CORDIC_DMA_DIR_IN_OUT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic);
|
||||
HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic);
|
||||
void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic);
|
||||
void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic);
|
||||
|
||||
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
|
||||
pCORDIC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc);
|
||||
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
|
||||
uint32_t NbCalc, uint32_t DMADirection);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Callback functions *********************************************************/
|
||||
void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic);
|
||||
void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* IRQ handler management *****************************************************/
|
||||
void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORDIC_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic);
|
||||
uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CORDIC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_CORDIC_H */
|
||||
421
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h
Normal file
421
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h
Normal file
@@ -0,0 +1,421 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32G4xx_HAL_CORTEX_H
|
||||
#define __STM32G4xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||
}MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bit for pre-emption priority,
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bit for pre-emption priority,
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority,
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority,
|
||||
1 bit for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority,
|
||||
0 bit for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
|
||||
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
|
||||
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
|
||||
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
|
||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01)
|
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
|
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
|
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
|
||||
#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
|
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
|
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
|
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
|
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
|
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
|
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
|
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
|
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
|
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
|
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
|
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
|
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
|
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
|
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
|
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
|
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
|
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
|
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
|
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
|
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
|
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
|
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
|
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
|
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
|
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
|
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
|
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
|
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
|
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
|
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
|
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
|
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
|
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
|
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
|
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
|
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
|
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
|
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
|
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and Configuration functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2) || \
|
||||
((TYPE) == MPU_TEX_LEVEL4))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32G4xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
342
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h
Normal file
342
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h
Normal file
@@ -0,0 +1,342 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_CRC_H
|
||||
#define STM32G4xx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
} HAL_CRC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
|
||||
X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
|
||||
CRCLength fields must be set. */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
|
||||
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal,
|
||||
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
|
||||
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
|
||||
DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
||||
Value can be either one of
|
||||
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
|
||||
|
||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
||||
is set to DEFAULT_INIT_VALUE_ENABLE. */
|
||||
|
||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
|
||||
becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
|
||||
0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
|
||||
becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
|
||||
into 0x22CC4488 */
|
||||
} CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
|
||||
(8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
|
||||
half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
|
||||
(32-bit data)
|
||||
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
|
||||
error must occur if InputBufferFormat is not one of the three values listed
|
||||
above */
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
|
||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
|
||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
|
||||
* @{
|
||||
*/
|
||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
||||
* the CRC APIs to provide a correct result */
|
||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
|
||||
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
|
||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
|
||||
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state.
|
||||
* @param __HANDLE__ CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Set CRC INIT non-default value
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __INIT__ 32-bit initial value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __VALUE__ Value to be stored in the ID register
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Return the data stored in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval Value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_16B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_8B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_7B))
|
||||
|
||||
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRC HAL Extended module */
|
||||
#include "stm32g4xx_hal_crc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_CRC_H */
|
||||
150
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc_ex.h
Normal file
150
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc_ex.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_CRC_EX_H
|
||||
#define STM32G4xx_HAL_CRC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
|
||||
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
||||
|
||||
/**
|
||||
* @brief Unset CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
||||
|
||||
/**
|
||||
* @brief Set CRC non-default polynomial
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
|
||||
|
||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
|
||||
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_CRC_EX_H */
|
||||
650
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp.h
Normal file
650
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp.h
Normal file
@@ -0,0 +1,650 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_CRYP_H
|
||||
#define STM32G4xx_HAL_CRYP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(AES)
|
||||
|
||||
/** @defgroup CRYP CRYP
|
||||
* @brief CRYP HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRYP Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
||||
128 or 256 bit key length in TinyAES
|
||||
This parameter can be a value of @ref CRYP_Key_Size */
|
||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
||||
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
|
||||
counter in CTR mode */
|
||||
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
|
||||
AES Algorithm ECB/CBC/CTR/GCM or CCM
|
||||
This parameter can be a value of @ref CRYP_Algorithm_Mode */
|
||||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
||||
GCM : also known as Additional Authentication Data
|
||||
CCM : named B1 composed of the associated data length and Associated Data. */
|
||||
uint32_t HeaderSize; /*!< The size of header buffer */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processings.
|
||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
|
||||
} CRYP_ConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRYP State Structure definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
|
||||
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
|
||||
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
} HAL_CRYP_STATETypeDef;
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
/**
|
||||
* @brief HAL CRYP mode suspend definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */
|
||||
HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */
|
||||
} HAL_SuspendTypeDef;
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
/**
|
||||
* @brief CRYP handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __CRYP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
{
|
||||
AES_TypeDef *Instance; /*!< AES Register base address */
|
||||
|
||||
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
|
||||
|
||||
FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
|
||||
This parameter can be a value of ENABLE/DISABLE */
|
||||
|
||||
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
__IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
|
||||
|
||||
__IO uint16_t CrypInCount; /*!< Counter of input data in words */
|
||||
|
||||
__IO uint16_t CrypOutCount; /*!< Counter of output data in words */
|
||||
|
||||
uint16_t Size; /*!< Length of input data */
|
||||
|
||||
uint32_t Phase; /*!< CRYP peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRYP locking object */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
|
||||
|
||||
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
|
||||
configuration can be skipped */
|
||||
|
||||
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
|
||||
for a single signature computation after several
|
||||
messages processing */
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
|
||||
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
|
||||
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
|
||||
__IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
|
||||
|
||||
CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing is suspended */
|
||||
|
||||
uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing is suspended */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing is suspended */
|
||||
|
||||
uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing is suspended */
|
||||
|
||||
uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */
|
||||
|
||||
uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */
|
||||
|
||||
uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
|
||||
|
||||
uint32_t SUSPxR_saved[8]; /*!< copy of suspension registers */
|
||||
|
||||
uint32_t CR_saved; /*!< copy of CRYP control register when processing is suspended*/
|
||||
|
||||
uint32_t Key_saved[8]; /*!< copy of key registers */
|
||||
|
||||
uint16_t Size_saved; /*!< copy of input buffer size */
|
||||
|
||||
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
|
||||
|
||||
uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
|
||||
|
||||
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
|
||||
|
||||
FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
|
||||
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
} CRYP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
|
||||
* @brief HAL CRYP Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_MSPINIT_CB_ID = 0x00U, /*!< CRYP MspInit callback ID */
|
||||
HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, /*!< CRYP MspDeInit callback ID */
|
||||
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Input FIFO transfer completed callback ID */
|
||||
HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U, /*!< CRYP Output FIFO transfer completed callback ID */
|
||||
HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP Error callback ID */
|
||||
} HAL_CRYP_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
|
||||
* @brief HAL CRYP Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Error_Definition CRYP Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
|
||||
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
|
||||
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
|
||||
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
|
||||
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
|
||||
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
|
||||
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
|
||||
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
|
||||
#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
|
||||
#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
|
||||
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Size CRYP Key Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
|
||||
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
|
||||
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
|
||||
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
|
||||
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Interrupt CRYP Interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
|
||||
#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
|
||||
#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
|
||||
#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Flags CRYP Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* status flags */
|
||||
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
|
||||
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
|
||||
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
|
||||
/* clearing flags */
|
||||
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
|
||||
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
|
||||
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRYP handle state
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL;\
|
||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
||||
}while(0U)
|
||||
#else
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the CRYP peripheral.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
|
||||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP status flag is set or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
|
||||
* or a key preparation (for AES decryption).
|
||||
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
|
||||
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
|
||||
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
|
||||
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
|
||||
* @arg CRYP_FLAG_OFFU: Output FIFO is full
|
||||
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define CRYP_FLAG_MASK 0x0000001FU
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the CRYP pending status flag.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
|
||||
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP interrupt source to check
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @retval State of interruption (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR &\
|
||||
(__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt is set or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt to check.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
|
||||
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP interrupt.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the CRYP interrupt.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRYP HAL Extended module */
|
||||
#include "stm32g4xx_hal_cryp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
|
||||
pCRYP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
|
||||
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* encryption/decryption ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt Handler functions **********************************************/
|
||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
|
||||
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Macros CRYP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
|
||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_CTR) || \
|
||||
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
|
||||
((ALGORITHM) == CRYP_AES_CCM))
|
||||
|
||||
|
||||
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
|
||||
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_16B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_8B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_1B))
|
||||
|
||||
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
|
||||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
|
||||
|
||||
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
|
||||
(((((ALGO) == CRYP_AES_CTR)) && \
|
||||
((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
|
||||
(((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
|
||||
(((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
|
||||
((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Constants CRYP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Defines CRYP Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Variables CRYP Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Functions CRYP Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* AES */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_CRYP_H */
|
||||
130
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp_ex.h
Normal file
130
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp_ex.h
Normal file
@@ -0,0 +1,130 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_cryp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYPEx HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_CRYP_EX_H
|
||||
#define STM32G4xx_HAL_CRYP_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(AES)
|
||||
|
||||
/** @defgroup CRYPEx CRYPEx
|
||||
* @brief CRYP Extension HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* AES */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_CRYP_EX_H */
|
||||
638
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h
Normal file
638
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h
Normal file
@@ -0,0 +1,638 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_DAC_H
|
||||
#define STM32G4xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
|
||||
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
|
||||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||
|
||||
} HAL_DAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __DAC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
} DAC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration sample and hold Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel.
|
||||
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
|
||||
|
||||
uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel
|
||||
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
|
||||
|
||||
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
|
||||
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
|
||||
} DAC_SampleAndHoldConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode
|
||||
This parameter can be a value of @ref DAC_HighFrequency */
|
||||
|
||||
FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel.
|
||||
This parameter can be ENABLE or DISABLE */
|
||||
|
||||
FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel.
|
||||
This parameter can be ENABLE or DISABLE */
|
||||
|
||||
uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode.
|
||||
This parameter can be a value of @ref DAC_SampleAndHold */
|
||||
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection.
|
||||
Note: In case of sawtooth wave generation, this
|
||||
trigger corresponds to the reset trigger. */
|
||||
|
||||
uint32_t DAC_Trigger2; /*!< Specifies the external secondary trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection.
|
||||
Note: In case of sawtooth wave generation, this
|
||||
trigger corresponds to the step trigger.*/
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
|
||||
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
|
||||
|
||||
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
|
||||
This parameter must be a value of @ref DAC_UserTrimming
|
||||
DAC_UserTrimming is either factory or user trimming */
|
||||
|
||||
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
|
||||
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
|
||||
} DAC_ChannelConfTypeDef;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DAC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
|
||||
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
|
||||
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
|
||||
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
|
||||
|
||||
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
|
||||
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
|
||||
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
|
||||
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
|
||||
|
||||
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
|
||||
} HAL_DAC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DAC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Error_Code DAC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
|
||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
||||
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection DAC trigger selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_TRIGGER_NONE 0x00000000UL /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */
|
||||
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */
|
||||
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM15 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line9 event selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger */
|
||||
#define DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
#define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
|
||||
#define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer DAC output buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
|
||||
#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection DAC Channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 0x00000000U
|
||||
|
||||
#define DAC_CHANNEL_2 0x00000010U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment DAC data alignment
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R 0x00000000U
|
||||
#define DAC_ALIGN_12B_L 0x00000004U
|
||||
#define DAC_ALIGN_8B_R 0x00000008U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition DAC flags definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
#define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
|
||||
|
||||
#define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_IT_definition DAC IT definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
|
||||
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/
|
||||
#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via
|
||||
internal paths) and to an external pin. */
|
||||
#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via
|
||||
internal paths) and to an external pin.
|
||||
Note: this connection is not available in mode normal
|
||||
with buffer disabled. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_UserTrimming DAC User Trimming
|
||||
* @{
|
||||
*/
|
||||
#define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
|
||||
#define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_SampleAndHold DAC power mode
|
||||
* @{
|
||||
*/
|
||||
#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
|
||||
#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DAC_HighFrequency DAC high frequency interface mode
|
||||
* @{
|
||||
*/
|
||||
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
|
||||
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
|
||||
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
|
||||
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Delay for DAC channel voltage settling time from DAC channel startup */
|
||||
/* (transition from disable to enable). */
|
||||
/* Note: DAC channel startup time depends on board application environment: */
|
||||
/* impedance connected to DAC channel output. */
|
||||
/* The delay below is specified under conditions: */
|
||||
/* - voltage maximum transition (lowest to highest value) */
|
||||
/* - until voltage reaches final value +-1LSB */
|
||||
/* - DAC channel output buffer enabled */
|
||||
/* - load impedance of 5kOhm (min), 50pF (max) */
|
||||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tWAKEUP"). */
|
||||
/* Unit: us */
|
||||
#define DAC_DELAY_STARTUP_US (15UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DAC handle state.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __DAC_Channel__ specifies the DAC channel
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Disable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __DAC_Channel__ specifies the DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Set DHR12R1 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Set DHR12R2 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
|
||||
|
||||
|
||||
/** @brief Set DHR12RD alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Enable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
|
||||
*
|
||||
* (1) On this STM32 series, parameter not available on all instances.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
|
||||
*
|
||||
* (1) On this STM32 series, parameter not available on all instances.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified DAC interrupt source is enabled or not.
|
||||
* @param __HANDLE__ DAC handle
|
||||
* @param __INTERRUPT__ DAC interrupt source to check
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
|
||||
*
|
||||
* (1) On this STM32 series, parameter not available on all instances.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Get the selected DAC's flag status.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to get.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
|
||||
* @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag
|
||||
* @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1)
|
||||
*
|
||||
* (1) On this STM32 series, parameter not available on all instances.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the DAC's flag.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
|
||||
*
|
||||
* (1) On this STM32 series, parameter not available on all instances.
|
||||
* Refer to device datasheet for channels availability.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
|
||||
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
|
||||
(((DACX) == DAC2) ? \
|
||||
((CHANNEL) == DAC_CHANNEL_1) \
|
||||
: \
|
||||
(((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2)))
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC)
|
||||
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
|
||||
(((DACX) == DAC1) ? \
|
||||
((CHANNEL) == DAC_CHANNEL_1) \
|
||||
: \
|
||||
(((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2)))
|
||||
#else
|
||||
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
|
||||
(((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx */
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
|
||||
|
||||
#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extended module */
|
||||
#include "stm32g4xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/* DAC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
|
||||
pDAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
|
||||
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32G4xx_HAL_DAC_H */
|
||||
345
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h
Normal file
345
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h
Normal file
@@ -0,0 +1,345 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_DAC_EX_H
|
||||
#define STM32G4xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode
|
||||
* @{
|
||||
*/
|
||||
#define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */
|
||||
#define DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Private_Macros DACEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
|
||||
#define IS_DAC_TRIGGER(DACX, TRIGGER) \
|
||||
(((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG1) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG2) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG3) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG4) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG5) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG6) || \
|
||||
(((DACX) == DAC1) && \
|
||||
(((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \
|
||||
) || \
|
||||
(((DACX) == DAC2) && \
|
||||
(((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG02)) \
|
||||
) || \
|
||||
(((DACX) == DAC3) && \
|
||||
(((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG03)) \
|
||||
) || \
|
||||
(((DACX) == DAC4) && \
|
||||
(((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \
|
||||
) \
|
||||
)
|
||||
#else
|
||||
#define IS_DAC_TRIGGER(DACX, TRIGGER) \
|
||||
(((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
(((DACX) == DAC3) ? \
|
||||
((TRIGGER) == DAC_TRIGGER_T1_TRGO) \
|
||||
: ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
|
||||
) \
|
||||
)
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
|
||||
|
||||
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
|
||||
#define IS_DAC_TRIGGER2(DACX, TRIGGER) \
|
||||
(((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG1) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG2) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG3) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG4) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG5) || \
|
||||
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG6) || \
|
||||
(((DACX) == DAC1) && \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
|
||||
) || \
|
||||
(((DACX) == DAC2) && \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
|
||||
) || \
|
||||
(((DACX) == DAC3) && \
|
||||
((TRIGGER) == DAC_TRIGGER_T1_TRGO) \
|
||||
) || \
|
||||
(((DACX) == DAC4) && \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
|
||||
) \
|
||||
)
|
||||
#else
|
||||
#define IS_DAC_TRIGGER2(DACX, TRIGGER) \
|
||||
(((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||
(((DACX) == DAC3) ? \
|
||||
((TRIGGER) == DAC_TRIGGER_T1_TRGO) \
|
||||
:((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
|
||||
) \
|
||||
)
|
||||
#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
|
||||
#define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \
|
||||
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \
|
||||
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \
|
||||
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC))
|
||||
|
||||
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
|
||||
|
||||
#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
|
||||
|
||||
#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
|
||||
((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
|
||||
|
||||
#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
|
||||
|
||||
#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
|
||||
|
||||
#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
|
||||
((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
|
||||
((CONNECT) == DAC_CHIPCONNECT_BOTH))
|
||||
|
||||
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
|
||||
((TRIMMING) == DAC_TRIMMING_USER))
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||
|
||||
#define IS_DAC_SAWTOOTH_POLARITY(POLARITY) (((POLARITY) == DAC_SAWTOOTH_POLARITY_DECREMENT) || \
|
||||
((POLARITY) == DAC_SAWTOOTH_POLARITY_INCREMENT))
|
||||
|
||||
#define IS_DAC_RESET_DATA(DATA) ((DATA) <= 0x00000FFFUL)
|
||||
#define IS_DAC_STEP_DATA(DATA) ((DATA) <= 0x0000FFFFUL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Extended features functions ***********************************************/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity,
|
||||
uint32_t ResetData, uint32_t StepData);
|
||||
HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
|
||||
const uint32_t *pData, uint32_t Length, uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
|
||||
uint32_t NewTrimmingValue);
|
||||
uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
|
||||
/* are called by HAL_DAC_Start_DMA */
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_DAC_EX_H */
|
||||
211
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h
Normal file
211
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h
Normal file
@@ -0,0 +1,211 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32G4xx_HAL_DEF
|
||||
#define __STM32G4xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
|
||||
#include <stddef.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00U,
|
||||
HAL_ERROR = 0x01U,
|
||||
HAL_BUSY = 0x02U,
|
||||
HAL_TIMEOUT = 0x03U
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00U,
|
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
#if !defined(UNUSED)
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
#endif /* UNUSED */
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1U)
|
||||
/* Reserved for future use */
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0U)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0U)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4U)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5*/
|
||||
#define __ALIGN_BEGIN __align(4U)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
/* ARM Compiler V4/V5 and V6
|
||||
--------------------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif /* __CC_ARM */
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif /* __CC_ARM || __GNUC__ */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32G4xx_HAL_DEF */
|
||||
|
||||
852
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h
Normal file
852
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h
Normal file
@@ -0,0 +1,852 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32G4xx_HAL_DMA_H
|
||||
#define __STM32G4xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Request; /*!< Specifies the request selected for the specified channel.
|
||||
This parameter can be a value of @ref DMA_request */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
} HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
||||
} HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Callback ID structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
||||
|
||||
} HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
||||
|
||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
||||
|
||||
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
|
||||
|
||||
DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
|
||||
|
||||
uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
|
||||
|
||||
DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
|
||||
|
||||
DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
|
||||
|
||||
uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
|
||||
|
||||
} DMA_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
|
||||
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
|
||||
#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
|
||||
#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_request DMA request
|
||||
* @{
|
||||
*/
|
||||
#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
|
||||
|
||||
#define DMA_REQUEST_GENERATOR0 1U
|
||||
#define DMA_REQUEST_GENERATOR1 2U
|
||||
#define DMA_REQUEST_GENERATOR2 3U
|
||||
#define DMA_REQUEST_GENERATOR3 4U
|
||||
|
||||
#define DMA_REQUEST_ADC1 5U
|
||||
|
||||
#define DMA_REQUEST_DAC1_CHANNEL1 6U
|
||||
#define DMA_REQUEST_DAC1_CHANNEL2 7U
|
||||
|
||||
#define DMA_REQUEST_TIM6_UP 8U
|
||||
#define DMA_REQUEST_TIM7_UP 9U
|
||||
|
||||
#define DMA_REQUEST_SPI1_RX 10U
|
||||
#define DMA_REQUEST_SPI1_TX 11U
|
||||
#define DMA_REQUEST_SPI2_RX 12U
|
||||
#define DMA_REQUEST_SPI2_TX 13U
|
||||
#define DMA_REQUEST_SPI3_RX 14U
|
||||
#define DMA_REQUEST_SPI3_TX 15U
|
||||
|
||||
#define DMA_REQUEST_I2C1_RX 16U
|
||||
#define DMA_REQUEST_I2C1_TX 17U
|
||||
#define DMA_REQUEST_I2C2_RX 18U
|
||||
#define DMA_REQUEST_I2C2_TX 19U
|
||||
#define DMA_REQUEST_I2C3_RX 20U
|
||||
#define DMA_REQUEST_I2C3_TX 21U
|
||||
#if defined (I2C4)
|
||||
#define DMA_REQUEST_I2C4_RX 22U
|
||||
#define DMA_REQUEST_I2C4_TX 23U
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define DMA_REQUEST_USART1_RX 24U
|
||||
#define DMA_REQUEST_USART1_TX 25U
|
||||
#define DMA_REQUEST_USART2_RX 26U
|
||||
#define DMA_REQUEST_USART2_TX 27U
|
||||
#define DMA_REQUEST_USART3_RX 28U
|
||||
#define DMA_REQUEST_USART3_TX 29U
|
||||
|
||||
#define DMA_REQUEST_UART4_RX 30U
|
||||
#define DMA_REQUEST_UART4_TX 31U
|
||||
#if defined (UART5)
|
||||
#define DMA_REQUEST_UART5_RX 32U
|
||||
#define DMA_REQUEST_UART5_TX 33U
|
||||
#endif /* UART5 */
|
||||
|
||||
#define DMA_REQUEST_LPUART1_RX 34U
|
||||
#define DMA_REQUEST_LPUART1_TX 35U
|
||||
|
||||
#define DMA_REQUEST_ADC2 36U
|
||||
#if defined (ADC3)
|
||||
#define DMA_REQUEST_ADC3 37U
|
||||
#endif /* ADC3 */
|
||||
#if defined (ADC4)
|
||||
#define DMA_REQUEST_ADC4 38U
|
||||
#endif /* ADC4 */
|
||||
#if defined (ADC5)
|
||||
#define DMA_REQUEST_ADC5 39U
|
||||
#endif /* ADC5 */
|
||||
|
||||
#if defined (QUADSPI)
|
||||
#define DMA_REQUEST_QUADSPI 40U
|
||||
#endif /* QUADSPI */
|
||||
|
||||
#if defined (DAC2)
|
||||
#define DMA_REQUEST_DAC2_CHANNEL1 41U
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define DMA_REQUEST_TIM1_CH1 42U
|
||||
#define DMA_REQUEST_TIM1_CH2 43U
|
||||
#define DMA_REQUEST_TIM1_CH3 44U
|
||||
#define DMA_REQUEST_TIM1_CH4 45U
|
||||
#define DMA_REQUEST_TIM1_UP 46U
|
||||
#define DMA_REQUEST_TIM1_TRIG 47U
|
||||
#define DMA_REQUEST_TIM1_COM 48U
|
||||
|
||||
#define DMA_REQUEST_TIM8_CH1 49U
|
||||
#define DMA_REQUEST_TIM8_CH2 50U
|
||||
#define DMA_REQUEST_TIM8_CH3 51U
|
||||
#define DMA_REQUEST_TIM8_CH4 52U
|
||||
#define DMA_REQUEST_TIM8_UP 53U
|
||||
#define DMA_REQUEST_TIM8_TRIG 54U
|
||||
#define DMA_REQUEST_TIM8_COM 55U
|
||||
|
||||
#define DMA_REQUEST_TIM2_CH1 56U
|
||||
#define DMA_REQUEST_TIM2_CH2 57U
|
||||
#define DMA_REQUEST_TIM2_CH3 58U
|
||||
#define DMA_REQUEST_TIM2_CH4 59U
|
||||
#define DMA_REQUEST_TIM2_UP 60U
|
||||
|
||||
#define DMA_REQUEST_TIM3_CH1 61U
|
||||
#define DMA_REQUEST_TIM3_CH2 62U
|
||||
#define DMA_REQUEST_TIM3_CH3 63U
|
||||
#define DMA_REQUEST_TIM3_CH4 64U
|
||||
#define DMA_REQUEST_TIM3_UP 65U
|
||||
#define DMA_REQUEST_TIM3_TRIG 66U
|
||||
|
||||
#define DMA_REQUEST_TIM4_CH1 67U
|
||||
#define DMA_REQUEST_TIM4_CH2 68U
|
||||
#define DMA_REQUEST_TIM4_CH3 69U
|
||||
#define DMA_REQUEST_TIM4_CH4 70U
|
||||
#define DMA_REQUEST_TIM4_UP 71U
|
||||
|
||||
#if defined (TIM5)
|
||||
#define DMA_REQUEST_TIM5_CH1 72U
|
||||
#define DMA_REQUEST_TIM5_CH2 73U
|
||||
#define DMA_REQUEST_TIM5_CH3 74U
|
||||
#define DMA_REQUEST_TIM5_CH4 75U
|
||||
#define DMA_REQUEST_TIM5_UP 76U
|
||||
#define DMA_REQUEST_TIM5_TRIG 77U
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define DMA_REQUEST_TIM15_CH1 78U
|
||||
#define DMA_REQUEST_TIM15_UP 79U
|
||||
#define DMA_REQUEST_TIM15_TRIG 80U
|
||||
#define DMA_REQUEST_TIM15_COM 81U
|
||||
|
||||
#define DMA_REQUEST_TIM16_CH1 82U
|
||||
#define DMA_REQUEST_TIM16_UP 83U
|
||||
#define DMA_REQUEST_TIM17_CH1 84U
|
||||
#define DMA_REQUEST_TIM17_UP 85U
|
||||
|
||||
#if defined (TIM20)
|
||||
#define DMA_REQUEST_TIM20_CH1 86U
|
||||
#define DMA_REQUEST_TIM20_CH2 87U
|
||||
#define DMA_REQUEST_TIM20_CH3 88U
|
||||
#define DMA_REQUEST_TIM20_CH4 89U
|
||||
#define DMA_REQUEST_TIM20_UP 90U
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define DMA_REQUEST_AES_IN 91U
|
||||
#define DMA_REQUEST_AES_OUT 92U
|
||||
|
||||
#if defined (TIM20)
|
||||
#define DMA_REQUEST_TIM20_TRIG 93U
|
||||
#define DMA_REQUEST_TIM20_COM 94U
|
||||
#endif /* TIM20 */
|
||||
|
||||
#if defined (HRTIM1)
|
||||
#define DMA_REQUEST_HRTIM1_M 95U
|
||||
#define DMA_REQUEST_HRTIM1_A 96U
|
||||
#define DMA_REQUEST_HRTIM1_B 97U
|
||||
#define DMA_REQUEST_HRTIM1_C 98U
|
||||
#define DMA_REQUEST_HRTIM1_D 99U
|
||||
#define DMA_REQUEST_HRTIM1_E 100U
|
||||
#define DMA_REQUEST_HRTIM1_F 101U
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
#define DMA_REQUEST_DAC3_CHANNEL1 102U
|
||||
#define DMA_REQUEST_DAC3_CHANNEL2 103U
|
||||
#if defined (DAC4)
|
||||
#define DMA_REQUEST_DAC4_CHANNEL1 104U
|
||||
#define DMA_REQUEST_DAC4_CHANNEL2 105U
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined (SPI4)
|
||||
#define DMA_REQUEST_SPI4_RX 106U
|
||||
#define DMA_REQUEST_SPI4_TX 107U
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define DMA_REQUEST_SAI1_A 108U
|
||||
#define DMA_REQUEST_SAI1_B 109U
|
||||
|
||||
#define DMA_REQUEST_FMAC_READ 110U
|
||||
#define DMA_REQUEST_FMAC_WRITE 111U
|
||||
|
||||
#define DMA_REQUEST_CORDIC_READ 112U
|
||||
#define DMA_REQUEST_CORDIC_WRITE 113U
|
||||
|
||||
#define DMA_REQUEST_UCPD1_RX 114U
|
||||
#define DMA_REQUEST_UCPD1_TX 115U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
|
||||
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
|
||||
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
|
||||
#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
|
||||
#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
|
||||
#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC DMA_CCR_TCIE
|
||||
#define DMA_IT_HT DMA_CCR_HTIE
|
||||
#define DMA_IT_TE DMA_CCR_TEIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_GL1 0x00000001U
|
||||
#define DMA_FLAG_TC1 0x00000002U
|
||||
#define DMA_FLAG_HT1 0x00000004U
|
||||
#define DMA_FLAG_TE1 0x00000008U
|
||||
#define DMA_FLAG_GL2 0x00000010U
|
||||
#define DMA_FLAG_TC2 0x00000020U
|
||||
#define DMA_FLAG_HT2 0x00000040U
|
||||
#define DMA_FLAG_TE2 0x00000080U
|
||||
#define DMA_FLAG_GL3 0x00000100U
|
||||
#define DMA_FLAG_TC3 0x00000200U
|
||||
#define DMA_FLAG_HT3 0x00000400U
|
||||
#define DMA_FLAG_TE3 0x00000800U
|
||||
#define DMA_FLAG_GL4 0x00001000U
|
||||
#define DMA_FLAG_TC4 0x00002000U
|
||||
#define DMA_FLAG_HT4 0x00004000U
|
||||
#define DMA_FLAG_TE4 0x00008000U
|
||||
#define DMA_FLAG_GL5 0x00010000U
|
||||
#define DMA_FLAG_TC5 0x00020000U
|
||||
#define DMA_FLAG_HT5 0x00040000U
|
||||
#define DMA_FLAG_TE5 0x00080000U
|
||||
#define DMA_FLAG_GL6 0x00100000U
|
||||
#define DMA_FLAG_TC6 0x00200000U
|
||||
#define DMA_FLAG_HT6 0x00400000U
|
||||
#define DMA_FLAG_TE6 0x00800000U
|
||||
#if defined (DMA1_Channel7)
|
||||
#define DMA_FLAG_GL7 0x01000000U
|
||||
#define DMA_FLAG_TC7 0x02000000U
|
||||
#define DMA_FLAG_HT7 0x04000000U
|
||||
#define DMA_FLAG_TE7 0x08000000U
|
||||
#endif /* DMA1_Channel7 */
|
||||
#if defined (DMA1_Channel8)
|
||||
#define DMA_FLAG_GL8 0x10000000U
|
||||
#define DMA_FLAG_TC8 0x20000000U
|
||||
#define DMA_FLAG_HT8 0x40000000U
|
||||
#define DMA_FLAG_TE8 0x80000000U
|
||||
#endif /* DMA1_Channel8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DMA handle state.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
|
||||
#if defined (DMA1_Channel8)
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\
|
||||
DMA_FLAG_TC8)
|
||||
#elif defined (DMA1_Channel6)
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
|
||||
DMA_FLAG_TC6)
|
||||
#endif /* DMA1_Channel8 */
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#if defined (DMA1_Channel8)
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\
|
||||
DMA_FLAG_HT8)
|
||||
#elif defined (DMA1_Channel6)
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
|
||||
DMA_FLAG_HT6)
|
||||
#endif /* DMA1_Channel8 */
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#if defined (DMA1_Channel8)
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\
|
||||
DMA_FLAG_TE8)
|
||||
#elif defined (DMA1_Channel6)
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
|
||||
DMA_FLAG_TE6)
|
||||
#endif /* DMA1_Channel8 */
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#if defined (DMA1_Channel8)
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\
|
||||
DMA_ISR_GIF8)
|
||||
#elif defined (DMA1_Channel6)
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
|
||||
DMA_ISR_GIF6)
|
||||
#endif /* DMA1_Channel8 */
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx Transfer error flag
|
||||
* @arg DMA_FLAG_GLx Global interrupt flag
|
||||
* Where x can be from 1 to 8 to select the DMA Channel x flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#if defined (DMA1_Channel8)
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
|
||||
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
|
||||
#elif defined (DMA1_Channel6)
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
|
||||
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
|
||||
#endif /* DMA1_Channel8 */
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx Transfer error flag
|
||||
* @arg DMA_FLAG_GLx Global interrupt flag
|
||||
* Where x can be from 1 to 8 to select the DMA Channel x flag.
|
||||
* @retval None
|
||||
*/
|
||||
#if defined (DMA1_Channel8)
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
|
||||
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
|
||||
#else
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
|
||||
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
|
||||
#endif /* DMA1_Channel8 */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE Transfer error interrupt mask
|
||||
* @retval The state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Return the number of remaining data units in the current DMA Channel transfer.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The number of remaining data units in the current DMA Channel transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32g4xx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
|
||||
uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
|
||||
uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
|
||||
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR))
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32G4xx_HAL_DMA_H */
|
||||
|
||||
264
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h
Normal file
264
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h
Normal file
@@ -0,0 +1,264 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32G4xx_HAL_DMA_EX_H
|
||||
#define __STM32G4xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Synchro definition
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMAMUX Synchronization configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
|
||||
|
||||
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
|
||||
|
||||
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
|
||||
This parameter can take the value ENABLE or DISABLE*/
|
||||
|
||||
|
||||
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
|
||||
This parameter can take the value ENABLE or DISABLE */
|
||||
|
||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||
|
||||
|
||||
} HAL_DMA_MuxSyncConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMAMUX request generator parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
|
||||
|
||||
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
|
||||
|
||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||
|
||||
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */
|
||||
#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */
|
||||
#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */
|
||||
#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */
|
||||
#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
|
||||
#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
|
||||
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMAEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup DMAEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------------------- REQUEST -----------------------------------------*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
|
||||
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||
/* -------------------------------------------------------------------------- */
|
||||
|
||||
/* ------------------------- SYNCHRO -----------------------------------------*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
|
||||
/* -------------------------------------------------------------------------- */
|
||||
|
||||
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
|
||||
* @brief DMAEx private macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)
|
||||
|
||||
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||
|
||||
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
|
||||
|
||||
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
|
||||
|
||||
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
|
||||
((EVENT) == ENABLE))
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32G4xx_HAL_DMA_EX_H */
|
||||
|
||||
315
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h
Normal file
315
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h
Normal file
@@ -0,0 +1,315 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_EXTI_H
|
||||
#define STM32G4xx_HAL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_EXTI_COMMON_CB_ID = 0x00UL
|
||||
} EXTI_CallbackIDTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< Exti line number */
|
||||
void (* PendingCallback)(void); /*!< Exti pending callback */
|
||||
} EXTI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
} EXTI_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
|
||||
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
|
||||
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
|
||||
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
|
||||
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
|
||||
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
|
||||
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
|
||||
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
|
||||
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
|
||||
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
|
||||
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
|
||||
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
|
||||
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
|
||||
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
|
||||
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
|
||||
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
|
||||
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
|
||||
#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u)
|
||||
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u)
|
||||
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
|
||||
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u)
|
||||
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u)
|
||||
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
|
||||
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
|
||||
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
|
||||
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
|
||||
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
|
||||
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
|
||||
#define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du)
|
||||
#define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu)
|
||||
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
|
||||
#define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u)
|
||||
#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
|
||||
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u)
|
||||
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
|
||||
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
|
||||
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
|
||||
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u)
|
||||
#define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u)
|
||||
#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u)
|
||||
#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u)
|
||||
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
|
||||
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_NONE 0x00000000U
|
||||
#define EXTI_MODE_INTERRUPT 0x00000001U
|
||||
#define EXTI_MODE_EVENT 0x00000002U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TRIGGER_NONE 0x00000000U
|
||||
#define EXTI_TRIGGER_RISING 0x00000001U
|
||||
#define EXTI_TRIGGER_FALLING 0x00000002U
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000U
|
||||
#define EXTI_GPIOB 0x00000001U
|
||||
#define EXTI_GPIOC 0x00000002U
|
||||
#define EXTI_GPIOD 0x00000003U
|
||||
#define EXTI_GPIOE 0x00000004U
|
||||
#define EXTI_GPIOF 0x00000005U
|
||||
#define EXTI_GPIOG 0x00000006U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI Line property definition
|
||||
*/
|
||||
#define EXTI_PROPERTY_SHIFT 24U
|
||||
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
|
||||
|
||||
/**
|
||||
* @brief EXTI Register and bit usage
|
||||
*/
|
||||
#define EXTI_REG_SHIFT 16U
|
||||
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
|
||||
#define EXTI_PIN_MASK 0x0000001FU
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode
|
||||
*/
|
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities
|
||||
*/
|
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
|
||||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#define EXTI_LINE_NB 44UL
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
|
||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
|
||||
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
|
||||
|
||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
|
||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
|
||||
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF) || \
|
||||
((__PORT__) == EXTI_GPIOG))
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__EDGE__) (((__EDGE__) == EXTI_TRIGGER_RISING) || \
|
||||
((__EDGE__) == EXTI_TRIGGER_FALLING)|| \
|
||||
((__EDGE__) == EXTI_TRIGGER_RISING_FALLING))
|
||||
|
||||
#define IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_EXTI_H */
|
||||
|
||||
1442
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h
Normal file
1442
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h
Normal file
@@ -0,0 +1,1442 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_fdcan.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FDCAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_FDCAN_H
|
||||
#define STM32G4xx_HAL_FDCAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
#if defined(FDCAN1)
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FDCAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */
|
||||
HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */
|
||||
HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */
|
||||
HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */
|
||||
} HAL_FDCAN_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider.
|
||||
The clock is common to all FDCAN instances.
|
||||
This parameter is applied only at initialisation of
|
||||
first FDCAN instance.
|
||||
This parameter can be a value of @ref FDCAN_clock_divider. */
|
||||
|
||||
uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
|
||||
This parameter can be a value of @ref FDCAN_frame_format */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the FDCAN mode.
|
||||
This parameter can be a value of @ref FDCAN_operating_mode */
|
||||
|
||||
FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is
|
||||
divided for generating the nominal bit time quanta.
|
||||
This parameter must be a number between 1 and 512 */
|
||||
|
||||
uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
|
||||
hardware is allowed to lengthen or shorten a bit to perform
|
||||
resynchronization.
|
||||
This parameter must be a number between 1 and 128 */
|
||||
|
||||
uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||
This parameter must be a number between 2 and 256 */
|
||||
|
||||
uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter must be a number between 2 and 128 */
|
||||
|
||||
uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is
|
||||
divided for generating the data bit time quanta.
|
||||
This parameter must be a number between 1 and 32 */
|
||||
|
||||
uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
|
||||
hardware is allowed to lengthen or shorten a data bit to
|
||||
perform resynchronization.
|
||||
This parameter must be a number between 1 and 16 */
|
||||
|
||||
uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1.
|
||||
This parameter must be a number between 1 and 32 */
|
||||
|
||||
uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2.
|
||||
This parameter must be a number between 1 and 16 */
|
||||
|
||||
uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters.
|
||||
This parameter must be a number between 0 and 28 */
|
||||
|
||||
uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters.
|
||||
This parameter must be a number between 0 and 8 */
|
||||
|
||||
uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.
|
||||
This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
|
||||
|
||||
} FDCAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN filter structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IdType; /*!< Specifies the identifier type.
|
||||
This parameter can be a value of @ref FDCAN_id_type */
|
||||
|
||||
uint32_t FilterIndex; /*!< Specifies the filter which will be initialized.
|
||||
This parameter must be a number between:
|
||||
- 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
|
||||
- 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */
|
||||
|
||||
uint32_t FilterType; /*!< Specifies the filter type.
|
||||
This parameter can be a value of @ref FDCAN_filter_type.
|
||||
The value FDCAN_FILTER_RANGE_NO_EIDM is permitted
|
||||
only when IdType is FDCAN_EXTENDED_ID. */
|
||||
|
||||
uint32_t FilterConfig; /*!< Specifies the filter configuration.
|
||||
This parameter can be a value of @ref FDCAN_filter_config */
|
||||
|
||||
uint32_t FilterID1; /*!< Specifies the filter identification 1.
|
||||
This parameter must be a number between:
|
||||
- 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
|
||||
- 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
|
||||
|
||||
uint32_t FilterID2; /*!< Specifies the filter identification 2.
|
||||
This parameter must be a number between:
|
||||
- 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
|
||||
- 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
|
||||
|
||||
} FDCAN_FilterTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN Tx header structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Identifier; /*!< Specifies the identifier.
|
||||
This parameter must be a number between:
|
||||
- 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
|
||||
- 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
|
||||
|
||||
uint32_t IdType; /*!< Specifies the identifier type for the message that will be
|
||||
transmitted.
|
||||
This parameter can be a value of @ref FDCAN_id_type */
|
||||
|
||||
uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted.
|
||||
This parameter can be a value of @ref FDCAN_frame_type */
|
||||
|
||||
uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter can be a value of @ref FDCAN_data_length_code */
|
||||
|
||||
uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
|
||||
This parameter can be a value of @ref FDCAN_error_state_indicator */
|
||||
|
||||
uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without
|
||||
bit rate switching.
|
||||
This parameter can be a value of @ref FDCAN_bit_rate_switching */
|
||||
|
||||
uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or
|
||||
FD format.
|
||||
This parameter can be a value of @ref FDCAN_format */
|
||||
|
||||
uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control.
|
||||
This parameter can be a value of @ref FDCAN_EFC */
|
||||
|
||||
uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO
|
||||
element for identification of Tx message status.
|
||||
This parameter must be a number between 0 and 0xFF */
|
||||
|
||||
} FDCAN_TxHeaderTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN Rx header structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Identifier; /*!< Specifies the identifier.
|
||||
This parameter must be a number between:
|
||||
- 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
|
||||
- 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
|
||||
|
||||
uint32_t IdType; /*!< Specifies the identifier type of the received message.
|
||||
This parameter can be a value of @ref FDCAN_id_type */
|
||||
|
||||
uint32_t RxFrameType; /*!< Specifies the the received message frame type.
|
||||
This parameter can be a value of @ref FDCAN_frame_type */
|
||||
|
||||
uint32_t DataLength; /*!< Specifies the received frame length.
|
||||
This parameter can be a value of @ref FDCAN_data_length_code */
|
||||
|
||||
uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
|
||||
This parameter can be a value of @ref FDCAN_error_state_indicator */
|
||||
|
||||
uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit
|
||||
rate switching.
|
||||
This parameter can be a value of @ref FDCAN_bit_rate_switching */
|
||||
|
||||
uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD
|
||||
format.
|
||||
This parameter can be a value of @ref FDCAN_format */
|
||||
|
||||
uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
|
||||
reception.
|
||||
This parameter must be a number between 0 and 0xFFFF */
|
||||
|
||||
uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
|
||||
This parameter must be a number between:
|
||||
- 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
|
||||
- 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID
|
||||
When the frame is a Non-Filter matching frame, this parameter
|
||||
is unused. */
|
||||
|
||||
uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
|
||||
Acceptance of non-matching frames may be enabled via
|
||||
HAL_FDCAN_ConfigGlobalFilter().
|
||||
This parameter takes 0 if the frame matched an Rx filter or
|
||||
1 if it did not match any Rx filter */
|
||||
|
||||
} FDCAN_RxHeaderTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN Tx event FIFO structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Identifier; /*!< Specifies the identifier.
|
||||
This parameter must be a number between:
|
||||
- 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
|
||||
- 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
|
||||
|
||||
uint32_t IdType; /*!< Specifies the identifier type for the transmitted message.
|
||||
This parameter can be a value of @ref FDCAN_id_type */
|
||||
|
||||
uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message.
|
||||
This parameter can be a value of @ref FDCAN_frame_type */
|
||||
|
||||
uint32_t DataLength; /*!< Specifies the length of the transmitted frame.
|
||||
This parameter can be a value of @ref FDCAN_data_length_code */
|
||||
|
||||
uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
|
||||
This parameter can be a value of @ref FDCAN_error_state_indicator */
|
||||
|
||||
uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit
|
||||
rate switching.
|
||||
This parameter can be a value of @ref FDCAN_bit_rate_switching */
|
||||
|
||||
uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD
|
||||
format.
|
||||
This parameter can be a value of @ref FDCAN_format */
|
||||
|
||||
uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
|
||||
transmission.
|
||||
This parameter must be a number between 0 and 0xFFFF */
|
||||
|
||||
uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element
|
||||
for identification of Tx message status.
|
||||
This parameter must be a number between 0 and 0xFF */
|
||||
|
||||
uint32_t EventType; /*!< Specifies the event type.
|
||||
This parameter can be a value of @ref FDCAN_event_type */
|
||||
|
||||
} FDCAN_TxEventFifoTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN High Priority Message Status structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterList; /*!< Specifies the filter list of the matching filter element.
|
||||
This parameter can be:
|
||||
- 0 : Standard Filter List
|
||||
- 1 : Extended Filter List */
|
||||
|
||||
uint32_t FilterIndex; /*!< Specifies the index of matching filter element.
|
||||
This parameter can be a number between:
|
||||
- 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard)
|
||||
- 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */
|
||||
|
||||
uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
|
||||
This parameter can be a value of @ref FDCAN_hp_msg_storage */
|
||||
|
||||
uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the
|
||||
message was stored.
|
||||
This parameter is valid only when MessageStorage is:
|
||||
FDCAN_HP_STORAGE_RXFIFO0
|
||||
or
|
||||
FDCAN_HP_STORAGE_RXFIFO1 */
|
||||
|
||||
} FDCAN_HpMsgStatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN Protocol Status structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
|
||||
uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
|
||||
of a CAN FD format frame with its BRS flag set.
|
||||
This parameter can be a value of @ref FDCAN_protocol_error_code */
|
||||
|
||||
uint32_t Activity; /*!< Specifies the FDCAN module communication state.
|
||||
This parameter can be a value of @ref FDCAN_communication_state */
|
||||
|
||||
uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
|
||||
This parameter can be:
|
||||
- 0 : The FDCAN is in Error_Active state
|
||||
- 1 : The FDCAN is in Error_Passive state */
|
||||
|
||||
uint32_t Warning; /*!< Specifies the FDCAN module warning status.
|
||||
This parameter can be:
|
||||
- 0 : error counters (RxErrorCnt and TxErrorCnt) are below the
|
||||
Error_Warning limit of 96
|
||||
- 1 : at least one of error counters has reached the Error_Warning
|
||||
limit of 96 */
|
||||
|
||||
uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
|
||||
This parameter can be:
|
||||
- 0 : The FDCAN is not in Bus_Off state
|
||||
- 1 : The FDCAN is in Bus_Off state */
|
||||
|
||||
uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
|
||||
This parameter can be:
|
||||
- 0 : Last received CAN FD message did not have its ESI flag set
|
||||
- 1 : Last received CAN FD message had its ESI flag set */
|
||||
|
||||
uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
|
||||
This parameter can be:
|
||||
- 0 : Last received CAN FD message did not have its BRS flag set
|
||||
- 1 : Last received CAN FD message had its BRS flag set */
|
||||
|
||||
uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received
|
||||
since last protocol status.
|
||||
This parameter can be:
|
||||
- 0 : No CAN FD message received
|
||||
- 1 : CAN FD message received */
|
||||
|
||||
uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
|
||||
This parameter can be:
|
||||
- 0 : No protocol exception event occurred since last read access
|
||||
- 1 : Protocol exception event occurred */
|
||||
|
||||
uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
|
||||
This parameter can be a number between 0 and 127 */
|
||||
|
||||
} FDCAN_ProtocolStatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN Error Counters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
|
||||
This parameter can be a number between 0 and 127 */
|
||||
|
||||
uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
|
||||
This parameter can be:
|
||||
- 0 : The Receive Error Counter (RxErrorCnt) is below the error
|
||||
passive level of 128
|
||||
- 1 : The Receive Error Counter (RxErrorCnt) has reached the error
|
||||
passive level of 128 */
|
||||
|
||||
uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
|
||||
This parameter can be a number between 0 and 255.
|
||||
This counter is incremented each time when a FDCAN protocol error causes
|
||||
the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255;
|
||||
the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag
|
||||
FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
|
||||
|
||||
} FDCAN_ErrorCountersTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN Message RAM blocks
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
|
||||
This parameter must be a 32-bit word address */
|
||||
|
||||
uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
|
||||
This parameter must be a 32-bit word address */
|
||||
|
||||
uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address.
|
||||
This parameter must be a 32-bit word address */
|
||||
|
||||
uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address.
|
||||
This parameter must be a 32-bit word address */
|
||||
|
||||
uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address.
|
||||
This parameter must be a 32-bit word address */
|
||||
|
||||
uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address.
|
||||
This parameter must be a 32-bit word address */
|
||||
|
||||
} FDCAN_MsgRamAddressTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FDCAN handle structure definition
|
||||
*/
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
typedef struct __FDCAN_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
|
||||
{
|
||||
FDCAN_GlobalTypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */
|
||||
|
||||
FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */
|
||||
|
||||
uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
|
||||
of latest Tx FIFO/Queue request */
|
||||
|
||||
__IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< FDCAN locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< FDCAN Error code */
|
||||
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */
|
||||
void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */
|
||||
void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */
|
||||
void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */
|
||||
void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */
|
||||
void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */
|
||||
void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */
|
||||
void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */
|
||||
void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */
|
||||
void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */
|
||||
void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */
|
||||
|
||||
void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
|
||||
|
||||
} FDCAN_HandleTypeDef;
|
||||
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
/**
|
||||
* @brief HAL FDCAN common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
|
||||
HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, /*!< FDCAN High priority message callback ID */
|
||||
HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, /*!< FDCAN Timestamp wraparound callback ID */
|
||||
HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U, /*!< FDCAN Timeout occurred callback ID */
|
||||
HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */
|
||||
|
||||
HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */
|
||||
HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */
|
||||
|
||||
} HAL_FDCAN_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL FDCAN Callback pointer definition
|
||||
*/
|
||||
typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */
|
||||
typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */
|
||||
typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */
|
||||
typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */
|
||||
typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */
|
||||
typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */
|
||||
typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */
|
||||
|
||||
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
|
||||
#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */
|
||||
#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */
|
||||
#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */
|
||||
#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */
|
||||
#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
|
||||
#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */
|
||||
#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
|
||||
#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */
|
||||
#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */
|
||||
#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
|
||||
#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
|
||||
#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */
|
||||
#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */
|
||||
#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */
|
||||
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_frame_format FDCAN Frame Format
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */
|
||||
#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */
|
||||
#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
|
||||
#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
|
||||
#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */
|
||||
#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */
|
||||
#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
|
||||
#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */
|
||||
#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */
|
||||
#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */
|
||||
#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */
|
||||
#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
|
||||
#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
|
||||
#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
|
||||
#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
|
||||
#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
|
||||
#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
|
||||
#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
|
||||
#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
|
||||
#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
|
||||
#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
|
||||
#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */
|
||||
#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_id_type FDCAN ID Type
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
|
||||
#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_frame_type FDCAN Frame Type
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */
|
||||
#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
|
||||
#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */
|
||||
#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
|
||||
#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_format FDCAN format
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
|
||||
#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_EFC FDCAN Event FIFO control
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */
|
||||
#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_filter_type FDCAN Filter Type
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */
|
||||
#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */
|
||||
#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */
|
||||
#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */
|
||||
#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */
|
||||
#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */
|
||||
#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */
|
||||
#define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */
|
||||
#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */
|
||||
#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Tx_location FDCAN Tx Location
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */
|
||||
#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */
|
||||
#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Rx_location FDCAN Rx Location
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */
|
||||
#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_event_type FDCAN Event Type
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */
|
||||
#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */
|
||||
#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */
|
||||
#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
|
||||
#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */
|
||||
#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */
|
||||
#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */
|
||||
#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */
|
||||
#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */
|
||||
#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */
|
||||
#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */
|
||||
#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_communication_state FDCAN communication state
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
|
||||
#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */
|
||||
#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */
|
||||
#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
|
||||
#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
|
||||
#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
|
||||
#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
|
||||
#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
|
||||
#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Timestamp FDCAN timestamp
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
|
||||
#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */
|
||||
#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
|
||||
#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */
|
||||
#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
|
||||
#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */
|
||||
#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Interrupt_Masks Interrupt masks
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */
|
||||
#define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_flags FDCAN Flags
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */
|
||||
#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */
|
||||
#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */
|
||||
#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */
|
||||
#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */
|
||||
#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */
|
||||
#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */
|
||||
#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */
|
||||
#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */
|
||||
#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */
|
||||
#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */
|
||||
#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */
|
||||
#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */
|
||||
#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */
|
||||
#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */
|
||||
#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */
|
||||
#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */
|
||||
#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */
|
||||
#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */
|
||||
#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */
|
||||
#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */
|
||||
#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */
|
||||
#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */
|
||||
#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Interrupts FDCAN Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */
|
||||
#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */
|
||||
#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */
|
||||
#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */
|
||||
#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */
|
||||
#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */
|
||||
#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */
|
||||
#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */
|
||||
#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */
|
||||
#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */
|
||||
#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */
|
||||
#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */
|
||||
#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */
|
||||
#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */
|
||||
#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
|
||||
#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
|
||||
#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_LIST_RX_FIFO0 (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \
|
||||
FDCAN_IT_RX_FIFO0_FULL | \
|
||||
FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */
|
||||
#define FDCAN_IT_LIST_RX_FIFO1 (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \
|
||||
FDCAN_IT_RX_FIFO1_FULL | \
|
||||
FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */
|
||||
#define FDCAN_IT_LIST_SMSG (FDCAN_IT_TX_ABORT_COMPLETE | \
|
||||
FDCAN_IT_TX_COMPLETE | \
|
||||
FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */
|
||||
#define FDCAN_IT_LIST_TX_FIFO_ERROR (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \
|
||||
FDCAN_IT_TX_EVT_FIFO_FULL | \
|
||||
FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \
|
||||
FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */
|
||||
#define FDCAN_IT_LIST_MISC (FDCAN_IT_TIMEOUT_OCCURRED | \
|
||||
FDCAN_IT_RAM_ACCESS_FAILURE | \
|
||||
FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */
|
||||
#define FDCAN_IT_LIST_BIT_LINE_ERROR (FDCAN_IT_ERROR_PASSIVE | \
|
||||
FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */
|
||||
#define FDCAN_IT_LIST_PROTOCOL_ERROR (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \
|
||||
FDCAN_IT_DATA_PROTOCOL_ERROR | \
|
||||
FDCAN_IT_ARB_PROTOCOL_ERROR | \
|
||||
FDCAN_IT_RAM_WATCHDOG | \
|
||||
FDCAN_IT_BUS_OFF | \
|
||||
FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group
|
||||
* @{
|
||||
*/
|
||||
#define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group:
|
||||
RF0LL: Rx FIFO 0 Message Lost
|
||||
RF0FL: Rx FIFO 0 is Full
|
||||
RF0NL: Rx FIFO 0 Has New Message */
|
||||
#define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group:
|
||||
RF1LL: Rx FIFO 1 Message Lost
|
||||
RF1FL: Rx FIFO 1 is Full
|
||||
RF1NL: Rx FIFO 1 Has New Message */
|
||||
#define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG /*!< Status Message Interrupts Group:
|
||||
TCFL: Transmission Cancellation Finished
|
||||
TCL: Transmission Completed
|
||||
HPML: High Priority Message */
|
||||
#define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group:
|
||||
TEFLL: Tx Event FIFO Element Lost
|
||||
TEFFL: Tx Event FIFO Full
|
||||
TEFNL: Tx Event FIFO New Entry
|
||||
TFEL: Tx FIFO Empty Interrupt Line */
|
||||
#define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC /*!< Misc. Interrupts Group:
|
||||
TOOL: Timeout Occurred
|
||||
MRAFL: Message RAM Access Failure
|
||||
TSWL: Timestamp Wraparound */
|
||||
#define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group:
|
||||
EPL: Error Passive
|
||||
ELOL: Error Logging Overflow */
|
||||
#define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR /*!< Protocol Error Group:
|
||||
ARAL: Access to Reserved Address Line
|
||||
PEDL: Protocol Error in Data Phase Line
|
||||
PEAL: Protocol Error in Arbitration Phase Line
|
||||
WDIL: Watchdog Interrupt Line
|
||||
BOL: Bus_Off Status
|
||||
EWL: Warning Status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset FDCAN handle state.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
|
||||
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FDCAN interrupts.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
* @param __INTERRUPT__ FDCAN interrupt.
|
||||
* This parameter can be any combination of @arg FDCAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(__HANDLE__)->Instance->IE |= (__INTERRUPT__)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FDCAN interrupts.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
* @param __INTERRUPT__ FDCAN interrupt.
|
||||
* This parameter can be any combination of @arg FDCAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FDCAN interrupt is set or not.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
* @param __INTERRUPT__ FDCAN interrupt.
|
||||
* This parameter can be one of @arg FDCAN_Interrupts
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FDCAN interrupts.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
* @param __INTERRUPT__ specifies the interrupts to clear.
|
||||
* This parameter can be any combination of @arg FDCAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
|
||||
((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FDCAN flag is set or not.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
* @param __FLAG__ FDCAN flag.
|
||||
* This parameter can be one of @arg FDCAN_flags
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FDCAN flags.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
* @param __FLAG__ specifies the flags to clear.
|
||||
* This parameter can be any combination of @arg FDCAN_flags
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((__HANDLE__)->Instance->IR) = (__FLAG__)
|
||||
|
||||
/** @brief Check if the specified FDCAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ FDCAN handle.
|
||||
* @param __INTERRUPT__ specifies the FDCAN interrupt source to check.
|
||||
* This parameter can be a value of @arg FDCAN_Interrupts
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FDCAN_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FDCAN_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
|
||||
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
|
||||
void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
|
||||
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
|
||||
pFDCAN_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TxEventFifoCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_RxFifo0CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_RxFifo1CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
|
||||
pFDCAN_ErrorStatusCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FDCAN_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
|
||||
uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
|
||||
uint32_t RejectRemoteExt);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
|
||||
uint32_t TimeoutPeriod);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
|
||||
uint32_t TdcFilter);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FDCAN_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Control functions **********************************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
|
||||
const uint8_t *pTxData);
|
||||
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
|
||||
FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
|
||||
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
|
||||
FDCAN_ErrorCountersTypeDef *ErrorCounters);
|
||||
uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
|
||||
uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
|
||||
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
|
||||
uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FDCAN_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Interrupts management ******************************************************/
|
||||
HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
|
||||
HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
|
||||
uint32_t BufferIndexes);
|
||||
HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
|
||||
void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FDCAN_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Callback functions *********************************************************/
|
||||
void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
|
||||
void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
|
||||
void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
|
||||
void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
|
||||
void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
|
||||
void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
|
||||
void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FDCAN_Exported_Functions_Group6
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
|
||||
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \
|
||||
((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
|
||||
((FORMAT) == FDCAN_FRAME_FD_BRS ))
|
||||
#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \
|
||||
((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
|
||||
((MODE) == FDCAN_MODE_BUS_MONITORING ) || \
|
||||
((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \
|
||||
((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK ))
|
||||
#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV10) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV12) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV14) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV16) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV18) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV20) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV22) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV24) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV26) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV28) || \
|
||||
((CKDIV) == FDCAN_CLOCK_DIV30))
|
||||
#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
|
||||
#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
|
||||
#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
|
||||
#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
|
||||
#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
|
||||
#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
|
||||
#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
|
||||
#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
|
||||
#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
|
||||
#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
|
||||
#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
|
||||
((MODE) == FDCAN_TX_QUEUE_OPERATION))
|
||||
#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
|
||||
((ID_TYPE) == FDCAN_EXTENDED_ID))
|
||||
#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \
|
||||
((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \
|
||||
((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \
|
||||
((CONFIG) == FDCAN_FILTER_REJECT ) || \
|
||||
((CONFIG) == FDCAN_FILTER_HP ) || \
|
||||
((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
|
||||
((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP))
|
||||
#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
|
||||
((LOCATION) == FDCAN_TX_BUFFER2 ))
|
||||
#define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \
|
||||
((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2)))
|
||||
#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
|
||||
((FIFO) == FDCAN_RX_FIFO1))
|
||||
#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
|
||||
((MODE) == FDCAN_RX_FIFO_OVERWRITE))
|
||||
#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
|
||||
((TYPE) == FDCAN_FILTER_DUAL ) || \
|
||||
((TYPE) == FDCAN_FILTER_MASK ))
|
||||
#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \
|
||||
((TYPE) == FDCAN_FILTER_DUAL ) || \
|
||||
((TYPE) == FDCAN_FILTER_MASK ) || \
|
||||
((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
|
||||
#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \
|
||||
((TYPE) == FDCAN_REMOTE_FRAME))
|
||||
#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_1 ) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_2 ) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_3 ) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_4 ) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_5 ) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_6 ) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_7 ) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_8 ) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_12) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_16) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_20) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_24) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_32) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_48) || \
|
||||
((DLC) == FDCAN_DLC_BYTES_64))
|
||||
#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
|
||||
((ESI) == FDCAN_ESI_PASSIVE))
|
||||
#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
|
||||
((BRS) == FDCAN_BRS_ON ))
|
||||
#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
|
||||
((FDF) == FDCAN_FD_CAN ))
|
||||
#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \
|
||||
((EFC) == FDCAN_STORE_TX_EVENTS))
|
||||
#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
|
||||
#define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
|
||||
#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
|
||||
((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
|
||||
((DESTINATION) == FDCAN_REJECT ))
|
||||
#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
|
||||
((DESTINATION) == FDCAN_REJECT_REMOTE))
|
||||
#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
|
||||
((IT_LINE) == FDCAN_INTERRUPT_LINE1))
|
||||
#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
|
||||
((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
|
||||
#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
|
||||
((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
|
||||
#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \
|
||||
((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
|
||||
((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \
|
||||
((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 ))
|
||||
|
||||
#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
|
||||
#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_FDCAN_H */
|
||||
1017
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h
Normal file
1017
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h
Normal file
@@ -0,0 +1,1017 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_FLASH_H
|
||||
#define STM32G4xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< Mass erase or page erase.
|
||||
This parameter can be a value of @ref FLASH_Type_Erase */
|
||||
uint32_t Banks; /*!< Select bank to erase.
|
||||
This parameter must be a value of @ref FLASH_Banks
|
||||
(FLASH_BANK_BOTH should be used only for mass erase) */
|
||||
uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled.
|
||||
This parameter must be a value between 0 and (max number of pages in the bank - 1)
|
||||
(eg : 127 for 512KB dual bank) */
|
||||
uint32_t NbPages; /*!< Number of pages to be erased.
|
||||
This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes Program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< Option byte to be configured.
|
||||
This parameter can be a combination of the values of @ref FLASH_OB_Type */
|
||||
uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
|
||||
Only one WRP area could be programmed at the same time.
|
||||
This parameter can be value of @ref FLASH_OB_WRP_Area */
|
||||
uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
|
||||
This parameter must be a value between 0 and (max number of pages in the bank - 1) */
|
||||
uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
|
||||
This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
|
||||
uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
|
||||
This parameter can be a value of @ref FLASH_OB_Read_Protection */
|
||||
uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_Type */
|
||||
uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
|
||||
@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
|
||||
@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
|
||||
@ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
|
||||
@ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*),
|
||||
@ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
|
||||
@ref FLASH_OB_USER_CCMSRAM_RST
|
||||
@note (*) availability depends on devices */
|
||||
uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
|
||||
This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
|
||||
and @ref FLASH_OB_PCROP_RDP */
|
||||
uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
|
||||
This parameter must be a value between begin and end of bank
|
||||
=> Be careful of the bank swapping for the address */
|
||||
uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
|
||||
This parameter must be a value between PCROP Start address and end of bank */
|
||||
uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK).
|
||||
This parameter can be a value of @ref FLASH_OB_Boot_Lock */
|
||||
uint32_t SecBank; /*!< Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC).
|
||||
Only one securable memory area could be programmed at the same time.
|
||||
This parameter can be one of the following values:
|
||||
FLASH_BANK_1: Securable memory area to be programmed in bank 1
|
||||
FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*)
|
||||
@note (*) availability depends on devices */
|
||||
uint32_t SecSize; /*!< Size of securable memory area to be programmed (used for OPTIONBYTE_SEC),
|
||||
in number of pages. Securable memory area is starting from first page of the bank.
|
||||
Only one securable memory could be programmed at the same time.
|
||||
This parameter must be a value between 0 and (max number of pages in the bank - 1) */
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0,
|
||||
FLASH_PROC_PAGE_ERASE,
|
||||
FLASH_PROC_MASS_ERASE,
|
||||
FLASH_PROC_PROGRAM,
|
||||
FLASH_PROC_PROGRAM_LAST
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Cache structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_CACHE_DISABLED = 0,
|
||||
FLASH_CACHE_ICACHE_ENABLED,
|
||||
FLASH_CACHE_DCACHE_ENABLED,
|
||||
FLASH_CACHE_ICACHE_DCACHE_ENABLED
|
||||
} FLASH_CacheTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
__IO uint32_t ErrorCode; /* FLASH error code */
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
__IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
|
||||
__IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
|
||||
__IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
|
||||
__IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
|
||||
__IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error FLASH Error
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_ERROR_NONE 0x00000000U
|
||||
#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
|
||||
#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
|
||||
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
|
||||
#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
|
||||
#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
|
||||
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
|
||||
#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
|
||||
#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
|
||||
#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
|
||||
#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
|
||||
#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
|
||||
#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define HAL_FLASH_ERROR_ECCC2 FLASH_FLAG_ECCC2
|
||||
#define HAL_FLASH_ERROR_ECCD2 FLASH_FLAG_ECCD2
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Erase FLASH Erase Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/
|
||||
#define FLASH_TYPEERASE_MASSERASE 0x01U /*!<Flash mass erase activation*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Banks FLASH Banks
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define FLASH_BANK_2 0x00000002U /*!< Bank 2 */
|
||||
#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
|
||||
#else
|
||||
#define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Program Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00U /*!< Program a double-word (64-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_FAST 0x01U /*!< Fast program a 32 row double-word (64-bit) at a specified address.
|
||||
And another 32 row double-word (64-bit) will be programmed */
|
||||
#define FLASH_TYPEPROGRAM_FAST_AND_LAST 0x02U /*!< Fast program a 32 row double-word (64-bit) at a specified address.
|
||||
And this is the last 32 row double-word (64-bit) programmed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */
|
||||
#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */
|
||||
#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */
|
||||
#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
|
||||
#define OPTIONBYTE_BOOT_LOCK 0x10U /*!< Boot lock option byte configuration */
|
||||
#define OPTIONBYTE_SEC 0x20U /*!< Securable memory option byte configuration */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPAREA_BANK1_AREAA 0x00U /*!< Flash Bank 1 Area A */
|
||||
#define OB_WRPAREA_BANK1_AREAB 0x01U /*!< Flash Bank 1 Area B */
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define OB_WRPAREA_BANK2_AREAA 0x02U /*!< Flash Bank 2 Area A */
|
||||
#define OB_WRPAREA_BANK2_AREAB 0x04U /*!< Flash Bank 2 Area B */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Boot_Lock FLASH Boot Lock
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot Lock Disable */
|
||||
#define OB_BOOT_LOCK_ENABLE FLASH_SEC1R_BOOT_LOCK /*!< Boot Lock Enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 0xAAU
|
||||
#define OB_RDP_LEVEL_1 0xBBU
|
||||
#define OB_RDP_LEVEL_2 0xCCU /*!< Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */
|
||||
#define OB_USER_nRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */
|
||||
#define OB_USER_nRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */
|
||||
#define OB_USER_IWDG_SW 0x00000008U /*!< Independent watchdog selection */
|
||||
#define OB_USER_IWDG_STOP 0x00000010U /*!< Independent watchdog counter freeze in stop mode */
|
||||
#define OB_USER_IWDG_STDBY 0x00000020U /*!< Independent watchdog counter freeze in standby mode */
|
||||
#define OB_USER_WWDG_SW 0x00000040U /*!< Window watchdog selection */
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define OB_USER_BFB2 0x00000080U /*!< Dual-bank boot */
|
||||
#define OB_USER_DBANK 0x00000100U /*!< Single bank with 128-bits data or two banks with 64-bits data */
|
||||
#endif
|
||||
#if defined (FLASH_OPTR_PB4_PUPEN)
|
||||
#define OB_USER_PB4_PUPEN 0x00000100U /*!< USB power delivery dead-battery/TDI pull-up */
|
||||
#endif
|
||||
#define OB_USER_nBOOT1 0x00000200U /*!< Boot configuration */
|
||||
#define OB_USER_SRAM_PE 0x00000400U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
|
||||
#define OB_USER_CCMSRAM_RST 0x00000800U /*!< CCMSRAM Erase when system reset */
|
||||
#define OB_USER_nRST_SHDW 0x00001000U /*!< Reset generated when entering the shutdown mode */
|
||||
#define OB_USER_nSWBOOT0 0x00002000U /*!< Software BOOT0 */
|
||||
#define OB_USER_nBOOT0 0x00004000U /*!< nBOOT0 option bit */
|
||||
#define OB_USER_NRST_MODE 0x00008000U /*!< Reset pin configuration */
|
||||
#define OB_USER_IRHEN 0x00010000U /*!< Internal Reset Holder enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL_0 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 1.7V */
|
||||
#define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.0V */
|
||||
#define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.2V */
|
||||
#define OB_BOR_LEVEL_3 FLASH_OPTR_BOR_LEV_3 /*!< Reset level threshold is around 2.5V */
|
||||
#define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_4 /*!< Reset level threshold is around 2.8V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */
|
||||
#define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
|
||||
* @{
|
||||
*/
|
||||
#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */
|
||||
#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
|
||||
* @{
|
||||
*/
|
||||
#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */
|
||||
#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */
|
||||
#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */
|
||||
#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */
|
||||
#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */
|
||||
#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
|
||||
* @{
|
||||
*/
|
||||
#define OB_BFB2_DISABLE 0x00000000U /*!< Dual-bank boot disable */
|
||||
#define OB_BFB2_ENABLE FLASH_OPTR_BFB2 /*!< Dual-bank boot enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_DBANK_128_BITS 0x00000000U /*!< Single-bank with 128-bits data */
|
||||
#define OB_DBANK_64_BITS FLASH_OPTR_DBANK /*!< Dual-bank with 64-bits data */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
#if defined (FLASH_OPTR_PB4_PUPEN)
|
||||
/** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_PB4_PUPEN_DISABLE 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */
|
||||
#define OB_PB4_PUPEN_ENABLE FLASH_OPTR_PB4_PUPEN /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
|
||||
#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM_PE FLASH Option Bytes User SRAM Parity Check Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM_PARITY_ENABLE 0x00000000U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
|
||||
#define OB_SRAM_PARITY_DISABLE FLASH_OPTR_SRAM_PE /*!< SRAM parity check disable (first 32kB of SRAM1 + CCM SRAM) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_OB_USER_CCMSRAM_RST FLASH Option Bytes User CCMSRAM Erase On Reset Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_CCMSRAM_RST_ERASE 0x00000000U /*!< CCMSRAM erased when a system reset occurs */
|
||||
#define OB_CCMSRAM_RST_NOT_ERASE FLASH_OPTR_CCMSRAM_RST /*!< CCMSRAM is not erased when a system reset occurs */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */
|
||||
#define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PB8/BOOT0 pin */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */
|
||||
#define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_NRST_MODE FLASH Option Bytes User NRST mode bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_NRST_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0 /*!< Reset pin is in Reset input mode only */
|
||||
#define OB_NRST_MODE_GPIO FLASH_OPTR_NRST_MODE_1 /*!< Reset pin is in GPIO mode only */
|
||||
#define OB_NRST_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE /*!< Reset pin is in reset input and output mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_INTERNAL_RESET_HOLDER FLASH Option Bytes User internal reset holder bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_IRH_DISABLE 0x00000000U /*!< Internal Reset holder disable */
|
||||
#define OB_IRH_ENABLE FLASH_OPTR_IRHEN /*!< Internal Reset holder enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
|
||||
is decreased from Level 1 to Level 0 */
|
||||
#define OB_PCROP_RDP_ERASE FLASH_PCROP1ER_PCROP_RDP /*!< PCROP area is erased when the RDP level is
|
||||
decreased from Level 1 to Level 0 (full mass erase) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
|
||||
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
|
||||
#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
|
||||
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */
|
||||
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */
|
||||
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
|
||||
#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
|
||||
#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */
|
||||
#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */
|
||||
#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */
|
||||
#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */
|
||||
#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */
|
||||
#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */
|
||||
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys FLASH Keys
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY1 0x45670123U /*!< Flash key1 */
|
||||
#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
|
||||
to unlock the FLASH registers access */
|
||||
|
||||
#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
|
||||
#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
|
||||
to unlock the RUN_PD bit in FLASH_ACR */
|
||||
|
||||
#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */
|
||||
#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
|
||||
to allow option bytes operations */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags FLASH Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
|
||||
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
|
||||
#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
|
||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
|
||||
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
|
||||
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
|
||||
#define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
|
||||
#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
|
||||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
|
||||
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction in 64 LSB bits */
|
||||
#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection in 64 LSB bits */
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define FLASH_FLAG_ECCC2 FLASH_ECCR_ECCC2 /*!< FLASH ECC correction in 64 MSB bits (mode 128 bits only) */
|
||||
#define FLASH_FLAG_ECCD2 FLASH_ECCR_ECCD2 /*!< FLASH ECC detection in 64 MSB bits (mode 128 bits only) */
|
||||
#endif
|
||||
|
||||
#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
|
||||
FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
|
||||
FLASH_FLAG_OPTVERR)
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD | FLASH_FLAG_ECCC2 | FLASH_FLAG_ECCD2)
|
||||
#else
|
||||
#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
|
||||
#endif
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
|
||||
#define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/
|
||||
#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24U) /*!< ECC Correction Interrupt source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__ FLASH Latency.
|
||||
* This parameter can be one of the following values :
|
||||
* @arg FLASH_LATENCY_0: FLASH Zero wait state
|
||||
* @arg FLASH_LATENCY_1: FLASH One wait state
|
||||
* @arg FLASH_LATENCY_2: FLASH Two wait states
|
||||
* @arg FLASH_LATENCY_3: FLASH Three wait states
|
||||
* @arg FLASH_LATENCY_4: FLASH Four wait states
|
||||
* @arg FLASH_LATENCY_5: FLASH Five wait states
|
||||
* @arg FLASH_LATENCY_6: FLASH Six wait states
|
||||
* @arg FLASH_LATENCY_7: FLASH Seven wait states
|
||||
* @arg FLASH_LATENCY_8: FLASH Eight wait states
|
||||
* @arg FLASH_LATENCY_9: FLASH Nine wait states
|
||||
* @arg FLASH_LATENCY_10: FLASH Ten wait state
|
||||
* @arg FLASH_LATENCY_11: FLASH Eleven wait state
|
||||
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
|
||||
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
|
||||
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
|
||||
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH_Latency.
|
||||
* This parameter can be one of the following values :
|
||||
* @arg FLASH_LATENCY_0: FLASH Zero wait state
|
||||
* @arg FLASH_LATENCY_1: FLASH One wait state
|
||||
* @arg FLASH_LATENCY_2: FLASH Two wait states
|
||||
* @arg FLASH_LATENCY_3: FLASH Three wait states
|
||||
* @arg FLASH_LATENCY_4: FLASH Four wait states
|
||||
* @arg FLASH_LATENCY_5: FLASH Five wait states
|
||||
* @arg FLASH_LATENCY_6: FLASH Six wait states
|
||||
* @arg FLASH_LATENCY_7: FLASH Seven wait states
|
||||
* @arg FLASH_LATENCY_8: FLASH Eight wait states
|
||||
* @arg FLASH_LATENCY_9: FLASH Nine wait states
|
||||
* @arg FLASH_LATENCY_10: FLASH Ten wait state
|
||||
* @arg FLASH_LATENCY_11: FLASH Eleven wait state
|
||||
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
|
||||
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
|
||||
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
|
||||
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH instruction cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH instruction cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH data cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH data cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
|
||||
|
||||
/**
|
||||
* @brief Reset the FLASH instruction Cache.
|
||||
* @note This function must be used only when the Instruction Cache is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
|
||||
CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief Reset the FLASH data Cache.
|
||||
* @note This function must be used only when the data Cache is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
|
||||
CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH power down during Low-power run mode.
|
||||
* @note Writing this bit to 1, automatically the keys are
|
||||
* lost and a new unlock sequence is necessary to re-write it to 0.
|
||||
*/
|
||||
#define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
|
||||
WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
|
||||
SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH power down during Low-power run mode.
|
||||
* @note Writing this bit to 0, automatically the keys are
|
||||
* lost and a new unlock sequence is necessary to re-write it to 1.
|
||||
*/
|
||||
#define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
|
||||
WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
|
||||
CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH power down during Low-Power sleep mode
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH power down during Low-Power sleep mode
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_OPERR: Error Interrupt
|
||||
* @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
|
||||
* @arg FLASH_IT_ECCC: ECC Correction Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_OPERR: Error Interrupt
|
||||
* @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
|
||||
* @arg FLASH_IT_ECCC: ECC Correction Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FLASH flag is set or not.
|
||||
* @param __FLAG__ specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_OPERR: FLASH Operation error flag
|
||||
* @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
|
||||
* @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
|
||||
* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
|
||||
* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
|
||||
* @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
|
||||
* @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
|
||||
* @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
|
||||
* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
|
||||
* @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
|
||||
* @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
|
||||
* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
|
||||
* @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
|
||||
* @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
|
||||
* @note (*) availability depends on devices
|
||||
* @retval The new state of FLASH_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the FLASH's pending flags.
|
||||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_OPERR: FLASH Operation error flag
|
||||
* @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
|
||||
* @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
|
||||
* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
|
||||
* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
|
||||
* @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
|
||||
* @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
|
||||
* @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
|
||||
* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
|
||||
* @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
|
||||
* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
|
||||
* @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
|
||||
* @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
|
||||
* @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags
|
||||
* @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags
|
||||
* @note (*) availability depends on devices
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
|
||||
if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
|
||||
} while (0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */
|
||||
#include "stm32g4xx_hal_flash_ex.h"
|
||||
#include "stm32g4xx_hal_flash_ramfunc.h"
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Variables FLASH Exported Variables
|
||||
* @{
|
||||
*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Program operation functions ***********************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
|
||||
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \
|
||||
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
|
||||
#define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 128U : \
|
||||
((FLASH_SIZE == 0x00040000U) ? 64U : 32U))
|
||||
#define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */
|
||||
#else
|
||||
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \
|
||||
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
|
||||
#define FLASH_BANK_SIZE (FLASH_SIZE)
|
||||
#define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : \
|
||||
((FLASH_SIZE == 0x00040000U) ? 128U : 64U))
|
||||
#endif
|
||||
|
||||
#define FLASH_PAGE_SIZE 0x800U /* 2 KB */
|
||||
|
||||
#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
|
||||
((BANK) == FLASH_BANK_2) || \
|
||||
((BANK) == FLASH_BANK_BOTH))
|
||||
|
||||
#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
|
||||
((BANK) == FLASH_BANK_2))
|
||||
#else
|
||||
#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
|
||||
|
||||
#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
|
||||
#endif
|
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
|
||||
|
||||
#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
|
||||
|
||||
#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
|
||||
|
||||
#define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB)
|
||||
|
||||
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
|
||||
OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC)))
|
||||
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
|
||||
((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
|
||||
#else
|
||||
#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
|
||||
#endif
|
||||
|
||||
#define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))
|
||||
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_1) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_2))
|
||||
|
||||
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))
|
||||
|
||||
#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
|
||||
((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
|
||||
((LEVEL) == OB_BOR_LEVEL_4))
|
||||
|
||||
#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
|
||||
|
||||
#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
|
||||
|
||||
#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
|
||||
|
||||
#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
|
||||
|
||||
#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
|
||||
|
||||
#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
|
||||
|
||||
#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
|
||||
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
#define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
|
||||
|
||||
#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
|
||||
#endif
|
||||
|
||||
#if defined (FLASH_OPTR_PB4_PUPEN)
|
||||
#define IS_OB_USER_PB4_PUPEN(VALUE) (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE))
|
||||
#endif
|
||||
|
||||
#define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
|
||||
|
||||
#define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
|
||||
|
||||
|
||||
#define IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))
|
||||
|
||||
#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
|
||||
|
||||
#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))
|
||||
|
||||
#define IS_OB_USER_NRST_MODE(VALUE) (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \
|
||||
((VALUE) == OB_NRST_MODE_INPUT_OUTPUT))
|
||||
|
||||
#define IS_OB_USER_IRHEN(VALUE) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))
|
||||
|
||||
#define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
|
||||
|
||||
#define IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB)
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
|
||||
((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
|
||||
((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
|
||||
((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
|
||||
((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
|
||||
((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
|
||||
((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
|
||||
((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_FLASH_H */
|
||||
|
||||
89
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
Normal file
89
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
Normal file
@@ -0,0 +1,89 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_FLASH_EX_H
|
||||
#define STM32G4xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Extended Program operation functions *************************************/
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
|
||||
void HAL_FLASHEx_EnableDebugger(void);
|
||||
void HAL_FLASHEx_DisableDebugger(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
void FLASH_PageErase(uint32_t Page, uint32_t Banks);
|
||||
void FLASH_FlushCaches(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_FLASH_EX_H */
|
||||
|
||||
@@ -0,0 +1,74 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_flash_ramfunc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH RAMFUNC driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_FLASH_RAMFUNC_H
|
||||
#define STM32G4xx_FLASH_RAMFUNC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_RAMFUNC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_RAMFUNC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
|
||||
#if defined (FLASH_OPTR_DBANK)
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_FLASH_RAMFUNC_H */
|
||||
|
||||
723
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h
Normal file
723
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h
Normal file
@@ -0,0 +1,723 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_fmac.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header for stm32g4xx_hal_fmac.c module
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_FMAC_H
|
||||
#define STM32G4xx_HAL_FMAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
#if defined(FMAC)
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_Types FMAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FMAC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_FMAC_STATE_RESET = 0x00U, /*!< FMAC not yet initialized or disabled */
|
||||
HAL_FMAC_STATE_READY = 0x20U, /*!< FMAC initialized and ready for use */
|
||||
HAL_FMAC_STATE_BUSY = 0x24U, /*!< FMAC internal process is ongoing */
|
||||
HAL_FMAC_STATE_BUSY_RD = 0x25U, /*!< FMAC reading configuration is ongoing */
|
||||
HAL_FMAC_STATE_BUSY_WR = 0x26U, /*!< FMAC writing configuration is ongoing */
|
||||
HAL_FMAC_STATE_TIMEOUT = 0xA0U, /*!< FMAC in Timeout state */
|
||||
HAL_FMAC_STATE_ERROR = 0xE0U /*!< FMAC in Error state */
|
||||
} HAL_FMAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMAC Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __FMAC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
{
|
||||
FMAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
uint32_t FilterParam; /*!< Filter configuration (operation and parameters).
|
||||
Set to 0 if no valid configuration was applied. */
|
||||
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
int16_t *pInput; /*!< Pointer to FMAC input data buffer */
|
||||
|
||||
uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */
|
||||
|
||||
uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput).
|
||||
In case of early interruption of the filter operation,
|
||||
its value will be updated. */
|
||||
|
||||
int16_t *pOutput; /*!< Pointer to FMAC output data buffer */
|
||||
|
||||
uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */
|
||||
|
||||
uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput).
|
||||
In case of early interruption of the filter operation,
|
||||
its value will be updated. */
|
||||
|
||||
DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle
|
||||
parameters */
|
||||
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */
|
||||
|
||||
void (* HalfGetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get half data callback */
|
||||
|
||||
void (* GetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get data callback */
|
||||
|
||||
void (* HalfOutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC half output data ready callback */
|
||||
|
||||
void (* OutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC output data ready callback */
|
||||
|
||||
void (* FilterConfigCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter configuration callback */
|
||||
|
||||
void (* FilterPreloadCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter preload callback */
|
||||
|
||||
void (* MspInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_FMAC_REGISTER_CALLBACKS) */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< FMAC locking object */
|
||||
|
||||
__IO HAL_FMAC_StateTypeDef State; /*!< FMAC state related to global handle management
|
||||
This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
|
||||
|
||||
__IO HAL_FMAC_StateTypeDef RdState; /*!< FMAC state related to read operations (access to Y buffer)
|
||||
This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
|
||||
|
||||
__IO HAL_FMAC_StateTypeDef WrState; /*!< FMAC state related to write operations (access to X1 buffer)
|
||||
This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< FMAC peripheral error code
|
||||
This parameter can be a value of @ref FMAC_Error_Code */
|
||||
|
||||
} FMAC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief FMAC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_FMAC_ERROR_CB_ID = 0x00U, /*!< FMAC error callback ID */
|
||||
HAL_FMAC_HALF_GET_DATA_CB_ID = 0x01U, /*!< FMAC get half data callback ID */
|
||||
HAL_FMAC_GET_DATA_CB_ID = 0x02U, /*!< FMAC get data callback ID */
|
||||
HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID = 0x03U, /*!< FMAC half output data ready callback ID */
|
||||
HAL_FMAC_OUTPUT_DATA_READY_CB_ID = 0x04U, /*!< FMAC output data ready callback ID */
|
||||
HAL_FMAC_FILTER_CONFIG_CB_ID = 0x05U, /*!< FMAC filter configuration callback ID */
|
||||
HAL_FMAC_FILTER_PRELOAD_CB_ID = 0x06U, /*!< FMAC filter preload callback ID */
|
||||
|
||||
HAL_FMAC_MSPINIT_CB_ID = 0x07U, /*!< FMAC MspInit callback ID */
|
||||
HAL_FMAC_MSPDEINIT_CB_ID = 0x08U, /*!< FMAC MspDeInit callback ID */
|
||||
} HAL_FMAC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL FMAC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer to an FMAC callback function */
|
||||
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief FMAC Filter Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory
|
||||
(0x00 to 0xFF). Ignored if InputBufferSize is set to 0
|
||||
(previous configuration kept).
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer
|
||||
(including the optional "headroom").
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number
|
||||
of free spaces in the buffer is lower than this threshold.
|
||||
This parameter can be a value
|
||||
of @ref FMAC_Data_Buffer_Threshold. */
|
||||
|
||||
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal
|
||||
memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0
|
||||
(previous configuration kept).
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal
|
||||
memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0
|
||||
(previous configuration kept).
|
||||
Note: the buffers can overlap or even coincide exactly. */
|
||||
|
||||
uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer
|
||||
(including the optional "headroom").
|
||||
0 if a previous configuration should be kept. */
|
||||
|
||||
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number
|
||||
of unread values in the buffer is lower than this threshold.
|
||||
This parameter can be a value
|
||||
of @ref FMAC_Data_Buffer_Threshold. */
|
||||
|
||||
int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
|
||||
If not needed, it should be set to NULL. */
|
||||
|
||||
uint8_t CoeffASize; /*!< Size of the coefficient vector A. */
|
||||
|
||||
int16_t *pCoeffB; /*!< Initialization of the coefficient vector B.
|
||||
If not needed (re-use of a previously loaded buffer),
|
||||
it should be set to NULL. */
|
||||
|
||||
uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
|
||||
|
||||
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area):
|
||||
DMA, IT, Polling, None.
|
||||
This parameter can be a value of @ref FMAC_Buffer_Access. */
|
||||
|
||||
uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range
|
||||
is exceeded, wrapping is done when the clipping feature is disabled
|
||||
and saturation is done when the clipping feature is enabled.
|
||||
This parameter can be a value of @ref FMAC_Clip_State. */
|
||||
|
||||
uint32_t Filter; /*!< Filter type.
|
||||
This parameter can be a value
|
||||
of @ref FMAC_Functions (filter related values). */
|
||||
|
||||
uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */
|
||||
|
||||
uint8_t Q; /*!< Parameter Q (vector length, etc.). Ignored if not needed. */
|
||||
|
||||
uint8_t R; /*!< Parameter R (gain, etc.). Ignored if not needed. */
|
||||
|
||||
} FMAC_FilterConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_Constants FMAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Error_Code FMAC Error code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */
|
||||
#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */
|
||||
#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */
|
||||
#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */
|
||||
#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */
|
||||
#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Functions FMAC Functions
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
|
||||
#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
|
||||
#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
|
||||
#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
|
||||
#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Data_Buffer_Threshold FMAC Data Buffer Threshold
|
||||
* @{
|
||||
* @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
|
||||
*/
|
||||
#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 1.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 1. */
|
||||
#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 2.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 2. */
|
||||
#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 4.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 4. */
|
||||
#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces
|
||||
in the buffer is less than 8.
|
||||
Output: Buffer empty flag set if the number
|
||||
of unread values in the buffer is less than 8. */
|
||||
#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Buffer_Access FMAC Buffer Access
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */
|
||||
#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */
|
||||
#define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */
|
||||
#define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Clip_State FMAC Clip State
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */
|
||||
#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Flags FMAC status flags
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_FLAG_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
|
||||
#define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
|
||||
#define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
|
||||
#define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
|
||||
#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag
|
||||
(this helps in debugging a filter) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FMAC_Interrupts_Enable FMAC Interrupts Enable bit
|
||||
* @{
|
||||
*/
|
||||
#define FMAC_IT_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
|
||||
#define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
|
||||
#define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
|
||||
#define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
|
||||
#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable
|
||||
(this helps in debugging a filter) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_variables FMAC Exported variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reset FMAC handle state.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_FMAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMAC_STATE_RESET)
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FMAC interrupt
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC Interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FMAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the FMAC interrupt
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC Interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FMAC interrupt occurred or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
|
||||
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
|
||||
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
|
||||
* @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
|
||||
* @arg @ref FMAC_FLAG_SAT Saturation Error Flag
|
||||
* @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
|
||||
*/
|
||||
#define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear specified FMAC interrupt status. Dummy macro as the
|
||||
interrupt status flags are read-only.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to clear.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FMAC status flag is set or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __FLAG__ FMAC flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
|
||||
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
|
||||
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
|
||||
* @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
|
||||
* @arg @ref FMAC_FLAG_SAT Saturation error Flag
|
||||
* @retval SET (flag is set) or RESET (flag is reset)
|
||||
*/
|
||||
#define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear specified FMAC status flag. Dummy macro as no
|
||||
flag can be cleared.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __FLAG__ FMAC flag to clear.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FMAC interrupt is enabled or not.
|
||||
* @param __HANDLE__ FMAC handle.
|
||||
* @param __INTERRUPT__ FMAC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref FMAC_IT_RIEN Read interrupt enable
|
||||
* @arg @ref FMAC_IT_WIEN Write interrupt enable
|
||||
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
|
||||
* @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
(((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FMAC_PARAM_P_MAX_IIR 64U /*!< Maximum value of P parameter with IIR */
|
||||
#define FMAC_PARAM_P_MAX_FIR 127U /*!< Maximum value of P parameter with FIR */
|
||||
#define FMAC_PARAM_P_MIN 2U /*!< Minimum value of P parameter */
|
||||
#define FMAC_PARAM_Q_MAX 63U /*!< Maximum value of Q parameter */
|
||||
#define FMAC_PARAM_Q_MIN 1U /*!< Minimum value of Q parameter */
|
||||
#define FMAC_PARAM_R_MAX 7U /*!< Maximum value of R parameter */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros-------------------------------------------------------------*/
|
||||
/** @addtogroup FMAC_Private_Macros FMAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC function.
|
||||
* @param __FUNCTION__ ID of the function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function used for input data, output data or coefficients.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function used with N values as input or output data.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_N_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC load function used with N + M values as coefficients.
|
||||
* @param __FUNCTION__ ID of the load function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_N_M_LOAD_FUNCTION(__FUNCTION__) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter function.
|
||||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_FILTER_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC threshold.
|
||||
* @param __THRESHOLD__ Value of the threshold.
|
||||
* @retval SET (__THRESHOLD__ is a valid value) or RESET (__THRESHOLD__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == FMAC_THRESHOLD_1) || \
|
||||
((__THRESHOLD__) == FMAC_THRESHOLD_2) || \
|
||||
((__THRESHOLD__) == FMAC_THRESHOLD_4) || \
|
||||
((__THRESHOLD__) == FMAC_THRESHOLD_NO_VALUE) || \
|
||||
((__THRESHOLD__) == FMAC_THRESHOLD_8))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter P.
|
||||
* @param __P__ Value of the filter parameter P.
|
||||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
|
||||
(((__P__) >= FMAC_PARAM_P_MIN) && \
|
||||
((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__P__) >= FMAC_PARAM_P_MIN) && \
|
||||
((__P__) <= FMAC_PARAM_P_MAX_IIR))))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter Q.
|
||||
* @param __Q__ Value of the filter parameter Q.
|
||||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
|
||||
(((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC filter parameter R.
|
||||
* @param __R__ Value of the filter parameter.
|
||||
* @param __FUNCTION__ ID of the filter function.
|
||||
* @retval SET (__R__ is a valid value) or RESET (__R__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
|
||||
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \
|
||||
((__R__) <= FMAC_PARAM_R_MAX))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC buffer access.
|
||||
* @param __BUFFER_ACCESS__ Type of access.
|
||||
* @retval SET (__BUFFER_ACCESS__ is a valid value) or RESET (__BUFFER_ACCESS__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_BUFFER_ACCESS(__BUFFER_ACCESS__) (((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_NONE) || \
|
||||
((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_DMA) || \
|
||||
((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_POLLING) || \
|
||||
((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_IT))
|
||||
|
||||
/**
|
||||
* @brief Verify the FMAC clip feature.
|
||||
* @param __CLIP_STATE__ Clip state.
|
||||
* @retval SET (__CLIP_STATE__ is a valid value) or RESET (__CLIP_STATE__ is invalid)
|
||||
*/
|
||||
#define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \
|
||||
((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
|
||||
|
||||
/**
|
||||
* @brief Check whether the threshold is applicable.
|
||||
* @param __SIZE__ Size of the matching buffer.
|
||||
* @param __WM__ Watermark value.
|
||||
* @param __ACCESS__ Access to the buffer (polling, it, dma, none).
|
||||
* @retval THRESHOLD
|
||||
*/
|
||||
#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
|
||||
(( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
|
||||
((__WM__) == FMAC_THRESHOLD_2)? 2U: \
|
||||
((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
|
||||
((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
|
||||
((__WM__) == FMAC_THRESHOLD_1))|| \
|
||||
((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/** @addtogroup FMAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac);
|
||||
HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac);
|
||||
|
||||
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
|
||||
pFMAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
|
||||
int16_t *pOutput, uint8_t OutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
|
||||
int16_t *pOutput, uint8_t OutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
|
||||
HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Callback functions *********************************************************/
|
||||
void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac);
|
||||
void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* IRQ handler management *****************************************************/
|
||||
void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FMAC_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac);
|
||||
uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FMAC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_FMAC_H */
|
||||
326
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
Normal file
326
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
Normal file
@@ -0,0 +1,326 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_GPIO_H
|
||||
#define STM32G4xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0U,
|
||||
GPIO_PIN_SET
|
||||
} GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIO_pins GPIO pins
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode GPIO mode
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0x00WX00YZ
|
||||
* - W : EXTI trigger detection on 3 bits
|
||||
* - X : EXTI mode (IT or Event) on 2 bits
|
||||
* - Y : Output type (Push Pull or Open Drain) on 1 bit
|
||||
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed GPIO speed
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 5 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< range 50 MHz to 120 MHz, please refer to the product datasheet */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull GPIO pull
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_Pos 0U
|
||||
#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
|
||||
#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
|
||||
#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
|
||||
#define MODE_AF (0x2UL << GPIO_MODE_Pos)
|
||||
#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
|
||||
#define OUTPUT_TYPE_Pos 4U
|
||||
#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
|
||||
#define EXTI_MODE_Pos 16U
|
||||
#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
|
||||
#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
|
||||
#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
|
||||
#define TRIGGER_MODE_Pos 20U
|
||||
#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
|
||||
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
|
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
|
||||
|
||||
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
|
||||
((__PULL__) == GPIO_PULLUP) || \
|
||||
((__PULL__) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extended module */
|
||||
#include "stm32g4xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @brief GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_GPIO_H */
|
||||
|
||||
340
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
Normal file
340
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
Normal file
@@ -0,0 +1,340 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_GPIO_EX_H
|
||||
#define STM32G4xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @brief GPIO Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#if defined(TIM5)
|
||||
#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
|
||||
#endif /* TIM5 */
|
||||
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM17_COMP1 ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#if defined(TIM5)
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
#endif /* TIM5 */
|
||||
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
|
||||
#if defined(TIM20)
|
||||
#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
|
||||
#endif /* TIM20 */
|
||||
#define GPIO_AF2_TIM1_COMP1 ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM15_COMP1 ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16_COMP1 ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */
|
||||
#if defined(TIM20)
|
||||
#define GPIO_AF2_TIM20_COMP1 ((uint8_t)0x02) /* TIM20/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM20_COMP2 ((uint8_t)0x02) /* TIM20/COMP2 Break in Alternate Function mapping */
|
||||
#endif /* TIM20 */
|
||||
#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
|
||||
#if defined(TIM20)
|
||||
#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */
|
||||
#endif /* TIM20 */
|
||||
#define GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
|
||||
#if defined(I2C4)
|
||||
#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
|
||||
#endif /* I2C4 */
|
||||
#if defined(HRTIM1)
|
||||
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
|
||||
#endif /* HRTIM1 */
|
||||
#if defined(QUADSPI)
|
||||
#define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */
|
||||
#endif /* QUADSPI */
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
|
||||
#define GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF4_TIM8_COMP1 ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
|
||||
#if defined(I2C4)
|
||||
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
|
||||
#endif /* I2C4 */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
|
||||
#if defined(SPI4)
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
|
||||
#endif /* SPI4 */
|
||||
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM8_COMP1 ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
|
||||
#if defined(UART5)
|
||||
#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
|
||||
#endif /* UART5 */
|
||||
#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
|
||||
#if defined(TIM5)
|
||||
#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */
|
||||
#endif /* TIM5 */
|
||||
#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
|
||||
#if defined(TIM20)
|
||||
#define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */
|
||||
#endif /* TIM20 */
|
||||
#define GPIO_AF6_TIM1_COMP1 ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM1_COMP2 ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */
|
||||
#define GPIO_AF6_TIM8_COMP2 ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */
|
||||
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
|
||||
#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#if defined(COMP5)
|
||||
#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
|
||||
#endif /* COMP5 */
|
||||
#if defined(COMP6)
|
||||
#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
|
||||
#endif /* COMP6 */
|
||||
#if defined(COMP7)
|
||||
#define GPIO_AF7_COMP7 ((uint8_t)0x07) /* COMP7 Alternate Function mapping */
|
||||
#endif /* COMP7 */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
|
||||
#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
|
||||
#if defined(COMP5)
|
||||
#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
|
||||
#endif /* COMP5 */
|
||||
#if defined(COMP6)
|
||||
#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
|
||||
#endif /* COMP6 */
|
||||
#if defined(COMP7)
|
||||
#define GPIO_AF8_COMP7 ((uint8_t)0x08) /* COMP7 Alternate Function mapping */
|
||||
#endif /* COMP7 */
|
||||
#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
|
||||
#if defined(I2C4)
|
||||
#define GPIO_AF8_I2C4 ((uint8_t)0x08) /* I2C4 Alternate Function mapping */
|
||||
#endif /* I2C4 */
|
||||
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
|
||||
#if defined(UART5)
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
|
||||
#endif /* UART5 */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM15_COMP1 ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
|
||||
#if defined(FDCAN2)
|
||||
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
|
||||
#endif /* FDCAN2 */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM8_COMP2 ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */
|
||||
#define GPIO_AF10_TIM17_COMP1 ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */
|
||||
#if defined(QUADSPI)
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_FDCAN1 ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */
|
||||
#if defined(FDCAN3)
|
||||
#define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */
|
||||
#endif /* FDCAN3 */
|
||||
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
|
||||
#if defined(HRTIM1)
|
||||
#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
|
||||
#endif /* HRTIM1 */
|
||||
#if defined(FMC_BANK1)
|
||||
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
|
||||
#endif /* FMC_BANK1 */
|
||||
#define GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#if defined(HRTIM1)
|
||||
#define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */
|
||||
#endif /* HRTIM1 */
|
||||
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */
|
||||
#define GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */
|
||||
#define GPIO_AF14_UART4 ((uint8_t)0x0E) /* UART4 Alternate Function mapping */
|
||||
#if defined(UART5)
|
||||
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
|
||||
#endif /* UART5 */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
|
||||
((__GPIOx__) == (GPIOB))? 1UL :\
|
||||
((__GPIOx__) == (GPIOC))? 2UL :\
|
||||
((__GPIOx__) == (GPIOD))? 3UL :\
|
||||
((__GPIOx__) == (GPIOE))? 4UL :\
|
||||
((__GPIOx__) == (GPIOF))? 5UL : 6UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_GPIO_EX_H */
|
||||
|
||||
5153
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h
Normal file
5153
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h
Normal file
File diff suppressed because it is too large
Load Diff
838
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h
Normal file
838
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h
Normal file
@@ -0,0 +1,838 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_I2C_H
|
||||
#define STM32G4xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization section
|
||||
in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
||||
mode is selected.
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 Peripheral initialization status\n
|
||||
* 0 : Reset (peripheral not initialized)\n
|
||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
/*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||
|
||||
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
|
||||
/*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
|
||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32g4xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
|
||||
>> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
|
||||
>> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
|
||||
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32g4xx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32G4xx_HAL_I2C_H */
|
||||
190
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h
Normal file
190
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h
Normal file
@@ -0,0 +1,190 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_I2C_EX_H
|
||||
#define STM32G4xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
#if defined(SYSCFG_CFGR1_I2C3_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C3_FMP */
|
||||
#if defined(SYSCFG_CFGR1_I2C4_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C4_FMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#if defined (I2C3)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
|
||||
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
|
||||
#else
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
|
||||
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
|
||||
#endif /* I2C3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32g4xx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_I2C_EX_H */
|
||||
554
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2s.h
Normal file
554
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2s.h
Normal file
@@ -0,0 +1,554 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_I2S_H
|
||||
#define STM32G4xx_HAL_I2S_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
#if defined(SPI_I2S_SUPPORT)
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Types I2S Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
} I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
|
||||
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
|
||||
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
|
||||
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
|
||||
} HAL_I2S_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __I2S_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
{
|
||||
SPI_TypeDef *Instance; /*!< I2S registers base address */
|
||||
|
||||
I2S_InitTypeDef Init; /*!< I2S communication parameters */
|
||||
|
||||
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
|
||||
|
||||
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
|
||||
|
||||
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
|
||||
|
||||
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2S Error code
|
||||
This parameter can be a value of @ref I2S_Error */
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
|
||||
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
|
||||
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
|
||||
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
|
||||
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
|
||||
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
} I2S_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
/**
|
||||
* @brief HAL I2S Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
|
||||
HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
|
||||
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
|
||||
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
|
||||
HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
|
||||
HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
|
||||
HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2S_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2S Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
|
||||
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup I2S_Error I2S Error
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
|
||||
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
|
||||
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
|
||||
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
|
||||
#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode I2S Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX (0x00000000U)
|
||||
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
|
||||
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
|
||||
#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard I2S Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS (0x00000000U)
|
||||
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
|
||||
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
|
||||
#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
|
||||
#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format I2S Data Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B (0x00000000U)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
|
||||
#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
|
||||
#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output I2S MCLK Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K (192000U)
|
||||
#define I2S_AUDIOFREQ_96K (96000U)
|
||||
#define I2S_AUDIOFREQ_48K (48000U)
|
||||
#define I2S_AUDIOFREQ_44K (44100U)
|
||||
#define I2S_AUDIOFREQ_32K (32000U)
|
||||
#define I2S_AUDIOFREQ_22K (22050U)
|
||||
#define I2S_AUDIOFREQ_16K (16000U)
|
||||
#define I2S_AUDIOFREQ_11K (11025U)
|
||||
#define I2S_AUDIOFREQ_8K (8000U)
|
||||
#define I2S_AUDIOFREQ_DEFAULT (2U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW (0x00000000U)
|
||||
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_IT_TXE SPI_CR2_TXEIE
|
||||
#define I2S_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define I2S_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_TXE SPI_SR_TXE
|
||||
#define I2S_FLAG_RXNE SPI_SR_RXNE
|
||||
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||
#define I2S_FLAG_OVR SPI_SR_OVR
|
||||
#define I2S_FLAG_FRE SPI_SR_FRE
|
||||
|
||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_BSY SPI_SR_BSY
|
||||
|
||||
#define I2S_FLAG_MASK (SPI_SR_RXNE\
|
||||
| SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_macros I2S Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2S handle state
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
||||
|
||||
/** @brief Disable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
||||
|
||||
/** @brief Enable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
||||
|
||||
/** @brief Disable the specified I2S interrupts.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_FRE: Frame error flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2S OVR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
}while(0U)
|
||||
/** @brief Clears the I2S UDR pending flag.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
|
||||
__IO uint32_t tmpreg_udr = 0x00U;\
|
||||
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
|
||||
UNUSED(tmpreg_udr); \
|
||||
}while(0U)
|
||||
/** @brief Flush the I2S DR Register.
|
||||
* @param __HANDLE__ specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
|
||||
__IO uint32_t tmpreg_dr = 0x00U;\
|
||||
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
|
||||
UNUSED(tmpreg_dr); \
|
||||
}while(0U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2S_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
|
||||
pI2S_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
||||
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of I2S SR register.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun error flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
|
||||
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of I2S CR2 register.
|
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval SET or RESET.
|
||||
*/
|
||||
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks if I2S Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the I2S Mode.
|
||||
* This parameter can be a value of @ref I2S_Mode
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
|
||||
((__MODE__) == I2S_MODE_SLAVE_RX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_TX) || \
|
||||
((__MODE__) == I2S_MODE_MASTER_RX))
|
||||
|
||||
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
|
||||
((__STANDARD__) == I2S_STANDARD_MSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_LSB) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
|
||||
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
|
||||
|
||||
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
|
||||
((__FORMAT__) == I2S_DATAFORMAT_32B))
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
|
||||
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
|
||||
|
||||
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
|
||||
* @param __CPOL__ specifies the I2S serial clock steady state.
|
||||
* This parameter can be a value of @ref I2S_Clock_Polarity
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
|
||||
((__CPOL__) == I2S_CPOL_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SPI_I2S_SUPPORT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_I2S_H */
|
||||
|
||||
892
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda.h
Normal file
892
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda.h
Normal file
@@ -0,0 +1,892 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_IRDA_H
|
||||
#define STM32G4xx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
|
||||
where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDAEx_Word_Length */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Transfer_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
|
||||
to achieve low-power frequency.
|
||||
@note Prescaler value 0 is forbidden */
|
||||
|
||||
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
|
||||
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source.
|
||||
This parameter can be a value of @ref IRDA_ClockPrescaler. */
|
||||
|
||||
} IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates:
|
||||
* gState and RxState (see @ref IRDA_State_Definition).
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (Peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef uint32_t HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA clock sources definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
|
||||
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
|
||||
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
||||
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
|
||||
IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
|
||||
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
|
||||
} IRDA_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __IRDA_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
|
||||
|
||||
const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /*!< USART RX RDR register mask */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< IRDA Error code */
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
|
||||
|
||||
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
|
||||
|
||||
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
|
||||
|
||||
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
|
||||
|
||||
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
|
||||
|
||||
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
|
||||
|
||||
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
|
||||
|
||||
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
} IRDA_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL IRDA Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
|
||||
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
|
||||
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
|
||||
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
|
||||
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
|
||||
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
|
||||
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
|
||||
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
|
||||
|
||||
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
|
||||
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
|
||||
|
||||
} HAL_IRDA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA Callback pointer definition
|
||||
*/
|
||||
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
|
||||
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State_Definition IRDA State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between
|
||||
gState and RxState values */
|
||||
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
|
||||
#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
|
||||
#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
|
||||
#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
|
||||
#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
|
||||
#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
|
||||
#define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
|
||||
#define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
|
||||
#define IRDA_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
|
||||
#define IRDA_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
|
||||
#define IRDA_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
|
||||
#define IRDA_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
|
||||
#define IRDA_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
|
||||
#define IRDA_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
|
||||
#define IRDA_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
|
||||
#define IRDA_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
|
||||
#define IRDA_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State IRDA State
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
|
||||
#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
|
||||
#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
|
||||
#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
|
||||
#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
|
||||
#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
|
||||
#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
|
||||
#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
|
||||
#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
|
||||
#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
|
||||
#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
|
||||
#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */
|
||||
#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
|
||||
#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */
|
||||
#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
|
||||
#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
|
||||
#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
|
||||
#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
|
||||
#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
|
||||
#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
|
||||
#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
|
||||
#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
|
||||
|
||||
/* Elements values convention: 000000000XXYYYYYb
|
||||
- YYYYY : Interrupt source position in the XX register (5bits)
|
||||
- XX : Interrupt source register (2bits)
|
||||
- 01: CR1 register
|
||||
- 10: CR2 register
|
||||
- 11: CR3 register */
|
||||
#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
|
||||
|
||||
/* Elements values convention: 0000ZZZZ00000000b
|
||||
- ZZZZ : Flag position in the ISR register(4bits) */
|
||||
#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
|
||||
#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
|
||||
#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
|
||||
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
|
||||
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
|
||||
#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
|
||||
#define IRDA_CR_POS 5U /*!< IRDA control register position */
|
||||
#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
|
||||
#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle state.
|
||||
* @param __HANDLE__ IRDA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
} while(0U)
|
||||
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Flush the IRDA DR register.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
|
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Clear the specified IRDA pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF
|
||||
* @arg @ref IRDA_CLEAR_FEF
|
||||
* @arg @ref IRDA_CLEAR_NEF
|
||||
* @arg @ref IRDA_CLEAR_OREF
|
||||
* @arg @ref IRDA_CLEAR_TCF
|
||||
* @arg @ref IRDA_CLEAR_IDLEF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Clear the IRDA PE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
|
||||
|
||||
|
||||
/** @brief Clear the IRDA FE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
|
||||
|
||||
/** @brief Clear the IRDA NE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
|
||||
|
||||
/** @brief Clear the IRDA ORE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
|
||||
|
||||
/** @brief Clear the IRDA IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
|
||||
|
||||
/** @brief Check whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_BUSY Busy flag
|
||||
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
|
||||
* @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
|
||||
* @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
|
||||
* @arg @ref IRDA_FLAG_TC Transmission Complete flag
|
||||
* @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
|
||||
* @arg @ref IRDA_FLAG_ORE OverRun Error flag
|
||||
* @arg @ref IRDA_FLAG_NE Noise Error flag
|
||||
* @arg @ref IRDA_FLAG_FE Framing Error flag
|
||||
* @arg @ref IRDA_FLAG_PE Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))):\
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
|
||||
((__HANDLE__)->Instance->CR1 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
|
||||
((__HANDLE__)->Instance->CR2 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << \
|
||||
((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ORE OverRun Error interrupt
|
||||
* @arg @ref IRDA_IT_NE Noise Error interrupt
|
||||
* @arg @ref IRDA_IT_FE Framing Error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
|
||||
((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
|
||||
& IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
|
||||
& (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
|
||||
/** @brief Set a specific IRDA request flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __REQ__ specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
|
||||
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
|
||||
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
/** @brief Enable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Disable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
|
||||
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
|
||||
* @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
|
||||
|
||||
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
|
||||
* @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
|
||||
|
||||
/** @brief Ensure that IRDA frame parity is valid.
|
||||
* @param __PARITY__ IRDA frame parity.
|
||||
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
|
||||
((__PARITY__) == IRDA_PARITY_EVEN) || \
|
||||
((__PARITY__) == IRDA_PARITY_ODD))
|
||||
|
||||
/** @brief Ensure that IRDA communication mode is valid.
|
||||
* @param __MODE__ IRDA communication mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
|
||||
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
|
||||
|
||||
/** @brief Ensure that IRDA power mode is valid.
|
||||
* @param __MODE__ IRDA power mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((__MODE__) == IRDA_POWERMODE_NORMAL))
|
||||
|
||||
/** @brief Ensure that IRDA clock Prescaler is valid.
|
||||
* @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
|
||||
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
|
||||
|
||||
/** @brief Ensure that IRDA state is valid.
|
||||
* @param __STATE__ IRDA state mode.
|
||||
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
|
||||
((__STATE__) == IRDA_STATE_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA associated UART/USART mode is valid.
|
||||
* @param __MODE__ IRDA associated UART/USART mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
|
||||
((__MODE__) == IRDA_MODE_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA sampling rate is valid.
|
||||
* @param __ONEBIT__ IRDA sampling rate.
|
||||
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
|
||||
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA DMA TX mode is valid.
|
||||
* @param __DMATX__ IRDA DMA TX mode.
|
||||
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
|
||||
((__DMATX__) == IRDA_DMA_TX_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA DMA RX mode is valid.
|
||||
* @param __DMARX__ IRDA DMA RX mode.
|
||||
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
|
||||
((__DMARX__) == IRDA_DMA_RX_ENABLE))
|
||||
|
||||
/** @brief Ensure that IRDA request is valid.
|
||||
* @param __PARAM__ IRDA request.
|
||||
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
|
||||
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
|
||||
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include IRDA HAL Extended module */
|
||||
#include "stm32g4xx_hal_irda_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
|
||||
pIRDA_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_IRDA_H */
|
||||
|
||||
635
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda_ex.h
Normal file
635
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda_ex.h
Normal file
@@ -0,0 +1,635 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_IRDA_EX_H
|
||||
#define STM32G4xx_HAL_IRDA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx IRDAEx
|
||||
* @brief IRDA Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
|
||||
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
|
||||
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the IRDA clock source.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#if defined(UART5) && !defined(USART3)
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART5) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART5_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART5CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif defined(UART5) && defined(USART3)
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART5) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART5_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART5CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif defined(UART4) && !defined(USART3)
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif defined(UART4) && defined(USART3)
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#elif defined(USART3)
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#else
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
#endif /* UART5 && !USART3 */
|
||||
|
||||
/** @brief Compute the mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003FU ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Ensure that IRDA frame length is valid.
|
||||
* @param __LENGTH__ IRDA frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_9B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_IRDA_EX_H */
|
||||
|
||||
237
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_iwdg.h
Normal file
237
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_iwdg.h
Normal file
@@ -0,0 +1,237 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_IWDG_H
|
||||
#define STM32G4xx_HAL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||
This parameter can be a value of @ref IWDG_Prescaler */
|
||||
|
||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
} IWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
} IWDG_HandleTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Window_option IWDG Window option
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the IWDG peripheral.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Key Register BitMask
|
||||
*/
|
||||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
|
||||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG prescaler value.
|
||||
* @param __PRESCALER__ IWDG prescaler value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_256))
|
||||
|
||||
/**
|
||||
* @brief Check IWDG reload value.
|
||||
* @param __RELOAD__ IWDG reload value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG window value.
|
||||
* @param __WINDOW__ IWDG window value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_IWDG_H */
|
||||
877
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h
Normal file
877
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h
Normal file
@@ -0,0 +1,877 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_lptim.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of LPTIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_LPTIM_H
|
||||
#define STM32G4xx_HAL_LPTIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup LPTIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR2_IM37 /*!< External interrupt line 37 Connected to the LPTIM EXTI Line */
|
||||
|
||||
/**
|
||||
* @brief LPTIM Clock configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Selects the clock source.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Source */
|
||||
|
||||
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
|
||||
|
||||
} LPTIM_ClockConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Clock configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
|
||||
if the ULPTIM input is selected.
|
||||
Note: This parameter is used only when Ultra low power clock source is used.
|
||||
Note: If the polarity is configured on 'both edges', an auxiliary clock
|
||||
(one of the Low power oscillator) must be active.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Polarity */
|
||||
|
||||
uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
|
||||
Note: This parameter is used only when Ultra low power clock source is used.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
|
||||
|
||||
} LPTIM_ULPClockConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Trigger configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Selects the Trigger source.
|
||||
This parameter can be a value of @ref LPTIM_Trigger_Source */
|
||||
|
||||
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
|
||||
Note: This parameter is used only when an external trigger is used.
|
||||
This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
|
||||
|
||||
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
|
||||
Note: This parameter is used only when an external trigger is used.
|
||||
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
|
||||
} LPTIM_TriggerConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
|
||||
|
||||
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
|
||||
|
||||
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
|
||||
|
||||
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
|
||||
This parameter can be a value of @ref LPTIM_Output_Polarity */
|
||||
|
||||
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
|
||||
values is done immediately or after the end of current period.
|
||||
This parameter can be a value of @ref LPTIM_Updating_Mode */
|
||||
|
||||
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
|
||||
or each external event.
|
||||
This parameter can be a value of @ref LPTIM_Counter_Source */
|
||||
|
||||
uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
|
||||
This parameter can be a value of @ref LPTIM_Input1_Source */
|
||||
|
||||
uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
|
||||
Note: This parameter is used only for encoder feature so is used only
|
||||
for LPTIM1 instance.
|
||||
This parameter can be a value of @ref LPTIM_Input2_Source */
|
||||
} LPTIM_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL LPTIM State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
|
||||
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
||||
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
|
||||
} HAL_LPTIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __LPTIM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
{
|
||||
LPTIM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
|
||||
|
||||
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< LPTIM locking object */
|
||||
|
||||
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
|
||||
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
|
||||
void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
|
||||
void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
|
||||
void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
|
||||
void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
|
||||
void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
|
||||
void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
|
||||
void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
|
||||
void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
} LPTIM_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL LPTIM Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
|
||||
HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
|
||||
HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
|
||||
HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
|
||||
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
|
||||
HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
|
||||
HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
|
||||
HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
|
||||
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
|
||||
} HAL_LPTIM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL TIM Callback pointer definition
|
||||
*/
|
||||
typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
|
||||
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
|
||||
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_PRESCALER_DIV1 0x00000000U
|
||||
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
|
||||
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
|
||||
#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
|
||||
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
|
||||
#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
|
||||
#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
|
||||
#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
|
||||
#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
|
||||
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
|
||||
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
|
||||
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
|
||||
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
|
||||
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
|
||||
#define LPTIM_TRIGSOURCE_0 0x00000000U
|
||||
#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
|
||||
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
|
||||
#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
|
||||
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
|
||||
#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
|
||||
#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
|
||||
#define LPTIM_TRIGSOURCE_7 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
|
||||
#define LPTIM_TRIGSOURCE_8 LPTIM_CFGR_TRIGSEL_3
|
||||
#define LPTIM_TRIGSOURCE_9 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_3)
|
||||
#define LPTIM_TRIGSOURCE_10 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
|
||||
#define LPTIM_TRIGSOURCE_11 (LPTIM_CFGR_TRIGSEL_0 |LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
|
||||
#define LPTIM_TRIGSOURCE_12 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_3)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
|
||||
#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
|
||||
#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
|
||||
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
|
||||
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
|
||||
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
|
||||
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U
|
||||
#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_IN1_0
|
||||
#define LPTIM_INPUT1SOURCE_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
|
||||
#if defined(COMP5)
|
||||
#define LPTIM_INPUT1SOURCE_COMP5 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_0)
|
||||
#endif /* COMP5 */
|
||||
#if defined(COMP7)
|
||||
#define LPTIM_INPUT1SOURCE_COMP7 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
|
||||
#endif /* COMP7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U
|
||||
#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_IN2_0
|
||||
#define LPTIM_INPUT2SOURCE_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
|
||||
#if defined(COMP6)
|
||||
#define LPTIM_INPUT2SOURCE_COMP6 (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_0)
|
||||
#endif /* COMP6 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
|
||||
#define LPTIM_FLAG_UP LPTIM_ISR_UP
|
||||
#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
|
||||
#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
|
||||
#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
|
||||
#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
|
||||
#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
|
||||
#define LPTIM_IT_UP LPTIM_IER_UPIE
|
||||
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
|
||||
#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
|
||||
#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
|
||||
#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
|
||||
#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset LPTIM handle state.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the LPTIM peripheral.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Disable the LPTIM peripheral.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @note The following sequence is required to solve LPTIM disable HW limitation.
|
||||
* Please check Errata Sheet ES0335 for more details under "MCU may remain
|
||||
* stuck in LPTIM interrupt when entering Stop mode" section.
|
||||
* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
|
||||
* check for TIMEOUT.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
|
||||
|
||||
/**
|
||||
* @brief Start the LPTIM peripheral in Continuous mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
|
||||
/**
|
||||
* @brief Start the LPTIM peripheral in single mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
|
||||
|
||||
/**
|
||||
* @brief Reset the LPTIM Counter register in synchronous mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
|
||||
|
||||
/**
|
||||
* @brief Reset after read of the LPTIM Counter register in asynchronous mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
|
||||
|
||||
/**
|
||||
* @brief Write the passed parameter in the Autoreload register.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Autoreload value
|
||||
* This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
|
||||
* @retval None
|
||||
* @note The ARR register can only be modified when the LPTIM instance is enabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Write the passed parameter in the Compare register.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Compare value
|
||||
* @retval None
|
||||
* @note The CMP register can only be modified when the LPTIM instance is enabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified LPTIM flag is set or not.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __FLAG__ LPTIM flag to check
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
||||
* @retval The state of the specified flag (SET or RESET).
|
||||
*/
|
||||
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified LPTIM flag.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __FLAG__ LPTIM flag to clear.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified LPTIM interrupt.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __INTERRUPT__ LPTIM interrupt to set.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified LPTIM interrupt.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __INTERRUPT__ LPTIM interrupt to set.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified LPTIM interrupt source is enabled or not.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __INTERRUPT__ LPTIM interrupt to check.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval Interrupt status.
|
||||
*/
|
||||
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR2\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR2\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR2\
|
||||
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR2\
|
||||
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions.
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* MSP functions *************************************************************/
|
||||
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group2
|
||||
* @brief Start-Stop operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Start/Stop operation functions *********************************************/
|
||||
/* ################################# PWM Mode ################################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################# One Pulse Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################## Set once Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################### Encoder Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################# Time out Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################## Counter Mode ###############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group3
|
||||
* @brief Read operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Reading operation functions ************************************************/
|
||||
uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group4
|
||||
* @brief LPTIM IRQ handler and callback functions.
|
||||
* @{
|
||||
*/
|
||||
/* LPTIM IRQ functions *******************************************************/
|
||||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* CallBack functions ********************************************************/
|
||||
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
|
||||
pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Group5
|
||||
* @brief Peripheral State functions.
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Types LPTIM Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
|
||||
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
|
||||
|
||||
|
||||
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
|
||||
|
||||
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
|
||||
|
||||
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
|
||||
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
|
||||
|
||||
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
|
||||
|
||||
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
|
||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
|
||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
|
||||
|
||||
#if defined(STM32G414xx) || defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32G474xx) || defined(STM32G484xx)
|
||||
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_9) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_10)|| \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_11)|| \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_12))
|
||||
#else
|
||||
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_9))
|
||||
#endif /* STM32G414xx || STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */
|
||||
|
||||
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
|
||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
|
||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
|
||||
|
||||
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
|
||||
|
||||
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
|
||||
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
|
||||
|
||||
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
|
||||
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
|
||||
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
|
||||
((__PERIOD__) <= 0x0000FFFFUL))
|
||||
|
||||
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
|
||||
|
||||
#if defined(COMP5) && defined(COMP6) && defined(COMP7)
|
||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP5) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP7))))
|
||||
#else
|
||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3))))
|
||||
#endif /* COMP5 && COMP6 && COMP7 */
|
||||
|
||||
#if defined(COMP5) && defined(COMP6) && defined(COMP7)
|
||||
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
(((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \
|
||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4) || \
|
||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP6)))
|
||||
#else
|
||||
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
(((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \
|
||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4)))
|
||||
#endif /* COMP5 && COMP6 && COMP7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_LPTIM_H */
|
||||
378
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nand.h
Normal file
378
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nand.h
Normal file
@@ -0,0 +1,378 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_nand.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of NAND HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_NAND_H
|
||||
#define STM32G4xx_HAL_NAND_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FMC_BANK3)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_ll_fmc.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Exported_Types NAND Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL NAND State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
|
||||
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
|
||||
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
|
||||
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
|
||||
} HAL_NAND_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory electronic signature Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*<! NAND memory electronic signature maker and device IDs */
|
||||
|
||||
uint8_t Maker_Id;
|
||||
|
||||
uint8_t Device_Id;
|
||||
|
||||
uint8_t Third_Id;
|
||||
|
||||
uint8_t Fourth_Id;
|
||||
} NAND_IDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory address Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Page; /*!< NAND memory Page address */
|
||||
|
||||
uint16_t Plane; /*!< NAND memory Zone address */
|
||||
|
||||
uint16_t Block; /*!< NAND memory Block address */
|
||||
|
||||
} NAND_AddressTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory info Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
|
||||
for 8 bits addressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
|
||||
for 8 bits addressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
|
||||
|
||||
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
|
||||
|
||||
uint32_t PlaneNbr; /*!< NAND memory number of planes */
|
||||
|
||||
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
|
||||
|
||||
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
|
||||
parameter is mandatory for some NAND parts after the read
|
||||
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
|
||||
This parameter could be ENABLE or DISABLE
|
||||
Please check the Read Mode sequence in the NAND device datasheet */
|
||||
} NAND_DeviceConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __NAND_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
{
|
||||
FMC_NAND_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< NAND locking object */
|
||||
|
||||
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
|
||||
|
||||
NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
|
||||
void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
} NAND_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL NAND Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
|
||||
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
|
||||
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
|
||||
} HAL_NAND_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL NAND Callback pointer definition
|
||||
*/
|
||||
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Exported_Macros NAND Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset NAND handle state
|
||||
* @param __HANDLE__ specifies the NAND handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_NAND_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
|
||||
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
|
||||
|
||||
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint8_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint16_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
||||
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
|
||||
|
||||
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
|
||||
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
||||
/* NAND callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
|
||||
pNAND_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
|
||||
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NAND Control functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
|
||||
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
|
||||
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* NAND State functions *******************************************************/
|
||||
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
|
||||
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup NAND_Private_Constants NAND Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define NAND_DEVICE 0x80000000UL
|
||||
#define NAND_WRITE_TIMEOUT 0x01000000UL
|
||||
|
||||
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
|
||||
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
|
||||
|
||||
#define NAND_CMD_AREA_A ((uint8_t)0x00)
|
||||
#define NAND_CMD_AREA_B ((uint8_t)0x01)
|
||||
#define NAND_CMD_AREA_C ((uint8_t)0x50)
|
||||
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
|
||||
|
||||
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
|
||||
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
|
||||
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
|
||||
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
|
||||
#define NAND_CMD_READID ((uint8_t)0x90)
|
||||
#define NAND_CMD_STATUS ((uint8_t)0x70)
|
||||
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
|
||||
#define NAND_CMD_RESET ((uint8_t)0xFF)
|
||||
|
||||
/* NAND memory status */
|
||||
#define NAND_VALID_ADDRESS 0x00000100UL
|
||||
#define NAND_INVALID_ADDRESS 0x00000200UL
|
||||
#define NAND_TIMEOUT_ERROR 0x00000400UL
|
||||
#define NAND_BUSY 0x00000000UL
|
||||
#define NAND_ERROR 0x00000001UL
|
||||
#define NAND_READY 0x00000040UL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Private_Macros NAND Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief NAND memory address computation.
|
||||
* @param __ADDRESS__ NAND memory address.
|
||||
* @param __HANDLE__ NAND handle.
|
||||
* @retval NAND Raw address value
|
||||
*/
|
||||
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
|
||||
(((__ADDRESS__)->Block + \
|
||||
(((__ADDRESS__)->Plane) * \
|
||||
((__HANDLE__)->Config.PlaneSize))) * \
|
||||
((__HANDLE__)->Config.BlockSize)))
|
||||
|
||||
/**
|
||||
* @brief NAND memory Column address computation.
|
||||
* @param __HANDLE__ NAND handle.
|
||||
* @retval NAND Raw address value
|
||||
*/
|
||||
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
|
||||
|
||||
/**
|
||||
* @brief NAND memory address cycling.
|
||||
* @param __ADDRESS__ NAND memory address.
|
||||
* @retval NAND address cycling value.
|
||||
*/
|
||||
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
|
||||
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
|
||||
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
|
||||
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
|
||||
|
||||
/**
|
||||
* @brief NAND memory Columns cycling.
|
||||
* @param __ADDRESS__ NAND memory address.
|
||||
* @retval NAND Column address cycling value.
|
||||
*/
|
||||
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
|
||||
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FMC_BANK3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_NAND_H */
|
||||
326
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nor.h
Normal file
326
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nor.h
Normal file
@@ -0,0 +1,326 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_nor.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of NOR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_NOR_H
|
||||
#define STM32G4xx_HAL_NOR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_ll_fmc.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/** @defgroup NOR_Exported_Types NOR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL SRAM State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
|
||||
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
|
||||
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
|
||||
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
|
||||
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
|
||||
} HAL_NOR_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NOR Status typedef
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_STATUS_SUCCESS = 0U,
|
||||
HAL_NOR_STATUS_ONGOING,
|
||||
HAL_NOR_STATUS_ERROR,
|
||||
HAL_NOR_STATUS_TIMEOUT
|
||||
} HAL_NOR_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NOR ID typedef
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
|
||||
|
||||
uint16_t Device_Code1;
|
||||
|
||||
uint16_t Device_Code2;
|
||||
|
||||
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
|
||||
These codes can be accessed by performing read operations with specific
|
||||
control signals and addresses set.They can also be accessed by issuing
|
||||
an Auto Select command */
|
||||
} NOR_IDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NOR CFI typedef
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*!< Defines the information stored in the memory's Common flash interface
|
||||
which contains a description of various electrical and timing parameters,
|
||||
density information and functions supported by the memory */
|
||||
|
||||
uint16_t CFI_1;
|
||||
|
||||
uint16_t CFI_2;
|
||||
|
||||
uint16_t CFI_3;
|
||||
|
||||
uint16_t CFI_4;
|
||||
} NOR_CFITypeDef;
|
||||
|
||||
/**
|
||||
* @brief NOR handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __NOR_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
|
||||
{
|
||||
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||
|
||||
FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< NOR locking object */
|
||||
|
||||
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
|
||||
|
||||
uint32_t CommandSet; /*!< NOR algorithm command set and control */
|
||||
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
} NOR_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL NOR Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
|
||||
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
|
||||
} HAL_NOR_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL NOR Callback pointer definition
|
||||
*/
|
||||
typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup NOR_Exported_Macros NOR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset NOR handle state
|
||||
* @param __HANDLE__ specifies the NOR handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_NOR_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup NOR_Exported_Functions NOR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
|
||||
FMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
|
||||
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
|
||||
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
||||
uint32_t uwBufferSize);
|
||||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
|
||||
uint32_t uwBufferSize);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
|
||||
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
|
||||
|
||||
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
|
||||
/* NOR callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
|
||||
pNOR_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
|
||||
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NOR Control functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NOR State functions ********************************************************/
|
||||
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
|
||||
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup NOR_Private_Constants NOR Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* NOR device IDs addresses */
|
||||
#define MC_ADDRESS ((uint16_t)0x0000)
|
||||
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
|
||||
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
|
||||
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
|
||||
|
||||
/* NOR CFI IDs addresses */
|
||||
#define CFI1_ADDRESS ((uint16_t)0x0061)
|
||||
#define CFI2_ADDRESS ((uint16_t)0x0062)
|
||||
#define CFI3_ADDRESS ((uint16_t)0x0063)
|
||||
#define CFI4_ADDRESS ((uint16_t)0x0064)
|
||||
|
||||
/* NOR operation wait timeout */
|
||||
#define NOR_TMEOUT ((uint16_t)0xFFFF)
|
||||
|
||||
/* NOR memory data width */
|
||||
#define NOR_MEMORY_8B ((uint8_t)0x00)
|
||||
#define NOR_MEMORY_16B ((uint8_t)0x01)
|
||||
|
||||
/* NOR memory device read/write start address */
|
||||
#define NOR_MEMORY_ADRESS1 (0x60000000U)
|
||||
#define NOR_MEMORY_ADRESS2 (0x64000000U)
|
||||
#define NOR_MEMORY_ADRESS3 (0x68000000U)
|
||||
#define NOR_MEMORY_ADRESS4 (0x6C000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup NOR_Private_Macros NOR Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief NOR memory address shifting.
|
||||
* @param __NOR_ADDRESS NOR base address
|
||||
* @param __NOR_MEMORY_WIDTH_ NOR memory width
|
||||
* @param __ADDRESS__ NOR memory address
|
||||
* @retval NOR shifted address value
|
||||
*/
|
||||
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
|
||||
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
|
||||
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
|
||||
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
|
||||
|
||||
/**
|
||||
* @brief NOR memory write data to specified address.
|
||||
* @param __ADDRESS__ NOR memory address
|
||||
* @param __DATA__ Data to write
|
||||
* @retval None
|
||||
*/
|
||||
#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
|
||||
(*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
|
||||
__DSB(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_NOR_H */
|
||||
575
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp.h
Normal file
575
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp.h
Normal file
@@ -0,0 +1,575 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_opamp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of OPAMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_OPAMP_H
|
||||
#define STM32G4xx_HAL_OPAMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6)
|
||||
|
||||
/** @addtogroup OPAMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief OPAMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PowerMode; /*!< Specifies the power mode Normal or High Speed.
|
||||
This parameter must be a value of @ref OPAMP_PowerMode */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the OPAMP mode
|
||||
This parameter must be a value of @ref OPAMP_Mode
|
||||
mode is either Standalone, Follower or PGA */
|
||||
|
||||
uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & Pga modes
|
||||
- In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
|
||||
This parameter must be a value of @ref OPAMP_InvertingInput
|
||||
InvertingInput is either VINM0 or VINM1
|
||||
- In PGA mode: i.e when mode is OPAMP_PGA_MODE
|
||||
& in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
|
||||
This parameter is Not Applicable */
|
||||
|
||||
uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp:
|
||||
This parameter must be a value of @ref OPAMP_NonInvertingInput
|
||||
NonInvertingInput is either VINP0, VINP1, VINP2 or VINP3 */
|
||||
|
||||
FunctionalState InternalOutput; /*!< Specifies the configuration of the internal output from OPAMP to ADC.
|
||||
This parameter can be ENABLE or DISABLE
|
||||
Note: When this output is enabled, regular output to I/O is disabled */
|
||||
|
||||
uint32_t TimerControlledMuxmode; /*!< Specifies if the Timer controlled Mux mode is enabled or disabled
|
||||
This parameter must be a single value of @ref OPAMP_TimerControlledMuxmode
|
||||
or a combination of them to build a more complex switch scheme by
|
||||
using different timers */
|
||||
|
||||
uint32_t InvertingInputSecondary; /*!< Specifies the inverting input (secondary) of the opamp when
|
||||
TimerControlledMuxmode is enabled
|
||||
i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
|
||||
- In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
|
||||
This parameter must be a value of @ref OPAMP_InvertingInputSecondary
|
||||
InvertingInputSecondary is either VINM0 or VINM1
|
||||
- In PGA mode: i.e when mode is OPAMP_PGA_MODE
|
||||
& in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
|
||||
This parameter must be a value of @ref OPAMP_InvertingInputSecondary
|
||||
and is used to choose secondary mode (PGA or follower) */
|
||||
|
||||
uint32_t NonInvertingInputSecondary; /*!< Specifies the non inverting input (secondary) of the opamp when
|
||||
TimerControlledMuxmode is enabled
|
||||
i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
|
||||
This parameter must be a value of @ref OPAMP_NonInvertingInputSecondary
|
||||
NonInvertingInput is either VINP0, VINP1, VINP2 or VINP3 */
|
||||
|
||||
uint32_t PgaConnect; /*!< Specifies the inverting pin in PGA mode
|
||||
i.e. when mode is OPAMP_PGA_MODE
|
||||
This parameter must be a value of @ref OPAMP_PgaConnect
|
||||
Either: not connected, connected to VINM0
|
||||
In this last case, VINM0 can then be used to input signal (negative gain case
|
||||
with or without bias on VINPx) or to input bias (positive gain case with bias) */
|
||||
|
||||
uint32_t PgaGain; /*!< Specifies the gain in PGA mode
|
||||
i.e. when mode is OPAMP_PGA_MODE.
|
||||
This parameter must be a value of @ref OPAMP_PgaGain
|
||||
(2, 4, 8, 16, 32 or 64) for positive gain & (-1, -3 ,-7, -15, -31 or -63) for negative gain */
|
||||
|
||||
uint32_t UserTrimming; /*!< Specifies the trimming mode
|
||||
This parameter must be a value of @ref OPAMP_UserTrimming
|
||||
UserTrimming is either factory or user trimming */
|
||||
|
||||
uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS)
|
||||
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS)
|
||||
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
} OPAMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_OPAMP_STATE_RESET = 0x00000000UL, /*!< OPAMP is not yet Initialized */
|
||||
|
||||
HAL_OPAMP_STATE_READY = 0x00000001UL, /*!< OPAMP is initialized and ready for use */
|
||||
HAL_OPAMP_STATE_CALIBBUSY = 0x00000002UL, /*!< OPAMP is enabled in auto calibration mode */
|
||||
|
||||
HAL_OPAMP_STATE_BUSY = 0x00000004UL, /*!< OPAMP is enabled and running in normal mode */
|
||||
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005UL, /*!< OPAMP control register is locked
|
||||
only system reset allows reconfiguring the opamp. */
|
||||
|
||||
} HAL_OPAMP_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief OPAMP Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __OPAMP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
|
||||
OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
|
||||
HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
|
||||
|
||||
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __OPAMP_HandleTypeDef *hopamp);
|
||||
void (* MspDeInitCallback)(struct __OPAMP_HandleTypeDef *hopamp);
|
||||
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
|
||||
|
||||
} OPAMP_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief OPAMP_TrimmingValueTypeDef definition
|
||||
*/
|
||||
|
||||
typedef uint32_t OPAMP_TrimmingValueTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL OPAMP Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OPAMP_MSPINIT_CB_ID = 0x01UL, /*!< OPAMP MspInit Callback ID */
|
||||
HAL_OPAMP_MSPDEINIT_CB_ID = 0x02UL, /*!< OPAMP MspDeInit Callback ID */
|
||||
HAL_OPAMP_ALL_CB_ID = 0x03UL /*!< OPAMP All ID */
|
||||
} HAL_OPAMP_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL OPAMP Callback pointer definition
|
||||
*/
|
||||
typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
|
||||
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup OPAMP_Mode OPAMP Mode
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_STANDALONE_MODE (0x00000000UL) /*!< standalone mode */
|
||||
#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
|
||||
#define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL /*!< follower mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_NONINVERTINGINPUT_IO0 (0x00000000UL) /*!< Non inverting input connected to I/O VINP0
|
||||
(PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
#define OPAMP_NONINVERTINGINPUT_IO1 OPAMP_CSR_VPSEL_0 /*!< Non inverting input connected to I/O VINP1
|
||||
(PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
#define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< Non inverting input connected to I/O VINP2
|
||||
(PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
#define OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL /*!< Non inverting input connected to I/O VINP3
|
||||
(PD14 for OPAMP2) */
|
||||
#define OPAMP_NONINVERTINGINPUT_DAC OPAMP_CSR_VPSEL /*!< Non inverting input connected internally to DAC channel
|
||||
(DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_INVERTINGINPUT_IO0 (0x00000000UL) /*!< Inverting input connected to I/O VINM0
|
||||
(PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< Inverting input connected to I/0 VINM1
|
||||
(PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode
|
||||
* @note The switch can be controlled either by a single timer or a combination of them,
|
||||
* in this case application has to 'ORed' the values below
|
||||
* ex OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 | OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000UL) /*!< Timer controlled Mux mode disabled */
|
||||
#define OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 OPAMP_TCMR_T1CMEN /*!< Timer controlled Mux mode enabled using TIM1 OC6 */
|
||||
#define OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 OPAMP_TCMR_T8CMEN /*!< Timer controlled Mux mode enabled using TIM8 OC6 */
|
||||
#if defined(TIM20)
|
||||
#define OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6 OPAMP_TCMR_T20CMEN /*!< Timer controlled Mux mode enabled using TIM20 OC6
|
||||
Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_NonInvertingInputSecondary OPAMP Non Inverting Input Secondary
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_IO0 (0x00000000UL) /*!< Secondary non inverting input connected to I/O VINP0
|
||||
(PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_IO1 OPAMP_TCMR_VPSSEL_0 /*!< Secondary non inverting input connected to I/O VINP1
|
||||
(PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_TCMR_VPSSEL_1 /*!< Secondary non inverting input connected to I/O VINP2
|
||||
(PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_TCMR_VPSSEL /*!< Secondary non inverting input connected to I/O VINP3
|
||||
(PD14 for OPAMP2) */
|
||||
#define OPAMP_SEC_NONINVERTINGINPUT_DAC OPAMP_TCMR_VPSSEL /*!< Secondary non inverting input connected internally to DAC channel
|
||||
(DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_InvertingInputSecondary OPAMP Inverting Input Secondary
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000UL) /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref OPAMP_STANDALONE_MODE
|
||||
has been configured by call to @ref HAL_OPAMP_Init().
|
||||
Secondary inverting input connected to I/O VINM0
|
||||
(PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
#define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_TCMR_VMSSEL /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref OPAMP_STANDALONE_MODE
|
||||
has been configured by call to @ref HAL_OPAMP_Init().
|
||||
Secondary inverting input connected to I/0 VINM1
|
||||
(PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6)
|
||||
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
|
||||
#define OPAMP_SEC_INVERTINGINPUT_PGA (0x00000000UL) /*!< OPAMP secondary mode is PGA mode - Only applicable if configured mode through call to @ref HAL_OPAMP_Init()
|
||||
is @ref OPAMP_PGA_MODE or @ref OPAMP_FOLLOWER_MODE.
|
||||
OPAMP secondary inverting input is:
|
||||
- Not connected if configured mode is @ref OPAMP_FOLLOWER_MODE
|
||||
- Not connected if configured mode is @ref OPAMP_PGA_MODE and PGA connect mode is @ref OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
|
||||
- Connected to VINM0 and possibly VINM1 if any of the other modes as been configured
|
||||
(see @ref OPAMP_PgaConnect description for more details on PGA connection modes) */
|
||||
#define OPAMP_SEC_INVERTINGINPUT_FOLLOWER OPAMP_TCMR_VMSSEL /*!< OPAMP secondary mode is Follower mode - Only applicable if configured mode through call to @ref HAL_OPAMP_Init()
|
||||
is @ref OPAMP_PGA_MODE or @ref OPAMP_FOLLOWER_MODE.
|
||||
OPAMP secondary inverting input is not connected. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000UL) /*!< In PGA mode, the inverting input is not connected */
|
||||
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_4 /*!< In PGA mode, the inverting input is connected to VINM0 for filtering */
|
||||
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the inverting input is connected to VINM0
|
||||
- Input signal on VINM0, bias on VINPx: negative gain
|
||||
- Bias on VINM0, input signal on VINPx: positive gain */
|
||||
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the inverting input is connected to VINM0
|
||||
- Input signal on VINM0, bias on VINPx: negative gain
|
||||
- Bias on VINM0, input signal on VINPx: positive gain
|
||||
And VINM1 is connected too for filtering */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
|
||||
* @note Gain sign:
|
||||
* - is positive if the @ref OPAMP_PgaConnect configuration is
|
||||
* @ref OPAMP_PGA_CONNECT_INVERTINGINPUT_NO or OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
|
||||
* - may be positive or negative if the @ref OPAMP_PgaConnect configuration is
|
||||
* @ref OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS or OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS
|
||||
* see @ref OPAMP_PgaConnect for more details
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_PGA_GAIN_2_OR_MINUS_1 (0x00000000UL) /*!< PGA gain could be 2 or -1 */
|
||||
#define OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0) /*!< PGA gain could be 4 or -3 */
|
||||
#define OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 ) /*!< PGA gain could be 8 or -7 */
|
||||
#define OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0) /*!< PGA gain could be 16 or -15 */
|
||||
#define OPAMP_PGA_GAIN_32_OR_MINUS_31 (OPAMP_CSR_PGGAIN_2 ) /*!< PGA gain could be 32 or -31 */
|
||||
#define OPAMP_PGA_GAIN_64_OR_MINUS_63 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_0) /*!< PGA gain could be 64 or -63 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_PowerMode OPAMP PowerMode
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_POWERMODE_NORMALSPEED (0x00000000UL) /*!< Output in normal mode */
|
||||
#define OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN /*!< Output in highspeed mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
|
||||
#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFUL) /*!< Dummy trimming value */
|
||||
|
||||
#define OPAMP_FACTORYTRIMMING_N (0x00000000UL) /*!< Offset trimming N */
|
||||
#define OPAMP_FACTORYTRIMMING_P (0x00000001UL) /*!< Offset trimming P */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_VREF OPAMP VREF
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_VREF_3VDDA (0x00000000UL) /*!< OPAMP Vref = 3.3% VDDA */
|
||||
#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPAMP Vref = 10% VDDA */
|
||||
#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPAMP Vref = 50% VDDA */
|
||||
#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPAMP Vref = 90% VDDA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup OPAMP_Private_Constants OPAMP Private Constants
|
||||
* @brief OPAMP Private constants and defines
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup OPAMP_Input OPAMP Input
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_INPUT_INVERTING ( 24UL) /*!< Inverting input */
|
||||
#define OPAMP_INPUT_NONINVERTING ( 19UL) /*!< Non inverting input */
|
||||
|
||||
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
|
||||
((INPUT) == OPAMP_INPUT_NONINVERTING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup OPAMP_Private_Macros OPAMP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
|
||||
((INPUT) == OPAMP_PGA_MODE) || \
|
||||
((INPUT) == OPAMP_FOLLOWER_MODE))
|
||||
|
||||
#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
|
||||
((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
|
||||
((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
|
||||
((INPUT) == OPAMP_NONINVERTINGINPUT_IO3) || \
|
||||
((INPUT) == OPAMP_NONINVERTINGINPUT_DAC))
|
||||
|
||||
#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
|
||||
((INPUT) == OPAMP_INVERTINGINPUT_IO1))
|
||||
|
||||
#if defined(TIM20)
|
||||
#define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) \
|
||||
((MUXMODE) <= (OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 | \
|
||||
OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 | \
|
||||
OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6))
|
||||
#else
|
||||
#define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) \
|
||||
((MUXMODE) <= (OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 | \
|
||||
OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6))
|
||||
#endif
|
||||
|
||||
#define IS_OPAMP_SEC_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
|
||||
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
|
||||
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
|
||||
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3) || \
|
||||
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_DAC))
|
||||
|
||||
#define IS_OPAMP_SEC_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
|
||||
((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1) || \
|
||||
((INPUT) == OPAMP_SEC_INVERTINGINPUT_PGA) || \
|
||||
((INPUT) == OPAMP_SEC_INVERTINGINPUT_FOLLOWER))
|
||||
|
||||
#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO) || \
|
||||
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
|
||||
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS) || \
|
||||
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))
|
||||
|
||||
#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1) || \
|
||||
((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3) || \
|
||||
((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7) || \
|
||||
((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15) || \
|
||||
((GAIN) == OPAMP_PGA_GAIN_32_OR_MINUS_31) || \
|
||||
((GAIN) == OPAMP_PGA_GAIN_64_OR_MINUS_63))
|
||||
|
||||
#define IS_OPAMP_POWERMODE(POWERMODE) (((POWERMODE) == OPAMP_POWERMODE_NORMALSPEED) || \
|
||||
((POWERMODE) == OPAMP_POWERMODE_HIGHSPEED) )
|
||||
|
||||
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
|
||||
((TRIMMING) == OPAMP_TRIMMING_USER))
|
||||
|
||||
#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
|
||||
((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
|
||||
|
||||
#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FUL)
|
||||
|
||||
#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
|
||||
((VREF) == OPAMP_VREF_10VDDA) || \
|
||||
((VREF) == OPAMP_VREF_50VDDA) || \
|
||||
((VREF) == OPAMP_VREF_90VDDA))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset OPAMP handle state
|
||||
* @param __HANDLE__ OPAMP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include OPAMP HAL Extended module */
|
||||
#include "stm32g4xx_hal_opamp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
|
||||
HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp);
|
||||
void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
|
||||
void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
|
||||
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
|
||||
HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
|
||||
/* OPAMP callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId,
|
||||
pOPAMP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId);
|
||||
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
|
||||
|
||||
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
|
||||
HAL_StatusTypeDef HAL_OPAMP_LockTimerMux(OPAMP_HandleTypeDef *hopamp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
|
||||
OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_OPAMP_H */
|
||||
89
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp_ex.h
Normal file
89
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp_ex.h
Normal file
@@ -0,0 +1,89 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_opamp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of OPAMP HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_OPAMP_EX_H
|
||||
#define STM32G4xx_HAL_OPAMP_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6)
|
||||
|
||||
/** @addtogroup OPAMPEx OPAMPEx
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions *****************************************************/
|
||||
|
||||
#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx)
|
||||
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
|
||||
OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6);
|
||||
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
|
||||
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
|
||||
OPAMP_HandleTypeDef *hopamp3);
|
||||
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
|
||||
OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6);
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC)
|
||||
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1);
|
||||
#endif /* STM32G473xx || STM32G474xx || STM32G483xx || STM32G484xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32G4xx_HAL_OPAMP_EX_H */
|
||||
991
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h
Normal file
991
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h
Normal file
@@ -0,0 +1,991 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_PCD_H
|
||||
#define STM32G4xx_HAL_PCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_ll_usb.h"
|
||||
|
||||
#if defined (USB)
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Types PCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PCD State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_STATE_RESET = 0x00,
|
||||
HAL_PCD_STATE_READY = 0x01,
|
||||
HAL_PCD_STATE_ERROR = 0x02,
|
||||
HAL_PCD_STATE_BUSY = 0x03,
|
||||
HAL_PCD_STATE_TIMEOUT = 0x04
|
||||
} PCD_StateTypeDef;
|
||||
|
||||
/* Device LPM suspend state */
|
||||
typedef enum
|
||||
{
|
||||
LPM_L0 = 0x00, /* on */
|
||||
LPM_L1 = 0x01, /* LPM L1 sleep */
|
||||
LPM_L2 = 0x02, /* suspend */
|
||||
LPM_L3 = 0x03, /* off */
|
||||
} PCD_LPM_StateTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_LPM_L0_ACTIVE = 0x00, /* on */
|
||||
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
|
||||
} PCD_LPM_MsgTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_BCD_ERROR = 0xFF,
|
||||
PCD_BCD_CONTACT_DETECTION = 0xFE,
|
||||
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
|
||||
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
|
||||
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
|
||||
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
|
||||
|
||||
} PCD_BCD_MsgTypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
typedef USB_TypeDef PCD_TypeDef;
|
||||
typedef USB_CfgTypeDef PCD_InitTypeDef;
|
||||
typedef USB_EPTypeDef PCD_EPTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PCD Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __PCD_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
__IO uint8_t USB_Address; /*!< USB Address */
|
||||
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< PCD Error code */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||
uint32_t BESL;
|
||||
|
||||
|
||||
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
|
||||
void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
|
||||
void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
|
||||
void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
|
||||
void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
|
||||
void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
|
||||
void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
|
||||
|
||||
void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
|
||||
void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
|
||||
void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
|
||||
void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
|
||||
void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
|
||||
void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
|
||||
|
||||
void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
} PCD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PCD HAL Extended module */
|
||||
#include "stm32g4xx_hal_pcd_ex.h"
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Speed PCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SPEED_FULL USBD_FS_SPEED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_PHY_Module PCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define PCD_PHY_ULPI 1U
|
||||
#define PCD_PHY_EMBEDDED 2U
|
||||
#define PCD_PHY_UTMI 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Error_Code_definition PCD Error Code definition
|
||||
* @brief PCD Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
|
||||
((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
|
||||
&= (uint16_t)(~(__INTERRUPT__)))
|
||||
|
||||
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
|
||||
* @brief HAL USB OTG PCD Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
|
||||
HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
|
||||
HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
|
||||
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
|
||||
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
|
||||
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
|
||||
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
|
||||
|
||||
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
|
||||
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
|
||||
|
||||
} HAL_PCD_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
|
||||
* @brief HAL USB OTG PCD Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
|
||||
typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
|
||||
typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
|
||||
typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
|
||||
typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
|
||||
typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
|
||||
typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
|
||||
pPCD_CallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_DataInStageCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
|
||||
pPCD_IsoInIncpltCallbackTypeDef pCallback);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Constants PCD Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define PCD_EP0MPS_64 EP_MPS_64
|
||||
#define PCD_EP0MPS_32 EP_MPS_32
|
||||
#define PCD_EP0MPS_16 EP_MPS_16
|
||||
#define PCD_EP0MPS_08 EP_MPS_8
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_ENDP PCD ENDP
|
||||
* @{
|
||||
*/
|
||||
#define PCD_ENDP0 0U
|
||||
#define PCD_ENDP1 1U
|
||||
#define PCD_ENDP2 2U
|
||||
#define PCD_ENDP3 3U
|
||||
#define PCD_ENDP4 4U
|
||||
#define PCD_ENDP5 5U
|
||||
#define PCD_ENDP6 6U
|
||||
#define PCD_ENDP7 7U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SNG_BUF 0U
|
||||
#define PCD_DBL_BUF 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Macros PCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************** Bit definition for USB_COUNTn_RX register *************/
|
||||
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
|
||||
#define USB_CNTRX_BLSIZE (0x1U << 15)
|
||||
|
||||
/* SetENDPOINT */
|
||||
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
|
||||
(*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
|
||||
|
||||
/* GetENDPOINT */
|
||||
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
|
||||
|
||||
|
||||
/**
|
||||
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wType Endpoint Type.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
|
||||
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
|
||||
|
||||
|
||||
/**
|
||||
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval Endpoint Type
|
||||
*/
|
||||
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
|
||||
|
||||
/**
|
||||
* @brief free buffer used from the application realizing it to the line
|
||||
* toggles bit SW_BUF in the double buffered endpoint register
|
||||
* @param USBx USB device.
|
||||
* @param bEpNum, bDir
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
|
||||
do { \
|
||||
if ((bDir) == 0U) \
|
||||
{ \
|
||||
/* OUT double buffered endpoint */ \
|
||||
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
else if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN double buffered endpoint */ \
|
||||
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_TX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_RX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wStaterx new state.
|
||||
* @param wStatetx new state.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
} \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
} \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_TXRX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
|
||||
* /STAT_RX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval status
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
|
||||
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
|
||||
|
||||
/**
|
||||
* @brief sets directly the VALID tx/rx-status into the endpoint register
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
|
||||
#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
|
||||
|
||||
/**
|
||||
* @brief checks stall condition in an endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval TRUE = endpoint in stall condition.
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
|
||||
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
|
||||
|
||||
/**
|
||||
* @brief set & clear EP_KIND bit.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_KIND(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
|
||||
} while(0) /* PCD_SET_EP_KIND */
|
||||
|
||||
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_CLEAR_EP_KIND */
|
||||
|
||||
/**
|
||||
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
|
||||
#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
|
||||
|
||||
/**
|
||||
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
|
||||
#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
|
||||
|
||||
/**
|
||||
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_CLEAR_RX_EP_CTR */
|
||||
|
||||
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
|
||||
} while(0) /* PCD_CLEAR_TX_EP_CTR */
|
||||
|
||||
/**
|
||||
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_RX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wEPVal; \
|
||||
\
|
||||
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
|
||||
} while(0) /* PCD_RX_DTOG */
|
||||
|
||||
#define PCD_TX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wEPVal; \
|
||||
\
|
||||
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
|
||||
} while(0) /* PCD_TX_DTOG */
|
||||
/**
|
||||
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
|
||||
\
|
||||
if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
|
||||
{ \
|
||||
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0) /* PCD_CLEAR_RX_DTOG */
|
||||
|
||||
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
|
||||
\
|
||||
if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
|
||||
{ \
|
||||
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0) /* PCD_CLEAR_TX_DTOG */
|
||||
|
||||
/**
|
||||
* @brief Sets address in an endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param bAddr Address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
|
||||
do { \
|
||||
uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_ADDRESS */
|
||||
|
||||
/**
|
||||
* @brief Gets address in an endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
|
||||
|
||||
#define PCD_EP_TX_CNT(USBx, bEpNum) \
|
||||
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
|
||||
((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
|
||||
|
||||
#define PCD_EP_RX_CNT(USBx, bEpNum) \
|
||||
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
|
||||
((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
|
||||
|
||||
|
||||
/**
|
||||
* @brief sets address of the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wAddr address to be set (must be word aligned).
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
|
||||
do { \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_TX_ADDRESS */
|
||||
|
||||
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
|
||||
do { \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_RX_ADDRESS */
|
||||
|
||||
/**
|
||||
* @brief Gets address of the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval address of the buffer.
|
||||
*/
|
||||
#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
|
||||
#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
|
||||
|
||||
/**
|
||||
* @brief Sets counter of rx buffer with no. of blocks.
|
||||
* @param pdwReg Register pointer
|
||||
* @param wCount Counter.
|
||||
* @param wNBlocks no. of Blocks.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
|
||||
do { \
|
||||
(wNBlocks) = (wCount) >> 5; \
|
||||
if (((wCount) & 0x1fU) == 0U) \
|
||||
{ \
|
||||
(wNBlocks)--; \
|
||||
} \
|
||||
*(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
|
||||
} while(0) /* PCD_CALC_BLK32 */
|
||||
|
||||
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
|
||||
do { \
|
||||
(wNBlocks) = (wCount) >> 1; \
|
||||
if (((wCount) & 0x1U) != 0U) \
|
||||
{ \
|
||||
(wNBlocks)++; \
|
||||
} \
|
||||
*(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
|
||||
} while(0) /* PCD_CALC_BLK2 */
|
||||
|
||||
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
|
||||
do { \
|
||||
uint32_t wNBlocks; \
|
||||
\
|
||||
*(pdwReg) &= 0x3FFU; \
|
||||
\
|
||||
if ((wCount) == 0U) \
|
||||
{ \
|
||||
*(pdwReg) |= USB_CNTRX_BLSIZE; \
|
||||
} \
|
||||
else if ((wCount) <= 62U) \
|
||||
{ \
|
||||
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
|
||||
} \
|
||||
} while(0) /* PCD_SET_EP_CNT_RX_REG */
|
||||
|
||||
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
|
||||
do { \
|
||||
uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *pdwReg; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief sets counter for the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wCount Counter value.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
|
||||
do { \
|
||||
uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
|
||||
*_wRegVal = (uint16_t)(wCount); \
|
||||
} while(0)
|
||||
|
||||
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
|
||||
do { \
|
||||
uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *_wRegVal; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
|
||||
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief gets counter of the tx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
|
||||
#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
|
||||
|
||||
/**
|
||||
* @brief Sets buffer 0/1 address in a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wBuf0Addr buffer 0 address.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
|
||||
do { \
|
||||
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
|
||||
|
||||
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
|
||||
do { \
|
||||
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
|
||||
|
||||
/**
|
||||
* @brief Sets addresses in a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wBuf0Addr: buffer 0 address.
|
||||
* @param wBuf1Addr = buffer 1 address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
|
||||
do { \
|
||||
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
|
||||
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF_ADDR */
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
|
||||
#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param bDir endpoint dir EP_DBUF_OUT = OUT
|
||||
* EP_DBUF_IN = IN
|
||||
* @param wCount: Counter value
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
|
||||
do { \
|
||||
if ((bDir) == 0U) \
|
||||
/* OUT endpoint */ \
|
||||
{ \
|
||||
PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN endpoint */ \
|
||||
PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
|
||||
} \
|
||||
} \
|
||||
} while(0) /* SetEPDblBuf0Count*/
|
||||
|
||||
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
|
||||
do { \
|
||||
uint32_t _wBase = (uint32_t)(USBx); \
|
||||
__IO uint16_t *_wEPRegVal; \
|
||||
\
|
||||
if ((bDir) == 0U) \
|
||||
{ \
|
||||
/* OUT endpoint */ \
|
||||
PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN endpoint */ \
|
||||
_wBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
|
||||
*_wEPRegVal = (uint16_t)(wCount); \
|
||||
} \
|
||||
} \
|
||||
} while(0) /* SetEPDblBuf1Count */
|
||||
|
||||
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
|
||||
do { \
|
||||
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF_CNT */
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
|
||||
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_PCD_H */
|
||||
87
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h
Normal file
87
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h
Normal file
@@ -0,0 +1,87 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PCD HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_PCD_EX_H
|
||||
#define STM32G4xx_HAL_PCD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
#if defined (USB)
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCDEx
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
||||
uint16_t ep_kind, uint32_t pmaadress);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
|
||||
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* STM32G4xx_HAL_PCD_EX_H */
|
||||
411
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h
Normal file
411
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h
Normal file
@@ -0,0 +1,411 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_PWR_H
|
||||
#define STM32G4xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level. */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode. */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */
|
||||
#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */
|
||||
#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */
|
||||
#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */
|
||||
#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */
|
||||
#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */
|
||||
#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */
|
||||
#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macros PWR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check whether or not a specific PWR flag is set.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 1.
|
||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 2.
|
||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 3.
|
||||
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 4.
|
||||
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 5.
|
||||
* @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
|
||||
* entered StandBy mode.
|
||||
* @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
|
||||
* the internal wakeup line.
|
||||
* @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
|
||||
* low-power regulator is ready.
|
||||
* @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
|
||||
* regulator is ready in main mode or is in low-power mode.
|
||||
* @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
|
||||
* in the selected voltage range or is still changing to the required voltage level.
|
||||
* @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
|
||||
* below or above the selected PVD threshold.
|
||||
@if PWR_CR2_PVME1
|
||||
* @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
|
||||
* is below or above PVM1 threshold (applicable when USB feature is supported).
|
||||
@endif
|
||||
@if PWR_CR2_PVME2
|
||||
* @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
|
||||
* is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
|
||||
@endif
|
||||
* @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
|
||||
* is below or above PVM3 threshold.
|
||||
* @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
|
||||
* is below or above PVM4 threshold.
|
||||
*
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\
|
||||
(PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
|
||||
(PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
|
||||
|
||||
/** @brief Clear a specific PWR flag.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 1.
|
||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 2.
|
||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 3.
|
||||
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 4.
|
||||
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 5.
|
||||
* @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
|
||||
* @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
|
||||
* entered Standby mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
|
||||
(PWR->SCR = (__FLAG__)) :\
|
||||
(PWR->SCR = (1U << ((__FLAG__) & 31U))) )
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Check whether or not the PVD EXTI interrupt flag is set.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI interrupt flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Private_Macros PWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING) ||\
|
||||
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
|
||||
((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
|
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PWR HAL Extended module */
|
||||
#include "stm32g4xx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32G4xx_HAL_PWR_H */
|
||||
|
||||
817
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h
Normal file
817
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h
Normal file
@@ -0,0 +1,817 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_PWR_EX_H
|
||||
#define STM32G4xx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief PWR PVM configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
|
||||
This parameter can be a value of @ref PWREx_PVM_Type. */
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWREx_PVM_Mode. */
|
||||
}PWR_PVMTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polariry */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
|
||||
#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
|
||||
#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
|
||||
#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
|
||||
#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
#define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
|
||||
#endif /* PWR_CR2_PVME1 */
|
||||
#if defined(PWR_CR2_PVME2)
|
||||
#define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
|
||||
#endif /* PWR_CR2_PVME2 */
|
||||
#define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
|
||||
#define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVM_MODE_NORMAL 0x00000000U /*!< basic mode is used */
|
||||
#define PWR_PVM_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVM_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVM_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVM_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVM_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVM_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR5_R1MODE)
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */
|
||||
#endif /*PWR_CR5_R1MODE */
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BATTERY_CHARGING_RESISTOR_5 0x00000000U /*!< VBAT charging through a 5 kOhms resistor */
|
||||
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BATTERY_CHARGING_DISABLE 0x00000000U
|
||||
#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
|
||||
#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
|
||||
#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
|
||||
#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
|
||||
#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
|
||||
#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
|
||||
#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
|
||||
#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
|
||||
#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
|
||||
#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
|
||||
#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
|
||||
#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
|
||||
#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
|
||||
#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
|
||||
#define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
|
||||
#define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_GPIO GPIO port
|
||||
* @{
|
||||
*/
|
||||
#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */
|
||||
#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */
|
||||
#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */
|
||||
#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */
|
||||
#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */
|
||||
#define PWR_GPIO_F 0x00000005U /*!< GPIO port F */
|
||||
#define PWR_GPIO_G 0x00000006U /*!< GPIO port G */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
#define PWR_EXTI_LINE_PVM1 0x00000008U /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */
|
||||
#endif /* PWR_CR2_PVME1 */
|
||||
#if defined(PWR_CR2_PVME2)
|
||||
#define PWR_EXTI_LINE_PVM2 0x00000010U /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */
|
||||
#endif /* PWR_CR2_PVME2 */
|
||||
#define PWR_EXTI_LINE_PVM3 0x00000020U /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */
|
||||
#define PWR_EXTI_LINE_PVM4 0x00000040U /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
#define PWR_EVENT_LINE_PVM1 0x00000008U /*!< Event line 35 Connected to the PVM1 EXTI Line */
|
||||
#endif /* PWR_CR2_PVME1 */
|
||||
#if defined(PWR_CR2_PVME2)
|
||||
#define PWR_EVENT_LINE_PVM2 0x00000010U /*!< Event line 36 Connected to the PVM2 EXTI Line */
|
||||
#endif /* PWR_CR2_PVME2 */
|
||||
#define PWR_EVENT_LINE_PVM3 0x00000020U /*!< Event line 37 Connected to the PVM3 EXTI Line */
|
||||
#define PWR_EVENT_LINE_PVM4 0x00000040U /*!< Event line 38 Connected to the PVM4 EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Flag PWR Status Flags
|
||||
* Elements values convention: 0000 0000 0XXY YYYYb
|
||||
* - Y YYYY : Flag position in the XX register (5 bits)
|
||||
* - XX : Status register (2 bits)
|
||||
* - 01: SR1 register
|
||||
* - 10: SR2 register
|
||||
* The only exception is PWR_FLAG_WU, encompassing all
|
||||
* wake-up flags and set to PWR_SR1_WUF.
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_WUF1 0x0020U /*!< Wakeup event on wakeup pin 1 */
|
||||
#define PWR_FLAG_WUF2 0x0021U /*!< Wakeup event on wakeup pin 2 */
|
||||
#define PWR_FLAG_WUF3 0x0022U /*!< Wakeup event on wakeup pin 3 */
|
||||
#define PWR_FLAG_WUF4 0x0023U /*!< Wakeup event on wakeup pin 4 */
|
||||
#define PWR_FLAG_WUF5 0x0024U /*!< Wakeup event on wakeup pin 5 */
|
||||
#define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
|
||||
#define PWR_FLAG_SB 0x0028U /*!< Standby flag */
|
||||
#define PWR_FLAG_WUFI 0x002FU /*!< Wakeup on internal wakeup line */
|
||||
|
||||
#define PWR_FLAG_REGLPS 0x0048U /*!< Low-power regulator start flag */
|
||||
#define PWR_FLAG_REGLPF 0x0049U /*!< Low-power regulator flag */
|
||||
#define PWR_FLAG_VOSF 0x004AU /*!< Voltage scaling flag */
|
||||
#define PWR_FLAG_PVDO 0x004BU /*!< Power Voltage Detector output flag */
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
#define PWR_FLAG_PVMO1 0x004CU /*!< Power Voltage Monitoring 1 output flag */
|
||||
#endif /* PWR_CR2_PVME1 */
|
||||
#if defined(PWR_CR2_PVME2)
|
||||
#define PWR_FLAG_PVMO2 0x004DU /*!< Power Voltage Monitoring 2 output flag */
|
||||
#endif /* PWR_CR2_PVME2 */
|
||||
#define PWR_FLAG_PVMO3 0x004EU /*!< Power Voltage Monitoring 3 output flag */
|
||||
#define PWR_FLAG_PVMO4 0x004FU /*!< Power Voltage Monitoring 4 output flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVM1 Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVM1 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
|
||||
|
||||
#endif /* PWR_CR2_PVME1 */
|
||||
|
||||
|
||||
#if defined(PWR_CR2_PVME2)
|
||||
/**
|
||||
* @brief Enable the PVM2 Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM2 Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM2 Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM2 Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM2 Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM2 Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM2 Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM2 Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVM2 Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVM2 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
|
||||
|
||||
#endif /* PWR_CR2_PVME2 */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVM3 Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVM3 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM4 Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM4 Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM4 Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM4 Event Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM4 Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM4 Extended Interrupt Rising Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM4 Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM4 Extended Interrupt Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
|
||||
|
||||
/**
|
||||
* @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
|
||||
* @retval EXTI PVM4 Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVM4 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure the main internal regulator output voltage.
|
||||
* @param __REGULATOR__: specifies the regulator output voltage to achieve
|
||||
* a tradeoff between performance and power consumption.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST Regulator voltage output range 1 mode,
|
||||
* typical output voltage at 1.28 V,
|
||||
* system frequency up to 170 MHz.
|
||||
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
|
||||
* typical output voltage at 1.2 V,
|
||||
* system frequency up to 150 MHz.
|
||||
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
|
||||
* typical output voltage at 1.0 V,
|
||||
* system frequency up to 26 MHz.
|
||||
* @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
|
||||
* whether or not VOSF flag is cleared when moving from range 2 to range 1. User
|
||||
* may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5) || \
|
||||
((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5_LOW))
|
||||
|
||||
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
|
||||
((TYPE) == PWR_PVM_2) ||\
|
||||
((TYPE) == PWR_PVM_3) ||\
|
||||
((TYPE) == PWR_PVM_4))
|
||||
|
||||
#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
|
||||
((MODE) == PWR_PVM_MODE_IT_RISING) ||\
|
||||
((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
|
||||
|
||||
#if defined(PWR_CR5_R1MODE)
|
||||
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
|
||||
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
|
||||
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
|
||||
#else
|
||||
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
|
||||
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
|
||||
#endif
|
||||
|
||||
|
||||
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
|
||||
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
|
||||
|
||||
#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
|
||||
((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
|
||||
|
||||
#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U)
|
||||
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
|
||||
((GPIO) == PWR_GPIO_B) ||\
|
||||
((GPIO) == PWR_GPIO_C) ||\
|
||||
((GPIO) == PWR_GPIO_D) ||\
|
||||
((GPIO) == PWR_GPIO_E) ||\
|
||||
((GPIO) == PWR_GPIO_F) ||\
|
||||
((GPIO) == PWR_GPIO_G))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
||||
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
|
||||
void HAL_PWREx_DisableBatteryCharging(void);
|
||||
void HAL_PWREx_EnableInternalWakeUpLine(void);
|
||||
void HAL_PWREx_DisableInternalWakeUpLine(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
|
||||
void HAL_PWREx_EnablePullUpPullDownConfig(void);
|
||||
void HAL_PWREx_DisablePullUpPullDownConfig(void);
|
||||
void HAL_PWREx_EnableSRAM2ContentRetention(void);
|
||||
void HAL_PWREx_DisableSRAM2ContentRetention(void);
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
void HAL_PWREx_EnablePVM1(void);
|
||||
void HAL_PWREx_DisablePVM1(void);
|
||||
#endif /* PWR_CR2_PVME1 */
|
||||
#if defined(PWR_CR2_PVME2)
|
||||
void HAL_PWREx_EnablePVM2(void);
|
||||
void HAL_PWREx_DisablePVM2(void);
|
||||
#endif /* PWR_CR2_PVME2 */
|
||||
void HAL_PWREx_EnablePVM3(void);
|
||||
void HAL_PWREx_DisablePVM3(void);
|
||||
void HAL_PWREx_EnablePVM4(void);
|
||||
void HAL_PWREx_DisablePVM4(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWREx_EnableLowPowerRunMode(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
|
||||
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
|
||||
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
|
||||
void HAL_PWREx_EnterSHUTDOWNMode(void);
|
||||
|
||||
void HAL_PWREx_PVD_PVM_IRQHandler(void);
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
void HAL_PWREx_PVM1Callback(void);
|
||||
#endif /* PWR_CR2_PVME1 */
|
||||
#if defined(PWR_CR2_PVME2)
|
||||
void HAL_PWREx_PVM2Callback(void);
|
||||
#endif /* PWR_CR2_PVME2 */
|
||||
void HAL_PWREx_PVM3Callback(void);
|
||||
void HAL_PWREx_PVM4Callback(void);
|
||||
|
||||
#if defined(PWR_CR3_UCPD_STDBY)
|
||||
void HAL_PWREx_EnableUCPDStandbyMode(void);
|
||||
void HAL_PWREx_DisableUCPDStandbyMode(void);
|
||||
#endif /* PWR_CR3_UCPD_STDBY */
|
||||
#if defined(PWR_CR3_UCPD_DBDIS)
|
||||
void HAL_PWREx_EnableUCPDDeadBattery(void);
|
||||
void HAL_PWREx_DisableUCPDDeadBattery(void);
|
||||
#endif /* PWR_CR3_UCPD_DBDIS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32G4xx_HAL_PWR_EX_H */
|
||||
|
||||
750
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_qspi.h
Normal file
750
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_qspi.h
Normal file
@@ -0,0 +1,750 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_qspi.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of QSPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_QSPI_H
|
||||
#define STM32G4xx_HAL_QSPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
#if defined(QUADSPI)
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Types QSPI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief QSPI Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
|
||||
This parameter can be a value between 1 and 16 */
|
||||
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
|
||||
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
|
||||
This parameter can be a value of @ref QSPI_SampleShifting */
|
||||
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
|
||||
required to address the flash memory. The flash capacity can be up to 4GB
|
||||
(addressed using 32 bits) in indirect mode, but the addressable space in
|
||||
memory-mapped mode is limited to 256MB
|
||||
This parameter can be a number between 0 and 31 */
|
||||
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
|
||||
of clock cycles which the chip select must remain high between commands.
|
||||
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
|
||||
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
|
||||
This parameter can be a value of @ref QSPI_ClockMode */
|
||||
uint32_t FlashID; /* Specifies the Flash which will be used,
|
||||
This parameter can be a value of @ref QSPI_Flash_Select */
|
||||
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
|
||||
This parameter can be a value of @ref QSPI_DualFlash_Mode */
|
||||
}QSPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL QSPI State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
|
||||
HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
|
||||
HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
|
||||
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
|
||||
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
|
||||
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
|
||||
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
|
||||
HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
|
||||
HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
|
||||
}HAL_QSPI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __QSPI_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
|
||||
QSPI_InitTypeDef Init; /* QSPI communication parameters */
|
||||
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
|
||||
__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
|
||||
__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
|
||||
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
|
||||
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
|
||||
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
|
||||
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
|
||||
__IO HAL_LockTypeDef Lock; /* Locking object */
|
||||
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
|
||||
__IO uint32_t ErrorCode; /* QSPI Error code */
|
||||
uint32_t Timeout; /* Timeout for the QSPI memory access */
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
#endif
|
||||
}QSPI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Command structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Instruction; /* Specifies the Instruction to be sent
|
||||
This parameter can be a value (8-bit) between 0x00 and 0xFF */
|
||||
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
|
||||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
|
||||
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
|
||||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
|
||||
uint32_t AddressSize; /* Specifies the Address Size
|
||||
This parameter can be a value of @ref QSPI_AddressSize */
|
||||
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
|
||||
This parameter can be a value of @ref QSPI_AlternateBytesSize */
|
||||
uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
|
||||
This parameter can be a number between 0 and 31 */
|
||||
uint32_t InstructionMode; /* Specifies the Instruction Mode
|
||||
This parameter can be a value of @ref QSPI_InstructionMode */
|
||||
uint32_t AddressMode; /* Specifies the Address Mode
|
||||
This parameter can be a value of @ref QSPI_AddressMode */
|
||||
uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
|
||||
This parameter can be a value of @ref QSPI_AlternateBytesMode */
|
||||
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
|
||||
This parameter can be a value of @ref QSPI_DataMode */
|
||||
uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
|
||||
until end of memory)*/
|
||||
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
|
||||
This parameter can be a value of @ref QSPI_DdrMode */
|
||||
uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
|
||||
output by one quarter of QUADSPI output clock in DDR mode.
|
||||
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
|
||||
uint32_t SIOOMode; /* Specifies the send instruction only once mode
|
||||
This parameter can be a value of @ref QSPI_SIOOMode */
|
||||
}QSPI_CommandTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Auto Polling mode configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF */
|
||||
uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF */
|
||||
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
|
||||
This parameter can be any value between 1 and 4 */
|
||||
uint32_t MatchMode; /* Specifies the method used for determining a match.
|
||||
This parameter can be a value of @ref QSPI_MatchMode */
|
||||
uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
|
||||
This parameter can be a value of @ref QSPI_AutomaticStop */
|
||||
}QSPI_AutoPollingTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Memory Mapped mode configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
|
||||
This parameter can be a value of @ref QSPI_TimeOutActivation */
|
||||
}QSPI_MemoryMappedTypeDef;
|
||||
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL QSPI Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
|
||||
HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
|
||||
HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
|
||||
HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
|
||||
HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
|
||||
HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
|
||||
HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */
|
||||
HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */
|
||||
HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
|
||||
HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
|
||||
|
||||
HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
|
||||
HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
|
||||
}HAL_QSPI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL QSPI Callback pointer definition
|
||||
*/
|
||||
typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ErrorCode QSPI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
|
||||
#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
|
||||
#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
|
||||
#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
|
||||
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ClockMode QSPI Clock Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
|
||||
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Flash_Select QSPI Flash Select
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/
|
||||
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
|
||||
#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AddressSize QSPI Address Size
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
|
||||
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
|
||||
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
|
||||
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
|
||||
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
|
||||
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
|
||||
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AddressMode QSPI Address Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
|
||||
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
|
||||
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
|
||||
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
|
||||
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
|
||||
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DataMode QSPI Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
|
||||
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
|
||||
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
|
||||
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DdrMode QSPI DDR Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
|
||||
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
|
||||
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one quarter of QUADSPI output clock in DDR mode*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
|
||||
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_MatchMode QSPI Match Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
|
||||
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
|
||||
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
|
||||
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Flags QSPI Flags
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
|
||||
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
|
||||
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
|
||||
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
|
||||
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
|
||||
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Interrupts QSPI Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
|
||||
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
|
||||
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
|
||||
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
|
||||
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
|
||||
* @brief QSPI Timeout definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset QSPI handle state.
|
||||
* @param __HANDLE__ QSPI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable the QSPI peripheral.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Disable the QSPI peripheral.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Enable the specified QSPI interrupt.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
||||
|
||||
|
||||
/** @brief Disable the specified QSPI interrupt.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ specifies the QSPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the selected QSPI flag is set or not.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __FLAG__ specifies the QSPI flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
|
||||
* @arg QSPI_FLAG_TO: QSPI Timeout flag
|
||||
* @arg QSPI_FLAG_SM: QSPI Status match flag
|
||||
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
|
||||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
|
||||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clears the specified QSPI's flag status.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __FLAG__ specifies the QSPI clear register flag that needs to be set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_TO: QSPI Timeout flag
|
||||
* @arg QSPI_FLAG_SM: QSPI Status match flag
|
||||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
|
||||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup QSPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* QSPI IRQ handler method */
|
||||
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI indirect mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
|
||||
/* QSPI status flag polling mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
|
||||
|
||||
/* QSPI memory-mapped mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
|
||||
|
||||
/* Callback functions in non-blocking modes ***********************************/
|
||||
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI indirect mode */
|
||||
void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI status flag polling mode */
|
||||
void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI memory-mapped mode */
|
||||
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
/* QSPI callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
|
||||
uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Private_Macros QSPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
|
||||
|
||||
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U))
|
||||
|
||||
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
|
||||
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
|
||||
|
||||
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
|
||||
|
||||
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
|
||||
|
||||
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
|
||||
((CLKMODE) == QSPI_CLOCK_MODE_3))
|
||||
|
||||
#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
|
||||
((FLASH_ID) == QSPI_FLASH_ID_2))
|
||||
|
||||
#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
|
||||
((MODE) == QSPI_DUALFLASH_DISABLE))
|
||||
|
||||
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
|
||||
|
||||
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
|
||||
|
||||
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
|
||||
|
||||
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
|
||||
|
||||
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
|
||||
((MODE) == QSPI_INSTRUCTION_1_LINE) || \
|
||||
((MODE) == QSPI_INSTRUCTION_2_LINES) || \
|
||||
((MODE) == QSPI_INSTRUCTION_4_LINES))
|
||||
|
||||
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
|
||||
((MODE) == QSPI_ADDRESS_1_LINE) || \
|
||||
((MODE) == QSPI_ADDRESS_2_LINES) || \
|
||||
((MODE) == QSPI_ADDRESS_4_LINES))
|
||||
|
||||
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
|
||||
|
||||
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
|
||||
((MODE) == QSPI_DATA_1_LINE) || \
|
||||
((MODE) == QSPI_DATA_2_LINES) || \
|
||||
((MODE) == QSPI_DATA_4_LINES))
|
||||
|
||||
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
|
||||
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
|
||||
|
||||
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
|
||||
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
|
||||
|
||||
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
|
||||
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
|
||||
|
||||
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
|
||||
|
||||
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
|
||||
|
||||
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
|
||||
((MODE) == QSPI_MATCH_MODE_OR))
|
||||
|
||||
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
|
||||
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
|
||||
|
||||
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
|
||||
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
|
||||
|
||||
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(QUADSPI) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_QSPI_H */
|
||||
3406
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h
Normal file
3406
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h
Normal file
@@ -0,0 +1,3406 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RCC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_RCC_H
|
||||
#define STM32G4xx_HAL_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RCC_Exported_Types RCC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RCC PLL configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLState; /*!< The new state of the PLL.
|
||||
This parameter can be a value of @ref RCC_PLL_Config */
|
||||
|
||||
uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
|
||||
This parameter must be a value of @ref RCC_PLL_Clock_Source */
|
||||
|
||||
uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
|
||||
This parameter must be a value of @ref RCC_PLLM_Clock_Divider */
|
||||
|
||||
uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
|
||||
This parameter must be a number between Min_Data = 8 and Max_Data = 127 */
|
||||
|
||||
uint32_t PLLP; /*!< PLLP: Division factor for ADC clock.
|
||||
This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
|
||||
|
||||
uint32_t PLLQ; /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks.
|
||||
This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
|
||||
|
||||
uint32_t PLLR; /*!< PLLR: Division for the main system clock.
|
||||
User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ.
|
||||
This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
|
||||
|
||||
}RCC_PLLInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OscillatorType; /*!< The oscillators to be configured.
|
||||
This parameter can be a value of @ref RCC_Oscillator_Type */
|
||||
|
||||
uint32_t HSEState; /*!< The new state of the HSE.
|
||||
This parameter can be a value of @ref RCC_HSE_Config */
|
||||
|
||||
uint32_t LSEState; /*!< The new state of the LSE.
|
||||
This parameter can be a value of @ref RCC_LSE_Config */
|
||||
|
||||
uint32_t HSIState; /*!< The new state of the HSI.
|
||||
This parameter can be a value of @ref RCC_HSI_Config */
|
||||
|
||||
uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
|
||||
uint32_t LSIState; /*!< The new state of the LSI.
|
||||
This parameter can be a value of @ref RCC_LSI_Config */
|
||||
|
||||
uint32_t HSI48State; /*!< The new state of the HSI48.
|
||||
This parameter can be a value of @ref RCC_HSI48_Config */
|
||||
|
||||
RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
|
||||
|
||||
}RCC_OscInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RCC System, AHB and APB busses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockType; /*!< The clock to be configured.
|
||||
This parameter can be a value of @ref RCC_System_Clock_Type */
|
||||
|
||||
uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_System_Clock_Source */
|
||||
|
||||
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_AHB_Clock_Source */
|
||||
|
||||
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
|
||||
|
||||
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
|
||||
|
||||
}RCC_ClkInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RCC_Exported_Constants RCC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Timeout_Value Timeout Values
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
|
||||
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Oscillator_Type Oscillator Type
|
||||
* @{
|
||||
*/
|
||||
#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */
|
||||
#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
|
||||
#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
|
||||
#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
|
||||
#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
|
||||
#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_Config HSE Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
|
||||
#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
|
||||
#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Config LSE Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
|
||||
#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
|
||||
#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSI_Config HSI Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
|
||||
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
|
||||
#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSI_Config LSI Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
|
||||
#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSI48_Config HSI48 Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
|
||||
#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Config PLL Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */
|
||||
#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
|
||||
#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */
|
||||
#define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */
|
||||
#define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */
|
||||
#define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */
|
||||
#define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */
|
||||
#define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */
|
||||
#define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */
|
||||
#define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */
|
||||
#define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */
|
||||
#define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */
|
||||
#define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */
|
||||
#define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */
|
||||
#define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */
|
||||
#define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */
|
||||
#define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */
|
||||
#define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */
|
||||
#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */
|
||||
#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */
|
||||
#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */
|
||||
#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */
|
||||
#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
|
||||
#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */
|
||||
#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */
|
||||
#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */
|
||||
#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */
|
||||
#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */
|
||||
#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */
|
||||
#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */
|
||||
#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */
|
||||
#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */
|
||||
#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
|
||||
#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */
|
||||
#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */
|
||||
#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */
|
||||
#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */
|
||||
#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */
|
||||
#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */
|
||||
#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */
|
||||
#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */
|
||||
#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */
|
||||
#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */
|
||||
#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */
|
||||
#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */
|
||||
#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */
|
||||
#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */
|
||||
#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */
|
||||
#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */
|
||||
#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */
|
||||
#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */
|
||||
#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */
|
||||
#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */
|
||||
#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
|
||||
#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */
|
||||
#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
|
||||
#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Type System Clock Type
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
|
||||
#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
|
||||
#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
|
||||
#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source System Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
|
||||
#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
|
||||
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
|
||||
#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
|
||||
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
|
||||
#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
|
||||
#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
|
||||
#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
|
||||
#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
|
||||
#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
|
||||
#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
|
||||
#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
|
||||
#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
|
||||
#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
|
||||
#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
|
||||
#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
|
||||
#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
|
||||
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
|
||||
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
|
||||
#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO_Index MCO Index
|
||||
* @{
|
||||
*/
|
||||
/* 32 28 20 16 0
|
||||
--------------------------------
|
||||
| MCO | GPIO | GPIO | GPIO |
|
||||
| Index | AF | Port | Pin |
|
||||
-------------------------------*/
|
||||
|
||||
#define RCC_MCO_GPIOPORT_POS 16U
|
||||
#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS)
|
||||
#define RCC_MCO_GPIOAF_POS 20U
|
||||
#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS)
|
||||
#define RCC_MCO_INDEX_POS 28U
|
||||
#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS)
|
||||
#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */
|
||||
#define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
|
||||
#define RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)
|
||||
|
||||
/* Legacy Defines*/
|
||||
#define RCC_MCO1 RCC_MCO_PA8
|
||||
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
|
||||
#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
|
||||
#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
|
||||
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
|
||||
#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
|
||||
#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
|
||||
#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
|
||||
#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
|
||||
#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
|
||||
#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
|
||||
#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
|
||||
#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
|
||||
#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
|
||||
#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
|
||||
#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
|
||||
#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
|
||||
#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
|
||||
#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
|
||||
#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag Flags
|
||||
* Elements values convention: XXXYYYYYb
|
||||
* - YYYYY : Flag position in the register
|
||||
* - XXX : Register index
|
||||
* - 001: CR register
|
||||
* - 010: BDCR register
|
||||
* - 011: CSR register
|
||||
* - 100: CRRCR register
|
||||
* @{
|
||||
*/
|
||||
/* Flags in the CR register */
|
||||
#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
|
||||
#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
|
||||
#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
|
||||
|
||||
/* Flags in the BDCR register */
|
||||
#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
|
||||
#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
|
||||
|
||||
/* Flags in the CSR register */
|
||||
#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
|
||||
#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
|
||||
#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
|
||||
#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */
|
||||
#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
|
||||
#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
|
||||
#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
|
||||
#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
|
||||
|
||||
/* Flags in the CRRCR register */
|
||||
#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSEDrive_Config LSE Drive Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
|
||||
#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
|
||||
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
|
||||
#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Macros RCC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
|
||||
* @brief Enable or disable the AHB1 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_FMAC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
|
||||
|
||||
#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
|
||||
|
||||
#define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
|
||||
|
||||
#define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
|
||||
|
||||
#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
|
||||
|
||||
#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
|
||||
* @brief Enable or disable the AHB2 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
|
||||
#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
|
||||
|
||||
#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
|
||||
|
||||
#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
|
||||
|
||||
#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
|
||||
|
||||
#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
|
||||
|
||||
#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
|
||||
|
||||
#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
|
||||
|
||||
#define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
|
||||
* @brief Enable or disable the AHB3 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
|
||||
* @brief Enable or disable the APB1 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_CRS_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_USB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
|
||||
|
||||
#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
|
||||
|
||||
#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
|
||||
|
||||
#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
|
||||
|
||||
#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
|
||||
|
||||
#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
|
||||
|
||||
#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN)
|
||||
|
||||
#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
|
||||
|
||||
#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
|
||||
|
||||
#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
|
||||
|
||||
#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
|
||||
|
||||
#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
|
||||
|
||||
#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
|
||||
|
||||
#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
|
||||
|
||||
#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
|
||||
* @brief Enable or disable the APB2 peripheral clock.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
|
||||
|
||||
#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
|
||||
|
||||
#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
|
||||
|
||||
#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
|
||||
|
||||
#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
|
||||
|
||||
#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
|
||||
|
||||
#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
|
||||
* @brief Check whether the AHB1 peripheral clock is enabled or not.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
|
||||
* @brief Check whether the AHB2 peripheral clock is enabled or not.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
|
||||
|
||||
|
||||
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
|
||||
* @brief Check whether the AHB3 peripheral clock is enabled or not.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
|
||||
* @brief Check whether the APB1 peripheral clock is enabled or not.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
|
||||
|
||||
#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
|
||||
|
||||
#if defined(USB)
|
||||
#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)
|
||||
#endif /* USB */
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
|
||||
|
||||
#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
|
||||
* @brief Check whether the APB2 peripheral clock is enabled or not.
|
||||
* @note After reset, the peripheral clock (used for registers read/write access)
|
||||
* is disabled and the application software has to enable this clock before
|
||||
* using it.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
|
||||
#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
|
||||
* @brief Force or release AHB1 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
|
||||
|
||||
#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
|
||||
|
||||
#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
|
||||
|
||||
#define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
|
||||
|
||||
#define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
|
||||
|
||||
#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
|
||||
|
||||
#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
|
||||
|
||||
|
||||
#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
|
||||
|
||||
#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
|
||||
|
||||
#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
|
||||
|
||||
#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
|
||||
|
||||
#define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
|
||||
|
||||
#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
|
||||
|
||||
#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
|
||||
* @brief Force or release AHB2 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
|
||||
|
||||
#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
|
||||
|
||||
#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
|
||||
|
||||
#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
|
||||
|
||||
#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
|
||||
|
||||
#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
|
||||
|
||||
#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
|
||||
|
||||
#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
|
||||
|
||||
#define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
|
||||
|
||||
|
||||
#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
|
||||
|
||||
#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
|
||||
|
||||
#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
|
||||
|
||||
#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
|
||||
|
||||
#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
|
||||
|
||||
#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
|
||||
|
||||
#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
|
||||
|
||||
#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
|
||||
|
||||
#define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
|
||||
* @brief Force or release AHB3 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
|
||||
* @brief Force or release APB1 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
|
||||
|
||||
#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
|
||||
|
||||
#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
|
||||
|
||||
#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
|
||||
|
||||
#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
|
||||
|
||||
#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
|
||||
|
||||
#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
|
||||
|
||||
#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
|
||||
|
||||
#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
|
||||
|
||||
#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
|
||||
|
||||
#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
|
||||
|
||||
#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
|
||||
|
||||
#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
|
||||
|
||||
#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
|
||||
|
||||
#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
|
||||
|
||||
#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
|
||||
|
||||
#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
|
||||
|
||||
#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
|
||||
|
||||
#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
|
||||
|
||||
#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
|
||||
|
||||
#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
|
||||
|
||||
#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
|
||||
|
||||
#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
|
||||
|
||||
#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
|
||||
|
||||
#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
|
||||
|
||||
#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
|
||||
|
||||
#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
|
||||
|
||||
#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
|
||||
* @brief Force or release APB2 peripheral reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
|
||||
|
||||
#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
|
||||
|
||||
#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
|
||||
|
||||
#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
|
||||
|
||||
#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
|
||||
|
||||
#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
|
||||
|
||||
#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
|
||||
|
||||
#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
|
||||
#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
|
||||
|
||||
#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
|
||||
|
||||
#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
|
||||
|
||||
#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
|
||||
|
||||
#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
|
||||
|
||||
#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
|
||||
|
||||
#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
|
||||
|
||||
#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
|
||||
* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
|
||||
|
||||
#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
|
||||
|
||||
#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
|
||||
|
||||
#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
|
||||
|
||||
#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
|
||||
|
||||
#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
|
||||
|
||||
#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
|
||||
|
||||
|
||||
#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
|
||||
|
||||
#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
|
||||
|
||||
#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
|
||||
|
||||
#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
|
||||
|
||||
#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
|
||||
|
||||
#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
|
||||
|
||||
#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
|
||||
* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
|
||||
|
||||
#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
|
||||
|
||||
#define __HAL_RCC_CCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
|
||||
|
||||
#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
|
||||
|
||||
|
||||
#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
|
||||
|
||||
#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
|
||||
|
||||
#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
|
||||
|
||||
#define __HAL_RCC_CCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
|
||||
|
||||
#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
|
||||
* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
|
||||
* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
|
||||
|
||||
#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
|
||||
|
||||
#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
|
||||
|
||||
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
|
||||
|
||||
#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
|
||||
|
||||
#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
|
||||
|
||||
#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
|
||||
|
||||
#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
|
||||
|
||||
#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
|
||||
|
||||
#if defined(USB)
|
||||
#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
|
||||
#endif /* USB */
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
|
||||
|
||||
#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
|
||||
|
||||
#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
|
||||
|
||||
|
||||
#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
|
||||
|
||||
#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
|
||||
|
||||
#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
|
||||
|
||||
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
|
||||
|
||||
#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
|
||||
|
||||
#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
|
||||
|
||||
#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
|
||||
|
||||
#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
|
||||
|
||||
#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
|
||||
|
||||
#if defined(USB)
|
||||
#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
|
||||
#endif /* USB */
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
|
||||
|
||||
#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
|
||||
|
||||
#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
|
||||
* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
|
||||
|
||||
#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
|
||||
|
||||
#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
|
||||
|
||||
#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
|
||||
#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
|
||||
|
||||
#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
|
||||
|
||||
#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
|
||||
|
||||
#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
|
||||
|
||||
#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
|
||||
* @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
|
||||
|
||||
|
||||
#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
|
||||
* @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
|
||||
|
||||
|
||||
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U)
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)
|
||||
|
||||
#if defined(DAC2)
|
||||
#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U)
|
||||
#endif /* DAC2 */
|
||||
|
||||
#define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)
|
||||
|
||||
#if defined(DAC4)
|
||||
#define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U)
|
||||
#endif /* DAC4 */
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
|
||||
#endif /* AES */
|
||||
|
||||
#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
|
||||
* @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
#if defined(FMC_BANK1)
|
||||
#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
|
||||
#endif /* FMC_BANK1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
|
||||
* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)
|
||||
|
||||
|
||||
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
|
||||
|
||||
#if defined(TIM5)
|
||||
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
|
||||
#endif /* TIM5 */
|
||||
|
||||
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
|
||||
|
||||
#if defined(UART4)
|
||||
#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
|
||||
#endif /* UART5 */
|
||||
|
||||
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
|
||||
|
||||
#if defined(I2C4)
|
||||
#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
|
||||
* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
|
||||
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
|
||||
* power consumption.
|
||||
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
|
||||
* @note By default, all peripheral clocks are enabled during SLEEP mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
|
||||
|
||||
#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
|
||||
#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
|
||||
|
||||
#if defined(SPI4)
|
||||
#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U)
|
||||
#endif /* SPI4 */
|
||||
|
||||
#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
|
||||
|
||||
#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
|
||||
|
||||
#if defined(TIM20)
|
||||
#define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U)
|
||||
#endif /* TIM20 */
|
||||
|
||||
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
|
||||
|
||||
#if defined(HRTIM1)
|
||||
#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U)
|
||||
#endif /* HRTIM1 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macros to force or release the Backup domain reset.
|
||||
* @note This function resets the RTC peripheral (including the backup registers)
|
||||
* and the RTC clock source selection in RCC_CSR register.
|
||||
* @note The BKPSRAM is not affected by this reset.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
|
||||
|
||||
#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macros to enable or disable the RTC clock.
|
||||
* @note As the RTC is in the Backup domain and write access is denied to
|
||||
* this domain after reset, you have to enable write access using
|
||||
* HAL_PWR_EnableBkUpAccess() function before to configure the RTC
|
||||
* (to be done once after reset).
|
||||
* @note These macros must be used after the RTC clock source was selected.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
|
||||
|
||||
#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
|
||||
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
|
||||
* It is used (enabled by hardware) as system clock source after startup
|
||||
* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
|
||||
* of the HSE used directly or indirectly as system clock (if the Clock
|
||||
* Security System CSS is enabled).
|
||||
* @note HSI can not be stopped if it is used as system clock source. In this case,
|
||||
* you have to select another source of the system clock then stop the HSI.
|
||||
* @note After enabling the HSI, the application software should wait on HSIRDY
|
||||
* flag to be set indicating that HSI clock is stable and can be used as
|
||||
* system clock source.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
|
||||
* clock cycles.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
|
||||
|
||||
#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
|
||||
|
||||
/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
|
||||
* @note The calibration is used to compensate for the variations in voltage
|
||||
* and temperature that influence the frequency of the internal HSI RC.
|
||||
* @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
|
||||
* (default is RCC_HSICALIBRATION_DEFAULT).
|
||||
* This parameter must be a number between 0 and 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
|
||||
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
|
||||
* in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
|
||||
* @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
|
||||
* speed because of the HSI startup time.
|
||||
* @note The enable of this function has not effect on the HSION bit.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
|
||||
|
||||
#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
|
||||
|
||||
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
|
||||
* @note After enabling the LSI, the application software should wait on
|
||||
* LSIRDY flag to be set indicating that LSI clock is stable and can
|
||||
* be used to clock the IWDG and/or the RTC.
|
||||
* @note LSI can not be disabled if the IWDG is running.
|
||||
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
|
||||
* clock cycles.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
|
||||
|
||||
#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the External High Speed oscillator (HSE).
|
||||
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
|
||||
* supported by this macro. User should request a transition to HSE Off
|
||||
* first and then HSE On or HSE Bypass.
|
||||
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
|
||||
* software should wait on HSERDY flag to be set indicating that HSE clock
|
||||
* is stable and can be used to clock the PLL and/or system clock.
|
||||
* @note HSE state can not be changed if it is used directly or through the
|
||||
* PLL as system clock. In this case, you have to select another source
|
||||
* of the system clock then change the HSE state (ex. disable it).
|
||||
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
|
||||
* @note This function reset the CSSON bit, so if the clock security system(CSS)
|
||||
* was previously enabled you have to enable it again after calling this
|
||||
* function.
|
||||
* @param __STATE__ specifies the new state of the HSE.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
|
||||
* 6 HSE oscillator clock cycles.
|
||||
* @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
|
||||
* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
|
||||
do { \
|
||||
if((__STATE__) == RCC_HSE_ON) \
|
||||
{ \
|
||||
SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
||||
} \
|
||||
else if((__STATE__) == RCC_HSE_BYPASS) \
|
||||
{ \
|
||||
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
||||
SET_BIT(RCC->CR, RCC_CR_HSEON); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
|
||||
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the External Low Speed oscillator (LSE).
|
||||
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
|
||||
* supported by this macro. User should request a transition to LSE Off
|
||||
* first and then LSE On or LSE Bypass.
|
||||
* @note As the LSE is in the Backup domain and write access is denied to
|
||||
* this domain after reset, you have to enable write access using
|
||||
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
||||
* (to be done once after reset).
|
||||
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
|
||||
* software should wait on LSERDY flag to be set indicating that LSE clock
|
||||
* is stable and can be used to clock the RTC.
|
||||
* @param __STATE__ specifies the new state of the LSE.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
|
||||
* 6 LSE oscillator clock cycles.
|
||||
* @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
|
||||
* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
|
||||
do { \
|
||||
if((__STATE__) == RCC_LSE_ON) \
|
||||
{ \
|
||||
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
||||
} \
|
||||
else if((__STATE__) == RCC_LSE_BYPASS) \
|
||||
{ \
|
||||
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
||||
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
||||
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
|
||||
* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
|
||||
* @note After enabling the HSI48, the application software should wait on HSI48RDY
|
||||
* flag to be set indicating that HSI48 clock is stable.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
|
||||
|
||||
#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
|
||||
|
||||
/** @brief Macros to configure the RTC clock (RTCCLK).
|
||||
* @note As the RTC clock configuration bits are in the Backup domain and write
|
||||
* access is denied to this domain after reset, you have to enable write
|
||||
* access using the Power Backup Access macro before to configure
|
||||
* the RTC clock source (to be done once after reset).
|
||||
* @note Once the RTC clock is configured it cannot be changed unless the
|
||||
* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
|
||||
* a Power On Reset (POR).
|
||||
*
|
||||
* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
|
||||
*
|
||||
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
|
||||
* work in STOP and STANDBY modes, and can be used as wakeup source.
|
||||
* However, when the HSE clock is used as RTC clock source, the RTC
|
||||
* cannot be used in STOP and STANDBY modes.
|
||||
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
|
||||
* RTC clock source).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
|
||||
MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
|
||||
|
||||
|
||||
/** @brief Macro to get the RTC clock source.
|
||||
* @retval The returned value can be one of the following:
|
||||
* @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
|
||||
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
|
||||
*/
|
||||
#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
|
||||
|
||||
/** @brief Macros to enable or disable the main PLL.
|
||||
* @note After enabling the main PLL, the application software should wait on
|
||||
* PLLRDY flag to be set indicating that PLL clock is stable and can
|
||||
* be used as system clock source.
|
||||
* @note The main PLL can not be disabled if it is used as system clock source
|
||||
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
|
||||
|
||||
#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
|
||||
|
||||
/** @brief Macro to configure the PLL clock source.
|
||||
* @note This function must be used only when the main PLL is disabled.
|
||||
* @param __PLLSOURCE__ specifies the PLL entry clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
|
||||
* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
|
||||
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
|
||||
* @retval None
|
||||
*
|
||||
*/
|
||||
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
|
||||
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
|
||||
|
||||
/** @brief Macro to configure the PLL source division factor M.
|
||||
* @note This function must be used only when the main PLL is disabled.
|
||||
* @param __PLLM__ specifies the division factor for PLL VCO input clock
|
||||
* This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
|
||||
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
|
||||
* frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
|
||||
* of 8 MHz to limit PLL jitter.
|
||||
* @retval None
|
||||
*
|
||||
*/
|
||||
#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
|
||||
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the main PLL clock source, multiplication and division factors.
|
||||
* @note This macro must be used only when the main PLL is disabled.
|
||||
* @note This macro preserves the PLL's output clocks enable state.
|
||||
*
|
||||
* @param __PLLSOURCE__ specifies the PLL entry clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
|
||||
* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
|
||||
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
|
||||
*
|
||||
* @param __PLLM__ specifies the division factor for PLL VCO input clock.
|
||||
* This parameter must be a value of @ref RCC_PLLM_Clock_Divider
|
||||
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
|
||||
* frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
|
||||
* of 8 MHz to limit PLL jitter.
|
||||
*
|
||||
* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.
|
||||
* This parameter must be a number between 8 and 127.
|
||||
* @note You have to set the PLLN parameter correctly to ensure that the VCO
|
||||
* output frequency is between 64 and 344 MHz.
|
||||
*
|
||||
* @param __PLLP__ specifies the division factor for SAI clock.
|
||||
* This parameter must be a number in the range (2 to 31).
|
||||
*
|
||||
* @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
|
||||
* This parameter must be in the range (2, 4, 6 or 8).
|
||||
* @note If the USB OTG FS is used in your application, you have to set the
|
||||
* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
|
||||
* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
|
||||
* correctly.
|
||||
* @param __PLLR__ specifies the division factor for the main system clock.
|
||||
* @note You have to set the PLLR parameter correctly to not exceed 170MHZ.
|
||||
* This parameter must be in the range (2, 4, 6 or 8).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
|
||||
MODIFY_REG(RCC->PLLCFGR, \
|
||||
(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
|
||||
RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
|
||||
((__PLLSOURCE__) | \
|
||||
(((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
|
||||
((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
|
||||
((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
|
||||
((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
|
||||
((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
|
||||
|
||||
/** @brief Macro to get the oscillator used as PLL clock source.
|
||||
* @retval The oscillator used as PLL clock source. The returned value can be one
|
||||
* of the following:
|
||||
* - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
|
||||
* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
|
||||
* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
|
||||
*/
|
||||
#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
|
||||
|
||||
/**
|
||||
* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK)
|
||||
* @note Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime
|
||||
* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
|
||||
* be stopped if used as System Clock.
|
||||
* @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC.
|
||||
* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz),
|
||||
* FDCAN (<=48 MHz) and QSPI (<=48 MHz).
|
||||
* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
|
||||
|
||||
#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
|
||||
|
||||
/**
|
||||
* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
|
||||
* @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC.
|
||||
* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz),
|
||||
* FDCAN (<=48 MHz) and QSPI (<=48 MHz).
|
||||
* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz)
|
||||
* @retval SET / RESET
|
||||
*/
|
||||
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the system clock source.
|
||||
* @param __SYSCLKSOURCE__ specifies the system clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
|
||||
* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
|
||||
* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the clock source used as system clock.
|
||||
* @retval The clock source used as system clock. The returned value can be one
|
||||
* of the following:
|
||||
* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
|
||||
* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
|
||||
* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
|
||||
*/
|
||||
#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
|
||||
* @note As the LSE is in the Backup domain and write access is denied to
|
||||
* this domain after reset, you have to enable write access using
|
||||
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
||||
* (to be done once after reset).
|
||||
* @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
|
||||
* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
|
||||
* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
|
||||
* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
|
||||
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
|
||||
|
||||
/** @brief Macro to configure the MCO clock.
|
||||
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
|
||||
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
|
||||
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
|
||||
* @param __MCODIV__ specifies the MCO clock prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
|
||||
* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
|
||||
* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
|
||||
* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
|
||||
* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
|
||||
*/
|
||||
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
|
||||
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
|
||||
|
||||
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
|
||||
* @brief macros to manage the specified RCC Flags and interrupts.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
|
||||
* the selected interrupts).
|
||||
* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
||||
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
||||
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
||||
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
||||
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
|
||||
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
|
||||
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
|
||||
* the selected interrupts).
|
||||
* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
||||
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
||||
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
||||
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
||||
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
|
||||
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
|
||||
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
|
||||
|
||||
/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
|
||||
* bits to clear the selected interrupt pending bits.
|
||||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
||||
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
||||
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
||||
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
||||
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
|
||||
* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
|
||||
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
|
||||
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the RCC interrupt has occurred or not.
|
||||
* @param __INTERRUPT__ specifies the RCC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
||||
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
||||
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
||||
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
|
||||
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
|
||||
* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
|
||||
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
|
||||
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Set RMVF bit to clear the reset flags.
|
||||
* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
|
||||
* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
|
||||
|
||||
/** @brief Check whether the selected RCC flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
|
||||
* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
|
||||
* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
|
||||
* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
|
||||
* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
|
||||
* @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
|
||||
* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
|
||||
* @arg @ref RCC_FLAG_BORRST BOR reset
|
||||
* @arg @ref RCC_FLAG_OBLRST OBLRST reset
|
||||
* @arg @ref RCC_FLAG_PINRST Pin reset
|
||||
* @arg @ref RCC_FLAG_SFTRST Software reset
|
||||
* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
|
||||
* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
|
||||
* @arg @ref RCC_FLAG_LPWRRST Low Power reset
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
|
||||
((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
|
||||
((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
|
||||
((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
|
||||
((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
|
||||
? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup RCC_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
/* Defines used for Flags */
|
||||
#define CR_REG_INDEX 1U
|
||||
#define BDCR_REG_INDEX 2U
|
||||
#define CSR_REG_INDEX 3U
|
||||
#define CRRCR_REG_INDEX 4U
|
||||
|
||||
#define RCC_FLAG_MASK 0x1FU
|
||||
|
||||
/* Define used for IS_RCC_CLOCKTYPE() */
|
||||
#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2) /*!< All clcoktype to configure */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup RCC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
|
||||
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
|
||||
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
|
||||
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
|
||||
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
|
||||
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
|
||||
|
||||
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
|
||||
((__HSE__) == RCC_HSE_BYPASS))
|
||||
|
||||
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
|
||||
((__LSE__) == RCC_LSE_BYPASS))
|
||||
|
||||
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
|
||||
|
||||
#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
|
||||
|
||||
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
|
||||
|
||||
#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
|
||||
|
||||
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
|
||||
((__PLL__) == RCC_PLL_ON))
|
||||
|
||||
#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
|
||||
((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_PLLSOURCE_HSE))
|
||||
|
||||
#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
|
||||
|
||||
#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
|
||||
|
||||
#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
|
||||
|
||||
#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
|
||||
((__VALUE__) == 6U) || ((__VALUE__) == 8U))
|
||||
|
||||
#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
|
||||
((__VALUE__) == 6U) || ((__VALUE__) == 8U))
|
||||
|
||||
#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
|
||||
|
||||
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
|
||||
((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
|
||||
|
||||
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
|
||||
((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
|
||||
((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
|
||||
((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
|
||||
((__HCLK__) == RCC_SYSCLK_DIV512))
|
||||
|
||||
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
|
||||
((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
|
||||
((__PCLK__) == RCC_HCLK_DIV16))
|
||||
|
||||
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
|
||||
((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
|
||||
|
||||
#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO_PA8) || \
|
||||
((__MCOX__) == RCC_MCO_PG10))
|
||||
|
||||
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
|
||||
((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
|
||||
((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
|
||||
((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
|
||||
|
||||
#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
|
||||
((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
|
||||
((__DIV__) == RCC_MCODIV_16))
|
||||
|
||||
#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
|
||||
((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
|
||||
((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
|
||||
((__DRIVE__) == RCC_LSEDRIVE_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include RCC HAL Extended module */
|
||||
#include "stm32g4xx_hal_rcc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RCC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup RCC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_RCC_DeInit(void);
|
||||
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
||||
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
|
||||
void HAL_RCC_EnableCSS(void);
|
||||
void HAL_RCC_EnableLSECSS(void);
|
||||
void HAL_RCC_DisableLSECSS(void);
|
||||
uint32_t HAL_RCC_GetSysClockFreq(void);
|
||||
uint32_t HAL_RCC_GetHCLKFreq(void);
|
||||
uint32_t HAL_RCC_GetPCLK1Freq(void);
|
||||
uint32_t HAL_RCC_GetPCLK2Freq(void);
|
||||
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
||||
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
|
||||
/* CSS NMI IRQ handler */
|
||||
void HAL_RCC_NMI_IRQHandler(void);
|
||||
/* User Callbacks in non blocking mode (IT mode) */
|
||||
void HAL_RCC_CSSCallback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_RCC_H */
|
||||
|
||||
1646
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h
Normal file
1646
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h
Normal file
@@ -0,0 +1,1646 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_rcc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RCC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_RCC_EX_H
|
||||
#define STM32G4xx_HAL_RCC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RCC extended clocks structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
|
||||
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
|
||||
|
||||
uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
|
||||
This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
|
||||
|
||||
uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
|
||||
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
|
||||
#if defined(USART3)
|
||||
uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
|
||||
This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
|
||||
#endif /* UART3 */
|
||||
|
||||
#if defined(UART4)
|
||||
uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
|
||||
This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
|
||||
This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
|
||||
|
||||
#endif /* UART5 */
|
||||
|
||||
uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
|
||||
This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
|
||||
|
||||
uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
|
||||
This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
|
||||
|
||||
uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
|
||||
This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
|
||||
|
||||
uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
|
||||
This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
|
||||
|
||||
#if defined(I2C4)
|
||||
|
||||
uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
|
||||
This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
|
||||
#endif /* I2C4 */
|
||||
|
||||
uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
|
||||
This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
|
||||
|
||||
uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
|
||||
This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
|
||||
|
||||
uint32_t I2sClockSelection; /*!< Specifies I2S clock source.
|
||||
This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
|
||||
#if defined(FDCAN1)
|
||||
|
||||
uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source.
|
||||
This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */
|
||||
#endif /* FDCAN1 */
|
||||
#if defined(USB)
|
||||
|
||||
uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG).
|
||||
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
|
||||
#endif /* USB */
|
||||
|
||||
uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB).
|
||||
This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
|
||||
|
||||
uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source.
|
||||
This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source.
|
||||
This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source.
|
||||
This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */
|
||||
#endif
|
||||
|
||||
uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
|
||||
This parameter can be a value of @ref RCC_RTC_Clock_Source */
|
||||
}RCC_PeriphCLKInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RCC_CRS Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
|
||||
This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
|
||||
|
||||
uint32_t Source; /*!< Specifies the SYNC signal source.
|
||||
This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
|
||||
|
||||
uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
|
||||
This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
|
||||
|
||||
uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
|
||||
It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
|
||||
This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
|
||||
|
||||
uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
|
||||
This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
|
||||
|
||||
uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
|
||||
This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
|
||||
|
||||
}RCC_CRSInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RCC_CRS Synchronization structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
|
||||
This parameter must be a number between 0 and 0xFFFF */
|
||||
|
||||
uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
|
||||
This parameter must be a number between 0 and 0x7F */
|
||||
|
||||
uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
|
||||
value latched in the time of the last SYNC event.
|
||||
This parameter must be a number between 0 and 0xFFFF */
|
||||
|
||||
uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
|
||||
frequency error counter latched in the time of the last SYNC event.
|
||||
It shows whether the actual frequency is below or above the target.
|
||||
This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
|
||||
|
||||
}RCC_CRSSynchroInfoTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */
|
||||
#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PERIPHCLK_USART1 0x00000001U
|
||||
#define RCC_PERIPHCLK_USART2 0x00000002U
|
||||
#define RCC_PERIPHCLK_USART3 0x00000004U
|
||||
#if defined(UART4)
|
||||
#define RCC_PERIPHCLK_UART4 0x00000008U
|
||||
#endif /* UART4 */
|
||||
#if defined(UART5)
|
||||
#define RCC_PERIPHCLK_UART5 0x00000010U
|
||||
#endif /* UART5 */
|
||||
#define RCC_PERIPHCLK_LPUART1 0x00000020U
|
||||
#define RCC_PERIPHCLK_I2C1 0x00000040U
|
||||
#define RCC_PERIPHCLK_I2C2 0x00000080U
|
||||
#define RCC_PERIPHCLK_I2C3 0x00000100U
|
||||
#define RCC_PERIPHCLK_LPTIM1 0x00000200U
|
||||
#define RCC_PERIPHCLK_SAI1 0x00000400U
|
||||
#define RCC_PERIPHCLK_I2S 0x00000800U
|
||||
#if defined(FDCAN1)
|
||||
#define RCC_PERIPHCLK_FDCAN 0x00001000U
|
||||
#endif /* FDCAN1 */
|
||||
#define RCC_PERIPHCLK_USB 0x00002000U
|
||||
#define RCC_PERIPHCLK_RNG 0x00004000U
|
||||
#define RCC_PERIPHCLK_ADC12 0x00008000U
|
||||
#if defined(ADC345_COMMON)
|
||||
#define RCC_PERIPHCLK_ADC345 0x00010000U
|
||||
#endif /* ADC345_COMMON */
|
||||
#if defined(I2C4)
|
||||
#define RCC_PERIPHCLK_I2C4 0x00020000U
|
||||
#endif /* I2C4 */
|
||||
#if defined(QUADSPI)
|
||||
#define RCC_PERIPHCLK_QSPI 0x00040000U
|
||||
#endif /* QUADSPI */
|
||||
#define RCC_PERIPHCLK_RTC 0x00080000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U
|
||||
#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
|
||||
#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
|
||||
#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
|
||||
#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
|
||||
#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
|
||||
#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
|
||||
#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(UART4)
|
||||
/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
|
||||
#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
|
||||
#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
|
||||
#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
|
||||
#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* UART5 */
|
||||
|
||||
/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
|
||||
#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
|
||||
#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
|
||||
#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
|
||||
#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
|
||||
#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
|
||||
#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
|
||||
#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U
|
||||
#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
|
||||
#define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1
|
||||
#define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SPI_I2S_SUPPORT)
|
||||
/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U
|
||||
#define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0
|
||||
#define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1
|
||||
#define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SPI_I2S_SUPPORT */
|
||||
|
||||
#if defined(FDCAN1)
|
||||
/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FDCANCLKSOURCE_HSE 0x00000000U
|
||||
#define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0
|
||||
#define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RNGCLKSOURCE_HSI48 0x00000000U
|
||||
#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_USBCLKSOURCE_HSI48 0x00000000U
|
||||
#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_ADC12CLKSOURCE_NONE 0x00000000U
|
||||
#define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0
|
||||
#define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
/** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_ADC345CLKSOURCE_NONE 0x00000000U
|
||||
#define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0
|
||||
#define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#if defined(I2C4)
|
||||
/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U
|
||||
#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
|
||||
#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* I2C4 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
/** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U
|
||||
#define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0
|
||||
#define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
|
||||
* @{
|
||||
*/
|
||||
#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_NONE 0x00000000U
|
||||
#define RCC_CRS_TIMEOUT 0x00000001U
|
||||
#define RCC_CRS_SYNCOK 0x00000002U
|
||||
#define RCC_CRS_SYNCWARN 0x00000004U
|
||||
#define RCC_CRS_SYNCERR 0x00000008U
|
||||
#define RCC_CRS_SYNCMISS 0x00000010U
|
||||
#define RCC_CRS_TRIMOVF 0x00000020U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
|
||||
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
|
||||
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */
|
||||
#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
|
||||
#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
|
||||
#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
|
||||
#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
|
||||
#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
|
||||
#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
|
||||
#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
|
||||
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds
|
||||
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval.
|
||||
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
|
||||
corresponds to a higher output frequency */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
|
||||
#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
|
||||
#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
|
||||
#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
|
||||
#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
|
||||
#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
|
||||
#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
|
||||
#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
|
||||
#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
|
||||
#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
|
||||
#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
|
||||
#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
|
||||
#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
|
||||
#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Macro to configure the USART1 clock (USART1CLK).
|
||||
*
|
||||
* @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
|
||||
* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
|
||||
* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
|
||||
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USART1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
|
||||
* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
|
||||
* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
|
||||
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
|
||||
|
||||
/** @brief Macro to configure the USART2 clock (USART2CLK).
|
||||
*
|
||||
* @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
|
||||
* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
|
||||
* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
|
||||
* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USART2 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
|
||||
* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
|
||||
* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
|
||||
* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
|
||||
|
||||
/** @brief Macro to configure the USART3 clock (USART3CLK).
|
||||
*
|
||||
* @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
|
||||
* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
|
||||
* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
|
||||
* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USART3 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
|
||||
* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
|
||||
* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
|
||||
* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
|
||||
|
||||
#if defined(UART4)
|
||||
/** @brief Macro to configure the UART4 clock (UART4CLK).
|
||||
*
|
||||
* @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
|
||||
* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
|
||||
* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
|
||||
* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the UART4 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
|
||||
* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
|
||||
* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
|
||||
* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
|
||||
/** @brief Macro to configure the UART5 clock (UART5CLK).
|
||||
*
|
||||
* @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
|
||||
* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
|
||||
* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
|
||||
* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the UART5 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
|
||||
* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
|
||||
* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
|
||||
* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
|
||||
|
||||
#endif /* UART5 */
|
||||
|
||||
/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
|
||||
*
|
||||
* @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
|
||||
* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
|
||||
* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
|
||||
* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the LPUART1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
|
||||
* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
|
||||
* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
|
||||
* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
|
||||
|
||||
/** @brief Macro to configure the I2C1 clock (I2C1CLK).
|
||||
*
|
||||
* @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
|
||||
* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
|
||||
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2C1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
|
||||
* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
|
||||
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
|
||||
|
||||
|
||||
/** @brief Macro to configure the I2C2 clock (I2C2CLK).
|
||||
*
|
||||
* @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
|
||||
* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
|
||||
* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2C2 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
|
||||
* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
|
||||
* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
|
||||
|
||||
/** @brief Macro to configure the I2C3 clock (I2C3CLK).
|
||||
*
|
||||
* @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
|
||||
* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
|
||||
* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2C3 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
|
||||
* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
|
||||
* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
|
||||
|
||||
#if defined(I2C4)
|
||||
|
||||
/** @brief Macro to configure the I2C4 clock (I2C4CLK).
|
||||
*
|
||||
* @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
|
||||
* @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
|
||||
* @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2C4 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
|
||||
* @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
|
||||
* @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
|
||||
|
||||
#endif /* I2C4 */
|
||||
|
||||
/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
|
||||
*
|
||||
* @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
|
||||
* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
|
||||
* @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
|
||||
* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the LPTIM1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
|
||||
* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
|
||||
* @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
|
||||
* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
|
||||
|
||||
/**
|
||||
* @brief Macro to configure the SAI1 clock source.
|
||||
* @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
|
||||
* from the HSI, system PLL, System Clock or external clock.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
|
||||
* @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
|
||||
* @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
|
||||
* @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#if defined(SAI1)
|
||||
#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the SAI1 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
|
||||
* @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
|
||||
* @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
|
||||
* @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI
|
||||
*
|
||||
*/
|
||||
#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
|
||||
#endif /* SAI1 */
|
||||
|
||||
#if defined(SPI_I2S_SUPPORT)
|
||||
/**
|
||||
* @brief Macro to configure the I2S clock source.
|
||||
* @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived
|
||||
* from the HSI, system PLL, System Clock or external clock.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
|
||||
* @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
|
||||
* @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT
|
||||
* @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the I2S clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
|
||||
* @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
|
||||
* @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT
|
||||
* @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI
|
||||
*
|
||||
*/
|
||||
#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))
|
||||
#endif /* SPI_I2S_SUPPORT */
|
||||
|
||||
#if defined(FDCAN1)
|
||||
/**
|
||||
* @brief Macro to configure the FDCAN clock source.
|
||||
* @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived
|
||||
* from the HSE, system PLL or PCLK1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
|
||||
* @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
|
||||
* @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the FDCAN clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
|
||||
* @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
|
||||
* @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
|
||||
*
|
||||
*/
|
||||
#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL)))
|
||||
#endif /* FDCAN1 */
|
||||
|
||||
/** @brief Macro to configure the RNG clock.
|
||||
*
|
||||
* @note USB and RNG peripherals share the same 48MHz clock source.
|
||||
*
|
||||
* @param __RNG_CLKSOURCE__ specifies the RNG clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48
|
||||
* @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the RNG clock.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48
|
||||
* @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
|
||||
|
||||
#if defined(USB)
|
||||
|
||||
/** @brief Macro to configure the USB clock (USBCLK).
|
||||
*
|
||||
* @note USB, RNG peripherals share the same 48MHz clock source.
|
||||
*
|
||||
* @param __USB_CLKSOURCE__ specifies the USB clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the USB clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
|
||||
* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
|
||||
|
||||
#endif /* USB */
|
||||
|
||||
/** @brief Macro to configure the ADC12 interface clock.
|
||||
* @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock
|
||||
* @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock
|
||||
* @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__))
|
||||
|
||||
/** @brief Macro to get the ADC12 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock
|
||||
* @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock
|
||||
* @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL))
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
/** @brief Macro to configure the ADC345 interface clock.
|
||||
* @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock
|
||||
* @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock
|
||||
* @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__)
|
||||
|
||||
/** @brief Macro to get the ADC345 clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock
|
||||
* @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock
|
||||
* @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL))
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
|
||||
/** @brief Macro to configure the QuadSPI clock.
|
||||
* @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock
|
||||
* @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock
|
||||
* @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \
|
||||
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__)
|
||||
|
||||
/** @brief Macro to get the QuadSPI clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
* @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock
|
||||
* @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock
|
||||
* @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock
|
||||
*/
|
||||
#define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL))
|
||||
|
||||
#endif /* QUADSPI */
|
||||
|
||||
/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
|
||||
* @brief macros to manage the specified RCC Flags and interrupts.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the RCC LSE CSS Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
/**
|
||||
* @brief Disable the RCC LSE CSS Extended Interrupt Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
/**
|
||||
* @brief Enable the RCC LSE CSS Event Line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
/**
|
||||
* @brief Disable the RCC LSE CSS Event Line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
/**
|
||||
* @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
/**
|
||||
* @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
|
||||
* @retval EXTI RCC LSE CSS Line Status.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
/**
|
||||
* @brief Clear the RCC LSE CSS EXTI flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CRS interrupts.
|
||||
* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
|
||||
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
|
||||
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
|
||||
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CRS interrupts.
|
||||
* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
|
||||
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
|
||||
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
|
||||
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the CRS interrupt has occurred or not.
|
||||
* @param __INTERRUPT__ specifies the CRS interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
|
||||
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
|
||||
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
|
||||
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the CRS interrupt pending bits
|
||||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
|
||||
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
|
||||
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
|
||||
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
|
||||
* @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
|
||||
* @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
|
||||
* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
|
||||
*/
|
||||
/* CRS IT Error Mask */
|
||||
#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
|
||||
|
||||
#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
|
||||
if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified CRS flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
|
||||
* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
|
||||
* @arg @ref RCC_CRS_FLAG_ERR Error
|
||||
* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
|
||||
* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
|
||||
* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
|
||||
* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
|
||||
* @retval The new state of _FLAG_ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the CRS specified FLAG.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
|
||||
* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
|
||||
* @arg @ref RCC_CRS_FLAG_ERR Error
|
||||
* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
|
||||
* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
|
||||
* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
|
||||
* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
|
||||
* @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
/* CRS Flag Error Mask */
|
||||
#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
|
||||
|
||||
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
|
||||
if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
WRITE_REG(CRS->ICR, (__FLAG__)); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the oscillator clock for frequency error counter.
|
||||
* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the oscillator clock for frequency error counter.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
|
||||
|
||||
/**
|
||||
* @brief Enable the automatic hardware adjustment of TRIM bits.
|
||||
* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the automatic hardware adjustment of TRIM bits.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
|
||||
|
||||
/**
|
||||
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
|
||||
* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
|
||||
* of the synchronization source after prescaling. It is then decreased by one in order to
|
||||
* reach the expected synchronization on the zero value. The formula is the following:
|
||||
* RELOAD = (fTARGET / fSYNC) -1
|
||||
* @param __FTARGET__ Target frequency (value in Hz)
|
||||
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RCCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
|
||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
void HAL_RCCEx_EnableLSECSS(void);
|
||||
void HAL_RCCEx_DisableLSECSS(void);
|
||||
void HAL_RCCEx_EnableLSECSS_IT(void);
|
||||
void HAL_RCCEx_LSECSS_IRQHandler(void);
|
||||
void HAL_RCCEx_LSECSS_Callback(void);
|
||||
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
|
||||
void HAL_RCCEx_DisableLSCO(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCCEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
|
||||
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
|
||||
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
|
||||
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
|
||||
void HAL_RCCEx_CRS_IRQHandler(void);
|
||||
void HAL_RCCEx_CRS_SyncOkCallback(void);
|
||||
void HAL_RCCEx_CRS_SyncWarnCallback(void);
|
||||
void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
|
||||
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup RCCEx_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_LSCOSOURCE_LSE))
|
||||
|
||||
#if defined(STM32G474xx) || defined(STM32G484xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
#elif defined(STM32G473xx) || defined(STM32G483xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
|
||||
#elif defined(STM32G471xx)
|
||||
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
|
||||
#elif defined(STM32G431xx) || defined(STM32G441xx)
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
|
||||
#elif defined(STM32G411xB) || defined(STM32G411xC)
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
#elif defined(STM32G414xx)
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
#elif defined(STM32GBK1CB)
|
||||
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
|
||||
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
|
||||
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
|
||||
#endif /* STM32G474xx || STM32G484xx */
|
||||
|
||||
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
|
||||
((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
|
||||
|
||||
#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
|
||||
|
||||
#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
|
||||
|
||||
#if defined(UART4)
|
||||
#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
|
||||
#endif /* UART4 */
|
||||
|
||||
#if defined(UART5)
|
||||
#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
|
||||
|
||||
#endif /* UART5 */
|
||||
|
||||
#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
|
||||
|
||||
#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
|
||||
((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
|
||||
|
||||
#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
|
||||
((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
|
||||
|
||||
#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
|
||||
((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
|
||||
|
||||
#if defined(I2C4)
|
||||
|
||||
#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
|
||||
((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
|
||||
|
||||
#endif /* I2C4 */
|
||||
|
||||
#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
|
||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
|
||||
|
||||
#if defined(SAI1)
|
||||
#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \
|
||||
((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
|
||||
#endif /* SAI1 */
|
||||
|
||||
#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \
|
||||
((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \
|
||||
((__SOURCE__) == RCC_I2SCLKSOURCE_HSI))
|
||||
|
||||
#if defined(FDCAN1)
|
||||
#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
|
||||
((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))
|
||||
|
||||
#endif /* FDCAN1 */
|
||||
#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
|
||||
((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))
|
||||
|
||||
#if defined(USB)
|
||||
#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
|
||||
((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
|
||||
|
||||
#endif /* USB */
|
||||
|
||||
#define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \
|
||||
((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK))
|
||||
|
||||
#if defined(ADC345_COMMON)
|
||||
#define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \
|
||||
((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \
|
||||
((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK))
|
||||
#endif /* ADC345_COMMON */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
|
||||
#define IS_RCC_QSPICLKSOURCE(__SOURCE__) \
|
||||
(((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \
|
||||
((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \
|
||||
((__SOURCE__) == RCC_QSPICLKSOURCE_PLL))
|
||||
|
||||
#endif /* QUADSPI */
|
||||
|
||||
#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
|
||||
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
|
||||
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
|
||||
|
||||
#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
|
||||
((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
|
||||
((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
|
||||
((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
|
||||
|
||||
#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
|
||||
((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
|
||||
|
||||
#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
|
||||
|
||||
#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
|
||||
|
||||
#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
|
||||
|
||||
#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
|
||||
((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_RCC_EX_H */
|
||||
|
||||
379
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rng.h
Normal file
379
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rng.h
Normal file
@@ -0,0 +1,379 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_rng.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RNG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_RNG_H
|
||||
#define STM32G4xx_HAL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (RNG)
|
||||
|
||||
/** @defgroup RNG RNG
|
||||
* @brief RNG HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types RNG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockErrorDetection; /*!< CED Clock error detection */
|
||||
} RNG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
|
||||
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
|
||||
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
|
||||
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
|
||||
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
|
||||
|
||||
} HAL_RNG_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __RNG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
{
|
||||
RNG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
RNG_InitTypeDef Init; /*!< RNG configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RNG locking object */
|
||||
|
||||
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< RNG Error code */
|
||||
|
||||
uint32_t RandomNumber; /*!< Last Generated RNG Data */
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
|
||||
void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
} RNG_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL RNG Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
|
||||
|
||||
HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
|
||||
HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
|
||||
|
||||
} HAL_RNG_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL RNG Callback pointer definition
|
||||
*/
|
||||
typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
|
||||
typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
|
||||
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Constants RNG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
|
||||
#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
|
||||
#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
|
||||
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
|
||||
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
|
||||
* @{
|
||||
*/
|
||||
#define RNG_CED_ENABLE 0x00000000U /*!< Clock error detection Enabled */
|
||||
#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Error_Definition RNG Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
|
||||
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
|
||||
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
|
||||
#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Macros RNG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RNG handle state
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_RNG_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG peripheral.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG peripheral.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Check the selected RNG flag status.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @param __FLAG__ RNG flag
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_FLAG_DRDY: Data ready
|
||||
* @arg RNG_FLAG_CECS: Clock error current status
|
||||
* @arg RNG_FLAG_SECS: Seed error current status
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the selected RNG flag status.
|
||||
* @param __HANDLE__ RNG handle
|
||||
* @param __FLAG__ RNG flag to clear
|
||||
* @note WARNING: This is a dummy macro for HAL code alignment,
|
||||
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG interrupts.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG interrupts.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RNG interrupt has occurred or not.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_DRDY: Data ready interrupt
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the RNG interrupt status flags.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Functions RNG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
|
||||
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
|
||||
pRNG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
|
||||
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Macros RNG Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
|
||||
((IT) == RNG_IT_SEI))
|
||||
|
||||
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
|
||||
((FLAG) == RNG_FLAG_CECS) || \
|
||||
((FLAG) == RNG_FLAG_SECS))
|
||||
|
||||
/**
|
||||
* @brief Verify the RNG Clock Error Detection mode.
|
||||
* @param __MODE__ RNG Clock Error Detection mode
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \
|
||||
((__MODE__) == RNG_CED_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* RNG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32G4xx_HAL_RNG_H */
|
||||
|
||||
1023
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc.h
Normal file
1023
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc.h
Normal file
@@ -0,0 +1,1023 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_RTC_H
|
||||
#define STM32G4xx_HAL_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
|
||||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
|
||||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
|
||||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
|
||||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
|
||||
|
||||
} HAL_RTCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
|
||||
|
||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
||||
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
|
||||
|
||||
uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
|
||||
This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */
|
||||
|
||||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
||||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
|
||||
|
||||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
|
||||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
|
||||
|
||||
uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode.
|
||||
This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
|
||||
} RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
|
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
|
||||
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity */
|
||||
|
||||
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
|
||||
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity.
|
||||
This field will be used only by HAL_RTC_GetTime function */
|
||||
|
||||
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
|
||||
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
|
||||
please use HAL_RTC_DST_xxx functions */
|
||||
} RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
|
||||
} RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
|
||||
|
||||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
|
||||
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
|
||||
|
||||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint32_t Alarm; /*!< Specifies the alarm .
|
||||
This parameter can be a value of @ref RTC_Alarms_Definitions */
|
||||
} RTC_AlarmTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __RTC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
||||
{
|
||||
RTC_TypeDef *Instance; /*!< Legacy register base address. Not used anymore,
|
||||
the driver directly uses cmsis base address */
|
||||
|
||||
RTC_InitTypeDef Init; /*!< RTC required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RTC locking object */
|
||||
|
||||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
|
||||
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
|
||||
void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */
|
||||
void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */
|
||||
void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
|
||||
|
||||
void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
|
||||
void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
|
||||
#if (RTC_TAMP_NB == 3)
|
||||
void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
|
||||
#endif /* RTC_TAMP_NB */
|
||||
void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */
|
||||
#ifdef RTC_TAMP_INT_2_SUPPORT
|
||||
void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */
|
||||
#endif /* RTC_TAMP_INT_2_SUPPORT */
|
||||
void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */
|
||||
void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 4 Event callback */
|
||||
void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */
|
||||
#ifdef RTC_TAMP_INT_6_SUPPORT
|
||||
void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */
|
||||
#endif /* RTC_TAMP_INT_6_SUPPORT */
|
||||
#ifdef RTC_TAMP_INT_7_SUPPORT
|
||||
void (* InternalTamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 7 Event callback */
|
||||
#endif /* RTC_TAMP_INT_7_SUPPORT */
|
||||
|
||||
void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
||||
|
||||
} RTC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL LPTIM Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
|
||||
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */
|
||||
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */
|
||||
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */
|
||||
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
|
||||
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
|
||||
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
|
||||
HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 0x07U, /*!< RTC Internal Tamper 1 Callback ID */
|
||||
HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 0x08U, /*!< RTC Internal Tamper 2 Callback ID */
|
||||
HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 0x09U, /*!< RTC Internal Tamper 3 Callback ID */
|
||||
HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 0x0AU, /*!< RTC Internal Tamper 4 Callback ID */
|
||||
HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 0x0BU, /*!< RTC Internal Tamper 5 Callback ID */
|
||||
HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 0x0CU, /*!< RTC Internal Tamper 6 Callback ID */
|
||||
HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID = 0x0DU, /*!< RTC Internal Tamper 7 Callback ID */
|
||||
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
|
||||
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
|
||||
} HAL_RTC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL RTC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Hour_Formats RTC Hour Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT_24 0x00000000U
|
||||
#define RTC_HOURFORMAT_12 RTC_CR_FMT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_DISABLE 0x00000000U
|
||||
#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
|
||||
#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
|
||||
#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
|
||||
#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
|
||||
#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000U
|
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_PULLUP_NONE 0x00000000U
|
||||
#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_REMAP_NONE 0x00000000U
|
||||
#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT12_AM 0x0U
|
||||
#define RTC_HOURFORMAT12_PM 0x1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
|
||||
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_STOREOPERATION_RESET 0x00000000U
|
||||
#define RTC_STOREOPERATION_SET RTC_CR_BKP
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FORMAT_BIN 0x00000000U
|
||||
#define RTC_FORMAT_BCD 0x00000001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Coded in BCD format */
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
|
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05U)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07U)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMMASK_NONE 0x00000000U
|
||||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
|
||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
|
||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
|
||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
|
||||
#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | \
|
||||
RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARM_A RTC_CR_ALRAE
|
||||
#define RTC_ALARM_B RTC_CR_ALRBE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] not used in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] not used in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] not used in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] not used in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] not used in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] not used in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] not used in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] not used in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] not used in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] not used in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] not used in Alarm
|
||||
comparison. Only SS[13:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */
|
||||
#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */
|
||||
#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */
|
||||
#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_MASK 0x001FU /*!< RTC flags mask (5bits) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
||||
* Elements values convention: 000000XX000YYYYYb
|
||||
* - YYYYY : Interrupt flag position in the XX register (5bits)
|
||||
* - XX : Interrupt status register (2bits)
|
||||
* - 01: ICSR register
|
||||
* - 10: SR or SCR or MISR registers
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
|
||||
#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */
|
||||
#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */
|
||||
#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */
|
||||
#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */
|
||||
#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */
|
||||
#define RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos) /*!< Alarm B write flag */
|
||||
#define RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos) /*!< Alarm A write flag */
|
||||
#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */
|
||||
#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */
|
||||
#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */
|
||||
#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */
|
||||
#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */
|
||||
#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */
|
||||
#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */
|
||||
#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */
|
||||
#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */
|
||||
#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */
|
||||
#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Macros RTC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RTC handle state
|
||||
* @param __HANDLE__ RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL;\
|
||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection for RTC registers.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xCAU; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53U; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection for RTC registers.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xFFU; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Calendar is initialized.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Add 1 hour (summer time change).
|
||||
* @note This interface is deprecated.
|
||||
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __BKP__ Backup
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_STOREOPERATION_RESET
|
||||
* @arg @ref RTC_STOREOPERATION_SET
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \
|
||||
do { \
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
|
||||
SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H); \
|
||||
MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
|
||||
} while(0);
|
||||
|
||||
/**
|
||||
* @brief Subtract 1 hour (winter time change).
|
||||
* @note This interface is deprecated.
|
||||
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __BKP__ Backup
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_STOREOPERATION_RESET
|
||||
* @arg @ref RTC_STOREOPERATION_SET
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \
|
||||
do { \
|
||||
__HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
|
||||
SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H); \
|
||||
MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
|
||||
__HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
|
||||
} while(0);
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_ALRA Alarm A interrupt
|
||||
* @arg @ref RTC_IT_ALRB Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarms flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Alarm Flag sources to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_ALRAF
|
||||
* @arg @ref RTC_FLAG_ALRBF
|
||||
* @arg @ref RTC_FLAG_ALRAWF
|
||||
* @arg @ref RTC_FLAG_ALRBWF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarms pending flags.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_ALRAF
|
||||
* @arg @ref RTC_FLAG_ALRBF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? (((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRAF))) : \
|
||||
((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRBF)))
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief set rising edge interrupt on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief set rising edge interrupt on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief clear interrupt on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include RTC HAL Extended module */
|
||||
#include "stm32g4xx_hal_rtc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Functions RTC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID,
|
||||
pRTC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
|
||||
* @{
|
||||
*/
|
||||
/* RTC Time and Date functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
|
||||
* @{
|
||||
*/
|
||||
/* RTC Alarm functions ********************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
|
||||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Constants RTC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Masks Definition */
|
||||
#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
|
||||
RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
|
||||
RTC_TR_SU)
|
||||
#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
|
||||
RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
|
||||
RTC_DR_DU)
|
||||
#define RTC_ICSR_RESERVED_MASK (RTC_ICSR_RECALPF | RTC_ICSR_INIT | RTC_ICSR_INITF | \
|
||||
RTC_ICSR_RSF | RTC_ICSR_INITS | RTC_ICSR_SHPF | \
|
||||
RTC_ICSR_WUTWF | RTC_ICSR_ALRBWF | RTC_ICSR_ALRAWF)
|
||||
#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
|
||||
#define RTC_INIT_MASK 0xFFFFFFFFU
|
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
|
||||
((OUTPUT) == RTC_OUTPUT_ALARMB) || \
|
||||
((OUTPUT) == RTC_OUTPUT_WAKEUP) || \
|
||||
((OUTPUT) == RTC_OUTPUT_TAMPER))
|
||||
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
|
||||
((FORMAT) == RTC_HOURFORMAT_24))
|
||||
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
|
||||
((POL) == RTC_OUTPUT_POLARITY_LOW))
|
||||
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
||||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
|
||||
|
||||
#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
|
||||
((TYPE) == RTC_OUTPUT_PULLUP_ON))
|
||||
|
||||
#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
|
||||
((REMAP) == RTC_OUTPUT_REMAP_POS1))
|
||||
|
||||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
|
||||
((PM) == RTC_HOURFORMAT12_PM))
|
||||
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
|
||||
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
|
||||
((OPERATION) == RTC_STOREOPERATION_SET))
|
||||
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
|
||||
((FORMAT) == RTC_FORMAT_BCD))
|
||||
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
|
||||
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
|
||||
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
|
||||
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
||||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
||||
|
||||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)
|
||||
|
||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \
|
||||
((ALARM) == RTC_ALARM_B))
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0UL) || \
|
||||
(((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))
|
||||
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
|
||||
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
|
||||
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
|
||||
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
|
||||
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
|
||||
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions -------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Functions RTC Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
|
||||
uint8_t RTC_ByteToBcd2(uint8_t Value);
|
||||
uint8_t RTC_Bcd2ToByte(uint8_t Value);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_RTC_H */
|
||||
1383
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc_ex.h
Normal file
1383
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc_ex.h
Normal file
@@ -0,0 +1,1383 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_rtc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RTC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_RTC_EX_H
|
||||
#define STM32G4xx_HAL_RTC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx RTCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Tamper; /*!< Specifies the Tamper Pin.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Pins */
|
||||
|
||||
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Trigger */
|
||||
|
||||
uint32_t NoErase; /*!< Specifies the Tamper no erase mode.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
|
||||
|
||||
uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
|
||||
|
||||
uint32_t Filter; /*!< Specifies the TAMP Filter Tamper.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Filter */
|
||||
|
||||
uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies */
|
||||
|
||||
uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration */
|
||||
|
||||
uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
|
||||
This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */
|
||||
|
||||
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
|
||||
} RTC_TamperTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IntTamper; /*!< Specifies the Internal Tamper Pin.
|
||||
This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */
|
||||
|
||||
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
|
||||
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
|
||||
} RTC_InternalTamperTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
|
||||
#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
|
||||
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
|
||||
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
|
||||
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibration
|
||||
period is 32s, else 2exp20 RTCCLK pulses */
|
||||
#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration
|
||||
period is 16s, else 2exp19 RTCCLK pulses */
|
||||
#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration
|
||||
period is 8s, else 2exp18 RTCCLK pulses */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
|
||||
during a X -second window = Y - CALM[8:0]
|
||||
with Y = 512, 256, 128 when X = 32, 16, 8 */
|
||||
#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
|
||||
during a 32-second window = CALM[8:0] */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CALIBOUTPUT_512HZ 0x00000000U
|
||||
#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SHIFTADD1S_RESET 0x00000000U
|
||||
#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Pins RTCEx Tamper Pins Definition
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPER_1 TAMP_CR1_TAMP1E
|
||||
#define RTC_TAMPER_2 TAMP_CR1_TAMP2E
|
||||
#if (RTC_TAMP_NB == 3)
|
||||
#define RTC_TAMPER_3 TAMP_CR1_TAMP3E
|
||||
#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3 )
|
||||
#elif (RTC_TAMP_NB == 8)
|
||||
#define RTC_TAMPER_3 TAMP_CR1_TAMP3E
|
||||
#define RTC_TAMPER_4 TAMP_CR1_TAMP4E
|
||||
#define RTC_TAMPER_5 TAMP_CR1_TAMP5E
|
||||
#define RTC_TAMPER_6 TAMP_CR1_TAMP6E
|
||||
#define RTC_TAMPER_7 TAMP_CR1_TAMP7E
|
||||
#define RTC_TAMPER_8 TAMP_CR1_TAMP8E
|
||||
#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\
|
||||
RTC_TAMPER_3 | RTC_TAMPER_4 |\
|
||||
RTC_TAMPER_5 | RTC_TAMPER_6 |\
|
||||
RTC_TAMPER_7 | RTC_TAMPER_8 )
|
||||
#else
|
||||
#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2)
|
||||
#endif /* RTC_TAMP_NB */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Internal_Tamper_Pins RTCEx Internal Tamper Pins Definition
|
||||
* @{
|
||||
*/
|
||||
#if defined (RTC_TAMP_INT_1_SUPPORT)
|
||||
#define RTC_INT_TAMPER_1 TAMP_CR1_ITAMP1E
|
||||
#else
|
||||
#define RTC_INT_TAMPER_1 0U
|
||||
#endif /* RTC_TAMP_INT_1_SUPPORT */
|
||||
#if defined (RTC_TAMP_INT_2_SUPPORT)
|
||||
#define RTC_INT_TAMPER_2 TAMP_CR1_ITAMP2E
|
||||
#else
|
||||
#define RTC_INT_TAMPER_2 0U
|
||||
#endif /* RTC_TAMP_INT_2_SUPPORT */
|
||||
#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E
|
||||
#define RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E
|
||||
#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E
|
||||
#if defined (RTC_TAMP_INT_6_SUPPORT)
|
||||
#define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E
|
||||
#else
|
||||
#define RTC_INT_TAMPER_6 0U
|
||||
#endif /* RTC_TAMP_INT_6_SUPPORT */
|
||||
#if defined (RTC_TAMP_INT_7_SUPPORT)
|
||||
#define RTC_INT_TAMPER_7 TAMP_CR1_ITAMP7E
|
||||
#else
|
||||
#define RTC_INT_TAMPER_7 0U
|
||||
#endif /* RTC_TAMP_INT_7_SUPPORT */
|
||||
#if defined (RTC_TAMP_INT_8_SUPPORT)
|
||||
#define RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E
|
||||
#else
|
||||
#define RTC_INT_TAMPER_8 0U
|
||||
#endif /* RTC_TAMP_INT_8_SUPPORT */
|
||||
|
||||
#define RTC_INT_TAMPER_ALL ( RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\
|
||||
RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\
|
||||
RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\
|
||||
RTC_INT_TAMPER_7 | RTC_INT_TAMPER_8 )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
|
||||
#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
|
||||
#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
|
||||
#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_MaskFlag RTCEx Tamper MaskFlag
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERMASK_FLAG_DISABLE 0x00U
|
||||
#define RTC_TAMPERMASK_FLAG_ENABLE 0x01U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00U
|
||||
#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
|
||||
#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8
|
||||
consecutive samples at the active level */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 32768 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 16384 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 8192 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 4096 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 2048 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 1024 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 512 */
|
||||
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \
|
||||
TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
|
||||
sampling during 1 RTCCLK cycle */
|
||||
#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
|
||||
sampling during 2 RTCCLK cycles */
|
||||
#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before
|
||||
sampling during 4 RTCCLK cycles */
|
||||
#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before
|
||||
sampling during 8 RTCCLK cycles */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */
|
||||
#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
|
||||
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Internal_Tamper_Interrupt RTCEx Internal Tamper Interrupt
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TAMP_1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */
|
||||
#define RTC_IT_TAMP_2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */
|
||||
#if (RTC_TAMP_NB == 3)
|
||||
#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */
|
||||
#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 | RTC_IT_TAMP_3 )
|
||||
#elif (RTC_TAMP_NB == 8)
|
||||
#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */
|
||||
#define RTC_IT_TAMP_4 TAMP_IER_TAMP4IE /*!< Tamper 4 Interrupt */
|
||||
#define RTC_IT_TAMP_5 TAMP_IER_TAMP5IE /*!< Tamper 5 Interrupt */
|
||||
#define RTC_IT_TAMP_6 TAMP_IER_TAMP6IE /*!< Tamper 6 Interrupt */
|
||||
#define RTC_IT_TAMP_7 TAMP_IER_TAMP7IE /*!< Tamper 7 Interrupt */
|
||||
#define RTC_IT_TAMP_8 TAMP_IER_TAMP8IE /*!< Tamper 8 Interrupt */
|
||||
#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 |\
|
||||
RTC_IT_TAMP_3 | RTC_IT_TAMP_4 |\
|
||||
RTC_IT_TAMP_5 | RTC_IT_TAMP_6 |\
|
||||
RTC_IT_TAMP_7 | RTC_IT_TAMP_8 )
|
||||
#else
|
||||
#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2)
|
||||
#endif /* RTC_TAMP_NB */
|
||||
|
||||
#if defined (RTC_TAMP_INT_1_SUPPORT)
|
||||
#define RTC_IT_INT_TAMP_1 TAMP_IER_ITAMP1IE /*!< Tamper 1 internal Interrupt */
|
||||
#else
|
||||
#define RTC_IT_INT_TAMP_1 0U
|
||||
#endif /* RTC_TAMP_INT_1_SUPPORT */
|
||||
#if defined (RTC_TAMP_INT_2_SUPPORT)
|
||||
#define RTC_IT_INT_TAMP_2 TAMP_IER_ITAMP2IE /*!< Tamper 2 internal Interrupt */
|
||||
#else
|
||||
#define RTC_IT_INT_TAMP_2 0U
|
||||
#endif /* RTC_TAMP_INT_2_SUPPORT */
|
||||
#define RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE /*!< Tamper 3 internal Interrupt */
|
||||
#define RTC_IT_INT_TAMP_4 TAMP_IER_ITAMP4IE /*!< Tamper 4 internal Interrupt */
|
||||
#define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE /*!< Tamper 5 internal Interrupt */
|
||||
#if defined (RTC_TAMP_INT_6_SUPPORT)
|
||||
#define RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE /*!< Tamper 6 internal Interrupt */
|
||||
#else
|
||||
#define RTC_IT_INT_TAMP_6 0U
|
||||
#endif /* RTC_TAMP_INT_6_SUPPORT */
|
||||
#if defined (RTC_TAMP_INT_7_SUPPORT)
|
||||
#define RTC_IT_INT_TAMP_7 TAMP_IER_ITAMP7IE /*!< Tamper 7 internal Interrupt */
|
||||
#else
|
||||
#define RTC_IT_INT_TAMP_7 0U
|
||||
#endif /* RTC_TAMP_INT_7_SUPPORT */
|
||||
#if defined (RTC_TAMP_INT_8_SUPPORT)
|
||||
#define RTC_IT_INT_TAMP_8 TAMP_IER_ITAMP8IE /*!< Tamper 8 internal Interrupt */
|
||||
#else
|
||||
#define RTC_IT_INT_TAMP_8 0U
|
||||
#endif /* RTC_TAMP_INT_8_SUPPORT */
|
||||
|
||||
#define RTC_IT_INT_TAMP_ALL (RTC_IT_INT_TAMP_1 | RTC_IT_INT_TAMP_2 |\
|
||||
RTC_IT_INT_TAMP_3 | RTC_IT_INT_TAMP_4 |\
|
||||
RTC_IT_INT_TAMP_5 | RTC_IT_INT_TAMP_6 |\
|
||||
RTC_IT_INT_TAMP_7 | RTC_IT_INT_TAMP_8 )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Flags RTCEx Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F
|
||||
#define RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F
|
||||
#if (RTC_TAMP_NB == 3)
|
||||
#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F
|
||||
#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3)
|
||||
#elif (RTC_TAMP_NB == 8)
|
||||
#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F
|
||||
#define RTC_FLAG_TAMP_4 TAMP_SR_TAMP4F
|
||||
#define RTC_FLAG_TAMP_5 TAMP_SR_TAMP5F
|
||||
#define RTC_FLAG_TAMP_6 TAMP_SR_TAMP6F
|
||||
#define RTC_FLAG_TAMP_7 TAMP_SR_TAMP7F
|
||||
#define RTC_FLAG_TAMP_8 TAMP_SR_TAMP8F
|
||||
#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\
|
||||
RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 |\
|
||||
RTC_FLAG_TAMP_6 | RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8)
|
||||
|
||||
#else
|
||||
#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2)
|
||||
#endif /* RTC_TAMP_NB */
|
||||
|
||||
#if defined (RTC_TAMP_INT_1_SUPPORT)
|
||||
#define RTC_FLAG_INT_TAMP_1 TAMP_SR_ITAMP1F /*!< Tamper 1 Interrupt flag */
|
||||
#else
|
||||
#define RTC_FLAG_INT_TAMP_1 0U
|
||||
#endif /* RTC_TAMP_INT_1_SUPPORT */
|
||||
#if defined (RTC_TAMP_INT_2_SUPPORT)
|
||||
#define RTC_FLAG_INT_TAMP_2 TAMP_SR_ITAMP2F /*!< Tamper 2 Interrupt flag */
|
||||
#else
|
||||
#define RTC_FLAG_INT_TAMP_2 0U
|
||||
#endif /* RTC_TAMP_INT_2_SUPPORT */
|
||||
#define RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F /*!< Tamper 3 Interrupt flag */
|
||||
#define RTC_FLAG_INT_TAMP_4 TAMP_SR_ITAMP4F /*!< Tamper 4 Interrupt flag */
|
||||
#define RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F /*!< Tamper 5 Interrupt flag */
|
||||
#if defined (RTC_TAMP_INT_6_SUPPORT)
|
||||
#define RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F /*!< Tamper 6 Interrupt flag */
|
||||
#else
|
||||
#define RTC_FLAG_INT_TAMP_6 0U
|
||||
#endif /* RTC_TAMP_INT_6_SUPPORT */
|
||||
#if defined (RTC_TAMP_INT_7_SUPPORT)
|
||||
#define RTC_FLAG_INT_TAMP_7 TAMP_SR_ITAMP7F /*!< Tamper 7 Interrupt flag */
|
||||
#else
|
||||
#define RTC_FLAG_INT_TAMP_7 0U
|
||||
#endif /* RTC_TAMP_INT_7_SUPPORT */
|
||||
#if defined (RTC_TAMP_INT_8_SUPPORT)
|
||||
#define RTC_FLAG_INT_TAMP_8 TAMP_SR_ITAMP8F /*!< Tamper 8 Interrupt flag */
|
||||
#else
|
||||
#define RTC_FLAG_INT_TAMP_8 0U
|
||||
#endif /* RTC_TAMP_INT_8_SUPPORT */
|
||||
#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP_1 | RTC_FLAG_INT_TAMP_2 |\
|
||||
RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP_4 |\
|
||||
RTC_FLAG_INT_TAMP_5 | RTC_FLAG_INT_TAMP_6 |\
|
||||
RTC_FLAG_INT_TAMP_7 | RTC_FLAG_INT_TAMP_8)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition
|
||||
* @{
|
||||
*/
|
||||
#define RTC_BKP_NUMBER RTC_BACKUP_NB
|
||||
#if (RTC_BACKUP_NB == 5)
|
||||
#define RTC_BKP_DR0 0x00000000U
|
||||
#define RTC_BKP_DR1 0x00000001U
|
||||
#define RTC_BKP_DR2 0x00000002U
|
||||
#define RTC_BKP_DR3 0x00000003U
|
||||
#define RTC_BKP_DR4 0x00000004U
|
||||
#elif (RTC_BACKUP_NB == 16)
|
||||
#define RTC_BKP_DR0 0x00U
|
||||
#define RTC_BKP_DR1 0x01U
|
||||
#define RTC_BKP_DR2 0x02U
|
||||
#define RTC_BKP_DR3 0x03U
|
||||
#define RTC_BKP_DR4 0x04U
|
||||
#define RTC_BKP_DR5 0x05U
|
||||
#define RTC_BKP_DR6 0x06U
|
||||
#define RTC_BKP_DR7 0x07U
|
||||
#define RTC_BKP_DR8 0x08U
|
||||
#define RTC_BKP_DR9 0x09U
|
||||
#define RTC_BKP_DR10 0x0AU
|
||||
#define RTC_BKP_DR11 0x0BU
|
||||
#define RTC_BKP_DR12 0x0CU
|
||||
#define RTC_BKP_DR13 0x0DU
|
||||
#define RTC_BKP_DR14 0x0EU
|
||||
#define RTC_BKP_DR15 0x0FU
|
||||
#elif (RTC_BACKUP_NB == 32)
|
||||
#define RTC_BKP_DR0 0x00U
|
||||
#define RTC_BKP_DR1 0x01U
|
||||
#define RTC_BKP_DR2 0x02U
|
||||
#define RTC_BKP_DR3 0x03U
|
||||
#define RTC_BKP_DR4 0x04U
|
||||
#define RTC_BKP_DR5 0x05U
|
||||
#define RTC_BKP_DR6 0x06U
|
||||
#define RTC_BKP_DR7 0x07U
|
||||
#define RTC_BKP_DR8 0x08U
|
||||
#define RTC_BKP_DR9 0x09U
|
||||
#define RTC_BKP_DR10 0x0AU
|
||||
#define RTC_BKP_DR11 0x0BU
|
||||
#define RTC_BKP_DR12 0x0CU
|
||||
#define RTC_BKP_DR13 0x0DU
|
||||
#define RTC_BKP_DR14 0x0EU
|
||||
#define RTC_BKP_DR15 0x0FU
|
||||
#define RTC_BKP_DR16 0x10U
|
||||
#define RTC_BKP_DR17 0x11U
|
||||
#define RTC_BKP_DR18 0x12U
|
||||
#define RTC_BKP_DR19 0x13U
|
||||
#define RTC_BKP_DR20 0x14U
|
||||
#define RTC_BKP_DR21 0x15U
|
||||
#define RTC_BKP_DR22 0x16U
|
||||
#define RTC_BKP_DR23 0x17U
|
||||
#define RTC_BKP_DR24 0x18U
|
||||
#define RTC_BKP_DR25 0x19U
|
||||
#define RTC_BKP_DR26 0x1AU
|
||||
#define RTC_BKP_DR27 0x1BU
|
||||
#define RTC_BKP_DR28 0x1CU
|
||||
#define RTC_BKP_DR29 0x1DU
|
||||
#define RTC_BKP_DR30 0x1EU
|
||||
#define RTC_BKP_DR31 0x1FU
|
||||
#else
|
||||
#error "no RTC Backup Registers Definition"
|
||||
#endif /* RTC_BKP_NUMBER */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Clear the specified RTC pending flag.
|
||||
* @param __HANDLE__ specifies the RTC Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RTC_CLEAR_ITSF Clear Internal Time-stamp flag
|
||||
* @arg @ref RTC_CLEAR_TSOVF Clear Time-stamp overflow flag
|
||||
* @arg @ref RTC_CLEAR_TSF Clear Time-stamp flag
|
||||
* @arg @ref RTC_CLEAR_WUTF Clear Wakeup timer flag
|
||||
* @arg @ref RTC_CLEAR_ALRBF Clear Alarm B flag
|
||||
* @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR = (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Check whether the specified RTC flag is set or not.
|
||||
* @param __HANDLE__ specifies the RTC Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref RTC_FLAG_RECALPF Recalibration pending Flag
|
||||
* @arg @ref RTC_FLAG_INITF Initialization flag
|
||||
* @arg @ref RTC_FLAG_RSF Registers synchronization flag
|
||||
* @arg @ref RTC_FLAG_INITS Initialization status flag
|
||||
* @arg @ref RTC_FLAG_SHPF Shift operation pending flag
|
||||
* @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag
|
||||
* @arg @ref RTC_FLAG_ALRBWF Alarm B write flag
|
||||
* @arg @ref RTC_FLAG_ALRAWF Alarm A write flag
|
||||
* @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag
|
||||
* @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag
|
||||
* @arg @ref RTC_FLAG_TSF Time-stamp flag
|
||||
* @arg @ref RTC_FLAG_WUTF Wakeup timer flag
|
||||
* @arg @ref RTC_FLAG_ALRBF Alarm B flag
|
||||
* @arg @ref RTC_FLAG_ALRAF Alarm A flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \
|
||||
((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))
|
||||
|
||||
/* ---------------------------------WAKEUPTIMER---------------------------------*/
|
||||
/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the RTC WakeUp Timer peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC WakeUp Timer peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC WakeUpTimer interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC WakeUpTimer interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)\
|
||||
& ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL)
|
||||
/**
|
||||
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR)\
|
||||
& (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC WakeUpTimers flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_WUTF
|
||||
* @arg @ref RTC_FLAG_WUTWF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Wake Up timers pending flags.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_WUTF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
|
||||
|
||||
/* WAKE-UP TIMER EXTI */
|
||||
/* ------------------ */
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* ---------------------------------TIMESTAMP---------------------------------*/
|
||||
/** @defgroup RTCEx_Timestamp RTC Timestamp
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the RTC TimeStamp peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC TimeStamp peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC TimeStamp interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_TS TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC TimeStamp interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_TS TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_TS TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)\
|
||||
& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
|
||||
/**
|
||||
* @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_IT_TS TimeStamp interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR)\
|
||||
& (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC TimeStamps flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_TSF
|
||||
* @arg @ref RTC_FLAG_TSOVF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Time Stamps pending flags.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC TimeStamp Flag to clear.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_TSF
|
||||
* @arg @ref RTC_FLAG_TSOVF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
|
||||
|
||||
/* TIMESTAMP TIMER EXTI */
|
||||
/* -------------------- */
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Timestamp associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Timestamp associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
|
||||
|
||||
/**
|
||||
* @brief set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the interrupt on the RTC Timestamp associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Timestamp associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Timestamp associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC internal TimeStamp peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC internal TimeStamp peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Internal Time Stamps flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_ITSF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Internal Time Stamps pending flags.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_ITSF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC TimeStamp on Tamper detection.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC TimeStamp on Tamper detection.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Tamper detection output.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Tamper detection output.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* ------------------------------Calibration----------------------------------*/
|
||||
/** @defgroup RTCEx_Calibration RTC Calibration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC calibration output.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
|
||||
|
||||
/**
|
||||
* @brief Disable the calibration output.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the clock reference detection.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
|
||||
|
||||
/**
|
||||
* @brief Disable the clock reference detection.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC shift operations flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
|
||||
* This parameter can be:
|
||||
* @arg @ref RTC_FLAG_SHPF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* ------------------------------Tamper----------------------------------*/
|
||||
/** @defgroup RTCEx_Tamper RTCEx tamper
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the TAMP Tamper input detection.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __TAMPER__ specifies the RTC Tamper source to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_TAMPER_ALL: All tampers
|
||||
* @arg RTC_TAMPER_1: Tamper1
|
||||
* @arg RTC_TAMPER_2: Tamper2
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__))
|
||||
|
||||
/**
|
||||
* @brief Disable the TAMP Tamper input detection.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __TAMPER__ specifies the RTC Tamper sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_TAMPER_ALL: All tampers
|
||||
* @arg RTC_TAMPER_1: Tamper1
|
||||
* @arg RTC_TAMPER_2: Tamper2
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__))
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
* @brief Enable the TAMP Tamper interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_TAMP_ALL: All tampers interrupts
|
||||
* @arg RTC_IT_TAMP_1: Tamper1 interrupt
|
||||
* @arg RTC_IT_TAMP_2: Tamper2 interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the TAMP Tamper interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_TAMP_ALL: All tampers interrupts
|
||||
* @arg RTC_IT_TAMP_1: Tamper1 interrupt
|
||||
* @arg RTC_IT_TAMP_2: Tamper2 interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__))
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
* @brief Check whether the specified TAMP Tamper interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TAMP_ALL: All tampers interrupts
|
||||
* @arg RTC_IT_TAMP_1: Tamper1 interrupt
|
||||
* @arg RTC_IT_TAMP_2: Tamper2 interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((TAMP->MISR)\
|
||||
& (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified TAMP Tamper interrupt has been enabled or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_TAMP_ALL: All tampers interrupts
|
||||
* @arg RTC_IT_TAMP_1: Tamper1 interrupt
|
||||
* @arg RTC_IT_TAMP_2: Tamper2 interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((TAMP->IER)\
|
||||
& (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the selected TAMP Tampers flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TAMP_ALL: All tampers flag
|
||||
* @arg RTC_FLAG_TAMP_1: Tamper1 flag
|
||||
* @arg RTC_FLAG_TAMP_2: Tamper2 flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0UL)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear the TAMP Tampers pending flags.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Tamper Flag to clear.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_TAMP_ALL: All tampers flag
|
||||
* @arg RTC_FLAG_TAMP_1: Tamper1 flag
|
||||
* @arg RTC_FLAG_TAMP_2: Tamper2 flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((TAMP->SCR) = (__FLAG__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Tamper associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Tamper associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear the interrupt on the RTC WakeUp Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_EVENT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Tamper associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Tamper associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* RTC TimeStamp functions *****************************************/
|
||||
/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
|
||||
RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
|
||||
void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* RTC Wake-up functions ******************************************************/
|
||||
/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
|
||||
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Extended Control functions ************************************************/
|
||||
/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod,
|
||||
uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Extended RTC features functions *******************************************/
|
||||
/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper);
|
||||
HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout);
|
||||
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
#if (RTC_TAMP_NB == 3)
|
||||
void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
#endif /* RTC_TAMP_NB */
|
||||
|
||||
#ifdef RTC_TAMP_INT_1_SUPPORT
|
||||
void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
#endif /* RTC_TAMP_INT_1_SUPPORT */
|
||||
#ifdef RTC_TAMP_INT_2_SUPPORT
|
||||
void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
#endif /* RTC_TAMP_INT_2_SUPPORT */
|
||||
void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
#ifdef RTC_TAMP_INT_6_SUPPORT
|
||||
void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
#endif /* RTC_TAMP_INT_6_SUPPORT */
|
||||
#ifdef RTC_TAMP_INT_7_SUPPORT
|
||||
void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc);
|
||||
#endif /* RTC_TAMP_INT_7_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
|
||||
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC tamper/Time Stamp/CSS_LSE events */
|
||||
#define RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC tamper/Time Stamp/CSS_LSE events */
|
||||
#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
|
||||
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
|
||||
|
||||
|
||||
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
|
||||
|
||||
|
||||
|
||||
#define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
|
||||
((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
|
||||
|
||||
#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE) (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
|
||||
((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))
|
||||
|
||||
|
||||
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
|
||||
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
|
||||
|
||||
#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
|
||||
|
||||
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
|
||||
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
|
||||
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
|
||||
|
||||
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
|
||||
((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
|
||||
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
|
||||
|
||||
#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \
|
||||
((LPCAL) == RTC_LPCAL_RESET))
|
||||
|
||||
#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
|
||||
(((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))
|
||||
|
||||
#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \
|
||||
(((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))
|
||||
|
||||
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
|
||||
((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
|
||||
((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
|
||||
((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
|
||||
|
||||
#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
|
||||
((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
|
||||
|
||||
#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
|
||||
((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
|
||||
|
||||
#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \
|
||||
((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
|
||||
((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
|
||||
((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
|
||||
|
||||
#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
|
||||
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
|
||||
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
|
||||
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
|
||||
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
|
||||
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
|
||||
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
|
||||
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
|
||||
|
||||
#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
|
||||
((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
|
||||
((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
|
||||
((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
|
||||
|
||||
#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
|
||||
((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
|
||||
|
||||
#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
|
||||
((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
|
||||
|
||||
#define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER)
|
||||
|
||||
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
|
||||
((SEL) == RTC_SHIFTADD1S_SET))
|
||||
|
||||
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
|
||||
|
||||
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
|
||||
((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_RTC_EX_H */
|
||||
959
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h
Normal file
959
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h
Normal file
@@ -0,0 +1,959 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_sai.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SAI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_SAI_H
|
||||
#define STM32G4xx_HAL_SAI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(SAI1)
|
||||
|
||||
/** @addtogroup SAI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SAI_Exported_Types SAI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */
|
||||
HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */
|
||||
HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
|
||||
HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
|
||||
HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
|
||||
} HAL_SAI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SAI Callback prototype
|
||||
*/
|
||||
typedef void (*SAIcallback)(void);
|
||||
|
||||
/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
|
||||
* @brief SAI PDM Init structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState Activation; /*!< Enable/disable PDM interface */
|
||||
uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
|
||||
uint32_t ClockEnable; /*!< Specifies which clock must be enabled.
|
||||
This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
|
||||
} SAI_PdmInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
|
||||
* @brief SAI Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
|
||||
This parameter can be a value of @ref SAI_Block_Mode */
|
||||
|
||||
uint32_t Synchro; /*!< Specifies SAI Block synchronization
|
||||
This parameter can be a value of @ref SAI_Block_Synchronization */
|
||||
|
||||
uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
|
||||
for BlockA and BlockB
|
||||
This parameter can be a value of @ref SAI_Block_SyncExt
|
||||
@note If both audio blocks of same SAI are used, this parameter has
|
||||
to be set to the same value for each audio block */
|
||||
|
||||
uint32_t MckOutput; /*!< Specifies whether master clock output will be generated or not.
|
||||
This parameter can be a value of @ref SAI_Block_MckOutput */
|
||||
|
||||
uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
|
||||
This parameter can be a value of @ref SAI_Block_Output_Drive
|
||||
@note This value has to be set before enabling the audio block
|
||||
but after the audio block configuration. */
|
||||
|
||||
uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
|
||||
This parameter can be a value of @ref SAI_Block_NoDivider
|
||||
@note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
|
||||
should be aligned to a number equal to a power of 2, from 8 to 256.
|
||||
If bit NODIV in the SAI_xCR1 register is set, the frame length can
|
||||
take any of the values from 8 to 256. */
|
||||
|
||||
uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
|
||||
This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
|
||||
|
||||
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
|
||||
This parameter can be a value of @ref SAI_Audio_Frequency */
|
||||
|
||||
uint32_t Mckdiv; /*!< Specifies the master clock divider.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 63.
|
||||
@note This parameter is used only if AudioFrequency is set to
|
||||
SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
|
||||
|
||||
uint32_t MckOverSampling; /*!< Specifies the master clock oversampling.
|
||||
This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
|
||||
|
||||
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
|
||||
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
|
||||
|
||||
uint32_t CompandingMode; /*!< Specifies the companding mode type.
|
||||
This parameter can be a value of @ref SAI_Block_Companding_Mode */
|
||||
|
||||
uint32_t TriState; /*!< Specifies the companding mode type.
|
||||
This parameter can be a value of @ref SAI_TRIState_Management */
|
||||
|
||||
SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */
|
||||
|
||||
/* This part of the structure is automatically filled if your are using the high level initialisation
|
||||
function HAL_SAI_InitProtocol */
|
||||
|
||||
uint32_t Protocol; /*!< Specifies the SAI Block protocol.
|
||||
This parameter can be a value of @ref SAI_Block_Protocol */
|
||||
|
||||
uint32_t DataSize; /*!< Specifies the SAI Block data size.
|
||||
This parameter can be a value of @ref SAI_Block_Data_Size */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
|
||||
|
||||
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
|
||||
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
|
||||
} SAI_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
|
||||
* @brief SAI Frame Init structure definition
|
||||
* @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
|
||||
This parameter must be a number between Min_Data = 8 and Max_Data = 256.
|
||||
@note If master clock MCLK_x pin is declared as an output, the frame length
|
||||
should be aligned to a number equal to power of 2 in order to keep
|
||||
in an audio frame, an integer number of MCLK pulses by bit Clock. */
|
||||
|
||||
uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
|
||||
This Parameter specifies the length in number of bit clock (SCK + 1)
|
||||
of the active level of FS signal in audio frame.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
|
||||
|
||||
uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Definition */
|
||||
|
||||
uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Polarity */
|
||||
|
||||
uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Offset */
|
||||
|
||||
} SAI_FrameInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
|
||||
* @brief SAI Block Slot Init Structure definition
|
||||
* @note For SPDIF protocol, these parameters are not used (set by hardware).
|
||||
* @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
|
||||
|
||||
uint32_t SlotSize; /*!< Specifies the Slot Size.
|
||||
This parameter can be a value of @ref SAI_Block_Slot_Size */
|
||||
|
||||
uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
|
||||
|
||||
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
|
||||
This parameter can be a value of @ref SAI_Block_Slot_Active */
|
||||
} SAI_SlotInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
|
||||
* @brief SAI handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __SAI_HandleTypeDef
|
||||
{
|
||||
SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
|
||||
|
||||
SAI_InitTypeDef Init; /*!< SAI communication parameters */
|
||||
|
||||
SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
|
||||
|
||||
SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
|
||||
|
||||
uint16_t XferSize; /*!< SAI transfer size */
|
||||
|
||||
uint16_t XferCount; /*!< SAI transfer counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
|
||||
|
||||
SAIcallback mutecallback; /*!< SAI mute callback */
|
||||
|
||||
void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SAI locking object */
|
||||
|
||||
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SAI Error code */
|
||||
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */
|
||||
void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */
|
||||
void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */
|
||||
void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */
|
||||
void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */
|
||||
void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */
|
||||
void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */
|
||||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
|
||||
} SAI_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief SAI callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */
|
||||
HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
|
||||
HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */
|
||||
HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
|
||||
HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */
|
||||
HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */
|
||||
HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */
|
||||
} HAL_SAI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SAI callback pointer definition
|
||||
*/
|
||||
typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
|
||||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SAI_Exported_Constants SAI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Error_Code SAI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */
|
||||
#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */
|
||||
#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */
|
||||
#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */
|
||||
#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */
|
||||
#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */
|
||||
#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */
|
||||
#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_SyncExt SAI External synchronisation
|
||||
* @{
|
||||
*/
|
||||
#define SAI_SYNCEXT_DISABLE 0U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MCK_OUTPUT_DISABLE 0x00000000U
|
||||
#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Protocol SAI Supported protocol
|
||||
* @{
|
||||
*/
|
||||
#define SAI_I2S_STANDARD 0U
|
||||
#define SAI_I2S_MSBJUSTIFIED 1U
|
||||
#define SAI_I2S_LSBJUSTIFIED 2U
|
||||
#define SAI_PCM_LONG 3U
|
||||
#define SAI_PCM_SHORT 4U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Protocol_DataSize SAI protocol data size
|
||||
* @{
|
||||
*/
|
||||
#define SAI_PROTOCOL_DATASIZE_16BIT 0U
|
||||
#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
|
||||
#define SAI_PROTOCOL_DATASIZE_24BIT 2U
|
||||
#define SAI_PROTOCOL_DATASIZE_32BIT 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define SAI_AUDIO_FREQUENCY_192K 192000U
|
||||
#define SAI_AUDIO_FREQUENCY_96K 96000U
|
||||
#define SAI_AUDIO_FREQUENCY_48K 48000U
|
||||
#define SAI_AUDIO_FREQUENCY_44K 44100U
|
||||
#define SAI_AUDIO_FREQUENCY_32K 32000U
|
||||
#define SAI_AUDIO_FREQUENCY_22K 22050U
|
||||
#define SAI_AUDIO_FREQUENCY_16K 16000U
|
||||
#define SAI_AUDIO_FREQUENCY_11K 11025U
|
||||
#define SAI_AUDIO_FREQUENCY_8K 8000U
|
||||
#define SAI_AUDIO_FREQUENCY_MCKDIV 0U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
|
||||
#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
|
||||
* @{
|
||||
*/
|
||||
#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
|
||||
#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Mode SAI Block Mode
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MODEMASTER_TX 0x00000000U
|
||||
#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0
|
||||
#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1
|
||||
#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Protocol SAI Block Protocol
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FREE_PROTOCOL 0x00000000U
|
||||
#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
|
||||
#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Data_Size SAI Block Data Size
|
||||
* @{
|
||||
*/
|
||||
#define SAI_DATASIZE_8 SAI_xCR1_DS_1
|
||||
#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
|
||||
#define SAI_DATASIZE_16 SAI_xCR1_DS_2
|
||||
#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
|
||||
#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
|
||||
#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FIRSTBIT_MSB 0x00000000U
|
||||
#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
|
||||
* @{
|
||||
*/
|
||||
#define SAI_CLOCKSTROBING_FALLINGEDGE 0U
|
||||
#define SAI_CLOCKSTROBING_RISINGEDGE 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
|
||||
* @{
|
||||
*/
|
||||
#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */
|
||||
#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
|
||||
* @{
|
||||
*/
|
||||
#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U
|
||||
#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MASTERDIVIDER_ENABLE 0x00000000U
|
||||
#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FS_STARTFRAME 0x00000000U
|
||||
#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FS_ACTIVE_LOW 0x00000000U
|
||||
#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FS_FIRSTBIT 0x00000000U
|
||||
#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
|
||||
* @{
|
||||
*/
|
||||
#define SAI_SLOTSIZE_DATASIZE 0x00000000U
|
||||
#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
|
||||
#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
|
||||
* @{
|
||||
*/
|
||||
#define SAI_SLOT_NOTACTIVE 0x00000000U
|
||||
#define SAI_SLOTACTIVE_0 0x00000001U
|
||||
#define SAI_SLOTACTIVE_1 0x00000002U
|
||||
#define SAI_SLOTACTIVE_2 0x00000004U
|
||||
#define SAI_SLOTACTIVE_3 0x00000008U
|
||||
#define SAI_SLOTACTIVE_4 0x00000010U
|
||||
#define SAI_SLOTACTIVE_5 0x00000020U
|
||||
#define SAI_SLOTACTIVE_6 0x00000040U
|
||||
#define SAI_SLOTACTIVE_7 0x00000080U
|
||||
#define SAI_SLOTACTIVE_8 0x00000100U
|
||||
#define SAI_SLOTACTIVE_9 0x00000200U
|
||||
#define SAI_SLOTACTIVE_10 0x00000400U
|
||||
#define SAI_SLOTACTIVE_11 0x00000800U
|
||||
#define SAI_SLOTACTIVE_12 0x00001000U
|
||||
#define SAI_SLOTACTIVE_13 0x00002000U
|
||||
#define SAI_SLOTACTIVE_14 0x00004000U
|
||||
#define SAI_SLOTACTIVE_15 0x00008000U
|
||||
#define SAI_SLOTACTIVE_ALL 0x0000FFFFU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
|
||||
* @{
|
||||
*/
|
||||
#define SAI_STEREOMODE 0x00000000U
|
||||
#define SAI_MONOMODE SAI_xCR1_MONO
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_TRIState_Management SAI TRIState Management
|
||||
* @{
|
||||
*/
|
||||
#define SAI_OUTPUT_NOTRELEASED 0x00000000U
|
||||
#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
|
||||
#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
|
||||
#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
|
||||
#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
|
||||
#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
|
||||
* @{
|
||||
*/
|
||||
#define SAI_NOCOMPANDING 0x00000000U
|
||||
#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
|
||||
#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
|
||||
#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
|
||||
#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
|
||||
* @{
|
||||
*/
|
||||
#define SAI_ZERO_VALUE 0x00000000U
|
||||
#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
|
||||
#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
|
||||
#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
|
||||
#define SAI_IT_FREQ SAI_xIMR_FREQIE
|
||||
#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE
|
||||
#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE
|
||||
#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
|
||||
#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
|
||||
#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
|
||||
#define SAI_FLAG_FREQ SAI_xSR_FREQ
|
||||
#define SAI_FLAG_CNRDY SAI_xSR_CNRDY
|
||||
#define SAI_FLAG_AFSDET SAI_xSR_AFSDET
|
||||
#define SAI_FLAG_LFSDET SAI_xSR_LFSDET
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FIFOSTATUS_EMPTY 0x00000000U
|
||||
#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
|
||||
#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
|
||||
#define SAI_FIFOSTATUS_HALFFULL 0x00030000U
|
||||
#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
|
||||
#define SAI_FIFOSTATUS_FULL 0x00050000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SAI_Exported_Macros SAI Exported Macros
|
||||
* @brief macros to handle interrupts and specific configurations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SAI handle state.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_SAI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
|
||||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified SAI interrupts.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
|
||||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
|
||||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
|
||||
* @arg SAI_IT_FREQ: FIFO request interrupt enable
|
||||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
|
||||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
|
||||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified SAI interrupts.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
|
||||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
|
||||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
|
||||
* @arg SAI_IT_FREQ: FIFO request interrupt enable
|
||||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
|
||||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
|
||||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified SAI interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __INTERRUPT__ specifies the SAI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
|
||||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
|
||||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
|
||||
* @arg SAI_IT_FREQ: FIFO request interrupt enable
|
||||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
|
||||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
|
||||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SAI flag is set or not.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
|
||||
* @arg SAI_FLAG_MUTEDET: Mute detection flag.
|
||||
* @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
|
||||
* @arg SAI_FLAG_FREQ: FIFO request flag.
|
||||
* @arg SAI_FLAG_CNRDY: Codec not ready flag.
|
||||
* @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
|
||||
* @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified SAI pending flag.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
|
||||
* @arg SAI_FLAG_MUTEDET: Clear Mute detection
|
||||
* @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
|
||||
* @arg SAI_FLAG_FREQ: Clear FIFO request
|
||||
* @arg SAI_FLAG_CNRDY: Clear Codec not ready
|
||||
* @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
|
||||
* @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
|
||||
|
||||
/** @brief Enable SAI.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
|
||||
|
||||
/** @brief Disable SAI.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include SAI HAL Extension module */
|
||||
#include "stm32g4xx_hal_sai_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SAI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup SAI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
|
||||
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
|
||||
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
/* SAI callbacks register/unregister functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
|
||||
HAL_SAI_CallbackIDTypeDef CallbackID,
|
||||
pSAI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
|
||||
HAL_SAI_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/** @addtogroup SAI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* Abort function */
|
||||
HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* Mute management */
|
||||
HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
|
||||
HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
|
||||
HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SAI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai);
|
||||
uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SAI_Private_Macros SAI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_SAI_BLOCK_SYNCEXT(STATE) ((STATE) == SAI_SYNCEXT_DISABLE)
|
||||
|
||||
#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
|
||||
((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
|
||||
((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
|
||||
((PROTOCOL) == SAI_PCM_LONG) ||\
|
||||
((PROTOCOL) == SAI_PCM_SHORT))
|
||||
|
||||
#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
|
||||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
|
||||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
|
||||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
|
||||
|
||||
#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
|
||||
|
||||
#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
|
||||
((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
|
||||
|
||||
#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
|
||||
|
||||
#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
|
||||
(((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
|
||||
|
||||
#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
|
||||
((MODE) == SAI_MODEMASTER_RX) || \
|
||||
((MODE) == SAI_MODESLAVE_TX) || \
|
||||
((MODE) == SAI_MODESLAVE_RX))
|
||||
|
||||
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
|
||||
((PROTOCOL) == SAI_AC97_PROTOCOL) || \
|
||||
((PROTOCOL) == SAI_SPDIF_PROTOCOL))
|
||||
|
||||
#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
|
||||
((DATASIZE) == SAI_DATASIZE_10) || \
|
||||
((DATASIZE) == SAI_DATASIZE_16) || \
|
||||
((DATASIZE) == SAI_DATASIZE_20) || \
|
||||
((DATASIZE) == SAI_DATASIZE_24) || \
|
||||
((DATASIZE) == SAI_DATASIZE_32))
|
||||
|
||||
#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
|
||||
((BIT) == SAI_FIRSTBIT_LSB))
|
||||
|
||||
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
|
||||
((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
|
||||
|
||||
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
|
||||
((SYNCHRO) == SAI_SYNCHRONOUS))
|
||||
|
||||
#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
|
||||
((VALUE) == SAI_MCK_OUTPUT_DISABLE))
|
||||
|
||||
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
|
||||
((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
|
||||
|
||||
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
|
||||
((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
|
||||
|
||||
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
|
||||
|
||||
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
|
||||
((VALUE) == SAI_LAST_SENT_VALUE))
|
||||
|
||||
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
|
||||
((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
|
||||
((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
|
||||
((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
|
||||
((MODE) == SAI_ALAW_2CPL_COMPANDING))
|
||||
|
||||
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
|
||||
|
||||
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
|
||||
((STATE) == SAI_OUTPUT_RELEASED))
|
||||
|
||||
#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
|
||||
((MODE) == SAI_STEREOMODE))
|
||||
|
||||
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
|
||||
|
||||
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
|
||||
|
||||
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
|
||||
((SIZE) == SAI_SLOTSIZE_16B) || \
|
||||
((SIZE) == SAI_SLOTSIZE_32B))
|
||||
|
||||
#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
|
||||
|
||||
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
|
||||
((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
|
||||
|
||||
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
|
||||
((POLARITY) == SAI_FS_ACTIVE_HIGH))
|
||||
|
||||
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
|
||||
((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
|
||||
|
||||
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
|
||||
|
||||
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
|
||||
|
||||
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SAI_Private_Functions SAI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* SAI1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_SAI_H */
|
||||
|
||||
108
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h
Normal file
108
Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h
Normal file
@@ -0,0 +1,108 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g4xx_hal_sai_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SAI HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32G4xx_HAL_SAI_EX_H
|
||||
#define STM32G4xx_HAL_SAI_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32g4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32G4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(SAI1)
|
||||
|
||||
/** @addtogroup SAIEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SAIEx_Exported_Types SAIEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PDM microphone delay structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t MicPair; /*!< Specifies which pair of microphones is selected.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
|
||||
|
||||
uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
|
||||
|
||||
uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
|
||||
} SAIEx_PdmMicDelayParamTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai,
|
||||
const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* SAI1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32G4xx_HAL_SAI_EX_H */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user