\doxysection{SEGGER\+\_\+\+RTT.\+h}
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\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00099}00099\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined(\_\_ARM\_ARCH\_8\_1M\_MAIN\_\_))\ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M85}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00100}00100\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00101}00101\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00102}00102\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00103}00103\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00104}00104\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 0}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00105}00105\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00106}00106\ \textcolor{preprocessor}{\ \ \#elif\ (defined\ \_\_ARMCC\_VERSION)}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00107}00107\ \ \ \ \ \textcolor{comment}{//}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00108}00108\ \ \ \ \ \textcolor{comment}{//\ ARM\ compiler}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00109}00109\ \ \ \ \ \textcolor{comment}{//\ ARM\ compiler\ V6.0\ and\ later\ is\ clang\ based.}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00110}00110\ \ \ \ \ \textcolor{comment}{//\ Our\ ASM\ part\ is\ compatible\ to\ clang.}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00111}00111\ \ \ \ \ \textcolor{comment}{//}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00112}00112\ \textcolor{preprocessor}{\ \ \ \ \#if\ (\_\_ARMCC\_VERSION\ >=\ 6000000)}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00113}00113\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CC\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00114}00114\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00115}00115\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CC\_HAS\_RTT\_ASM\_SUPPORT\ 0}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00116}00116\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00117}00117\ \textcolor{preprocessor}{\ \ \ \ \#if\ (defined\ \_\_ARM\_ARCH\_6M\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M0\ /\ M1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00118}00118\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 0\ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ No\ ASM\ support\ for\ this\ architecture}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00119}00119\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined\ \_\_ARM\_ARCH\_7M\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M3}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00120}00120\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00121}00121\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined\ \_\_ARM\_ARCH\_7EM\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M4/M7}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00122}00122\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00123}00123\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00124}00124\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00125}00125\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined\ \_\_ARM\_ARCH\_8M\_BASE\_\_)\ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M23}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00126}00126\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 0}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00127}00127\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00128}00128\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00129}00129\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined\ \_\_ARM\_ARCH\_8M\_MAIN\_\_)\ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M33}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00130}00130\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00131}00131\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00132}00132\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00133}00133\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined\ \_\_ARM\_ARCH\_8\_1M\_MAIN\_\_)\ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M85}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00134}00134\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00135}00135\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00136}00136\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00137}00137\ \textcolor{preprocessor}{\ \ \ \ \#elif\ ((defined\ \_\_ARM\_ARCH\_7A\_\_)\ ||\ (defined\ \_\_ARM\_ARCH\_7R\_\_))\ \ }\textcolor{comment}{//\ Cortex-\/A/R\ 32-\/bit\ ARMv7-\/A/R}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00138}00138\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00139}00139\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00140}00140\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00141}00141\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 0}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00142}00142\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00143}00143\ \textcolor{preprocessor}{\ \ \#elif\ ((defined\ \_\_GNUC\_\_)\ ||\ (defined\ \_\_clang\_\_))}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00144}00144\ \ \ \ \ \textcolor{comment}{//}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00145}00145\ \ \ \ \ \textcolor{comment}{//\ GCC\ /\ Clang}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00146}00146\ \ \ \ \ \textcolor{comment}{//}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00147}00147\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_CC\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00148}00148\ \ \ \ \ \textcolor{comment}{//\ ARM\ 7/9:\ \_\_ARM\_ARCH\_5\_\_\ /\ \_\_ARM\_ARCH\_5E\_\_\ /\ \_\_ARM\_ARCH\_5T\_\_\ /\ \_\_ARM\_ARCH\_5T\_\_\ /\ \_\_ARM\_ARCH\_5TE\_\_}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00149}00149\ \textcolor{preprocessor}{\ \ \ \ \#if\ (defined\ \_\_ARM\_ARCH\_7M\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M3}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00150}00150\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00151}00151\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined\ \_\_ARM\_ARCH\_7EM\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M4/M7}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00152}00152\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00153}00153\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1\ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Only\ Cortex-\/M7\ needs\ a\ DMB\ but\ we\ cannot\ distinguish\ M4\ and\ M7\ here...}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00154}00154\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00155}00155\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined\ \_\_ARM\_ARCH\_8M\_BASE\_\_)\ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M23}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00156}00156\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 0}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00157}00157\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00158}00158\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00159}00159\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined\ \_\_ARM\_ARCH\_8M\_MAIN\_\_)\ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M33}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00160}00160\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00161}00161\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00162}00162\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00163}00163\ \textcolor{preprocessor}{\ \ \ \ \#elif\ (defined\ \_\_ARM\_ARCH\_8\_1M\_MAIN\_\_)\ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M85}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00164}00164\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00165}00165\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00166}00166\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00167}00167\ \textcolor{preprocessor}{\ \ \ \ \#elif\ ((defined\ \_\_ARM\_ARCH\_7A\_\_)\ ||\ (defined\ \_\_ARM\_ARCH\_7R\_\_))\ \ }\textcolor{comment}{//\ Cortex-\/A/R\ 32-\/bit\ ARMv7-\/A/R}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00168}00168\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_NEEDS\_DMB\ \ \ \ \ \ \ \ \ \ \ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00169}00169\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ RTT\_\_DMB()\ \_\_asm\ volatile\ ("{}dmb\(\backslash\)n"{}\ :\ :\ :);}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00170}00170\ \textcolor{preprocessor}{\ \ \ \ \#else}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00171}00171\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 0}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00172}00172\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00173}00173\ \textcolor{preprocessor}{\ \ \#elif\ ((defined\ \_\_IASMARM\_\_)\ ||\ (defined\ \_\_ICCARM\_\_))}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00174}00174\ \ \ \ \ \textcolor{comment}{//}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00175}00175\ \ \ \ \ \textcolor{comment}{//\ IAR\ assembler/compiler}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00176}00176\ \ \ \ \ \textcolor{comment}{//}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00177}00177\ \textcolor{preprocessor}{\ \ \ \ \#define\ \_CC\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00178}00178\ \textcolor{preprocessor}{\ \ \ \ \#if\ (\_\_VER\_\_\ <\ 6300000)}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00179}00179\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ VOLATILE}}
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\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00181}00181\ \textcolor{preprocessor}{\ \ \ \ \ \ \#define\ VOLATILE\ volatile}}
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\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00183}00183\ \textcolor{preprocessor}{\ \ \ \ \#if\ (defined\ \_\_ARM7M\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Needed\ for\ old\ versions\ that\ do\ not\ know\ the\ define\ yet}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00184}00184\ \textcolor{preprocessor}{\ \ \ \ \ \ \#if\ (\_\_CORE\_\_\ ==\ \_\_ARM7M\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M3}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00185}00185\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 1}}
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\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00187}00187\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00188}00188\ \textcolor{preprocessor}{\ \ \ \ \#if\ (defined\ \_\_ARM7EM\_\_)}}
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\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00192}00192\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#define\ RTT\_\_DMB()\ asm\ VOLATILE\ ("{}DMB"{});}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00193}00193\ \textcolor{preprocessor}{\ \ \ \ \ \ \#endif}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00194}00194\ \textcolor{preprocessor}{\ \ \ \ \#endif}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00195}00195\ \textcolor{preprocessor}{\ \ \ \ \#if\ (defined\ \_\_ARM8M\_BASELINE\_\_)}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00196}00196\ \textcolor{preprocessor}{\ \ \ \ \ \ \#if\ (\_\_CORE\_\_\ ==\ \_\_ARM8M\_BASELINE\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{comment}{//\ Cortex-\/M23}}
\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00197}00197\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#define\ \_CORE\_HAS\_RTT\_ASM\_SUPPORT\ 0}}
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\DoxyCodeLine{\Hypertarget{_s_e_g_g_e_r___r_t_t_8h_source_l00199}00199\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \#define\ RTT\_\_DMB()\ asm\ VOLATILE\ ("{}DMB"{});}}
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