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compare: Razvalyaev:eaddf277ead76be21fab3de132aeea7308a8df55
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61d3aeaba6 ... eaddf277ea

Author SHA1 Message Date
Razvalyaev
eaddf277ea +gerber и чпу 2026-08-09 15:28:44 +03:00
Razvalyaev
706ae4de82 плата сделана и под аналог и под цифру 2026-08-09 13:57:26 +03:00
Razvalyaev
cec997d1d2 Перепиновка под будущий аналог 
+скрипт для конвертации падов под CNC
 2026-08-09 10:19:12 +03:00
36 changed files with 8442 additions and 7 deletions
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7
.gitignore vendored
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@@ -1,7 +1,6 @@
/tests/
/PCB/Project Logs*/
/*/__Previews
/*/History
/*/Project Logs*/
__Previews/
History
Project Logs*/

BIN
PCB/Libs/BPW34.PcbLib Normal file
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2544
PCB/Libs/BPW34_VERTICAL_P5.08mm.step Normal file
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@@ -0,0 +1,2544 @@
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#2131 = MECHANICAL_DESIGN_GEOMETRIC_PRESENTATION_REPRESENTATION('',(
#2132),#1413);
#2132 = STYLED_ITEM('color',(#2133),#747);
#2133 = PRESENTATION_STYLE_ASSIGNMENT((#2134));
#2134 = SURFACE_STYLE_USAGE(.BOTH.,#2135);
#2135 = SURFACE_SIDE_STYLE('',(#2136,#2140));
#2136 = SURFACE_STYLE_FILL_AREA(#2137);
#2137 = FILL_AREA_STYLE('',(#2138));
#2138 = FILL_AREA_STYLE_COLOUR('',#2139);
#2139 = COLOUR_RGB('',0.720000003324,0.78000000177,0.800000010877);
#2140 = SURFACE_STYLE_RENDERING_WITH_PROPERTIES(.NORMAL_SHADING.,#2139,(
#2141));
#2141 = SURFACE_STYLE_TRANSPARENT(0.420000016689);
#2142 = MECHANICAL_DESIGN_GEOMETRIC_PRESENTATION_REPRESENTATION('',(
#2143),#728);
#2143 = STYLED_ITEM('color',(#2144),#398);
#2144 = PRESENTATION_STYLE_ASSIGNMENT((#2145));
#2145 = SURFACE_STYLE_USAGE(.BOTH.,#2146);
#2146 = SURFACE_SIDE_STYLE('',(#2147));
#2147 = SURFACE_STYLE_FILL_AREA(#2148);
#2148 = FILL_AREA_STYLE('',(#2149));
#2149 = FILL_AREA_STYLE_COLOUR('',#2150);
#2150 = COLOUR_RGB('',0.720000003324,0.740000011925,0.760000013601);
#2151 = MECHANICAL_DESIGN_GEOMETRIC_PRESENTATION_REPRESENTATION('',(
#2152),#1762);
#2152 = STYLED_ITEM('color',(#2153),#1432);
#2153 = PRESENTATION_STYLE_ASSIGNMENT((#2154));
#2154 = SURFACE_STYLE_USAGE(.BOTH.,#2155);
#2155 = SURFACE_SIDE_STYLE('',(#2156));
#2156 = SURFACE_STYLE_FILL_AREA(#2157);
#2157 = FILL_AREA_STYLE('',(#2158));
#2158 = FILL_AREA_STYLE_COLOUR('',#2159);
#2159 = COLOUR_RGB('',9.999999991362E-02,0.1599999992,0.190000001765);
#2160 = MECHANICAL_DESIGN_GEOMETRIC_PRESENTATION_REPRESENTATION('',(
#2161),#379);
#2161 = STYLED_ITEM('color',(#2162),#49);
#2162 = PRESENTATION_STYLE_ASSIGNMENT((#2163));
#2163 = SURFACE_STYLE_USAGE(.BOTH.,#2164);
#2164 = SURFACE_SIDE_STYLE('',(#2165));
#2165 = SURFACE_STYLE_FILL_AREA(#2166);
#2166 = FILL_AREA_STYLE('',(#2167));
#2167 = FILL_AREA_STYLE_COLOUR('',#2150);
ENDSEC;
END-ISO-10303-21;

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PCB/Libs/J_ARK3_2.54.PcbLib Normal file
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130
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"""Generate the custom STEP models used by the OptoTest PCB libraries.
The coordinate system follows Altium's usual convention: XY is the PCB plane and
Z points away from the top side of the PCB. All dimensions are in millimetres.
"""
from pathlib import Path
import sys
CADQUERY_PATH = Path.home() / "AppData/Local/Temp/codex-cadquery"
if CADQUERY_PATH.exists():
sys.path.insert(0, str(CADQUERY_PATH))
import cadquery as cq
OUT_DIR = Path(__file__).resolve().parent
def box(x, y, z, cx=0.0, cy=0.0, bottom=0.0):
return cq.Workplane("XY").box(x, y, z).translate((cx, cy, bottom + z / 2))
def cylinder(diameter, height, cx=0.0, cy=0.0, bottom=0.0):
return (
cq.Workplane("XY")
.circle(diameter / 2)
.extrude(height)
.translate((cx, cy, bottom))
)
def add_dip8_precision_socket(assembly):
"""7.62-mm-row precision/turned-pin DIP-8 socket seated on the PCB."""
black = cq.Color(0.055, 0.055, 0.060)
gold = cq.Color(0.78, 0.55, 0.12)
dark = cq.Color(0.015, 0.015, 0.018)
# Two turned-pin carrier rails and end bridges. The centre remains open,
# matching the precision socket used by the SN75451 model.
assembly.add(box(2.35, 10.15, 3.65, -3.81, 0, 0.35), color=black)
assembly.add(box(2.35, 10.15, 3.65, +3.81, 0, 0.35), color=black)
assembly.add(box(5.30, 1.15, 1.10, 0, -4.50, 0.35), color=black)
assembly.add(box(5.30, 1.15, 1.10, 0, +4.50, 0.35), color=black)
for x in (-3.81, 3.81):
for y in (-3.81, -1.27, 1.27, 3.81):
assembly.add(cylinder(0.50, 3.15, x, y, -2.80), color=gold)
assembly.add(cylinder(1.22, 3.20, x, y, 0.55), color=gold)
assembly.add(cylinder(0.70, 3.23, x, y, 0.57), color=dark)
def make_opa380_adapter():
assembly = cq.Assembly(name="OPA380_SOIC8_ADAPTER_DIP8_PRECISION_SOCKET")
add_dip8_precision_socket(assembly)
green = cq.Color(0.035, 0.30, 0.12)
copper = cq.Color(0.72, 0.43, 0.12)
silver = cq.Color(0.72, 0.74, 0.76)
black = cq.Color(0.035, 0.035, 0.040)
marking = cq.Color(0.82, 0.82, 0.78)
# DIP-8/SOIC-8 adapter. Its lower pins plug into the precision socket.
for x in (-3.81, 3.81):
for y in (-3.81, -1.27, 1.27, 3.81):
assembly.add(cylinder(0.46, 3.30, x, y, 2.80), color=copper)
assembly.add(box(10.25, 10.25, 1.20, 0, 0, 6.00), color=green)
# Visible DIP pads on the adapter PCB.
for x in (-3.81, 3.81):
for y in (-3.81, -1.27, 1.27, 3.81):
assembly.add(cylinder(1.30, 0.06, x, y, 7.20), color=copper)
# OPA380 in TI D (SOIC-8): nominal 3.9 x 4.9 mm body, 1.27-mm pitch.
body = box(3.90, 4.90, 1.55, 0, 0, 7.33)
try:
body = body.edges("|Z").fillet(0.18)
except Exception:
pass
assembly.add(body, color=black)
# Gull-wing leads. Pin 1 is at the lower-left corner in top view.
for x in (-2.55, 2.55):
for y in (-1.905, -0.635, 0.635, 1.905):
assembly.add(box(1.25, 0.42, 0.16, x, y, 7.25), color=silver)
assembly.add(cylinder(0.42, 0.035, -1.28, -1.55, 8.88), color=marking)
output = OUT_DIR / "OPA380_SOIC8_ADAPTER_DIP8_PRECISION_SOCKET.step"
assembly.save(str(output), mode="default")
return output
def make_bpw34_vertical():
assembly = cq.Assembly(name="BPW34_VERTICAL_P5.08mm")
silver = cq.Color(0.72, 0.74, 0.76)
clear = cq.Color(0.72, 0.78, 0.80, 0.58)
die = cq.Color(0.10, 0.16, 0.19)
cathode_mark = cq.Color(0.25, 0.28, 0.30)
# Leads occupy footprint positions 1 and 3. Position 2 (x=0) is omitted.
# Centre-to-centre distance is therefore exactly 2 x 2.54 = 5.08 mm.
for x in (-2.54, 2.54):
assembly.add(box(0.50, 0.38, 5.30, x, 0, -2.60), color=silver)
# Upright BPW34 body, based on Vishay drawing 6.544-5315.01-4:
# 4.65-mm face width, 4.3-mm face height and 2.0-mm package depth.
# The leads are deliberately formed out to the requested 5.08-mm spacing.
body = box(4.65, 2.00, 4.30, 0, 0, 2.15)
try:
body = body.edges("|Z").fillet(0.25)
except Exception:
pass
assembly.add(body, color=clear)
# Visible detector die and bond area inside the transparent package.
assembly.add(box(3.00, 0.12, 3.00, 0, -0.89, 2.80), color=die)
# Cathode-side stripe, located by footprint pad 1 (left in top/front view).
assembly.add(box(0.22, 0.08, 3.55, -2.16, -1.06, 2.50), color=cathode_mark)
output = OUT_DIR / "BPW34_VERTICAL_P5.08mm.step"
assembly.save(str(output), mode="default")
return output
if __name__ == "__main__":
for model in (make_opa380_adapter(), make_bpw34_vertical()):
print(model)

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202
PCB/OptoTest.PrjPcb
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@@ -86,7 +86,7 @@ ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=VRLHYREI
DocumentUniqueId=FNFLLWRF
[Document4]
DocumentPath=Libs\ESP32-S3-SuperMini.SchLib
@@ -103,7 +103,7 @@ ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=LHZTVGFY
DocumentUniqueId=IWYWSUPY
[Document5]
DocumentPath=Libs\HFBR-1528Z_HFBR-2528Z.PcbLib
@@ -273,7 +273,7 @@ ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=A8G5624N
DocumentUniqueId=LAFSSKWH
[Document15]
DocumentPath=Libs\SN75451BP.PcbLib
@@ -326,6 +326,202 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document18]
DocumentPath=Libs\Sensor.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=SCOMYVDB
[Document19]
DocumentPath=Libs\BPW34.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=DEJBNXAE
[Document20]
DocumentPath=Libs\OPA380.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=TPLFYPML
[Document21]
DocumentPath=Libs\OPA380.SchLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=A8G5624N
[Document22]
DocumentPath=Libs\J_ARK3_2.54.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document23]
DocumentPath=Libs\J_ARK3.SchLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=WYDOVXHH
[Document24]
DocumentPath=gerber.Cam
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[Document25]
DocumentPath=nc_drills.Cam
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=
[GeneratedDocument1]
DocumentPath=Project Outputs for OptoTest\OptoTest.DRR
DItemRevisionGUID=
[GeneratedDocument2]
DocumentPath=Project Outputs for OptoTest\OptoTest.EXTREP
DItemRevisionGUID=
[GeneratedDocument3]
DocumentPath=Project Outputs for OptoTest\OptoTest.GBL
DItemRevisionGUID=
[GeneratedDocument4]
DocumentPath=Project Outputs for OptoTest\OptoTest.GBO
DItemRevisionGUID=
[GeneratedDocument5]
DocumentPath=Project Outputs for OptoTest\OptoTest.GBP
DItemRevisionGUID=
[GeneratedDocument6]
DocumentPath=Project Outputs for OptoTest\OptoTest.GBS
DItemRevisionGUID=
[GeneratedDocument7]
DocumentPath=Project Outputs for OptoTest\OptoTest.GKO
DItemRevisionGUID=
[GeneratedDocument8]
DocumentPath=Project Outputs for OptoTest\OptoTest.GTL
DItemRevisionGUID=
[GeneratedDocument9]
DocumentPath=Project Outputs for OptoTest\OptoTest.GTO
DItemRevisionGUID=
[GeneratedDocument10]
DocumentPath=Project Outputs for OptoTest\OptoTest.GTP
DItemRevisionGUID=
[GeneratedDocument11]
DocumentPath=Project Outputs for OptoTest\OptoTest.GTS
DItemRevisionGUID=
[GeneratedDocument12]
DocumentPath=Project Outputs for OptoTest\OptoTest.LDP
DItemRevisionGUID=
[GeneratedDocument13]
DocumentPath=Project Outputs for OptoTest\OptoTest.REP
DItemRevisionGUID=
[GeneratedDocument14]
DocumentPath=Project Outputs for OptoTest\OptoTest.RUL
DItemRevisionGUID=
[GeneratedDocument15]
DocumentPath=Project Outputs for OptoTest\OptoTest.TXT
DItemRevisionGUID=
[Configuration1]
Name=Sources
ParameterCount=0

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18
PCB/Project Outputs for OptoTest/OptoTest-macro.APR_LIB Normal file
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@@ -0,0 +1,18 @@
G04:AMPARAMS|DCode=41|XSize=2.3mm|YSize=1.8mm|CornerRadius=0.225mm|HoleSize=0mm|Usage=FLASHONLY|Rotation=90.000|XOffset=0mm|YOffset=0mm|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD41*
21,1,2.3000,1.3500,0,0,90.0*
21,1,1.8500,1.8000,0,0,90.0*
1,1,0.4500,0.6750,0.9250*
1,1,0.4500,0.6750,-0.9250*
1,1,0.4500,-0.6750,-0.9250*
1,1,0.4500,-0.6750,0.9250*
%
G04:AMPARAMS|DCode=42|XSize=2.45mm|YSize=1.95mm|CornerRadius=0.3mm|HoleSize=0mm|Usage=FLASHONLY|Rotation=90.000|XOffset=0mm|YOffset=0mm|HoleType=Round|Shape=RoundedRectangle|*
%AMROUNDEDRECTD42*
21,1,2.4500,1.3500,0,0,90.0*
21,1,1.8500,1.9500,0,0,90.0*
1,1,0.6000,0.6750,0.9250*
1,1,0.6000,0.6750,-0.9250*
1,1,0.6000,-0.6750,-0.9250*
1,1,0.6000,-0.6750,0.9250*
%

17
PCB/Project Outputs for OptoTest/OptoTest.DRR Normal file
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@@ -0,0 +1,17 @@
----------------------------------------------------------------------------------------------------------------------------------
NCDrill File Report For: OptoTest.PcbDoc 09.08.2026 13:58:41
----------------------------------------------------------------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
ASCII RoundHoles File : OptoTest.TXT
Tool Hole Size Hole Tolerance Hole Type Hole Count Plated Tool Travel
----------------------------------------------------------------------------------------------------------------------------------
T1 0.9mm (35mil) Round 4 PTH 0.00mm (0.00inch)
T2 1.3mm (51mil) Round 57 PTH 0.00mm (0.00inch)
T3 2mm (79mil) Round 8 PTH 0.00mm (0.00inch)
T4 3.1mm (122mil) Round 4 NPTH 0.00mm (0.00inch)
----------------------------------------------------------------------------------------------------------------------------------
Totals 73
Total Processing Time (hh:mm:ss) : 00:00:00

18
PCB/Project Outputs for OptoTest/OptoTest.EXTREP Normal file
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@@ -0,0 +1,18 @@
------------------------------------------------------------------------------------------
Gerber File Extension Report For: OptoTest.GBR 09.08.2026 13:57:58
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTO Top Overlay
.GTP Top Paste
.GTS Top Solder
.GTL Top Layer
.GBL Bottom Layer
.GBS Bottom Solder
.GBP Bottom Paste
.GBO Bottom Overlay
.GKO Keep-Out Layer
------------------------------------------------------------------------------------------

1905
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@@ -0,0 +1,1905 @@
G04*
G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,19.1.9 (167)*
G04*
G04 Layer_Physical_Order=3*
G04 Layer_Color=16711680*
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%ADD38C,2.8000*%
%ADD39C,1.5240*%
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G04:AMPARAMS|DCode=41|XSize=2.3mm|YSize=1.8mm|CornerRadius=0.225mm|HoleSize=0mm|Usage=FLASHONLY|Rotation=90.000|XOffset=0mm|YOffset=0mm|HoleType=Round|Shape=RoundedRectangle|*
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%
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G37*
G36*
X666500Y456500D02*
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X658987Y448987D01*
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Y456500D01*
D02*
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D02*
G37*
G36*
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Y433500D01*
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D02*
G37*
G36*
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X380000Y469092D01*
D02*
G37*
G36*
X256000D02*
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X242500Y463500D01*
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X256000Y430908D01*
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X263306Y432361D01*
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X266607Y465874D01*
X263306Y467639D01*
X259725Y468725D01*
X256000Y469092D01*
D02*
G37*
G36*
X80300Y426500D02*
X68300D01*
Y414500D01*
X80300D01*
Y426500D01*
D02*
G37*
G36*
X383500Y418747D02*
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X398747D01*
X398725Y403725D01*
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X390607Y415874D01*
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D02*
G37*
G36*
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Y403500D01*
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X266607Y415874D01*
X263306Y417639D01*
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D02*
G37*
G36*
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Y418747D01*
D02*
G37*
G36*
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D02*
G37*
G36*
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D02*
G37*
G36*
X666500Y398936D02*
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X666500D01*
Y398936D01*
D02*
G37*
G36*
X398747Y396500D02*
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X383725Y381275D01*
X387306Y382361D01*
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D02*
G37*
G36*
X274747D02*
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Y381253D01*
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X271874Y389393D01*
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D02*
G37*
G36*
X376500D02*
X361253D01*
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D02*
G37*
G36*
X252500D02*
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X242500Y386500D01*
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X252500Y381253D01*
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D02*
G37*
G36*
X439436Y385000D02*
X427800D01*
Y373364D01*
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X435313Y377487D01*
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D02*
G37*
G36*
X420800D02*
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Y385000D01*
D02*
G37*
G36*
X666500Y380300D02*
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D02*
G37*
G36*
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D02*
G37*
G36*
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D02*
G37*
G36*
X666500Y131336D02*
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Y131336D01*
D02*
G37*
G36*
Y112700D02*
X654864D01*
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X661347Y103250D01*
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D02*
G37*
G36*
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D02*
G37*
G36*
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D02*
G37*
G36*
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G37*
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D02*
G37*
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D02*
G37*
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D02*
G37*
G36*
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D02*
G37*
G36*
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D02*
G37*
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G37*
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D02*
G37*
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D18*
X554000Y380000D02*
D03*
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D03*
X554000Y405000D02*
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X571000D02*
D03*
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D03*
D20*
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D03*
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D03*
Y61000D02*
D03*
Y79000D02*
D03*
X620000Y52000D02*
D03*
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D03*
D21*
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D03*
X553000D02*
D03*
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D03*
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X549000Y97000D02*
D03*
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D03*
X446000Y60000D02*
D03*
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D03*
D33*
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358
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75
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235
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10
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431
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933
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X470235D01*
X467696Y394060D01*
X555235Y112382D02*
Y117461D01*
X552696Y120000D01*
X542539D01*
X540000Y117461D01*
Y112382D01*
X542539Y109843D01*
X552696D01*
X555235Y112382D01*
X540000Y104765D02*
X555235D01*
Y97147D01*
X552696Y94608D01*
X547617D01*
X545078Y97147D01*
Y104765D01*
X555235Y89530D02*
Y79373D01*
Y84452D01*
X540000D01*
X537461Y74295D02*
Y64138D01*
X540000Y59060D02*
X555235D01*
Y51442D01*
X552696Y48903D01*
X547617D01*
X545078Y51442D01*
Y59060D01*
Y53981D02*
X540000Y48903D01*
X555235Y43825D02*
X540000Y33668D01*
X555235D02*
X540000Y43825D01*
X135157Y407696D02*
X132618Y410235D01*
X127539D01*
X125000Y407696D01*
Y397539D01*
X127539Y395000D01*
X132618D01*
X135157Y397539D01*
X140235Y410235D02*
X150392D01*
Y407696D01*
X140235Y397539D01*
Y395000D01*
X135157Y382696D02*
X132618Y385235D01*
X127539D01*
X125000Y382696D01*
Y372539D01*
X127539Y370000D01*
X132618D01*
X135157Y372539D01*
X150392Y385235D02*
X145313Y382696D01*
X140235Y377617D01*
Y372539D01*
X142774Y370000D01*
X147853D01*
X150392Y372539D01*
Y375078D01*
X147853Y377617D01*
X140235D01*
X546157Y357196D02*
X543618Y359735D01*
X538539D01*
X536000Y357196D01*
Y347039D01*
X538539Y344500D01*
X543618D01*
X546157Y347039D01*
X551235Y357196D02*
X553774Y359735D01*
X558853D01*
X561392Y357196D01*
Y354657D01*
X558853Y352118D01*
X556313D01*
X558853D01*
X561392Y349578D01*
Y347039D01*
X558853Y344500D01*
X553774D01*
X551235Y347039D01*
X547157Y303696D02*
X544618Y306235D01*
X539539D01*
X537000Y303696D01*
Y293539D01*
X539539Y291000D01*
X544618D01*
X547157Y293539D01*
X562392Y291000D02*
X552235D01*
X562392Y301157D01*
Y303696D01*
X559853Y306235D01*
X554774D01*
X552235Y303696D01*
X122235Y282383D02*
Y287461D01*
X119696Y290000D01*
X109539D01*
X107000Y287461D01*
Y282383D01*
X109539Y279843D01*
X119696D01*
X122235Y282383D01*
Y274765D02*
X107000D01*
Y264608D01*
X122235Y249373D02*
Y259530D01*
X107000D01*
Y249373D01*
X114618Y259530D02*
Y254452D01*
X122235Y244295D02*
X107000D01*
Y236677D01*
X109539Y234138D01*
X119696D01*
X122235Y236677D01*
Y244295D01*
X232696Y119843D02*
X235235Y122382D01*
Y127461D01*
X232696Y130000D01*
X230157D01*
X227617Y127461D01*
Y122382D01*
X225078Y119843D01*
X222539D01*
X220000Y122382D01*
Y127461D01*
X222539Y130000D01*
X235235Y114765D02*
X220000D01*
X225078Y109687D01*
X220000Y104608D01*
X235235D01*
X217461Y99530D02*
Y89373D01*
X232696Y74138D02*
X235235Y76677D01*
Y81756D01*
X232696Y84295D01*
X230157D01*
X227617Y81756D01*
Y76677D01*
X225078Y74138D01*
X222539D01*
X220000Y76677D01*
Y81756D01*
X222539Y84295D01*
X235235Y69060D02*
Y58903D01*
Y63981D01*
X220000D01*
Y53825D02*
X230157D01*
X235235Y48746D01*
X230157Y43668D01*
X220000D01*
X227617D01*
Y53825D01*
X220000Y38590D02*
X235235D01*
Y30972D01*
X232696Y28433D01*
X227617D01*
X225078Y30972D01*
Y38590D01*
Y33511D02*
X220000Y28433D01*
X235235Y23354D02*
Y13198D01*
Y18276D01*
X220000D01*
X232696Y464843D02*
X235235Y467383D01*
Y472461D01*
X232696Y475000D01*
X230157D01*
X227617Y472461D01*
Y467383D01*
X225078Y464843D01*
X222539D01*
X220000Y467383D01*
Y472461D01*
X222539Y475000D01*
X235235Y459765D02*
X220000D01*
X225078Y454687D01*
X220000Y449608D01*
X235235D01*
X217461Y444530D02*
Y434373D01*
X220000Y429295D02*
X235235D01*
X230157Y424216D01*
X235235Y419138D01*
X220000D01*
X235235Y406442D02*
Y411521D01*
X232696Y414060D01*
X222539D01*
X220000Y411521D01*
Y406442D01*
X222539Y403903D01*
X232696D01*
X235235Y406442D01*
Y398825D02*
X220000D01*
Y391207D01*
X222539Y388668D01*
X232696D01*
X235235Y391207D01*
Y398825D01*
Y373433D02*
Y383590D01*
X220000D01*
Y373433D01*
X227617Y383590D02*
Y378511D01*
D12*
X330617Y375792D02*
G03*
X330929Y474127I-12617J49208D01*
G01*
X330477Y386323D02*
G03*
X330477Y463677I-12477J38677D01*
G01*
X305382Y474208D02*
G03*
X305072Y375873I12617J-49208D01*
G01*
X368800Y364040D02*
G03*
X378960Y374200I0J10160D01*
G01*
X257040D02*
G03*
X267200Y364040I10160J0D01*
G01*
Y485960D02*
G03*
X257040Y475800I0J-10160D01*
G01*
X378960D02*
G03*
X368800Y485960I-10160J0D01*
G01*
X305523Y463677D02*
G03*
X305523Y386323I12477J-38677D01*
G01*
X330617Y25792D02*
G03*
X330929Y124127I-12617J49208D01*
G01*
X330477Y36323D02*
G03*
X330477Y113677I-12477J38677D01*
G01*
X305382Y124208D02*
G03*
X305072Y25873I12617J-49208D01*
G01*
X368800Y14040D02*
G03*
X378960Y24200I0J10160D01*
G01*
X257040D02*
G03*
X267200Y14040I10160J0D01*
G01*
Y135960D02*
G03*
X257040Y125800I0J-10160D01*
G01*
X378960D02*
G03*
X368800Y135960I-10160J0D01*
G01*
X305523Y113677D02*
G03*
X305523Y36323I12477J-38677D01*
G01*
D13*
X694000Y158000D02*
Y190000D01*
X485000D02*
X694000D01*
X485000Y158000D02*
Y190000D01*
Y158000D02*
X694000D01*
Y310000D02*
Y342000D01*
X484000D02*
X694000D01*
X484000Y310000D02*
Y342000D01*
Y310000D02*
X694000D01*
D14*
X497474Y309660D02*
X532526D01*
Y302040D02*
Y309660D01*
X497474Y302040D02*
Y309660D01*
X532526Y289340D02*
Y296960D01*
X497474Y289340D02*
Y296960D01*
Y289340D02*
X532526D01*
X497474Y341840D02*
X532526D01*
X497474D02*
Y349460D01*
X532526Y341840D02*
Y349460D01*
X497474Y354540D02*
Y362160D01*
X532526Y354540D02*
Y362160D01*
X497474D02*
X532526D01*
X82474Y385160D02*
X117526D01*
Y377540D02*
Y385160D01*
X82474Y377540D02*
Y385160D01*
X117526Y364840D02*
Y372460D01*
X82474Y364840D02*
Y372460D01*
Y364840D02*
X117526D01*
X82474Y410160D02*
X117526D01*
Y402540D02*
Y410160D01*
X82474Y402540D02*
Y410160D01*
X117526Y389840D02*
Y397460D01*
X82474Y389840D02*
Y397460D01*
Y389840D02*
X117526D01*
X459660Y35474D02*
Y70526D01*
X452040Y35474D02*
X459660D01*
X452040Y70526D02*
X459660D01*
X439340Y35474D02*
X446960D01*
X439340Y70526D02*
X446960D01*
X439340Y35474D02*
Y70526D01*
X480160Y35474D02*
Y70526D01*
X472540Y35474D02*
X480160D01*
X472540Y70526D02*
X480160D01*
X459840Y35474D02*
X467460D01*
X459840Y70526D02*
X467460D01*
X459840Y35474D02*
Y70526D01*
X458652Y121526D02*
X458652Y107810D01*
X439348Y121526D02*
X458652D01*
X439348Y107810D02*
X439348Y121526D01*
X458652Y86474D02*
Y100190D01*
X439348Y86474D02*
X458652D01*
X439348D02*
Y100190D01*
X465974Y148652D02*
X479690Y148652D01*
X465974Y129348D02*
Y148652D01*
Y129348D02*
X479690Y129348D01*
X487310Y148652D02*
X501026D01*
Y129348D02*
Y148652D01*
X487310Y129348D02*
X501026D01*
D15*
X60800Y444000D02*
X182800D01*
Y131000D02*
Y444000D01*
X60800Y131000D02*
X182800D01*
X60800D02*
Y444000D01*
D16*
X565250Y21000D02*
X689000D01*
Y134000D01*
X565250D02*
X689000D01*
X565250Y21000D02*
Y134000D01*
Y366000D02*
Y477000D01*
X689000D01*
Y366000D02*
Y477000D01*
X565250Y366000D02*
X689000D01*
D17*
X477000Y91000D02*
X461765D01*
Y98617D01*
X464304Y101157D01*
X469383D01*
X471922Y98617D01*
Y91000D01*
Y96078D02*
X477000Y101157D01*
Y113853D02*
X461765D01*
X469383Y106235D01*
Y116392D01*
X440664Y82331D02*
X438998Y83997D01*
X435666D01*
X434000Y82331D01*
Y75666D01*
X435666Y74000D01*
X438998D01*
X440664Y75666D01*
X443997Y74000D02*
X447329D01*
X445663D01*
Y83997D01*
X443997Y82331D01*
X452327D02*
X453994Y83997D01*
X457326D01*
X458992Y82331D01*
Y75666D01*
X457326Y74000D01*
X453994D01*
X452327Y75666D01*
Y82331D01*
M02*

50
PCB/Project Outputs for OptoTest/OptoTest.GTP Normal file
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@@ -0,0 +1,50 @@
G04*
G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,19.1.9 (167)*
G04*
G04 Layer_Color=8421504*
%FSLAX44Y44*%
%MOMM*%
G71*
G01*
G75*
%ADD18R,1.3000X1.5000*%
%ADD19R,1.5000X1.3000*%
%ADD20R,1.4000X1.2000*%
%ADD21R,1.2000X1.4000*%
D18*
X523500Y299500D02*
D03*
X506500D02*
D03*
Y352000D02*
D03*
X523500D02*
D03*
X108500Y375000D02*
D03*
X91500D02*
D03*
X108500Y400000D02*
D03*
X91500D02*
D03*
D19*
X449500Y44500D02*
D03*
Y61500D02*
D03*
X470000Y44500D02*
D03*
Y61500D02*
D03*
D20*
X449000Y113000D02*
D03*
Y95000D02*
D03*
D21*
X474500Y139000D02*
D03*
X492500D02*
D03*
M02*

210
PCB/Project Outputs for OptoTest/OptoTest.GTS Normal file
View File

@@ -0,0 +1,210 @@
G04*
G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,19.1.9 (167)*
G04*
G04 Layer_Color=8388736*
%FSLAX44Y44*%
%MOMM*%
G71*
G01*
G75*
%ADD22R,1.4500X1.6500*%
%ADD23R,1.6500X1.4500*%
%ADD24R,1.5500X1.3500*%
%ADD25R,1.3500X1.5500*%
%ADD26O,2.2500X2.1500*%
%ADD27C,2.2500*%
%ADD28R,2.2500X2.2500*%
%ADD29R,2.2500X2.2500*%
%ADD30C,3.0000*%
%ADD31C,1.6740*%
%ADD32C,1.8500*%
D22*
X523500Y299500D02*
D03*
X506500D02*
D03*
Y352000D02*
D03*
X523500D02*
D03*
X108500Y375000D02*
D03*
X91500D02*
D03*
X108500Y400000D02*
D03*
X91500D02*
D03*
D23*
X449500Y44500D02*
D03*
Y61500D02*
D03*
X470000Y44500D02*
D03*
Y61500D02*
D03*
D24*
X449000Y113000D02*
D03*
Y95000D02*
D03*
D25*
X474500Y139000D02*
D03*
X492500D02*
D03*
D26*
X593800Y434600D02*
D03*
D27*
X139800Y36000D02*
D03*
X114400D02*
D03*
X89000D02*
D03*
X678900Y326200D02*
D03*
X653500D02*
D03*
X628100D02*
D03*
X602700D02*
D03*
X577300D02*
D03*
X551900D02*
D03*
X526500D02*
D03*
X501100D02*
D03*
X678900Y173800D02*
D03*
X653500D02*
D03*
X628100D02*
D03*
X602700D02*
D03*
X577300D02*
D03*
X551900D02*
D03*
X526500D02*
D03*
X501100D02*
D03*
X416900Y34400D02*
D03*
Y59800D02*
D03*
Y85200D02*
D03*
Y110600D02*
D03*
X493100D02*
D03*
Y85200D02*
D03*
Y59800D02*
D03*
X424300Y439300D02*
D03*
Y413900D02*
D03*
Y388500D02*
D03*
X500500D02*
D03*
Y413900D02*
D03*
Y439300D02*
D03*
Y464700D02*
D03*
X109200Y430000D02*
D03*
X134600D02*
D03*
X160000D02*
D03*
X670000Y40000D02*
D03*
Y116200D02*
D03*
X593800D02*
D03*
Y90800D02*
D03*
Y65400D02*
D03*
Y409200D02*
D03*
Y460000D02*
D03*
X670000D02*
D03*
Y383800D02*
D03*
X58400Y109000D02*
D03*
X160000D02*
D03*
X134600D02*
D03*
X109200D02*
D03*
X83800D02*
D03*
D28*
X493100Y34400D02*
D03*
X424300Y464684D02*
D03*
X185400Y109000D02*
D03*
D29*
X83800Y430000D02*
D03*
X593800Y40000D02*
D03*
Y383800D02*
D03*
D30*
X380000Y400000D02*
D03*
X256000D02*
D03*
X380000Y450000D02*
D03*
X256000D02*
D03*
X380000Y50000D02*
D03*
X256000D02*
D03*
X380000Y100000D02*
D03*
X256000D02*
D03*
D31*
X25000Y475000D02*
D03*
Y25000D02*
D03*
X375000Y250000D02*
D03*
X650000D02*
D03*
D32*
X500000Y224000D02*
D03*
X525000Y233000D02*
D03*
X450000Y272000D02*
D03*
X574999Y198000D02*
D03*
M02*

2
PCB/Project Outputs for OptoTest/OptoTest.LDP Normal file
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@@ -0,0 +1,2 @@
Layer Pairs Export File for PCB: E:\.WORK\ARDUINO\OptoTest\PCB\OptoTest.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=optotest.txt|DrillLayers=gtl,g1,gbl

179
PCB/Project Outputs for OptoTest/OptoTest.REP Normal file
View File

@@ -0,0 +1,179 @@
*************************************************************
FileName = OptoTest.GBR
AutoAperture = True
*************************************************************
Generating : Top Paste
File : OptoTest.GTP
Adding Layer : Top Paste
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D18
D19
D20
D21
*************************************************************
*************************************************************
Generating : Top Layer
File : OptoTest.GTL
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D18
D19
D20
D21
D33
D34
D35
D36
D37
D38
D39
D40
*************************************************************
*************************************************************
Generating : Bottom Solder
File : OptoTest.GBS
Adding Layer : Bottom Solder
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D22
D24
D25
D26
D27
D28
D29
D30
D31
D32
D42
*************************************************************
*************************************************************
Generating : Top Solder
File : OptoTest.GTS
Adding Layer : Top Solder
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
*************************************************************
*************************************************************
Generating : Top Overlay
File : OptoTest.GTO
Adding Layer : Top Overlay
Used DCodes :
D10
D11
D12
D13
D14
D15
D16
D17
*************************************************************
*************************************************************
Generating : Bottom Overlay
File : OptoTest.GBO
Adding Layer : Bottom Overlay
Used DCodes :
D10
D11
D14
D43
*************************************************************
*************************************************************
Generating : Bottom Paste
File : OptoTest.GBP
Adding Layer : Bottom Paste
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D18
D20
D21
D41
*************************************************************
*************************************************************
Generating : Bottom Layer
File : OptoTest.GBL
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D18
D20
D21
D33
D34
D35
D36
D37
D38
D39
D40
D41
*************************************************************
*************************************************************
Generating : Keep-Out Layer
File : OptoTest.GKO
Adding Layer : Keep-Out Layer
Used DCodes :
*************************************************************

7
PCB/Project Outputs for OptoTest/OptoTest.RUL Normal file
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@@ -0,0 +1,7 @@
DRC Rules Export File for PCB: E:\.WORK\ARDUINO\OptoTest\PCB\OptoTest.PcbDoc
RuleKind=Clearance|RuleName=Vint|Scope=Board|Minimum=118.11
RuleKind=MinimumAnnularRing|RuleName=MinimumAnnularRing|Scope=Board|Minimum=5.91
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=2.95
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=19.69

89
PCB/Project Outputs for OptoTest/OptoTest.TXT Normal file
View File

@@ -0,0 +1,89 @@
M48
;Layer_Color=9474304
;FILE_FORMAT=4:4
METRIC,LZ
;TYPE=PLATED
T1F00S00C0.9000
T2F00S00C1.3000
T3F00S00C2.0000
;TYPE=NON_PLATED
T4F00S00C3.1000
%
T01
X00574999Y00198
X00525Y00233
X005Y00224
X0045Y00272
T02
X00089Y00036
X001144
X001398
X004169Y000344
Y000598
X004931
Y000344
X005938Y0004
X0067
Y001162
X006789Y001738
X006535
X006281
X006027
X005773
X005938Y001162
Y000908
Y000654
X006027Y003262
X005773
X006281
X006535
X006789
X0067Y003838
X005938
Y004092
Y004346
X005005Y004393
Y004139
Y003885
X005011Y003262
X005265
X005519
Y001738
X005265
X005011
X004931Y001106
Y000852
X004169
Y001106
X001854Y00109
X004243Y003885
Y004139
Y004393
X0016Y0043
X001346
X001092
X000838
Y00109
X000584
X001092
X001346
X0016
X004243Y00464684
X005005Y004647
X005938Y0046
X0067
T03
X00256Y0005
X0038
Y001
X00256
Y004
Y0045
X0038
Y004
T04
X00025Y00025
X0065Y0025
X00375
X00025Y00475
M30

32
PCB/Project Outputs for OptoTest/OptoTest.apr Normal file
View File

@@ -0,0 +1,32 @@
D10 ROUNDED 7.874 7.874 0.000 LINE 0.000
D11 ROUNDED 10.000 10.000 0.000 LINE 0.000
D12 ROUNDED 6.000 6.000 0.000 LINE 0.000
D13 ROUNDED 7.087 7.087 0.000 LINE 0.000
D14 ROUNDED 3.937 3.937 0.000 LINE 0.000
D15 ROUNDED 5.906 5.906 0.000 LINE 0.000
D16 ROUNDED 9.842 9.842 0.000 LINE 0.000
D17 ROUNDED 6.063 6.063 0.000 LINE 0.000
D18 RECTANGULAR 59.055 51.181 0.000 FLASH 90.000
D19 RECTANGULAR 59.055 51.181 0.000 FLASH 180.000
D20 RECTANGULAR 55.118 47.244 0.000 FLASH 180.000
D21 RECTANGULAR 55.118 47.244 0.000 FLASH 270.000
D22 RECTANGULAR 64.961 57.087 0.000 FLASH 90.000
D23 RECTANGULAR 64.961 57.087 0.000 FLASH 180.000
D24 RECTANGULAR 61.024 53.150 0.000 FLASH 180.000
D25 RECTANGULAR 61.024 53.150 0.000 FLASH 270.000
D26 ROUNDED 84.646 88.583 0.000 FLASH 270.000
D27 ROUNDED 88.583 88.583 0.000 FLASH 0.000
D28 RECTANGULAR 88.583 88.583 0.000 FLASH 180.000
D29 RECTANGULAR 88.583 88.583 0.000 FLASH 270.000
D30 ROUNDED 118.110 118.110 0.000 FLASH 0.000
D31 ROUNDED 65.906 65.906 0.000 FLASH 0.000
D32 ROUNDED 72.835 72.835 0.000 FLASH 0.000
D33 ROUNDED 31.496 31.496 0.000 LINE 0.000
D34 ROUNDED 78.740 82.677 0.000 FLASH 270.000
D35 ROUNDED 82.677 82.677 0.000 FLASH 0.000
D36 RECTANGULAR 82.677 82.677 0.000 FLASH 180.000
D37 RECTANGULAR 82.677 82.677 0.000 FLASH 270.000
D38 ROUNDED 110.236 110.236 0.000 FLASH 0.000
D39 ROUNDED 60.000 60.000 0.000 FLASH 0.000
D40 ROUNDED 66.929 66.929 0.000 FLASH 0.000
D43 ROUNDED 5.000 5.000 0.000 LINE 0.000

12
PCB/Project Outputs for OptoTest/Status Report.Txt Normal file
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Output: NC Drill Files
Type : NC Drill
From : Project [OptoTest.PrjPcb]
Generated File[OptoTest.TXT]
Generated File[OptoTest.LDP]
Generated File[OptoTest.DRR]
Files Generated : 3
Documents Printed : 0
Finished Output Generation At 13:58:41 On 09.08.2026

72
PCB/Project Outputs for OptoTest/pcb-project.pcb.json Normal file
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{
"alignment": {
"circle_diameter": 3,
"top_point": [
0,
-1.9999999999999998
]
},
"cutout": {
"bottom": 2,
"enabled": false,
"left": 2,
"right": 2,
"side": "auto",
"tab_width": 3,
"tabs_enabled": true,
"top": 2
},
"files": [
{
"layer": "bottom",
"mirror_x": false,
"mirror_y": false,
"path": "OptoTest.GBL"
},
{
"layer": "top",
"mirror_x": false,
"mirror_y": false,
"path": "OptoTest.GTL"
},
{
"layer": "drill",
"mirror_x": false,
"mirror_y": false,
"path": "OptoTest.TXT"
}
],
"mirror": {
"axis": "Y",
"enabled": true,
"left_reference_offset": -9,
"point": [
91,
0
],
"reference_distance": 200
},
"output_dir": "F:/Work/CNC/CNC Software/CNCGerber/cam-output",
"settings": {
"combine_top_and_cutout": false,
"cut_depth_per_pass": 0.5,
"cut_multidepth": false,
"cut_z": -0.05,
"drill_depth_per_pass": 0.5,
"drill_diameter": 0.5,
"drill_multidepth": false,
"drill_side": "top",
"drill_z": -2.3,
"feedrate_rapid": 500,
"feedrate_xy": 200,
"feedrate_z": 100,
"include_m_commands": false,
"mill_diameter": 0.5,
"min_copper_strip_width": 0,
"spindle_speed": 10000,
"travel_z": 2,
"units": "MM"
},
"type": "cncgerber-pcb-project",
"version": 1
}

62
PCB/Scripts/RivetViaConverter/README.md Normal file
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# Rivet Via Converter для Altium Designer
Скрипт анализирует все отверстия активного `PcbDoc` и преобразует в размеры
имеющихся заклёпок как сквозные Via, так и все сверлёные Pad. Обрабатываются
свободные объекты на плате и примитивы внутри футпринтов:
| Исходный Hole Size | Новый Hole Size | Диаметр меди | Диаметр зоны изоляции |
|---:|---:|---:|---:|
| `<= 0,3 мм` | `0,9 мм` | `1,7 мм` | `2,2 мм` |
| `<= 1,1 мм` | `1,3 мм` | `2,1 мм` | `2,7 мм` |
| `> 1,1 мм` | `2,0 мм` | `2,8 мм` | `3,7 мм` |
Дополнительный запас к внешнему диаметру не добавляется. Глухие и скрытые Via
не изменяются. Также игнорируются неплакированные Pad и отверстия, у которых
внешний размер площадки равен диаметру отверстия, то есть отсутствует медное
кольцо. SMD Pad с нулевым размером отверстия не изменяются. Диаметр меди всегда
равен `Hole Size + 0,8 мм`. У сверлёных Pad задаются одинаковые X/Y-размеры меди
на Top, Mid и Bottom, но исходная форма площадки сохраняется. Готовые размеры распознаются
отдельно, поэтому скрипт можно запускать повторно без дальнейшего увеличения.
Скрипт проверяет активное общее правило Clearance со Scope `All / All`. Для
каждой группы отдельное правило создаётся или обновляется только тогда, когда
общий clearance меньше требуемого зазора от края меди. Если общий clearance уже
достаточен, правило группы не создаётся, а ранее созданное скриптом правило
удаляется.
Возможные отдельные правила:
- `RIVET_03_RoutingIsolation` — зазор от края меди `0,25 мм`;
- `RIVET_11_RoutingIsolation` — зазор от края меди `0,30 мм`;
- `RIVET_GT11_RoutingIsolation` — зазор от края меди `0,45 мм`.
Область действия первой стороны каждого правила автоматически выбирает Via и
plated Pad с соответствующей парой Hole Size/диаметр. Вторая сторона выбирает
только дорожки, дуги трассировки, медные Fill/Region и Polygon. Поэтому другие
Pad и Via могут располагаться ближе и продолжают использовать обычное правило
clearance платы, например `0,5 мм`.
Например, при общем clearance `0,5 мм` он уже превышает все три требуемых
значения (`0,25 / 0,30 / 0,45 мм`), поэтому ни одно дополнительное правило не
понадобится.
## Запуск
1. Откройте `RivetViaConverter.PrjScr` в Altium Designer.
2. Откройте и сделайте активным нужный `PcbDoc`.
3. Выберите `File -> Run Script`.
4. Для проверки без изменений запустите `AnalyzeVias` — несмотря на историческое
имя процедуры, она проверяет и Via, и сверлёные Pad.
5. Для преобразования и синхронизации правил запустите `ConvertViasToRivets` —
она изменяет оба типа объектов.
6. Проверьте показанную сводку и нажмите `OK`.
Все изменения формируются как одна операция Undo. Скрипт не сохраняет файл
автоматически.
## После преобразования
Запустите DRC: увеличенные площадки могут нарушить Clearance или выйти слишком
близко к контуру платы. Также проверьте настройки Solder Mask Expansion: медь
вокруг заклёпки должна быть открыта с обеих сторон платы. Сам скрипт настройки
паяльной маски и правила PCB не меняет.

8
PCB/Scripts/RivetViaConverter/RivetViaConverter.PrjScr Normal file
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[Design]
Version=1.0
HierarchyMode=0
[Document1]
DocumentPath=RivetViaConverter.pas
AnnotationEnabled=1

843
PCB/Scripts/RivetViaConverter/RivetViaConverter.pas Normal file
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{ RivetViaConverter.pas
Converts through-hole vias and drilled pads to the available PCB rivet sizes.
Source classification is based on the object's current hole diameter:
<= 0.3 mm -> drill 0.9 mm, copper diameter 1.7 mm
<= 1.1 mm -> drill 1.3 mm, copper diameter 2.1 mm
> 1.1 mm -> drill 2.0 mm, copper diameter 2.8 mm
Copper diameter is always drill diameter + 0.8 mm.
Existing complete hole/diameter target pairs are recognized before source
thresholds, making repeated runs safe (idempotent).
}
Const
CLASS_NONE = 0;
CLASS_03 = 1;
CLASS_08 = 2;
CLASS_12 = 3;
CLASS_NOT_THROUGH = 4;
Var
GTotalVias : Integer;
GChange03 : Integer;
GChange08 : Integer;
GChange12 : Integer;
GAlreadyReady : Integer;
GSkippedLarge : Integer;
GSkippedNotThru : Integer;
GFootprintVias : Integer;
GTotalDrilledPads : Integer;
GFootprintPads : Integer;
GSkippedNoRing : Integer;
GSkippedNonPlated : Integer;
GRulesCreated : Integer;
GRulesUpdated : Integer;
GRulesRemoved : Integer;
GRulesNotNeeded : Integer;
GDefaultClearance : TCoord;
GDefaultRuleFound : Boolean;
Function CoordIsNear(A, B : TCoord) : Boolean;
Begin
Result := Abs(A - B) <= MMsToCoord(0.001);
End;
Function IsThroughBoardVia(Via : IPCB_Via) : Boolean;
Begin
Result := (Via.LowLayer = eTopLayer) And
(Via.HighLayer = eBottomLayer);
End;
Function ViaHasNoAnnularRing(Via : IPCB_Via) : Boolean;
Begin
Result := Via.Size <= Via.HoleSize + MMsToCoord(0.001);
End;
Function ClassifyHole(Hole : TCoord;
Var TargetHole : TCoord;
Var TargetSize : TCoord) : Integer;
Begin
Result := CLASS_NONE;
TargetHole := 0;
TargetSize := 0;
If Hole <= MMsToCoord(0.3) Then
Begin
Result := CLASS_03;
TargetHole := MMsToCoord(0.9);
TargetSize := MMsToCoord(1.7);
End
Else If Hole <= MMsToCoord(1.1) Then
Begin
Result := CLASS_08;
TargetHole := MMsToCoord(1.3);
TargetSize := MMsToCoord(2.1);
End
Else If Hole > MMsToCoord(1.1) Then
Begin
Result := CLASS_12;
TargetHole := MMsToCoord(2.0);
TargetSize := MMsToCoord(2.8);
End;
End;
Function ViaMatchesKnownTemplate(Via : IPCB_Via) : Boolean;
Begin
Result :=
(CoordIsNear(Via.HoleSize, MMsToCoord(0.9)) And
CoordIsNear(Via.Size, MMsToCoord(1.7))) Or
(CoordIsNear(Via.HoleSize, MMsToCoord(1.3)) And
CoordIsNear(Via.Size, MMsToCoord(2.1))) Or
(CoordIsNear(Via.HoleSize, MMsToCoord(2.0)) And
CoordIsNear(Via.Size, MMsToCoord(2.8)));
End;
Function ClassifyVia(Via : IPCB_Via;
Var TargetHole : TCoord;
Var TargetSize : TCoord) : Integer;
Begin
If Not IsThroughBoardVia(Via) Then
Begin
TargetHole := 0;
TargetSize := 0;
Result := CLASS_NOT_THROUGH;
Exit;
End;
{ Migrate exact target pairs produced by older script versions without
moving them into a larger group based on their already enlarged drill. }
If CoordIsNear(Via.HoleSize, MMsToCoord(0.9)) And
CoordIsNear(Via.Size, MMsToCoord(2.0)) Then
Begin
TargetHole := MMsToCoord(0.9);
TargetSize := MMsToCoord(1.7);
Result := CLASS_03;
Exit;
End;
If CoordIsNear(Via.HoleSize, MMsToCoord(1.3)) And
CoordIsNear(Via.Size, MMsToCoord(2.5)) Then
Begin
TargetHole := MMsToCoord(1.3);
TargetSize := MMsToCoord(2.1);
Result := CLASS_08;
Exit;
End;
If CoordIsNear(Via.HoleSize, MMsToCoord(2.0)) And
CoordIsNear(Via.Size, MMsToCoord(3.5)) Then
Begin
TargetHole := MMsToCoord(2.0);
TargetSize := MMsToCoord(2.8);
Result := CLASS_12;
Exit;
End;
Result := ClassifyHole(Via.HoleSize, TargetHole, TargetSize);
End;
Procedure ResetCounts;
Begin
GTotalVias := 0;
GChange03 := 0;
GChange08 := 0;
GChange12 := 0;
GAlreadyReady := 0;
GSkippedLarge := 0;
GSkippedNotThru := 0;
GFootprintVias := 0;
GTotalDrilledPads := 0;
GFootprintPads := 0;
GSkippedNoRing := 0;
GSkippedNonPlated := 0;
End;
Procedure AnalyzeOneVia(Via : IPCB_Via; IsInFootprint : Boolean);
Var
ViaClass : Integer;
TargetHole : TCoord;
TargetSize : TCoord;
Begin
Inc(GTotalVias);
If IsInFootprint Then
Inc(GFootprintVias);
If ViaHasNoAnnularRing(Via) Then
Begin
Inc(GSkippedNoRing);
Exit;
End;
ViaClass := ClassifyVia(Via, TargetHole, TargetSize);
If ViaClass = CLASS_NOT_THROUGH Then
Inc(GSkippedNotThru)
Else If ViaClass = CLASS_NONE Then
Inc(GSkippedLarge)
Else If ViaMatchesKnownTemplate(Via) Then
Inc(GAlreadyReady)
Else If ViaClass = CLASS_03 Then
Inc(GChange03)
Else If ViaClass = CLASS_08 Then
Inc(GChange08)
Else If ViaClass = CLASS_12 Then
Inc(GChange12);
End;
Function PadHasNoAnnularRing(Pad : IPCB_Pad) : Boolean;
Var
MaxSize : TCoord;
Begin
MaxSize := Pad.TopXSize;
If Pad.TopYSize > MaxSize Then MaxSize := Pad.TopYSize;
If Pad.MidXSize > MaxSize Then MaxSize := Pad.MidXSize;
If Pad.MidYSize > MaxSize Then MaxSize := Pad.MidYSize;
If Pad.BotXSize > MaxSize Then MaxSize := Pad.BotXSize;
If Pad.BotYSize > MaxSize Then MaxSize := Pad.BotYSize;
Result := MaxSize <= Pad.HoleSize + MMsToCoord(0.001);
End;
Function PadIsReady(Pad : IPCB_Pad; TargetHole, TargetSize : TCoord) : Boolean;
Begin
Result := CoordIsNear(Pad.HoleSize, TargetHole) And
CoordIsNear(Pad.TopXSize, TargetSize) And
CoordIsNear(Pad.TopYSize, TargetSize) And
CoordIsNear(Pad.MidXSize, TargetSize) And
CoordIsNear(Pad.MidYSize, TargetSize) And
CoordIsNear(Pad.BotXSize, TargetSize) And
CoordIsNear(Pad.BotYSize, TargetSize);
End;
Function PadMatchesKnownTemplate(Pad : IPCB_Pad) : Boolean;
Begin
Result :=
PadIsReady(Pad, MMsToCoord(0.9), MMsToCoord(1.7)) Or
PadIsReady(Pad, MMsToCoord(1.3), MMsToCoord(2.1)) Or
PadIsReady(Pad, MMsToCoord(2.0), MMsToCoord(2.8));
End;
Function ClassifyPad(Pad : IPCB_Pad;
Var TargetHole : TCoord;
Var TargetSize : TCoord) : Integer;
Begin
{ Migrate exact target pairs produced by older script versions. }
If PadIsReady(Pad, MMsToCoord(0.9), MMsToCoord(2.0)) Then
Begin
TargetHole := MMsToCoord(0.9);
TargetSize := MMsToCoord(1.7);
Result := CLASS_03;
Exit;
End;
If PadIsReady(Pad, MMsToCoord(1.3), MMsToCoord(2.5)) Then
Begin
TargetHole := MMsToCoord(1.3);
TargetSize := MMsToCoord(2.1);
Result := CLASS_08;
Exit;
End;
If PadIsReady(Pad, MMsToCoord(2.0), MMsToCoord(3.5)) Then
Begin
TargetHole := MMsToCoord(2.0);
TargetSize := MMsToCoord(2.8);
Result := CLASS_12;
Exit;
End;
Result := ClassifyHole(Pad.HoleSize, TargetHole, TargetSize);
End;
Procedure AnalyzeOnePad(Pad : IPCB_Pad; IsInFootprint : Boolean);
Var
PadClass : Integer;
TargetHole : TCoord;
TargetSize : TCoord;
Begin
{ HoleSize = 0 means an SMD pad. It must remain untouched. }
If Pad.HoleSize <= 0 Then
Exit;
Inc(GTotalDrilledPads);
If IsInFootprint Then
Inc(GFootprintPads);
If Not Pad.Plated Then
Begin
Inc(GSkippedNonPlated);
Exit;
End;
If PadHasNoAnnularRing(Pad) Then
Begin
Inc(GSkippedNoRing);
Exit;
End;
PadClass := ClassifyPad(Pad, TargetHole, TargetSize);
If PadClass = CLASS_NONE Then
Inc(GSkippedLarge)
Else If PadMatchesKnownTemplate(Pad) Then
Inc(GAlreadyReady)
Else If PadClass = CLASS_03 Then
Inc(GChange03)
Else If PadClass = CLASS_08 Then
Inc(GChange08)
Else If PadClass = CLASS_12 Then
Inc(GChange12);
End;
Procedure AnalyzeBoard(Board : IPCB_Board);
Var
Iterator : IPCB_BoardIterator;
ComponentIterator : IPCB_BoardIterator;
GroupIterator : IPCB_GroupIterator;
Via : IPCB_Via;
Pad : IPCB_Pad;
Component : IPCB_Component;
Begin
ResetCounts;
{ First process free vias placed directly on the board. }
Iterator := Board.BoardIterator_Create;
Iterator.AddFilter_ObjectSet(MkSet(eViaObject));
Iterator.AddFilter_LayerSet(AllLayers);
Iterator.AddFilter_Method(eProcessAll);
Try
Via := Iterator.FirstPCBObject;
While Via <> Nil Do
Begin
If Not Via.InComponent Then
AnalyzeOneVia(Via, False);
Via := Iterator.NextPCBObject;
End;
Finally
Board.BoardIterator_Destroy(Iterator);
End;
{ Process free drilled pads placed directly on the board. }
Iterator := Board.BoardIterator_Create;
Iterator.AddFilter_ObjectSet(MkSet(ePadObject));
Iterator.AddFilter_LayerSet(AllLayers);
Iterator.AddFilter_Method(eProcessAll);
Try
Pad := Iterator.FirstPCBObject;
While Pad <> Nil Do
Begin
If Not Pad.InComponent Then
AnalyzeOnePad(Pad, False);
Pad := Iterator.NextPCBObject;
End;
Finally
Board.BoardIterator_Destroy(Iterator);
End;
{ Board iterators do not expose component child primitives consistently
across Altium versions. Walk each footprint explicitly. }
ComponentIterator := Board.BoardIterator_Create;
ComponentIterator.AddFilter_ObjectSet(MkSet(eComponentObject));
ComponentIterator.AddFilter_LayerSet(AllLayers);
ComponentIterator.AddFilter_Method(eProcessAll);
Try
Component := ComponentIterator.FirstPCBObject;
While Component <> Nil Do
Begin
GroupIterator := Component.GroupIterator_Create;
GroupIterator.AddFilter_ObjectSet(MkSet(eViaObject));
Try
Via := GroupIterator.FirstPCBObject;
While Via <> Nil Do
Begin
AnalyzeOneVia(Via, True);
Via := GroupIterator.NextPCBObject;
End;
Finally
Component.GroupIterator_Destroy(GroupIterator);
End;
GroupIterator := Component.GroupIterator_Create;
GroupIterator.AddFilter_ObjectSet(MkSet(ePadObject));
Try
Pad := GroupIterator.FirstPCBObject;
While Pad <> Nil Do
Begin
AnalyzeOnePad(Pad, True);
Pad := GroupIterator.NextPCBObject;
End;
Finally
Component.GroupIterator_Destroy(GroupIterator);
End;
Component := ComponentIterator.NextPCBObject;
End;
Finally
Board.BoardIterator_Destroy(ComponentIterator);
End;
End;
Function ChangesCount : Integer;
Begin
Result := GChange03 + GChange08 + GChange12;
End;
Function BuildSummary : String;
Begin
Result :=
'Rivet hole analysis' + #13#10 + #13#10 +
'All vias: ' + IntToStr(GTotalVias) + #13#10 +
'Vias inside footprints: ' + IntToStr(GFootprintVias) + #13#10 +
'All drilled pads: ' + IntToStr(GTotalDrilledPads) + #13#10 +
'Drilled pads inside footprints: ' + IntToStr(GFootprintPads) + #13#10 +
'Will set 1.7 / 0.9 mm: ' + IntToStr(GChange03) + #13#10 +
'Will set 2.1 / 1.3 mm: ' + IntToStr(GChange08) + #13#10 +
'Will set 2.8 / 2.0 mm: ' + IntToStr(GChange12) + #13#10 +
'Already ready: ' + IntToStr(GAlreadyReady) + #13#10 +
'Skipped, no annular ring: ' + IntToStr(GSkippedNoRing) + #13#10 +
'Skipped, non-plated pad: ' + IntToStr(GSkippedNonPlated) + #13#10 +
'Skipped, unsupported hole: ' + IntToStr(GSkippedLarge) + #13#10 +
'Skipped, blind/buried via: ' + IntToStr(GSkippedNotThru);
End;
Function ApplyOneVia(Via : IPCB_Via) : Boolean;
Var
ViaClass : Integer;
TargetHole : TCoord;
TargetSize : TCoord;
Begin
Result := False;
If ViaHasNoAnnularRing(Via) Then
Exit;
If ViaMatchesKnownTemplate(Via) Then
Exit;
ViaClass := ClassifyVia(Via, TargetHole, TargetSize);
If (ViaClass >= CLASS_03) And (ViaClass <= CLASS_12) And
(Not (CoordIsNear(Via.HoleSize, TargetHole) And
CoordIsNear(Via.Size, TargetSize))) Then
Begin
PCBServer.SendMessageToRobots(
Via.I_ObjectAddress,
c_Broadcast,
PCBM_BeginModify,
c_NoEventData);
Try
Via.HoleSize := TargetHole;
Via.Size := TargetSize;
Finally
PCBServer.SendMessageToRobots(
Via.I_ObjectAddress,
c_Broadcast,
PCBM_EndModify,
c_NoEventData);
End;
Result := True;
End;
End;
Function ApplyOnePad(Pad : IPCB_Pad) : Boolean;
Var
PadClass : Integer;
TargetHole : TCoord;
TargetSize : TCoord;
Begin
Result := False;
If Pad.HoleSize <= 0 Then
Exit;
If Not Pad.Plated Then
Exit;
If PadHasNoAnnularRing(Pad) Then
Exit;
If PadMatchesKnownTemplate(Pad) Then
Exit;
PadClass := ClassifyPad(Pad, TargetHole, TargetSize);
If (PadClass >= CLASS_03) And (PadClass <= CLASS_12) And
(Not PadIsReady(Pad, TargetHole, TargetSize)) Then
Begin
PCBServer.SendMessageToRobots(
Pad.I_ObjectAddress,
c_Broadcast,
PCBM_BeginModify,
c_NoEventData);
Try
Pad.HoleSize := TargetHole;
Pad.TopXSize := TargetSize;
Pad.TopYSize := TargetSize;
Pad.MidXSize := TargetSize;
Pad.MidYSize := TargetSize;
Pad.BotXSize := TargetSize;
Pad.BotYSize := TargetSize;
Finally
PCBServer.SendMessageToRobots(
Pad.I_ObjectAddress,
c_Broadcast,
PCBM_EndModify,
c_NoEventData);
End;
Result := True;
End;
End;
Function FindIsolationRule(Board : IPCB_Board;
RuleName : String) : IPCB_ClearanceConstraint;
Var
Iterator : IPCB_BoardIterator;
Rule : IPCB_Rule;
Begin
Result := Nil;
Iterator := Board.BoardIterator_Create;
Iterator.AddFilter_ObjectSet(MkSet(eRuleObject));
Iterator.AddFilter_LayerSet(AllLayers);
Iterator.AddFilter_Method(eProcessAll);
Try
Rule := Iterator.FirstPCBObject;
While Rule <> Nil Do
Begin
If (Rule.RuleKind = eRule_Clearance) And
(Rule.Name = RuleName) Then
Begin
Result := Rule;
Exit;
End;
Rule := Iterator.NextPCBObject;
End;
Finally
Board.BoardIterator_Destroy(Iterator);
End;
End;
Function ScopeIsAll(ScopeExpression : String) : Boolean;
Var
S : String;
Begin
S := UpperCase(Trim(ScopeExpression));
Result := (S = 'ALL') Or (S = '');
End;
Function FindDefaultClearance(Board : IPCB_Board;
Var DefaultGap : TCoord) : Boolean;
Var
Iterator : IPCB_BoardIterator;
Rule : IPCB_Rule;
ClearanceRule : IPCB_ClearanceConstraint;
Begin
Result := False;
DefaultGap := 0;
Iterator := Board.BoardIterator_Create;
Iterator.AddFilter_ObjectSet(MkSet(eRuleObject));
Iterator.AddFilter_LayerSet(AllLayers);
Iterator.AddFilter_Method(eProcessAll);
Try
{ Rule iterators follow the board's rule order. The first enabled
All/All clearance rule is therefore the active default rule. }
Rule := Iterator.FirstPCBObject;
While Rule <> Nil Do
Begin
If (Rule.RuleKind = eRule_Clearance) And
Rule.DRCEnabled And
ScopeIsAll(Rule.Scope1Expression) And
ScopeIsAll(Rule.Scope2Expression) Then
Begin
ClearanceRule := Rule;
DefaultGap := ClearanceRule.Gap;
Result := True;
Exit;
End;
Rule := Iterator.NextPCBObject;
End;
Finally
Board.BoardIterator_Destroy(Iterator);
End;
End;
Procedure RemoveIsolationRuleIfPresent(Board : IPCB_Board;
RuleName : String);
Var
Rule : IPCB_ClearanceConstraint;
Begin
Rule := FindIsolationRule(Board, RuleName);
If Rule <> Nil Then
Begin
Board.RemovePCBObject(Rule);
Inc(GRulesRemoved);
End;
End;
Function BuildIsolationScope(HoleMM, CopperMM : String) : String;
Begin
Result :=
'((IsVia And (AsMM(HoleSize) = ' + HoleMM + ') And ' +
'(AsMM(ViaDiameter) = ' + CopperMM + ')) Or ' +
'(IsPad And (PadIsPlated = ''True'') And ' +
'(AsMM(HoleSize) = ' + HoleMM + ') And ' +
'(AsMM(PadXSize_TopLayer) = ' + CopperMM + ') And ' +
'(AsMM(PadYSize_TopLayer) = ' + CopperMM + ')))';
End;
Procedure EnsureIsolationRule(Board : IPCB_Board;
RuleName : String;
HoleMM : String;
CopperMM : String;
IsolationGap : TCoord;
DefaultFound : Boolean;
DefaultGap : TCoord);
Var
Rule : IPCB_ClearanceConstraint;
Begin
If DefaultFound And (DefaultGap >= IsolationGap) Then
Begin
RemoveIsolationRuleIfPresent(Board, RuleName);
Inc(GRulesNotNeeded);
Exit;
End;
Rule := FindIsolationRule(Board, RuleName);
If Rule = Nil Then
Begin
Rule := PCBServer.PCBRuleFactory(eRule_Clearance);
PCBServer.SendMessageToRobots(
Rule.I_ObjectAddress,
c_Broadcast,
PCBM_BeginModify,
c_NoEventData);
Try
Rule.Name := RuleName;
Rule.Comment :=
'Rivet routing/polygon isolation. Pads and vias use normal clearance.';
Rule.DRCEnabled := True;
Rule.Scope1Expression := BuildIsolationScope(HoleMM, CopperMM);
Rule.Scope2Expression :=
'IsTrack Or IsArc Or IsFill Or IsRegion Or InPolygon';
Rule.Gap := IsolationGap;
Board.AddPCBObject(Rule);
Finally
PCBServer.SendMessageToRobots(
Rule.I_ObjectAddress,
c_Broadcast,
PCBM_EndModify,
c_NoEventData);
End;
Inc(GRulesCreated);
End
Else
Begin
PCBServer.SendMessageToRobots(
Rule.I_ObjectAddress,
c_Broadcast,
PCBM_BeginModify,
c_NoEventData);
Try
Rule.Comment :=
'Rivet routing/polygon isolation. Pads and vias use normal clearance.';
Rule.DRCEnabled := True;
Rule.Scope1Expression := BuildIsolationScope(HoleMM, CopperMM);
Rule.Scope2Expression :=
'IsTrack Or IsArc Or IsFill Or IsRegion Or InPolygon';
Rule.Gap := IsolationGap;
Finally
PCBServer.SendMessageToRobots(
Rule.I_ObjectAddress,
c_Broadcast,
PCBM_EndModify,
c_NoEventData);
End;
Inc(GRulesUpdated);
End;
End;
Procedure EnsureIsolationRules(Board : IPCB_Board);
Begin
GRulesCreated := 0;
GRulesUpdated := 0;
GRulesRemoved := 0;
GRulesNotNeeded := 0;
GDefaultRuleFound := FindDefaultClearance(Board, GDefaultClearance);
{ Overall isolation diameters are 2.2, 2.7 and 3.7 mm.
Gap is measured from the copper edge, hence (zone - copper) / 2. }
EnsureIsolationRule(Board, 'RIVET_03_RoutingIsolation',
'0.9', '1.7', MMsToCoord(0.25),
GDefaultRuleFound, GDefaultClearance);
EnsureIsolationRule(Board, 'RIVET_11_RoutingIsolation',
'1.3', '2.1', MMsToCoord(0.30),
GDefaultRuleFound, GDefaultClearance);
EnsureIsolationRule(Board, 'RIVET_GT11_RoutingIsolation',
'2.0', '2.8', MMsToCoord(0.45),
GDefaultRuleFound, GDefaultClearance);
End;
Function ApplyChanges(Board : IPCB_Board) : Integer;
Var
Iterator : IPCB_BoardIterator;
ComponentIterator : IPCB_BoardIterator;
GroupIterator : IPCB_GroupIterator;
Via : IPCB_Via;
Pad : IPCB_Pad;
Component : IPCB_Component;
Begin
Result := 0;
PCBServer.PreProcess;
Try
Iterator := Board.BoardIterator_Create;
Iterator.AddFilter_ObjectSet(MkSet(eViaObject));
Iterator.AddFilter_LayerSet(AllLayers);
Iterator.AddFilter_Method(eProcessAll);
Try
Via := Iterator.FirstPCBObject;
While Via <> Nil Do
Begin
If (Not Via.InComponent) And ApplyOneVia(Via) Then
Inc(Result);
Via := Iterator.NextPCBObject;
End;
Finally
Board.BoardIterator_Destroy(Iterator);
End;
{ Process free drilled pads. }
Iterator := Board.BoardIterator_Create;
Iterator.AddFilter_ObjectSet(MkSet(ePadObject));
Iterator.AddFilter_LayerSet(AllLayers);
Iterator.AddFilter_Method(eProcessAll);
Try
Pad := Iterator.FirstPCBObject;
While Pad <> Nil Do
Begin
If (Not Pad.InComponent) And ApplyOnePad(Pad) Then
Inc(Result);
Pad := Iterator.NextPCBObject;
End;
Finally
Board.BoardIterator_Destroy(Iterator);
End;
{ Process vias and drilled pads embedded in placed footprints. }
ComponentIterator := Board.BoardIterator_Create;
ComponentIterator.AddFilter_ObjectSet(MkSet(eComponentObject));
ComponentIterator.AddFilter_LayerSet(AllLayers);
ComponentIterator.AddFilter_Method(eProcessAll);
Try
Component := ComponentIterator.FirstPCBObject;
While Component <> Nil Do
Begin
GroupIterator := Component.GroupIterator_Create;
GroupIterator.AddFilter_ObjectSet(MkSet(eViaObject));
Try
Via := GroupIterator.FirstPCBObject;
While Via <> Nil Do
Begin
If ApplyOneVia(Via) Then
Inc(Result);
Via := GroupIterator.NextPCBObject;
End;
Finally
Component.GroupIterator_Destroy(GroupIterator);
End;
GroupIterator := Component.GroupIterator_Create;
GroupIterator.AddFilter_ObjectSet(MkSet(ePadObject));
Try
Pad := GroupIterator.FirstPCBObject;
While Pad <> Nil Do
Begin
If ApplyOnePad(Pad) Then
Inc(Result);
Pad := GroupIterator.NextPCBObject;
End;
Finally
Component.GroupIterator_Destroy(GroupIterator);
End;
Component := ComponentIterator.NextPCBObject;
End;
Finally
Board.BoardIterator_Destroy(ComponentIterator);
End;
EnsureIsolationRules(Board);
Finally
PCBServer.PostProcess;
End;
Client.SendMessage('PCB:Zoom', 'Action=Redraw', 255, Client.CurrentView);
End;
Procedure AnalyzeVias;
Var
Board : IPCB_Board;
Begin
Board := PCBServer.GetCurrentPCBBoard;
If Board = Nil Then
Begin
ShowMessage('Open and focus a PCB document first.');
Exit;
End;
AnalyzeBoard(Board);
ShowMessage(BuildSummary);
End;
Procedure ConvertViasToRivets;
Var
Board : IPCB_Board;
ChangedCount : Integer;
Prompt : String;
ResultMessage : String;
Begin
Board := PCBServer.GetCurrentPCBBoard;
If Board = Nil Then
Begin
ShowMessage('Open and focus a PCB document first.');
Exit;
End;
AnalyzeBoard(Board);
Prompt := BuildSummary + #13#10 + #13#10;
If ChangesCount = 0 Then
Prompt := Prompt + 'Object sizes are ready. Isolation rules will still be reconciled.' +
#13#10;
Prompt := Prompt +
'Press OK to modify the board and reconcile isolation rules,' +
#13#10 + 'or Cancel to stop.';
If MessageDlg(Prompt, mtConfirmation, mbOKCancel, 0) = mrCancel Then
Exit;
ChangedCount := ApplyChanges(Board);
ResultMessage :=
'Done. Modified vias/pads: ' + IntToStr(ChangedCount) +
#13#10 + 'Isolation rules created: ' + IntToStr(GRulesCreated) +
#13#10 + 'Isolation rules updated: ' + IntToStr(GRulesUpdated) +
#13#10 + 'Isolation rules removed: ' + IntToStr(GRulesRemoved) +
#13#10 + 'Groups covered by default clearance: ' +
IntToStr(GRulesNotNeeded);
If GDefaultRuleFound Then
ResultMessage := ResultMessage + #13#10 +
'Default clearance: ' + FloatToStr(CoordToMMs(GDefaultClearance)) + ' mm'
Else
ResultMessage := ResultMessage + #13#10 +
'Default All/All clearance rule was not found.';
ResultMessage := ResultMessage + #13#10 +
'Use Undo to revert the complete operation.';
ShowMessage(ResultMessage);
End;

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