commit de03c67f911ff089c11676d1f20bcf52e3594ace Author: Razvalyaev Date: Thu May 14 18:29:48 2026 +0300 Переструктурировано все. Отедльный проект под плату для ламп и отдельный проект под материнскую плату diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..6c871e5 --- /dev/null +++ b/.gitignore @@ -0,0 +1,8 @@ +/Lamp_board/__Previews/ +/Lamp_board/History/ +/Lamp_board/Project Logs for Lamp_board/ +/Lamp_board/Project Outputs for Lamp_board/ +/Lamp_motherboard/__Previews/ +/Lamp_motherboard/History/ +/Lamp_motherboard/Project Logs for Lamp_motherboard/ +/Lamp_motherboard/Project Outputs for Lamp_motherboard/ diff --git a/Lamp_board/Lamp.SchDoc b/Lamp_board/Lamp.SchDoc new file mode 100644 index 0000000..8bf48df Binary files /dev/null and b/Lamp_board/Lamp.SchDoc differ diff --git a/Lamp_board/Lamps_board.PcbDoc b/Lamp_board/Lamps_board.PcbDoc new file mode 100644 index 0000000..46fdb61 Binary files /dev/null and b/Lamp_board/Lamps_board.PcbDoc differ diff --git a/Lamp_board/Lamps_board.PrjPcb b/Lamp_board/Lamps_board.PrjPcb new file mode 100644 index 0000000..48a9662 --- /dev/null +++ b/Lamp_board/Lamps_board.PrjPcb @@ -0,0 +1,1327 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Sources +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= +IncludeDesignInRelease=0 + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Document1] +DocumentPath=Lamps_board.PcbDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=QXMBNEKL + +[Document2] +DocumentPath=Lamp.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=0 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=QWVATKCH + +[Document3] +DocumentPath=SegCtrl.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=2 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=UJSGQANR + +[Document4] +DocumentPath=Lamps_board.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=LXTRFNTD + +[Configuration1] +Name=Sources +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +Variant=[No Variations] +OutputJobsCount=0 +ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2 +ConfigurationType=Source + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=Adobe PDF +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=CadnetixNetlist +OutputName1=Cadnetix Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=CalayNetlist +OutputName2=Calay Netlist +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=EDIF +OutputName3=EDIF for PCB +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=EESofNetlist +OutputName4=EESof Netlist +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +OutputType5=IntergraphNetlist +OutputName5=Intergraph Netlist +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 +OutputType6=MentorBoardStationNetlist +OutputName6=Mentor BoardStation Netlist +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=MultiWire +OutputName7=MultiWire +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=OrCadPCB2Netlist +OutputName8=Orcad/PCB2 Netlist +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=PADSNetlist +OutputName9=PADS ASCII Netlist +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Pcad +OutputName10=Pcad for PCB +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=PCADNetlist +OutputName11=PCAD Netlist +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 +OutputType12=PCADnltNetlist +OutputName12=PCADnlt Netlist +OutputDocumentPath12= +OutputVariantName12= +OutputDefault12=0 +OutputType13=Protel2Netlist +OutputName13=Protel2 Netlist +OutputDocumentPath13= +OutputVariantName13= +OutputDefault13=0 +OutputType14=ProtelNetlist +OutputName14=Protel +OutputDocumentPath14= +OutputVariantName14= +OutputDefault14=0 +OutputType15=RacalNetlist +OutputName15=Racal Netlist +OutputDocumentPath15= +OutputVariantName15= +OutputDefault15=0 +OutputType16=RINFNetlist +OutputName16=RINF Netlist +OutputDocumentPath16= +OutputVariantName16= +OutputDefault16=0 +OutputType17=SciCardsNetlist +OutputName17=SciCards Netlist +OutputDocumentPath17= +OutputVariantName17= +OutputDefault17=0 +OutputType18=TangoNetlist +OutputName18=Tango Netlist +OutputDocumentPath18= +OutputVariantName18= +OutputDefault18=0 +OutputType19=TelesisNetlist +OutputName19=Telesis Netlist +OutputDocumentPath19= +OutputVariantName19= +OutputDefault19=0 +OutputType20=WireListNetlist +OutputName20=WireList Netlist +OutputDocumentPath20= +OutputVariantName20= +OutputDefault20=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=Adobe PDF +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=Virtual Printer +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Composite +OutputName1=Composite Drawing +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 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+Configuration1_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|NumberOfDecimals=4|NumberOfUnits=4|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Metric|ZeroesMode=SuppressTrailingZeroes +OutputType2=Mask +OutputName2=Solder/Paste Mask Prints +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType3=IPC2581 +OutputName3=IPC-2581 Files +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=Test Points +OutputName4=Test Point Report +OutputDocumentPath4= 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Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 + +[SmartPDF] +PageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + diff --git a/Lamp_board/Lamps_board.PrjPcbStructure b/Lamp_board/Lamps_board.PrjPcbStructure new file mode 100644 index 0000000..0a8cf99 --- /dev/null +++ b/Lamp_board/Lamps_board.PrjPcbStructure @@ -0,0 +1,14 @@ +Record=TopLevelDocument|FileName=Lamps_board.SchDoc +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=Lamp_HOUR_H|SchDesignator=Lamp_HOUR_H|FileName=Lamp.SchDoc|SymbolType=Normal|RawFileName=Lamp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=Lamp_HOUR_L|SchDesignator=Lamp_HOUR_L|FileName=Lamp.SchDoc|SymbolType=Normal|RawFileName=Lamp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=Lamp_MIN_H|SchDesignator=Lamp_MIN_H|FileName=Lamp.SchDoc|SymbolType=Normal|RawFileName=Lamp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=Lamp_MIN_L|SchDesignator=Lamp_MIN_L|FileName=Lamp.SchDoc|SymbolType=Normal|RawFileName=Lamp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=Lamp_SEC_H|SchDesignator=Lamp_SEC_H|FileName=Lamp.SchDoc|SymbolType=Normal|RawFileName=Lamp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=Lamp_SEC_L|SchDesignator=Lamp_SEC_L|FileName=Lamp.SchDoc|SymbolType=Normal|RawFileName=Lamp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=SegCtrl_A|SchDesignator=SegCtrl_A|FileName=SegCtrl.SchDoc|SymbolType=Normal|RawFileName=SegCtrl.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=SegCtrl_B|SchDesignator=SegCtrl_B|FileName=SegCtrl.SchDoc|SymbolType=Normal|RawFileName=SegCtrl.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=SegCtrl_C|SchDesignator=SegCtrl_C|FileName=SegCtrl.SchDoc|SymbolType=Normal|RawFileName=SegCtrl.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=SegCtrl_D|SchDesignator=SegCtrl_D|FileName=SegCtrl.SchDoc|SymbolType=Normal|RawFileName=SegCtrl.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=SegCtrl_E|SchDesignator=SegCtrl_E|FileName=SegCtrl.SchDoc|SymbolType=Normal|RawFileName=SegCtrl.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=SegCtrl_F|SchDesignator=SegCtrl_F|FileName=SegCtrl.SchDoc|SymbolType=Normal|RawFileName=SegCtrl.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=Lamps_board.SchDoc|Designator=SegCtrl_G|SchDesignator=SegCtrl_G|FileName=SegCtrl.SchDoc|SymbolType=Normal|RawFileName=SegCtrl.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= diff --git a/Lamp_board/Lamps_board.SchDoc b/Lamp_board/Lamps_board.SchDoc new file mode 100644 index 0000000..4b8f51d Binary files /dev/null and b/Lamp_board/Lamps_board.SchDoc differ diff --git a/Lamp_board/SegCtrl.SchDoc b/Lamp_board/SegCtrl.SchDoc new file mode 100644 index 0000000..26edf72 Binary files /dev/null and b/Lamp_board/SegCtrl.SchDoc differ diff --git a/Lamp_motherboard/Lamp_motherboard.PrjPcb b/Lamp_motherboard/Lamp_motherboard.PrjPcb new file mode 100644 index 0000000..1bf2bd9 --- /dev/null +++ b/Lamp_motherboard/Lamp_motherboard.PrjPcb @@ -0,0 +1,1072 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= 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+PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=Adobe PDF +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=BOM_Violations +OutputName1=BOM Checks Report +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Component states check +OutputName2=Server's components states check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=Configuration compliance +OutputName3=Environment configuration compliance check +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +OutputType4=Design Rules Check +OutputName4=Design Rules Check +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9 +OutputType5=Differences Report +OutputName5=Differences Report +OutputDocumentPath5= +OutputVariantName5= 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PARASOLID +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=MBAExportSTEP +OutputName8=Export STEP +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 +OutputType9=Save As/Export PCB +OutputName9=Save As/Export PCB +OutputDocumentPath9= +OutputVariantName9= +OutputDefault9=0 +OutputType10=Save As/Export Schematic +OutputName10=Save As/Export Schematic +OutputDocumentPath10= +OutputVariantName10= +OutputDefault10=0 +OutputType11=Specctra Design PCB +OutputName11=Specctra Design PCB +OutputDocumentPath11= +OutputVariantName11= +OutputDefault11=0 + +[OutputGroup10] +Name=PostProcess Outputs +Description= +TargetPrinter=Adobe PDF +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Copy Files +OutputName1=Copy Files +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 + +[Modification Levels] +Type1=1 +Type2=1 +Type3=1 +Type4=1 +Type5=1 +Type6=1 +Type7=1 +Type8=1 +Type9=1 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