From 1b48ea179d8485cdb2a4e55467d0fd8ba4584505 Mon Sep 17 00:00:00 2001 From: sokolovstanislav Date: Wed, 3 Dec 2025 15:51:27 +0300 Subject: [PATCH] =?UTF-8?q?=D0=90=D0=BD=D0=B0=D0=BB=D0=B8=D0=B7=D0=B0?= =?UTF-8?q?=D1=82=D0=BE=D1=80=20=D0=B2=D1=85=D0=BE=D0=B4=D0=BD=D1=8B=D1=85?= =?UTF-8?q?=20=D1=81=D0=B8=D0=B3=D0=BD=D0=B0=D0=BB=D0=BE=D0=B2=20=D1=81=20?= =?UTF-8?q?=D1=84=D0=BE=D1=80=D0=BC=D0=B8=D1=80=D0=BE=D0=B2=D0=B0=D0=BD?= =?UTF-8?q?=D0=B8=D0=B5=D0=BC=20=D0=BF=D1=80=D0=B5=D1=80=D1=8B=D0=B2=D0=B0?= =?UTF-8?q?=D0=BD=D0=B8=D1=8F=20=D0=B8=20=D0=B7=D0=B0=D1=89=D0=B5=D0=BB?= =?UTF-8?q?=D0=BA=D0=BE=D0=B9=20=D0=B2=D1=85=D0=BE=D0=B4=D0=BD=D0=BE=D0=B3?= =?UTF-8?q?=D0=BE=20=D0=B2=D0=B5=D0=BA=D1=82=D0=BE=D1=80=D0=B0.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- IP_AXI_Inputs_1.0/bd/bd.tcl | 86 ++ IP_AXI_Inputs_1.0/component.xml | 910 ++++++++++++++++++ .../IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.mdd | 10 + .../IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.tcl | 5 + .../IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.c | 6 + .../IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.h | 79 ++ .../src/IP_AXI_Inputs_selftest.c | 60 ++ .../drivers/IP_AXI_Inputs_v1_0/src/Makefile | 26 + .../bfm_design/IP_AXI_Inputs_v1_0_tb.sv | 197 ++++ .../example_designs/bfm_design/design.tcl | 88 ++ .../IP_AXI_Inputs_v1_0_hw_test.tcl | 45 + .../debug_hw_design/design.tcl | 118 +++ IP_AXI_Inputs_1.0/hdl/IP_AXI_Inputs_v1_0.vhd | 125 +++ .../hdl/IP_AXI_Inputs_v1_0_S00_AXI.vhd | 420 ++++++++ IP_AXI_Inputs_1.0/xgui/IP_AXI_Inputs_v1_0.tcl | 62 ++ 15 files changed, 2237 insertions(+) create mode 100644 IP_AXI_Inputs_1.0/bd/bd.tcl create mode 100644 IP_AXI_Inputs_1.0/component.xml create mode 100644 IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.mdd create mode 100644 IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.tcl create mode 100644 IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.c create mode 100644 IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.h create mode 100644 IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs_selftest.c create mode 100644 IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/Makefile create mode 100644 IP_AXI_Inputs_1.0/example_designs/bfm_design/IP_AXI_Inputs_v1_0_tb.sv create mode 100644 IP_AXI_Inputs_1.0/example_designs/bfm_design/design.tcl create mode 100644 IP_AXI_Inputs_1.0/example_designs/debug_hw_design/IP_AXI_Inputs_v1_0_hw_test.tcl create mode 100644 IP_AXI_Inputs_1.0/example_designs/debug_hw_design/design.tcl create mode 100644 IP_AXI_Inputs_1.0/hdl/IP_AXI_Inputs_v1_0.vhd create mode 100644 IP_AXI_Inputs_1.0/hdl/IP_AXI_Inputs_v1_0_S00_AXI.vhd create mode 100644 IP_AXI_Inputs_1.0/xgui/IP_AXI_Inputs_v1_0.tcl diff --git a/IP_AXI_Inputs_1.0/bd/bd.tcl b/IP_AXI_Inputs_1.0/bd/bd.tcl new file mode 100644 index 0000000..4804aeb --- /dev/null +++ b/IP_AXI_Inputs_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/IP_AXI_Inputs_1.0/component.xml b/IP_AXI_Inputs_1.0/component.xml new file mode 100644 index 0000000..ac77b20 --- /dev/null +++ b/IP_AXI_Inputs_1.0/component.xml @@ -0,0 +1,910 @@ + + + setcorp + user + IP_AXI_Inputs + 1.0 + + + S00_AXI + + + + + + + + + AWADDR + + + s00_axi_awaddr + + + + + AWPROT + + + s00_axi_awprot + + + + + AWVALID + + + s00_axi_awvalid + + + + + AWREADY + + + s00_axi_awready + + + + + WDATA + + + s00_axi_wdata + + + + + WSTRB + + + s00_axi_wstrb + + + + + WVALID + + + s00_axi_wvalid + + + + + WREADY + + + s00_axi_wready + + + + + BRESP + + + s00_axi_bresp + + + + + BVALID + + + s00_axi_bvalid + + + + + BREADY + + + s00_axi_bready + + + + + ARADDR + + + s00_axi_araddr + + + + + ARPROT + + + s00_axi_arprot + + + + + ARVALID + + + s00_axi_arvalid + + + + + ARREADY + + + s00_axi_arready + + + + + RDATA + + + s00_axi_rdata + + + + + RRESP + + + s00_axi_rresp + + + + + RVALID + + + s00_axi_rvalid + + + + + RREADY + + + s00_axi_rready + + + + + + WIZ_DATA_WIDTH + 32 + + + WIZ_NUM_REG + 4 + + + SUPPORTS_NARROW_BURST + 0 + + + + + S00_AXI_RST + + + + + + + RST + + + s00_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S00_AXI_CLK + + + + + + + CLK + + + s00_axi_aclk + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + ASSOCIATED_RESET + s00_axi_aresetn + + + + + interrupt + + + + + + + INTERRUPT + + + interrupt + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + + S00_AXI + + S00_AXI_reg + 0 + 4096 + 32 + register + + + OFFSET_BASE_PARAM + C_S00_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S00_AXI_HIGHADDR + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + IP_AXI_Inputs_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 72615f2e + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + IP_AXI_Inputs_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 72615f2e + + + + + xilinx_softwaredriver + Software Driver + :vivado.xilinx.com:sw.driver + + xilinx_softwaredriver_view_fileset + + + + viewChecksum + 1d8bf0ce + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + dda4df14 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + data + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + interrupt + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x0 + + + + + s00_axi_awaddr + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_araddr + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_arvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_arready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_S00_AXI_DATA_WIDTH + C S00 AXI DATA WIDTH + Width of S_AXI data bus + 32 + + + C_S00_AXI_ADDR_WIDTH + C S00 AXI ADDR WIDTH + Width of S_AXI address bus + 4 + + + + + + choice_list_6fc15197 + 32 + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_9ca20931 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + + + choice_pairs_ce1226b1 + 1 + 0 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/IP_AXI_Inputs_v1_0_S00_AXI.vhd + vhdlSource + + + hdl/IP_AXI_Inputs_v1_0.vhd + vhdlSource + CHECKSUM_f1f0aa53 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/IP_AXI_Inputs_v1_0_S00_AXI.vhd + vhdlSource + + + hdl/IP_AXI_Inputs_v1_0.vhd + vhdlSource + + + + xilinx_softwaredriver_view_fileset + + drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.mdd + mdd + driver_mdd + + + drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.tcl + tclSource + driver_tcl + + + drivers/IP_AXI_Inputs_v1_0/src/Makefile + driver_src + + + drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.h + cSource + driver_src + + + drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.c + cSource + driver_src + + + drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs_selftest.c + cSource + driver_src + + + + xilinx_xpgui_view_fileset + + xgui/IP_AXI_Inputs_v1_0.tcl + tclSource + CHECKSUM_dda4df14 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + My new AXI IP + + + C_S00_AXI_DATA_WIDTH + C S00 AXI DATA WIDTH + Width of S_AXI data bus + 32 + + + + false + + + + + + C_S00_AXI_ADDR_WIDTH + C S00 AXI ADDR WIDTH + Width of S_AXI address bus + 4 + + + + false + + + + + + C_S00_AXI_BASEADDR + C S00 AXI BASEADDR + 0xFFFFFFFF + + + + false + + + + + + C_S00_AXI_HIGHADDR + C S00 AXI HIGHADDR + 0x00000000 + + + + false + + + + + + Component_Name + IP_AXI_Inputs_v1_0 + + + + + + zynq + + + AXI_Peripheral + + IP_AXI_Inputs_v1.0 + 2 + 2025-12-03T12:29:19Z + + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + d:/GITEA/GitHub/ES/IP_cores/IP_AXI_Inputs_1.0 + + + + 2019.1 + + + + + + + + + diff --git a/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.mdd b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.mdd new file mode 100644 index 0000000..64ea3ec --- /dev/null +++ b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.mdd @@ -0,0 +1,10 @@ + + +OPTION psf_version = 2.1; + +BEGIN DRIVER IP_AXI_Inputs + OPTION supported_peripherals = (IP_AXI_Inputs); + OPTION copyfiles = all; + OPTION VERSION = 1.0; + OPTION NAME = IP_AXI_Inputs; +END DRIVER diff --git a/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.tcl b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.tcl new file mode 100644 index 0000000..a8617ca --- /dev/null +++ b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/data/IP_AXI_Inputs.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "IP_AXI_Inputs" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.c b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.c new file mode 100644 index 0000000..03630ec --- /dev/null +++ b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.c @@ -0,0 +1,6 @@ + + +/***************************** Include Files *******************************/ +#include "IP_AXI_Inputs.h" + +/************************** Function Definitions ***************************/ diff --git a/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.h b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.h new file mode 100644 index 0000000..02c514b --- /dev/null +++ b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs.h @@ -0,0 +1,79 @@ + +#ifndef IP_AXI_INPUTS_H +#define IP_AXI_INPUTS_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define IP_AXI_INPUTS_S00_AXI_SLV_REG0_OFFSET 0 +#define IP_AXI_INPUTS_S00_AXI_SLV_REG1_OFFSET 4 +#define IP_AXI_INPUTS_S00_AXI_SLV_REG2_OFFSET 8 +#define IP_AXI_INPUTS_S00_AXI_SLV_REG3_OFFSET 12 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a IP_AXI_INPUTS register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the IP_AXI_INPUTSdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void IP_AXI_INPUTS_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define IP_AXI_INPUTS_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a IP_AXI_INPUTS register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the IP_AXI_INPUTS device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 IP_AXI_INPUTS_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define IP_AXI_INPUTS_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the IP_AXI_INPUTS instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus IP_AXI_INPUTS_Reg_SelfTest(void * baseaddr_p); + +#endif // IP_AXI_INPUTS_H diff --git a/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs_selftest.c b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs_selftest.c new file mode 100644 index 0000000..9d3891a --- /dev/null +++ b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/IP_AXI_Inputs_selftest.c @@ -0,0 +1,60 @@ + +/***************************** Include Files *******************************/ +#include "IP_AXI_Inputs.h" +#include "xparameters.h" +#include "stdio.h" +#include "xil_io.h" + +/************************** Constant Definitions ***************************/ +#define READ_WRITE_MUL_FACTOR 0x10 + +/************************** Function Definitions ***************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the IP_AXI_INPUTSinstance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus IP_AXI_INPUTS_Reg_SelfTest(void * baseaddr_p) +{ + u32 baseaddr; + int write_loop_index; + int read_loop_index; + int Index; + + baseaddr = (u32) baseaddr_p; + + xil_printf("******************************\n\r"); + xil_printf("* User Peripheral Self Test\n\r"); + xil_printf("******************************\n\n\r"); + + /* + * Write to user logic slave module register(s) and read back + */ + xil_printf("User logic slave module test...\n\r"); + + for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) + IP_AXI_INPUTS_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); + for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) + if ( IP_AXI_INPUTS_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ + xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); + return XST_FAILURE; + } + + xil_printf(" - slave register write/read passed\n\n\r"); + + return XST_SUCCESS; +} diff --git a/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/Makefile b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/Makefile new file mode 100644 index 0000000..2c7d1eb --- /dev/null +++ b/IP_AXI_Inputs_1.0/drivers/IP_AXI_Inputs_v1_0/src/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling IP_AXI_Inputs..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/IP_AXI_Inputs_1.0/example_designs/bfm_design/IP_AXI_Inputs_v1_0_tb.sv b/IP_AXI_Inputs_1.0/example_designs/bfm_design/IP_AXI_Inputs_v1_0_tb.sv new file mode 100644 index 0000000..262d1fc --- /dev/null +++ b/IP_AXI_Inputs_1.0/example_designs/bfm_design/IP_AXI_Inputs_v1_0_tb.sv @@ -0,0 +1,197 @@ + +`timescale 1ns / 1ps +`include "IP_AXI_Inputs_v1_0_tb_include.svh" + +import axi_vip_pkg::*; +import IP_AXI_Inputs_v1_0_bfm_1_master_0_0_pkg::*; + +module IP_AXI_Inputs_v1_0_tb(); + + +xil_axi_uint error_cnt = 0; +xil_axi_uint comparison_cnt = 0; +axi_transaction wr_transaction; +axi_transaction rd_transaction; +axi_monitor_transaction mst_monitor_transaction; +axi_monitor_transaction master_moniter_transaction_queue[$]; +xil_axi_uint master_moniter_transaction_queue_size =0; +axi_monitor_transaction mst_scb_transaction; +axi_monitor_transaction passthrough_monitor_transaction; +axi_monitor_transaction passthrough_master_moniter_transaction_queue[$]; +xil_axi_uint passthrough_master_moniter_transaction_queue_size =0; +axi_monitor_transaction passthrough_mst_scb_transaction; +axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$]; +xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0; +axi_monitor_transaction passthrough_slv_scb_transaction; +axi_monitor_transaction slv_monitor_transaction; +axi_monitor_transaction slave_moniter_transaction_queue[$]; +xil_axi_uint slave_moniter_transaction_queue_size =0; +axi_monitor_transaction slv_scb_transaction; +xil_axi_uint mst_agent_verbosity = 0; +xil_axi_uint slv_agent_verbosity = 0; +xil_axi_uint passthrough_agent_verbosity = 0; +bit clock; +bit reset; +integer result_slave; +bit [31:0] S00_AXI_test_data[3:0]; + localparam LC_AXI_BURST_LENGTH = 8; + localparam LC_AXI_DATA_WIDTH = 32; +task automatic COMPARE_DATA; + input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]expected; + input [(LC_AXI_BURST_LENGTH * LC_AXI_DATA_WIDTH)-1:0]actual; + begin + if (expected === 'hx || actual === 'hx) begin + $display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); + result_slave = 0; $stop; + end + if (actual != expected) begin + $display("TESTBENCH ERROR! Data expected is not equal to actual.", " expected = 0x%h",expected, " actual = 0x%h",actual); + result_slave = 0; + $stop; + end + else + begin + $display("TESTBENCH Passed! Data expected is equal to actual.", + " expected = 0x%h",expected, " actual = 0x%h",actual); + end + end +endtask +integer i; +integer j; +xil_axi_uint trans_cnt_before_switch = 48; +xil_axi_uint passthrough_cmd_switch_cnt = 0; +event passthrough_mastermode_start_event; +event passthrough_mastermode_end_event; +event passthrough_slavemode_end_event; +xil_axi_uint mtestID; +xil_axi_ulong mtestADDR; +xil_axi_len_t mtestBurstLength; +xil_axi_size_t mtestDataSize; +xil_axi_burst_t mtestBurstType; +xil_axi_lock_t mtestLOCK; +xil_axi_cache_t mtestCacheType = 0; +xil_axi_prot_t mtestProtectionType = 3'b000; +xil_axi_region_t mtestRegion = 4'b000; +xil_axi_qos_t mtestQOS = 4'b000; +xil_axi_data_beat dbeat; +xil_axi_data_beat [255:0] mtestWUSER; +xil_axi_data_beat mtestAWUSER = 'h0; +xil_axi_data_beat mtestARUSER = 0; +xil_axi_data_beat [255:0] mtestRUSER; +xil_axi_uint mtestBUSER = 0; +xil_axi_resp_t mtestBresp; +xil_axi_resp_t[255:0] mtestRresp; +bit [63:0] mtestWDataL; +bit [63:0] mtestRDataL; +axi_transaction pss_wr_transaction; +axi_transaction pss_rd_transaction; +axi_transaction reactive_transaction; +axi_transaction rd_payload_transaction; +axi_transaction wr_rand; +axi_transaction rd_rand; +axi_transaction wr_reactive; +axi_transaction rd_reactive; +axi_transaction wr_reactive2; +axi_transaction rd_reactive2; +axi_ready_gen bready_gen; +axi_ready_gen rready_gen; +axi_ready_gen awready_gen; +axi_ready_gen wready_gen; +axi_ready_gen arready_gen; +axi_ready_gen bready_gen2; +axi_ready_gen rready_gen2; +axi_ready_gen awready_gen2; +axi_ready_gen wready_gen2; +axi_ready_gen arready_gen2; +xil_axi_payload_byte data_mem[xil_axi_ulong]; +IP_AXI_Inputs_v1_0_bfm_1_master_0_0_mst_t mst_agent_0; + + `BD_WRAPPER DUT( + .ARESETN(reset), + .ACLK(clock) + ); + +initial begin + mst_agent_0 = new("master vip agent",DUT.`BD_INST_NAME.master_0.inst.IF);//ms + mst_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE); + mst_agent_0.set_agent_tag("Master VIP"); + mst_agent_0.set_verbosity(mst_agent_verbosity); + mst_agent_0.start_master(); + $timeformat (-12, 1, " ps", 1); + end + initial begin + reset <= 1'b0; + #200ns; + reset <= 1'b1; + repeat (5) @(negedge clock); + end + always #5 clock <= ~clock; + initial begin + S_AXI_TEST ( ); + + #1ns; + $finish; + end +task automatic S_AXI_TEST; +begin +#1; + $display("Sequential write transfers example similar to AXI BFM WRITE_BURST method starts"); + mtestID = 0; + mtestADDR = 64'h00000000; + mtestBurstLength = 0; + mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); + mtestBurstType = XIL_AXI_BURST_TYPE_INCR; + mtestLOCK = XIL_AXI_ALOCK_NOLOCK; + mtestCacheType = 0; + mtestProtectionType = 0; + mtestRegion = 0; + mtestQOS = 0; + result_slave = 1; + mtestWDataL[31:0] = 32'h00000001; + for(int i = 0; i < 4;i++) begin + S00_AXI_test_data[i] <= mtestWDataL[31:0]; + mst_agent_0.AXI4LITE_WRITE_BURST( + mtestADDR, + mtestProtectionType, + mtestWDataL, + mtestBresp + ); + mtestWDataL[31:0] = mtestWDataL[31:0] + 1; + mtestADDR = mtestADDR + 64'h4; + end + $display("Sequential write transfers example similar to AXI BFM WRITE_BURST method completes"); + $display("Sequential read transfers example similar to AXI BFM READ_BURST method starts"); + mtestID = 0; + mtestADDR = 64'h00000000; + mtestBurstLength = 0; + mtestDataSize = xil_axi_size_t'(xil_clog2(32/8)); + mtestBurstType = XIL_AXI_BURST_TYPE_INCR; + mtestLOCK = XIL_AXI_ALOCK_NOLOCK; + mtestCacheType = 0; + mtestProtectionType = 0; + mtestRegion = 0; + mtestQOS = 0; + for(int i = 0; i < 4;i++) begin + mst_agent_0.AXI4LITE_READ_BURST( + mtestADDR, + mtestProtectionType, + mtestRDataL, + mtestRresp + ); + mtestADDR = mtestADDR + 64'h4; + COMPARE_DATA(S00_AXI_test_data[i],mtestRDataL); + end + $display("Sequential read transfers example similar to AXI BFM READ_BURST method completes"); + $display("Sequential read transfers example similar to AXI VIP READ_BURST method completes"); + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); + if ( result_slave ) begin + $display("PTGEN_TEST: PASSED!"); + end else begin + $display("PTGEN_TEST: FAILED!"); + end + $display("---------------------------------------------------------"); + end +endtask + +endmodule diff --git a/IP_AXI_Inputs_1.0/example_designs/bfm_design/design.tcl b/IP_AXI_Inputs_1.0/example_designs/bfm_design/design.tcl new file mode 100644 index 0000000..de1c4bc --- /dev/null +++ b/IP_AXI_Inputs_1.0/example_designs/bfm_design/design.tcl @@ -0,0 +1,88 @@ +proc create_ipi_design { offsetfile design_name } { + create_bd_design $design_name + open_bd_design $design_name + + # Create Clock and Reset Ports + set ACLK [ create_bd_port -dir I -type clk ACLK ] + set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK + set ARESETN [ create_bd_port -dir I -type rst ARESETN ] + set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN + set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK + + # Create instance: IP_AXI_Inputs_0, and set properties + set IP_AXI_Inputs_0 [ create_bd_cell -type ip -vlnv setcorp:user:IP_AXI_Inputs:1.0 IP_AXI_Inputs_0] + + # Create instance: master_0, and set properties + set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0] + set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0 + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins IP_AXI_Inputs_0/S00_AXI] + + # Create port connections + connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins IP_AXI_Inputs_0/S00_AXI_ACLK] + connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins IP_AXI_Inputs_0/S00_AXI_ARESETN] +set_property target_simulator XSim [current_project] +set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1] + + # Auto assign address + assign_bd_address + + # Copy all address to interface_address.vh file + set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/IP_AXI_Inputs_v1_0_tb_include.svh" + set fp [open $offset_file "w"] + puts $fp "`ifndef IP_AXI_Inputs_v1_0_tb_include_vh_" + puts $fp "`define IP_AXI_Inputs_v1_0_tb_include_vh_\n" + puts $fp "//Configuration current bd names" + puts $fp "`define BD_NAME ${design_name}" + puts $fp "`define BD_INST_NAME ${design_name}_i" + puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" + puts $fp "//Configuration address parameters" + + puts $fp "`endif" + close $fp +} + +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores setcorp:user:IP_AXI_Inputs:1.0]]]] +set test_bench_file ${ip_path}/example_designs/bfm_design/IP_AXI_Inputs_v1_0_tb.sv +set interface_address_vh_file "" + +# Set IP Repository and Update IP Catalogue +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "IP_AXI_Inputs_v1_0_bfm_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +create_ipi_design interface_address_vh_file ${design_name} +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +set_property SOURCE_SET sources_1 [get_filesets sim_1] +import_files -fileset sim_1 -norecurse -force $test_bench_file +remove_files -quiet -fileset sim_1 IP_AXI_Inputs_v1_0_tb_include.vh +import_files -fileset sim_1 -norecurse -force $interface_address_vh_file +set_property top IP_AXI_Inputs_v1_0_tb [get_filesets sim_1] +set_property top_lib {} [get_filesets sim_1] +set_property top_file {} [get_filesets sim_1] +launch_simulation -simset sim_1 -mode behavioral diff --git a/IP_AXI_Inputs_1.0/example_designs/debug_hw_design/IP_AXI_Inputs_v1_0_hw_test.tcl b/IP_AXI_Inputs_1.0/example_designs/debug_hw_design/IP_AXI_Inputs_v1_0_hw_test.tcl new file mode 100644 index 0000000..5555b9c --- /dev/null +++ b/IP_AXI_Inputs_1.0/example_designs/debug_hw_design/IP_AXI_Inputs_v1_0_hw_test.tcl @@ -0,0 +1,45 @@ +# Runtime Tcl commands to interact with - IP_AXI_Inputs_v1_0 + +# Sourcing design address info tcl +set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd +source ${bd_path}/IP_AXI_Inputs_v1_0_include.tcl + +# jtag axi master interface hardware name, change as per your design. +set jtag_axi_master hw_axi_1 +set ec 0 + +# hw test script +# Delete all previous axis transactions +if { [llength [get_hw_axi_txns -quiet]] } { + delete_hw_axi_txn [get_hw_axi_txns -quiet] +} + + +# Test all lite slaves. +set wdata_1 abcd1234 + +# Test: S00_AXI +# Create a write transaction at s00_axi_addr address +create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1 +# Create a read transaction at s00_axi_addr address +create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr +# Initiate transactions +run_hw_axi r_s00_axi_addr +run_hw_axi w_s00_axi_addr +run_hw_axi r_s00_axi_addr +set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]] +# Compare read data +if { $rdata_tmp == $wdata_1 } { + puts "Data comparison test pass for - S00_AXI" +} else { + puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp" + inc ec +} + +# Check error flag +if { $ec == 0 } { + puts "PTGEN_TEST: PASSED!" +} else { + puts "PTGEN_TEST: FAILED!" +} + diff --git a/IP_AXI_Inputs_1.0/example_designs/debug_hw_design/design.tcl b/IP_AXI_Inputs_1.0/example_designs/debug_hw_design/design.tcl new file mode 100644 index 0000000..388104d --- /dev/null +++ b/IP_AXI_Inputs_1.0/example_designs/debug_hw_design/design.tcl @@ -0,0 +1,118 @@ + +proc create_ipi_design { offsetfile design_name } { + + create_bd_design $design_name + open_bd_design $design_name + + # Create and configure Clock/Reset + create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 + create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 + + #Constraints will be provided manually while pin planning. + create_bd_port -dir I -type rst reset_rtl + set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] + set external_reset_port reset_rtl + create_bd_port -dir I -type clk clock_rtl + connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] + set external_clock_port clock_rtl + + #Avoid IPI DRC, make clock port synchronous to reset + if { $external_clock_port ne "" && $external_reset_port ne "" } { + set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] + } + + # Connect other sys_reset pins + connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] + + # Create instance: IP_AXI_Inputs_0, and set properties + set IP_AXI_Inputs_0 [ create_bd_cell -type ip -vlnv setcorp:user:IP_AXI_Inputs:1.0 IP_AXI_Inputs_0 ] + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] + set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] + connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Create instance: axi_peri_interconnect, and set properties + set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] + connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] + set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] + + set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Connect all clock & reset of IP_AXI_Inputs_0 slave interfaces.. + connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins IP_AXI_Inputs_0/S00_AXI] + connect_bd_net [get_bd_pins IP_AXI_Inputs_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins IP_AXI_Inputs_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + + # Auto assign address + assign_bd_address + + # Copy all address to IP_AXI_Inputs_v1_0_include.tcl file + set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/IP_AXI_Inputs_v1_0_include.tcl" + set fp [open $offset_file "w"] + puts $fp "# Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_IP_AXI_Inputs_0_S00_AXI_* ]] + puts $fp "set s00_axi_addr ${offset}" + + close $fp +} + +# Set IP Repository and Update IP Catalogue +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores setcorp:user:IP_AXI_Inputs:1.0]]]] +set hw_test_file ${ip_path}/example_designs/debug_hw_design/IP_AXI_Inputs_v1_0_hw_test.tcl + +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "IP_AXI_Inputs_v1_0_hw_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +set intf_address_include_file "" +create_ipi_design intf_address_include_file ${design_name} +save_bd_design +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +puts "-------------------------------------------------------------------------------------------------" +puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " +puts " please perform following steps to test design in targeted board." +puts "1. Generate bitstream" +puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" +puts "3. Download generated bitstream" +puts "4. Run generated hardware test using below command, this invokes basic read/write operation" +puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" +puts " : source -notrace ${hw_test_file}" +puts "-------------------------------------------------------------------------------------------------" + diff --git a/IP_AXI_Inputs_1.0/hdl/IP_AXI_Inputs_v1_0.vhd b/IP_AXI_Inputs_1.0/hdl/IP_AXI_Inputs_v1_0.vhd new file mode 100644 index 0000000..29e7fee --- /dev/null +++ b/IP_AXI_Inputs_1.0/hdl/IP_AXI_Inputs_v1_0.vhd @@ -0,0 +1,125 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity IP_AXI_Inputs_v1_0 is + generic ( + -- Users to add parameters here + + -- User parameters ends + -- Do not modify the parameters beyond this line + + + -- Parameters of Axi Slave Bus Interface S00_AXI + C_S00_AXI_DATA_WIDTH : integer := 32; + C_S00_AXI_ADDR_WIDTH : integer := 4 + ); + port ( + -- Users to add ports here + data : in std_logic_vector(31 downto 0); + interrupt : out std_logic := '0'; + -- User ports ends + -- Do not modify the ports beyond this line + + + -- Ports of Axi Slave Bus Interface S00_AXI + s00_axi_aclk : in std_logic; + s00_axi_aresetn : in std_logic; + s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_awprot : in std_logic_vector(2 downto 0); + s00_axi_awvalid : in std_logic; + s00_axi_awready : out std_logic; + s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); + s00_axi_wvalid : in std_logic; + s00_axi_wready : out std_logic; + s00_axi_bresp : out std_logic_vector(1 downto 0); + s00_axi_bvalid : out std_logic; + s00_axi_bready : in std_logic; + s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_arprot : in std_logic_vector(2 downto 0); + s00_axi_arvalid : in std_logic; + s00_axi_arready : out std_logic; + s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_rresp : out std_logic_vector(1 downto 0); + s00_axi_rvalid : out std_logic; + s00_axi_rready : in std_logic + ); +end IP_AXI_Inputs_v1_0; + +architecture arch_imp of IP_AXI_Inputs_v1_0 is + + -- component declaration + component IP_AXI_Inputs_v1_0_S00_AXI is + generic ( + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 4 + ); + port ( + data : in std_logic_vector(31 downto 0); + interrupt : out std_logic := '0'; + + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic + ); + end component IP_AXI_Inputs_v1_0_S00_AXI; + +begin + +-- Instantiation of Axi Bus Interface S00_AXI +IP_AXI_Inputs_v1_0_S00_AXI_inst : IP_AXI_Inputs_v1_0_S00_AXI + generic map ( + C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH + ) + port map ( + data => data, + interrupt => interrupt, + + S_AXI_ACLK => s00_axi_aclk, + S_AXI_ARESETN => s00_axi_aresetn, + S_AXI_AWADDR => s00_axi_awaddr, + S_AXI_AWPROT => s00_axi_awprot, + S_AXI_AWVALID => s00_axi_awvalid, + S_AXI_AWREADY => s00_axi_awready, + S_AXI_WDATA => s00_axi_wdata, + S_AXI_WSTRB => s00_axi_wstrb, + S_AXI_WVALID => s00_axi_wvalid, + S_AXI_WREADY => s00_axi_wready, + S_AXI_BRESP => s00_axi_bresp, + S_AXI_BVALID => s00_axi_bvalid, + S_AXI_BREADY => s00_axi_bready, + S_AXI_ARADDR => s00_axi_araddr, + S_AXI_ARPROT => s00_axi_arprot, + S_AXI_ARVALID => s00_axi_arvalid, + S_AXI_ARREADY => s00_axi_arready, + S_AXI_RDATA => s00_axi_rdata, + S_AXI_RRESP => s00_axi_rresp, + S_AXI_RVALID => s00_axi_rvalid, + S_AXI_RREADY => s00_axi_rready + ); + + -- Add user logic here + + -- User logic ends + +end arch_imp; diff --git a/IP_AXI_Inputs_1.0/hdl/IP_AXI_Inputs_v1_0_S00_AXI.vhd b/IP_AXI_Inputs_1.0/hdl/IP_AXI_Inputs_v1_0_S00_AXI.vhd new file mode 100644 index 0000000..07b407e --- /dev/null +++ b/IP_AXI_Inputs_1.0/hdl/IP_AXI_Inputs_v1_0_S00_AXI.vhd @@ -0,0 +1,420 @@ +library ieee; +use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity IP_AXI_Inputs_v1_0_S00_AXI is + generic ( + -- Users to add parameters here + + -- User parameters ends + -- Do not modify the parameters beyond this line + + -- Width of S_AXI data bus + C_S_AXI_DATA_WIDTH : integer := 32; + -- Width of S_AXI address bus + C_S_AXI_ADDR_WIDTH : integer := 4 + ); + port ( + -- Users to add ports here + data : in std_logic_vector(31 downto 0); + interrupt : out std_logic := '0'; + -- User ports ends + -- Do not modify the ports beyond this line + + -- Global Clock Signal + S_AXI_ACLK : in std_logic; + -- Global Reset Signal. This Signal is Active LOW + S_AXI_ARESETN : in std_logic; + -- Write address (issued by master, acceped by Slave) + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Write channel Protection type. This signal indicates the + -- privilege and security level of the transaction, and whether + -- the transaction is a data access or an instruction access. + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + -- Write address valid. This signal indicates that the master signaling + -- valid write address and control information. + S_AXI_AWVALID : in std_logic; + -- Write address ready. This signal indicates that the slave is ready + -- to accept an address and associated control signals. + S_AXI_AWREADY : out std_logic; + -- Write data (issued by master, acceped by Slave) + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Write strobes. This signal indicates which byte lanes hold + -- valid data. There is one write strobe bit for each eight + -- bits of the write data bus. + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + -- Write valid. This signal indicates that valid write + -- data and strobes are available. + S_AXI_WVALID : in std_logic; + -- Write ready. This signal indicates that the slave + -- can accept the write data. + S_AXI_WREADY : out std_logic; + -- Write response. This signal indicates the status + -- of the write transaction. + S_AXI_BRESP : out std_logic_vector(1 downto 0); + -- Write response valid. This signal indicates that the channel + -- is signaling a valid write response. + S_AXI_BVALID : out std_logic; + -- Response ready. This signal indicates that the master + -- can accept a write response. + S_AXI_BREADY : in std_logic; + -- Read address (issued by master, acceped by Slave) + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Protection type. This signal indicates the privilege + -- and security level of the transaction, and whether the + -- transaction is a data access or an instruction access. + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + -- Read address valid. This signal indicates that the channel + -- is signaling valid read address and control information. + S_AXI_ARVALID : in std_logic; + -- Read address ready. This signal indicates that the slave is + -- ready to accept an address and associated control signals. + S_AXI_ARREADY : out std_logic; + -- Read data (issued by slave) + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Read response. This signal indicates the status of the + -- read transfer. + S_AXI_RRESP : out std_logic_vector(1 downto 0); + -- Read valid. This signal indicates that the channel is + -- signaling the required read data. + S_AXI_RVALID : out std_logic; + -- Read ready. This signal indicates that the master can + -- accept the read data and response information. + S_AXI_RREADY : in std_logic + ); +end IP_AXI_Inputs_v1_0_S00_AXI; + +architecture arch_imp of IP_AXI_Inputs_v1_0_S00_AXI is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 1; + ------------------------------------------------ + ---- Signals for user logic register space example + signal dataBuf :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := x"00000000"; + signal dataPrev :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := x"00000000"; + signal countRead :std_logic_vector(3 downto 0) := x"0"; + signal countReadPrev :std_logic_vector(3 downto 0) := x"0"; + signal interruptBuf : std_logic := '0'; + -------------------------------------------------- + ---- Number of Slave Registers 4 + signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + process (S_AXI_ACLK) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"00" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"01" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + process (dataPrev, dataBuf, axi_araddr, S_AXI_ARESETN, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"00" => + reg_data_out <= dataPrev; + when b"01" => + if countRead = x"F" then + countRead <= (others => '0'); + else + countRead <= std_logic_vector(unsigned(countRead) + 1); + end if; + reg_data_out <= dataBuf; + when b"10" => + reg_data_out <= (others => '0'); + when b"11" => + reg_data_out <= (others => '1'); + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + + -- Add user logic here + process(S_AXI_ACLK) + + begin + if rising_edge(S_AXI_ACLK) then + if data /= dataPrev then + if interruptBuf = '0' then + dataBuf <= data; + interruptBuf <= '1'; + end if; + end if; + if interruptBuf = '1' and countRead /= countReadPrev then + interruptBuf <= '0'; + end if; + dataPrev <= data; + countReadPrev <= countRead; + end if; + end process; + + interrupt <= interruptBuf; + -- User logic ends + +end arch_imp; diff --git a/IP_AXI_Inputs_1.0/xgui/IP_AXI_Inputs_v1_0.tcl b/IP_AXI_Inputs_1.0/xgui/IP_AXI_Inputs_v1_0.tcl new file mode 100644 index 0000000..d8bf174 --- /dev/null +++ b/IP_AXI_Inputs_1.0/xgui/IP_AXI_Inputs_v1_0.tcl @@ -0,0 +1,62 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox] + set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH} + set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}] + set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH} + ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to validate C_S00_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S00_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to validate C_S00_AXI_BASEADDR + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to validate C_S00_AXI_HIGHADDR + return true +} + + +proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} +} +