1607 lines
50 KiB
C
1607 lines
50 KiB
C
/*
|
|
* detect_errors.c
|
|
*
|
|
* Created on: 4 äåê. 2020 ã.
|
|
* Author: star
|
|
*/
|
|
|
|
#include <adc_tools.h>
|
|
#include <detect_errors.h>
|
|
#include <detect_overload.h>
|
|
#include <edrk_main.h>
|
|
#include <optical_bus.h>
|
|
#include <params.h>
|
|
#include <params_temper_p.h>
|
|
#include <protect_levels.h>
|
|
#include <sync_tools.h>
|
|
#include <vector.h>
|
|
#include "v_rotor.h"
|
|
|
|
|
|
#include "control_station.h"
|
|
#include "DSP281x_Device.h"
|
|
#include "master_slave.h"
|
|
#include "another_bs.h"
|
|
#include "digital_filters.h"
|
|
|
|
|
|
void detect_error_from_knopka_avaria(void);
|
|
void detect_error_ute4ka_water(void);
|
|
void detect_error_t_vipr(void);
|
|
void detect_error_power_upc(void);
|
|
void detect_error_op_pit(void);
|
|
void detect_error_p_water(void);
|
|
void detect_error_pump_2(void);
|
|
void detect_error_pump_1(void);
|
|
void detect_error_pre_ready_pump(void);
|
|
void detect_error_fan(void);
|
|
void detect_error_block_qtv_from_svu(void);
|
|
|
|
void detect_error_predohr_vipr(void);
|
|
void detect_error_qtv(void);
|
|
void detect_error_pre_charge(void);
|
|
void detect_error_block_izol(void);
|
|
void detect_error_nagrev(void);
|
|
void detect_error_ground(void);
|
|
void detect_error_block_door(void);
|
|
void detect_error_optical_bus(void);
|
|
void detect_error_sync_bus(void);
|
|
int get_status_temper_acdrive_winding(int nc);
|
|
int get_status_temper_acdrive_winding_with_limits(int nc, int alarm, int abnormal);
|
|
int get_status_temper_acdrive_bear(int nc);
|
|
int get_status_temper_acdrive_bear_with_limits(int nc, int alarm, int abnormal);
|
|
int get_status_temper_air(int nc);
|
|
int get_status_temper_air_with_limits(int nc, int alarm, int abnormal);
|
|
int get_status_temper_u(int nc);
|
|
int get_status_temper_u_with_limits(int nc, int alarm, int abnormal);
|
|
int get_status_temper_water(int nc);
|
|
int get_status_p_water_max(void);
|
|
int get_status_p_water_min(int pump_on_off);
|
|
void detect_error_t_water(void);
|
|
void detect_error_t_air(void);
|
|
void detect_error_t_u(void);
|
|
void detect_error_acdrive_winding(void);
|
|
|
|
int get_common_state_warning(void);
|
|
int get_common_state_overheat(void);
|
|
void detect_error_sensor_rotor(void);
|
|
|
|
|
|
|
|
|
|
#pragma DATA_SECTION(protect_levels,".slow_vars");
|
|
PROTECT_LEVELS protect_levels = PROTECT_LEVELS_DEFAULTS;
|
|
|
|
|
|
|
|
|
|
///////////////////////////////////////////////
|
|
int get_status_temper_acdrive_winding(int nc)
|
|
{
|
|
if (edrk.temper_acdrive.winding.filter_real_int_temper[nc]>=ALARM_TEMPER_ACDRIVE_WINDING)
|
|
return 4;
|
|
if (edrk.temper_acdrive.winding.filter_real_int_temper[nc]>=ABNORMAL_TEMPER_ACDRIVE_WINDING)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
int get_status_temper_acdrive_winding_with_limits(int nc, int alarm, int abnormal)
|
|
{
|
|
if (edrk.temper_acdrive.winding.filter_real_int_temper[nc]>=alarm)
|
|
return 4;
|
|
if (edrk.temper_acdrive.winding.filter_real_int_temper[nc]>=abnormal)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
///////////////////////////////////////////////
|
|
int get_status_temper_acdrive_bear(int nc)
|
|
{
|
|
|
|
if (edrk.temper_acdrive.bear.filter_real_int_temper[nc]>=ALARM_TEMPER_ACDRIVE_WINDING)
|
|
return 4;
|
|
if (edrk.temper_acdrive.bear.filter_real_int_temper[nc]>=ABNORMAL_TEMPER_ACDRIVE_WINDING)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
int get_status_temper_acdrive_bear_with_limits(int nc, int alarm, int abnormal)
|
|
{
|
|
|
|
if (edrk.temper_acdrive.bear.filter_real_int_temper[nc]>=alarm)
|
|
return 4;
|
|
if (edrk.temper_acdrive.bear.filter_real_int_temper[nc]>=abnormal)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
int get_status_temper_air(int nc)
|
|
{
|
|
if (edrk.temper_edrk.real_int_temper_air[nc]>=ALARM_TEMPER_AIR_INT)
|
|
return 4;
|
|
if (edrk.temper_edrk.real_int_temper_air[nc]>=ABNORMAL_TEMPER_AIR_INT)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
int get_status_temper_air_with_limits(int nc, int alarm, int abnormal)
|
|
{
|
|
if (edrk.temper_edrk.real_int_temper_air[nc]>=alarm)
|
|
return 4;
|
|
if (edrk.temper_edrk.real_int_temper_air[nc]>=abnormal)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
int get_status_temper_u(int nc)
|
|
{
|
|
if (edrk.temper_edrk.real_int_temper_u[nc]>=ALARM_TEMPER_AF)
|
|
return 4;
|
|
if (edrk.temper_edrk.real_int_temper_u[nc]>=ABNORMAL_TEMPER_AF)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
int get_status_temper_u_with_limits(int nc, int alarm, int abnormal)
|
|
{
|
|
if (edrk.temper_edrk.real_int_temper_u[nc]>=alarm)
|
|
return 4;
|
|
if (edrk.temper_edrk.real_int_temper_u[nc]>=abnormal)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
int get_status_temper_water(int nc)
|
|
{
|
|
|
|
if (nc==INDEX_T_WATER_EXT) // ext
|
|
{
|
|
if (edrk.temper_edrk.real_int_temper_water[nc]>=protect_levels.alarm_temper_water_ext)
|
|
return 4;
|
|
if (edrk.temper_edrk.real_int_temper_water[nc]>=protect_levels.abnormal_temper_water_ext)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
if (nc==INDEX_T_WATER_INT) // int
|
|
{
|
|
if (edrk.temper_edrk.real_int_temper_water[nc]>=protect_levels.alarm_temper_water_int)
|
|
return 4;
|
|
if (edrk.temper_edrk.real_int_temper_water[nc]>=protect_levels.abnormal_temper_water_int)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
int get_status_p_water_max(void)
|
|
{
|
|
if (edrk.p_water_edrk.filter_real_int_p_water[0]>=protect_levels.alarm_p_water_max_int)
|
|
return 4;
|
|
if (edrk.p_water_edrk.filter_real_int_p_water[0]>=protect_levels.abnormal_p_water_max_int)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
int get_status_p_water_min(int pump_on_off)
|
|
{
|
|
if (pump_on_off == 0)
|
|
{
|
|
if (edrk.p_water_edrk.filter_real_int_p_water[0]<=ALARM_P_WATER_MIN_INT_ON_OFF_PUMP)
|
|
return 4;
|
|
if (edrk.p_water_edrk.filter_real_int_p_water[0]<=ABNORMAL_P_WATER_MIN_INT_ON_OFF_PUMP)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
if (pump_on_off == 1)
|
|
{
|
|
if (edrk.p_water_edrk.filter_real_int_p_water[0]<=protect_levels.alarm_p_water_min_int)
|
|
return 4;
|
|
if (edrk.p_water_edrk.filter_real_int_p_water[0]<=protect_levels.abnormal_p_water_min_int)
|
|
return 2;
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
void detect_error_sensor_rotor(void)
|
|
{
|
|
static unsigned int count_err1 = 0, count_err2 = 0, count_err3 = 0, count_err4 = 0;
|
|
|
|
|
|
if (edrk.Go)
|
|
{
|
|
// ñòîèì íà ìåñòå?
|
|
if (edrk.iq_f_rotor_hz==0)
|
|
{
|
|
// äîëãî ñòîèì!
|
|
if (pause_detect_error(&count_err3,TIME_WAIT_SENSOR_ROTOR_BREAK_ALL,1))
|
|
{
|
|
edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 1;
|
|
edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 1;
|
|
//edrk.errors.e9.bits.SENSOR_ROTOR_1_2_BREAK |= 1; // ïîêà óáåðåì!
|
|
}
|
|
else
|
|
{
|
|
// edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 0;
|
|
// edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 0;
|
|
edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = pause_detect_error(&count_err1,TIME_WAIT_SENSOR_ROTOR_BREAK_ONE_SENSOR,
|
|
inc_sensor.break_sensor1);
|
|
edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = pause_detect_error(&count_err2,TIME_WAIT_SENSOR_ROTOR_BREAK_ONE_SENSOR,
|
|
inc_sensor.break_sensor2);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
count_err3 = 0;
|
|
// edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 0;
|
|
// edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 0;
|
|
edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK |= pause_detect_error(&count_err1,TIME_WAIT_ERROR,inc_sensor.break_sensor1);
|
|
edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK |= pause_detect_error(&count_err2,TIME_WAIT_ERROR,inc_sensor.break_sensor2);
|
|
|
|
}
|
|
}
|
|
else
|
|
{
|
|
|
|
count_err1 = count_err2 = 0;
|
|
count_err3 = 0;
|
|
|
|
edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 0;
|
|
edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 0;
|
|
}
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
#define TIME_WAIT_T_WATER 30
|
|
void detect_error_t_water(void)
|
|
{
|
|
static unsigned int count_run = 0, count_run_static = 0;
|
|
int status;
|
|
|
|
status = get_status_temper_water(INDEX_T_WATER_INT);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_WATER_INT_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_WATER_INT_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_WATER_INT_MAX = 0;
|
|
|
|
status = get_status_temper_water(INDEX_T_WATER_EXT);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_WATER_EXT_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_WATER_EXT_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_WATER_EXT_MAX = 0;
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
|
|
void detect_error_t_air(void)
|
|
{
|
|
static unsigned int count_run = 0, count_run_static = 0;
|
|
int status,i;
|
|
|
|
|
|
status = get_status_temper_air_with_limits(0, protect_levels.alarm_temper_air_int_01,
|
|
protect_levels.abnormal_temper_air_int_01);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_AIR0_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_AIR0_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_AIR0_MAX = 0;
|
|
|
|
|
|
status = get_status_temper_air_with_limits(1, protect_levels.alarm_temper_air_int_02,
|
|
protect_levels.abnormal_temper_air_int_02);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_AIR1_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_AIR1_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_AIR1_MAX = 0;
|
|
|
|
|
|
status = get_status_temper_air_with_limits(2, protect_levels.alarm_temper_air_int_03,
|
|
protect_levels.abnormal_temper_air_int_03);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_AIR2_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_AIR2_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_AIR2_MAX = 0;
|
|
|
|
|
|
status = get_status_temper_air_with_limits(3, protect_levels.alarm_temper_air_int_04,
|
|
protect_levels.abnormal_temper_air_int_04);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_AIR3_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_AIR3_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_AIR3_MAX = 0;
|
|
}
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
|
|
void detect_error_t_u(void)
|
|
{
|
|
static unsigned int count_run = 0, count_run_static = 0;
|
|
int status,i;
|
|
|
|
|
|
status = get_status_temper_u_with_limits(0, protect_levels.alarm_temper_u_01,
|
|
protect_levels.abnormal_temper_u_01);
|
|
if (status == 4)
|
|
edrk.errors.e2.bits.T_UO1_MAX |= 1;
|
|
if (status == 2)
|
|
edrk.warnings.e2.bits.T_UO1_MAX = 1;
|
|
if (status == 1)
|
|
edrk.warnings.e2.bits.T_UO1_MAX = 0;
|
|
|
|
status = get_status_temper_u_with_limits(1, protect_levels.alarm_temper_u_02,
|
|
protect_levels.abnormal_temper_u_02);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_UO2_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_UO2_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_UO2_MAX = 0;
|
|
|
|
status = get_status_temper_u_with_limits(2, protect_levels.alarm_temper_u_03,
|
|
protect_levels.abnormal_temper_u_03);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_UO3_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_UO3_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_UO3_MAX = 0;
|
|
|
|
status = get_status_temper_u_with_limits(3, protect_levels.alarm_temper_u_04,
|
|
protect_levels.abnormal_temper_u_04);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_UO4_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_UO4_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_UO4_MAX = 0;
|
|
|
|
status = get_status_temper_u_with_limits(4, protect_levels.alarm_temper_u_05,
|
|
protect_levels.abnormal_temper_u_05);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_UO5_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_UO5_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_UO5_MAX = 0;
|
|
|
|
status = get_status_temper_u_with_limits(5, protect_levels.alarm_temper_u_06,
|
|
protect_levels.abnormal_temper_u_06);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_UO6_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_UO6_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_UO6_MAX = 0;
|
|
|
|
status = get_status_temper_u_with_limits(6, protect_levels.alarm_temper_u_07,
|
|
protect_levels.abnormal_temper_u_07);
|
|
if (status==4)
|
|
edrk.errors.e2.bits.T_UO7_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.T_UO7_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.T_UO7_MAX = 0;
|
|
|
|
}
|
|
|
|
void detect_error_t_bsu(void) {
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
void detect_error_acdrive_winding(void)
|
|
{
|
|
// static unsigned int count_run = 0, count_run_static = 0;
|
|
int status, i;
|
|
|
|
status = 0;
|
|
status |= get_status_temper_acdrive_winding_with_limits(
|
|
0, protect_levels.alarm_temper_acdrive_winding_U1,
|
|
protect_levels.abnormal_temper_acdrive_winding_U1);
|
|
if (status == 4) {
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1 = 1;
|
|
}
|
|
if (status == 2) {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1 = 1;
|
|
} else {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1 = 0;
|
|
}
|
|
|
|
status = 0;
|
|
status |= get_status_temper_acdrive_winding_with_limits(
|
|
1, protect_levels.alarm_temper_acdrive_winding_V1,
|
|
protect_levels.abnormal_temper_acdrive_winding_V1);
|
|
if (status == 4) {
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_V1 = 1;
|
|
}
|
|
if (status == 2) {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1 = 1;
|
|
} else {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1 = 0;
|
|
}
|
|
|
|
status = 0;
|
|
status |= get_status_temper_acdrive_winding_with_limits(
|
|
2, protect_levels.alarm_temper_acdrive_winding_W1,
|
|
protect_levels.abnormal_temper_acdrive_winding_W1);
|
|
if (status == 4) {
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_W1 = 1;
|
|
}
|
|
if (status == 2) {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1 = 1;
|
|
} else {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1 = 0;
|
|
}
|
|
|
|
status = 0;
|
|
status |= get_status_temper_acdrive_winding_with_limits(
|
|
3, protect_levels.alarm_temper_acdrive_winding_U2,
|
|
protect_levels.abnormal_temper_acdrive_winding_U2);
|
|
if (status == 4) {
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_U2 = 1;
|
|
}
|
|
if (status == 2) {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2 = 1;
|
|
} else {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2 = 0;
|
|
}
|
|
|
|
status = 0;
|
|
status |= get_status_temper_acdrive_winding_with_limits(
|
|
4, protect_levels.alarm_temper_acdrive_winding_V2,
|
|
protect_levels.abnormal_temper_acdrive_winding_V2);
|
|
if (status == 4) {
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_V2 = 1;
|
|
}
|
|
if (status == 2) {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2 = 1;
|
|
} else {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2 = 0;
|
|
}
|
|
|
|
status = 0;
|
|
status |= get_status_temper_acdrive_winding_with_limits(
|
|
5, protect_levels.alarm_temper_acdrive_winding_W2,
|
|
protect_levels.abnormal_temper_acdrive_winding_W2);
|
|
if (status == 4) {
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_W2 = 1;
|
|
}
|
|
if (status == 2) {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2 = 1;
|
|
} else {
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2 = 0;
|
|
}
|
|
|
|
if (edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_V1 ||
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_W1 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_U2 ||
|
|
edrk.errors.e10.bits.T_ACDRIVE_WINDING_V2 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_W2) {
|
|
edrk.errors.e7.bits.T_ACDRIVE_WINDING_MAX |= 1;
|
|
}
|
|
if (edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1 ||
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2 ||
|
|
edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2) {
|
|
edrk.warnings.e7.bits.T_ACDRIVE_WINDING_MAX = 1;
|
|
}
|
|
else
|
|
edrk.warnings.e7.bits.T_ACDRIVE_WINDING_MAX = 0;
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
void detect_error_acdrive_bear(void)
|
|
{
|
|
static unsigned int count_run = 0, count_run_static = 0;
|
|
int status,i;
|
|
|
|
// status = 0;
|
|
|
|
status = get_status_temper_acdrive_bear_with_limits(0, protect_levels.alarm_temper_acdrive_bear_DNE,
|
|
protect_levels.abnormal_temper_acdrive_bear_DNE);
|
|
if (status & 4)
|
|
edrk.errors.e7.bits.T_ACDRIVE_BEAR_MAX_DNE |= 1;
|
|
if (status == 2)
|
|
edrk.warnings.e7.bits.T_ACDRIVE_BEAR_MAX_DNE = 1;
|
|
if (status == 1)
|
|
edrk.warnings.e7.bits.T_ACDRIVE_BEAR_MAX_DNE = 0;
|
|
|
|
status = get_status_temper_acdrive_bear_with_limits(1, protect_levels.alarm_temper_acdrive_bear_NE,
|
|
protect_levels.abnormal_temper_acdrive_bear_NE);
|
|
if (status & 4)
|
|
edrk.errors.e9.bits.T_ACDRIVE_BEAR_MAX_NE |= 1;
|
|
if (status == 2)
|
|
edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE = 1;
|
|
if (status == 1)
|
|
edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE = 0;
|
|
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
#define TIME_WAIT_RUN_PUMP 100 //50
|
|
void detect_error_p_water(void)
|
|
{
|
|
static unsigned int count_run = 0, count_run_static = 0;
|
|
int status,i;
|
|
|
|
if (edrk.from_ing1.bits.NASOS_ON == 1)
|
|
{
|
|
if (pause_detect_error(&count_run,TIME_WAIT_RUN_PUMP,1))
|
|
{
|
|
status = get_status_p_water_max();
|
|
|
|
if (status & 4)
|
|
edrk.errors.e2.bits.P_WATER_INT_MAX |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.P_WATER_INT_MAX = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.P_WATER_INT_MAX = 0;
|
|
|
|
status = get_status_p_water_min(1);
|
|
|
|
if (status & 4)
|
|
edrk.errors.e2.bits.P_WATER_INT_MIN |= 1;
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.P_WATER_INT_MIN = 1;
|
|
if (status==1)
|
|
edrk.warnings.e2.bits.P_WATER_INT_MIN = 0;
|
|
|
|
}
|
|
}
|
|
else
|
|
count_run = 0;
|
|
|
|
|
|
// test if nasos off
|
|
status = get_status_p_water_min(0);
|
|
if (status>1)
|
|
{
|
|
if (pause_detect_error(&count_run_static,TIME_WAIT_RUN_PUMP,1))
|
|
{
|
|
if (status==4)
|
|
{
|
|
if (control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_PUMP]==0)
|
|
edrk.errors.e2.bits.P_WATER_INT_MIN |= 1;
|
|
}
|
|
if (status==2)
|
|
edrk.warnings.e2.bits.P_WATER_INT_MIN = 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
count_run_static = 0;
|
|
edrk.warnings.e2.bits.P_WATER_INT_MIN = 0;
|
|
}
|
|
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
|
|
///////////////////////////////////////////////
|
|
|
|
void detect_error_ground(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
|
|
if (edrk.from_ing1.bits.ZAZEML_OFF == 0)
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1))
|
|
edrk.errors.e5.bits.ERROR_GROUND_NET |= 1;
|
|
}
|
|
|
|
if (edrk.from_ing1.bits.ZAZEML_ON == 1)
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1))
|
|
edrk.errors.e5.bits.ERROR_GROUND_NET |= 1;
|
|
}
|
|
|
|
if ((edrk.from_ing1.bits.ZAZEML_OFF == 1) && (edrk.from_ing1.bits.ZAZEML_ON == 0))
|
|
count_err = 0;
|
|
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
void detect_error_nagrev(void)
|
|
{
|
|
|
|
static unsigned int count_err = 0;
|
|
|
|
if (edrk.from_ing1.bits.NAGREV_ON == edrk.to_ing.bits.NAGREV_OFF)
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1))
|
|
edrk.errors.e5.bits.ERROR_HEAT |= 1;
|
|
}
|
|
else
|
|
count_err = 0;
|
|
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
#define TIME_WAIT_ERROR_BLOCK_DOOR 30 //20
|
|
void detect_error_block_door(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
if ((edrk.from_ing2.bits.SOST_ZAMKA == 1 && edrk.to_ing.bits.BLOCK_KEY_OFF==1)
|
|
|| (edrk.from_ing2.bits.SOST_ZAMKA == 0 && edrk.to_ing.bits.BLOCK_KEY_OFF==0))
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_BLOCK_DOOR,1))
|
|
edrk.errors.e1.bits.BLOCK_DOOR |= 1;
|
|
}
|
|
else
|
|
count_err = 0;
|
|
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
void detect_error_block_izol(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
if (edrk.from_ing1.bits.BLOCK_IZOL_AVARIA == 1 )
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_IZOL,1))
|
|
edrk.errors.e5.bits.ERROR_ISOLATE |= 1;
|
|
}
|
|
|
|
if (edrk.from_ing1.bits.BLOCK_IZOL_AVARIA == 0 && edrk.from_ing1.bits.BLOCK_IZOL_NORMA == 0 )
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_IZOL,1))
|
|
edrk.warnings.e5.bits.ERROR_ISOLATE |= 1;
|
|
}
|
|
else
|
|
edrk.warnings.e5.bits.ERROR_ISOLATE = 0;
|
|
|
|
if (edrk.from_ing1.bits.BLOCK_IZOL_AVARIA == 0 && edrk.from_ing1.bits.BLOCK_IZOL_NORMA == 1 )
|
|
{
|
|
count_err = 0;
|
|
}
|
|
|
|
if (edrk.cmd_imit_low_isolation)
|
|
edrk.errors.e5.bits.ERROR_ISOLATE |= 1;
|
|
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
void detect_error_pre_charge(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
if (edrk.from_ing1.bits.ZARYAD_ON == 1 && edrk.to_ing.bits.ZARYAD_ON == 0)
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_CHARGE_ANSWER,1))
|
|
edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER |= 1;
|
|
}
|
|
|
|
if (edrk.from_ing1.bits.ZARYAD_ON == 0 && edrk.to_ing.bits.ZARYAD_ON == 1)
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_CHARGE_ANSWER,1))
|
|
edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER |= 1;
|
|
|
|
|
|
if (edrk.from_ing1.bits.ZARYAD_ON == 0 && edrk.to_ing.bits.ZARYAD_ON == 0)
|
|
count_err = 0;
|
|
|
|
|
|
// edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER |= 1;
|
|
// edrk.errors.e6.bits.ERROR_PRE_CHARGE_U |= 1;
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
void detect_error_qtv(void)
|
|
{
|
|
static unsigned int count_err_off = 0;
|
|
static unsigned int count_err_on = 0;
|
|
|
|
|
|
// íåò êîìàíäû íà âûêë, íî ñóõîé êîíòàêò ïðèøåë
|
|
if (edrk.from_shema_filter.bits.QTV_ON_OFF == 1 && edrk.cmd_to_qtv == 0)
|
|
{
|
|
if (pause_detect_error(&count_err_off,TIME_WAIT_ERROR_QTV,1))
|
|
edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER |= 1;
|
|
}
|
|
else
|
|
{
|
|
count_err_off = 0;
|
|
}
|
|
|
|
// áûëà êîìàíäà íà âêë, íî ñóõîé êîíòàêò íå ïðèøåë
|
|
if (edrk.from_shema_filter.bits.QTV_ON_OFF == 0 && edrk.cmd_to_qtv == 1)
|
|
{
|
|
if (pause_detect_error(&count_err_on,TIME_WAIT_ERROR_QTV,1))
|
|
edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER |= 1;
|
|
}
|
|
else
|
|
{
|
|
count_err_on = 0;
|
|
}
|
|
|
|
//
|
|
// if (edrk.from_shema.bits.QTV_ON_OFF == 0 && edrk.cmd_to_qtv == 0)
|
|
// count_err = 0;
|
|
|
|
// edrk.errors.e6.bits.QTV_ERROR_NOT_U |= 1;
|
|
|
|
// edrk.errors.e6.bits.QTV_ERROR_NOT_U |= detect_error_u_zpt();
|
|
edrk.errors.e6.bits.QTV_ERROR_NOT_U |= detect_error_u_in();
|
|
// edrk.errors.e6.bits.QTV_ERROR_NOT_U |= detect_error_u_zpt_on_predzaryad();
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
void detect_error_predohr_vipr(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
if (edrk.from_ing1.bits.VIPR_PREDOHR_NORMA == 0)
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1))
|
|
edrk.errors.e5.bits.ERROR_PRED_VIPR |= 1;
|
|
|
|
if (edrk.from_ing1.bits.VIPR_PREDOHR_NORMA == 1)
|
|
count_err = 0;
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
#define TIME_WAIT_ERROR_UMP_READY 1200 //120 ñåê //750 // æäåì 75 ñåê ò.ê. âîçìîæíî óìð çàíÿò íà ñáîð âòîðîãî áñ
|
|
#define TIME_WAIT_WARNING_UMP_READY 10
|
|
void detect_error_ump(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
static unsigned int count_err2 = 0;
|
|
|
|
static unsigned int prev_SumSbor = 0;
|
|
static unsigned int StageUMP = 0;
|
|
static unsigned int count_UMP_NOT_READY = 0;
|
|
int local_warning_ump = 0;
|
|
|
|
if (edrk.SumSbor==1)
|
|
{
|
|
switch (StageUMP) {
|
|
case 0: if (edrk.from_shema_filter.bits.UMP_ON_OFF == 1)
|
|
StageUMP++;
|
|
break;
|
|
case 1: if (edrk.from_shema_filter.bits.UMP_ON_OFF == 0)
|
|
StageUMP++;
|
|
break;
|
|
case 2:
|
|
break;
|
|
case 3:
|
|
break;
|
|
|
|
|
|
default: break;
|
|
}
|
|
|
|
if ((edrk.from_shema_filter.bits.READY_UMP == 0) && (StageUMP==0) && control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_UMP]==0)
|
|
{
|
|
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_UMP_READY,1))
|
|
edrk.errors.e7.bits.UMP_NOT_READY |= 1;
|
|
}
|
|
if (edrk.from_shema_filter.bits.READY_UMP == 1)
|
|
count_err = 0;
|
|
}
|
|
else
|
|
{
|
|
count_err= 0;
|
|
|
|
// ÓÌÏ âêëþ÷åí, à íå äîëæåí!
|
|
if (edrk.from_shema_filter.bits.UMP_ON_OFF==1)
|
|
if (pause_detect_error(&count_err2,TIME_WAIT_ERROR,1))
|
|
edrk.errors.e11.bits.ERROR_UMP_NOT_OFF |= 1;
|
|
|
|
if (edrk.from_shema_filter.bits.UMP_ON_OFF == 0)
|
|
count_err2 = 0;
|
|
|
|
// íåò ãîòîâíîñòè
|
|
if (edrk.ump_cmd_another_bs==0) // äðóãîé ÁÑ íå çàíÿë ÓÌÏ
|
|
local_warning_ump = !edrk.from_shema_filter.bits.READY_UMP;
|
|
// edrk.warnings.e7.bits.UMP_NOT_READY = !edrk.from_shema_filter.bits.READY_UMP;
|
|
|
|
|
|
|
|
StageUMP = 0;
|
|
}
|
|
|
|
edrk.warnings.e7.bits.UMP_NOT_READY = filter_digital_input( edrk.warnings.e7.bits.UMP_NOT_READY,
|
|
&count_UMP_NOT_READY,
|
|
TIME_WAIT_WARNING_UMP_READY,
|
|
local_warning_ump);
|
|
|
|
prev_SumSbor = edrk.SumSbor;
|
|
}
|
|
|
|
|
|
#define TIME_WAIT_BLOCK_QTV_FROM_SVU 20
|
|
///////////////////////////////////////////////
|
|
void detect_error_block_qtv_from_svu(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
|
|
if (edrk.from_shema.bits.SVU_BLOCK_QTV == 1 || control_station.active_array_cmd[CONTROL_STATION_CMD_BLOCK_BS])
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_BLOCK_QTV_FROM_SVU,1))
|
|
edrk.errors.e7.bits.SVU_BLOCK_ON_QTV |= 1;
|
|
}
|
|
else
|
|
{
|
|
count_err = 0;
|
|
}
|
|
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
void detect_error_fan(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
if (edrk.from_ing1.bits.VENTIL_ON == 0 && (edrk.to_ing.bits.NASOS_1_ON || edrk.to_ing.bits.NASOS_2_ON))
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_FAN,1))
|
|
edrk.errors.e5.bits.FAN |= 1;
|
|
|
|
if (edrk.from_ing1.bits.VENTIL_ON == 1 && (edrk.to_ing.bits.NASOS_1_ON == 0 && edrk.to_ing.bits.NASOS_2_ON == 0))
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_FAN,1))
|
|
edrk.errors.e5.bits.FAN |= 1;
|
|
|
|
if (edrk.from_ing1.bits.VENTIL_ON == 0 && (edrk.to_ing.bits.NASOS_1_ON == 0 && edrk.to_ing.bits.NASOS_2_ON == 0))
|
|
count_err = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
///////////////////////////////////////////////
|
|
void detect_error_pre_ready_pump(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
if (edrk.from_ing1.bits.NASOS_NORMA == 0)
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1))
|
|
{
|
|
// edrk.errors.e5.bits.PRE_READY_PUMP |= 1;
|
|
edrk.warnings.e5.bits.PRE_READY_PUMP = 1;
|
|
}
|
|
|
|
if (edrk.from_ing1.bits.NASOS_NORMA == 1)
|
|
{
|
|
count_err = 0;
|
|
edrk.warnings.e5.bits.PRE_READY_PUMP = 0;
|
|
}
|
|
}
|
|
///////////////////////////////////////////////
|
|
void detect_error_pump_1(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
// ñèãíàë íà âêë, à íàñîñ íå ïóñòèëñÿ
|
|
if (edrk.from_ing1.bits.NASOS_ON == 0 && edrk.to_ing.bits.NASOS_1_ON)
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_PUMP,1))
|
|
{
|
|
// edrk.errors.e5.bits.PUMP_1 |= 1;
|
|
edrk.warnings.e5.bits.PUMP_1 = 1;
|
|
}
|
|
}
|
|
|
|
|
|
// ñèãíàë íà âûêë, à íàñîñ íå îñòàíîâèëñÿ
|
|
if (edrk.from_ing1.bits.NASOS_ON == 1 && edrk.to_ing.bits.NASOS_1_ON==0 && edrk.SelectPump1_2==1)
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_PUMP,1))
|
|
edrk.errors.e5.bits.PUMP_1 |= 1;
|
|
|
|
|
|
if (edrk.from_ing1.bits.NASOS_ON == 0 && edrk.to_ing.bits.NASOS_1_ON==0 && edrk.SelectPump1_2==1)
|
|
{
|
|
// òóò âñå îê
|
|
count_err = 0;
|
|
}
|
|
|
|
if (edrk.from_ing1.bits.NASOS_ON == 1 && edrk.to_ing.bits.NASOS_1_ON==1 && edrk.SelectPump1_2==1)
|
|
{
|
|
// òóò âñå îê
|
|
count_err = 0;
|
|
edrk.warnings.e5.bits.PUMP_1 = 0;
|
|
}
|
|
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
void detect_error_pump_2(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
// ñèãíàë íà âêë, à íàñîñ íå ïóñòèëñÿ
|
|
if (edrk.from_ing1.bits.NASOS_ON == 0 && edrk.to_ing.bits.NASOS_2_ON)
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_PUMP,1))
|
|
// edrk.errors.e5.bits.PUMP_2 |= 1;
|
|
edrk.warnings.e5.bits.PUMP_2 = 1;
|
|
}
|
|
|
|
if (edrk.from_ing1.bits.NASOS_ON == 1 && edrk.to_ing.bits.NASOS_2_ON==0 && edrk.SelectPump1_2==2)
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR_PUMP,1))
|
|
edrk.errors.e5.bits.PUMP_2 |= 1;
|
|
}
|
|
|
|
if (edrk.from_ing1.bits.NASOS_ON == 0 && edrk.to_ing.bits.NASOS_2_ON==0 && edrk.SelectPump1_2==2)
|
|
{
|
|
// òóò âñå îê
|
|
count_err = 0;
|
|
}
|
|
|
|
if (edrk.from_ing1.bits.NASOS_ON == 1 && edrk.to_ing.bits.NASOS_2_ON==1 && edrk.SelectPump1_2==2)
|
|
{
|
|
// òóò âñå îê
|
|
count_err = 0;
|
|
edrk.warnings.e5.bits.PUMP_2 = 0;
|
|
}
|
|
}
|
|
///////////////////////////////////////////////
|
|
|
|
///////////////////////////////////////////////
|
|
void detect_error_op_pit(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
if (edrk.from_ing1.bits.OP_PIT_NORMA == 0 )
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1))
|
|
edrk.errors.e5.bits.OP_PIT |= 1;
|
|
|
|
if (edrk.from_ing1.bits.OP_PIT_NORMA == 1 )
|
|
count_err = 0;
|
|
}
|
|
///////////////////////////////////////////////
|
|
void detect_error_power_upc(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
if (edrk.from_ing1.bits.UPC_24V_NORMA == 0 )
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1))
|
|
edrk.errors.e5.bits.POWER_UPC |= 1;
|
|
|
|
if (edrk.from_ing1.bits.UPC_24V_NORMA == 1 )
|
|
count_err = 0;
|
|
}
|
|
///////////////////////////////////////////////
|
|
void detect_error_t_vipr(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
// if (edrk.from_ing.bits.VIPR_TEMPER_OK == 0 )
|
|
// if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1))
|
|
// edrk.errors.e5.bits.T_VIPR_MAX |= 1;
|
|
//
|
|
// if (edrk.from_ing.bits.VIPR_TEMPER_OK == 1 )
|
|
// pause_detect_error(&count_err,TIME_WAIT_ERROR,0);
|
|
}
|
|
///////////////////////////////////////////////
|
|
void detect_error_ute4ka_water(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
if (edrk.from_ing1.bits.OHLAD_UTE4KA_WATER == 1 )
|
|
if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1))
|
|
edrk.errors.e5.bits.UTE4KA_WATER |= 1;
|
|
|
|
|
|
if (edrk.from_ing1.bits.OHLAD_UTE4KA_WATER == 0 )
|
|
count_err = 0;
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
void detect_error_from_knopka_avaria(void)
|
|
{
|
|
edrk.errors.e5.bits.KEY_AVARIA |= edrk.from_ing1.bits.ALL_KNOPKA_AVARIA;
|
|
}
|
|
///////////////////////////////////////////////
|
|
void detect_error_optical_bus(void)
|
|
{
|
|
// if ()
|
|
|
|
|
|
|
|
}
|
|
|
|
#define TIME_WAIT_SYNC_SIGNAL 20 // 2 sec
|
|
///////////////////////////////////////////////
|
|
void detect_error_sync_bus(void)
|
|
{
|
|
static unsigned int count_err = 0;
|
|
|
|
// if (sync_data.flag_sync_1_2==0)
|
|
// edrk.errors.e7.bits.MASTER_SLAVE_SYNC |= 1;
|
|
|
|
if (!edrk.ms.ready1)
|
|
{
|
|
edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL = 0;
|
|
count_err = 0;
|
|
return;
|
|
}
|
|
|
|
// ó ýòîãî ÁÑ ñèíõðîñèãíàëà íåò, íî åñòü ó âòîðîãî, òîãäà ïðåäóïðåæäåíèå
|
|
if (sync_data.timeout_sync_signal && optical_read_data.data.cmd.bit.sync_line_detect
|
|
&& optical_read_data.status==1)
|
|
{
|
|
edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL = 1;
|
|
return;
|
|
}
|
|
else
|
|
edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL = 0;
|
|
|
|
|
|
// ó ýòîãî ÁÑ ñèíõðîñèãíàëà íåò, è ó âòîðîãî òîæå íåò, òîãäà àâàðèÿ
|
|
if (sync_data.timeout_sync_signal && optical_read_data.data.cmd.bit.sync_line_detect==0
|
|
&& edrk.ms.another_bs_maybe_on && optical_read_data.status==1)
|
|
{
|
|
if (pause_detect_error(&count_err,TIME_WAIT_SYNC_SIGNAL,1))
|
|
edrk.errors.e1.bits.NO_INPUT_SYNC_SIGNAL |= 1;
|
|
}
|
|
else
|
|
count_err = 0;
|
|
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
#pragma CODE_SECTION(detect_error_u_zpt_fast,".fast_run");
|
|
int detect_error_u_zpt_fast(void)
|
|
{
|
|
int err;
|
|
|
|
err = 0;
|
|
|
|
|
|
if (analog.iqU_1>=edrk.iqMAX_U_ZPT_Global)
|
|
edrk.errors.e0.bits.U_1_MAX |= 1;
|
|
|
|
if (analog.iqU_2>=edrk.iqMAX_U_ZPT_Global)
|
|
edrk.errors.e0.bits.U_2_MAX |= 1;
|
|
|
|
|
|
if (analog.iqU_1>=edrk.iqMAX_U_ZPT)
|
|
edrk.errors.e0.bits.U_1_MAX |= 1;
|
|
|
|
|
|
if (analog.iqU_2>=edrk.iqMAX_U_ZPT)
|
|
edrk.errors.e0.bits.U_2_MAX |= 1;
|
|
|
|
|
|
if (edrk.from_shema_filter.bits.QTV_ON_OFF == 1
|
|
// && edrk.to_shema.bits.QTV_ON
|
|
)
|
|
{
|
|
if (analog.iqU_1<=edrk.iqMIN_U_ZPT)
|
|
edrk.errors.e0.bits.U_1_MIN |= 1;
|
|
|
|
if (analog.iqU_2<=edrk.iqMIN_U_ZPT)
|
|
edrk.errors.e0.bits.U_2_MIN |= 1;
|
|
}
|
|
|
|
err = (edrk.errors.e0.bits.U_1_MAX || edrk.errors.e0.bits.U_2_MAX || edrk.errors.e0.bits.U_1_MIN || edrk.errors.e0.bits.U_2_MIN);
|
|
return err;
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
int detect_error_u_zpt(void)
|
|
{
|
|
int err;
|
|
|
|
err = 0;
|
|
|
|
if (edrk.iqMAX_U_ZPT>MINIMAL_LEVEL_ZAD_U)
|
|
{
|
|
if (analog.iqU_1>=edrk.iqMAX_U_ZPT_Global)
|
|
edrk.errors.e0.bits.U_1_MAX |= 1;
|
|
|
|
if (analog.iqU_2>=edrk.iqMAX_U_ZPT_Global)
|
|
edrk.errors.e0.bits.U_2_MAX |= 1;
|
|
}
|
|
|
|
|
|
if (edrk.iqMAX_U_ZPT>MINIMAL_LEVEL_ZAD_U && edrk.from_shema_filter.bits.QTV_ON_OFF == 1
|
|
// && edrk.to_shema.bits.QTV_ON
|
|
)
|
|
{
|
|
if (analog.iqU_1>=edrk.iqMAX_U_ZPT)
|
|
edrk.errors.e0.bits.U_1_MAX |= 1;
|
|
|
|
|
|
if (analog.iqU_2>=edrk.iqMAX_U_ZPT)
|
|
edrk.errors.e0.bits.U_2_MAX |= 1;
|
|
}
|
|
|
|
if (edrk.from_shema_filter.bits.QTV_ON_OFF == 1
|
|
//&& edrk.to_shema.bits.QTV_ON
|
|
)
|
|
{
|
|
if (analog.iqU_1<=edrk.iqMIN_U_ZPT)
|
|
edrk.errors.e0.bits.U_1_MIN |= 1;
|
|
|
|
if (analog.iqU_2<=edrk.iqMIN_U_ZPT)
|
|
edrk.errors.e0.bits.U_2_MIN |= 1;
|
|
}
|
|
|
|
err = (edrk.errors.e0.bits.U_1_MAX || edrk.errors.e0.bits.U_2_MAX || edrk.errors.e0.bits.U_1_MIN || edrk.errors.e0.bits.U_2_MIN);
|
|
return err;
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
///////////////////////////////////////////////
|
|
int detect_error_u_zpt_on_predzaryad(void)
|
|
{
|
|
int err;
|
|
|
|
err = 0;
|
|
|
|
if (edrk.iqMAX_U_ZPT>MINIMAL_LEVEL_ZAD_U)
|
|
{
|
|
if (analog.iqU_1>=edrk.iqMAX_U_ZPT_Predzaryad)
|
|
edrk.errors.e0.bits.U_1_MAX |= 1;
|
|
|
|
|
|
if (analog.iqU_2>=edrk.iqMAX_U_ZPT_Predzaryad)
|
|
edrk.errors.e0.bits.U_2_MAX |= 1;
|
|
}
|
|
|
|
err = (edrk.errors.e0.bits.U_1_MAX || edrk.errors.e0.bits.U_2_MAX || edrk.errors.e0.bits.U_1_MIN || edrk.errors.e0.bits.U_2_MIN);
|
|
return err;
|
|
|
|
}
|
|
|
|
///////////////////////////////////////////////
|
|
#pragma CODE_SECTION(detect_error_u_in,".fast_run");
|
|
int detect_error_u_in(void)
|
|
{
|
|
int err;
|
|
static unsigned int count_err_on = 0;
|
|
|
|
err = 0;
|
|
|
|
if (edrk.iqMAX_U_ZPT>MINIMAL_LEVEL_ZAD_U)
|
|
{
|
|
if (filter.iqUin_m1>=edrk.iqMAX_U_IN)
|
|
edrk.errors.e0.bits.U_IN_MAX |= 1;
|
|
|
|
|
|
if (filter.iqUin_m2>=edrk.iqMAX_U_IN)
|
|
edrk.errors.e0.bits.U_IN_MAX |= 1;
|
|
}
|
|
|
|
if (edrk.from_shema_filter.bits.QTV_ON_OFF == 1 && edrk.SumSbor
|
|
// && edrk.to_shema.bits.QTV_ON
|
|
)
|
|
{
|
|
if (control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_QTV]==1)
|
|
{
|
|
err = 0;
|
|
}
|
|
else
|
|
{
|
|
if ((filter.iqUin_m1<=edrk.iqMIN_U_IN) || (filter.iqUin_m2<=edrk.iqMIN_U_IN))
|
|
err = 1;
|
|
else
|
|
err = 0;
|
|
}
|
|
|
|
#if (WORK_ON_STEND_D)
|
|
if (err)
|
|
{
|
|
if (pause_detect_error(&count_err_on,TIME_WAIT_ERROR_QTV,1))
|
|
edrk.errors.e0.bits.U_IN_MIN |= 1;
|
|
}
|
|
else
|
|
count_err_on = 0;
|
|
|
|
|
|
|
|
#else
|
|
|
|
edrk.errors.e0.bits.U_IN_MIN |= err;
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
err = (edrk.errors.e0.bits.U_IN_MAX || edrk.errors.e0.bits.U_IN_MIN );
|
|
return err;
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
#define MAX_WAIT_AFTER_KVITIR 100//50
|
|
void detect_error_all(void)
|
|
{
|
|
unsigned int pause_after_kvitir=0;
|
|
|
|
|
|
if (f.count_wait_after_kvitir<=MAX_WAIT_AFTER_KVITIR)
|
|
{
|
|
f.count_wait_after_kvitir++;
|
|
pause_after_kvitir = 0;
|
|
}
|
|
else
|
|
pause_after_kvitir = 1;
|
|
|
|
|
|
|
|
detect_error_ute4ka_water();
|
|
// detect_error_t_vipr();
|
|
detect_error_power_upc();
|
|
detect_error_op_pit();
|
|
|
|
detect_error_pump_2();
|
|
detect_error_pump_1();
|
|
|
|
if (edrk.warnings.e5.bits.PUMP_1 && edrk.warnings.e5.bits.PUMP_2)
|
|
{
|
|
edrk.errors.e5.bits.PUMP_1 |= 1;
|
|
edrk.errors.e5.bits.PUMP_2 |= 1;
|
|
}
|
|
|
|
detect_error_pre_ready_pump();
|
|
detect_error_fan();
|
|
detect_error_qtv();
|
|
detect_error_pre_charge();
|
|
detect_error_block_izol();
|
|
detect_error_nagrev();
|
|
detect_error_ground();
|
|
detect_error_ump();
|
|
|
|
|
|
// äëÿ àâàðèè â äðóãîé Ï× èñêëþ÷àåì àâàðèþ èç ýòîãîæå Ï×, èíà÷å ïîëó÷àåì êîëüöî. Àâàðèè çàìûêàþòñÿ!
|
|
if (pause_after_kvitir)
|
|
{
|
|
detect_error_from_knopka_avaria();
|
|
detect_error_from_another_bs();
|
|
}
|
|
|
|
#if (_FLOOR6==1)
|
|
|
|
#else
|
|
detect_error_p_water();
|
|
#endif
|
|
|
|
detect_error_t_water();
|
|
detect_error_t_air();
|
|
detect_error_t_u();
|
|
detect_error_acdrive_bear();
|
|
detect_error_acdrive_winding();
|
|
detect_error_block_qtv_from_svu();
|
|
detect_error_block_door();
|
|
|
|
|
|
detect_error_optical_bus();
|
|
detect_error_sync_bus();
|
|
detect_alive_another_bs();
|
|
|
|
edrk.warning = get_common_state_warning();
|
|
edrk.overheat = get_common_state_overheat();
|
|
|
|
edrk.warnings.e10.bits.WARNING_I_OUT_OVER_1_6_NOMINAL = out_I_over_1_6.overload_detected;
|
|
|
|
// edrk.errors.e7.bits.ANOTHER_BS_ALARM |= optical_read_data.data.cmd.bit.alarm;
|
|
detect_error_sensor_rotor();
|
|
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
void clear_errors(void)
|
|
{
|
|
|
|
clear_errors_master_slave();
|
|
clear_sync_error();
|
|
|
|
edrk.errors.e0.all = 0;
|
|
edrk.errors.e1.all = 0;
|
|
edrk.errors.e2.all = 0;
|
|
edrk.errors.e3.all = 0;
|
|
edrk.errors.e4.all = 0;
|
|
edrk.errors.e5.all = 0;
|
|
edrk.errors.e6.all = 0;
|
|
edrk.errors.e7.all = 0;
|
|
edrk.errors.e8.all = 0;
|
|
edrk.errors.e9.all = 0;
|
|
edrk.errors.e10.all = 0;
|
|
edrk.errors.e11.all = 0;
|
|
edrk.errors.e12.all = 0;
|
|
|
|
// edrk.errors.e0.all = 0;
|
|
// edrk.errors.e0.all = 0;
|
|
edrk.Stop = 0;
|
|
|
|
edrk.count_lost_interrupt = 0;
|
|
|
|
f.count_wait_after_kvitir = 0;
|
|
|
|
|
|
}
|
|
///////////////////////////////////////////////
|
|
void clear_warnings(void)
|
|
{
|
|
|
|
edrk.warnings.e0.all = 0;
|
|
edrk.warnings.e1.all = 0;
|
|
edrk.warnings.e2.all = 0;
|
|
edrk.warnings.e3.all = 0;
|
|
edrk.warnings.e4.all = 0;
|
|
edrk.warnings.e5.all = 0;
|
|
edrk.warnings.e6.all = 0;
|
|
edrk.warnings.e7.all = 0;
|
|
edrk.warnings.e8.all = 0;
|
|
edrk.warnings.e9.all = 0;
|
|
edrk.warnings.e10.all = 0;
|
|
edrk.warnings.e11.all = 0;
|
|
edrk.warnings.e12.all = 0;
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////
|
|
//////////////////////////////////////////////////////////
|
|
void read_plane_errors(void)
|
|
{
|
|
if (project.controller.read.errors.bit.pwm_wdog)
|
|
edrk.errors.e9.bits.ERR_PWM_WDOG |= 1;
|
|
|
|
#if USE_TK_0
|
|
//af1
|
|
if (project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_ack ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_current ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_ack ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_current ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_ack ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_current ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_ack ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_current ||
|
|
project.cds_tk[0].read.sbus.time_err_tk_all.bit.tk_3210 ||
|
|
project.cds_tk[0].read.sbus.lock_status_error.bit.line_err_keys_3210)
|
|
edrk.errors.e6.bits.UO2_KEYS |= 1;
|
|
//af2
|
|
if (project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_ack ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_current ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_ack ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_current ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_ack ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_current ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_ack ||
|
|
project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_current ||
|
|
project.cds_tk[0].read.sbus.time_err_tk_all.bit.tk_7654 ||
|
|
project.cds_tk[0].read.sbus.lock_status_error.bit.line_err_keys_7654)
|
|
edrk.errors.e6.bits.UO3_KEYS |= 1;
|
|
#endif
|
|
|
|
#if USE_TK_1
|
|
//af3
|
|
if (project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_ack ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_current ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_ack ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_current ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_ack ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_current ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_ack ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_current ||
|
|
project.cds_tk[1].read.sbus.time_err_tk_all.bit.tk_3210 ||
|
|
project.cds_tk[1].read.sbus.lock_status_error.bit.line_err_keys_3210)
|
|
edrk.errors.e6.bits.UO4_KEYS |= 1;
|
|
//af4
|
|
if (project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_ack ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_current ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_ack ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_current ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_ack ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_current ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_ack ||
|
|
project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_current ||
|
|
project.cds_tk[1].read.sbus.time_err_tk_all.bit.tk_7654 ||
|
|
project.cds_tk[1].read.sbus.lock_status_error.bit.line_err_keys_7654)
|
|
edrk.errors.e6.bits.UO5_KEYS |= 1;
|
|
#endif
|
|
|
|
#if USE_TK_2
|
|
//af5
|
|
if (project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_ack ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_current ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_ack ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_current ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_ack ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_current ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_ack ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_current ||
|
|
project.cds_tk[2].read.sbus.time_err_tk_all.bit.tk_3210 ||
|
|
project.cds_tk[2].read.sbus.lock_status_error.bit.line_err_keys_3210)
|
|
edrk.errors.e6.bits.UO6_KEYS |= 1;
|
|
//af6
|
|
if (project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_ack ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_current ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_ack ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_current ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_ack ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_current ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_ack ||
|
|
project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_current ||
|
|
project.cds_tk[2].read.sbus.time_err_tk_all.bit.tk_7654 ||
|
|
project.cds_tk[2].read.sbus.lock_status_error.bit.line_err_keys_7654)
|
|
edrk.errors.e6.bits.UO7_KEYS |= 1;
|
|
|
|
|
|
#endif
|
|
|
|
#if USE_TK_3
|
|
|
|
if (project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_ack ||
|
|
project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_current ||
|
|
project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_ack ||
|
|
project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_current ||
|
|
project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk2_ack ||
|
|
project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk2_current ||
|
|
project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk3_ack ||
|
|
project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk3_current ||
|
|
project.cds_tk[3].read.sbus.time_err_tk_all.bit.tk_3210 ||
|
|
project.cds_tk[3].read.sbus.lock_status_error.bit.line_err_keys_3210)
|
|
edrk.errors.e6.bits.UO1_KEYS |= 1;
|
|
|
|
#endif
|
|
|
|
//all errors local status
|
|
|
|
|
|
#if USE_TK_0
|
|
if (project.cds_tk[0].read.sbus.lock_status_error.bit.err0_local)
|
|
edrk.errors.e4.bits.ERR_TK_0 |= 1;
|
|
#endif
|
|
#if USE_TK_1
|
|
if (project.cds_tk[1].read.sbus.lock_status_error.bit.err0_local)
|
|
edrk.errors.e4.bits.ERR_TK_1 |= 1;
|
|
#endif
|
|
#if USE_TK_2
|
|
if (project.cds_tk[2].read.sbus.lock_status_error.bit.err0_local)
|
|
edrk.errors.e4.bits.ERR_TK_2 |= 1;
|
|
#endif
|
|
#if USE_TK_3
|
|
if (project.cds_tk[3].read.sbus.lock_status_error.bit.err0_local)
|
|
edrk.errors.e4.bits.ERR_TK_3 |= 1;
|
|
#endif
|
|
|
|
|
|
#if USE_IN_0
|
|
if (project.cds_in[0].read.sbus.lock_status_error.bit.err0_local)
|
|
edrk.errors.e4.bits.ERR_IN_0 |= 1;
|
|
#endif
|
|
#if USE_IN_1
|
|
if (project.cds_in[1].read.sbus.lock_status_error.bit.err0_local)
|
|
edrk.errors.e4.bits.ERR_IN_1 |= 1;
|
|
#endif
|
|
|
|
#if USE_OUT_0
|
|
if (project.cds_out[0].read.sbus.lock_status_error.bit.err0_local)
|
|
edrk.errors.e4.bits.ERR_OUT_0 |= 1;
|
|
#endif
|
|
|
|
#if USE_ADC_0
|
|
if (project.adc[0].read.sbus.lock_status_error.all)
|
|
edrk.errors.e4.bits.ERR_ADC_0 |= 1;
|
|
#endif
|
|
#if USE_ADC_1
|
|
if (project.adc[1].read.sbus.lock_status_error.all)
|
|
edrk.errors.e4.bits.ERR_ADC_1 |= 1;
|
|
#endif
|
|
//
|
|
if (project.controller.read.errors.bit.status_er0)
|
|
edrk.errors.e5.bits.LINE_ERR0 |= 1;
|
|
if (project.controller.read.errors.bit.errHWP_trig)
|
|
edrk.errors.e5.bits.LINE_HWP |= 1;
|
|
|
|
if (project.controller.read.errors.bit.error_pbus
|
|
|| project.controller.read.errors_buses.bit.slave_addr_error
|
|
|| project.controller.read.errors_buses.bit.count_error_pbus
|
|
|| project.x_parallel_bus->flags.bit.error)
|
|
edrk.errors.e6.bits.ERR_PBUS |= 1;
|
|
|
|
if (project.controller.read.errors_buses.bit.err_sbus)
|
|
edrk.errors.e6.bits.ERR_SBUS |= 1;
|
|
|
|
///
|
|
|
|
#if USE_HWP_0
|
|
if (project.hwp[0].read.comp_s.minus.all || project.hwp[0].read.comp_s.plus.all)
|
|
edrk.errors.e1.bits.HWP_ERROR |= 1;
|
|
#endif
|
|
|
|
|
|
#if USE_TK_0
|
|
if (project.all_status_plates.tk0 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_TK_0 |= 1;
|
|
#endif
|
|
#if USE_TK_1
|
|
if (project.all_status_plates.tk1 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_TK_1 |= 1;
|
|
#endif
|
|
#if USE_TK_2
|
|
if (project.all_status_plates.tk2 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_TK_2 |= 1;
|
|
#endif
|
|
#if USE_TK_3
|
|
if (project.all_status_plates.tk3 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_TK_3 |= 1;
|
|
#endif
|
|
|
|
#if USE_ADC_0
|
|
if (project.all_status_plates.adc0 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_ADC_0 |= 1;
|
|
#endif
|
|
#if USE_ADC_1
|
|
if (project.all_status_plates.adc1 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_ADC_1 |= 1;
|
|
#endif
|
|
|
|
#if USE_HWP_0
|
|
if (project.all_status_plates.hwp0 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_HWP_0 |= 1;
|
|
#endif
|
|
|
|
#if USE_IN_0
|
|
if (project.all_status_plates.in0 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_IN_0 |= 1;
|
|
#endif
|
|
#if USE_IN_1
|
|
if (project.all_status_plates.in1 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_IN_1 |= 1;
|
|
#endif
|
|
|
|
#if USE_OUT_0
|
|
if (project.all_status_plates.out0 != component_Ready)
|
|
edrk.errors.e3.bits.NOT_READY_OUT_0 |= 1;
|
|
#endif
|
|
}
|
|
|
|
int get_common_state_warning() {
|
|
return edrk.warnings.e0.all != 0 || edrk.warnings.e1.all != 0 ||
|
|
edrk.warnings.e2.all != 0 || edrk.warnings.e3.all != 0 ||
|
|
edrk.warnings.e4.all != 0 || edrk.warnings.e5.all != 0 ||
|
|
edrk.warnings.e6.all != 0 || edrk.warnings.e7.all != 0 ||
|
|
edrk.warnings.e8.all != 0 || edrk.warnings.e9.all != 0 ||
|
|
edrk.warnings.e10.all != 0 || edrk.warnings.e11.all != 0 ||
|
|
edrk.warnings.e12.all != 0 ? 1 : 0;
|
|
}
|
|
|
|
int get_common_state_overheat() {
|
|
return edrk.warnings.e2.bits.T_AIR0_MAX | edrk.warnings.e2.bits.T_AIR1_MAX |
|
|
edrk.warnings.e2.bits.T_AIR2_MAX | edrk.warnings.e2.bits.T_AIR3_MAX |
|
|
edrk.warnings.e2.bits.T_UO1_MAX | edrk.warnings.e2.bits.T_UO2_MAX |
|
|
edrk.warnings.e2.bits.T_UO3_MAX | edrk.warnings.e2.bits.T_UO4_MAX |
|
|
edrk.warnings.e2.bits.T_UO5_MAX | edrk.warnings.e2.bits.T_UO6_MAX |
|
|
edrk.warnings.e2.bits.T_UO7_MAX | edrk.warnings.e2.bits.T_WATER_EXT_MAX |
|
|
edrk.warnings.e2.bits.T_WATER_INT_MAX |
|
|
edrk.errors.e2.bits.T_AIR0_MAX | edrk.errors.e2.bits.T_AIR1_MAX |
|
|
edrk.errors.e2.bits.T_AIR2_MAX | edrk.errors.e2.bits.T_AIR3_MAX |
|
|
edrk.errors.e2.bits.T_UO1_MAX | edrk.errors.e2.bits.T_UO2_MAX |
|
|
edrk.errors.e2.bits.T_UO3_MAX | edrk.errors.e2.bits.T_UO4_MAX |
|
|
edrk.errors.e2.bits.T_UO5_MAX | edrk.errors.e2.bits.T_UO6_MAX |
|
|
edrk.errors.e2.bits.T_UO7_MAX | edrk.errors.e2.bits.T_WATER_EXT_MAX |
|
|
edrk.errors.e2.bits.T_WATER_INT_MAX;
|
|
}
|
|
|