871 lines
19 KiB
C
871 lines
19 KiB
C
#include <project.h>
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#include "DSP281x_Examples.h" // DSP281x Examples Include File
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#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File
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#include "DSP281x_Device.h"
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#include "MemoryFunctions.h"
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#include "Spartan2E_Adr.h"
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//#include "xerror.h"
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//#include "SpaceVectorPWM.h"
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//#include "v_pwm24_v2.h"
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//#include "PWMTools.h"
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#define SelectLoadXilinx() WriteOper(0,0,0,1)
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//#define TypeAccess_Is_SerialBus 21
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#define dat_xilinx_line_do(bitb) \
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GpioDataRegs.GPEDAT.bit.GPIOE0=bitb
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#define setup_xilinx_line_do_on() \
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GpioMuxRegs.GPEDIR.bit.GPIOE0=1;\
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GpioDataRegs.GPEDAT.bit.GPIOE0=1
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#define reset_xilinx() WriteOper(1,1,0,1)
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#define XSEEPROM_WRITE_REPEAT 3
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#define XSEEPROM_READ_REPEAT 3
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#define XSEEPROM_MAX_ERROR_CONSECUTIVE_FRAME 20 // threshold
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#define XSEEPROM_MIN_LENTH 7 // max 7 => 1 word = 2 byte
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#define XSEEPROM_MAX_ERROR_CONSECUTIVE_BREAK (XSEEPROM_MAX_ERROR_CONSECUTIVE_FRAME + 10)
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#define xseeprom_pause { }
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#pragma DATA_SECTION(xeeprom_controll_fast,".fast_vars");
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unsigned int xeeprom_controll_fast;
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//XSerial_bus XSerial_bus0;
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//Xmemory_uni Xmemory_uni0;
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//XSerial_bus_stats XSerial_bus_stats0;
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#pragma DATA_SECTION(Controll, ".fast_vars");
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XControll_reg Controll;
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unsigned int xeeprom_controll_store;
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void write_bit_xilinx(unsigned char bitb);
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int xseeprom_read_all(unsigned int Mode_is_Verify, XSeeprom_t * Ptr);
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int xseeprom_write_all(XSeeprom_t * Ptr);
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void xseeprom_adr(unsigned int adr);
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//unsigned int xseeprom_case_xilinx (void);
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void xseeprom_delay(void);
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void xseeprom_init(void);
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void xControll_wr();
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unsigned int xseeprom_read_byte(unsigned int use_ack);
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void xseeprom_set_mode_ON (unsigned int set_mode);
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void xseeprom_start(void);
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void xseeprom_stop(void);
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void xseeprom_undo (void);
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unsigned int xseeprom_write_byte(unsigned int byte);
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void xseeprom_clk (unsigned int clk);
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unsigned int xseeprom_din (void);
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void xseeprom_dout (unsigned int data);
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void xseeprom_mode_wr (unsigned int mode);
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void ResetPeriphPlane();
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unsigned int time = 0;
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void write_byte_xilinx(unsigned char bx)
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{
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int i;
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for (i=0;i<=7;i++)
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write_bit_xilinx( (bx >> i) & 1);
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}
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void write_bit_xilinx(unsigned char bitb)
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{
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pause_1000(1);
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EALLOW;
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GpioDataRegs.GPBDAT.bit.GPIOB8=1;
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dat_xilinx_line_do(bitb);
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pause_1000(1);
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GpioDataRegs.GPBDAT.bit.GPIOB8=0;
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pause_1000(1);
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GpioDataRegs.GPBDAT.bit.GPIOB8=1;
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EDIS;
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}
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void setup_xilinx_line()
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{
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EALLOW;
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GpioMuxRegs.GPBMUX.bit.CAP4Q1_GPIOB8=0;
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GpioMuxRegs.GPAMUX.bit.CAP2Q2_GPIOA9=0;
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GpioMuxRegs.GPBDIR.bit.GPIOB8=1;
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GpioMuxRegs.GPADIR.bit.GPIOA9=0;
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GpioDataRegs.GPBDAT.bit.GPIOB8=1;
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// init line
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GpioMuxRegs.GPEMUX.bit.XNMI_XINT13_GPIOE2=0; // as io
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GpioMuxRegs.GPEDIR.bit.GPIOE2 = 0; // as input
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setup_xilinx_line_do_on();
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EDIS;
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}
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unsigned int read_init_xilinx()
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{
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unsigned int i;
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EALLOW;
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i=GpioDataRegs.GPEDAT.bit.GPIOE2;
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EDIS;
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return (i);
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}
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unsigned int read_done_xilinx()
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{
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unsigned int i;
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EALLOW;
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i=GpioDataRegs.GPADAT.bit.GPIOA9;
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EDIS;
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return (i);
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}
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long xverify_remote_eeprom(unsigned int adr_device, unsigned long adr,
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unsigned long adr_eeprom, unsigned long size, unsigned long *ok_write,
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unsigned long *write_error, unsigned long *repeat_error )
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{
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int i;
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static XSeeprom_t rom;
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unsigned long repeat_er=0;
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unsigned int er_wr=0;
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unsigned int er_rd=0;
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rom.Adr_device=adr_device;
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rom.Adr=adr;
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rom.Adr_seeprom=adr_eeprom;
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rom.size=size;
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if (er_wr)
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return 0;
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for (i=0; i<XSEEPROM_WRITE_REPEAT; i++) {
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er_rd=xseeprom_read_all(1,&rom);
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repeat_er+=rom.repeat_error;
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if((rom.repeat_error==0) && (er_rd==0))
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break;
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}
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*ok_write=rom.ok_write;
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*repeat_error=repeat_er;
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*write_error=((unsigned long)(rom.write_error<<8)) | ((unsigned long)(er_wr & 0x000f)) | ((unsigned long)(er_rd<<4 & 0x00f0));
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if (rom.write_error != 0)
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xerror(xseeprom_er_ID(3),(void *)0);
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if(er_rd!=0)
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xerror(xseeprom_er_ID(2),(void *)0);
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return 0;
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}
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long xread_remote_eeprom(unsigned int adr_device, unsigned long adr_eeprom,
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unsigned long adr, unsigned long size, unsigned long *ok_write,
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unsigned long *write_error, unsigned long *repeat_error ){
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int i;
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static XSeeprom_t rom;
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unsigned int er_wr=0;
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unsigned int er_rd=0;
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unsigned long repeat_er=0;
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rom.Adr_device=adr_device;
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rom.Adr=adr;
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rom.Adr_seeprom=adr_eeprom;
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rom.size=size;
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for (i=0; i<XSEEPROM_WRITE_REPEAT; i++) {
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er_rd=xseeprom_read_all(0,&rom);
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repeat_er+=rom.repeat_error;
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if((rom.repeat_error==0) && (er_rd==0))
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break;
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}
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*ok_write=rom.ok_write;
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*repeat_error=repeat_er;
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*write_error=(unsigned long)((er_wr & 0x000f) | (er_rd<<4 & 0x00f0));
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if(er_rd!=0)
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xerror(xseeprom_er_ID(2),(void *)0);
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return 0;
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}
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int xflash_remote_eeprom(unsigned int adr_device, unsigned long adr,
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unsigned long adr_eeprom, unsigned long size, unsigned long *ok_write,
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unsigned long *write_error, unsigned long *repeat_error )
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{
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int i;
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static XSeeprom_t rom;
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unsigned long repeat_er=0;
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unsigned int er_wr=0;
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unsigned int er_rd=0;
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unsigned int old_started=0;
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rom.Adr_device=adr_device;
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rom.Adr=adr;
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rom.Adr_seeprom=adr_eeprom;
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rom.size=size;
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old_started = x_parallel_bus_project.flags.bit.started;
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project_stop_parallel_bus();
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xseeprom_set_mode_ON(1); // on work with Spartan200E
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for (i=0; i<XSEEPROM_WRITE_REPEAT; i++) {
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er_wr=xseeprom_write_all(&rom);
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repeat_er+=rom.repeat_error;
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if((rom.repeat_error==0) && (er_wr==0))
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break;
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}
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*ok_write=rom.ok_write;
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*repeat_error=repeat_er;
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*write_error=(unsigned long)((er_wr & 0x000f) | (er_rd<<4 & 0x00f0));
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if(er_wr)
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return xerror(xseeprom_er_ID(1),(void *)0);
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// if (er_wr)
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// return 0;
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for (i=0; i<XSEEPROM_WRITE_REPEAT; i++) {
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er_rd=xseeprom_read_all(1,&rom);
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repeat_er+=rom.repeat_error;
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if((rom.repeat_error==0) && (er_rd==0))
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break;
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}
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xseeprom_set_mode_ON(0);
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*ok_write=rom.ok_write;
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*repeat_error=repeat_er;
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*write_error=((unsigned long)(rom.write_error<<8)) | ((unsigned long)(er_wr & 0x000f)) | ((unsigned long)(er_rd<<4 & 0x00f0));
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if(er_rd)
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xerror(xseeprom_er_ID(2),(void *)0);
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if (rom.write_error)
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xerror(xseeprom_er_ID(3),(void *)0);
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project_reload_all_plates(WITHOUT_RESET_ALL_PLATES_NO_STOP_ERROR);//wait_start_cds + load_cfg
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i_WriteMemory(ADR_BUS_ERROR_READ, 0);
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if(i_ReadMemory(ADR_ERRORS_TOTAL_INFO)) //<2F><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.
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{
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// xerror(main_er_ID(1),(void *)0);
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}
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i_WriteMemory(ADR_CONTR_REG_FOR_WRITE, 0xffff);
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if (old_started)
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project_start_parallel_bus();
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return 0; // no error
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}
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int load_xilinx_new(unsigned long adr,unsigned long size)
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{
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unsigned int wx;
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unsigned long adr_x;
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unsigned long adr_int;
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unsigned int done_line;
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volatile unsigned int Value;
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setup_xilinx_line();
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reset_xilinx();
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pause_1000(100);
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// controll levels on line INIT and DONE
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Value=read_init_xilinx(); // there must be level '0'
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if(Value != 0)
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return xerror(xtools_er_ID(1),(void *)0);
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Value=read_done_xilinx(); // there must be level '0'
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if(Value != 0)
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return xerror(xtools_er_ID(2),(void *)0);
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SelectLoadXilinx();
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pause_1000(100);
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Value=read_init_xilinx(); // there must be level '1'
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if(Value != 1)
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return xerror(xtools_er_ID(1),(void *)0);
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// down peripheral frequency
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// Clk_mode_store=XintfRegs.XINTCNF2.bit.CLKMODE;
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// xfrequency_peripheral_is_slow(1);
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adr_int= size+1-10;
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// fast part of loading
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for (adr_x=0;adr_x<adr_int;adr_x++)
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{
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wx=i_ReadMemory(adr_x+adr);
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write_byte_xilinx( (wx>>8) & 0xff);
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write_byte_xilinx( wx & 0xff);
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}
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// slow part of loading
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adr_x=adr_int;
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wx=i_ReadMemory(adr_x+adr);
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write_byte_xilinx( (wx>>8) & 0xff);
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pause_1000(10000);
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write_byte_xilinx( wx & 0xff);
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pause_1000(10000);
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adr_int++;
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// final part of loading
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for (adr_x=adr_int;adr_x<(size+1);adr_x++)
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{
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unsigned int bx;
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int i;
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done_line=read_done_xilinx();
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if(done_line==1)
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break;
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wx=i_ReadMemory(adr_x+adr);
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bx=(wx>>8) & 0xff;
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for (i=0;i<=7;i++)
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{
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write_bit_xilinx( (bx >> i) & 1);
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done_line=read_done_xilinx();
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if(done_line==1)
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break;
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}
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if(done_line==1)
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break;
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wx=i_ReadMemory(adr_x+adr);
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bx= wx & 0xff;
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for (i=0;i<=7;i++)
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{
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write_bit_xilinx( (bx >> i) & 1);
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done_line=read_done_xilinx();
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if(done_line==1)
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break;
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}
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if(done_line==1)
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break;
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}
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// configure line DO as input
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// EALLOW;
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// setup_xilinx_line_do_off();
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// EDIS;
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// activation part of loading
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// restore peripheral frequency
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// xfrequency_peripheral_is_slow(Clk_mode_store);
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// DONE activate on clock 2
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write_bit_xilinx(1); // clock 3, activate GWE
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write_bit_xilinx(1); // clock 4, activate GSR
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write_bit_xilinx(1); // clock 5, activate GTS. Led is work.
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write_bit_xilinx(1); // clock 6, activate DLL
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write_bit_xilinx(0); // clock 7
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write_bit_xilinx(1);
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pause_1000(100);
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write_bit_xilinx(0);
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pause_1000(100);
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// controll line DONE
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Value=read_done_xilinx(); // there must be level '1'
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if(Value != 1)
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return xerror(xtools_er_ID(2),(void *)0);
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// pause for DLL in Xilinx
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pause_1000(10000);
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return 0;
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}
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int xseeprom_write_all(XSeeprom_t * Ptr)
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{
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union XSeeprom_command_reg command;
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unsigned int data;
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unsigned int i;
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unsigned int er=0;
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unsigned long er_ack=0;
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unsigned int er_for_one_pack=0;
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unsigned int er_consecutive=0;
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unsigned long adr_x=Ptr->Adr;
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unsigned long adr_eeprom=Ptr->Adr_seeprom;
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unsigned int count_word=128;
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unsigned int wx;
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command.bit.bit7=1;
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command.bit.bit6=0;
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command.bit.bit5=1;
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command.bit.bit4=0;
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command.bit.bit3=0;
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command.bit.A1=1;
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command.bit.WR0=0;
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Ptr->ok_write=0;
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Ptr->repeat_error=0;
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Ptr->write_error=0;
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xseeprom_init();
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pause_1000(100);
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xseeprom_adr(Ptr->Adr_device);
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// xseeprom_set_mode_ON(1);
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xeeprom_controll_fast=Controll.all;
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pause_1000(100);
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while ((adr_x-Ptr->Adr)<(Ptr->size)) { // while size
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er=0;
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for(;;){
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Led2_Toggle();
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xseeprom_start();
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command.bit.P0=(adr_eeprom>>15 & 0x0001);
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er=xseeprom_write_byte(command.all);
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if(er)
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break;
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data=adr_eeprom>>7 & 0x00ff;
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er=xseeprom_write_byte(data);
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if(er)
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break;
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data=adr_eeprom<<1 & 0x00ff;
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er=xseeprom_write_byte(data);
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break;
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}
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i=0;
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while ( (i<count_word) && (er == 0) && ((adr_x+i-Ptr->Adr)<(Ptr->size)) && ((adr_eeprom<<1 & 0x00ff)+2*i < 0x00ff) ) {
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wx=i_ReadMemory(adr_x+i);
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er=xseeprom_write_byte(wx>>8);
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if(er)
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break;
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er=xseeprom_write_byte(wx);
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if(er)
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break;
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i+=1;
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}
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xseeprom_stop();
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xseeprom_delay();
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if (er == 0) {
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adr_x+=i;
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adr_eeprom+=i;
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Ptr->ok_write+=i;
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er_consecutive=0;
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} else {
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er_consecutive++;
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er_ack++;
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if (er_consecutive > XSEEPROM_MAX_ERROR_CONSECUTIVE_FRAME) {
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if (er_for_one_pack < XSEEPROM_MIN_LENTH) {
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er_for_one_pack +=1;
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er_consecutive=0;
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}
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}
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Led1_Toggle();
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}
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switch (er_for_one_pack) {
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case 0 : count_word = 128; break;
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case 1 : count_word = 64; break;
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case 2 : count_word = 32; break;
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case 3 : count_word = 16; break;
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case 4 : count_word = 8; break;
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case 5 : count_word = 4; break;
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case 6 : count_word = 2; break;
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case 7 : count_word = 1; break;
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default : break;
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}
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Ptr->repeat_error=er_ack;
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if(er_consecutive > XSEEPROM_MAX_ERROR_CONSECUTIVE_BREAK) {
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xseeprom_undo();
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return(4);
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}
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} // while size
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xseeprom_undo();
|
||
return 0;
|
||
}
|
||
|
||
int xseeprom_read_all(unsigned int Mode_is_Verify, XSeeprom_t * Ptr)
|
||
{
|
||
union XSeeprom_command_reg command;
|
||
unsigned int data;
|
||
// unsigned int i;
|
||
|
||
unsigned long i;
|
||
|
||
unsigned int er;
|
||
unsigned long er_ack=0;
|
||
unsigned int er_consecutive=0;
|
||
unsigned long adr_x=Ptr->Adr;
|
||
unsigned long adr_eeprom=Ptr->Adr_seeprom;
|
||
unsigned int count_word=128;
|
||
unsigned int data_rd;
|
||
unsigned int wx;
|
||
|
||
command.bit.bit7=1;
|
||
command.bit.bit6=0;
|
||
command.bit.bit5=1;
|
||
command.bit.bit4=0;
|
||
command.bit.bit3=0;
|
||
command.bit.A1=1;
|
||
|
||
Ptr->ok_write=0;
|
||
Ptr->repeat_error=0;
|
||
Ptr->write_error=0;
|
||
|
||
xseeprom_init();
|
||
xseeprom_adr(Ptr->Adr_device);
|
||
// xseeprom_set_mode_ON(1);
|
||
|
||
xeeprom_controll_fast=Controll.all;
|
||
|
||
|
||
pause_1000(100);
|
||
|
||
while ((adr_x-Ptr->Adr)<(Ptr->size)) { // while size
|
||
er=0;
|
||
for(;;){
|
||
Led2_Toggle();
|
||
xseeprom_start();
|
||
command.bit.P0=(adr_eeprom>>15 & 0x0001);
|
||
command.bit.WR0=0;
|
||
er=xseeprom_write_byte(command.all);
|
||
if(er)
|
||
break;
|
||
|
||
data=adr_eeprom>>7 & 0x00ff;
|
||
er=xseeprom_write_byte(data);
|
||
if(er)
|
||
break;
|
||
|
||
data=adr_eeprom<<1 & 0x00ff;
|
||
er=xseeprom_write_byte(data);
|
||
if(er)
|
||
break;
|
||
|
||
xseeprom_start();
|
||
command.bit.WR0=1;
|
||
er=xseeprom_write_byte(command.all);
|
||
break;
|
||
}
|
||
|
||
i=0;
|
||
while ( (i<count_word) && (er == 0) && ((adr_x-Ptr->Adr)<(Ptr->size)) && (( adr_eeprom<<1 & 0x00ff)+2*i < 0x00ff) ) {
|
||
data_rd=xseeprom_read_byte(1);
|
||
data_rd<<=8;
|
||
if( ((i+1)!=count_word) && ((adr_x-Ptr->Adr)<(Ptr->size-1)) && ((adr_eeprom<<1 & 0x00ff)+2*i+1 < 0x00ff) )
|
||
data_rd|=xseeprom_read_byte(1); // use ack
|
||
else
|
||
data_rd|=xseeprom_read_byte(0); // don't use ack
|
||
if(Mode_is_Verify==0)
|
||
{
|
||
i_WriteMemory((adr_x),data_rd);
|
||
}
|
||
else {
|
||
wx=i_ReadMemory(adr_x);
|
||
if(wx!=data_rd)
|
||
Ptr->write_error++;
|
||
}
|
||
i++;
|
||
adr_x++;
|
||
}
|
||
|
||
xseeprom_stop();
|
||
// xseeprom_delay();
|
||
|
||
if (er == 0) {
|
||
adr_eeprom+=i;
|
||
Ptr->ok_write+=i;
|
||
er_consecutive=0;
|
||
} else {
|
||
er_consecutive++;
|
||
er_ack++;
|
||
Led1_Toggle();
|
||
}
|
||
|
||
Ptr->repeat_error=er_ack;
|
||
if(er_consecutive > XSEEPROM_MAX_ERROR_CONSECUTIVE_BREAK) {
|
||
xseeprom_undo();
|
||
return(4);
|
||
}
|
||
} // while size
|
||
ResetPeriphPlane();
|
||
xseeprom_undo();
|
||
return 0;
|
||
}
|
||
|
||
void xseeprom_adr(unsigned int adr)
|
||
{
|
||
Controll.bit.line_P7_4_Sorce_Is_Tms=1;
|
||
Controll.bit.line_P7_4_Is=adr;
|
||
xControll_wr();
|
||
}
|
||
|
||
void xseeprom_delay(void)
|
||
{
|
||
pause_1000(10000);
|
||
}
|
||
|
||
void ResetPeriphPlane()
|
||
{
|
||
Controll.bit.line_P7_4_Is = 0xf;
|
||
// Controll.bit.RemotePlane_Is_Reset = 1;
|
||
xControll_wr();
|
||
pause_1000(10000);
|
||
// Controll.bit.RemotePlane_Is_Reset = 0;
|
||
Controll.bit.line_P7_4_Is = 0x0;
|
||
xControll_wr();
|
||
}
|
||
|
||
void xseeprom_init(void)
|
||
{
|
||
xeeprom_controll_store=Controll.all;
|
||
Controll.bit.line_CLKS_Sorce_Is_Tms=1;
|
||
Controll.bit.line_CLKS_Is=1;
|
||
Controll.bit.line_ER0_OUT_Sorce_Is_Tms=1;
|
||
Controll.bit.line_ER0_OUT_Is=1;
|
||
Controll.bit.line_P7_4_Sorce_Is_Tms=1;
|
||
Controll.bit.line_P7_4_Is=0xf;
|
||
Controll.bit.line_Z_ER0_OUT_Is=0; // read
|
||
Controll.bit.line_SET_MODE_Is=0; // off
|
||
// <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD>
|
||
Controll.bit.OE_BUF_Is_ON=0;//1;
|
||
// <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>
|
||
Controll.bit.RemotePlane_Is_Reset=0;
|
||
xControll_wr();
|
||
}
|
||
|
||
void xControll_wr()
|
||
{
|
||
i_WriteMemory(ADR_CONTR_REG_FOR_WRITE, Controll.all);
|
||
}
|
||
/*
|
||
unsigned int xseeprom_case_xilinx (void) {
|
||
xinput_new_uni_rd_status(&Xinput_new_uni_tms0);
|
||
return Xinput_new_uni_tms0.ChanalsPtr.ChanalPtr[XINPUT_NEW_TMS0_NUMBER_LINE_CASE_XILINX].rd_status;
|
||
}
|
||
*/
|
||
unsigned int xseeprom_read_byte(unsigned int use_ack){
|
||
int i;
|
||
unsigned int data=0;
|
||
|
||
xseeprom_dout(1);
|
||
xseeprom_mode_wr(0);
|
||
for (i=7;i>=0;i--)
|
||
{
|
||
xseeprom_pause
|
||
xseeprom_clk(1);
|
||
xseeprom_pause
|
||
data=data<<1|(xseeprom_din() & 0x0001);
|
||
xseeprom_clk(0);
|
||
xseeprom_pause
|
||
}
|
||
|
||
pause_1000(10);
|
||
|
||
xseeprom_mode_wr(1);
|
||
xseeprom_dout(!use_ack); // ack
|
||
xseeprom_pause
|
||
xseeprom_clk(1);
|
||
xseeprom_pause
|
||
xseeprom_clk(0);
|
||
xseeprom_pause
|
||
xseeprom_dout(1);
|
||
xseeprom_mode_wr(0);
|
||
|
||
|
||
pause_1000(10);
|
||
return data;
|
||
}
|
||
|
||
void xseeprom_set_mode_ON (unsigned int set_mode) {
|
||
Controll.bit.line_SET_MODE_Is=~set_mode;
|
||
xControll_wr();
|
||
}
|
||
|
||
void xseeprom_start(void) {
|
||
xseeprom_clk(1);
|
||
xseeprom_dout(1);
|
||
xseeprom_mode_wr(1);
|
||
xseeprom_pause
|
||
xseeprom_dout(0); // start
|
||
xseeprom_pause
|
||
xseeprom_clk(0);
|
||
xseeprom_pause
|
||
}
|
||
|
||
void xseeprom_stop(void) {
|
||
xseeprom_mode_wr(1);
|
||
xseeprom_dout(0);
|
||
pause_1000(10);
|
||
xseeprom_clk(1);
|
||
pause_1000(10);
|
||
xseeprom_dout(1);
|
||
pause_1000(10);
|
||
}
|
||
|
||
void xseeprom_undo (void){
|
||
Controll.all=xeeprom_controll_store;
|
||
Controll.bit.OE_BUF_Is_ON=1;
|
||
xControll_wr();
|
||
}
|
||
|
||
unsigned int xseeprom_write_byte(unsigned int byte){
|
||
int i;
|
||
unsigned int ack;
|
||
|
||
xseeprom_mode_wr(1);
|
||
for (i=7;i>=0;i--)
|
||
{
|
||
xseeprom_dout((byte >> i) & 1);
|
||
xseeprom_pause
|
||
xseeprom_clk(1);
|
||
xseeprom_pause
|
||
xseeprom_clk(0);
|
||
xseeprom_pause
|
||
}
|
||
|
||
xseeprom_dout(1);
|
||
xseeprom_mode_wr(0);
|
||
pause_1000(10);
|
||
|
||
xseeprom_pause
|
||
xseeprom_clk(1);
|
||
pause_1000(10);
|
||
xseeprom_pause
|
||
ack=xseeprom_din();
|
||
xseeprom_clk(0);
|
||
xseeprom_pause
|
||
|
||
pause_1000(10);
|
||
|
||
/*
|
||
// xseeprom_dout(1);
|
||
xseeprom_mode_wr(0);
|
||
pause_1000(10);
|
||
|
||
// xseeprom_mode_wr(0);
|
||
xseeprom_dout(1);
|
||
xseeprom_pause
|
||
xseeprom_clk(1);
|
||
xseeprom_pause
|
||
ack=xseeprom_din();
|
||
xseeprom_clk(0);
|
||
xseeprom_pause
|
||
|
||
pause_1000(10);
|
||
*/
|
||
return ack; // '0' - ok!
|
||
}
|
||
|
||
void xseeprom_clk (unsigned int clk) {
|
||
xeeprom_controll_fast&=0xfdff;
|
||
xeeprom_controll_fast|=(clk<<9 & 0x0200);
|
||
i_WriteMemory(ADR_CONTR_REG_FOR_WRITE,xeeprom_controll_fast);
|
||
}
|
||
|
||
unsigned int xseeprom_din (void) {
|
||
return (i_ReadMemory(ADR_CONTR_REG_FOR_READ)>>15 & 0x0001);
|
||
}
|
||
|
||
void xseeprom_dout (unsigned int data) {
|
||
xeeprom_controll_fast&=0xff7f;
|
||
xeeprom_controll_fast|=(data<<7 & 0x0080);
|
||
i_WriteMemory(ADR_CONTR_REG_FOR_WRITE,xeeprom_controll_fast);
|
||
}
|
||
|
||
void xseeprom_mode_wr (unsigned int mode) { // '1' - write, '0' - read
|
||
xeeprom_controll_fast&=0xffef;
|
||
xeeprom_controll_fast|=(mode<<4 & 0x0010);
|
||
i_WriteMemory(ADR_CONTR_REG_FOR_WRITE,xeeprom_controll_fast);
|
||
}
|
||
|
||
|
||
|
||
|
||
|
||
/*********************** example ******************************************
|
||
* i=xilinx_live_smart(0x5aaa);
|
||
* i=i|xilinx_live_smart(0x0000)
|
||
***************************************************************************/
|
||
unsigned int xilinx_live_smart(unsigned int d) // dout(15:0) = din(11:8) & din(15:12) & not din(7:0);
|
||
{
|
||
unsigned int dout;
|
||
unsigned int d_rd;
|
||
|
||
i_WriteMemory(ADR_XTEST_REG,d);
|
||
dout = ~d;
|
||
d_rd = i_ReadMemory(ADR_XTEST_REG);
|
||
if (d_rd!=dout)
|
||
return 1;
|
||
return 0;
|
||
}
|
||
|
||
|
||
|
||
//////////////////////////////////////////////////////////////////////
|
||
//////////////////////////////////////////////////////////////////////
|
||
//////////////////////////////////////////////////////////////////////
|
||
//////////////////////////////////////////////////////////////////////
|
||
|
||
int enable_er0_control(void)
|
||
{
|
||
return xilinx_live_smart(0x5AA5);
|
||
}
|
||
|
||
|
||
|
||
int test_xilinx_live(void)
|
||
{
|
||
unsigned int i;
|
||
//test xilinx controller on read/write operation
|
||
for(i=0;i<10000;i++)
|
||
if(xilinx_live_smart(i))
|
||
return xerror(main_er_ID(1),(void *)0);
|
||
return 0;
|
||
}
|
||
|
||
//////////////////////////////////////////////////////////////////////
|
||
//////////////////////////////////////////////////////////////////////
|
||
|
||
|
||
//////////////////////////////////////////////////////////////////////
|
||
//////////////////////////////////////////////////////////////////////
|
||
|
||
|
||
|
||
|
||
|