Razvalyaev
7e0063eee0
Все основные файлы подтянуты без изменений Изменены (только папка main_matlab): - заглушки для ненужных функций (main_matlab.c) - iq библиотека (IQmathLib_matlab.c) - библиотеки DSP281x
311 lines
7.7 KiB
C
311 lines
7.7 KiB
C
#include "x_serial_bus.h"
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#include "xp_cds_out.h"
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#include "x_serial_bus.h"
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#include "xp_tools.h"
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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void cds_out_init(T_cds_out *v)
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{
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if (v->useit == 0)
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{
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clear_adr_sync_table(v->plane_address);
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return ;
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}
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set_adr_sync_table(v->plane_address);
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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int cds_out_read_all(T_cds_out *v)
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{
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int err = 0;
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if (v->useit == 0)
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return 0;
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err = cds_out_read_sbus(v);
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err |= cds_out_read_pbus(v);
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return err;
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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int cds_out_write_all(T_cds_out *v)
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{
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int err = 0;
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if (v->useit == 0)
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return 0;
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err = cds_out_write_sbus(v);
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err |= cds_out_write_pbus(v);
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return err;
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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int cds_out_write_sbus(T_cds_out *v)
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{
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unsigned int old_err, err = 0, err_ready = 0;
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static unsigned int e;
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static unsigned int c_ok=0;
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if (v->useit == 0)
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return 0;
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e = 0;
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old_err = v->status_serial_bus.count_write_error;
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x_serial_bus_project.slave_addr = v->plane_address; // number plate
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//0 data_out
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x_serial_bus_project.reg_addr = 0; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.data_out.all; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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{
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v->status_serial_bus.count_write_error++;
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e |= 1;
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}
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//1 enable_protect_out
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x_serial_bus_project.reg_addr = 1; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.enable_protect_out.all; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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{
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v->status_serial_bus.count_write_error++;
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e |= 2;
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}
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//6 protect_error
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// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6)
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// v->write.sbus.protect_error.bit.enable_err_switch = 0; // <20><><EFBFBD> SP6 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20>.<2E>. <20><> <20><><EFBFBD> <20><><EFBFBD><EFBFBD>
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x_serial_bus_project.reg_addr = 6; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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{
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v->status_serial_bus.count_write_error++;
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e |= 4;
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}
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//7 cmd_reset_error
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/*
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x_serial_bus_project.reg_addr = 7; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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v->status_serial_bus.count_error++;
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*/
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if (old_err == v->status_serial_bus.count_write_error)// no errors
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{
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v->status_serial_bus.count_write_ok++;
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c_ok++;
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err = 0; // no errors
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}
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else
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{
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err = 1; // !errors!
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c_ok = 0;
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}
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err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus);
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set_status_cds(err_ready, &v->status);
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return err_ready;
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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int cds_out_write_pbus(T_cds_out *v)
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{
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if (v->useit == 0)
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return 0;
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return 0;
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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int cds_out_read_sbus(T_cds_out *v)
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{
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unsigned int old_err, err = 0, err_ready = 0;
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if (v->useit == 0)
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return 0;
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old_err = v->status_serial_bus.count_read_error;
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x_serial_bus_project.slave_addr = v->plane_address; // number plate
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//0 data_out
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x_serial_bus_project.reg_addr = 0; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.data_out.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//1 enable_protect_out
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x_serial_bus_project.reg_addr = 1; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.enable_protect_out.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//6 protect_error
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x_serial_bus_project.reg_addr = 6; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.protect_error.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//7 lock_status_error
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x_serial_bus_project.reg_addr = 7; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data;
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else
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v->status_serial_bus.count_read_error++;
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//15 current_status_error
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x_serial_bus_project.reg_addr = 15; // adr memory in plate
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x_serial_bus_project.read(&x_serial_bus_project); // read
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if (x_serial_bus_project.flags.bit.read_error == 0) // check error
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{
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v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1;
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v->type_cds_xilinx = v->read.type_cds_xilinx;
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v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe;
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}
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else
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v->status_serial_bus.count_read_error++;
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///////////
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if (old_err == v->status_serial_bus.count_read_error)// no errors
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{
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v->status_serial_bus.count_read_ok++;
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err = 0; // no errors
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}
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else
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err = 1; // !errors!
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err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus);
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set_status_cds(err_ready, &v->status);
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return err_ready;
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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int cds_out_read_pbus(T_cds_out *v)
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{
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if (v->useit == 0)
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return 0;
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return 0;
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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void cds_out_reset_error(T_cds_out *v)
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{
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if (v->useit == 0)
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return ;
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if (v->status == component_Error || v->status == component_ErrorSBus)
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v->status = component_Started;
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clear_cur_stat_sbus(&v->status_serial_bus);
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clear_cur_stat_pbus(&v->status_parallel_bus);
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x_serial_bus_project.slave_addr = v->plane_address; // number plate
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//7 cmd_reset_error
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x_serial_bus_project.reg_addr = 7; // adr memory in plate
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x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data
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if (x_serial_bus_project.write(&x_serial_bus_project)) // make write
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v->status_serial_bus.count_write_error++;
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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void cds_out_store_disable_error(T_cds_out *v)
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{
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if (v->useit == 0)
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return ;
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v->store_protect_error = v->write.sbus.protect_error.all;
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v->write.sbus.protect_error.all = 0; // disable all error.
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cds_out_write_sbus(v);
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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void cds_out_restore_enable_error(T_cds_out *v)
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{
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if (v->useit == 0)
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return ;
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v->write.sbus.protect_error.all = v->store_protect_error; // restore all setup error.
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cds_out_write_sbus(v);
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}
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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