Razvalyaev
7e0063eee0
Все основные файлы подтянуты без изменений Изменены (только папка main_matlab): - заглушки для ненужных функций (main_matlab.c) - iq библиотека (IQmathLib_matlab.c) - библиотеки DSP281x
341 lines
8.1 KiB
C
341 lines
8.1 KiB
C
#include "TuneUpPlane.h"
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#include "DSP281x_Examples.h"
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#include "DSP281x_Device.h"
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#include "DSP281x_Xintf.h"
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#define SelectWorkWithFlash() WriteOper(0,0,0,0)
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#define SelectStrob67_ForFlash() WriteOper(1,0,1,0)
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unsigned int cl_led1 = 0;
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unsigned int cl_led2 = 0;
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void SetupOperLine();
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#pragma CODE_SECTION(Led1_Toggle,".fast_run");
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#pragma CODE_SECTION(Led2_Toggle,".fast_run");
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#pragma CODE_SECTION(i_led2_on_off,".fast_run");
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void i_led2_on_off(int i)
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{
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EALLOW;
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if (i) GpioDataRegs.GPDSET.bit.GPIOD6=1;
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else GpioDataRegs.GPDCLEAR.bit.GPIOD6=1;
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EDIS;
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}
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#pragma CODE_SECTION(i_led1_on_off,".fast_run");
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void i_led1_on_off(int i)
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{
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EALLOW;
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if (i) GpioDataRegs.GPASET.bit.GPIOA10=1;
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else GpioDataRegs.GPACLEAR.bit.GPIOA10=1;
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EDIS;
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}
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//#pragma CODE_SECTION(i_led2_on_off_special,".fast_run");
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//void i_led2_on_off_special(int i)
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//{
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// EALLOW;
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//
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// if (i) GpioDataRegs.GPDSET.bit.GPIOD6=1;
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// else GpioDataRegs.GPDCLEAR.bit.GPIOD6=1;
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//
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//
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// EDIS;
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//}
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#pragma CODE_SECTION(i_led1_on_off_special,".fast_run");
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void i_led1_on_off_special(int i)
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{
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EALLOW;
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if (i)
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{
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GpioDataRegs.GPASET.bit.GPIOA10=1;
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cl_led1++;
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}
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else
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{
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if (cl_led1)
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cl_led1--;
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if (cl_led1 == 0)
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GpioDataRegs.GPACLEAR.bit.GPIOA10=1;
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}
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EDIS;
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}
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#pragma CODE_SECTION(i_led2_on_off_special,".fast_run");
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void i_led2_on_off_special(int i)
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{
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EALLOW;
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if (i)
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{
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GpioDataRegs.GPDSET.bit.GPIOD6=1;
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cl_led2++;
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}
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else
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{
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if (cl_led2)
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cl_led2--;
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if (cl_led2 == 0)
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GpioDataRegs.GPDCLEAR.bit.GPIOD6=1;
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}
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EDIS;
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}
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void Led1_Toggle()
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{
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EALLOW;
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GpioDataRegs.GPATOGGLE.bit.GPIOA10=1;
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EDIS;
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}
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void Led2_Toggle()
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{
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EALLOW;
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GpioDataRegs.GPDTOGGLE.bit.GPIOD6=1;
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EDIS;
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}
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void SetupLedsLine()
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{
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EALLOW;
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GpioMuxRegs.GPDMUX.bit.T4CTRIP_SOCB_GPIOD6 = 0;
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GpioDataRegs.GPDDAT.bit.GPIOD6 = 0;
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GpioMuxRegs.GPDDIR.bit.GPIOD6 = 1;
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GpioMuxRegs.GPAMUX.bit.CAP3QI1_GPIOA10 = 0;
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GpioDataRegs.GPADAT.bit.GPIOA10 = 0;
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GpioMuxRegs.GPADIR.bit.GPIOA10 = 1;
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EDIS;
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}
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#pragma CODE_SECTION(pause_1000,".fast_run");
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void pause_1000(unsigned long t)
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{
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unsigned long i;
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t = t >> 1;
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for (i = 0; i < t; i++)
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{
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DSP28x_usDelay(40L);
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}
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}
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//Xilinx Zone
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void XintfZone0_Timing(void)
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{
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// Zone 0------------------------------------
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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XintfRegs.XTIMING0.bit.XWRLEAD = 3;//2;
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XintfRegs.XTIMING0.bit.XWRACTIVE = 5;//2;//1; // 1
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XintfRegs.XTIMING0.bit.XWRTRAIL = 1;//0;
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// Zone read timing
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XintfRegs.XTIMING0.bit.XRDLEAD = 3;
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XintfRegs.XTIMING0.bit.XRDACTIVE = 5;//1
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XintfRegs.XTIMING0.bit.XRDTRAIL = 1;//1
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// do not double all Zone read/write lead/active/trail timing
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XintfRegs.XTIMING0.bit.X2TIMING = 0;
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// Zone will not sample READY
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XintfRegs.XTIMING0.bit.USEREADY = 0;//1;
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XintfRegs.XTIMING0.bit.READYMODE = 0;//1;
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// Size must be 1,1 - other values are reserved
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XintfRegs.XTIMING0.bit.XSIZE = 3;
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//Force a pipeline flush to ensure that the write to
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//the last register configured occurs before returning.
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asm(" RPT #7 || NOP");
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}
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void XintfZone6_And7_Timing(void)
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{
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// All Zones---------------------------------
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// Timing for all zones based on XTIMCLK = SYSCLKOUT/2
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XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
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// Buffer up to 0 writes
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XintfRegs.XINTCNF2.bit.WRBUFF = 0;
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// XCLKOUT is enabled
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XintfRegs.XINTCNF2.bit.CLKOFF = 0;
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// XCLKOUT = XTIMCLK
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#ifdef XLOW_FREQUENCY_MODE
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XintfRegs.XINTCNF2.bit.CLKMODE = 1;
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#else
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XintfRegs.XINTCNF2.bit.CLKMODE = 0;
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#endif
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XintfRegs.XINTCNF2.bit.MPNMC = 0;
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// Zone 6------------------------------------
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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XintfRegs.XTIMING6.bit.XWRLEAD = 3;
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XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
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XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
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// Zone read timing
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XintfRegs.XTIMING6.bit.XRDLEAD = 3;
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XintfRegs.XTIMING6.bit.XRDACTIVE = 7;//3;
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XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
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// do not double all Zone read/write lead/active/trail timing
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XintfRegs.XTIMING6.bit.X2TIMING = 0;
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// Zone will not sample READY
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XintfRegs.XTIMING6.bit.USEREADY = 0;//1;
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XintfRegs.XTIMING6.bit.READYMODE = 0;//1;
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// Size must be 1,1 - other values are reserved
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XintfRegs.XTIMING6.bit.XSIZE = 3;
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// Zone 7------------------------------------
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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XintfRegs.XTIMING7.bit.XWRLEAD = 3;
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XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
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XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
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// Zone read timing
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XintfRegs.XTIMING7.bit.XRDLEAD = 3;
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XintfRegs.XTIMING7.bit.XRDACTIVE = 3;
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XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
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// don't double all Zone read/write lead/active/trail timing
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XintfRegs.XTIMING7.bit.X2TIMING = 0;
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// Zone will not sample XREADY signal
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XintfRegs.XTIMING7.bit.USEREADY = 0;
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XintfRegs.XTIMING7.bit.READYMODE = 0;
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// Size must be 1,1 - other values are reserved
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XintfRegs.XTIMING7.bit.XSIZE = 3;
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//Force a pipeline flush to ensure that the write to
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//the last register configured occurs before returning.
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asm(" RPT #7 || NOP");
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}
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void XintfZone2_Timing(void)
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{
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// All Zones---------------------------------
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// Timing for all zones based on XTIMCLK = SYSCLKOUT/2
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XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
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// Buffer up to 0 writes
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XintfRegs.XINTCNF2.bit.WRBUFF = 0;
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// XCLKOUT is enabled
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XintfRegs.XINTCNF2.bit.CLKOFF = 0;
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// XCLKOUT = XTIMCLK
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XintfRegs.XINTCNF2.bit.CLKMODE = 0;
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XintfRegs.XINTCNF2.bit.MPNMC = 0;
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// Zone 6------------------------------------
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// When using ready, ACTIVE must be 1 or greater
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// Lead must always be 1 or greater
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// Zone write timing
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XintfRegs.XTIMING2.bit.XWRLEAD = 3;//2;
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XintfRegs.XTIMING2.bit.XWRACTIVE = 4;//2;
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XintfRegs.XTIMING2.bit.XWRTRAIL = 2;//2;
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// Zone read timing
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XintfRegs.XTIMING2.bit.XRDLEAD = 2;
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XintfRegs.XTIMING2.bit.XRDACTIVE = 3; //1;
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XintfRegs.XTIMING2.bit.XRDTRAIL = 1;//2;//0;
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// do not double all Zone read/write lead/active/trail timing
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XintfRegs.XTIMING2.bit.X2TIMING = 0;
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// Zone will not sample READY
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XintfRegs.XTIMING2.bit.USEREADY = 0;//1;
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XintfRegs.XTIMING2.bit.READYMODE = 0;//1;
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// Size must be 1,1 - other values are reserved
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XintfRegs.XTIMING2.bit.XSIZE = 3;
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//Force a pipeline flush to ensure that the write to
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//the last register configured occurs before returning.
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asm(" RPT #7 || NOP");
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}
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void FlashInit()
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{
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SetupOperLine();
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SelectStrob67_ForFlash();
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XintfZone6_And7_Timing();
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SelectWorkWithFlash();
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}
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void SetupOperLine()
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{
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EALLOW;
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GpioMuxRegs.GPAMUX.bit.C1TRIP_GPIOA13=0;
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GpioMuxRegs.GPAMUX.bit.C2TRIP_GPIOA14=0;
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GpioMuxRegs.GPAMUX.bit.C3TRIP_GPIOA15=0;
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GpioMuxRegs.GPBMUX.bit.C4TRIP_GPIOB13=0;
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GpioMuxRegs.GPBMUX.bit.C6TRIP_GPIOB15=0;
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GpioMuxRegs.GPADIR.bit.GPIOA13=1;
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GpioMuxRegs.GPADIR.bit.GPIOA14=1;
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GpioMuxRegs.GPADIR.bit.GPIOA15=1;
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GpioMuxRegs.GPBDIR.bit.GPIOB13=1;
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GpioMuxRegs.GPBDIR.bit.GPIOB15=1;
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GpioMuxRegs.GPAQUAL.all=0;
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GpioMuxRegs.GPBQUAL.all=0;
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EDIS;
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WriteOper(1,1,1,1);
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}
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void WriteOper(unsigned char oper_mode1,unsigned char oper_mode2, unsigned char oper_mode3, unsigned char oper_mode4)
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{
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EALLOW;
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GpioDataRegs.GPADAT.bit.GPIOA13=oper_mode1;
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GpioDataRegs.GPADAT.bit.GPIOA14=oper_mode2;
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GpioDataRegs.GPADAT.bit.GPIOA15=oper_mode3;
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GpioDataRegs.GPBDAT.bit.GPIOB13=oper_mode4;
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asm(" NOP");
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GpioDataRegs.GPBDAT.bit.GPIOB15=0;
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asm(" NOP");
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asm(" NOP");
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asm(" NOP");
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GpioDataRegs.GPBDAT.bit.GPIOB15=1;
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asm(" NOP");
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asm(" NOP");
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asm(" NOP");
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GpioDataRegs.GPBDAT.bit.GPIOB15=0;
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asm(" NOP");
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asm(" NOP");
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asm(" NOP");
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EDIS;
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}
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