From 7e0063eee03ddb7092e62d8782b77898e62f6c12 Mon Sep 17 00:00:00 2001 From: Razvalyaev Date: Mon, 13 Jan 2025 11:09:58 +0300 Subject: [PATCH] =?UTF-8?q?#3=20=D0=A1=D0=BA=D0=BE=D0=BC=D0=BF=D0=B8=D0=BB?= =?UTF-8?q?=D0=B8=D0=BB=D0=BE=D1=81=D1=8C,=20=D0=BD=D0=BE=20=D0=BF=D0=BE?= =?UTF-8?q?=D0=BA=D0=B0=20=D0=BD=D0=B8=D1=87=D0=B5=D0=B3=D0=BE=20=D0=BD?= =?UTF-8?q?=D0=B5=20=D0=B2=D1=8B=D0=B7=D1=8B=D0=B2=D0=B0=D0=B5=D1=82=D1=81?= =?UTF-8?q?=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Все основные файлы подтянуты без изменений Изменены (только папка main_matlab): - заглушки для ненужных функций (main_matlab.c) - iq библиотека (IQmathLib_matlab.c) - библиотеки DSP281x --- Inu/Src/N12_Libs/CAN_Setup.c | 2201 ++++++ Inu/Src/N12_Libs/CAN_Setup.h | 751 ++ Inu/Src/N12_Libs/RS_modbus_pult.h | 31 + Inu/Src/N12_Libs/RS_modbus_pultl.c | 1013 +++ Inu/Src/N12_Libs/alarm_log_can.c | 543 ++ Inu/Src/N12_Libs/alarm_log_can.h | 135 + Inu/Src/N12_Libs/big_dsp_module.c | 26 + Inu/Src/N12_Libs/big_dsp_module.h | 19 + Inu/Src/N12_Libs/build_version.c | 24 + Inu/Src/N12_Libs/build_version.h | 30 + Inu/Src/N12_Libs/control_station.c | 194 + Inu/Src/N12_Libs/control_station.h | 134 + Inu/Src/N12_Libs/filter_v1.c | 367 + Inu/Src/N12_Libs/filter_v1.h | 73 + Inu/Src/N12_Libs/global_time.c | 149 + Inu/Src/N12_Libs/global_time.h | 58 + Inu/Src/N12_Libs/iq_values_norma_f.h | 6025 ++++++++++++++ Inu/Src/N12_Libs/iq_values_norma_iu.h | 7025 +++++++++++++++++ Inu/Src/N12_Libs/iq_values_norma_oborot.h | 22 + Inu/Src/N12_Libs/log_params.c | 149 + Inu/Src/N12_Libs/log_params.h | 109 + Inu/Src/N12_Libs/log_to_memory.c | 484 ++ Inu/Src/N12_Libs/log_to_memory.h | 96 + Inu/Src/N12_Libs/math_pi.h | 50 + Inu/Src/N12_Libs/mathlib.c | 437 + Inu/Src/N12_Libs/mathlib.h | 81 + Inu/Src/N12_Libs/modbus_table_v2.c | 89 + Inu/Src/N12_Libs/modbus_table_v2.h | 42 + Inu/Src/N12_Libs/not_use/IQmathLib.h | 4721 +++++++++++ Inu/Src/N12_Libs/not_use/adaptive_filters.c | 626 ++ Inu/Src/N12_Libs/not_use/pi_adaptive.c | 40 + Inu/Src/N12_Libs/options_table.c | 37 + Inu/Src/N12_Libs/options_table.h | 17 + Inu/Src/N12_Libs/oscil_can.c | 293 + Inu/Src/N12_Libs/oscil_can.h | 103 + Inu/Src/N12_Libs/params_protect.h | 63 + Inu/Src/N12_Libs/pid_reg3.c | 64 + Inu/Src/N12_Libs/pid_reg3.h | 98 + Inu/Src/N12_Libs/rmp_cntl_v1.c | 51 + Inu/Src/N12_Libs/rmp_cntl_v1.h | 48 + Inu/Src/N12_Libs/rmp_cntl_v2.c | 193 + Inu/Src/N12_Libs/rmp_cntl_v2.h | 69 + Inu/Src/N12_Libs/svgen_dq.h | 38 + Inu/Src/N12_Libs/svgen_dq_v2.c | 122 + Inu/Src/N12_Libs/svgen_mf.c | 164 + Inu/Src/N12_Libs/svgen_mf.h | 46 + Inu/Src/N12_Libs/uf_alg_ing.c | 736 ++ Inu/Src/N12_Libs/uf_alg_ing.h | 93 + Inu/Src/N12_Libs/vhzprof.c | 45 + Inu/Src/N12_Libs/vhzprof.h | 41 + Inu/Src/N12_Libs/word_structurs.h | 64 + .../abc_to_alphabeta.c | 0 .../abc_to_alphabeta.h | 0 .../abc_to_dq.c | 0 .../abc_to_dq.h | 0 .../alg_pll.c | 0 .../alg_pll.h | 0 .../alphabeta_to_dq.c | 0 .../alphabeta_to_dq.h | 0 .../dq_to_alphabeta_cos.c | 0 .../dq_to_alphabeta_cos.h | 0 .../params_pll.h | 0 .../regul_power.c | 0 .../regul_power.h | 0 .../regul_turns.c | 0 .../regul_turns.h | 0 .../smooth.c | 0 .../smooth.h | 0 .../teta_calc.c | 0 .../teta_calc.h | 0 .../vector_control.c | 0 .../vector_control.h | 0 Inu/Src/N12_Xilinx/CRC_Functions.c | 143 + Inu/Src/N12_Xilinx/CRC_Functions.h | 12 + Inu/Src/N12_Xilinx/MemoryFunctions.c | 325 + Inu/Src/N12_Xilinx/MemoryFunctions.h | 36 + Inu/Src/N12_Xilinx/RS_Function_terminal.c | 98 + Inu/Src/N12_Xilinx/RS_Function_terminal.h | 605 ++ Inu/Src/N12_Xilinx/RS_Functions.c | 2639 +++++++ Inu/Src/N12_Xilinx/RS_Functions.h | 142 + Inu/Src/N12_Xilinx/RS_modbus_svu.c | 328 + Inu/Src/N12_Xilinx/RS_modbus_svu.h | 27 + Inu/Src/N12_Xilinx/Spartan2E_Adr.h | 90 + Inu/Src/N12_Xilinx/Spartan2E_Functions.c | 896 +++ Inu/Src/N12_Xilinx/Spartan2E_Functions.h | 264 + Inu/Src/N12_Xilinx/TuneUpPlane.c | 340 + Inu/Src/N12_Xilinx/TuneUpPlane.h | 38 + Inu/Src/N12_Xilinx/modbus_struct.h | 39 + .../N12_Xilinx/not_use/xp_rotation_sensor.c | 267 + .../N12_Xilinx/not_use/xp_rotation_sensor.h | 346 + Inu/Src/N12_Xilinx/profile_interrupt.c | 36 + Inu/Src/N12_Xilinx/profile_interrupt.h | 48 + Inu/Src/N12_Xilinx/xHWP.c | 11 + Inu/Src/N12_Xilinx/xHWP.h | 6 + Inu/Src/N12_Xilinx/xPeriphSP6_loader.c | 561 ++ Inu/Src/N12_Xilinx/xPeriphSP6_loader.h | 133 + Inu/Src/N12_Xilinx/x_basic_types.h | 111 + Inu/Src/N12_Xilinx/x_int13.c | 218 + Inu/Src/N12_Xilinx/x_int13.h | 36 + Inu/Src/N12_Xilinx/x_parallel_bus.c | 238 + Inu/Src/N12_Xilinx/x_parallel_bus.h | 127 + Inu/Src/N12_Xilinx/x_project_useit.h | 7 + Inu/Src/N12_Xilinx/x_serial_bus.c | 319 + Inu/Src/N12_Xilinx/x_serial_bus.h | 87 + Inu/Src/N12_Xilinx/x_wdog.c | 23 + Inu/Src/N12_Xilinx/x_wdog.h | 18 + Inu/Src/N12_Xilinx/xerror.c | 428 + Inu/Src/N12_Xilinx/xerror.h | 66 + Inu/Src/N12_Xilinx/xp_adc.c | 643 ++ Inu/Src/N12_Xilinx/xp_adc.h | 267 + Inu/Src/N12_Xilinx/xp_cds_in.c | 440 ++ Inu/Src/N12_Xilinx/xp_cds_in.h | 517 ++ Inu/Src/N12_Xilinx/xp_cds_out.c | 310 + Inu/Src/N12_Xilinx/xp_cds_out.h | 286 + Inu/Src/N12_Xilinx/xp_cds_rs.c | 399 + Inu/Src/N12_Xilinx/xp_cds_rs.h | 182 + Inu/Src/N12_Xilinx/xp_cds_status_bus.c | 217 + Inu/Src/N12_Xilinx/xp_cds_status_bus.h | 95 + Inu/Src/N12_Xilinx/xp_cds_tk.c | 196 + Inu/Src/N12_Xilinx/xp_cds_tk.h | 114 + Inu/Src/N12_Xilinx/xp_cds_tk_10510.c | 280 + Inu/Src/N12_Xilinx/xp_cds_tk_10510.h | 460 ++ Inu/Src/N12_Xilinx/xp_cds_tk_21180.c | 280 + Inu/Src/N12_Xilinx/xp_cds_tk_21180.h | 459 ++ Inu/Src/N12_Xilinx/xp_cds_tk_21300.c | 280 + Inu/Src/N12_Xilinx/xp_cds_tk_21300.h | 460 ++ Inu/Src/N12_Xilinx/xp_cds_tk_22220.c | 302 + Inu/Src/N12_Xilinx/xp_cds_tk_22220.h | 539 ++ Inu/Src/N12_Xilinx/xp_cds_tk_23470.c | 280 + Inu/Src/N12_Xilinx/xp_cds_tk_23470.h | 459 ++ Inu/Src/N12_Xilinx/xp_cds_tk_23550.c | 560 ++ Inu/Src/N12_Xilinx/xp_cds_tk_23550.h | 616 ++ Inu/Src/N12_Xilinx/xp_cds_tk_balzam.c | 236 + Inu/Src/N12_Xilinx/xp_cds_tk_balzam.h | 403 + Inu/Src/N12_Xilinx/xp_controller.c | 58 + Inu/Src/N12_Xilinx/xp_controller.h | 144 + Inu/Src/N12_Xilinx/xp_hwp.c | 1419 ++++ Inu/Src/N12_Xilinx/xp_hwp.h | 445 ++ Inu/Src/N12_Xilinx/xp_id_plate_info.h | 71 + Inu/Src/N12_Xilinx/xp_inc_sensor.c | 396 + Inu/Src/N12_Xilinx/xp_inc_sensor.h | 137 + Inu/Src/N12_Xilinx/xp_incremental_sensors.c | 235 + Inu/Src/N12_Xilinx/xp_incremental_sensors.h | 531 ++ Inu/Src/N12_Xilinx/xp_optlink_tms2tms.c | 98 + Inu/Src/N12_Xilinx/xp_optlink_tms2tms.h | 110 + Inu/Src/N12_Xilinx/xp_plane_adr.h | 175 + Inu/Src/N12_Xilinx/xp_project.c | 1986 +++++ Inu/Src/N12_Xilinx/xp_project.h | 462 ++ Inu/Src/N12_Xilinx/xp_tools.c | 41 + Inu/Src/N12_Xilinx/xp_tools.h | 16 + Inu/Src/N12_Xilinx/xp_write_xpwm_time.c | 671 ++ Inu/Src/N12_Xilinx/xp_write_xpwm_time.h | 228 + Inu/Src/main_matlab/IQmathLib.h | 2 + Inu/Src/main_matlab/main_matlab.c | 50 +- Inu/Src/main_matlab/{ => old}/adc_tools.h | 0 .../main_matlab/{ => old}/adc_tools_matlab.c | 0 Inu/Src/main_matlab/{ => old}/errors_matlab.c | 0 .../main_matlab/{ => old}/io_verbal_names.h | 0 .../{ => old}/rotation_speed_matlab.c | 0 .../main_matlab/{ => old}/v_pwm24_matlab.c | 0 .../{ => old}/xp_write_xpwm_time_matlab.c | 0 Inu/Src2/551/VectorControl/abc_to_alphabeta.c | 23 + Inu/Src2/551/VectorControl/abc_to_alphabeta.h | 39 + Inu/Src2/551/VectorControl/abc_to_dq.c | 39 + Inu/Src2/551/VectorControl/abc_to_dq.h | 42 + Inu/Src2/551/VectorControl/alg_pll.c | 577 ++ Inu/Src2/551/VectorControl/alg_pll.h | 188 + Inu/Src2/551/VectorControl/alphabeta_to_dq.c | 24 + Inu/Src2/551/VectorControl/alphabeta_to_dq.h | 32 + .../551/VectorControl/dq_to_alphabeta_cos.c | 39 + .../551/VectorControl/dq_to_alphabeta_cos.h | 40 + Inu/Src2/551/VectorControl/params_pll.h | 41 + Inu/Src2/551/VectorControl/regul_power.c | 88 + Inu/Src2/551/VectorControl/regul_power.h | 30 + Inu/Src2/551/VectorControl/regul_turns.c | 143 + Inu/Src2/551/VectorControl/regul_turns.h | 29 + Inu/Src2/551/VectorControl/smooth.c | 180 + Inu/Src2/551/VectorControl/smooth.h | 78 + Inu/Src2/551/VectorControl/teta_calc.c | 91 + Inu/Src2/551/VectorControl/teta_calc.h | 36 + Inu/Src2/551/VectorControl/vector_control.c | 297 + Inu/Src2/551/VectorControl/vector_control.h | 82 + Inu/Src2/551/main/281xEvTimersInit.c | 636 ++ Inu/Src2/551/main/281xEvTimersInit.h | 18 + Inu/Src2/551/main/CAN_project.h | 256 + Inu/Src2/551/main/Main.c | 126 + Inu/Src2/551/main/PWMTMSHandle.c | 510 ++ Inu/Src2/551/main/PWMTMSHandle.h | 25 + Inu/Src2/551/main/PWMTools.c | 2438 ++++++ Inu/Src2/551/main/PWMTools.h | 54 + Inu/Src2/551/main/adc_internal.h | 33 + Inu/Src2/551/main/adc_tools.c | 1412 ++++ Inu/Src2/551/main/adc_tools.h | 402 + Inu/Src2/551/main/alarm_log.c | 196 + Inu/Src2/551/main/alarm_log.h | 16 + Inu/Src2/551/main/alg_simple_scalar.c | 976 +++ Inu/Src2/551/main/alg_simple_scalar.h | 101 + Inu/Src2/551/main/alg_uf_const.c | 80 + Inu/Src2/551/main/alg_uf_const.h | 34 + Inu/Src2/551/main/another_bs.c | 458 ++ Inu/Src2/551/main/another_bs.h | 21 + Inu/Src2/551/main/break_regul.c | 204 + Inu/Src2/551/main/break_regul.h | 70 + Inu/Src2/551/main/calc_rms_vals.c | 265 + Inu/Src2/551/main/calc_rms_vals.h | 66 + Inu/Src2/551/main/calc_tempers.c | 284 + Inu/Src2/551/main/calc_tempers.h | 16 + Inu/Src2/551/main/can_bs2bs.c | 83 + Inu/Src2/551/main/can_bs2bs.h | 21 + Inu/Src2/551/main/can_protocol_ukss.h | 63 + Inu/Src2/551/main/control_station_project.c | 2493 ++++++ Inu/Src2/551/main/control_station_project.h | 109 + Inu/Src2/551/main/detect_error_3_phase.c | 167 + Inu/Src2/551/main/detect_error_3_phase.h | 148 + Inu/Src2/551/main/detect_errors.c | 1606 ++++ Inu/Src2/551/main/detect_errors.h | 80 + Inu/Src2/551/main/detect_errors_adc.c | 310 + Inu/Src2/551/main/detect_errors_adc.h | 45 + Inu/Src2/551/main/detect_overload.c | 92 + Inu/Src2/551/main/detect_overload.h | 32 + Inu/Src2/551/main/detect_phase_break.c | 112 + Inu/Src2/551/main/detect_phase_break.h | 36 + Inu/Src2/551/main/detect_phase_break2.c | 203 + Inu/Src2/551/main/detect_phase_break2.h | 50 + Inu/Src2/551/main/digital_filters.c | 103 + Inu/Src2/551/main/digital_filters.h | 19 + Inu/Src2/551/main/edrk_main.c | 2736 +++++++ Inu/Src2/551/main/edrk_main.h | 1838 +++++ Inu/Src2/551/main/f281xbmsk.h | 244 + Inu/Src2/551/main/f281xpwm.c | 288 + Inu/Src2/551/main/f281xpwm.h | 163 + Inu/Src2/551/main/limit_lib.c | 50 + Inu/Src2/551/main/limit_lib.h | 15 + Inu/Src2/551/main/limit_power.c | 237 + Inu/Src2/551/main/limit_power.h | 21 + Inu/Src2/551/main/logs_hmi.c | 1150 +++ Inu/Src2/551/main/logs_hmi.h | 86 + Inu/Src2/551/main/manch.h | 182 + Inu/Src2/551/main/master_slave.c | 586 ++ Inu/Src2/551/main/master_slave.h | 34 + Inu/Src2/551/main/message2.c | 907 +++ Inu/Src2/551/main/message2.h | 33 + Inu/Src2/551/main/message2can.c | 278 + Inu/Src2/551/main/message2can.h | 18 + Inu/Src2/551/main/message2test.c | 678 ++ Inu/Src2/551/main/message2test.h | 33 + Inu/Src2/551/main/message_modbus.c | 897 +++ Inu/Src2/551/main/message_modbus.h | 61 + Inu/Src2/551/main/message_terminals_can.c | 128 + Inu/Src2/551/main/message_terminals_can.h | 15 + Inu/Src2/551/main/modbus_hmi.c | 393 + Inu/Src2/551/main/modbus_hmi.h | 39 + Inu/Src2/551/main/modbus_hmi_read.c | 222 + Inu/Src2/551/main/modbus_hmi_read.h | 15 + Inu/Src2/551/main/modbus_hmi_update.c | 2022 +++++ Inu/Src2/551/main/modbus_hmi_update.h | 39 + Inu/Src2/551/main/modbus_svu_update.c | 710 ++ Inu/Src2/551/main/modbus_svu_update.h | 17 + Inu/Src2/551/main/not_use/log_to_mem.c | 249 + Inu/Src2/551/main/not_use/log_to_mem.h | 201 + Inu/Src2/551/main/optical_bus.c | 413 + Inu/Src2/551/main/optical_bus.h | 109 + Inu/Src2/551/main/optical_bus_tools.c | 791 ++ Inu/Src2/551/main/optical_bus_tools.h | 14 + Inu/Src2/551/main/overheat_limit.c | 80 + Inu/Src2/551/main/overheat_limit.h | 13 + Inu/Src2/551/main/params.h | 182 + Inu/Src2/551/main/params_alg.h | 218 + Inu/Src2/551/main/params_bsu.h | 123 + Inu/Src2/551/main/params_hwp.h | 9 + Inu/Src2/551/main/params_motor.h | 59 + Inu/Src2/551/main/params_norma.h | 70 + Inu/Src2/551/main/params_protect_adc.h | 25 + Inu/Src2/551/main/params_pwm24.h | 48 + Inu/Src2/551/main/params_temper_p.h | 58 + Inu/Src2/551/main/pll_tools.c | 105 + Inu/Src2/551/main/pll_tools.h | 22 + Inu/Src2/551/main/project.c | 1049 +++ Inu/Src2/551/main/project.h | 74 + Inu/Src2/551/main/project_setup.h | 414 + Inu/Src2/551/main/protect_levels.h | 119 + Inu/Src2/551/main/pump_control.c | 255 + Inu/Src2/551/main/pump_control.h | 27 + Inu/Src2/551/main/pwm_logs.c | 476 ++ Inu/Src2/551/main/pwm_logs.h | 16 + Inu/Src2/551/main/pwm_test_lines.c | 36 + Inu/Src2/551/main/pwm_test_lines.h | 63 + Inu/Src2/551/main/ramp_zadanie_tools.c | 417 + Inu/Src2/551/main/ramp_zadanie_tools.h | 20 + Inu/Src2/551/main/sbor_shema.c | 1764 +++++ Inu/Src2/551/main/sbor_shema.h | 24 + Inu/Src2/551/main/sim_model.c | 222 + Inu/Src2/551/main/sim_model.h | 21 + Inu/Src2/551/main/sync_tools.c | 520 ++ Inu/Src2/551/main/sync_tools.h | 113 + Inu/Src2/551/main/synhro_tools.c | 144 + Inu/Src2/551/main/synhro_tools.h | 19 + Inu/Src2/551/main/temper_p_tools.c | 77 + Inu/Src2/551/main/temper_p_tools.h | 22 + Inu/Src2/551/main/tk_Test.c | 369 + Inu/Src2/551/main/tk_Test.h | 12 + Inu/Src2/551/main/ukss_tools.c | 605 ++ Inu/Src2/551/main/ukss_tools.h | 33 + Inu/Src2/551/main/uom_tools.c | 149 + Inu/Src2/551/main/uom_tools.h | 15 + Inu/Src2/551/main/v_pwm24_v2.c | 948 +++ Inu/Src2/551/main/v_pwm24_v2.h | 161 + Inu/Src2/551/main/v_rotor.c | 1095 +++ Inu/Src2/551/main/v_rotor.h | 185 + Inu/Src2/551/main/v_rotor_22220.c | 666 ++ Inu/Src2/551/main/v_rotor_22220.h | 54 + Inu/Src2/551/main/vector.h | 254 + Inu/Src2/551/main/xPlatesAddress.h | 21 + Inu/controller.c | 11 +- Inu/controller.h | 4 +- controller.ilk | Bin 0 -> 385240 bytes run_mex.bat | 50 +- 317 files changed, 97782 insertions(+), 65 deletions(-) create mode 100644 Inu/Src/N12_Libs/CAN_Setup.c create mode 100644 Inu/Src/N12_Libs/CAN_Setup.h create mode 100644 Inu/Src/N12_Libs/RS_modbus_pult.h create mode 100644 Inu/Src/N12_Libs/RS_modbus_pultl.c create mode 100644 Inu/Src/N12_Libs/alarm_log_can.c create mode 100644 Inu/Src/N12_Libs/alarm_log_can.h create mode 100644 Inu/Src/N12_Libs/big_dsp_module.c create mode 100644 Inu/Src/N12_Libs/big_dsp_module.h create mode 100644 Inu/Src/N12_Libs/build_version.c create mode 100644 Inu/Src/N12_Libs/build_version.h create mode 100644 Inu/Src/N12_Libs/control_station.c create mode 100644 Inu/Src/N12_Libs/control_station.h create mode 100644 Inu/Src/N12_Libs/filter_v1.c create mode 100644 Inu/Src/N12_Libs/filter_v1.h create mode 100644 Inu/Src/N12_Libs/global_time.c create mode 100644 Inu/Src/N12_Libs/global_time.h create mode 100644 Inu/Src/N12_Libs/iq_values_norma_f.h create mode 100644 Inu/Src/N12_Libs/iq_values_norma_iu.h create mode 100644 Inu/Src/N12_Libs/iq_values_norma_oborot.h create mode 100644 Inu/Src/N12_Libs/log_params.c create mode 100644 Inu/Src/N12_Libs/log_params.h create mode 100644 Inu/Src/N12_Libs/log_to_memory.c create mode 100644 Inu/Src/N12_Libs/log_to_memory.h create mode 100644 Inu/Src/N12_Libs/math_pi.h create mode 100644 Inu/Src/N12_Libs/mathlib.c create mode 100644 Inu/Src/N12_Libs/mathlib.h create mode 100644 Inu/Src/N12_Libs/modbus_table_v2.c create mode 100644 Inu/Src/N12_Libs/modbus_table_v2.h create mode 100644 Inu/Src/N12_Libs/not_use/IQmathLib.h create mode 100644 Inu/Src/N12_Libs/not_use/adaptive_filters.c create mode 100644 Inu/Src/N12_Libs/not_use/pi_adaptive.c create mode 100644 Inu/Src/N12_Libs/options_table.c create mode 100644 Inu/Src/N12_Libs/options_table.h create mode 100644 Inu/Src/N12_Libs/oscil_can.c create mode 100644 Inu/Src/N12_Libs/oscil_can.h create mode 100644 Inu/Src/N12_Libs/params_protect.h create mode 100644 Inu/Src/N12_Libs/pid_reg3.c create mode 100644 Inu/Src/N12_Libs/pid_reg3.h create mode 100644 Inu/Src/N12_Libs/rmp_cntl_v1.c create mode 100644 Inu/Src/N12_Libs/rmp_cntl_v1.h create mode 100644 Inu/Src/N12_Libs/rmp_cntl_v2.c create mode 100644 Inu/Src/N12_Libs/rmp_cntl_v2.h create mode 100644 Inu/Src/N12_Libs/svgen_dq.h create mode 100644 Inu/Src/N12_Libs/svgen_dq_v2.c create mode 100644 Inu/Src/N12_Libs/svgen_mf.c create mode 100644 Inu/Src/N12_Libs/svgen_mf.h create mode 100644 Inu/Src/N12_Libs/uf_alg_ing.c create mode 100644 Inu/Src/N12_Libs/uf_alg_ing.h create mode 100644 Inu/Src/N12_Libs/vhzprof.c create mode 100644 Inu/Src/N12_Libs/vhzprof.h create mode 100644 Inu/Src/N12_Libs/word_structurs.h rename Inu/Src/{VectorControl => N12_VectorControl}/abc_to_alphabeta.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/abc_to_alphabeta.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/abc_to_dq.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/abc_to_dq.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/alg_pll.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/alg_pll.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/alphabeta_to_dq.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/alphabeta_to_dq.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/dq_to_alphabeta_cos.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/dq_to_alphabeta_cos.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/params_pll.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/regul_power.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/regul_power.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/regul_turns.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/regul_turns.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/smooth.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/smooth.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/teta_calc.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/teta_calc.h (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/vector_control.c (100%) rename Inu/Src/{VectorControl => N12_VectorControl}/vector_control.h (100%) create mode 100644 Inu/Src/N12_Xilinx/CRC_Functions.c create mode 100644 Inu/Src/N12_Xilinx/CRC_Functions.h create mode 100644 Inu/Src/N12_Xilinx/MemoryFunctions.c create mode 100644 Inu/Src/N12_Xilinx/MemoryFunctions.h create mode 100644 Inu/Src/N12_Xilinx/RS_Function_terminal.c create mode 100644 Inu/Src/N12_Xilinx/RS_Function_terminal.h create mode 100644 Inu/Src/N12_Xilinx/RS_Functions.c create mode 100644 Inu/Src/N12_Xilinx/RS_Functions.h create mode 100644 Inu/Src/N12_Xilinx/RS_modbus_svu.c create mode 100644 Inu/Src/N12_Xilinx/RS_modbus_svu.h create mode 100644 Inu/Src/N12_Xilinx/Spartan2E_Adr.h create mode 100644 Inu/Src/N12_Xilinx/Spartan2E_Functions.c create mode 100644 Inu/Src/N12_Xilinx/Spartan2E_Functions.h create mode 100644 Inu/Src/N12_Xilinx/TuneUpPlane.c create mode 100644 Inu/Src/N12_Xilinx/TuneUpPlane.h create mode 100644 Inu/Src/N12_Xilinx/modbus_struct.h create mode 100644 Inu/Src/N12_Xilinx/not_use/xp_rotation_sensor.c create mode 100644 Inu/Src/N12_Xilinx/not_use/xp_rotation_sensor.h create mode 100644 Inu/Src/N12_Xilinx/profile_interrupt.c create mode 100644 Inu/Src/N12_Xilinx/profile_interrupt.h create mode 100644 Inu/Src/N12_Xilinx/xHWP.c create mode 100644 Inu/Src/N12_Xilinx/xHWP.h create mode 100644 Inu/Src/N12_Xilinx/xPeriphSP6_loader.c create mode 100644 Inu/Src/N12_Xilinx/xPeriphSP6_loader.h create mode 100644 Inu/Src/N12_Xilinx/x_basic_types.h create mode 100644 Inu/Src/N12_Xilinx/x_int13.c create mode 100644 Inu/Src/N12_Xilinx/x_int13.h create mode 100644 Inu/Src/N12_Xilinx/x_parallel_bus.c create mode 100644 Inu/Src/N12_Xilinx/x_parallel_bus.h create mode 100644 Inu/Src/N12_Xilinx/x_project_useit.h create mode 100644 Inu/Src/N12_Xilinx/x_serial_bus.c create mode 100644 Inu/Src/N12_Xilinx/x_serial_bus.h create mode 100644 Inu/Src/N12_Xilinx/x_wdog.c create mode 100644 Inu/Src/N12_Xilinx/x_wdog.h create mode 100644 Inu/Src/N12_Xilinx/xerror.c create mode 100644 Inu/Src/N12_Xilinx/xerror.h create mode 100644 Inu/Src/N12_Xilinx/xp_adc.c create mode 100644 Inu/Src/N12_Xilinx/xp_adc.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_in.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_in.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_out.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_out.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_rs.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_rs.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_status_bus.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_status_bus.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_10510.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_10510.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_21180.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_21180.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_21300.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_21300.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_22220.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_22220.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_23470.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_23470.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_23550.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_23550.h create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_balzam.c create mode 100644 Inu/Src/N12_Xilinx/xp_cds_tk_balzam.h create mode 100644 Inu/Src/N12_Xilinx/xp_controller.c create mode 100644 Inu/Src/N12_Xilinx/xp_controller.h create mode 100644 Inu/Src/N12_Xilinx/xp_hwp.c create mode 100644 Inu/Src/N12_Xilinx/xp_hwp.h create mode 100644 Inu/Src/N12_Xilinx/xp_id_plate_info.h create mode 100644 Inu/Src/N12_Xilinx/xp_inc_sensor.c create mode 100644 Inu/Src/N12_Xilinx/xp_inc_sensor.h create mode 100644 Inu/Src/N12_Xilinx/xp_incremental_sensors.c create mode 100644 Inu/Src/N12_Xilinx/xp_incremental_sensors.h create mode 100644 Inu/Src/N12_Xilinx/xp_optlink_tms2tms.c create mode 100644 Inu/Src/N12_Xilinx/xp_optlink_tms2tms.h create mode 100644 Inu/Src/N12_Xilinx/xp_plane_adr.h create mode 100644 Inu/Src/N12_Xilinx/xp_project.c create mode 100644 Inu/Src/N12_Xilinx/xp_project.h create mode 100644 Inu/Src/N12_Xilinx/xp_tools.c create mode 100644 Inu/Src/N12_Xilinx/xp_tools.h create mode 100644 Inu/Src/N12_Xilinx/xp_write_xpwm_time.c create mode 100644 Inu/Src/N12_Xilinx/xp_write_xpwm_time.h rename Inu/Src/main_matlab/{ => old}/adc_tools.h (100%) rename Inu/Src/main_matlab/{ => old}/adc_tools_matlab.c (100%) rename Inu/Src/main_matlab/{ => old}/errors_matlab.c (100%) rename Inu/Src/main_matlab/{ => old}/io_verbal_names.h (100%) rename Inu/Src/main_matlab/{ => old}/rotation_speed_matlab.c (100%) rename Inu/Src/main_matlab/{ => old}/v_pwm24_matlab.c (100%) rename Inu/Src/main_matlab/{ => old}/xp_write_xpwm_time_matlab.c (100%) create mode 100644 Inu/Src2/551/VectorControl/abc_to_alphabeta.c create mode 100644 Inu/Src2/551/VectorControl/abc_to_alphabeta.h create mode 100644 Inu/Src2/551/VectorControl/abc_to_dq.c create mode 100644 Inu/Src2/551/VectorControl/abc_to_dq.h create mode 100644 Inu/Src2/551/VectorControl/alg_pll.c create mode 100644 Inu/Src2/551/VectorControl/alg_pll.h create mode 100644 Inu/Src2/551/VectorControl/alphabeta_to_dq.c create mode 100644 Inu/Src2/551/VectorControl/alphabeta_to_dq.h create mode 100644 Inu/Src2/551/VectorControl/dq_to_alphabeta_cos.c create mode 100644 Inu/Src2/551/VectorControl/dq_to_alphabeta_cos.h create mode 100644 Inu/Src2/551/VectorControl/params_pll.h create mode 100644 Inu/Src2/551/VectorControl/regul_power.c create mode 100644 Inu/Src2/551/VectorControl/regul_power.h create mode 100644 Inu/Src2/551/VectorControl/regul_turns.c create mode 100644 Inu/Src2/551/VectorControl/regul_turns.h create mode 100644 Inu/Src2/551/VectorControl/smooth.c create mode 100644 Inu/Src2/551/VectorControl/smooth.h create mode 100644 Inu/Src2/551/VectorControl/teta_calc.c create mode 100644 Inu/Src2/551/VectorControl/teta_calc.h create mode 100644 Inu/Src2/551/VectorControl/vector_control.c create mode 100644 Inu/Src2/551/VectorControl/vector_control.h create mode 100644 Inu/Src2/551/main/281xEvTimersInit.c create mode 100644 Inu/Src2/551/main/281xEvTimersInit.h create mode 100644 Inu/Src2/551/main/CAN_project.h create mode 100644 Inu/Src2/551/main/Main.c create mode 100644 Inu/Src2/551/main/PWMTMSHandle.c create mode 100644 Inu/Src2/551/main/PWMTMSHandle.h create mode 100644 Inu/Src2/551/main/PWMTools.c create mode 100644 Inu/Src2/551/main/PWMTools.h create mode 100644 Inu/Src2/551/main/adc_internal.h create mode 100644 Inu/Src2/551/main/adc_tools.c create mode 100644 Inu/Src2/551/main/adc_tools.h create mode 100644 Inu/Src2/551/main/alarm_log.c create mode 100644 Inu/Src2/551/main/alarm_log.h create mode 100644 Inu/Src2/551/main/alg_simple_scalar.c create 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Inu/Src2/551/main/detect_errors.c create mode 100644 Inu/Src2/551/main/detect_errors.h create mode 100644 Inu/Src2/551/main/detect_errors_adc.c create mode 100644 Inu/Src2/551/main/detect_errors_adc.h create mode 100644 Inu/Src2/551/main/detect_overload.c create mode 100644 Inu/Src2/551/main/detect_overload.h create mode 100644 Inu/Src2/551/main/detect_phase_break.c create mode 100644 Inu/Src2/551/main/detect_phase_break.h create mode 100644 Inu/Src2/551/main/detect_phase_break2.c create mode 100644 Inu/Src2/551/main/detect_phase_break2.h create mode 100644 Inu/Src2/551/main/digital_filters.c create mode 100644 Inu/Src2/551/main/digital_filters.h create mode 100644 Inu/Src2/551/main/edrk_main.c create mode 100644 Inu/Src2/551/main/edrk_main.h create mode 100644 Inu/Src2/551/main/f281xbmsk.h create mode 100644 Inu/Src2/551/main/f281xpwm.c create mode 100644 Inu/Src2/551/main/f281xpwm.h create mode 100644 Inu/Src2/551/main/limit_lib.c create mode 100644 Inu/Src2/551/main/limit_lib.h create mode 100644 Inu/Src2/551/main/limit_power.c create mode 100644 Inu/Src2/551/main/limit_power.h create mode 100644 Inu/Src2/551/main/logs_hmi.c create mode 100644 Inu/Src2/551/main/logs_hmi.h create mode 100644 Inu/Src2/551/main/manch.h create mode 100644 Inu/Src2/551/main/master_slave.c create mode 100644 Inu/Src2/551/main/master_slave.h create mode 100644 Inu/Src2/551/main/message2.c create mode 100644 Inu/Src2/551/main/message2.h create mode 100644 Inu/Src2/551/main/message2can.c create mode 100644 Inu/Src2/551/main/message2can.h create mode 100644 Inu/Src2/551/main/message2test.c create mode 100644 Inu/Src2/551/main/message2test.h create mode 100644 Inu/Src2/551/main/message_modbus.c create mode 100644 Inu/Src2/551/main/message_modbus.h create mode 100644 Inu/Src2/551/main/message_terminals_can.c create mode 100644 Inu/Src2/551/main/message_terminals_can.h create mode 100644 Inu/Src2/551/main/modbus_hmi.c create mode 100644 Inu/Src2/551/main/modbus_hmi.h create mode 100644 Inu/Src2/551/main/modbus_hmi_read.c create mode 100644 Inu/Src2/551/main/modbus_hmi_read.h create mode 100644 Inu/Src2/551/main/modbus_hmi_update.c create mode 100644 Inu/Src2/551/main/modbus_hmi_update.h create mode 100644 Inu/Src2/551/main/modbus_svu_update.c create mode 100644 Inu/Src2/551/main/modbus_svu_update.h create mode 100644 Inu/Src2/551/main/not_use/log_to_mem.c create mode 100644 Inu/Src2/551/main/not_use/log_to_mem.h create mode 100644 Inu/Src2/551/main/optical_bus.c create mode 100644 Inu/Src2/551/main/optical_bus.h create mode 100644 Inu/Src2/551/main/optical_bus_tools.c create mode 100644 Inu/Src2/551/main/optical_bus_tools.h create mode 100644 Inu/Src2/551/main/overheat_limit.c create mode 100644 Inu/Src2/551/main/overheat_limit.h create mode 100644 Inu/Src2/551/main/params.h create mode 100644 Inu/Src2/551/main/params_alg.h create mode 100644 Inu/Src2/551/main/params_bsu.h create mode 100644 Inu/Src2/551/main/params_hwp.h create mode 100644 Inu/Src2/551/main/params_motor.h create mode 100644 Inu/Src2/551/main/params_norma.h create mode 100644 Inu/Src2/551/main/params_protect_adc.h create mode 100644 Inu/Src2/551/main/params_pwm24.h create mode 100644 Inu/Src2/551/main/params_temper_p.h create mode 100644 Inu/Src2/551/main/pll_tools.c create mode 100644 Inu/Src2/551/main/pll_tools.h create mode 100644 Inu/Src2/551/main/project.c create mode 100644 Inu/Src2/551/main/project.h create mode 100644 Inu/Src2/551/main/project_setup.h create mode 100644 Inu/Src2/551/main/protect_levels.h create mode 100644 Inu/Src2/551/main/pump_control.c create mode 100644 Inu/Src2/551/main/pump_control.h create mode 100644 Inu/Src2/551/main/pwm_logs.c create mode 100644 Inu/Src2/551/main/pwm_logs.h create mode 100644 Inu/Src2/551/main/pwm_test_lines.c create mode 100644 Inu/Src2/551/main/pwm_test_lines.h create mode 100644 Inu/Src2/551/main/ramp_zadanie_tools.c create mode 100644 Inu/Src2/551/main/ramp_zadanie_tools.h create mode 100644 Inu/Src2/551/main/sbor_shema.c create mode 100644 Inu/Src2/551/main/sbor_shema.h create mode 100644 Inu/Src2/551/main/sim_model.c create mode 100644 Inu/Src2/551/main/sim_model.h create mode 100644 Inu/Src2/551/main/sync_tools.c create mode 100644 Inu/Src2/551/main/sync_tools.h create mode 100644 Inu/Src2/551/main/synhro_tools.c create mode 100644 Inu/Src2/551/main/synhro_tools.h create mode 100644 Inu/Src2/551/main/temper_p_tools.c create mode 100644 Inu/Src2/551/main/temper_p_tools.h create mode 100644 Inu/Src2/551/main/tk_Test.c create mode 100644 Inu/Src2/551/main/tk_Test.h create mode 100644 Inu/Src2/551/main/ukss_tools.c create mode 100644 Inu/Src2/551/main/ukss_tools.h create mode 100644 Inu/Src2/551/main/uom_tools.c create mode 100644 Inu/Src2/551/main/uom_tools.h create mode 100644 Inu/Src2/551/main/v_pwm24_v2.c create mode 100644 Inu/Src2/551/main/v_pwm24_v2.h create mode 100644 Inu/Src2/551/main/v_rotor.c create mode 100644 Inu/Src2/551/main/v_rotor.h create mode 100644 Inu/Src2/551/main/v_rotor_22220.c create mode 100644 Inu/Src2/551/main/v_rotor_22220.h create mode 100644 Inu/Src2/551/main/vector.h create mode 100644 Inu/Src2/551/main/xPlatesAddress.h create mode 100644 controller.ilk diff --git a/Inu/Src/N12_Libs/CAN_Setup.c b/Inu/Src/N12_Libs/CAN_Setup.c new file mode 100644 index 0000000..e43a61c --- /dev/null +++ b/Inu/Src/N12_Libs/CAN_Setup.c @@ -0,0 +1,2201 @@ +#include "CAN_Setup.h" // DSP281x Headerfile Include File + +#include "modbus_table_v2.h" +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "global_time.h" +#include "TuneUpPlane.h" +#include "profile_interrupt.h" + + + + +unsigned int CanTimeOutErrorTR = 0; +unsigned int CanBusOffError = 0; + + + +int enable_can_recive_after_units_box = 0; +int flag_enable_can_from_mpu=0; +int flag_enable_can_from_terminal=0; +long time_pause_enable_can_from_mpu=0; +long time_pause_enable_can_from_terminal=0; +int flag_disable_update_modbus_in_can_from_mpu=0; + +//unsigned long can_base_adr_terminal, can_base_adr_units, can_base_adr_mpu1, can_base_adr_alarm_log; + +//unsigned int enable_profile_led1_can = 1; +//unsigned int enable_profile_led2_can = 0; + +#pragma DATA_SECTION(cycle,".slow_vars") +CYCLE cycle[UNIT_QUA]; + + +#pragma DATA_SECTION(new_cycle_fifo,".slow_vars") +NEW_CYCLE_FIFO new_cycle_fifo; + +#pragma DATA_SECTION(fifo,".slow_vars") +#pragma DATA_SECTION(refo,".slow_vars") +FIFO fifo, refo; + + + + +#pragma DATA_SECTION(BUSY,".slow_vars") +int BUSY = 0; + + +#pragma DATA_SECTION(Unites, ".slow_vars") +int Unites[UNIT_QUA_UNITS][UNIT_LEN]; + +#pragma DATA_SECTION(TerminalUnites, ".slow_vars") +int TerminalUnites[TERMINAL_UNIT_QUA_UNITS][TERMINAL_UNIT_LEN]; + +#pragma DATA_SECTION(CanOpenUnites, ".slow_vars") +int CanOpenUnites[CANOPENUNIT_LEN]; + + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + + +//#pragma DATA_SECTION(CAN_timeout,".slow_vars") +#pragma DATA_SECTION(CAN_timeout,".fast_vars") +// +int CAN_timeout[UNIT_QUA]; +// +#pragma DATA_SECTION(CAN_request_sent,".slow_vars") +int CAN_request_sent[UNIT_QUA]; +// +#pragma DATA_SECTION(CAN_answer_wait,".slow_vars") +int CAN_answer_wait[UNIT_QUA]; +// +#pragma DATA_SECTION(CAN_no_answer,".slow_vars") +int CAN_no_answer[UNIT_QUA]; + +// , +#pragma DATA_SECTION(CAN_refresh_cicle,".slow_vars") +int CAN_refresh_cicle[UNIT_QUA]; +// +#pragma DATA_SECTION(CAN_count_cycle_input_units,".slow_vars") +int CAN_count_cycle_input_units[UNIT_QUA_UNITS]; + +#pragma DATA_SECTION(CAN_timeout_cicle,".fast_vars") +//#pragma DATA_SECTION(CAN_timeout_cicle, ".slow_vars") +// +unsigned int CAN_timeout_cicle[UNIT_QUA]; + + + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +#pragma DATA_SECTION(unites_can_setup, ".slow_vars") +UNITES_CAN_SETUP unites_can_setup = UNITES_CAN_SETUP_DEFAULT; +#pragma DATA_SECTION(mpu_can_setup, ".slow_vars") +MPU_CAN_SETUP mpu_can_setup = MPU_CAN_SETUP_DEFAULT; +#pragma DATA_SECTION(terminal_can_setup, ".slow_vars") +TERMINAL_CAN_SETUP terminal_can_setup = TERMINAL_CAN_SETUP_DEFAULT; +#pragma DATA_SECTION(alarm_log_can_setup, ".slow_vars") +ALARM_LOG_CAN_SETUP alarm_log_can_setup = ALARM_LOG_CAN_SETUP_DEFAULT; + + +#pragma DATA_SECTION(mailboxs_can_setup, ".slow_vars") +MAILBOXS_CAN_SETUP mailboxs_can_setup = MAILBOXS_CAN_SETUP_DEFAULT; + +#pragma DATA_SECTION(canopen_can_setup, ".slow_vars") +CANOPEN_CAN_SETUP canopen_can_setup = CANOPEN_CAN_SETUP_DEFAULT; + + + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +int init_units_can_boxs(UNITES_CAN_SETUP *p) +{ + int c,e; + + e=0; + for (c=0;cactive_box[c]) + { + p->adr_box[c+UNITS_NUMERATION_FROM_0_OR_1] = e; + + if (p->revers_box[c]) // , Unites TMS + { + p->can_in_mbox_adr[e] = p->can_base_adr + c; + p->can_out_mbox_adr[e] = p->can_base_adr + OFFSET_CAN_ADR_UNITS + c; + } + else + { + p->can_out_mbox_adr[e] = p->can_base_adr + c; + p->can_in_mbox_adr[e] = p->can_base_adr + OFFSET_CAN_ADR_UNITS + c; + } +// p->can_in_mbox_adr[e] = START_CAN_ADR_UNITS + c*2; +// p->can_out_mbox_adr[e] = START_CAN_ADR_UNITS + OFFSET_CAN_ADR_UNITS + c*2; + e++; + } + } + + p->max_number = e; + + + return e; +} + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + +int init_canopen_can_boxs(CANOPEN_CAN_SETUP *p) +{ + int i; + +// p->max_number = 8; + for(i = 0; i < CANOPENUNIT_LEN; i++) + CanOpenUnites[i] = 0; + + return 1; +} + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + +int init_mpu_can_boxs(MPU_CAN_SETUP *p ) +{ + int c,e; + + e = 0; + for (c=0;cactive_box[c]) + { + p->adr_box[c] = e; + p->can_out_mbox_adr[e] = p->can_base_adr + c; + p->can_in_mbox_adr[e] = p->can_base_adr + 0x10 + c; //OFFSET_CAN_ADR_MPU + e++; + } + } + + p->max_number = e; + + return e; +} + +///////////////////////////////////////////////////////// + +int init_terminal_can_boxs(TERMINAL_CAN_SETUP *p ) +{ + int c,e; + + e = 0; + for (c=0;cactive_box[c]) + { + p->adr_box[c] = e; + p->can_out_mbox_adr[e] = p->can_base_adr + c; + p->can_in_mbox_adr[e] = p->can_base_adr + 0x10 + c; //OFFSET_CAN_ADR_MPU + e++; + } + } + + p->max_number = e; + + return e; +} + + +///////////////////////////////////////////////////////// +int init_alarm_log_can_boxs(ALARM_LOG_CAN_SETUP *p ) +{ + int c,e; + + e = 0; + for (c=0;cactive_box[c]) + { + p->adr_box[c] = e; + p->can_out_mbox_adr[e] = p->can_base_adr + c; + p->can_in_mbox_adr[e] = p->can_base_adr + 0x10 + c; //OFFSET_CAN_ADR_MPU + e++; + } + } + + p->max_number = e; + + return e; +} + + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + +void init_mailboxs_can( UNITES_CAN_SETUP *p_units, + MPU_CAN_SETUP *p_mpu, + TERMINAL_CAN_SETUP *p_terminal, + ALARM_LOG_CAN_SETUP *p_alarm_log, + CANOPEN_CAN_SETUP *p_canopen, + MAILBOXS_CAN_SETUP *p_mailboxs ) +{ + volatile int c,e,max_number_in,max_number_out; + + e = 0; + max_number_in = 0; + max_number_out = 0; + + if (p_units->max_number>0) + { + for (c=0;cmax_number;c++) + { + p_mailboxs->can_mbox_adr[e] = p_units->can_in_mbox_adr[c] | 0x80000000; + p_mailboxs->type_in_out_box[e] = CAN_BOX_TYPE_IN; + p_mailboxs->local_number_box[e] = c; + p_mailboxs->type_box[e] = UNITS_TYPE_BOX; + + p_units->adr_in_mbox[c] = e; + + max_number_in++; + e++; + + p_mailboxs->can_mbox_adr[e] = p_units->can_out_mbox_adr[c] | 0x80000000; + p_mailboxs->type_in_out_box[e] = CAN_BOX_TYPE_OUT; + p_mailboxs->local_number_box[e] = c; + p_mailboxs->type_box[e] = UNITS_TYPE_BOX; + + p_units->adr_out_mbox[c] = e; + + max_number_out++; + e++; + } + } + + if (p_mpu->max_number>0) + { + for (c=0;cmax_number;c++) + { + p_mailboxs->can_mbox_adr[e] = p_mpu->can_in_mbox_adr[c] | 0x80000000; + p_mailboxs->type_in_out_box[e] = CAN_BOX_TYPE_IN; + p_mailboxs->local_number_box[e] = c; + p_mailboxs->type_box[e] = MPU_TYPE_BOX; + + p_mpu->adr_in_mbox[c] = e; + + max_number_in++; + e++; + + p_mailboxs->can_mbox_adr[e] = p_mpu->can_out_mbox_adr[c] | 0x80000000; + p_mailboxs->type_in_out_box[e] = CAN_BOX_TYPE_OUT; + p_mailboxs->local_number_box[e] = c; + p_mailboxs->type_box[e] = MPU_TYPE_BOX; + + p_mpu->adr_out_mbox[c] = e; + + max_number_out++; + e++; + } + } + + if (p_terminal->max_number>0) + { + for (c=0;cmax_number;c++) + { + p_mailboxs->can_mbox_adr[e] = p_terminal->can_in_mbox_adr[c] | 0x80000000; + p_mailboxs->type_in_out_box[e] = CAN_BOX_TYPE_IN; + p_mailboxs->local_number_box[e] = c; + p_mailboxs->type_box[e] = TERMINAL_TYPE_BOX; + + p_terminal->adr_in_mbox[c] = e; + + max_number_in++; + e++; + + p_mailboxs->can_mbox_adr[e] = p_terminal->can_out_mbox_adr[c] | 0x80000000; + p_mailboxs->type_in_out_box[e] = CAN_BOX_TYPE_OUT; + p_mailboxs->local_number_box[e] = c; + p_mailboxs->type_box[e] = TERMINAL_TYPE_BOX; + + p_terminal->adr_out_mbox[c] = e; + + max_number_out++; + e++; + } + } + + + if (p_alarm_log->max_number>0) + { + for (c=0;cmax_number;c++) + { + p_mailboxs->can_mbox_adr[e] = p_alarm_log->can_in_mbox_adr[c] | 0x80000000; + p_mailboxs->type_in_out_box[e] = CAN_BOX_TYPE_IN; + p_mailboxs->local_number_box[e] = c; + p_mailboxs->type_box[e] = ALARM_LOG_TYPE_BOX; + + p_alarm_log->adr_in_mbox[c] = e; + + max_number_in++; + e++; + + p_mailboxs->can_mbox_adr[e] = p_alarm_log->can_out_mbox_adr[c] | 0x80000000; + p_mailboxs->type_in_out_box[e] = CAN_BOX_TYPE_OUT; + p_mailboxs->local_number_box[e] = c; + p_mailboxs->type_box[e] = ALARM_LOG_TYPE_BOX; + + p_alarm_log->adr_out_mbox[c] = e; + + max_number_out++; + e++; + } + } + + + if (p_canopen->max_number>0) + { + for (c=0;cmax_number;c++) + { + p_mailboxs->can_mbox_adr[e] = p_canopen->can_in_mbox_adr[c]; + p_mailboxs->type_in_out_box[e] = CAN_BOX_TYPE_IN; + p_mailboxs->local_number_box[e] = c; + p_mailboxs->type_box[e] = CANOPEN_TYPE_BOX; + + p_canopen->adr_in_mbox[c] = e; + + max_number_in++; + e++; + } + } + + p_mailboxs->max_number_in = max_number_in; + p_mailboxs->max_number_out = max_number_out; +} + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + +void init_all_mailboxs(unsigned long can_base_adr_units, unsigned long can_base_adr_mpu, unsigned long can_base_adr_alarm_log, unsigned long can_base_adr_terminal) +{ +// + unites_can_setup.can_base_adr = can_base_adr_units; + init_units_can_boxs(&unites_can_setup); +// + mpu_can_setup.can_base_adr = can_base_adr_mpu; + init_mpu_can_boxs(&mpu_can_setup); +// + terminal_can_setup.can_base_adr = can_base_adr_terminal; + init_terminal_can_boxs(&terminal_can_setup); +// + alarm_log_can_setup.can_base_adr = can_base_adr_alarm_log; + init_alarm_log_can_boxs(&alarm_log_can_setup); +// + init_canopen_can_boxs(&canopen_can_setup); +// + init_mailboxs_can(&unites_can_setup, &mpu_can_setup, &terminal_can_setup, &alarm_log_can_setup, &canopen_can_setup, &mailboxs_can_setup); + +} + + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + + + + +void reset_CAN_timeout_cicle(int box) +{ + CAN_timeout_cicle[box]=0; +} + + +#pragma CODE_SECTION(inc_CAN_timeout_cicle, ".fast_run2"); +void inc_CAN_timeout_cicle() +{ + unsigned int i, t_refresh; + static unsigned int old_time = 0; + + t_refresh = get_delta_milisec(&old_time, 1); + if (t_refresh>1000) + t_refresh = 1000; + + + for(i = 0; i < UNIT_QUA; i++) + { + if (CAN_timeout_cicle[i] < MAX_CAN_WAIT_TIMEOUT) + { + CAN_timeout_cicle[i] += t_refresh; + } + else + { + CAN_timeout[i] = 1; + CAN_refresh_cicle[i] = -1; + } + } +} + + + +void InitCan(unsigned long can_base_adr_units, unsigned long can_base_adr_mpu, unsigned long can_base_adr_alarm_log, unsigned long can_base_adr_terminal) +{ + struct ECAN_REGS ECanaShadow; + int i, c; + volatile struct MBOX *tmbox; + volatile Uint32 *tmoto; + + unsigned long canme_bits = 0; + unsigned long canmd_bits = 0; + unsigned long canmim_bits = 0; + + + init_all_mailboxs(can_base_adr_units, can_base_adr_mpu, can_base_adr_alarm_log, can_base_adr_terminal); + +// Configure CAN pins using GPIO regs here + EALLOW; + + GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1; + GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1; + +// Configure the eCAN RX and TX pins for eCAN transmissions + ECanaRegs.CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant + ECanaRegs.CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant + + +// Specify that 8 bits will be sent/received + for (c=0;c<32;c++) + { + tmbox = &ECanaMboxes.MBOX0 + c; + tmbox->MSGCTRL.all = 0x00000008; + } + +// Disable all Mailboxes +// Required before writing the MSGIDs + ECanaRegs.CANME.all = 0; + + canme_bits = 0; + canmd_bits = 0; + canmim_bits = 0; + + // receive+transive //Ura + for (c=0;c<32;c++) + { + + if (mailboxs_can_setup.can_mbox_adr[c]) + { + tmbox = &ECanaMboxes.MBOX0 + c; + if(mailboxs_can_setup.type_box[c] == UNITS_TYPE_BOX) + { +// tmbox->MSGID.bit.IDE = 0; +// tmbox->MSGID.bit.STDMSGID = mailboxs_can_setup.can_mbox_adr[c]; + tmbox->MSGID.all = mailboxs_can_setup.can_mbox_adr[c]; + } + else + { + if(mailboxs_can_setup.type_box[c] == CANOPEN_TYPE_BOX) + { + tmbox->MSGID.bit.IDE = 0; + tmbox->MSGID.bit.STDMSGID = mailboxs_can_setup.can_mbox_adr[c]; + //tmbox->MSGID.all = mailboxs_can_setup.can_mbox_adr[c]; + } + else + tmbox->MSGID.all = mailboxs_can_setup.can_mbox_adr[c]; + } + + canme_bits |= ((unsigned long)1<> 4) ) + return 3; + if (load_level_byte < (NEW_CYCLE_FIFO_LEN >> 2) ) + return 2; + if (load_level_byte < (NEW_CYCLE_FIFO_LEN >> 1) ) + return 1; + + return 0; +} +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// + +int new_cycle_fifo_load(int box, unsigned long adr, int * adr_from, unsigned long addr_to, unsigned long quant, int extended, int priority, int cmd_wait) +{ + unsigned int ind; + + if (((new_cycle_fifo.index_data - new_cycle_fifo.index_send)&NEW_CYCLE_FIFO_LEN_MASK)>=(NEW_CYCLE_FIFO_LEN_MASK-3)) + { + new_cycle_fifo.count_lost++; +// may_be_send_cycle_fifo(); // , -, ! + return -1; // ! + } + + if (new_cycle_fifo.cycle_data[new_cycle_fifo.index_data].box==0) // + { + + new_cycle_fifo.cycle_data[new_cycle_fifo.index_data].box = box; + new_cycle_fifo.cycle_data[new_cycle_fifo.index_data].adr = adr; + new_cycle_fifo.cycle_data[new_cycle_fifo.index_data].adr_to = addr_to; + new_cycle_fifo.cycle_data[new_cycle_fifo.index_data].adr_from = adr_from; + new_cycle_fifo.cycle_data[new_cycle_fifo.index_data].quant = quant; + new_cycle_fifo.cycle_data[new_cycle_fifo.index_data].extended = extended; + new_cycle_fifo.cycle_data[new_cycle_fifo.index_data].priority = priority; + new_cycle_fifo.cycle_data[new_cycle_fifo.index_data].busy = 1; + + + // + new_cycle_fifo.cycle_box[box]++; + + if (new_cycle_fifo.index_data == new_cycle_fifo.index_send) + { + // , + // + + } + + // + new_cycle_fifo.index_data++; + new_cycle_fifo.index_data &= NEW_CYCLE_FIFO_LEN_MASK; +// if (new_cycle_fifo.index_data>=NEW_CYCLE_FIFO_LEN) // +// new_cycle_fifo.index_data = 0; // + +// may_be_send_fifo(); +// if (cmd_wait==0) +// may_be_send_cycle_fifo(); + + return 1; // ! + } + else + { + new_cycle_fifo.count_lost++; + +// may_be_send_cycle_fifo(); // , -, ! + return -1; // ! + } + + +} + +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// + + +int CAN_FLY_free(int box) +{ + return !cycle[box].FLY; +} + + +int CAN_cycle_free(int box) +{ + int i; + +#if (CAN_PROTOCOL_VERSION==2) + + if (new_cycle_fifo.cycle_box[box] >= 200) + { + new_cycle_fifo.lost_box[box]++; + return 0; + } + else + return 1; + +#endif + +#if (CAN_PROTOCOL_VERSION==1) + return !cycle[box].busy; +#endif +} + +int CAN_cycle_full_free(int box, int statistics_flag) +{ + int i; + +#if (CAN_PROTOCOL_VERSION==2) + + if (new_cycle_fifo.cycle_box[box] != 0) + { + if (statistics_flag==CAN_BOX_STAT_ON) + new_cycle_fifo.lost_box[box]++; + return 0; + } + else + return 1; + +#endif + +#if (CAN_PROTOCOL_VERSION==1) + return !cycle[box].busy; +#endif +} +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// + +int CAN_FIFO_free(unsigned int quant) +{ +#if (CAN_PROTOCOL_VERSION==2) + return 0; +#endif + +#if (CAN_PROTOCOL_VERSION==1) + return ((FIFO_LEN-(unsigned int)fifo.adr)>quant); +#endif + +} + +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// + +void CAN_cycle_stop(int box) +{ + cycle[box].busy=0; +} + + +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// + + +#pragma CODE_SECTION(CAN_send2,".fast_run2"); +void CAN_send2(int box,unsigned long hiword, unsigned long loword) +{ + volatile struct MBOX *Mailbox; + unsigned long mask; + +// cycle[box].FLY = 1; + + new_cycle_fifo.flag_inter = 1; + + mask = ((unsigned long)1<MDH.all = hiword; + Mailbox->MDL.all = loword; + + + ECanaRegs.CANTRS.all = mask; + +} + +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +/////////////////////////////////////////////// +int get_real_out_mbox(int type_box, int box) +{ + if (type_box==FREE_TYPE_BOX) + return -1; + + if (type_box==UNITS_TYPE_BOX) + { + if (box new_cycle_fifo.cycle_data[cur_send_index].priority) + && new_cycle_fifo.cycle_data[next_send_index].box) + { + // + new_data = new_cycle_fifo.cycle_data[next_send_index]; + new_cycle_fifo.index_send--; + new_cycle_fifo.index_send &= NEW_CYCLE_FIFO_LEN_MASK; + // -1 + new_cycle_fifo.cycle_data[new_cycle_fifo.index_send] = new_data; + + new_cycle_fifo.cycle_data[next_send_index].box = 0; + new_cycle_fifo.cycle_data[next_send_index].busy = 0; + return; + + } + } while (next_send_index!=new_cycle_fifo.index_data); + + return; + + + + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//#pragma CODE_SECTION(CAN_cycle_fifo_step,".fast_run1"); +int CAN_cycle_fifo_one_box(void) +{ + unsigned long hiword,loword,mask; + unsigned int * point; + unsigned int box=0, index; + + index = new_cycle_fifo.index_send; + // ? ... + if (index == new_cycle_fifo.index_data) + return 0; + // ... . +// if (new_cycle_fifo.cycle_data[index].box==0) +// return; + + // , , quant . + if(new_cycle_fifo.cycle_data[index].adr>=new_cycle_fifo.cycle_data[index].quant || new_cycle_fifo.cycle_data[index].box==0) + { + // + if (new_cycle_fifo.cycle_data[index].box) + new_cycle_fifo.cycle_box[new_cycle_fifo.cycle_data[index].box]--; + // new_fifo + new_cycle_fifo.cycle_data[index].busy = 0; + // , + new_cycle_fifo.cycle_data[index].box = 0; + + // + new_cycle_fifo.index_send++; + new_cycle_fifo.index_send &= NEW_CYCLE_FIFO_LEN_MASK; + + return 0; + } + + +// , + mask = 0xE000; + if(new_cycle_fifo.cycle_data[index].adr==new_cycle_fifo.cycle_data[index].quant-1) mask = 0x8000; + if(new_cycle_fifo.cycle_data[index].adr==new_cycle_fifo.cycle_data[index].quant-2) mask = 0xC000; + + point = (unsigned int *)&hiword; + + // + if (new_cycle_fifo.cycle_data[index].extended == 0) + point[1] = mask | (new_cycle_fifo.cycle_data[index].adr_to + new_cycle_fifo.cycle_data[index].adr); + else + { + // , , mask . + point[1] = (new_cycle_fifo.cycle_data[index].adr_to + new_cycle_fifo.cycle_data[index].adr)/3L; // 3 , 65535*3 = 196605 , extended=1 + } + + // + point[0] = new_cycle_fifo.cycle_data[index].adr_from[new_cycle_fifo.cycle_data[index].adr]; + point = (unsigned int *)&loword; + // + point[1] = new_cycle_fifo.cycle_data[index].adr_from[new_cycle_fifo.cycle_data[index].adr+1]; + // + point[0] = new_cycle_fifo.cycle_data[index].adr_from[new_cycle_fifo.cycle_data[index].adr+2]; + + new_cycle_fifo.cycle_data[index].adr+=3; + + box = new_cycle_fifo.cycle_data[index].box; + + +#if (CAN_PROTOCOL_VERSION==2) + CAN_send2(box,hiword,loword); + //new_fifo_load(box,hiword,loword); +#endif + + + return 1; + +} +//////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////// + +//#pragma CODE_SECTION(CAN_cycle_fifo_step,".fast_run1"); +int CAN_cycle_fifo_step(void) +{ + unsigned long hiword,loword,mask; + unsigned int * point; + unsigned int box=0, index; + + index = new_cycle_fifo.index_send; + // ? ... + if (index==new_cycle_fifo.index_data) + return 0; + // ... . +// if (new_cycle_fifo.cycle_data[index].box==0) +// return; + + if (new_cycle_fifo.flag_inter==0) + { + realign_new_cycle_fifo_on_priority(); + CAN_cycle_fifo_one_box(); + + } + + + return 1; +} +//////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +#define CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCK 333L //99 // 3 +//#pragma CODE_SECTION(CAN_cycle_send,".fast_run2"); +void CAN_cycle_send(int type_box, int box, unsigned long Addr, int * Data, unsigned long quant, int extended, int priority) +{ + int real_mbox; + unsigned int old_time; + + real_mbox = get_real_out_mbox (type_box, box); + if (real_mbox<0) + return; + +#if (CAN_PROTOCOL_VERSION==1) + cycle[real_mbox].adr = 0; + cycle[real_mbox].adr_from = Data; + cycle[real_mbox].adr_to = Addr; + cycle[real_mbox].quant = quant; + cycle[real_mbox].busy = 1; + cycle[real_mbox].extended = extended; + + + CAN_cycle_step(real_mbox); +#endif + + +#if (CAN_PROTOCOL_VERSION==2) + if (priority==CAN_BOX_PRIORITY_LOW) + { + do + { +// if (get_new_cycle_fifo_load_level()<=2) + + if (quant>CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCK) + { + if (new_cycle_fifo_load (real_mbox, 0, Data, Addr, CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCK, extended, priority, 1) == 1) + { + quant -= CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCK; + Data += CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCK; + Addr += CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCK; + } + } + else + { + new_cycle_fifo_load (real_mbox, 0, Data, Addr, quant, extended, priority, 0); + quant = 0; + } + + } + while (quant>0); + +// + + } + else + new_cycle_fifo_load (real_mbox, 0, Data, Addr, quant, extended, priority, 0); + +#endif + +} +//////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void detect_time_refresh_units(int box, int adr) +{ + if (box>=UNIT_QUA_UNITS) + return; + + if (adr==unites_can_setup.adr_detect_refresh[box]) + { + //CAN_count_cycle_input_units[box]++; + if (box=MPU_UNIT_QUA_UNITS) + return; + + if (adr==mpu_can_setup.adr_detect_refresh[box]) + { + //CAN_count_cycle_input_units[box]++; + if (box> 16 ) & 0xffff; + CanOpenUnites[adr+1] = (h_word ) & 0xffff; + CanOpenUnites[adr+2] = (l_word >> 16 ) & 0xffff; + CanOpenUnites[adr+3] = (l_word ) & 0xffff; + } +} + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +void parse_data_from_mbox(unsigned int box, unsigned long hiword, + unsigned long loword) +{ + unsigned int bit[3], real_mbox; + int local_number_box; + int adr; + static int reply_box = 0; + static volatile int err=0; + + +//////////////////////////////////////////////////////////////////// +// CAN OPEN +//////////////////////////////////////////////////////////////////// + + if (mailboxs_can_setup.type_box[box] == CANOPEN_TYPE_BOX) + { +#ifdef BWC_CAN_FATEC + messageParserToUnites(box, hiword, loword); +#endif +#ifdef BWC_CAN_SIEMENS + messageParserToUnitesSiemens(box, hiword, loword); +#endif +#ifdef INGITIM_CAN_OPEN + messagePaserToUnitesIngitim(box, hiword, loword); +#endif +// messageParser(box, hiword, loword); + return; + } + + adr = hiword >> 16; + bit[0] = adr & 0x8000; + bit[1] = adr & 0x4000; + bit[2] = adr & 0x2000; + adr &= 0x1fff; +// ------------------------------------------------------------------------- +// CAN-, 8 : +// | 3 | (13 ) | data1 | data2 | data3 | +// : [0|1] - dataX +// : +// "" : =data1, +1=data2, +2=data3 +// "" : , +2, +3 +// , = "1". +// ------------------------------------------------------------------------- + + +//////////////////////////////////////////////////////////////////// +//SMPU_CAN_DEVICE - ID = 0x80CEB0E1; +//////////////////////////////////////////////////////////////////// + +/* if (mailboxs_can_setup.type_box[box] == SMPU_TYPE_BOX) + { + if (adr==5 || adr==1) + { + run_cmd_super_can_5(adr,(unsigned int)((hiword ) & 0xffff),(unsigned int)((loword>>16) & 0xffff),(unsigned int)((loword) & 0xffff)); + } + else + ready_run_cmd_super_can(adr,(unsigned int)((hiword ) & 0xffff),(unsigned int)((loword>>16) & 0xffff),(unsigned int)((loword) & 0xffff)); + + return; + } + +*/ + +/////////////////////////////////////////////////////////////////// +//MPU +/////////////////////////////////////////////////////////////////// + + if (mailboxs_can_setup.type_box[box] == MPU_TYPE_BOX) + { + local_number_box = mailboxs_can_setup.local_number_box[box]; + if (local_number_box>=MPU_UNIT_QUA_UNITS) + return; + + if(bit[0]) + { + timer_pause_enable_can_from_mpu(); + if (adr0) + { + if (flag_enable_can_from_mpu && flag_disable_update_modbus_in_can_from_mpu==0) + modbus_table_can_in[adr-1].all = /*(unsigned int)*/((hiword ) & 0xffff); + detect_time_refresh_mpu(local_number_box,adr-1); + } + adr++; + } + else + { + err++; + } + } + if(bit[1]) + { + timer_pause_enable_can_from_mpu(); + if (adr0) + { + if (flag_enable_can_from_mpu && flag_disable_update_modbus_in_can_from_mpu==0) + modbus_table_can_in[adr-1].all = /*(unsigned int)*/((loword>>16) & 0xffff); + detect_time_refresh_mpu(local_number_box,adr-1); + } + adr++; + } + else + { + err++; + } + } + + if(bit[2]) + { + timer_pause_enable_can_from_mpu(); + if (adr0) + { + if (flag_enable_can_from_mpu && flag_disable_update_modbus_in_can_from_mpu==0) + modbus_table_can_in[adr-1].all = /*(unsigned int)*/((loword) & 0xffff); + detect_time_refresh_mpu(local_number_box,adr-1); + } + adr++; + } + else + { + err++; + } + } + real_mbox = get_real_in_mbox (MPU_TYPE_BOX, 0); + + return; + } + +/////////////////////////////////////////////////////////////////// +//TERMINAL +//////////////////////////////////////////////////////////////////// + + if (mailboxs_can_setup.type_box[box] == TERMINAL_TYPE_BOX) + { + local_number_box = mailboxs_can_setup.local_number_box[box]; + if (local_number_box>=TERMINAL_UNIT_QUA_UNITS) + return; + + if(bit[0]) + { + timer_pause_enable_can_from_terminal(); + if (adr=0) && flag_enable_can_from_terminal) + { + TerminalUnites[local_number_box][adr] = /*(unsigned int)*/((hiword ) & 0xffff); + } + adr++; + } + } + if(bit[1]) + { + timer_pause_enable_can_from_terminal(); + if (adr=0) && flag_enable_can_from_terminal) + { + TerminalUnites[local_number_box][adr] = /*(unsigned int)*/((loword>>16) & 0xffff); + } + adr++; + } + } + + if(bit[2]) + { + timer_pause_enable_can_from_terminal(); + if (adr=0) && flag_enable_can_from_terminal) + { + TerminalUnites[local_number_box][adr] = /*(unsigned int)*/((loword) & 0xffff); + } + adr++; + } + } + + return; + } + +//////////////////////////////////////////////////////////////////// +//UKSS +//////////////////////////////////////////////////////////////////// + if (mailboxs_can_setup.type_box[box] == UNITS_TYPE_BOX) + { + local_number_box = mailboxs_can_setup.local_number_box[box]; + + if (local_number_box>=UNIT_QUA_UNITS) + return; + + if(bit[0]) + { + if ( (adr=0) ) + { + Unites[local_number_box][adr] = (hiword ) & 0xffff; + detect_time_refresh_units(local_number_box,adr); + } + adr++; + } + + + if(bit[1]) + { + if ( (adr=0) ) + { + Unites[local_number_box][adr] = ((loword>>16) & 0xffff); + detect_time_refresh_units(local_number_box,adr); + } + adr++; + } + + if(bit[2]) + { + if ( (adr=0) ) + { + Unites[local_number_box][adr] = (loword ) & 0xffff; + detect_time_refresh_units(local_number_box,adr); + } + adr++; + } + + return; + } +} + + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + +//#pragma CODE_SECTION(CAN_handler,".fast_run"); +interrupt void CAN_handler(void) +{ + volatile struct MBOX *Mailbox; + unsigned long hiword, loword, mask = 1; + int box,type_in_out_box, box_i; + + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + + PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.can) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.can) + i_led2_on_off_special(1); +#endif + + EINT; + + box = ECanaRegs.CANGIF0.bit.MIV0; + + mask <<= box; + + type_in_out_box = mailboxs_can_setup.type_in_out_box[box]; + + if(type_in_out_box == CAN_BOX_TYPE_OUT) + { + cycle[box].FLY=0; +// new_cycle_fifo.flag_inter = 0; + + ECanaRegs.CANTA.all = mask; + ECanaRegs.CANAA.all = mask; + +#ifdef SUPER_CAN + if(box == SMPU_CAN_DEVICE_TRANSMIT) // SMPU_CAN_DEVICE_TRANSMIT - ID = 0x80CEB0F1; + { + loword = Mailbox->MDL.all; + hiword = Mailbox->MDH.all; + adr = (hiword >> 16) & 0x1FFF; + if(adr == 5) // + { + flag_send_mess_super_can = 1; + } + } +#endif + +#if (CAN_PROTOCOL_VERSION==1) + if(!BUSY && fifo.adr && !cycle[fifo.pak[fifo.adr-1].box].FLY) + { + BUSY=1; + fifo.adr--; + CAN_send( fifo.pak[fifo.adr].box, + fifo.pak[fifo.adr].hiword, + fifo.pak[fifo.adr].loword); + BUSY=0; + } + else if(refo.adr && !cycle[refo.pak[refo.adr-1].box].FLY) + { + refo.adr--; + CAN_send( refo.pak[refo.adr].box, + refo.pak[refo.adr].hiword, + refo.pak[refo.adr].loword); + } + + if(cycle[box].busy) // 26.01.2011 Dimas + CAN_cycle_step(box); // 26.01.2011 Dimas +#endif + + + + +#if (CAN_PROTOCOL_VERSION==2) + + new_cycle_fifo.flag_inter = CAN_cycle_fifo_one_box();//CAN_cycle_fifo_step(new_cycle_fifo.index_send); + +// // +// new_fifo_unload(); +// +// // +// if(cycle[box].busy) // +// CAN_cycle_step(box); // +// +// +// if(cycle[box].busy==0) // +// { +// // +// for (box_i=0;box_iMDL.all; + hiword = Mailbox->MDH.all; + + if (enable_can_recive_after_units_box) + { + parse_data_from_mbox(box, hiword, loword); + } + + CAN_timeout[box]=0; // + CAN_refresh_cicle[box]=CAN_timeout_cicle[box]; + CAN_timeout_cicle[box]=0; + +// led2_toggle(); + } + +//#if (CAN_PROTOCOL_VERSION==2) +//// // +//// new_fifo_unload(); +//// +// // +// for (box_i=0;box_i=TIME_PAUSE_CAN_FROM_TERMINAL) + { + time_pause_enable_can_from_terminal=TIME_PAUSE_CAN_FROM_TERMINAL; + flag_enable_can_from_terminal = 1; + } + +} + + +void timer_pause_enable_can_from_mpu(void) +{ + time_pause_enable_can_from_mpu++; + if (time_pause_enable_can_from_mpu>=TIME_PAUSE_CAN_FROM_MPU) + { + time_pause_enable_can_from_mpu=TIME_PAUSE_CAN_FROM_MPU; + flag_enable_can_from_mpu = 1; + } + +} + +unsigned int test_can_live_mpu(void) +{ + if (CAN_timeout[get_real_out_mbox(MPU_TYPE_BOX,0)]==0) + return 1; + else + return 0; +} + + +unsigned int test_can_live_terminal(int n) +{ + if (CAN_timeout[get_real_out_mbox(TERMINAL_TYPE_BOX,n)]==0) + return 1; + else + return 0; +} + + + +void InitCanSoft(void) +{ + struct ECAN_REGS ECanaShadow; + int i, c; + volatile struct MBOX *tmbox; + volatile Uint32 *tmoto; + + unsigned long canme_bits = 0; + unsigned long canmd_bits = 0; + unsigned long canmim_bits = 0; + + +// Configure CAN pins using GPIO regs here + EALLOW; + +// GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1; +// GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1; + +// Configure the eCAN RX and TX pins for eCAN transmissions +// ECanaRegs.CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant +// ECanaRegs.CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant + + +// Specify that 8 bits will be sent/received +// for (c=0;c<32;c++) +// { +// tmbox = &ECanaMboxes.MBOX0 + c; +// tmbox->MSGCTRL.all = 0x00000008; +// } + +// Disable all Mailboxes +// Required before writing the MSGIDs +// ECanaRegs.CANME.all = 0; + + canme_bits = 0; + canmd_bits = 0; + canmim_bits = 0; + + // receive+transive //Ura + for (c=0;c<32;c++) + { + + if (mailboxs_can_setup.can_mbox_adr[c]) + { +// tmbox = &ECanaMboxes.MBOX0 + c; +// if(mailboxs_can_setup.type_box[c] == UNITS_TYPE_BOX) +// { +//// tmbox->MSGID.bit.IDE = 0; +//// tmbox->MSGID.bit.STDMSGID = mailboxs_can_setup.can_mbox_adr[c]; +// tmbox->MSGID.all = mailboxs_can_setup.can_mbox_adr[c]; +// } +// else +// { +// if(mailboxs_can_setup.type_box[c] == CANOPEN_TYPE_BOX) +// { +// tmbox->MSGID.bit.IDE = 0; +// tmbox->MSGID.bit.STDMSGID = mailboxs_can_setup.can_mbox_adr[c]; +// //tmbox->MSGID.all = mailboxs_can_setup.can_mbox_adr[c]; +// } +// else +// tmbox->MSGID.all = mailboxs_can_setup.can_mbox_adr[c]; +// } + + canme_bits |= ((unsigned long)1< + +#include "word_structurs.h" +#include "DSP281x_Device.h" + +#define MAX_COUNT_UNITES_TERMINAL 4 // +#define MAX_COUNT_UNITES_UKSS 16 // +#define MAX_COUNT_UNITES_MPU 4 // +#define MAX_COUNT_UNITES_ALARM_LOG 2 // + +//////////////////////////////////////// + +#define CAN_ADR_TERMINAL_DEFAULT 0x00EEEE01 +#define START_CAN_ADR_UNITS_DEFAULT 0x00235500 +#define CAN_ADR_MPU_DEFAULT 0x00CEB0E1 +#define CAN_ADR_ALARM_LOG_DEFAULT 0x0BCDEF01 + + +//////////////////////////////////////// +// - MPU +// CAN_project.c +//////////////////////////////////////// + +#ifndef USE_MPU_0 +#define USE_MPU_0 0 +#endif + +#ifndef USE_MPU_1 +#define USE_MPU_1 0 +#endif + +#ifndef USE_MPU_2 +#define USE_MPU_2 0 +#endif + +#ifndef USE_MPU_3 +#define USE_MPU_3 0 +#endif + + + +#define MPU_UNIT_QUA_UNITS ( USE_MPU_0 + USE_MPU_1 \ + + USE_MPU_2 + USE_MPU_3 \ + ) //- MPU_CAN + + + + + +/////////////////////////////////////////// +// - TERMINAL_CAN +/////////////////////////////////////////// + +//////////////////////////////////////// +// - TERMINAL +// CAN_project.c +//////////////////////////////////////// +#ifndef USE_TERMINAL_1_OSCIL +#define USE_TERMINAL_1_OSCIL 0 +#endif + +#ifndef USE_TERMINAL_1_CMD +#define USE_TERMINAL_1_CMD 0 +#endif + +#ifndef USE_TERMINAL_2_OSCIL +#define USE_TERMINAL_2_OSCIL 0 +#endif + +#ifndef USE_TERMINAL_2_CMD +#define USE_TERMINAL_2_CMD 0 +#endif + + + +#define TERMINAL_UNIT_QUA_UNITS ( USE_TERMINAL_1_OSCIL + USE_TERMINAL_1_CMD \ + + USE_TERMINAL_2_OSCIL + USE_TERMINAL_2_CMD \ + ) //- TERMINAL_CAN + + +//////////////////////////////////////// +// - ALARM_LOG +// CAN_project.c +//////////////////////////////////////// + +#ifndef USE_ALARM_LOG_0 +#define USE_ALARM_LOG_0 0 +#endif + +#ifndef USE_ALARM_LOG_1 +#define USE_ALARM_LOG_1 0 +#endif + + + +#define ALARM_LOG_UNIT_QUA_UNITS ( USE_ALARM_LOG_0 + USE_ALARM_LOG_1 \ + ) //- ALARM_LOG_CAN + + + + + + +//////////////////////////////////////// +// - ukss +// CAN_project.c +//////////////////////////////////////// + +#ifndef USE_UKSS_0 +#define USE_UKSS_0 0 +#endif + +#ifndef USE_UKSS_1 +#define USE_UKSS_1 0 +#endif + +#ifndef USE_UKSS_2 +#define USE_UKSS_2 0 +#endif + +#ifndef USE_UKSS_3 +#define USE_UKSS_3 0 +#endif + +#ifndef USE_UKSS_4 +#define USE_UKSS_4 0 +#endif + +#ifndef USE_UKSS_5 +#define USE_UKSS_5 0 +#endif + +#ifndef USE_UKSS_6 +#define USE_UKSS_6 0 +#endif + +#ifndef USE_UKSS_7 +#define USE_UKSS_7 0 +#endif + +#ifndef USE_UKSS_8 +#define USE_UKSS_8 0 +#endif + +#ifndef USE_UKSS_9 +#define USE_UKSS_9 0 +#endif + +#ifndef USE_UKSS_10 +#define USE_UKSS_10 0 +#endif + +#ifndef USE_UKSS_11 +#define USE_UKSS_11 0 +#endif + +#ifndef USE_UKSS_12 +#define USE_UKSS_12 0 +#endif + +#ifndef USE_UKSS_13 +#define USE_UKSS_13 0 +#endif + +#ifndef USE_UKSS_14 +#define USE_UKSS_14 0 +#endif + +#ifndef USE_UKSS_15 +#define USE_UKSS_15 0 +#endif + + +#ifndef USE_R_B_0 +#define USE_R_B_0 0 +#endif +#ifndef USE_R_B_1 +#define USE_R_B_1 0 +#endif +#ifndef USE_R_B_2 +#define USE_R_B_2 0 +#endif +#ifndef USE_R_B_3 +#define USE_R_B_3 0 +#endif +#ifndef USE_R_B_4 +#define USE_R_B_4 0 +#endif +#ifndef USE_R_B_5 +#define USE_R_B_5 0 +#endif +#ifndef USE_R_B_6 +#define USE_R_B_6 0 +#endif +#ifndef USE_R_B_7 +#define USE_R_B_7 0 +#endif +#ifndef USE_R_B_8 +#define USE_R_B_8 0 +#endif +#ifndef USE_R_B_9 +#define USE_R_B_9 0 +#endif +#ifndef USE_R_B_10 +#define USE_R_B_10 0 +#endif +#ifndef USE_R_B_11 +#define USE_R_B_11 0 +#endif +#ifndef USE_R_B_12 +#define USE_R_B_12 0 +#endif +#ifndef USE_R_B_13 +#define USE_R_B_13 0 +#endif +#ifndef USE_R_B_14 +#define USE_R_B_14 0 +#endif +#ifndef USE_R_B_15 +#define USE_R_B_15 0 +#endif + + +#define UNIT_QUA_UNITS ( USE_UKSS_0 + USE_UKSS_1 \ + + USE_UKSS_2 + USE_UKSS_3 \ + + USE_UKSS_4 + USE_UKSS_5 \ + + USE_UKSS_6 + USE_UKSS_7 \ + + USE_UKSS_8 + USE_UKSS_9 \ + + USE_UKSS_10 + USE_UKSS_11 \ + + USE_UKSS_12 + USE_UKSS_13 \ + + USE_UKSS_14 + USE_UKSS_15) // 2 //3//8 // CAN CANMODBUS - - Unites + +/////////////////////////////////////////// +// CAN_Open +/////////////////////////////////////////// + +#ifdef INGITIM_CAN_OPEN + #define MBOX0_CANOPEN 0x00000013 //0x180 t1PDO1 + #define MBOX1_CANOPEN 0x0000018d //0x280 t2PDO1 + #define MBOX2_CANOPEN 0x000000c5 //0x380 t3PDO1 + #define MBOX3_CANOPEN 0x12000000 //0x480 t4PDO1 + #define MBOX4_CANOPEN 0x16000000 //0x580 t4PDO1 + #define MBOX5_CANOPEN 0x1a000000 //0x680 t4PDO1 + +#define CANOPEN_CAN_SETUP_DEFAULT { {MBOX0_CANOPEN,MBOX1_CANOPEN,MBOX2_CANOPEN,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {0,1,2,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}, \ + {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}, \ + 3} + +#endif + + +#ifdef BWC_CAN_FATEC + #define MBOX0_CANOPEN 0x08040000 //201; 010 0000 0001 + #define MBOX1_CANOPEN 0x0C040000 //301; 011 0000 0001 + #define MBOX2_CANOPEN 0x10040000 //401; 100 0000 0001 + #define MBOX3_CANOPEN 0x14040000 //501; 101 0000 0001 + #define MBOX4_CANOPEN 0x08080000 //202; 010 0000 0010 + #define MBOX5_CANOPEN 0x0C080000 //302; 011 0000 0010 + #define MBOX6_CANOPEN 0x10080000 //402; 100 0000 0010 + #define MBOX7_CANOPEN 0x14080000 //502; 101 0000 0010 + +#define CANOPEN_CAN_SETUP_DEFAULT { {MBOX0_CANOPEN,MBOX1_CANOPEN,MBOX2_CANOPEN,MBOX3_CANOPEN,MBOX4_CANOPEN,MBOX5_CANOPEN,MBOX6_CANOPEN,MBOX7_CANOPEN,0,0,0,0,0,0,0,0}, \ + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {0,1,2,3,4,5,6,7,-1,-1,-1,-1,-1,-1,-1,-1}, \ + {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}, \ + 0} + +#endif + +#ifdef BWC_CAN_SIEMENS + #define MBOX0_CANOPEN 0x00040000 // 0x08040000 //201; 010 0000 0001 + #define MBOX1_CANOPEN 0x00080000 //301; 011 0000 0001 + +#define CANOPEN_CAN_SETUP_DEFAULT { {MBOX0_CANOPEN,MBOX1_CANOPEN,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {0,1,2,3,4,5,6,7,-1,-1,-1,-1,-1,-1,-1,-1}, \ + {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}, \ + 0} +#endif + + +#ifndef CANOPEN_CAN_SETUP_DEFAULT +#define CANOPEN_CAN_SETUP_DEFAULT { {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}, \ + {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}, \ + 0} +#endif + + +///////////////////////////////////////////////////////////////////// + + + + + +extern int CAN_input_data[]; +extern int CAN_output_data[]; +extern int* CAN_output; + +extern int flag_enable_can_from_mpu; + + +///////////////////////////////////////////////////////////////////// + + +#define UNIT_QUA 32 //12 // CAN - + + + +#define TERMINAL_UNIT_LEN 128 +#define UNIT_LEN 128 +#define FIFO_LEN 10 +#define NEW_FIFO_LEN 128 +#define NEW_CYCLE_FIFO_LEN 256 +#define NEW_CYCLE_FIFO_LEN_MASK (NEW_CYCLE_FIFO_LEN-1) + + + + +//////////////////////////////////////////////////// +//////////////////////////////////////////////////// +//////////////////////////////////////////////////// + +typedef struct +{ + int * adr_from; + unsigned int adr_to; + unsigned int adr; + unsigned int quant; + int busy; + int FLY; + int extended; + +} CYCLE; + + +typedef struct +{ + int * adr_from; + unsigned long adr_to; + unsigned long adr; + unsigned long quant; + int busy; + int FLY; + int extended; + int box; + int priority; + unsigned int quant_block; + +} NEW_CYCLE_DATA; + +typedef struct +{ + int box; + long hiword; + long loword; + +} PACK; + + + +typedef struct +{ + int adr; + PACK pak[FIFO_LEN]; + +}FIFO; + + +typedef struct +{ + int index_data; // + int index_send; // + int flag_inter; // + unsigned int count_lost; // + unsigned int count_load; // + unsigned int count_free; // + NEW_CYCLE_DATA cycle_data[NEW_CYCLE_FIFO_LEN]; + int cycle_box[UNIT_QUA]; + int lost_box[UNIT_QUA]; + + +}NEW_CYCLE_FIFO; + +////////////////////////////////////// +////////////////////////////////////// +////////////////////////////////////// + +#define USE_BOX 1 +#define NOT_USE_BOX 0 + +#define CAN_BOX_TYPE_IN 1 +#define CAN_BOX_TYPE_OUT 2 + + +#define FREE_TYPE_BOX 0 +#define UNITS_TYPE_BOX 1 +#define MPU_TYPE_BOX 2 +#define CANOPEN_TYPE_BOX 3 +#define SMPU_TYPE_BOX 4 +#define TERMINAL_TYPE_BOX 5 +#define ALARM_LOG_TYPE_BOX 6 + +///////////////////////////////////////////////////////////////////// + +#define CAN_BOX_PRIORITY_NORMAL 0 +#define CAN_BOX_PRIORITY_LOW -1 +#define CAN_BOX_PRIORITY_HIGH 1 + +///////////////////////////////////////////////////////////////////// +#define CAN_BOX_EXTENDED_ADR 1 +#define CAN_BOX_STANDART_ADR 0 +///////////////////////////////////////////////////////////////////// +#define CAN_BOX_STAT_ON 1 +#define CAN_BOX_STAT_OFF 0 +///////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////// + +typedef struct { + long can_in_mbox_adr[16]; + long can_out_mbox_adr[16]; + int adr_box[16]; + int adr_in_mbox[16]; + + int max_number; + +} CANOPEN_CAN_SETUP; + +///////////////////////////////////////////////////////////////////// +typedef struct { + long can_mbox_adr[32]; +// long can_out_mbox_adr[16]; + int type_box[32]; + int local_number_box[32]; + int type_in_out_box[32]; + + int max_number_in; + int max_number_out; + +} MAILBOXS_CAN_SETUP; + +#define MAILBOXS_CAN_SETUP_DEFAULT { {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + 0, \ + 0} + + +///////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////// + + +typedef struct { + unsigned long can_base_adr; + long can_in_mbox_adr[MAX_COUNT_UNITES_UKSS]; + long can_out_mbox_adr[MAX_COUNT_UNITES_UKSS]; + int adr_box[MAX_COUNT_UNITES_UKSS+1]; + int adr_in_mbox[MAX_COUNT_UNITES_UKSS+1]; + int adr_out_mbox[MAX_COUNT_UNITES_UKSS+1]; + + int active_box[MAX_COUNT_UNITES_UKSS]; + int adr_detect_refresh[MAX_COUNT_UNITES_UKSS]; + int revers_box[MAX_COUNT_UNITES_UKSS]; + + unsigned int CAN_count_cycle_input_units[MAX_COUNT_UNITES_UKSS]; + + int max_number; + +} UNITES_CAN_SETUP; + +///////////////////////////////////////////////////////////////////// + +typedef struct { + unsigned long can_base_adr; + long can_in_mbox_adr[MAX_COUNT_UNITES_MPU]; + long can_out_mbox_adr[MAX_COUNT_UNITES_MPU]; + int adr_box[MAX_COUNT_UNITES_MPU]; + + int adr_in_mbox[MAX_COUNT_UNITES_MPU]; + int adr_out_mbox[MAX_COUNT_UNITES_MPU]; + + int active_box[MAX_COUNT_UNITES_MPU]; + + unsigned int CAN_count_cycle_input_units[MAX_COUNT_UNITES_MPU]; + + + int adr_detect_refresh[MAX_COUNT_UNITES_MPU]; + + int max_number; + +} MPU_CAN_SETUP; + +///////////////////////////////////////////////////////////////////// + +typedef struct { + unsigned long can_base_adr; + long can_in_mbox_adr[MAX_COUNT_UNITES_TERMINAL]; + long can_out_mbox_adr[MAX_COUNT_UNITES_TERMINAL]; + int adr_box[MAX_COUNT_UNITES_TERMINAL]; + + int adr_in_mbox[MAX_COUNT_UNITES_TERMINAL]; + int adr_out_mbox[MAX_COUNT_UNITES_TERMINAL]; + + int active_box[MAX_COUNT_UNITES_TERMINAL]; + + unsigned int CAN_count_cycle_input_units[MAX_COUNT_UNITES_TERMINAL]; + + int max_number; + +} TERMINAL_CAN_SETUP; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////// + +typedef struct { + unsigned long can_base_adr; + long can_in_mbox_adr[MAX_COUNT_UNITES_ALARM_LOG]; + long can_out_mbox_adr[MAX_COUNT_UNITES_ALARM_LOG]; + int adr_box[MAX_COUNT_UNITES_ALARM_LOG]; + + int adr_in_mbox[MAX_COUNT_UNITES_ALARM_LOG]; + int adr_out_mbox[MAX_COUNT_UNITES_ALARM_LOG]; + + int active_box[MAX_COUNT_UNITES_ALARM_LOG]; + + unsigned int CAN_count_cycle_input_units[MAX_COUNT_UNITES_ALARM_LOG]; + + int max_number; + +} ALARM_LOG_CAN_SETUP; + +//////////////////////////////////////////////////////////////////////////////// +#define _UNITS_DEFAULT_ZERO {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} +#define _UNITS_DEFAULT_MINUS_ONE {-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1} + +#define UNITES_CAN_SETUP_DEFAULT { START_CAN_ADR_UNITS_DEFAULT, _UNITS_DEFAULT_ZERO, \ + _UNITS_DEFAULT_ZERO, \ + _UNITS_DEFAULT_MINUS_ONE, \ + _UNITS_DEFAULT_MINUS_ONE, \ + _UNITS_DEFAULT_MINUS_ONE, \ + {USE_UKSS_0,USE_UKSS_1,USE_UKSS_2,USE_UKSS_3,USE_UKSS_4,USE_UKSS_5, \ + USE_UKSS_6,USE_UKSS_7,USE_UKSS_8,USE_UKSS_9,USE_UKSS_10, \ + USE_UKSS_11,USE_UKSS_12,USE_UKSS_13,USE_UKSS_14,USE_UKSS_15}, \ + _UNITS_DEFAULT_ZERO, \ + {USE_R_B_0,USE_R_B_1,USE_R_B_2,USE_R_B_3,USE_R_B_4,USE_R_B_5,USE_R_B_6,USE_R_B_7,USE_R_B_8, \ + USE_R_B_9,USE_R_B_10,USE_R_B_11,USE_R_B_12,USE_R_B_13,USE_R_B_14,USE_R_B_15}, \ + _UNITS_DEFAULT_ZERO, \ + 0} + +///////////////////////////////////////////////////////////////////// + +#define _MPU_DEFAULT_ZERO {0,0,0,0} +#define _MPU_DEFAULT_MINUS_ONE {-1,-1,-1,-1} + +#define MPU_CAN_SETUP_DEFAULT { CAN_ADR_MPU_DEFAULT, _MPU_DEFAULT_ZERO, \ + _MPU_DEFAULT_ZERO, \ + _MPU_DEFAULT_MINUS_ONE, \ + _MPU_DEFAULT_MINUS_ONE, \ + _MPU_DEFAULT_MINUS_ONE, \ + {USE_MPU_0,USE_MPU_1,USE_MPU_2,USE_MPU_3}, \ + _MPU_DEFAULT_ZERO, \ + _MPU_DEFAULT_ZERO, \ + 0} + +//-------------------------------------------------------------------------------// + +#define _TERMINAL_DEFAULT_ZERO {0,0,0,0} +#define _TERMINAL_DEFAULT_MINUS_ONE {-1,-1,-1,-1} + +#define TERMINAL_CAN_SETUP_DEFAULT {CAN_ADR_TERMINAL_DEFAULT, _TERMINAL_DEFAULT_ZERO, \ + _TERMINAL_DEFAULT_ZERO, \ + _TERMINAL_DEFAULT_MINUS_ONE, \ + _TERMINAL_DEFAULT_MINUS_ONE, \ + _TERMINAL_DEFAULT_MINUS_ONE, \ + {USE_TERMINAL_1_OSCIL,USE_TERMINAL_1_CMD,USE_TERMINAL_2_OSCIL,USE_TERMINAL_2_CMD}, \ + _TERMINAL_DEFAULT_ZERO, \ + 0} +//-------------------------------------------------------------------------------// +#define _ALARM_LOG_DEFAULT_ZERO {0,0} +#define _ALARM_LOG_DEFAULT_MINUS_ONE {-1,-1} + +#define ALARM_LOG_CAN_SETUP_DEFAULT {CAN_ADR_ALARM_LOG_DEFAULT, _ALARM_LOG_DEFAULT_ZERO, \ + _ALARM_LOG_DEFAULT_ZERO, \ + _ALARM_LOG_DEFAULT_MINUS_ONE, \ + _ALARM_LOG_DEFAULT_MINUS_ONE, \ + _ALARM_LOG_DEFAULT_MINUS_ONE, \ + {USE_ALARM_LOG_0,USE_ALARM_LOG_1}, \ + _ALARM_LOG_DEFAULT_ZERO, \ + 0} + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +typedef struct { + WORD_INT2BITS_STRUCT buf[TERMINAL_UNIT_LEN]; +} TERMINAL_UNITES_STRUCT; +//// +typedef TERMINAL_UNITES_STRUCT *TERMINAL_UNITES_STRUCT_handle; +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + + +extern int TerminalUnites[TERMINAL_UNIT_QUA_UNITS][TERMINAL_UNIT_LEN]; + +extern int Unites[UNIT_QUA_UNITS][UNIT_LEN]; + + +//////////////////////////////////////////////////////////////////////////////// +extern CYCLE cycle[]; // 26.01.2011 Dimas + + +extern NEW_CYCLE_FIFO new_cycle_fifo; + +extern int CanOpenUnites[CANOPENUNIT_LEN]; + +//add yura +extern MAILBOXS_CAN_SETUP mailboxs_can_setup; + +extern FIFO fifo; + +extern int CAN_timeout[]; +extern int CAN_request_sent[]; +extern unsigned int CAN_timeout_cicle[]; + + +////////////////////////////////////////////////// +////////////////////////////////////////////////// +int init_units_can_boxs(UNITES_CAN_SETUP *p); +int init_canopen_can_boxs(CANOPEN_CAN_SETUP *p); +int init_mpu_can_boxs(MPU_CAN_SETUP *p ); +int init_terminal_can_boxs(TERMINAL_CAN_SETUP *p ); +int init_alarm_log_can_boxs(ALARM_LOG_CAN_SETUP *p ); +////////////////////////////////////////////////// + +void init_mailboxs_can( UNITES_CAN_SETUP *p_units, + MPU_CAN_SETUP *p_mpu, + TERMINAL_CAN_SETUP *p_terminal, + ALARM_LOG_CAN_SETUP *p_alarm_log, + CANOPEN_CAN_SETUP *p_canopen, + MAILBOXS_CAN_SETUP *p_mailboxs + ); + + +void init_all_mailboxs(unsigned long can_base_adr_units, unsigned long can_base_adr_mpu, unsigned long can_base_adr_alarm_log, unsigned long can_base_adr_terminal); + + + + +void InitCan(unsigned long can_base_adr_units, unsigned long can_base_adr_mpu, unsigned long can_base_adr_alarm_log, unsigned long can_base_adr_terminal); + + +//void CAN_send(int box, unsigned long hiword, unsigned long loword); +//void CAN_word_send(int type_box, int box, int Addr, int Data); +//void CAN_array_send(int type_box, int box, int Addr, int * Data); + +void CAN_cycle_send(int type_box, int box, unsigned long Addr, int * Data, unsigned long quant, int extended, int priority); + +//void FIFO_send(int box, unsigned long hiword, unsigned long loword); + +//int CAN_FLY_free(int box); +//int CAN_FIFO_free(unsigned int quant); + +int CAN_cycle_free(int box); +int CAN_cycle_full_free(int box, int statistics_flag); + +//void CAN_cycle_stop(int box); + + +//void CAN_cycle_step(int box); + + +void CAN_request(unsigned int addr, unsigned int quant); +void CAN_assign(unsigned int addr, unsigned int quant); + + +void reset_CAN_timeout_cicle(int box); +void inc_CAN_timeout_cicle(); + +unsigned int test_can_live_mpu(void); +unsigned int test_can_live_terminal(int n); +void InitCanSoft(void); + +void timer_pause_enable_can_from_mpu(void); +void timer_pause_enable_can_from_terminal(void); +void read_manch_can(void); +void write_manch_can(void); +void detect_time_refresh_units(int box, int adr); +void detect_time_refresh_mpu(int box, int adr); + + + +void parse_data_from_mbox(unsigned int box, unsigned long hiword, + unsigned long loword); + + +int get_real_out_mbox(int type_box, int box); +int get_real_in_mbox(int type_box, int box); + + + +void messagePaserToUnitesIngitim(int box, unsigned long h_word, unsigned long l_word); + + + + +////////////////// +void new_fifo_calc_load(void); +int new_fifo_load(int box,unsigned long hiword, unsigned long loword); + +int new_cycle_fifo_load(int box, unsigned long adr, int * adr_from, unsigned long addr_to, unsigned long quant, int extended, int priority, int cmd_wait); + +int get_new_cycle_fifo_load_level(void); + + +void CAN_send2(int box,unsigned long hiword, unsigned long loword); +int CAN_cycle_fifo_step(void); +int CAN_cycle_fifo_one_box(void); + +////////////////// +int CAN_may_be_send_cycle_fifo(void); + +void stop_can_interrupt(void); +void start_can_interrupt(void); + + +//// Prototype statements for functions found within this file. +interrupt void CAN_handler(void); +interrupt void CAN_reset_err(void); + + + +extern UNITES_CAN_SETUP unites_can_setup; +extern MPU_CAN_SETUP mpu_can_setup; + + +extern unsigned int CanTimeOutErrorTR; +extern unsigned int CanBusOffError; + +#endif // _CAN_SETUP + diff --git a/Inu/Src/N12_Libs/RS_modbus_pult.h b/Inu/Src/N12_Libs/RS_modbus_pult.h new file mode 100644 index 0000000..a1f7ce9 --- /dev/null +++ b/Inu/Src/N12_Libs/RS_modbus_pult.h @@ -0,0 +1,31 @@ +#ifndef _RS_MODBUS_PULT_H +#define _RS_MODBUS_PULT_H + +#include "modbus_struct.h" +#include "RS_Functions.h" + +void ModbusRTUsend1(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start, unsigned int count_bits); +void ModbusRTUreceiveAnswer1(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUreceive3(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUsend3(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start,unsigned int count_word); +void ModbusRTUreceiveAnswer3(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUsend4(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start, unsigned int count_word); +void ModbusRTUreceiveAnswer4(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUreceive4(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUsend5(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start); +void ModbusRTUreceiveAnswer5(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUsend6(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start); +void ModbusRTUreceiveAnswer6(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUsend15(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start,unsigned int count_bits); +void ModbusRTUreceiveAnswer15(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUreceive15(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUsend16(RS_DATA_STRUCT *rs_arr,int adr_contr, unsigned int adr_start,unsigned int count_words); +void ModbusRTUreceive16(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUreceiveAnswer16(RS_DATA_STRUCT *RS232_Arr); +void ModbusRTUsetDataArrays(MODBUS_REG_STRUCT *array_in, MODBUS_REG_STRUCT *array_out); +void ModbusRTUsetDiscretDataArray(MODBUS_REG_STRUCT *discrete_in, MODBUS_REG_STRUCT *discrete_out); + +extern int flag_wait_anwer_cmd1; + +#endif + diff --git a/Inu/Src/N12_Libs/RS_modbus_pultl.c b/Inu/Src/N12_Libs/RS_modbus_pultl.c new file mode 100644 index 0000000..0aa6313 --- /dev/null +++ b/Inu/Src/N12_Libs/RS_modbus_pultl.c @@ -0,0 +1,1013 @@ +#include + +#include "control_station.h" +#include "modbus_table_v2.h" +#include "options_table.h" +#include "RS_modbus_pult.h" +#include "DSP281x_Device.h" +#include "CRC_Functions.h" +#include "RS_Functions.h" +#include "RS_modbus_svu.h" + + + +//#pragma DATA_SECTION(p_analog_data_in, ".logs"); +MODBUS_REG_STRUCT *p_analog_data_in; + +//#pragma DATA_SECTION(p_analog_data_out, ".logs"); +MODBUS_REG_STRUCT *p_analog_data_out; + +//#pragma DATA_SECTION(p_discrete_data_out, ".logs"); +MODBUS_REG_STRUCT *p_discrete_data_out; + +//#pragma DATA_SECTION(p_discrete_data_in, ".logs"); +MODBUS_REG_STRUCT *p_discrete_data_in; + +static int adres_wait_answer_cmd1 = 0; +static int count_registers_wait_answer = 0; + +void ModbusRTUsetDataArrays(MODBUS_REG_STRUCT *array_in, MODBUS_REG_STRUCT *array_out) +{ + p_analog_data_in = array_in; + p_analog_data_out = array_out; +} + +void ModbusRTUsetDiscretDataArray(MODBUS_REG_STRUCT *discrete_in, MODBUS_REG_STRUCT *discrete_out) +{ + p_discrete_data_in = discrete_in; + p_discrete_data_out = discrete_out; +} +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/***************************************************************/ +/***************************************************************/ +/* ModBus - 1 + Digital Output Holding Registers */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUsend1(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start, unsigned int count_bits) +{ + // + unsigned int crc; + unsigned int count_data_bytes; + + count_data_bytes = (count_bits % 8) == 0 ? count_bits / 8 : count_bits / 8 + 1; + + rs_arr->buffer[0] = LOBYTE(adr_contr); + rs_arr->buffer[1] = CMD_RS232_MODBUS_1; + rs_arr->buffer[2] = HIBYTE(adr_start); + rs_arr->buffer[3] = LOBYTE(adr_start); + rs_arr->buffer[4] = HIBYTE(count_bits); + rs_arr->buffer[5] = LOBYTE(count_bits); + + crc = 0xffff; + crc = GetCRC16_IBM(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + + rs_arr->RS_DataWillSend = 1; + rs_arr->RS_DataWillSend2 = 1; + + RS_Send(rs_arr, rs_arr->buffer, 10); + + + /* */ + if (adr_contr > 0 && adr_contr < 0xff) + { + + RS_Len[CMD_RS232_MODBUS_1] = 5 + count_data_bytes; + count_registers_wait_answer = count_bits; + adres_wait_answer_cmd1 = adr_start; + RS_SetControllerLeading(rs_arr, true); + RS_SetAdrAnswerController(rs_arr, adr_contr); + } + + return; +} + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 1 + Digital Output Holding Registers */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUreceiveAnswer1(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned int first_word, end_byte_number, count_data_bytes, current_register, last_register; + unsigned int displacement_start, displacement, displacement_end, bits_in_last_byte, byte, mask = 0, mask_start, mask_end; + unsigned int i = 0, b = 0, buffer_position = 0, j = 0; +// unsigned char byte_buffer[SIZE_MODBUS_TABLE_DISCRET * 2]; + + /* . */ + first_word = (adres_wait_answer_cmd1 % 16 == 0) && (adres_wait_answer_cmd1 != 0) + ? adres_wait_answer_cmd1 / 16 + 1 + : adres_wait_answer_cmd1 / 16; + displacement_start = adres_wait_answer_cmd1 % 16; + displacement = adres_wait_answer_cmd1 % 16; + count_data_bytes = RS232_Arr->RS_Header[2]; + current_register = adres_wait_answer_cmd1; + last_register = adres_wait_answer_cmd1 + count_registers_wait_answer; + displacement_end = last_register % 16; + ///////////////////////////////////////////////// + + mask = 0; + mask_start = 0; + mask_end = 0; + for (i = 0; i < displacement_start; ++i) + { + mask_start |= 1 << i; + mask_end |= 1 << i; + } + mask_start = ~mask_start; + displacement = displacement_start; + for (i = 0; i < count_data_bytes; ++i) + { + byte = RS232_Arr->RS_Header[3 + i]; + mask = 0; + if ((last_register - current_register) > 8) { + mask = 0xFF; + } else { + for (j = 0; j < (last_register - current_register); ++j) { + mask |= 1 << j; + } + } + if (displacement < 8) + { + //mask = mask << displacement; + p_discrete_data_out[first_word].all &= ~(mask << displacement); + p_discrete_data_out[first_word].all |= (byte & mask) << displacement; + } else { + mask_start = (mask << displacement) & 0xFF00; + p_discrete_data_out[first_word].all &= ~mask_start; + p_discrete_data_out[first_word].all |= (byte & mask) << displacement; + mask_end = (mask >> (16 - displacement)) & 0xFF; + p_discrete_data_out[first_word].all &= ~mask_end; + p_discrete_data_out[first_word + 1].all |= (byte & mask) >> (16 - displacement); + } + + + displacement += 8; + if (displacement >= 16) { + displacement -= 16; + first_word += 1; + } + current_register += 8; + + } + + RS_SetControllerLeading(RS232_Arr, false); + RS_SetAdrAnswerController(RS232_Arr, 0); + return; +} +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 3 + Analog Input Registers */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUreceive3(RS_DATA_STRUCT *RS232_Arr) +{ + // y + unsigned int crc, Address_MB, Length_MB, i /*, Data*/; + // int buf_out[200]; + + /* y. */ + Address_MB = (RS232_Arr->RS_Header[2] << 8) | RS232_Arr->RS_Header[3]; + + /* */ + Length_MB = (RS232_Arr->RS_Header[4] << 8) | RS232_Arr->RS_Header[5]; + + ///////////////////////////////////////////////// + // + /* */ + + // f.RScount = SECOND*3; + + RS232_Arr->buffer[0] = RS232_Arr->addr_recive; //CNTRL_ADDR; + RS232_Arr->buffer[1] = CMD_RS232_MODBUS_3; + RS232_Arr->buffer[2] = Length_MB * 2; + + for (i = 0; i < Length_MB; i++) + { + if (Address_MB >= ADR_MODBUS_TABLE && Address_MB < 0xe00) + { +// RS232_Arr->buffer[3 + i * 2] = p_analog_data_out[Address_MB - ADR_MODBUS_TABLE + i].byte.HB; +// RS232_Arr->buffer[3 + i * 2 + 1] = p_analog_data_out[Address_MB - ADR_MODBUS_TABLE + i].byte.LB; + RS232_Arr->buffer[3 + i * 2] = p_analog_data_out[Address_MB + i].byte.HB; + RS232_Arr->buffer[3 + i * 2 + 1] = p_analog_data_out[Address_MB + i].byte.LB; + } + + if (Address_MB >= 0xe00 && Address_MB < 0xf00) + { + RS232_Arr->buffer[3 + i * 2] = options_controller[Address_MB - 0xe00 + i].byte.HB; + RS232_Arr->buffer[3 + i * 2 + 1] = options_controller[Address_MB - 0xe00 + i].byte.LB; + } + } + + crc = 0xffff; + crc = GetCRC16_IBM(crc, RS232_Arr->buffer, Length_MB * 2 + 3); + + RS232_Arr->buffer[Length_MB * 2 + 3] = LOBYTE(crc); + RS232_Arr->buffer[Length_MB * 2 + 4] = HIBYTE(crc); + + RS232_Arr->buffer[Length_MB * 2 + 5] = 0; + RS232_Arr->buffer[Length_MB * 2 + 6] = 0; +// RS232_Arr->RS_DataWillSend = 1; + RS_Send(RS232_Arr, RS232_Arr->buffer, Length_MB * 2 + 7); + + return; +} + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 3 + Analog Input Registers */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUsend3(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start, unsigned int count_word) +{ + // + unsigned int crc; //, Address_MB, Length_MB, i, Data; + // int buf_out[200]; + // int buf_in[200]; + + rs_arr->buffer[0] = LOBYTE(adr_contr); + rs_arr->buffer[1] = CMD_RS232_MODBUS_3; + rs_arr->buffer[2] = HIBYTE(adr_start); + rs_arr->buffer[3] = LOBYTE(adr_start); + rs_arr->buffer[4] = 0; + rs_arr->buffer[5] = LOBYTE(count_word); + + crc = 0xffff; + crc = GetCRC16_IBM(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + + rs_arr->RS_DataWillSend = 1; + rs_arr->RS_DataWillSend2 = 1; + + RS_Send(rs_arr, rs_arr->buffer, 10); + + /* */ + if (adr_contr > 0 && adr_contr < 0xff) + { + + RS_Len[CMD_RS232_MODBUS_3] = 5 + count_word * 2; + + adr_read_from_modbus3 = adr_start; + RS_SetControllerLeading(rs_arr, true); + RS_SetAdrAnswerController(rs_arr, adr_contr); + } + + return; +} + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 3 + Analog Input Registers */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUreceiveAnswer3(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned int Address_MB, Length_MB, i; + MODBUS_REG_STRUCT elementData; + + /* . */ + Address_MB = adr_read_from_modbus3; + + /* */ + Length_MB = RS232_Arr->RS_Header[2] >> 1; + + ///////////////////////////////////////////////// + // + /* */ + + for (i = 0; i < Length_MB; i++) + { + elementData.byte.HB = RS232_Arr->RS_Header[3 + i * 2]; + elementData.byte.LB = RS232_Arr->RS_Header[3 + i * 2 + 1]; +// p_analog_data_out[Address_MB - ADR_MODBUS_TABLE + i].all = elementData.all; + if ((Address_MB + i)buffer[0] = LOBYTE(adr_contr); + rs_arr->buffer[1] = CMD_RS232_MODBUS_4; + rs_arr->buffer[2] = HIBYTE(adr_start); + rs_arr->buffer[3] = LOBYTE(adr_start); + rs_arr->buffer[4] = 0; + rs_arr->buffer[5] = LOBYTE(count_word); + + crc = 0xffff; + crc = GetCRC16_IBM(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + + rs_arr->RS_DataWillSend = 1; + rs_arr->RS_DataWillSend2 = 1; + + RS_Send(rs_arr, rs_arr->buffer, 10); + + /* */ + if (adr_contr > 0 && adr_contr < 0xff) + { + + RS_Len[CMD_RS232_MODBUS_4] = 5 + count_word * 2; + + adr_read_from_modbus3 = adr_start; + RS_SetControllerLeading(rs_arr, true); + RS_SetAdrAnswerController(rs_arr, adr_contr); + } + + return; +} + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 4 + Analog Output Holding Registers */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUreceiveAnswer4(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned int Address_MB, Length_MB, i; + static unsigned int prev_Address_MB = 0; + + MODBUS_REG_STRUCT elementData; + + /* . */ + Address_MB = adr_read_from_modbus3; + + /* */ + Length_MB = RS232_Arr->RS_Header[2] >> 1; + + ///////////////////////////////////////////////// + // + /* */ + + for (i = 0; i < Length_MB; i++) + { + elementData.byte.HB = RS232_Arr->RS_Header[3 + i * 2]; + elementData.byte.LB = RS232_Arr->RS_Header[3 + i * 2 + 1]; +// p_analog_data_in[Address_MB - ADR_MODBUS_TABLE + i].all = elementData.all; + if ((Address_MB + i)RS_DataReadyFullUpdate = 1; + + prev_Address_MB = Address_MB; + + return; +} + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 4 + Analog Output Holding Registers */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUreceive4(RS_DATA_STRUCT *RS232_Arr) +{ + // y + unsigned int crc, Address_MB, Length_MB, i /*, Data*/; + // int buf_out[200]; + + /* y. */ + Address_MB = (RS232_Arr->RS_Header[2] << 8) | RS232_Arr->RS_Header[3]; + + /* */ + Length_MB = (RS232_Arr->RS_Header[4] << 8) | RS232_Arr->RS_Header[5]; + + ///////////////////////////////////////////////// + // + /* */ + + // f.RScount = SECOND*3; + + RS232_Arr->buffer[0] = RS232_Arr->addr_recive; //CNTRL_ADDR; + RS232_Arr->buffer[1] = CMD_RS232_MODBUS_4; + RS232_Arr->buffer[2] = Length_MB * 2; + + for (i = 0; i < Length_MB; i++) + { + if (Address_MB >= ADR_MODBUS_TABLE && Address_MB < 0xe00) + { +// RS232_Arr->buffer[3 + i * 2] = p_analog_data_out[Address_MB - ADR_MODBUS_TABLE + i].byte.HB; +// RS232_Arr->buffer[3 + i * 2 + 1] = p_analog_data_out[Address_MB - ADR_MODBUS_TABLE + i].byte.LB; + RS232_Arr->buffer[3 + i * 2] = p_analog_data_out[Address_MB + i].byte.HB; + RS232_Arr->buffer[3 + i * 2 + 1] = p_analog_data_out[Address_MB + i].byte.LB; + } + + if (Address_MB >= 0xe00 && Address_MB < 0xf00) + { + RS232_Arr->buffer[3 + i * 2] = options_controller[Address_MB - 0xe00 + i].byte.HB; + RS232_Arr->buffer[3 + i * 2 + 1] = options_controller[Address_MB - 0xe00 + i].byte.LB; + } + } + + crc = 0xffff; + crc = GetCRC16_IBM(crc, RS232_Arr->buffer, Length_MB * 2 + 3); + + RS232_Arr->buffer[Length_MB * 2 + 3] = LOBYTE(crc); + RS232_Arr->buffer[Length_MB * 2 + 4] = HIBYTE(crc); + + RS232_Arr->buffer[Length_MB * 2 + 5] = 0; + RS232_Arr->buffer[Length_MB * 2 + 6] = 0; +// RS232_Arr->RS_DataWillSend = 1; + RS_Send(RS232_Arr, RS232_Arr->buffer, Length_MB * 2 + 7); + + return; +} +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 5 + Analog Output Holding Registers */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUsend5(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start) +{ + // + unsigned int crc; + unsigned int byte_number; + unsigned int bit_number; + byte_number = adr_start / 16; + bit_number = adr_start % 16; + + + rs_arr->buffer[0] = LOBYTE(adr_contr); + rs_arr->buffer[1] = CMD_RS232_MODBUS_5; + rs_arr->buffer[2] = HIBYTE(adr_start); + rs_arr->buffer[3] = LOBYTE(adr_start); + if ((p_discrete_data_out[byte_number].all >> bit_number) & 1) { + rs_arr->buffer[4] = 0xFF; + rs_arr->buffer[5] = 0; + } else { + rs_arr->buffer[4] = 0; + rs_arr->buffer[5] = 0; + } + crc = 0xffff; + crc = GetCRC16_IBM(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + rs_arr->RS_DataWillSend = 1; + rs_arr->RS_DataWillSend2 = 1; + RS_Send(rs_arr, rs_arr->buffer, 10); + + /* */ + if (adr_contr > 0 && adr_contr < 0xff) + { + + RS_Len[CMD_RS232_MODBUS_5] = 8; + + adr_read_from_modbus3 = adr_start; + RS_SetControllerLeading(rs_arr, true); + RS_SetAdrAnswerController(rs_arr, adr_contr); + } + + return; +} + +/****************************************************************/ +/****************************************************************/ +/* ModBus - 5 + Digital Output Holding Registers */ +/****************************************************************/ +/****************************************************************/ +void ModbusRTUreceiveAnswer5(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned int Address_MB, Length_MB, i; + MODBUS_REG_STRUCT elementData; + + /* . */ + Address_MB = adr_read_from_modbus3; + + /* */ + Length_MB = RS232_Arr->RS_Header[2] >> 1; + + RS_SetControllerLeading(RS232_Arr, false); + RS_SetAdrAnswerController(RS232_Arr, 0); + + return; +} +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 6 + Analog Output Holding Registers */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUsend6(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start) +{ + // + unsigned int crc; //, Address_MB, Length_MB, i, Data; + // int buf_out[200]; + // int buf_in[200]; + + rs_arr->buffer[0] = LOBYTE(adr_contr); + rs_arr->buffer[1] = CMD_RS232_MODBUS_6; + rs_arr->buffer[2] = HIBYTE(adr_start); + rs_arr->buffer[3] = LOBYTE(adr_start); + rs_arr->buffer[4] = HIBYTE(p_analog_data_out[adr_start].all); + rs_arr->buffer[5] = LOBYTE(p_analog_data_out[adr_start].all); + + crc = 0xffff; + crc = GetCRC16_IBM(crc, rs_arr->buffer, 6); + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + + rs_arr->RS_DataWillSend = 1; + rs_arr->RS_DataWillSend2 = 1; + + RS_Send(rs_arr, rs_arr->buffer, 10); +// control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] = 1; + /* */ + if (adr_contr > 0 && adr_contr < 0xff) + { + + RS_Len[CMD_RS232_MODBUS_6] = 8; + + adr_read_from_modbus3 = adr_start; + RS_SetControllerLeading(rs_arr, true); + RS_SetAdrAnswerController(rs_arr, adr_contr); + } + + return; +} + +/****************************************************************/ +/****************************************************************/ +/* ModBus - 6 + Analog Output Holding Registers */ +/****************************************************************/ +/****************************************************************/ +void ModbusRTUreceiveAnswer6(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned int Address_MB, Length_MB, i; + MODBUS_REG_STRUCT elementData; + + /* . */ + Address_MB = adr_read_from_modbus3; + + /* */ + Length_MB = RS232_Arr->RS_Header[2] >> 1; + + RS_SetControllerLeading(RS232_Arr, false); + RS_SetAdrAnswerController(RS232_Arr, 0); + + return; +} +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 15 + Discrete Output Coils */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUsend15(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start, unsigned int count_bits) +{ + // + unsigned int crc; + unsigned int start_byte_number, end_byte_number, count_data_bytes; + unsigned int displacement_start, bits_in_last_byte, mask_start, mask_end; + unsigned int i = 0; + +// char byte_buffer[SIZE_MODBUS_TABLE_DISCRET * 2]; + + rs_arr->buffer[0] = LOBYTE(adr_contr); + rs_arr->buffer[1] = CMD_RS232_MODBUS_15; + rs_arr->buffer[2] = HIBYTE(adr_start); + rs_arr->buffer[3] = LOBYTE(adr_start); + rs_arr->buffer[4] = HIBYTE(count_bits); + rs_arr->buffer[5] = LOBYTE(count_bits); + + start_byte_number = adr_start / 8; + end_byte_number = (adr_start + (count_bits - 1)) / 8; + count_data_bytes = (count_bits % 8) == 0 ? count_bits / 8 + : count_bits / 8 + 1; + rs_arr->buffer[6] = count_data_bytes; + + displacement_start = adr_start % 8; + bits_in_last_byte = count_bits % 8; + if (bits_in_last_byte == 0) { bits_in_last_byte = 0xFF; } + + mask_start = 0; + for(i = 0; (i < (8 - displacement_start)) && (i < 8); i++) { + mask_start |= (1 << (7 - i)); + } + + mask_end = 0; + for(i = 0; (i < bits_in_last_byte) && (i < 8); i++) { + mask_end |= (1 << i); + } + + for (i = 0; i < count_data_bytes; i++) + { + if (i < count_data_bytes - 1) { + rs_arr->buffer[7 + i] = 0; + if (((i + start_byte_number) & 1) == 0) + { + rs_arr->buffer[7 + i] |= + (p_discrete_data_out[(i + start_byte_number) / 2].all >> displacement_start) & 0xFF; + } + if (((i + start_byte_number) & 1) == 1) + { + rs_arr->buffer[7 + i] |= + (((p_discrete_data_out[(i + start_byte_number) / 2].all >> 8) & mask_start) >> displacement_start); + rs_arr->buffer[7 + i] |= + (((p_discrete_data_out[(i + start_byte_number) / 2 + 1].all) & ~mask_start) << (8 - displacement_start)); + } + } else { + rs_arr->buffer[7 + i] = 0; + if (((i + start_byte_number) & 1) == 0) + { + rs_arr->buffer[7 + i] |= + ((p_discrete_data_out[(i + start_byte_number) / 2].all) >> displacement_start) & mask_end; + } + if (((i + start_byte_number) & 1) == 1) + { + rs_arr->buffer[7 + i] |= + (((p_discrete_data_out[(i + start_byte_number) / 2].all >> 8) & mask_start) >> displacement_start); + rs_arr->buffer[7 + i] |= + (((p_discrete_data_out[(i + start_byte_number) / 2 + 1].all) & ~mask_start) << (8 - displacement_start)) & mask_end; + } + } + } + + crc = 0xffff; + crc = GetCRC16_IBM(crc, rs_arr->buffer, count_data_bytes + 7); + rs_arr->buffer[count_data_bytes + 7] = LOBYTE(crc); + rs_arr->buffer[count_data_bytes + 8] = HIBYTE(crc); + + rs_arr->buffer[count_data_bytes + 9] = 0; + rs_arr->buffer[count_data_bytes + 10] = 0; + + rs_arr->RS_DataWillSend = 1; + rs_arr->RS_DataWillSend2 = 1; + +// RS_Send(rs_arr, rs_arr->buffer, (count_data_bytes + 10 + 2)); + RS_Send(rs_arr, rs_arr->buffer, (count_data_bytes + 10)); +// control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] = 1; + /* */ + if (adr_contr > 0 && adr_contr < 0xff) + { + RS_Len[CMD_RS232_MODBUS_15] = 8; + RS_SetControllerLeading(rs_arr, true); + RS_SetAdrAnswerController(rs_arr, adr_contr); + } + + return; +} + +/***************************************************************/ +/***************************************************************/ +/***************************************************************/ +/* ModBus - 15 + Discrete Output Coils */ +/***************************************************************/ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUreceiveAnswer15(RS_DATA_STRUCT *RS232_Arr) +{ + RS_SetAdrAnswerController(RS232_Arr, 0); + RS_SetControllerLeading(RS232_Arr, false); + +} + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 15 + Discrete Output Coils */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUreceive15(RS_DATA_STRUCT *RS232_Arr) +{ + // y + unsigned int crc, register_address, array_address, length, byte_count, quantity; + unsigned int d_word, mask_start, mask_end; + unsigned int i1, i2, i; + unsigned int word_number, displacement_start, displacement_end; + + /* y. */ + register_address = RS232_Arr->RS_Header[3] | (RS232_Arr->RS_Header[2] << 8); + array_address = register_address / 16; + /* quantity. */ + quantity = RS232_Arr->RS_Header[5] | ( RS232_Arr->RS_Header[4] << 8); + + /* */ + byte_count = RS232_Arr->RS_Header[6]; + + length = (byte_count & 0x1) ? (byte_count >> 1) + 1 : (byte_count >> 1); + + word_number = register_address / 16; + displacement_end = register_address % 16; + displacement_start = 16 - displacement_end; + mask_start = 0; + for(i = 0; (i < displacement_end) && (i < 15); i++) { + mask_start |= (1 << i); + } + mask_end = 0; + for(i = 0; (i < displacement_start) && (i < 15); i++) { + mask_end |= (1 << (15 - i)); + } + for (i = 0; i < length; i++) + { +// if (register_address >= ADR_MODBUS_TABLE && Address_MB < 0xe00) + if (register_address < 0xe00) + { + d_word = (RS232_Arr->buffer[7 + i * 2] << 8) | RS232_Arr->RS_Header[7 + i * 2 + 1]; + p_discrete_data_out[array_address + i].all &= mask_start; + p_discrete_data_out[array_address + i].all |= (d_word >> displacement_start) | mask_start; + if(i < length - 1) { + p_discrete_data_out[array_address + i].all &= mask_end; + p_discrete_data_out[array_address + i].all |= (d_word << displacement_end) | mask_end; + } + } + } + + ///////////////////////////////////////////////// + // + // + + RS232_Arr->buffer[0] = RS232_Arr->addr_recive; + RS232_Arr->buffer[1] = CMD_RS232_MODBUS_15; + RS232_Arr->buffer[2] = HIBYTE(register_address); + RS232_Arr->buffer[3] = LOBYTE(register_address); + RS232_Arr->buffer[4] = HIBYTE(quantity); + RS232_Arr->buffer[5] = LOBYTE(quantity); + + crc = 0xffff; + crc = GetCRC16_IBM(crc, RS232_Arr->buffer, 6); + + RS232_Arr->buffer[6] = LOBYTE(crc); + RS232_Arr->buffer[7] = HIBYTE(crc); + + RS232_Arr->buffer[8] = 0; + RS232_Arr->buffer[9] = 0; +// RS232_Arr->RS_DataWillSend = 1; + RS_Send(RS232_Arr, RS232_Arr->buffer, 10); + + return; +} +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +/***************************************************************/ +/***************************************************************/ +/***************************************************************/ +/* ModBus - 16 + */ +/***************************************************************/ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUsend16(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start, unsigned int count_word) +{ + + // + unsigned int crc, Address_MB, i; //, Length_MB; //, Bytecnt_MB, Data1,Data2; + // int Data, digital, ust_I, ust_Time; + + //Length_MB = count_word; + Address_MB = adr_start; + // + // + + rs_arr->buffer[0] = adr_contr; + rs_arr->buffer[1] = CMD_RS232_MODBUS_16; + + rs_arr->buffer[2] = HIBYTE(adr_start); + rs_arr->buffer[3] = LOBYTE(adr_start); + + rs_arr->buffer[4] = HIBYTE(count_word); + rs_arr->buffer[5] = LOBYTE(count_word); + + rs_arr->buffer[6] = LOBYTE(count_word * 2); + + for (i = 0; i < count_word; i++) + { +// rs_arr->buffer[7 + i * 2] = p_analog_data_out[Address_MB - ADR_MODBUS_TABLE + i].byte.HB; +// rs_arr->buffer[7 + i * 2 + 1] = p_analog_data_out[Address_MB - ADR_MODBUS_TABLE + i].byte.LB; + rs_arr->buffer[7 + i * 2] = p_analog_data_out[Address_MB + i].byte.HB; + rs_arr->buffer[7 + i * 2 + 1] = p_analog_data_out[Address_MB + i].byte.LB; + } + + crc = 0xffff; + // crc = get_crc_ccitt(crc, rs_arr->buffer, Length_MB*2+7); + crc = GetCRC16_IBM(crc, rs_arr->buffer, (unsigned long)(count_word * 2 + 7)); + + rs_arr->buffer[count_word * 2 + 7] = LOBYTE(crc); + rs_arr->buffer[count_word * 2 + 8] = HIBYTE(crc); + + rs_arr->buffer[count_word * 2 + 9] = 0; + rs_arr->buffer[count_word * 2 + 10] = 0; + + rs_arr->RS_DataWillSend = 1; + rs_arr->RS_DataWillSend2 = 1; + + RS_Send(rs_arr, rs_arr->buffer, (count_word * 2 + 10)); +// control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] = 1; + + // + if (adr_contr > 0 && adr_contr < 0xff) + { + //rs_arr->RS_Length = -1; + RS_Len[CMD_RS232_MODBUS_16] = 8; + RS_SetControllerLeading(rs_arr, true); + RS_SetAdrAnswerController(rs_arr, adr_contr); + } +} + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 16 + */ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUreceive16(RS_DATA_STRUCT *RS232_Arr) +{ + // y + unsigned int crc, Address_MB, Length_MB, Bytecnt_MB, i /*, Data1,Data2,Quantity*/; + int /*Data,*/ i1, i2; + + /* y. */ + Address_MB = RS232_Arr->RS_Header[3] | (RS232_Arr->RS_Header[2] << 8); + + /* quantity. */ + //Quantity = RS232_Arr->RS_Header[5] | ( RS232_Arr->RS_Header[4] << 8); + + /* */ + // Length_MB = (RS232_Arr->RS_Header[4] << 8 ) | RS232_Arr->RS_Header[5]; + + Bytecnt_MB = RS232_Arr->RS_Header[6]; + + Length_MB = Bytecnt_MB >> 1; + + for (i = 0; i < Length_MB; i++) + { + if (Address_MB >= ADR_MODBUS_TABLE && Address_MB < 0xe00) + { +// p_analog_data_out[Address_MB - ADR_MODBUS_TABLE + i].byte.HB = RS232_Arr->buffer[3 + i * 2]; +// p_analog_data_out[Address_MB - ADR_MODBUS_TABLE + i].byte.LB = RS232_Arr->buffer[3 + i * 2 + 1]; + p_analog_data_out[Address_MB + i].byte.HB = RS232_Arr->buffer[3 + i * 2]; + p_analog_data_out[Address_MB + i].byte.LB = RS232_Arr->buffer[3 + i * 2 + 1]; + } + + if (Address_MB >= 0xe00 && Address_MB < 0xf00) + { + options_controller[Address_MB - 0xe00 + i].byte.HB = RS232_Arr->RS_Header[7 + i * 2]; + options_controller[Address_MB - 0xe00 + i].byte.LB = RS232_Arr->RS_Header[7 + i * 2 + 1]; + } + } + + if (Address_MB >= 0xe00 && Address_MB < 0xf00) + { + i1 = options_controller[0].all; + i2 = options_controller[1].all; + store_data_flash(options_controller, sizeof(options_controller)); + SetCntrlAddr(i1, i2); /* */ + } + + ///////////////////////////////////////////////// + // + // + + RS232_Arr->buffer[0] = RS232_Arr->addr_recive; + RS232_Arr->buffer[1] = CMD_RS232_MODBUS_16; + RS232_Arr->buffer[2] = HIBYTE(Address_MB); + RS232_Arr->buffer[3] = LOBYTE(Address_MB); + RS232_Arr->buffer[4] = 0; + RS232_Arr->buffer[5] = 2; + + crc = 0xffff; + crc = GetCRC16_IBM(crc, RS232_Arr->buffer, 6); + + RS232_Arr->buffer[6] = LOBYTE(crc); + RS232_Arr->buffer[7] = HIBYTE(crc); + + RS232_Arr->buffer[8] = 0; + RS232_Arr->buffer[9] = 0; +// RS232_Arr->RS_DataWillSend = 1; + RS_Send(RS232_Arr, RS232_Arr->buffer, 10); + + return; +} + +/***************************************************************/ +/***************************************************************/ +/***************************************************************/ +/* ModBus - 16 + */ +/***************************************************************/ +/***************************************************************/ +/***************************************************************/ +void ModbusRTUreceiveAnswer16(RS_DATA_STRUCT *RS232_Arr) +{ + // + unsigned int Address_MB; //, crc, Length_MB, Bytecnt_MB/*, i, Data1,Data2*/; + //int Data, digital, ust_I, ust_Time; + + /* . */ +// Address_MB = RS232_Arr->RS_Header[3] | ( RS232_Arr->RS_Header[2] << 8); +// if (Address_MB == ADRES_LOG_REGISTERS) { +// } + err_send_log_16 = 0; + + /* */ + //Length_MB = (RS232_Arr->RS_Header[4] << 8 ) | RS232_Arr->RS_Header[5]; + + //Bytecnt_MB = RS232_Arr->RS_Header[6]; + + RS_SetAdrAnswerController(RS232_Arr, 0); + RS_SetControllerLeading(RS232_Arr, false); + + err_modbus16 = 0; + return; +} +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/Inu/Src/N12_Libs/alarm_log_can.c b/Inu/Src/N12_Libs/alarm_log_can.c new file mode 100644 index 0000000..551b992 --- /dev/null +++ b/Inu/Src/N12_Libs/alarm_log_can.c @@ -0,0 +1,543 @@ +/* + * oscil_can.c + * + * Created on: 24 2020 . + * Author: yura + */ + +#include "alarm_log_can.h" + +#include "CAN_Setup.h" +#include "global_time.h" +#include "CRC_Functions.h" + + +#pragma DATA_SECTION(alarm_log_can, ".slow_vars") +ALARM_LOG_CAN alarm_log_can = ALARM_LOG_CAN_CAN_DEFAULTS; + + + +//int oscil_buffer[OSCIL_CAN_NUMBER_CHANNEL][OSCIL_CAN_NUMBER_POINTS]; + + + +void alarm_log_clear_buffer(ALARM_LOG_CAN_handle al) +{ + unsigned int i,k; +/* + for (i=0;ioscil_buffer[i][k] = 0; + + for (i=0;itemp_oscil_buffer[i][k] = 0; + + + oc->current_position = 0; + // oc->enable_rewrite = 1; +*/ +} + +int compress_size = 0; +void alarm_log_compress_temp_buffer(ALARM_LOG_CAN_handle al) +{ + + +// compress_size = fastlz_compress_level(1, al->start_adr_real_logs, 100, al->start_adr_temp); +// compress_size = lzf_compress(al->start_adr_real_logs, 2000, al->start_adr_temp, 2000); + + +} + + +void alarm_log_copy_temp_buffer(ALARM_LOG_CAN_handle al) +{ + unsigned int i,k; + unsigned long clog, temp_length;//real_length + int *adr_finish_temp, *adr_current; + + +// real_length = al->real_points * al->oscills; + // real_adr = al->start_adr_real_logs; + + temp_length = al->temp_points * al->oscills; // + al->temp_log_ready = 0; + + + if (al->current_adr_real_log == al->start_adr_real_logs) // , ? + return; + + adr_current = al->current_adr_real_log; // + adr_finish_temp = al->start_adr_temp + temp_length; // temp + // adr_finish temp_log + // , + for (clog=0; clog= al->start_adr_real_logs) ) + { + *adr_finish_temp = *adr_current; // + // + adr_current--; + } + else + *adr_finish_temp = 0; // ! + + // + adr_finish_temp--; + + // ? + if (adr_current < al->start_adr_real_logs) + { + if (al->finish_adr_real_log) // ? + adr_current = al->finish_adr_real_log; // . + else + adr_current = al->start_adr_real_logs - 1; + } + } + + al->temp_log_ready = 1; + +/* + for (i=0;ioscil_buffer[i][k] = 0; + + for (i=0;itemp_oscil_buffer[i][k] = 0; + + + oc->current_position = 0; + // oc->enable_rewrite = 1; +*/ + +} + + + +//#define CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCKS 3330L// 9999L + +void alarm_log_send_buffer(ALARM_LOG_CAN_handle al) +{ + static unsigned int old_time = 0; + // static int prev_send_to_can = 0; + static unsigned long old_t = 0; + unsigned int i; + int real_mbox; + static int flag_send_buf = 0; + static unsigned long quant_local = 0; + static unsigned long addr_to = 0; + static int *start_adr; + static unsigned int k = 0; + + +// if (flag_send_buf) +// { +// +// +// +// return; +// } + + + if (al->global_enable==0) + return; + + real_mbox = get_real_out_mbox(ALARM_LOG_TYPE_BOX, ALARM_LOG_NUMBER_BOX_IN_CAN); + + if (al->stage==1) + { + + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_ON)) + { + CAN_cycle_send( + ALARM_LOG_TYPE_BOX, + ALARM_LOG_NUMBER_BOX_IN_CAN, + (unsigned long)(0xfffc*3L), + &(al->cmd_fffc[0]), 3, CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); + + CAN_cycle_send( + ALARM_LOG_TYPE_BOX, + ALARM_LOG_NUMBER_BOX_IN_CAN, + (unsigned long)(0xfffd*3L), + &(al->cmd_fffd[0]), 3, CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); + + CAN_cycle_send( + ALARM_LOG_TYPE_BOX, + ALARM_LOG_NUMBER_BOX_IN_CAN, + (unsigned long)(0xfffe*3L), + &(al->cmd_fffe[0]), 3, CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); + + al->stage = 2; + + quant_local = ((unsigned long)al->oscills * (unsigned long)al->temp_points); + al->progress_can = quant_local; + addr_to = 0; + start_adr = al->start_adr_temp; + + + } + + + return; + } + + + if (al->stage==2) + { + + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_OFF) && (get_new_cycle_fifo_load_level()<=2) ) + { +// if ((unsigned long)quant_local>(unsigned long)CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCKS) +// { +// k++; +// } + + al->progress_can = quant_local; + if ((unsigned long)quant_local > al->can_max_size_one_block) + { + + al->crc16 = GetCRC16_IBM( al->crc16, (unsigned int *)start_adr, al->can_max_size_one_block); + + CAN_cycle_send( + ALARM_LOG_TYPE_BOX, + ALARM_LOG_NUMBER_BOX_IN_CAN, + addr_to, + start_adr, al->can_max_size_one_block , CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); + + start_adr += al->can_max_size_one_block; + quant_local -= al->can_max_size_one_block; + addr_to += al->can_max_size_one_block; + + } + else + { + al->crc16 = GetCRC16_IBM_v2( al->crc16, (unsigned int *)start_adr, ((unsigned long)quant_local) ); + + CAN_cycle_send( + ALARM_LOG_TYPE_BOX, + ALARM_LOG_NUMBER_BOX_IN_CAN, + addr_to, + start_adr, ((unsigned long)quant_local) , CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); + al->stage = 3; + quant_local = 0; + } + + } + + + return; + } + + + if (al->stage==3) + { + al->cmd_ffff[1] = al->crc16; // CRC16 + + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_OFF)) + { + al->progress_can = 0; + + CAN_cycle_send( + ALARM_LOG_TYPE_BOX, + ALARM_LOG_NUMBER_BOX_IN_CAN, + (unsigned long)(0xffff*3L), + &(al->cmd_ffff[0]), 3 , CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); + al->stage = 100; + k--; + } + + + return; + } + + + if (al->stage==4) + { + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_OFF)) + { + CAN_cycle_send( + ALARM_LOG_TYPE_BOX, + ALARM_LOG_NUMBER_BOX_IN_CAN, + (unsigned long)(0xfffc*3L), + &(al->cmd_fffc[0]), 3, CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); + al->stage = 100; + k--; + } + + + return; + } + + + if (al->stage==100) + { + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_ON)) + { + // prev_send_to_can = 1; + al->stage = 0; + al->timer_send = (global_time.miliseconds - old_t); + } + + return; + } + +// , , +// .. OSCIL_TIME_WAIT . + +// if (prev_send_to_can && CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_OFF)==0) +// { +// old_time = (unsigned int)global_time.miliseconds; +// return; +// } +////// +// if (prev_send_to_can) +// { +// +// } +////// +// prev_send_to_can = 0; + + + if ((al->prev_status_alarm != al->status_alarm) && al->status_alarm) + { + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_ON)) + { + + al->prepare_data_can(al); + + if (al->copy2temp) + { + al->copy_temp_buffer(al); +// alarm_log_compress_temp_buffer(al); + if (al->temp_log_ready == 1) + { + old_t = global_time.miliseconds; + al->stage = 1; + } + else + { + old_t = global_time.miliseconds; + al->stage = 4; // - , ! + + } + + } + else + { + old_t = global_time.miliseconds; + al->stage = 4; // - , ! + + } + + +// flag_send_buf = 1; + + +// CAN_cycle_send( +// ALARM_LOG_TYPE_BOX, +// ALARM_LOG_NUMBER_BOX_IN_CAN, +// 0xfffc, +// &(al->cmd_fffc[0]), 3, CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); +// +// CAN_cycle_send( +// ALARM_LOG_TYPE_BOX, +// ALARM_LOG_NUMBER_BOX_IN_CAN, +// 0xfffd, +// &(al->cmd_fffd[0]), 3, CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); +// +// CAN_cycle_send( +// ALARM_LOG_TYPE_BOX, +// ALARM_LOG_NUMBER_BOX_IN_CAN, +// 0xfffe, +// &(al->cmd_fffe[0]), 3, CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); +// al->stage = 1; +// +// CAN_cycle_send( +// ALARM_LOG_TYPE_BOX, +// ALARM_LOG_NUMBER_BOX_IN_CAN, +// 0, +// al->start_adr, ((unsigned long)al->oscills * (unsigned long)al->points) , CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); +// al->stage = 2; +// +// CAN_cycle_send( +// ALARM_LOG_TYPE_BOX, +// ALARM_LOG_NUMBER_BOX_IN_CAN, +// 0xffff, +// &(al->cmd_ffff[0]), 3 , CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); +// al->stage = 0; +// +// +// prev_send_to_can = 1; + + } + } + al->prev_status_alarm = al->status_alarm; + + + +/* + + oc->global_enable = TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x1; + oc->send_after_cmd = (TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x2) >> 1; + oc->cmd_send = (TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x4) >> 2; + oc->stop_update_on_error = (TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x8) >> 3; + oc->stop_update_on_stop_pwm = (TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x10) >> 4; + + TerminalUnites[oc->number_can_box_terminal_oscil][0] &= ~0x4; // clear cmd_send + + oc->number_ch = TerminalUnites[oc->number_can_box_terminal_oscil][1]; + oc->number_points = TerminalUnites[oc->number_can_box_terminal_oscil][2]; + oc->step = TerminalUnites[oc->number_can_box_terminal_oscil][3]; + + + if (oc->global_enable==0) + return; + + real_mbox = get_real_out_mbox(TERMINAL_TYPE_BOX, oc->number_can_box_terminal_oscil); + + // , , + // .. OSCIL_TIME_WAIT . + if (prev_send_to_can && CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_OFF)==0) + { + old_time = (unsigned int)global_time.miliseconds; + return; + } + prev_send_to_can = 0; + + if (oc->send_after_cmd==0) + { + if (!detect_pause_milisec(OSCIL_TIME_WAIT,&old_time)) + return; + } + + + if ( (oc->send_after_cmd==0 || (oc->send_after_cmd==1 && oc->cmd_send==1 ) ) ) + { + + oc->cmd_send = 0; // clear cmd + + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_ON)) + { + + // oc->enable_rewrite = 0; + + + old_t = oc->current_position;// +// old_t = global_time.microseconds; + + oc->prepare_data_can(oc); + +// oc->timer_send = (global_time.microseconds - old_t); + oc->timer_send = (oc->current_position - old_t); + + flag_send_buf = 1; + + CAN_cycle_send( + TERMINAL_TYPE_BOX, + oc->number_can_box_terminal_oscil, + 0, + &(oc->temp_oscil_buffer[0][0]), (oc->number_ch * oc->number_points) , CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); + + prev_send_to_can = 1; + // while (CAN_cycle_free(real_mbox)==0); + +// oc->timer_send = (global_time.microseconds - old_t)/100; + + + oc->enable_rewrite = 1; + + +// if (cur_position_buf_modbus16_can >= SIZE_MODBUS_TABLE) +// { +// cur_position_buf_modbus16_can = 0; +//// modbus_table_can_out[ADR_CAN_TEST_PLUS_ONE].all++; +// } +// +// if ((cur_position_buf_modbus16_can + SIZE_BUF_WRITE_TO_MODBUS16_CAN) >= SIZE_MODBUS_TABLE) +// count_write_to_modbus_can = SIZE_MODBUS_TABLE - cur_position_buf_modbus16_can; +// else +// count_write_to_modbus_can = SIZE_BUF_WRITE_TO_MODBUS16_CAN; +// +// if (CAN_cycle_free(real_mbox)) +// { +// CAN_cycle_send( +// MPU_TYPE_BOX, +// edrk.flag_second_PCH, +// cur_position_buf_modbus16_can + 1, +// &modbus_table_can_out[cur_position_buf_modbus16_can].all, +// count_write_to_modbus_can, 0); +// +// cur_position_buf_modbus16_can = cur_position_buf_modbus16_can + SIZE_BUF_WRITE_TO_MODBUS16_CAN; +// } +// +// + + + + + + } + } +*/ + +} + + + +#pragma CODE_SECTION(alarm_log_prepare_data_can,".fast_run"); +void alarm_log_prepare_data_can(ALARM_LOG_CAN_handle al) +{ + unsigned int old_position, t_position; + int i, k; +// unsigned int crc; + + al->crc16 = 0xffff; +// crc = GetCRC16_IBM( crc, (unsigned int *)al->start_adr_temp, al->temp_points*al->oscills); + +// al->crc16 = crc; + + al->cmd_fffc[0] = 0x1234; + al->cmd_fffc[1] = 0x5678; + al->cmd_fffc[2] = 0x9abc; + + al->cmd_fffd[0] = al->post_points; + al->cmd_fffd[1] = al->step; + al->cmd_fffd[2] = 0x7777; + + al->cmd_fffe[0] = al->start; // START + al->cmd_fffe[1] = al->oscills; + al->cmd_fffe[2] = al->temp_points; + + al->cmd_ffff[0] = al->stop; // STOP + al->cmd_ffff[1] = al->crc16; // CRC16 + al->cmd_ffff[2] = 0x3333; + + + + /* + old_position = oc->current_position; + + for (i=0;i=0;k--) + { + if (t_position==0) + { + t_position = (OSCIL_CAN_NUMBER_POINTS+OSCIL_CAN_NUMBER_POINTS_ADD)-1; + } + else + t_position = t_position - 1; + + oc->temp_oscil_buffer[i][k] = oc->oscil_buffer[i][t_position]; + + } + + } +*/ + + return; +} + diff --git a/Inu/Src/N12_Libs/alarm_log_can.h b/Inu/Src/N12_Libs/alarm_log_can.h new file mode 100644 index 0000000..59ff998 --- /dev/null +++ b/Inu/Src/N12_Libs/alarm_log_can.h @@ -0,0 +1,135 @@ +/* + * oscil_can.h + * + * Created on: 24 2020 . + * Author: yura + */ + +#ifndef SRC_LIBS_NIO12_ALARM_LOG_CAN_H_ +#define SRC_LIBS_NIO12_ALARM_LOG_CAN_H_ + +#define CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCKS 195L //3330L // 9999L + + +#define ALARM_LOG_NUMBER_BOX_IN_CAN 0 + +#define ALARM_LOG_CODE_STATUS_LOG_STOP 1 // +#define ALARM_LOG_CODE_STATUS_LOG_RUN 2 // ... +#define ALARM_LOG_CODE_STATUS_LOG_RUN_TO_STOP 3 // , , . + + +/* +#define OSCIL_CAN_NUMBER_CHANNEL 32 // - +#define OSCIL_CAN_NUMBER_POINTS 500 // - ( ) +#define OSCIL_TIME_WAIT 5000 // CAN () +#define OSCIL_CAN_NUMBER_POINTS_ADD 100 // . oscil_buffer->temp_oscil_buffer + +#define OSCIL_CAN_NUMBER_POINTS_AFTER_STOP 100 // +*/ + + +typedef struct { + unsigned int global_enable; // + unsigned int copy2temp; // temp + unsigned int stage; + + int cmd_fffc[3]; + int cmd_fffd[3]; + int cmd_fffe[3]; + int cmd_ffff[3]; + + unsigned int post_points; // - + unsigned int step; // , + unsigned int start; // START + unsigned int oscills; // - - + + unsigned long real_points; // - , = points*oscills + // , . + + unsigned int stop; // START + unsigned int crc16; // crc16 + + int *start_adr_real_logs; // , + // + + int *start_adr_temp; // , + // , . + + int *finish_adr_real_log; // , + // + + int *current_adr_real_log; // + + // int *finish_adr_temp; // temp + unsigned long temp_points; // - , = temp_points*oscills + // . + + unsigned long progress_can; // , + unsigned int prev_status_alarm; // . status_alarm + unsigned int status_alarm; // , 0->1 + + unsigned int timer_send; // + + unsigned int temp_log_ready; // temp CAN + + unsigned long can_max_size_one_block; // , 3. + + void (*clear)(); // Clear buffers + void (*send)(); // Send buffers + void (*copy_temp_buffer)(); // Copy work buffers to temp buffers + void (*prepare_data_can)(); // + +} ALARM_LOG_CAN; + +typedef ALARM_LOG_CAN *ALARM_LOG_CAN_handle; + + + +#define ALARM_LOG_CAN_CAN_DEFAULTS { \ + 0, \ + 0, \ + 0, \ + {0,0,0}, \ + {0,0,0}, \ + {0,0,0}, \ + {0,0,0}, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + CAN_BOX_PRIORITY_LOW_MAX_SIZE_BLOCKS, \ + alarm_log_clear_buffer, \ + alarm_log_send_buffer, \ + alarm_log_copy_temp_buffer, \ + alarm_log_prepare_data_can \ +} + + + + +void alarm_log_clear_buffer(ALARM_LOG_CAN_handle); +void alarm_log_send_buffer(ALARM_LOG_CAN_handle); +//void alarm_log_next_position(ALARM_LOG_CAN_handle); +void alarm_log_prepare_data_can(ALARM_LOG_CAN_handle); +void alarm_log_copy_temp_buffer(ALARM_LOG_CAN_handle); + + + +extern ALARM_LOG_CAN alarm_log_can; + +#endif /* SRC_LIBS_NIO12_ALARM_LOG_CAN_H_ */ + + diff --git a/Inu/Src/N12_Libs/big_dsp_module.c b/Inu/Src/N12_Libs/big_dsp_module.c new file mode 100644 index 0000000..8688f17 --- /dev/null +++ b/Inu/Src/N12_Libs/big_dsp_module.c @@ -0,0 +1,26 @@ +//#define XLOW_FREQUENCY_MODE + + +#include "big_dsp_module.h" + +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "DSP281x_Examples.h" // DSP281x Examples Include File + + + +void setup_adr_pcb_controller() + +{ + EALLOW; + GpioMuxRegs.GPBMUX.bit.TDIRB_GPIOB11=0; + GpioMuxRegs.GPBDIR.bit.GPIOB11=0; + EDIS; +} + + +int get_adr_pcb_controller() +{ + return !GpioDataRegs.GPBDAT.bit.GPIOB11; +} + + diff --git a/Inu/Src/N12_Libs/big_dsp_module.h b/Inu/Src/N12_Libs/big_dsp_module.h new file mode 100644 index 0000000..f7d068f --- /dev/null +++ b/Inu/Src/N12_Libs/big_dsp_module.h @@ -0,0 +1,19 @@ +#ifndef _BIGDSPMODULE +#define _BIGDSPMODULE + + + +#ifdef __cplusplus + extern "C" { +#endif + + +void setup_adr_pcb_controller(); +int get_adr_pcb_controller(); + + +#ifdef __cplusplus + } +#endif + +#endif /* _BIGDSPMODULE */ diff --git a/Inu/Src/N12_Libs/build_version.c b/Inu/Src/N12_Libs/build_version.c new file mode 100644 index 0000000..147f0c1 --- /dev/null +++ b/Inu/Src/N12_Libs/build_version.c @@ -0,0 +1,24 @@ +/* + * build_version.c + * + * Created on: 17 . 2022 . + * Author: yura + */ + + +#include "build_version.h" + + + +float build_data_f = BUILD_DATA; +float build_time_f = BUILD_TIME; + +int build_data_i = (BUILD_DATA*1000); +int build_time_i = (BUILD_TIME*1000); + +int build_year = BUILD_YEAR; +int build_month = BUILD_MONTH; +int build_day = BUILD_DAY; + + + diff --git a/Inu/Src/N12_Libs/build_version.h b/Inu/Src/N12_Libs/build_version.h new file mode 100644 index 0000000..1100fb0 --- /dev/null +++ b/Inu/Src/N12_Libs/build_version.h @@ -0,0 +1,30 @@ +/* + * build_version.h + * + * Created on: 17 . 2022 . + * Author: yura + */ + +#ifndef SRC_N12_LIBS_BUILD_VERSION_H_ +#define SRC_N12_LIBS_BUILD_VERSION_H_ + + +#ifndef BUILD_DATA +#define BUILD_DATA 22.00 +#endif + +#ifndef BUILD_TIME +#define BUILD_TIME 00.01 +#endif + +extern float build_data_f; +extern float build_time_f; +extern int build_data_i; +extern int build_time_i; + + +extern int build_year, build_month, build_day; + + + +#endif /* SRC_N12_LIBS_BUILD_VERSION_H_ */ diff --git a/Inu/Src/N12_Libs/control_station.c b/Inu/Src/N12_Libs/control_station.c new file mode 100644 index 0000000..58b9cf8 --- /dev/null +++ b/Inu/Src/N12_Libs/control_station.c @@ -0,0 +1,194 @@ +/* + * control_station.c + * + * Created on: 1 . 2020 . + * Author: Yura + */ + + +#include "control_station.h" + +#include "global_time.h" + + +#pragma DATA_SECTION(control_station, ".slow_vars") +CONTROL_STATION control_station = CONTROL_STATION_DEFAULTS; +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + +void control_station_clear(CONTROL_STATION_handle cs) +{ + int i,k,j; + + for (i=0;icount_error_modbus[i] = 0; + cs->count_ok_modbus[i] = 0; + + + + cs->flag_waiting_answer[i] = 0; + cs->flag_message_sent[i] = 0; + cs->active_control_station[i] = 0; + cs->alive_control_station[i] = 0; + + for (k=0;karray_cmd[i][k] = 0; + + cs->detect_get_data_control_station[i] = 0; + cs->period_detect_active[i] = 0; + + cs->setup_time_detect_active[i] = CONTROL_STATION_SETUP_TIME_DETECT_ACTIVE; + cs->setup_time_detect_active_resend_485[i] = CONTROL_STATION_SETUP_TIME_DETECT_ACTIVE_RESEND_485; + cs->setup_time_send_cmd_after_off[i] = CONTROL_STATION_SETUP_TIME_SEND_CMD_AFTER_OFF; + + cs->time_detect_active[i] = 0; + cs->time_detect_answer_485[i] = 0; + + for (k=0;kraw_array_data[i][k].all = 0; + for (j=0;jraw_array_data_temp[i][k][j].all = 0; + } + + cs->flag_refresh_array[i] = 0; + + cs->prev_CAN_count_cycle_input_units[i] = 0; + cs->count_raw_array_data_temp[i] = 0; + + } + + for (k=0;kactive_array_cmd[k] = 0; +} + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + + +void control_station_update_timers(CONTROL_STATION_handle cs) +{ + static unsigned int old_time = 0; + volatile int i; + + + if (!detect_pause_milisec(CONTROL_STATION_TIME_WAIT,&old_time)) + return; + + + for (i=0;iflag_message_sent[i] == 1) + (cs->time_detect_answer_485[i])++; + +// cs->time_detect_answer_485[i] = 0; + + + + + if (cs->detect_get_data_control_station[i]) + { + cs->period_detect_active[i] = cs->time_detect_active[i]; + cs->time_detect_active[i] = 0; + cs->detect_get_data_control_station[i] = 0; + cs->alive_control_station[i] = 1; + } + else + { + + if (cs->time_detect_active[i]>=cs->setup_time_detect_active[i]) + { + cs->alive_control_station[i] = 0; // + cs->period_detect_active[i] = 0; +// cs->flag_message_sent[i] = 0; + cs->time_detect_active[i] = cs->setup_time_detect_active[i]+1; + } + else + { + cs->time_detect_active[i]++; + +// if (cs->flag_message_sent[i]) +// { +// if (cs->flag_waiting_answer[i]) +// cs->time_detect_active[i]++; +// else +// { +// cs->time_detect_active[i] = 0; +// } +// } +// else +// cs->time_detect_active[i]++; + } + + } + + + } + + + +} + + + + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + +void control_station_detect_active_station(CONTROL_STATION_handle cs) +{ + + + + + + +} + + + + + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + + + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + + + + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + + + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + + + + + + + + + diff --git a/Inu/Src/N12_Libs/control_station.h b/Inu/Src/N12_Libs/control_station.h new file mode 100644 index 0000000..a40ee94 --- /dev/null +++ b/Inu/Src/N12_Libs/control_station.h @@ -0,0 +1,134 @@ +/* + * control_station.h + * + * Created on: 1 . 2020 . + * Author: Vladislav + */ + +#ifndef SRC_LIBS_NIO12_CONTROL_STATION_H_ +#define SRC_LIBS_NIO12_CONTROL_STATION_H_ + +#include // + +#include "word_structurs.h" + + +////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// + + +#define COUNT_CONTROL_STATION CONTROL_STATION_LAST // - +//#define COUNT_CMD_ARR_CONTROL_STATION CONTROL_STATION_LAST // - + +////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// + + +#define CONTROL_STATION_TIME_WAIT 250//500 // + +#define CONTROL_STATION_SETUP_TIME_DETECT_ACTIVE 18//12//6 // CONTROL_STATION_TIME_WAIT +#define CONTROL_STATION_SETUP_TIME_DETECT_ACTIVE_RESEND_485 2 // CONTROL_STATION_TIME_WAIT +#define CONTROL_STATION_SETUP_TIME_SEND_CMD_AFTER_OFF 5 // CONTROL_STATION_TIME_WAIT + +#define CONTROL_STATION_MAX_RAW_DATA 256 //128 // - +#define CONTROL_STATION_MAX_RAW_DATA_TEMP 3 //128 // + +////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// + +typedef struct { + + unsigned int time_detect_active[COUNT_CONTROL_STATION]; // , + unsigned int period_detect_active[COUNT_CONTROL_STATION]; // + unsigned int time_detect_answer_485[COUNT_CONTROL_STATION]; // Modbus + + unsigned int setup_time_detect_active[COUNT_CONTROL_STATION]; // + unsigned int setup_time_detect_active_resend_485[COUNT_CONTROL_STATION]; // , setup_time_detect_active + unsigned int setup_time_send_cmd_after_off[COUNT_CONTROL_STATION]; // , Go. /. + + unsigned int active_control_station[COUNT_CONTROL_STATION]; // , ? + + unsigned int detect_get_data_control_station[COUNT_CONTROL_STATION]; // , , update_timers + + + unsigned int alive_control_station[COUNT_CONTROL_STATION]; // + + + int array_cmd[COUNT_CONTROL_STATION][CONTROL_STATION_CMD_LAST]; // , parse + int active_array_cmd[CONTROL_STATION_CMD_LAST]; // , parse + + WORD_UINT2BITS_STRUCT raw_array_data[COUNT_CONTROL_STATION][CONTROL_STATION_MAX_RAW_DATA]; // , parse. + WORD_UINT2BITS_STRUCT raw_array_data_temp[COUNT_CONTROL_STATION][CONTROL_STATION_MAX_RAW_DATA][CONTROL_STATION_MAX_RAW_DATA_TEMP]; // , parse. + + unsigned int flag_message_sent[COUNT_CONTROL_STATION]; // - + unsigned int flag_waiting_answer[COUNT_CONTROL_STATION]; // - + + unsigned int count_ok_modbus[COUNT_CONTROL_STATION]; // modbus 15 + unsigned int count_error_modbus[COUNT_CONTROL_STATION]; // modbus 15 + + unsigned int flag_refresh_array[COUNT_CONTROL_STATION]; // modbus + +/* + unsigned int cmd_go_from_control_station[COUNT_CONTROL_STATION]; // cmd_go / + unsigned int set_izad_from_control_station[COUNT_CONTROL_STATION]; // + unsigned int set_rotor_from_control_station[COUNT_CONTROL_STATION]; // + unsigned int cmd_charge_from_control_station[COUNT_CONTROL_STATION]; // + unsigned int cmd_uncharge_from_control_station[COUNT_CONTROL_STATION]; // + unsigned int cmd_checkback_from_control_station[COUNT_CONTROL_STATION]; // + unsigned int cmd_test_leds_from_control_station[COUNT_CONTROL_STATION]; // +*/ + unsigned int prev_CAN_count_cycle_input_units[COUNT_CONTROL_STATION]; // - CAN + unsigned int count_raw_array_data_temp[COUNT_CONTROL_STATION]; // CONTROL_STATION_MAX_RAW_DATA_TEMP + + void (*clear)(); // Clear buffers + void (*update_timers)(); // + void (*detect_active_station)(); // + +} CONTROL_STATION; + +typedef CONTROL_STATION *CONTROL_STATION_handle; + + + +#define CONTROL_STATION_DEFAULTS { \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + {0}, \ + control_station_clear, \ + control_station_update_timers, \ + control_station_detect_active_station \ +} + + + + +void control_station_clear(CONTROL_STATION_handle); +void control_station_update_timers(CONTROL_STATION_handle); +void control_station_detect_active_station(CONTROL_STATION_handle); + + + + +extern CONTROL_STATION control_station; + + + +#endif /* SRC_LIBS_NIO12_CONTROL_STATION_H_ */ diff --git a/Inu/Src/N12_Libs/filter_v1.c b/Inu/Src/N12_Libs/filter_v1.c new file mode 100644 index 0000000..5a8d337 --- /dev/null +++ b/Inu/Src/N12_Libs/filter_v1.c @@ -0,0 +1,367 @@ +#include "IQmathLib.h" +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File + + +#include "filter_v1.h" + + +//#include "filter.h" +//#include "myfir16.h" + + +/* +#define IIR16_COEFF {\ + -10304,25264,4493,8986,4493} + +#define IIR16_ISF 1298 +#define IIR16_NBIQ 1 +#define IIR16_QFMAT 14 + + + +#define FIR16_COEFF_50_75HZ {\ + 4927,-1568135,-2289592,-2814717,-2881240,-2030268,471,3407677,7601571,11730182,\ + 14023990,12910061,6880988,-4194369,-19136408,-34799420,-46792491,-49938254,-39649165,-12779469,\ + 30867456,88408033,153681876,218365909,273219549,309985256} + + + + +#define FIR16_COEFF_58 {\ + 1165,2622601,2884733,3409000,4129869,5178410,6489088,8127441,10093469,12387172,\ + 15008553,17957610,21168811,24707691,28443180,32375278,36438450,40567161,44761411,48890130,\ + 53018853,56885437,60620954,64028796,67108963,69861455,72155199,73924660,75300908,76087336,\ + } + + + + +#define FIR16_COEFF_WROTOR {\ + 316,1245500,1245499,1245499,1245498,1311034,1376569,1376568,1442103,1507637,\ + 1573172,1638706,1769776,1835310,1966380,2031914,2162984,2294053,2425123,2556192,\ + 2752797,2883866,3080471,3211539,3408144,3604749,3801353,3997957,4194562,4391166,\ + 4653306,4849910,5112050,5308653,5570793,5832933,6095072,6357212,6619351,6881491,\ + 7143630,7471306,7733445,7995584,8323260,8585399,8913074,9240749,9502889,9830564,\ + 10158239,10420379,10748054,11075729,11337869,11665544,11993219,12320895,12583034,12910710,\ + 13238386,13500525,13828201,14090341,14418017,14680157,15007833,15269973,15532113,15859790,\ + 16121930,16384071,16646211,16908352,17104957,17367098,17629239,17825844,18022449,18284591,\ + 18481196,18677802,18874407,19071013,19202083,19398689,19529759,19660830,19791900,19922971,\ + 20054041,20185112,20250647,20381718,20447253,20512789,20578324,20578323,20643859,20643859,\ + 20709395} + + +*/ + +/* Filter Symbolic Constants */ +//#define FIR_ORDER_58 58 + + + +//#define FIR_ORDER_50_75HZ 50 + + + +//#define FIR16_COEFF {\ +// 16519,532422588} + + +/* Filter Symbolic Constants */ +//#define FIR_ORDER 2 + + + + + +/* Create an Instance of FIRFILT_GEN module and place the object in "firfilt" section */ +//#pragma DATA_SECTION(fir, "firfilt"); +//FIR16 fir = FIR16_DEFAULTS; +//FIR16 fir_58 = FIR16_DEFAULTS; +//FIR16 fir_wrotor = FIR16_DEFAULTS; + +//FIR16 fir_50_75hz_0 = FIR16_DEFAULTS; +/* +FIR16 fir_50_75hz_1 = FIR16_DEFAULTS; +FIR16 fir_50_75hz_2 = FIR16_DEFAULTS; +FIR16 fir_50_75hz_3 = FIR16_DEFAULTS; +FIR16 fir_50_75hz_4 = FIR16_DEFAULTS; +FIR16 fir_50_75hz_5 = FIR16_DEFAULTS; +*/ + + + +/* Define the Delay buffer for the 50th order filterfilter and place it in "firldb" section */ +//#pragma DATA_SECTION(dbuffer_fir,"firldb"); +//long dbuffer_fir[(FIR_ORDER+2)/2]; + +//long dbuffer_fir_50_75hz_0[(FIR_ORDER_50_75HZ+2)/2]; +/*long dbuffer_fir_50_75hz_1[(FIR_ORDER_50_75HZ+2)/2]; +long dbuffer_fir_50_75hz_2[(FIR_ORDER_50_75HZ+2)/2]; +long dbuffer_fir_50_75hz_3[(FIR_ORDER_50_75HZ+2)/2]; +long dbuffer_fir_50_75hz_4[(FIR_ORDER_50_75HZ+2)/2]; +long dbuffer_fir_50_75hz_5[(FIR_ORDER_50_75HZ+2)/2]; + */ + + + + + + +//#pragma DATA_SECTION(dbuffer_fir_58,"firldb"); +//long dbuffer_fir_58[(FIR_ORDER_58+2)/2]; + +//#pragma DATA_SECTION(dbuffer_fir_wrotor,"firldb"); + + + +/* Define Constant Co-efficient Array and place the +.constant section in ROM memory */ + +//long const coeff_fir[(FIR_ORDER+2)/2]= FIR16_COEFF; +//long const coeff_fir_58[(FIR_ORDER_58+2)/2]= FIR16_COEFF_58; + + + + + +//long const coeff_fir_50_75hz_0[(FIR_ORDER_50_75HZ+2)/2]= FIR16_COEFF_50_75HZ; +/*long const coeff_fir_50_75hz_1[(FIR_ORDER_50_75HZ+2)/2]= FIR16_COEFF_50_75HZ; +long const coeff_fir_50_75hz_2[(FIR_ORDER_50_75HZ+2)/2]= FIR16_COEFF_50_75HZ; +long const coeff_fir_50_75hz_3[(FIR_ORDER_50_75HZ+2)/2]= FIR16_COEFF_50_75HZ; +long const coeff_fir_50_75hz_4[(FIR_ORDER_50_75HZ+2)/2]= FIR16_COEFF_50_75HZ; +long const coeff_fir_50_75hz_5[(FIR_ORDER_50_75HZ+2)/2]= FIR16_COEFF_50_75HZ; +*/ + + +/* Finter Input and Output Variables */ + + + +/* Create an Instance of IIR5BIQD16 module and place the object in "iirfilt" section */ +//#pragma DATA_SECTION(iir, "iirfilt"); +//IIR5BIQ16 iir = IIR5BIQ16_DEFAULTS; + +/* ============================================================================= +Modify the delay buffer size to comensurate with the no of biquads in the filter +Size of the Delay buffer=2*nbiq +==============================================================================*/ +/* Define the Delay buffer for the cascaded 6 biquad IIR filter and place it in "iirfilt" section */ +//#pragma DATA_SECTION(dbuffer_iir,"iirfilt"); +//int dbuffer_iir[2*IIR16_NBIQ]; + + +/* ============================================================================= +Modify the array size and symbolic constant to suit your filter requiremnt. +Size of the coefficient array=5*nbiq +==============================================================================*/ +/* Define the Delay buffer for the cascaded 6 biquad IIR filter and place it in "iirfilt" section */ + +//const int coeff_iir[5*IIR16_NBIQ]=IIR16_COEFF; + + +/* +void init_my_filter_fir() +{ + +// FIR Generic Filter Initialisation + fir.order=FIR_ORDER; + fir.dbuffer_ptr=dbuffer_fir; + fir.coeff_ptr=(long *)coeff_fir; + fir.init(&fir); +} + + +void init_my_filter_fir_50_75hz() +{ + +// FIR Generic Filter Initialisation + fir_50_75hz_0.order=FIR_ORDER_50_75HZ; + fir_50_75hz_0.dbuffer_ptr=dbuffer_fir_50_75hz_0; + fir_50_75hz_0.coeff_ptr=(long *)coeff_fir_50_75hz_0; + fir_50_75hz_0.init(&fir_50_75hz_0); + +} + + + + +//#pragma CODE_SECTION(calc_my_filter_fir,".fast_run"); +int calc_my_filter_fir(int xn) +{ +int yn; + +// xn=sgen.out; + fir.input=xn; + fir.calc(&fir); + yn=fir.output; + return yn; +} + + + +void init_my_filter_fir_58() +{ + +// FIR Generic Filter Initialisation + fir_58.order=FIR_ORDER_58; + fir_58.dbuffer_ptr=dbuffer_fir_58; + fir_58.coeff_ptr=(long *)coeff_fir_58; + fir_58.init(&fir_58); +} + + + + +//#pragma CODE_SECTION(calc_my_filter_fir_58,".fast_run"); +int calc_my_filter_fir_58(int xn) +{ +int yn; + +// xn=sgen.out; + fir_58.input=xn; + fir_58.calc(&fir_58); + yn=fir_58.output; + return yn; +} + + + + + + + +void calc_my_filter_fir_50_75hz(_iq xn_0,_iq xn_1,_iq xn_2,_iq xn_3,_iq xn_4,_iq xn_5, + _iq *yn_0,_iq *yn_1,_iq *yn_2,_iq *yn_3,_iq *yn_4,_iq *yn_5) +{ + fir_50_75hz_0.input=_IQtoIQ15(xn_0); + fir_50_75hz_0.calc(&fir_50_75hz_0); + *yn_0=_IQ15toIQ(fir_50_75hz_0.output); +} + + + +void init_my_filter_iir() +{ + +// IIR Filter Initialisation + iir.dbuffer_ptr=dbuffer_iir; + iir.coeff_ptr=(int *)coeff_iir; + iir.qfmat=IIR16_QFMAT; + iir.nbiq=IIR16_NBIQ; + iir.isf=IIR16_ISF; + iir.init(&iir); +} + + +//#pragma CODE_SECTION(calc_my_filter_iir,".fast_run"); +int calc_my_filter_iir(int xn) +{ +int yn; + +// xn=sgen.out; + iir.input=xn; + iir.calc(&iir); + yn=iir.output; + return yn; +} + +*/ + +#pragma CODE_SECTION(exp_regul_iq19,".fast_run"); +_iq19 exp_regul_iq19(_iq19 k_exp_regul, _iq19 InpVarCurr, _iq19 InpVarInstant) +{ + _iq19 t1; + + t1 = (InpVarCurr + _IQ19mpy( (InpVarInstant-InpVarCurr), k_exp_regul)); + return t1; +} + + +#pragma CODE_SECTION(exp_regul_iq,".fast_run"); +// +// T = T/k_exp_regul +// +_iq exp_regul_iq(_iq k_exp_regul, _iq InpVarFiltered, _iq InpVarInstant) +{ + _iq t1; + t1 = (InpVarFiltered + _IQmpy( (InpVarInstant-InpVarFiltered), k_exp_regul)); + return t1; +} + +#pragma CODE_SECTION(exp_regul_iq,".fast_run"); +void exp_regul_iq_fast(_iq k_exp_regul, _iq *InpVarCurr, _iq InpVarInstant) +{ + _iq t1; + volatile _iq t2,t3,t4; + + + t2 = (InpVarInstant- *InpVarCurr); + t3 = _IQmpy( t2, k_exp_regul); + t4 = *InpVarCurr + t3; + t1 = t4; + *InpVarCurr = t1; +// t1 = (InpVarCurr + _IQmpy( (InpVarInstant-InpVarCurr), k_exp_regul)); +// return t1; +} + + + + + +/* + +_iq18 filter_1p(_iq18 predx,_iq18 predy, _iq18 inpx) +{ + _iq18 t1; + + t1 = _IQ18mpy(k1_filter_1p_fast,(predx+inpx))+_IQ18mpy(k2_filter_1p_fast,predy); + return t1; +} + + +*/ + +/* + +void init_filter_batter2() +{ + u_filter_batter2[0]=0; + u_filter_batter2[1]=0; + u_filter_batter2[2]=0; + + i_filter_batter2[0]=0; + i_filter_batter2[1]=0; + i_filter_batter2[2]=0; + + k_filter_batter2[0]=_IQ(K1_FILTER_BATTER2_3HZ); + k_filter_batter2[1]=_IQ(K2_FILTER_BATTER2_3HZ); + k_filter_batter2[2]=_IQ(K3_FILTER_BATTER2_3HZ ); + +} + + + + +//#pragma CODE_SECTION(filter_batter2,".fast_run"); +_iq filter_batter2(_iq InpVarCurr) +{ +_iq y; + + y = _IQmpy(k_filter_batter2[0],( InpVarCurr + _IQmpyI32(i_filter_batter2[0],2) + i_filter_batter2[1] ) ) + + _IQmpy(k_filter_batter2[1], u_filter_batter2[0]) + _IQmpy(k_filter_batter2[2], u_filter_batter2[1]); + + u_filter_batter2[1]=u_filter_batter2[0]; + u_filter_batter2[0]=y; + + i_filter_batter2[1]=i_filter_batter2[0]; + i_filter_batter2[0]=InpVarCurr; + return y; + +} + + +*/ + + + + diff --git a/Inu/Src/N12_Libs/filter_v1.h b/Inu/Src/N12_Libs/filter_v1.h new file mode 100644 index 0000000..6ca43e9 --- /dev/null +++ b/Inu/Src/N12_Libs/filter_v1.h @@ -0,0 +1,73 @@ +#ifndef _MY_FILTER +#define _MY_FILTER + + + +#ifdef __cplusplus + extern "C" { +#endif + + + + +#include "IQmathLib.h" +//#include "filter.h" +//#include "myfir16.h" + + + +#define k1_filter_1p_fast 62643 // 0.238965*262144 +#define k2_filter_1p_fast 136857 // 0.52207*262144 +#define k3_filter_1p_fast2 8552 + + +#define filter_1p_fast(predx, predy,inpx) predy=_IQ18mpy(k1_filter_1p_fast,(predx+inpx))+_IQ18mpy(k2_filter_1p_fast,predy);predx=inpx +#define filter_1p_fast2(predx, predy,inpx) predy=_IQ18mpy(k3_filter_1p_fast2,(predx+inpx));predx=inpx + + + + + +//extern FIR16 fir; +//extern FIR16 fir_wrotor; +//extern IIR5BIQ16 iir; + + +void init_my_filter_fir(); +int calc_my_filter_fir(int xn); + +void init_my_filter_fir_58(); +int calc_my_filter_fir_58(int xn); + + + +void calc_my_filter_fir_50_75hz(_iq xn_0,_iq xn_1,_iq xn_2,_iq xn_3,_iq xn_4,_iq xn_5, + _iq *yn_0,_iq *yn_1,_iq *yn_2,_iq *yn_3,_iq *yn_4,_iq *yn_5); + +void init_my_filter_fir_50_75hz(); + + + +void init_my_filter_iir(); +int calc_my_filter_iir(int xn); + + + +_iq19 exp_regul_iq19(_iq19 k_exp_regul, _iq19 InpVarCurr, _iq19 InpVarInstant); +_iq exp_regul_iq(_iq k_exp_regul, _iq InpVarFiltered, _iq InpVarInstant); + + + + +_iq18 filter_1p(_iq18 predx,_iq18 predy, _iq18 inpx); + +void exp_regul_iq_fast(_iq k_exp_regul, _iq *InpVarCurr, _iq InpVarInstant); + + + +#ifdef __cplusplus + } +#endif + +#endif /* _MY_FILTER */ + diff --git a/Inu/Src/N12_Libs/global_time.c b/Inu/Src/N12_Libs/global_time.c new file mode 100644 index 0000000..a5db6ef --- /dev/null +++ b/Inu/Src/N12_Libs/global_time.c @@ -0,0 +1,149 @@ +#include "global_time.h" + + +GLOBAL_TIME global_time = GLOBAL_TIME_DEFAULTS; + + +void init_global_time_struct(unsigned int freq_pwm) +{ + global_time.total_seconds = 0; + global_time.total_seconds10 = 0; + global_time.total_seconds10full = 0; + global_time.microseconds = 0; + global_time.microseconds_temp = 0; + global_time.pwm_tics = 0; + global_time.miliseconds = 0; + global_time.miliseconds_long = 0; + global_time.seconds = 0; + global_time.minuts = 0; + global_time.hours = 0; + global_time.freq_pwm_hz = freq_pwm; + global_time.microseconds_add = 1000000L / global_time.freq_pwm_hz; +} + +#pragma CODE_SECTION(global_time_calc,".fast_run2"); +void global_time_calc(GLOBAL_TIME_handle gt) +{ + unsigned int miliseconds_temp = 0; + static unsigned int miliseconds_temp10 = 0; + + gt->pwm_tics++; + gt->microseconds += gt->microseconds_add; + gt->microseconds_temp += gt->microseconds_add; + + if (gt->microseconds_temp>=1000) + { + if (gt->microseconds_temp>=2000) + { + miliseconds_temp = gt->microseconds_temp/1000; + gt->microseconds_temp -= miliseconds_temp*1000; + } + else + { + miliseconds_temp = 1; + gt->microseconds_temp -= 1000; + } + } + +// gt->miliseconds = gt->microseconds / 1000; + + gt->miliseconds += miliseconds_temp; + miliseconds_temp10 += miliseconds_temp; + + if(gt->pwm_tics == gt->freq_pwm_hz) + { + gt->total_seconds++; + gt->total_seconds10 += 10; + + gt->seconds++; + gt->pwm_tics = 0; + miliseconds_temp10 = 0; + + if(gt->seconds == 60) + { + gt->minuts++; + gt->seconds = 0; + + if(gt->minuts == 60) + { + gt->hours++; + gt->minuts = 0; + } + } + } + + //gt->total_seconds10 += 10; + gt->total_seconds10full = gt->total_seconds10 + miliseconds_temp10/100; +} + + +void init_timer_sec(unsigned int *start_time) +{ + *start_time = global_time.total_seconds; +} + +void init_timer_milisec(unsigned int *start_time) +{ + *start_time = global_time.miliseconds; +} + +int detect_pause_sec(unsigned int wait_pause, unsigned int *old_time) +{ + unsigned long delta; + + if(global_time.total_seconds >= *old_time) + { + delta = (unsigned int)((unsigned int)global_time.total_seconds - *old_time); + } + else + { + delta = (unsigned int)((unsigned int)global_time.total_seconds + (0xFFFFUL - *old_time)); + } + + if (delta>=wait_pause) + { + *old_time = (unsigned int)global_time.total_seconds; + return 1; + } + else + return 0; +} + +int detect_pause_milisec(unsigned int wait_pause, unsigned int *old_time) +{ + unsigned long delta; + if(global_time.miliseconds >= *old_time) + { + delta = (unsigned int)((unsigned int)global_time.miliseconds - *old_time); + } + else + { + delta = (unsigned int)((unsigned int)global_time.miliseconds + (0xFFFFUL - *old_time)); + } + + if (delta>=wait_pause) + { + *old_time = (unsigned int)global_time.miliseconds; + return 1; + } + else + return 0; +} + +unsigned int get_delta_milisec(unsigned int *old_time, unsigned int upd) +{ + unsigned long delta; + + if(global_time.miliseconds >= *old_time) + { + delta = (unsigned int)((unsigned int)global_time.miliseconds - *old_time); + } + else + { + delta = (unsigned int)((unsigned int)global_time.miliseconds + (0xFFFFUL - *old_time)); + } + if (upd) + *old_time = (unsigned int)global_time.miliseconds; + + return delta; +} diff --git a/Inu/Src/N12_Libs/global_time.h b/Inu/Src/N12_Libs/global_time.h new file mode 100644 index 0000000..f4f4e2c --- /dev/null +++ b/Inu/Src/N12_Libs/global_time.h @@ -0,0 +1,58 @@ +#ifndef _GLOBAL_TIME +#define _GLOBAL_TIME + +typedef struct { + unsigned long total_seconds; // + unsigned long total_seconds10; // + unsigned long total_seconds10full; // + unsigned long microseconds; + unsigned int microseconds_temp; + + unsigned int miliseconds; //??? + unsigned long miliseconds_long; //??? + unsigned int pwm_tics; + unsigned int seconds; + unsigned int minuts; + unsigned int hours; + unsigned int freq_pwm_hz; + unsigned int microseconds_add; + void (*calc)(); // ' +} GLOBAL_TIME; + +typedef GLOBAL_TIME *GLOBAL_TIME_handle; + +void global_time_calc(GLOBAL_TIME_handle); +void init_global_time_struct(unsigned int freq_pwm); + +/*----------------------------------------------------------------------------- +Default initalizer for the GLOBAL_TIME object. +-----------------------------------------------------------------------------*/ +#define GLOBAL_TIME_DEFAULTS { 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + global_time_calc \ +} +/*------------------------------------------------------------------------------ +Prototypes for the functions in global_time.c +------------------------------------------------------------------------------*/ + + +extern GLOBAL_TIME global_time; + +void init_timer_sec(unsigned int *start_time); // , +void init_timer_milisec(unsigned int *start_time); // , +int detect_pause_sec(unsigned int wait_pause, unsigned int *old_time); // +int detect_pause_milisec(unsigned int wait_pause, unsigned int *old_time); // ( 60000) +unsigned int get_delta_milisec(unsigned int *old_time, unsigned int upd); // old_time ; upd=1 - old_time - + +#endif //_GLOBAL_TIME diff --git a/Inu/Src/N12_Libs/iq_values_norma_f.h b/Inu/Src/N12_Libs/iq_values_norma_f.h new file mode 100644 index 0000000..19985b5 --- /dev/null +++ b/Inu/Src/N12_Libs/iq_values_norma_f.h @@ -0,0 +1,6025 @@ +/* + * iq_values_norma.h + * + * Created on: 9 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef _IQ_VALUES_NORMA_F_H_ +#define _IQ_VALUES_NORMA_F_H_ + +#include "params_norma.h" + + +#if (NORMA_FROTOR_INT==20) + +#define IQ_F_VALUE_MINUS_30_00 -25165824 // hz = -30 +#define IQ_F_VALUE_MINUS_29_99 -25157436 // hz = -29.99 +#define IQ_F_VALUE_MINUS_29_98 -25149047 // hz = -29.98 +#define IQ_F_VALUE_MINUS_29_97 -25140659 // hz = -29.97 +#define IQ_F_VALUE_MINUS_29_96 -25132270 // hz = -29.96 +#define IQ_F_VALUE_MINUS_29_95 -25123881 // hz = -29.95 +#define IQ_F_VALUE_MINUS_29_94 -25115493 // hz = -29.94 +#define IQ_F_VALUE_MINUS_29_93 -25107104 // hz = -29.93 +#define IQ_F_VALUE_MINUS_29_92 -25098716 // hz = -29.92 +#define IQ_F_VALUE_MINUS_29_91 -25090327 // hz = -29.91 +#define IQ_F_VALUE_MINUS_29_90 -25081938 // hz = -29.9 +#define IQ_F_VALUE_MINUS_29_89 -25073550 // hz = -29.89 +#define IQ_F_VALUE_MINUS_29_88 -25065161 // hz = -29.88 +#define IQ_F_VALUE_MINUS_29_87 -25056773 // hz = -29.87 +#define IQ_F_VALUE_MINUS_29_86 -25048384 // hz = -29.86 +#define IQ_F_VALUE_MINUS_29_85 -25039995 // hz = -29.85 +#define IQ_F_VALUE_MINUS_29_84 -25031607 // hz = -29.84 +#define IQ_F_VALUE_MINUS_29_83 -25023218 // hz = -29.83 +#define IQ_F_VALUE_MINUS_29_82 -25014830 // hz = -29.82 +#define IQ_F_VALUE_MINUS_29_81 -25006441 // hz = -29.81 +#define IQ_F_VALUE_MINUS_29_80 -24998052 // hz = -29.8 +#define IQ_F_VALUE_MINUS_29_79 -24989664 // hz = -29.79 +#define IQ_F_VALUE_MINUS_29_78 -24981275 // hz = -29.78 +#define IQ_F_VALUE_MINUS_29_77 -24972887 // hz = -29.77 +#define IQ_F_VALUE_MINUS_29_76 -24964498 // hz = -29.76 +#define IQ_F_VALUE_MINUS_29_75 -24956109 // hz = -29.75 +#define IQ_F_VALUE_MINUS_29_74 -24947721 // hz = -29.74 +#define IQ_F_VALUE_MINUS_29_73 -24939332 // hz = -29.73 +#define IQ_F_VALUE_MINUS_29_72 -24930943 // hz = -29.72 +#define IQ_F_VALUE_MINUS_29_71 -24922555 // hz = -29.71 +#define IQ_F_VALUE_MINUS_29_70 -24914166 // hz = -29.7 +#define IQ_F_VALUE_MINUS_29_69 -24905778 // hz = -29.69 +#define IQ_F_VALUE_MINUS_29_68 -24897389 // hz = -29.6799999999999 +#define IQ_F_VALUE_MINUS_29_67 -24889000 // hz = -29.6699999999999 +#define IQ_F_VALUE_MINUS_29_66 -24880612 // hz = -29.6599999999999 +#define IQ_F_VALUE_MINUS_29_65 -24872223 // hz = -29.6499999999999 +#define IQ_F_VALUE_MINUS_29_64 -24863835 // hz = -29.6399999999999 +#define IQ_F_VALUE_MINUS_29_63 -24855446 // hz = -29.6299999999999 +#define IQ_F_VALUE_MINUS_29_62 -24847057 // hz = -29.6199999999999 +#define IQ_F_VALUE_MINUS_29_61 -24838669 // hz = -29.6099999999999 +#define IQ_F_VALUE_MINUS_29_60 -24830280 // hz = -29.5999999999999 +#define IQ_F_VALUE_MINUS_29_59 -24821892 // hz = -29.5899999999999 +#define IQ_F_VALUE_MINUS_29_58 -24813503 // hz = -29.5799999999999 +#define IQ_F_VALUE_MINUS_29_57 -24805114 // hz = -29.5699999999999 +#define IQ_F_VALUE_MINUS_29_56 -24796726 // hz = -29.5599999999999 +#define IQ_F_VALUE_MINUS_29_55 -24788337 // hz = -29.5499999999999 +#define IQ_F_VALUE_MINUS_29_54 -24779949 // hz = -29.5399999999999 +#define IQ_F_VALUE_MINUS_29_53 -24771560 // hz = -29.5299999999999 +#define IQ_F_VALUE_MINUS_29_52 -24763171 // hz = -29.5199999999999 +#define IQ_F_VALUE_MINUS_29_51 -24754783 // hz = -29.5099999999999 +#define IQ_F_VALUE_MINUS_29_50 -24746394 // hz = -29.4999999999999 +#define IQ_F_VALUE_MINUS_29_49 -24738005 // hz = -29.4899999999999 +#define IQ_F_VALUE_MINUS_29_48 -24729617 // hz = -29.4799999999999 +#define IQ_F_VALUE_MINUS_29_47 -24721228 // hz = -29.4699999999999 +#define IQ_F_VALUE_MINUS_29_46 -24712840 // hz = -29.4599999999999 +#define IQ_F_VALUE_MINUS_29_45 -24704451 // hz = -29.4499999999999 +#define IQ_F_VALUE_MINUS_29_44 -24696062 // hz = -29.4399999999999 +#define IQ_F_VALUE_MINUS_29_43 -24687674 // hz = -29.4299999999999 +#define IQ_F_VALUE_MINUS_29_42 -24679285 // hz = -29.4199999999999 +#define IQ_F_VALUE_MINUS_29_41 -24670897 // hz = -29.4099999999999 +#define IQ_F_VALUE_MINUS_29_40 -24662508 // hz = -29.3999999999999 +#define IQ_F_VALUE_MINUS_29_39 -24654119 // hz = -29.3899999999999 +#define IQ_F_VALUE_MINUS_29_38 -24645731 // hz = -29.3799999999999 +#define IQ_F_VALUE_MINUS_29_37 -24637342 // hz = -29.3699999999999 +#define IQ_F_VALUE_MINUS_29_36 -24628954 // hz = -29.3599999999999 +#define IQ_F_VALUE_MINUS_29_35 -24620565 // hz = -29.3499999999999 +#define IQ_F_VALUE_MINUS_29_34 -24612176 // hz = -29.3399999999999 +#define IQ_F_VALUE_MINUS_29_33 -24603788 // hz = -29.3299999999999 +#define IQ_F_VALUE_MINUS_29_32 -24595399 // hz = -29.3199999999999 +#define IQ_F_VALUE_MINUS_29_31 -24587011 // hz = -29.3099999999999 +#define IQ_F_VALUE_MINUS_29_30 -24578622 // hz = -29.2999999999999 +#define IQ_F_VALUE_MINUS_29_29 -24570233 // hz = -29.2899999999999 +#define IQ_F_VALUE_MINUS_29_28 -24561845 // hz = -29.2799999999999 +#define IQ_F_VALUE_MINUS_29_27 -24553456 // hz = -29.2699999999999 +#define IQ_F_VALUE_MINUS_29_26 -24545068 // hz = -29.2599999999999 +#define IQ_F_VALUE_MINUS_29_25 -24536679 // hz = -29.2499999999999 +#define IQ_F_VALUE_MINUS_29_24 -24528290 // hz = -29.2399999999999 +#define IQ_F_VALUE_MINUS_29_23 -24519902 // hz = -29.2299999999999 +#define IQ_F_VALUE_MINUS_29_22 -24511513 // hz = -29.2199999999999 +#define IQ_F_VALUE_MINUS_29_21 -24503124 // hz = -29.2099999999999 +#define IQ_F_VALUE_MINUS_29_20 -24494736 // hz = -29.1999999999999 +#define IQ_F_VALUE_MINUS_29_19 -24486347 // hz = -29.1899999999999 +#define IQ_F_VALUE_MINUS_29_18 -24477959 // hz = -29.1799999999999 +#define IQ_F_VALUE_MINUS_29_17 -24469570 // hz = -29.1699999999999 +#define IQ_F_VALUE_MINUS_29_16 -24461181 // hz = -29.1599999999999 +#define IQ_F_VALUE_MINUS_29_15 -24452793 // hz = -29.1499999999999 +#define IQ_F_VALUE_MINUS_29_14 -24444404 // hz = -29.1399999999999 +#define IQ_F_VALUE_MINUS_29_13 -24436016 // hz = -29.1299999999999 +#define IQ_F_VALUE_MINUS_29_12 -24427627 // hz = -29.1199999999999 +#define IQ_F_VALUE_MINUS_29_11 -24419238 // hz = -29.1099999999999 +#define IQ_F_VALUE_MINUS_29_10 -24410850 // hz = -29.0999999999999 +#define IQ_F_VALUE_MINUS_29_09 -24402461 // hz = -29.0899999999999 +#define IQ_F_VALUE_MINUS_29_08 -24394073 // hz = -29.0799999999999 +#define IQ_F_VALUE_MINUS_29_07 -24385684 // hz = -29.0699999999999 +#define IQ_F_VALUE_MINUS_29_06 -24377295 // hz = -29.0599999999999 +#define IQ_F_VALUE_MINUS_29_05 -24368907 // hz = -29.0499999999999 +#define IQ_F_VALUE_MINUS_29_04 -24360518 // hz = -29.0399999999998 +#define IQ_F_VALUE_MINUS_29_03 -24352130 // hz = -29.0299999999998 +#define IQ_F_VALUE_MINUS_29_02 -24343741 // hz = -29.0199999999998 +#define IQ_F_VALUE_MINUS_29_01 -24335352 // hz = -29.0099999999998 +#define IQ_F_VALUE_MINUS_29_00 -24326964 // hz = -28.9999999999998 +#define IQ_F_VALUE_MINUS_28_99 -24318575 // hz = -28.9899999999998 +#define IQ_F_VALUE_MINUS_28_98 -24310186 // hz = -28.9799999999998 +#define IQ_F_VALUE_MINUS_28_97 -24301798 // hz = -28.9699999999998 +#define IQ_F_VALUE_MINUS_28_96 -24293409 // hz = -28.9599999999998 +#define IQ_F_VALUE_MINUS_28_95 -24285021 // hz = -28.9499999999998 +#define IQ_F_VALUE_MINUS_28_94 -24276632 // hz = -28.9399999999998 +#define IQ_F_VALUE_MINUS_28_93 -24268243 // hz = -28.9299999999998 +#define IQ_F_VALUE_MINUS_28_92 -24259855 // hz = -28.9199999999998 +#define IQ_F_VALUE_MINUS_28_91 -24251466 // hz = -28.9099999999998 +#define IQ_F_VALUE_MINUS_28_90 -24243078 // hz = -28.8999999999998 +#define IQ_F_VALUE_MINUS_28_89 -24234689 // hz = -28.8899999999998 +#define IQ_F_VALUE_MINUS_28_88 -24226300 // hz = -28.8799999999998 +#define IQ_F_VALUE_MINUS_28_87 -24217912 // hz = -28.8699999999998 +#define IQ_F_VALUE_MINUS_28_86 -24209523 // hz = -28.8599999999998 +#define IQ_F_VALUE_MINUS_28_85 -24201135 // hz = -28.8499999999998 +#define IQ_F_VALUE_MINUS_28_84 -24192746 // hz = -28.8399999999998 +#define IQ_F_VALUE_MINUS_28_83 -24184357 // hz = -28.8299999999998 +#define IQ_F_VALUE_MINUS_28_82 -24175969 // hz = -28.8199999999998 +#define IQ_F_VALUE_MINUS_28_81 -24167580 // hz = -28.8099999999998 +#define IQ_F_VALUE_MINUS_28_80 -24159192 // hz = -28.7999999999998 +#define IQ_F_VALUE_MINUS_28_79 -24150803 // hz = -28.7899999999998 +#define IQ_F_VALUE_MINUS_28_78 -24142414 // hz = -28.7799999999998 +#define IQ_F_VALUE_MINUS_28_77 -24134026 // hz = -28.7699999999998 +#define IQ_F_VALUE_MINUS_28_76 -24125637 // hz = -28.7599999999998 +#define IQ_F_VALUE_MINUS_28_75 -24117248 // hz = -28.7499999999998 +#define IQ_F_VALUE_MINUS_28_74 -24108860 // hz = -28.7399999999998 +#define IQ_F_VALUE_MINUS_28_73 -24100471 // hz = -28.7299999999998 +#define IQ_F_VALUE_MINUS_28_72 -24092083 // hz = -28.7199999999998 +#define IQ_F_VALUE_MINUS_28_71 -24083694 // hz = -28.7099999999998 +#define IQ_F_VALUE_MINUS_28_70 -24075305 // hz = -28.6999999999998 +#define IQ_F_VALUE_MINUS_28_69 -24066917 // hz = -28.6899999999998 +#define IQ_F_VALUE_MINUS_28_68 -24058528 // hz = -28.6799999999998 +#define IQ_F_VALUE_MINUS_28_67 -24050140 // hz = -28.6699999999998 +#define IQ_F_VALUE_MINUS_28_66 -24041751 // hz = -28.6599999999998 +#define IQ_F_VALUE_MINUS_28_65 -24033362 // hz = -28.6499999999998 +#define IQ_F_VALUE_MINUS_28_64 -24024974 // hz = -28.6399999999998 +#define IQ_F_VALUE_MINUS_28_63 -24016585 // hz = -28.6299999999998 +#define IQ_F_VALUE_MINUS_28_62 -24008197 // hz = -28.6199999999998 +#define IQ_F_VALUE_MINUS_28_61 -23999808 // hz = -28.6099999999998 +#define IQ_F_VALUE_MINUS_28_60 -23991419 // hz = -28.5999999999998 +#define IQ_F_VALUE_MINUS_28_59 -23983031 // hz = -28.5899999999998 +#define IQ_F_VALUE_MINUS_28_58 -23974642 // hz = -28.5799999999998 +#define IQ_F_VALUE_MINUS_28_57 -23966254 // hz = -28.5699999999998 +#define IQ_F_VALUE_MINUS_28_56 -23957865 // hz = -28.5599999999998 +#define IQ_F_VALUE_MINUS_28_55 -23949476 // hz = -28.5499999999998 +#define IQ_F_VALUE_MINUS_28_54 -23941088 // hz = -28.5399999999998 +#define IQ_F_VALUE_MINUS_28_53 -23932699 // hz = -28.5299999999998 +#define IQ_F_VALUE_MINUS_28_52 -23924311 // hz = -28.5199999999998 +#define IQ_F_VALUE_MINUS_28_51 -23915922 // hz = -28.5099999999998 +#define IQ_F_VALUE_MINUS_28_50 -23907533 // hz = -28.4999999999998 +#define IQ_F_VALUE_MINUS_28_49 -23899145 // hz = -28.4899999999998 +#define IQ_F_VALUE_MINUS_28_48 -23890756 // hz = -28.4799999999998 +#define IQ_F_VALUE_MINUS_28_47 -23882367 // hz = -28.4699999999998 +#define IQ_F_VALUE_MINUS_28_46 -23873979 // hz = -28.4599999999998 +#define IQ_F_VALUE_MINUS_28_45 -23865590 // hz = -28.4499999999998 +#define IQ_F_VALUE_MINUS_28_44 -23857202 // hz = -28.4399999999998 +#define IQ_F_VALUE_MINUS_28_43 -23848813 // hz = -28.4299999999998 +#define IQ_F_VALUE_MINUS_28_42 -23840424 // hz = -28.4199999999997 +#define IQ_F_VALUE_MINUS_28_41 -23832036 // hz = -28.4099999999998 +#define IQ_F_VALUE_MINUS_28_40 -23823647 // hz = -28.3999999999997 +#define IQ_F_VALUE_MINUS_28_39 -23815259 // hz = -28.3899999999998 +#define IQ_F_VALUE_MINUS_28_38 -23806870 // hz = -28.3799999999998 +#define IQ_F_VALUE_MINUS_28_37 -23798481 // hz = -28.3699999999997 +#define IQ_F_VALUE_MINUS_28_36 -23790093 // hz = -28.3599999999997 +#define IQ_F_VALUE_MINUS_28_35 -23781704 // hz = -28.3499999999997 +#define IQ_F_VALUE_MINUS_28_34 -23773316 // hz = -28.3399999999997 +#define IQ_F_VALUE_MINUS_28_33 -23764927 // hz = -28.3299999999997 +#define IQ_F_VALUE_MINUS_28_32 -23756538 // hz = -28.3199999999997 +#define IQ_F_VALUE_MINUS_28_31 -23748150 // hz = -28.3099999999997 +#define IQ_F_VALUE_MINUS_28_30 -23739761 // hz = -28.2999999999997 +#define IQ_F_VALUE_MINUS_28_29 -23731373 // hz = -28.2899999999997 +#define IQ_F_VALUE_MINUS_28_28 -23722984 // hz = -28.2799999999997 +#define IQ_F_VALUE_MINUS_28_27 -23714595 // hz = -28.2699999999997 +#define IQ_F_VALUE_MINUS_28_26 -23706207 // hz = -28.2599999999997 +#define IQ_F_VALUE_MINUS_28_25 -23697818 // hz = -28.2499999999997 +#define IQ_F_VALUE_MINUS_28_24 -23689429 // hz = -28.2399999999997 +#define IQ_F_VALUE_MINUS_28_23 -23681041 // hz = -28.2299999999997 +#define IQ_F_VALUE_MINUS_28_22 -23672652 // hz = -28.2199999999997 +#define IQ_F_VALUE_MINUS_28_21 -23664264 // hz = -28.2099999999997 +#define IQ_F_VALUE_MINUS_28_20 -23655875 // hz = -28.1999999999997 +#define IQ_F_VALUE_MINUS_28_19 -23647486 // hz = -28.1899999999997 +#define IQ_F_VALUE_MINUS_28_18 -23639098 // hz = -28.1799999999997 +#define IQ_F_VALUE_MINUS_28_17 -23630709 // hz = -28.1699999999997 +#define IQ_F_VALUE_MINUS_28_16 -23622321 // hz = -28.1599999999997 +#define IQ_F_VALUE_MINUS_28_15 -23613932 // hz = -28.1499999999997 +#define IQ_F_VALUE_MINUS_28_14 -23605543 // hz = -28.1399999999997 +#define IQ_F_VALUE_MINUS_28_13 -23597155 // hz = -28.1299999999997 +#define IQ_F_VALUE_MINUS_28_12 -23588766 // hz = -28.1199999999997 +#define IQ_F_VALUE_MINUS_28_11 -23580378 // hz = -28.1099999999997 +#define IQ_F_VALUE_MINUS_28_10 -23571989 // hz = -28.0999999999997 +#define IQ_F_VALUE_MINUS_28_09 -23563600 // hz = -28.0899999999997 +#define IQ_F_VALUE_MINUS_28_08 -23555212 // hz = -28.0799999999997 +#define IQ_F_VALUE_MINUS_28_07 -23546823 // hz = -28.0699999999997 +#define IQ_F_VALUE_MINUS_28_06 -23538435 // hz = -28.0599999999997 +#define IQ_F_VALUE_MINUS_28_05 -23530046 // hz = -28.0499999999997 +#define IQ_F_VALUE_MINUS_28_04 -23521657 // hz = -28.0399999999997 +#define IQ_F_VALUE_MINUS_28_03 -23513269 // hz = -28.0299999999997 +#define IQ_F_VALUE_MINUS_28_02 -23504880 // hz = -28.0199999999997 +#define IQ_F_VALUE_MINUS_28_01 -23496492 // hz = -28.0099999999997 +#define IQ_F_VALUE_MINUS_28_00 -23488103 // hz = -27.9999999999997 +#define IQ_F_VALUE_MINUS_27_99 -23479714 // hz = -27.9899999999997 +#define IQ_F_VALUE_MINUS_27_98 -23471326 // hz = -27.9799999999997 +#define IQ_F_VALUE_MINUS_27_97 -23462937 // hz = -27.9699999999997 +#define IQ_F_VALUE_MINUS_27_96 -23454548 // hz = -27.9599999999997 +#define IQ_F_VALUE_MINUS_27_95 -23446160 // hz = -27.9499999999997 +#define IQ_F_VALUE_MINUS_27_94 -23437771 // hz = -27.9399999999997 +#define IQ_F_VALUE_MINUS_27_93 -23429383 // hz = -27.9299999999997 +#define IQ_F_VALUE_MINUS_27_92 -23420994 // hz = -27.9199999999997 +#define IQ_F_VALUE_MINUS_27_91 -23412605 // hz = -27.9099999999997 +#define IQ_F_VALUE_MINUS_27_90 -23404217 // hz = -27.8999999999997 +#define IQ_F_VALUE_MINUS_27_89 -23395828 // hz = -27.8899999999997 +#define IQ_F_VALUE_MINUS_27_88 -23387440 // hz = -27.8799999999997 +#define IQ_F_VALUE_MINUS_27_87 -23379051 // hz = -27.8699999999997 +#define IQ_F_VALUE_MINUS_27_86 -23370662 // hz = -27.8599999999997 +#define IQ_F_VALUE_MINUS_27_85 -23362274 // hz = -27.8499999999997 +#define IQ_F_VALUE_MINUS_27_84 -23353885 // hz = -27.8399999999997 +#define IQ_F_VALUE_MINUS_27_83 -23345497 // hz = -27.8299999999997 +#define IQ_F_VALUE_MINUS_27_82 -23337108 // hz = -27.8199999999997 +#define IQ_F_VALUE_MINUS_27_81 -23328719 // hz = -27.8099999999997 +#define IQ_F_VALUE_MINUS_27_80 -23320331 // hz = -27.7999999999997 +#define IQ_F_VALUE_MINUS_27_79 -23311942 // hz = -27.7899999999997 +#define IQ_F_VALUE_MINUS_27_78 -23303554 // hz = -27.7799999999996 +#define IQ_F_VALUE_MINUS_27_77 -23295165 // hz = -27.7699999999997 +#define IQ_F_VALUE_MINUS_27_76 -23286776 // hz = -27.7599999999996 +#define IQ_F_VALUE_MINUS_27_75 -23278388 // hz = -27.7499999999997 +#define IQ_F_VALUE_MINUS_27_74 -23269999 // hz = -27.7399999999997 +#define IQ_F_VALUE_MINUS_27_73 -23261610 // hz = -27.7299999999996 +#define IQ_F_VALUE_MINUS_27_72 -23253222 // hz = -27.7199999999996 +#define IQ_F_VALUE_MINUS_27_71 -23244833 // hz = -27.7099999999996 +#define IQ_F_VALUE_MINUS_27_70 -23236445 // hz = -27.6999999999996 +#define IQ_F_VALUE_MINUS_27_69 -23228056 // hz = -27.6899999999996 +#define IQ_F_VALUE_MINUS_27_68 -23219667 // hz = -27.6799999999996 +#define IQ_F_VALUE_MINUS_27_67 -23211279 // hz = -27.6699999999996 +#define IQ_F_VALUE_MINUS_27_66 -23202890 // hz = -27.6599999999996 +#define IQ_F_VALUE_MINUS_27_65 -23194502 // hz = -27.6499999999996 +#define IQ_F_VALUE_MINUS_27_64 -23186113 // hz = -27.6399999999996 +#define IQ_F_VALUE_MINUS_27_63 -23177724 // hz = -27.6299999999996 +#define IQ_F_VALUE_MINUS_27_62 -23169336 // hz = -27.6199999999996 +#define IQ_F_VALUE_MINUS_27_61 -23160947 // hz = -27.6099999999996 +#define IQ_F_VALUE_MINUS_27_60 -23152559 // hz = -27.5999999999996 +#define IQ_F_VALUE_MINUS_27_59 -23144170 // hz = -27.5899999999996 +#define IQ_F_VALUE_MINUS_27_58 -23135781 // hz = -27.5799999999996 +#define IQ_F_VALUE_MINUS_27_57 -23127393 // hz = -27.5699999999996 +#define IQ_F_VALUE_MINUS_27_56 -23119004 // hz = -27.5599999999996 +#define IQ_F_VALUE_MINUS_27_55 -23110616 // hz = -27.5499999999996 +#define IQ_F_VALUE_MINUS_27_54 -23102227 // hz = -27.5399999999996 +#define IQ_F_VALUE_MINUS_27_53 -23093838 // hz = -27.5299999999996 +#define IQ_F_VALUE_MINUS_27_52 -23085450 // hz = -27.5199999999996 +#define IQ_F_VALUE_MINUS_27_51 -23077061 // hz = -27.5099999999996 +#define IQ_F_VALUE_MINUS_27_50 -23068672 // hz = -27.4999999999996 +#define IQ_F_VALUE_MINUS_27_49 -23060284 // hz = -27.4899999999996 +#define IQ_F_VALUE_MINUS_27_48 -23051895 // hz = -27.4799999999996 +#define IQ_F_VALUE_MINUS_27_47 -23043507 // hz = -27.4699999999996 +#define IQ_F_VALUE_MINUS_27_46 -23035118 // hz = -27.4599999999996 +#define IQ_F_VALUE_MINUS_27_45 -23026729 // hz = -27.4499999999996 +#define IQ_F_VALUE_MINUS_27_44 -23018341 // hz = -27.4399999999996 +#define IQ_F_VALUE_MINUS_27_43 -23009952 // hz = -27.4299999999996 +#define IQ_F_VALUE_MINUS_27_42 -23001564 // hz = -27.4199999999996 +#define IQ_F_VALUE_MINUS_27_41 -22993175 // hz = -27.4099999999996 +#define IQ_F_VALUE_MINUS_27_40 -22984786 // hz = -27.3999999999996 +#define IQ_F_VALUE_MINUS_27_39 -22976398 // hz = -27.3899999999996 +#define IQ_F_VALUE_MINUS_27_38 -22968009 // hz = -27.3799999999996 +#define IQ_F_VALUE_MINUS_27_37 -22959621 // hz = -27.3699999999996 +#define IQ_F_VALUE_MINUS_27_36 -22951232 // hz = -27.3599999999996 +#define IQ_F_VALUE_MINUS_27_35 -22942843 // hz = -27.3499999999996 +#define IQ_F_VALUE_MINUS_27_34 -22934455 // hz = -27.3399999999996 +#define IQ_F_VALUE_MINUS_27_33 -22926066 // hz = -27.3299999999996 +#define IQ_F_VALUE_MINUS_27_32 -22917678 // hz = -27.3199999999996 +#define IQ_F_VALUE_MINUS_27_31 -22909289 // hz = -27.3099999999996 +#define IQ_F_VALUE_MINUS_27_30 -22900900 // hz = -27.2999999999996 +#define IQ_F_VALUE_MINUS_27_29 -22892512 // hz = -27.2899999999996 +#define IQ_F_VALUE_MINUS_27_28 -22884123 // hz = -27.2799999999996 +#define IQ_F_VALUE_MINUS_27_27 -22875735 // hz = -27.2699999999996 +#define IQ_F_VALUE_MINUS_27_26 -22867346 // hz = -27.2599999999996 +#define IQ_F_VALUE_MINUS_27_25 -22858957 // hz = -27.2499999999996 +#define IQ_F_VALUE_MINUS_27_24 -22850569 // hz = -27.2399999999996 +#define IQ_F_VALUE_MINUS_27_23 -22842180 // hz = -27.2299999999996 +#define IQ_F_VALUE_MINUS_27_22 -22833791 // hz = -27.2199999999996 +#define IQ_F_VALUE_MINUS_27_21 -22825403 // hz = -27.2099999999996 +#define IQ_F_VALUE_MINUS_27_20 -22817014 // hz = -27.1999999999996 +#define IQ_F_VALUE_MINUS_27_19 -22808626 // hz = -27.1899999999996 +#define IQ_F_VALUE_MINUS_27_18 -22800237 // hz = -27.1799999999996 +#define IQ_F_VALUE_MINUS_27_17 -22791848 // hz = -27.1699999999996 +#define IQ_F_VALUE_MINUS_27_16 -22783460 // hz = -27.1599999999996 +#define IQ_F_VALUE_MINUS_27_15 -22775071 // hz = -27.1499999999996 +#define IQ_F_VALUE_MINUS_27_14 -22766683 // hz = -27.1399999999995 +#define IQ_F_VALUE_MINUS_27_13 -22758294 // hz = -27.1299999999996 +#define IQ_F_VALUE_MINUS_27_12 -22749905 // hz = -27.1199999999995 +#define IQ_F_VALUE_MINUS_27_11 -22741517 // hz = -27.1099999999996 +#define IQ_F_VALUE_MINUS_27_10 -22733128 // hz = -27.0999999999996 +#define IQ_F_VALUE_MINUS_27_09 -22724740 // hz = -27.0899999999995 +#define IQ_F_VALUE_MINUS_27_08 -22716351 // hz = -27.0799999999995 +#define IQ_F_VALUE_MINUS_27_07 -22707962 // hz = -27.0699999999995 +#define IQ_F_VALUE_MINUS_27_06 -22699574 // hz = -27.0599999999995 +#define IQ_F_VALUE_MINUS_27_05 -22691185 // hz = -27.0499999999995 +#define IQ_F_VALUE_MINUS_27_04 -22682797 // hz = -27.0399999999995 +#define IQ_F_VALUE_MINUS_27_03 -22674408 // hz = -27.0299999999995 +#define IQ_F_VALUE_MINUS_27_02 -22666019 // hz = -27.0199999999995 +#define IQ_F_VALUE_MINUS_27_01 -22657631 // hz = -27.0099999999995 +#define IQ_F_VALUE_MINUS_27_00 -22649242 // hz = -26.9999999999995 +#define IQ_F_VALUE_MINUS_26_99 -22640853 // hz = -26.9899999999995 +#define IQ_F_VALUE_MINUS_26_98 -22632465 // hz = -26.9799999999995 +#define IQ_F_VALUE_MINUS_26_97 -22624076 // hz = -26.9699999999995 +#define IQ_F_VALUE_MINUS_26_96 -22615688 // hz = -26.9599999999995 +#define IQ_F_VALUE_MINUS_26_95 -22607299 // hz = -26.9499999999995 +#define IQ_F_VALUE_MINUS_26_94 -22598910 // hz = -26.9399999999995 +#define IQ_F_VALUE_MINUS_26_93 -22590522 // hz = -26.9299999999995 +#define IQ_F_VALUE_MINUS_26_92 -22582133 // hz = -26.9199999999995 +#define IQ_F_VALUE_MINUS_26_91 -22573745 // hz = -26.9099999999995 +#define IQ_F_VALUE_MINUS_26_90 -22565356 // hz = -26.8999999999995 +#define IQ_F_VALUE_MINUS_26_89 -22556967 // hz = -26.8899999999995 +#define IQ_F_VALUE_MINUS_26_88 -22548579 // hz = -26.8799999999995 +#define IQ_F_VALUE_MINUS_26_87 -22540190 // hz = -26.8699999999995 +#define IQ_F_VALUE_MINUS_26_86 -22531802 // hz = -26.8599999999995 +#define IQ_F_VALUE_MINUS_26_85 -22523413 // hz = -26.8499999999995 +#define IQ_F_VALUE_MINUS_26_84 -22515024 // hz = -26.8399999999995 +#define IQ_F_VALUE_MINUS_26_83 -22506636 // hz = -26.8299999999995 +#define IQ_F_VALUE_MINUS_26_82 -22498247 // hz = -26.8199999999995 +#define IQ_F_VALUE_MINUS_26_81 -22489859 // hz = -26.8099999999995 +#define IQ_F_VALUE_MINUS_26_80 -22481470 // hz = -26.7999999999995 +#define IQ_F_VALUE_MINUS_26_79 -22473081 // hz = -26.7899999999995 +#define IQ_F_VALUE_MINUS_26_78 -22464693 // hz = -26.7799999999995 +#define IQ_F_VALUE_MINUS_26_77 -22456304 // hz = -26.7699999999995 +#define IQ_F_VALUE_MINUS_26_76 -22447916 // hz = -26.7599999999995 +#define IQ_F_VALUE_MINUS_26_75 -22439527 // hz = -26.7499999999995 +#define IQ_F_VALUE_MINUS_26_74 -22431138 // hz = -26.7399999999995 +#define IQ_F_VALUE_MINUS_26_73 -22422750 // hz = -26.7299999999995 +#define IQ_F_VALUE_MINUS_26_72 -22414361 // hz = -26.7199999999995 +#define IQ_F_VALUE_MINUS_26_71 -22405972 // hz = -26.7099999999995 +#define IQ_F_VALUE_MINUS_26_70 -22397584 // hz = -26.6999999999995 +#define IQ_F_VALUE_MINUS_26_69 -22389195 // hz = -26.6899999999995 +#define IQ_F_VALUE_MINUS_26_68 -22380807 // hz = -26.6799999999995 +#define IQ_F_VALUE_MINUS_26_67 -22372418 // hz = -26.6699999999995 +#define IQ_F_VALUE_MINUS_26_66 -22364029 // hz = -26.6599999999995 +#define IQ_F_VALUE_MINUS_26_65 -22355641 // hz = -26.6499999999995 +#define IQ_F_VALUE_MINUS_26_64 -22347252 // hz = -26.6399999999995 +#define IQ_F_VALUE_MINUS_26_63 -22338864 // hz = -26.6299999999995 +#define IQ_F_VALUE_MINUS_26_62 -22330475 // hz = -26.6199999999995 +#define IQ_F_VALUE_MINUS_26_61 -22322086 // hz = -26.6099999999995 +#define IQ_F_VALUE_MINUS_26_60 -22313698 // hz = -26.5999999999995 +#define IQ_F_VALUE_MINUS_26_59 -22305309 // hz = -26.5899999999995 +#define IQ_F_VALUE_MINUS_26_58 -22296921 // hz = -26.5799999999995 +#define IQ_F_VALUE_MINUS_26_57 -22288532 // hz = -26.5699999999995 +#define IQ_F_VALUE_MINUS_26_56 -22280143 // hz = -26.5599999999995 +#define IQ_F_VALUE_MINUS_26_55 -22271755 // hz = -26.5499999999995 +#define IQ_F_VALUE_MINUS_26_54 -22263366 // hz = -26.5399999999995 +#define IQ_F_VALUE_MINUS_26_53 -22254978 // hz = -26.5299999999995 +#define IQ_F_VALUE_MINUS_26_52 -22246589 // hz = -26.5199999999995 +#define IQ_F_VALUE_MINUS_26_51 -22238200 // hz = -26.5099999999995 +#define IQ_F_VALUE_MINUS_26_50 -22229812 // hz = -26.4999999999994 +#define IQ_F_VALUE_MINUS_26_49 -22221423 // hz = -26.4899999999995 +#define IQ_F_VALUE_MINUS_26_48 -22213034 // hz = -26.4799999999994 +#define IQ_F_VALUE_MINUS_26_47 -22204646 // hz = -26.4699999999995 +#define IQ_F_VALUE_MINUS_26_46 -22196257 // hz = -26.4599999999995 +#define IQ_F_VALUE_MINUS_26_45 -22187869 // hz = -26.4499999999994 +#define IQ_F_VALUE_MINUS_26_44 -22179480 // hz = -26.4399999999994 +#define IQ_F_VALUE_MINUS_26_43 -22171091 // hz = -26.4299999999994 +#define IQ_F_VALUE_MINUS_26_42 -22162703 // hz = -26.4199999999994 +#define IQ_F_VALUE_MINUS_26_41 -22154314 // hz = -26.4099999999994 +#define IQ_F_VALUE_MINUS_26_40 -22145926 // hz = -26.3999999999994 +#define IQ_F_VALUE_MINUS_26_39 -22137537 // hz = -26.3899999999994 +#define IQ_F_VALUE_MINUS_26_38 -22129148 // hz = -26.3799999999994 +#define IQ_F_VALUE_MINUS_26_37 -22120760 // hz = -26.3699999999994 +#define IQ_F_VALUE_MINUS_26_36 -22112371 // hz = -26.3599999999994 +#define IQ_F_VALUE_MINUS_26_35 -22103983 // hz = -26.3499999999994 +#define IQ_F_VALUE_MINUS_26_34 -22095594 // hz = -26.3399999999994 +#define IQ_F_VALUE_MINUS_26_33 -22087205 // hz = -26.3299999999994 +#define IQ_F_VALUE_MINUS_26_32 -22078817 // hz = -26.3199999999994 +#define IQ_F_VALUE_MINUS_26_31 -22070428 // hz = -26.3099999999994 +#define IQ_F_VALUE_MINUS_26_30 -22062040 // hz = -26.2999999999994 +#define IQ_F_VALUE_MINUS_26_29 -22053651 // hz = -26.2899999999994 +#define IQ_F_VALUE_MINUS_26_28 -22045262 // hz = -26.2799999999994 +#define IQ_F_VALUE_MINUS_26_27 -22036874 // hz = -26.2699999999994 +#define IQ_F_VALUE_MINUS_26_26 -22028485 // hz = -26.2599999999994 +#define IQ_F_VALUE_MINUS_26_25 -22020096 // hz = -26.2499999999994 +#define IQ_F_VALUE_MINUS_26_24 -22011708 // hz = -26.2399999999994 +#define IQ_F_VALUE_MINUS_26_23 -22003319 // hz = -26.2299999999994 +#define IQ_F_VALUE_MINUS_26_22 -21994931 // hz = -26.2199999999994 +#define IQ_F_VALUE_MINUS_26_21 -21986542 // hz = -26.2099999999994 +#define IQ_F_VALUE_MINUS_26_20 -21978153 // hz = -26.1999999999994 +#define IQ_F_VALUE_MINUS_26_19 -21969765 // hz = -26.1899999999994 +#define IQ_F_VALUE_MINUS_26_18 -21961376 // hz = -26.1799999999994 +#define IQ_F_VALUE_MINUS_26_17 -21952988 // hz = -26.1699999999994 +#define IQ_F_VALUE_MINUS_26_16 -21944599 // hz = -26.1599999999994 +#define IQ_F_VALUE_MINUS_26_15 -21936210 // hz = -26.1499999999994 +#define IQ_F_VALUE_MINUS_26_14 -21927822 // hz = -26.1399999999994 +#define IQ_F_VALUE_MINUS_26_13 -21919433 // hz = -26.1299999999994 +#define IQ_F_VALUE_MINUS_26_12 -21911045 // hz = -26.1199999999994 +#define IQ_F_VALUE_MINUS_26_11 -21902656 // hz = -26.1099999999994 +#define IQ_F_VALUE_MINUS_26_10 -21894267 // hz = -26.0999999999994 +#define IQ_F_VALUE_MINUS_26_09 -21885879 // hz = -26.0899999999994 +#define IQ_F_VALUE_MINUS_26_08 -21877490 // hz = -26.0799999999994 +#define IQ_F_VALUE_MINUS_26_07 -21869102 // hz = -26.0699999999994 +#define IQ_F_VALUE_MINUS_26_06 -21860713 // hz = -26.0599999999994 +#define IQ_F_VALUE_MINUS_26_05 -21852324 // hz = -26.0499999999994 +#define IQ_F_VALUE_MINUS_26_04 -21843936 // hz = -26.0399999999994 +#define IQ_F_VALUE_MINUS_26_03 -21835547 // hz = -26.0299999999994 +#define IQ_F_VALUE_MINUS_26_02 -21827159 // hz = -26.0199999999994 +#define IQ_F_VALUE_MINUS_26_01 -21818770 // hz = -26.0099999999994 +#define IQ_F_VALUE_MINUS_26_00 -21810381 // hz = -25.9999999999994 +#define IQ_F_VALUE_MINUS_25_99 -21801993 // hz = -25.9899999999994 +#define IQ_F_VALUE_MINUS_25_98 -21793604 // hz = -25.9799999999994 +#define IQ_F_VALUE_MINUS_25_97 -21785215 // hz = -25.9699999999994 +#define IQ_F_VALUE_MINUS_25_96 -21776827 // hz = -25.9599999999994 +#define IQ_F_VALUE_MINUS_25_95 -21768438 // hz = -25.9499999999994 +#define IQ_F_VALUE_MINUS_25_94 -21760050 // hz = -25.9399999999994 +#define IQ_F_VALUE_MINUS_25_93 -21751661 // hz = -25.9299999999994 +#define IQ_F_VALUE_MINUS_25_92 -21743272 // hz = -25.9199999999994 +#define IQ_F_VALUE_MINUS_25_91 -21734884 // hz = -25.9099999999994 +#define IQ_F_VALUE_MINUS_25_90 -21726495 // hz = -25.8999999999994 +#define IQ_F_VALUE_MINUS_25_89 -21718107 // hz = -25.8899999999994 +#define IQ_F_VALUE_MINUS_25_88 -21709718 // hz = -25.8799999999994 +#define IQ_F_VALUE_MINUS_25_87 -21701329 // hz = -25.8699999999994 +#define IQ_F_VALUE_MINUS_25_86 -21692941 // hz = -25.8599999999993 +#define IQ_F_VALUE_MINUS_25_85 -21684552 // hz = -25.8499999999994 +#define IQ_F_VALUE_MINUS_25_84 -21676164 // hz = -25.8399999999993 +#define IQ_F_VALUE_MINUS_25_83 -21667775 // hz = -25.8299999999994 +#define IQ_F_VALUE_MINUS_25_82 -21659386 // hz = -25.8199999999994 +#define IQ_F_VALUE_MINUS_25_81 -21650998 // hz = -25.8099999999993 +#define IQ_F_VALUE_MINUS_25_80 -21642609 // hz = -25.7999999999993 +#define IQ_F_VALUE_MINUS_25_79 -21634221 // hz = -25.7899999999993 +#define IQ_F_VALUE_MINUS_25_78 -21625832 // hz = -25.7799999999993 +#define IQ_F_VALUE_MINUS_25_77 -21617443 // hz = -25.7699999999993 +#define IQ_F_VALUE_MINUS_25_76 -21609055 // hz = -25.7599999999993 +#define IQ_F_VALUE_MINUS_25_75 -21600666 // hz = -25.7499999999993 +#define IQ_F_VALUE_MINUS_25_74 -21592277 // hz = -25.7399999999993 +#define IQ_F_VALUE_MINUS_25_73 -21583889 // hz = -25.7299999999993 +#define IQ_F_VALUE_MINUS_25_72 -21575500 // hz = -25.7199999999993 +#define IQ_F_VALUE_MINUS_25_71 -21567112 // hz = -25.7099999999993 +#define IQ_F_VALUE_MINUS_25_70 -21558723 // hz = -25.6999999999993 +#define IQ_F_VALUE_MINUS_25_69 -21550334 // hz = -25.6899999999993 +#define IQ_F_VALUE_MINUS_25_68 -21541946 // hz = -25.6799999999993 +#define IQ_F_VALUE_MINUS_25_67 -21533557 // hz = -25.6699999999993 +#define IQ_F_VALUE_MINUS_25_66 -21525169 // hz = -25.6599999999993 +#define IQ_F_VALUE_MINUS_25_65 -21516780 // hz = -25.6499999999993 +#define IQ_F_VALUE_MINUS_25_64 -21508391 // hz = -25.6399999999993 +#define IQ_F_VALUE_MINUS_25_63 -21500003 // hz = -25.6299999999993 +#define IQ_F_VALUE_MINUS_25_62 -21491614 // hz = -25.6199999999993 +#define IQ_F_VALUE_MINUS_25_61 -21483226 // hz = -25.6099999999993 +#define IQ_F_VALUE_MINUS_25_60 -21474837 // hz = -25.5999999999993 +#define IQ_F_VALUE_MINUS_25_59 -21466448 // hz = -25.5899999999993 +#define IQ_F_VALUE_MINUS_25_58 -21458060 // hz = -25.5799999999993 +#define IQ_F_VALUE_MINUS_25_57 -21449671 // hz = -25.5699999999993 +#define IQ_F_VALUE_MINUS_25_56 -21441283 // hz = -25.5599999999993 +#define IQ_F_VALUE_MINUS_25_55 -21432894 // hz = -25.5499999999993 +#define IQ_F_VALUE_MINUS_25_54 -21424505 // hz = -25.5399999999993 +#define IQ_F_VALUE_MINUS_25_53 -21416117 // hz = -25.5299999999993 +#define IQ_F_VALUE_MINUS_25_52 -21407728 // hz = -25.5199999999993 +#define IQ_F_VALUE_MINUS_25_51 -21399340 // hz = -25.5099999999993 +#define IQ_F_VALUE_MINUS_25_50 -21390951 // hz = -25.4999999999993 +#define IQ_F_VALUE_MINUS_25_49 -21382562 // hz = -25.4899999999993 +#define IQ_F_VALUE_MINUS_25_48 -21374174 // hz = -25.4799999999993 +#define IQ_F_VALUE_MINUS_25_47 -21365785 // hz = -25.4699999999993 +#define IQ_F_VALUE_MINUS_25_46 -21357396 // hz = -25.4599999999993 +#define IQ_F_VALUE_MINUS_25_45 -21349008 // hz = -25.4499999999993 +#define IQ_F_VALUE_MINUS_25_44 -21340619 // hz = -25.4399999999993 +#define IQ_F_VALUE_MINUS_25_43 -21332231 // hz = -25.4299999999993 +#define IQ_F_VALUE_MINUS_25_42 -21323842 // hz = -25.4199999999993 +#define IQ_F_VALUE_MINUS_25_41 -21315453 // hz = -25.4099999999993 +#define IQ_F_VALUE_MINUS_25_40 -21307065 // hz = -25.3999999999993 +#define IQ_F_VALUE_MINUS_25_39 -21298676 // hz = -25.3899999999993 +#define IQ_F_VALUE_MINUS_25_38 -21290288 // hz = -25.3799999999993 +#define IQ_F_VALUE_MINUS_25_37 -21281899 // hz = -25.3699999999993 +#define IQ_F_VALUE_MINUS_25_36 -21273510 // hz = -25.3599999999993 +#define IQ_F_VALUE_MINUS_25_35 -21265122 // hz = -25.3499999999993 +#define IQ_F_VALUE_MINUS_25_34 -21256733 // hz = -25.3399999999993 +#define IQ_F_VALUE_MINUS_25_33 -21248345 // hz = -25.3299999999993 +#define IQ_F_VALUE_MINUS_25_32 -21239956 // hz = -25.3199999999993 +#define IQ_F_VALUE_MINUS_25_31 -21231567 // hz = -25.3099999999993 +#define IQ_F_VALUE_MINUS_25_30 -21223179 // hz = -25.2999999999993 +#define IQ_F_VALUE_MINUS_25_29 -21214790 // hz = -25.2899999999993 +#define IQ_F_VALUE_MINUS_25_28 -21206402 // hz = -25.2799999999993 +#define IQ_F_VALUE_MINUS_25_27 -21198013 // hz = -25.2699999999993 +#define IQ_F_VALUE_MINUS_25_26 -21189624 // hz = -25.2599999999993 +#define IQ_F_VALUE_MINUS_25_25 -21181236 // hz = -25.2499999999993 +#define IQ_F_VALUE_MINUS_25_24 -21172847 // hz = -25.2399999999993 +#define IQ_F_VALUE_MINUS_25_23 -21164458 // hz = -25.2299999999993 +#define IQ_F_VALUE_MINUS_25_22 -21156070 // hz = -25.2199999999992 +#define IQ_F_VALUE_MINUS_25_21 -21147681 // hz = -25.2099999999993 +#define IQ_F_VALUE_MINUS_25_20 -21139293 // hz = -25.1999999999992 +#define IQ_F_VALUE_MINUS_25_19 -21130904 // hz = -25.1899999999993 +#define IQ_F_VALUE_MINUS_25_18 -21122515 // hz = -25.1799999999993 +#define IQ_F_VALUE_MINUS_25_17 -21114127 // hz = -25.1699999999992 +#define IQ_F_VALUE_MINUS_25_16 -21105738 // hz = -25.1599999999992 +#define IQ_F_VALUE_MINUS_25_15 -21097350 // hz = -25.1499999999992 +#define IQ_F_VALUE_MINUS_25_14 -21088961 // hz = -25.1399999999992 +#define IQ_F_VALUE_MINUS_25_13 -21080572 // hz = -25.1299999999992 +#define IQ_F_VALUE_MINUS_25_12 -21072184 // hz = -25.1199999999992 +#define IQ_F_VALUE_MINUS_25_11 -21063795 // hz = -25.1099999999992 +#define IQ_F_VALUE_MINUS_25_10 -21055407 // hz = -25.0999999999992 +#define IQ_F_VALUE_MINUS_25_09 -21047018 // hz = -25.0899999999992 +#define IQ_F_VALUE_MINUS_25_08 -21038629 // hz = -25.0799999999992 +#define IQ_F_VALUE_MINUS_25_07 -21030241 // hz = -25.0699999999992 +#define IQ_F_VALUE_MINUS_25_06 -21021852 // hz = -25.0599999999992 +#define IQ_F_VALUE_MINUS_25_05 -21013464 // hz = -25.0499999999992 +#define IQ_F_VALUE_MINUS_25_04 -21005075 // hz = -25.0399999999992 +#define IQ_F_VALUE_MINUS_25_03 -20996686 // hz = -25.0299999999992 +#define IQ_F_VALUE_MINUS_25_02 -20988298 // hz = -25.0199999999992 +#define IQ_F_VALUE_MINUS_25_01 -20979909 // hz = -25.0099999999992 +#define IQ_F_VALUE_MINUS_25_00 -20971520 // hz = -24.9999999999992 +#define IQ_F_VALUE_MINUS_24_99 -20963132 // hz = -24.9899999999992 +#define IQ_F_VALUE_MINUS_24_98 -20954743 // hz = -24.9799999999992 +#define IQ_F_VALUE_MINUS_24_97 -20946355 // hz = -24.9699999999992 +#define IQ_F_VALUE_MINUS_24_96 -20937966 // hz = -24.9599999999992 +#define IQ_F_VALUE_MINUS_24_95 -20929577 // hz = -24.9499999999992 +#define IQ_F_VALUE_MINUS_24_94 -20921189 // hz = -24.9399999999992 +#define IQ_F_VALUE_MINUS_24_93 -20912800 // hz = -24.9299999999992 +#define IQ_F_VALUE_MINUS_24_92 -20904412 // hz = -24.9199999999992 +#define IQ_F_VALUE_MINUS_24_91 -20896023 // hz = -24.9099999999992 +#define IQ_F_VALUE_MINUS_24_90 -20887634 // hz = -24.8999999999992 +#define IQ_F_VALUE_MINUS_24_89 -20879246 // hz = -24.8899999999992 +#define IQ_F_VALUE_MINUS_24_88 -20870857 // hz = -24.8799999999992 +#define IQ_F_VALUE_MINUS_24_87 -20862469 // hz = -24.8699999999992 +#define IQ_F_VALUE_MINUS_24_86 -20854080 // hz = -24.8599999999992 +#define IQ_F_VALUE_MINUS_24_85 -20845691 // hz = -24.8499999999992 +#define IQ_F_VALUE_MINUS_24_84 -20837303 // hz = -24.8399999999992 +#define IQ_F_VALUE_MINUS_24_83 -20828914 // hz = -24.8299999999992 +#define IQ_F_VALUE_MINUS_24_82 -20820526 // hz = -24.8199999999992 +#define IQ_F_VALUE_MINUS_24_81 -20812137 // hz = -24.8099999999992 +#define IQ_F_VALUE_MINUS_24_80 -20803748 // hz = -24.7999999999992 +#define IQ_F_VALUE_MINUS_24_79 -20795360 // hz = -24.7899999999992 +#define IQ_F_VALUE_MINUS_24_78 -20786971 // hz = -24.7799999999992 +#define IQ_F_VALUE_MINUS_24_77 -20778583 // hz = -24.7699999999992 +#define IQ_F_VALUE_MINUS_24_76 -20770194 // hz = -24.7599999999992 +#define IQ_F_VALUE_MINUS_24_75 -20761805 // hz = -24.7499999999992 +#define IQ_F_VALUE_MINUS_24_74 -20753417 // hz = -24.7399999999992 +#define IQ_F_VALUE_MINUS_24_73 -20745028 // hz = -24.7299999999992 +#define IQ_F_VALUE_MINUS_24_72 -20736639 // hz = -24.7199999999992 +#define IQ_F_VALUE_MINUS_24_71 -20728251 // hz = -24.7099999999992 +#define IQ_F_VALUE_MINUS_24_70 -20719862 // hz = -24.6999999999992 +#define IQ_F_VALUE_MINUS_24_69 -20711474 // hz = -24.6899999999992 +#define IQ_F_VALUE_MINUS_24_68 -20703085 // hz = -24.6799999999992 +#define IQ_F_VALUE_MINUS_24_67 -20694696 // hz = -24.6699999999992 +#define IQ_F_VALUE_MINUS_24_66 -20686308 // hz = -24.6599999999992 +#define IQ_F_VALUE_MINUS_24_65 -20677919 // hz = -24.6499999999992 +#define IQ_F_VALUE_MINUS_24_64 -20669531 // hz = -24.6399999999992 +#define IQ_F_VALUE_MINUS_24_63 -20661142 // hz = -24.6299999999992 +#define IQ_F_VALUE_MINUS_24_62 -20652753 // hz = -24.6199999999992 +#define IQ_F_VALUE_MINUS_24_61 -20644365 // hz = -24.6099999999992 +#define IQ_F_VALUE_MINUS_24_60 -20635976 // hz = -24.5999999999992 +#define IQ_F_VALUE_MINUS_24_59 -20627588 // hz = -24.5899999999992 +#define IQ_F_VALUE_MINUS_24_58 -20619199 // hz = -24.5799999999991 +#define IQ_F_VALUE_MINUS_24_57 -20610810 // hz = -24.5699999999992 +#define IQ_F_VALUE_MINUS_24_56 -20602422 // hz = -24.5599999999991 +#define IQ_F_VALUE_MINUS_24_55 -20594033 // hz = -24.5499999999992 +#define IQ_F_VALUE_MINUS_24_54 -20585645 // hz = -24.5399999999992 +#define IQ_F_VALUE_MINUS_24_53 -20577256 // hz = -24.5299999999991 +#define IQ_F_VALUE_MINUS_24_52 -20568867 // hz = -24.5199999999991 +#define IQ_F_VALUE_MINUS_24_51 -20560479 // hz = -24.5099999999991 +#define IQ_F_VALUE_MINUS_24_50 -20552090 // hz = -24.4999999999991 +#define IQ_F_VALUE_MINUS_24_49 -20543701 // hz = -24.4899999999991 +#define IQ_F_VALUE_MINUS_24_48 -20535313 // hz = -24.4799999999991 +#define IQ_F_VALUE_MINUS_24_47 -20526924 // hz = -24.4699999999991 +#define IQ_F_VALUE_MINUS_24_46 -20518536 // hz = -24.4599999999991 +#define IQ_F_VALUE_MINUS_24_45 -20510147 // hz = -24.4499999999991 +#define IQ_F_VALUE_MINUS_24_44 -20501758 // hz = -24.4399999999991 +#define IQ_F_VALUE_MINUS_24_43 -20493370 // hz = -24.4299999999991 +#define IQ_F_VALUE_MINUS_24_42 -20484981 // hz = -24.4199999999991 +#define IQ_F_VALUE_MINUS_24_41 -20476593 // hz = -24.4099999999991 +#define IQ_F_VALUE_MINUS_24_40 -20468204 // hz = -24.3999999999991 +#define IQ_F_VALUE_MINUS_24_39 -20459815 // hz = -24.3899999999991 +#define IQ_F_VALUE_MINUS_24_38 -20451427 // hz = -24.3799999999991 +#define IQ_F_VALUE_MINUS_24_37 -20443038 // hz = -24.3699999999991 +#define IQ_F_VALUE_MINUS_24_36 -20434650 // hz = -24.3599999999991 +#define IQ_F_VALUE_MINUS_24_35 -20426261 // hz = -24.3499999999991 +#define IQ_F_VALUE_MINUS_24_34 -20417872 // hz = -24.3399999999991 +#define IQ_F_VALUE_MINUS_24_33 -20409484 // hz = -24.3299999999991 +#define IQ_F_VALUE_MINUS_24_32 -20401095 // hz = -24.3199999999991 +#define IQ_F_VALUE_MINUS_24_31 -20392707 // hz = -24.3099999999991 +#define IQ_F_VALUE_MINUS_24_30 -20384318 // hz = -24.2999999999991 +#define IQ_F_VALUE_MINUS_24_29 -20375929 // hz = -24.2899999999991 +#define IQ_F_VALUE_MINUS_24_28 -20367541 // hz = -24.2799999999991 +#define IQ_F_VALUE_MINUS_24_27 -20359152 // hz = -24.2699999999991 +#define IQ_F_VALUE_MINUS_24_26 -20350764 // hz = -24.2599999999991 +#define IQ_F_VALUE_MINUS_24_25 -20342375 // hz = -24.2499999999991 +#define IQ_F_VALUE_MINUS_24_24 -20333986 // hz = -24.2399999999991 +#define IQ_F_VALUE_MINUS_24_23 -20325598 // hz = -24.2299999999991 +#define IQ_F_VALUE_MINUS_24_22 -20317209 // hz = -24.2199999999991 +#define IQ_F_VALUE_MINUS_24_21 -20308820 // hz = -24.2099999999991 +#define IQ_F_VALUE_MINUS_24_20 -20300432 // hz = -24.1999999999991 +#define IQ_F_VALUE_MINUS_24_19 -20292043 // hz = -24.1899999999991 +#define IQ_F_VALUE_MINUS_24_18 -20283655 // hz = -24.1799999999991 +#define IQ_F_VALUE_MINUS_24_17 -20275266 // hz = -24.1699999999991 +#define IQ_F_VALUE_MINUS_24_16 -20266877 // hz = -24.1599999999991 +#define IQ_F_VALUE_MINUS_24_15 -20258489 // hz = -24.1499999999991 +#define IQ_F_VALUE_MINUS_24_14 -20250100 // hz = -24.1399999999991 +#define IQ_F_VALUE_MINUS_24_13 -20241712 // hz = -24.1299999999991 +#define IQ_F_VALUE_MINUS_24_12 -20233323 // hz = -24.1199999999991 +#define IQ_F_VALUE_MINUS_24_11 -20224934 // hz = -24.1099999999991 +#define IQ_F_VALUE_MINUS_24_10 -20216546 // hz = -24.0999999999991 +#define IQ_F_VALUE_MINUS_24_09 -20208157 // hz = -24.0899999999991 +#define IQ_F_VALUE_MINUS_24_08 -20199769 // hz = -24.0799999999991 +#define IQ_F_VALUE_MINUS_24_07 -20191380 // hz = -24.0699999999991 +#define IQ_F_VALUE_MINUS_24_06 -20182991 // hz = -24.0599999999991 +#define IQ_F_VALUE_MINUS_24_05 -20174603 // hz = -24.0499999999991 +#define IQ_F_VALUE_MINUS_24_04 -20166214 // hz = -24.0399999999991 +#define IQ_F_VALUE_MINUS_24_03 -20157826 // hz = -24.0299999999991 +#define IQ_F_VALUE_MINUS_24_02 -20149437 // hz = -24.0199999999991 +#define IQ_F_VALUE_MINUS_24_01 -20141048 // hz = -24.0099999999991 +#define IQ_F_VALUE_MINUS_24_00 -20132660 // hz = -23.9999999999991 +#define IQ_F_VALUE_MINUS_23_99 -20124271 // hz = -23.9899999999991 +#define IQ_F_VALUE_MINUS_23_98 -20115882 // hz = -23.9799999999991 +#define IQ_F_VALUE_MINUS_23_97 -20107494 // hz = -23.9699999999991 +#define IQ_F_VALUE_MINUS_23_96 -20099105 // hz = -23.9599999999991 +#define IQ_F_VALUE_MINUS_23_95 -20090717 // hz = -23.9499999999991 +#define IQ_F_VALUE_MINUS_23_94 -20082328 // hz = -23.939999999999 +#define IQ_F_VALUE_MINUS_23_93 -20073939 // hz = -23.9299999999991 +#define IQ_F_VALUE_MINUS_23_92 -20065551 // hz = -23.919999999999 +#define IQ_F_VALUE_MINUS_23_91 -20057162 // hz = -23.9099999999991 +#define IQ_F_VALUE_MINUS_23_90 -20048774 // hz = -23.8999999999991 +#define IQ_F_VALUE_MINUS_23_89 -20040385 // hz = -23.889999999999 +#define IQ_F_VALUE_MINUS_23_88 -20031996 // hz = -23.879999999999 +#define IQ_F_VALUE_MINUS_23_87 -20023608 // hz = -23.869999999999 +#define IQ_F_VALUE_MINUS_23_86 -20015219 // hz = -23.859999999999 +#define IQ_F_VALUE_MINUS_23_85 -20006831 // hz = -23.849999999999 +#define IQ_F_VALUE_MINUS_23_84 -19998442 // hz = -23.839999999999 +#define IQ_F_VALUE_MINUS_23_83 -19990053 // hz = -23.829999999999 +#define IQ_F_VALUE_MINUS_23_82 -19981665 // hz = -23.819999999999 +#define IQ_F_VALUE_MINUS_23_81 -19973276 // hz = -23.809999999999 +#define IQ_F_VALUE_MINUS_23_80 -19964888 // hz = -23.799999999999 +#define IQ_F_VALUE_MINUS_23_79 -19956499 // hz = -23.789999999999 +#define IQ_F_VALUE_MINUS_23_78 -19948110 // hz = -23.779999999999 +#define IQ_F_VALUE_MINUS_23_77 -19939722 // hz = -23.769999999999 +#define IQ_F_VALUE_MINUS_23_76 -19931333 // hz = -23.759999999999 +#define IQ_F_VALUE_MINUS_23_75 -19922944 // hz = -23.749999999999 +#define IQ_F_VALUE_MINUS_23_74 -19914556 // hz = -23.739999999999 +#define IQ_F_VALUE_MINUS_23_73 -19906167 // hz = -23.729999999999 +#define IQ_F_VALUE_MINUS_23_72 -19897779 // hz = -23.719999999999 +#define IQ_F_VALUE_MINUS_23_71 -19889390 // hz = -23.709999999999 +#define IQ_F_VALUE_MINUS_23_70 -19881001 // hz = -23.699999999999 +#define IQ_F_VALUE_MINUS_23_69 -19872613 // hz = -23.689999999999 +#define IQ_F_VALUE_MINUS_23_68 -19864224 // hz = -23.679999999999 +#define IQ_F_VALUE_MINUS_23_67 -19855836 // hz = -23.669999999999 +#define IQ_F_VALUE_MINUS_23_66 -19847447 // hz = -23.659999999999 +#define IQ_F_VALUE_MINUS_23_65 -19839058 // hz = -23.649999999999 +#define IQ_F_VALUE_MINUS_23_64 -19830670 // hz = -23.639999999999 +#define IQ_F_VALUE_MINUS_23_63 -19822281 // hz = -23.629999999999 +#define IQ_F_VALUE_MINUS_23_62 -19813893 // hz = -23.619999999999 +#define IQ_F_VALUE_MINUS_23_61 -19805504 // hz = -23.609999999999 +#define IQ_F_VALUE_MINUS_23_60 -19797115 // hz = -23.599999999999 +#define IQ_F_VALUE_MINUS_23_59 -19788727 // hz = -23.589999999999 +#define IQ_F_VALUE_MINUS_23_58 -19780338 // hz = -23.579999999999 +#define IQ_F_VALUE_MINUS_23_57 -19771950 // hz = -23.569999999999 +#define IQ_F_VALUE_MINUS_23_56 -19763561 // hz = -23.559999999999 +#define IQ_F_VALUE_MINUS_23_55 -19755172 // hz = -23.549999999999 +#define IQ_F_VALUE_MINUS_23_54 -19746784 // hz = -23.539999999999 +#define IQ_F_VALUE_MINUS_23_53 -19738395 // hz = -23.529999999999 +#define IQ_F_VALUE_MINUS_23_52 -19730007 // hz = -23.519999999999 +#define IQ_F_VALUE_MINUS_23_51 -19721618 // hz = -23.509999999999 +#define IQ_F_VALUE_MINUS_23_50 -19713229 // hz = -23.499999999999 +#define IQ_F_VALUE_MINUS_23_49 -19704841 // hz = -23.489999999999 +#define IQ_F_VALUE_MINUS_23_48 -19696452 // hz = -23.479999999999 +#define IQ_F_VALUE_MINUS_23_47 -19688063 // hz = -23.469999999999 +#define IQ_F_VALUE_MINUS_23_46 -19679675 // hz = -23.459999999999 +#define IQ_F_VALUE_MINUS_23_45 -19671286 // hz = -23.449999999999 +#define IQ_F_VALUE_MINUS_23_44 -19662898 // hz = -23.439999999999 +#define IQ_F_VALUE_MINUS_23_43 -19654509 // hz = -23.429999999999 +#define IQ_F_VALUE_MINUS_23_42 -19646120 // hz = -23.419999999999 +#define IQ_F_VALUE_MINUS_23_41 -19637732 // hz = -23.409999999999 +#define IQ_F_VALUE_MINUS_23_40 -19629343 // hz = -23.399999999999 +#define IQ_F_VALUE_MINUS_23_39 -19620955 // hz = -23.389999999999 +#define IQ_F_VALUE_MINUS_23_38 -19612566 // hz = -23.379999999999 +#define IQ_F_VALUE_MINUS_23_37 -19604177 // hz = -23.369999999999 +#define IQ_F_VALUE_MINUS_23_36 -19595789 // hz = -23.359999999999 +#define IQ_F_VALUE_MINUS_23_35 -19587400 // hz = -23.349999999999 +#define IQ_F_VALUE_MINUS_23_34 -19579012 // hz = -23.339999999999 +#define IQ_F_VALUE_MINUS_23_33 -19570623 // hz = -23.329999999999 +#define IQ_F_VALUE_MINUS_23_32 -19562234 // hz = -23.319999999999 +#define IQ_F_VALUE_MINUS_23_31 -19553846 // hz = -23.309999999999 +#define IQ_F_VALUE_MINUS_23_30 -19545457 // hz = -23.2999999999989 +#define IQ_F_VALUE_MINUS_23_29 -19537069 // hz = -23.289999999999 +#define IQ_F_VALUE_MINUS_23_28 -19528680 // hz = -23.2799999999989 +#define IQ_F_VALUE_MINUS_23_27 -19520291 // hz = -23.269999999999 +#define IQ_F_VALUE_MINUS_23_26 -19511903 // hz = -23.2599999999989 +#define IQ_F_VALUE_MINUS_23_25 -19503514 // hz = -23.2499999999989 +#define IQ_F_VALUE_MINUS_23_24 -19495125 // hz = -23.2399999999989 +#define IQ_F_VALUE_MINUS_23_23 -19486737 // hz = -23.2299999999989 +#define IQ_F_VALUE_MINUS_23_22 -19478348 // hz = -23.2199999999989 +#define IQ_F_VALUE_MINUS_23_21 -19469960 // hz = -23.2099999999989 +#define IQ_F_VALUE_MINUS_23_20 -19461571 // hz = -23.1999999999989 +#define IQ_F_VALUE_MINUS_23_19 -19453182 // hz = -23.1899999999989 +#define IQ_F_VALUE_MINUS_23_18 -19444794 // hz = -23.1799999999989 +#define IQ_F_VALUE_MINUS_23_17 -19436405 // hz = -23.1699999999989 +#define IQ_F_VALUE_MINUS_23_16 -19428017 // hz = -23.1599999999989 +#define IQ_F_VALUE_MINUS_23_15 -19419628 // hz = -23.1499999999989 +#define IQ_F_VALUE_MINUS_23_14 -19411239 // hz = -23.1399999999989 +#define IQ_F_VALUE_MINUS_23_13 -19402851 // hz = -23.1299999999989 +#define IQ_F_VALUE_MINUS_23_12 -19394462 // hz = -23.1199999999989 +#define IQ_F_VALUE_MINUS_23_11 -19386074 // hz = -23.1099999999989 +#define IQ_F_VALUE_MINUS_23_10 -19377685 // hz = -23.0999999999989 +#define IQ_F_VALUE_MINUS_23_09 -19369296 // hz = -23.0899999999989 +#define IQ_F_VALUE_MINUS_23_08 -19360908 // hz = -23.0799999999989 +#define IQ_F_VALUE_MINUS_23_07 -19352519 // hz = -23.0699999999989 +#define IQ_F_VALUE_MINUS_23_06 -19344131 // hz = -23.0599999999989 +#define IQ_F_VALUE_MINUS_23_05 -19335742 // hz = -23.0499999999989 +#define IQ_F_VALUE_MINUS_23_04 -19327353 // hz = -23.0399999999989 +#define IQ_F_VALUE_MINUS_23_03 -19318965 // hz = -23.0299999999989 +#define IQ_F_VALUE_MINUS_23_02 -19310576 // hz = -23.0199999999989 +#define IQ_F_VALUE_MINUS_23_01 -19302188 // hz = -23.0099999999989 +#define IQ_F_VALUE_MINUS_23_00 -19293799 // hz = -22.9999999999989 +#define IQ_F_VALUE_MINUS_22_99 -19285410 // hz = -22.9899999999989 +#define IQ_F_VALUE_MINUS_22_98 -19277022 // hz = -22.9799999999989 +#define IQ_F_VALUE_MINUS_22_97 -19268633 // hz = -22.9699999999989 +#define IQ_F_VALUE_MINUS_22_96 -19260244 // hz = -22.9599999999989 +#define IQ_F_VALUE_MINUS_22_95 -19251856 // hz = -22.9499999999989 +#define IQ_F_VALUE_MINUS_22_94 -19243467 // hz = -22.9399999999989 +#define IQ_F_VALUE_MINUS_22_93 -19235079 // hz = -22.9299999999989 +#define IQ_F_VALUE_MINUS_22_92 -19226690 // hz = -22.9199999999989 +#define IQ_F_VALUE_MINUS_22_91 -19218301 // hz = -22.9099999999989 +#define IQ_F_VALUE_MINUS_22_90 -19209913 // hz = -22.8999999999989 +#define IQ_F_VALUE_MINUS_22_89 -19201524 // hz = -22.8899999999989 +#define IQ_F_VALUE_MINUS_22_88 -19193136 // hz = -22.8799999999989 +#define IQ_F_VALUE_MINUS_22_87 -19184747 // hz = -22.8699999999989 +#define IQ_F_VALUE_MINUS_22_86 -19176358 // hz = -22.8599999999989 +#define IQ_F_VALUE_MINUS_22_85 -19167970 // hz = -22.8499999999989 +#define IQ_F_VALUE_MINUS_22_84 -19159581 // hz = -22.8399999999989 +#define IQ_F_VALUE_MINUS_22_83 -19151193 // hz = -22.8299999999989 +#define IQ_F_VALUE_MINUS_22_82 -19142804 // hz = -22.8199999999989 +#define IQ_F_VALUE_MINUS_22_81 -19134415 // hz = -22.8099999999989 +#define IQ_F_VALUE_MINUS_22_80 -19126027 // hz = -22.7999999999989 +#define IQ_F_VALUE_MINUS_22_79 -19117638 // hz = -22.7899999999989 +#define IQ_F_VALUE_MINUS_22_78 -19109250 // hz = -22.7799999999989 +#define IQ_F_VALUE_MINUS_22_77 -19100861 // hz = -22.7699999999989 +#define IQ_F_VALUE_MINUS_22_76 -19092472 // hz = -22.7599999999989 +#define IQ_F_VALUE_MINUS_22_75 -19084084 // hz = -22.7499999999989 +#define IQ_F_VALUE_MINUS_22_74 -19075695 // hz = -22.7399999999989 +#define IQ_F_VALUE_MINUS_22_73 -19067306 // hz = -22.7299999999989 +#define IQ_F_VALUE_MINUS_22_72 -19058918 // hz = -22.7199999999989 +#define IQ_F_VALUE_MINUS_22_71 -19050529 // hz = -22.7099999999989 +#define IQ_F_VALUE_MINUS_22_70 -19042141 // hz = -22.6999999999989 +#define IQ_F_VALUE_MINUS_22_69 -19033752 // hz = -22.6899999999989 +#define IQ_F_VALUE_MINUS_22_68 -19025363 // hz = -22.6799999999989 +#define IQ_F_VALUE_MINUS_22_67 -19016975 // hz = -22.6699999999989 +#define IQ_F_VALUE_MINUS_22_66 -19008586 // hz = -22.6599999999988 +#define IQ_F_VALUE_MINUS_22_65 -19000198 // hz = -22.6499999999989 +#define IQ_F_VALUE_MINUS_22_64 -18991809 // hz = -22.6399999999988 +#define IQ_F_VALUE_MINUS_22_63 -18983420 // hz = -22.6299999999989 +#define IQ_F_VALUE_MINUS_22_62 -18975032 // hz = -22.6199999999988 +#define IQ_F_VALUE_MINUS_22_61 -18966643 // hz = -22.6099999999988 +#define IQ_F_VALUE_MINUS_22_60 -18958255 // hz = -22.5999999999988 +#define IQ_F_VALUE_MINUS_22_59 -18949866 // hz = -22.5899999999988 +#define IQ_F_VALUE_MINUS_22_58 -18941477 // hz = -22.5799999999988 +#define IQ_F_VALUE_MINUS_22_57 -18933089 // hz = -22.5699999999988 +#define IQ_F_VALUE_MINUS_22_56 -18924700 // hz = -22.5599999999988 +#define IQ_F_VALUE_MINUS_22_55 -18916312 // hz = -22.5499999999988 +#define IQ_F_VALUE_MINUS_22_54 -18907923 // hz = -22.5399999999988 +#define IQ_F_VALUE_MINUS_22_53 -18899534 // hz = -22.5299999999988 +#define IQ_F_VALUE_MINUS_22_52 -18891146 // hz = -22.5199999999988 +#define IQ_F_VALUE_MINUS_22_51 -18882757 // hz = -22.5099999999988 +#define IQ_F_VALUE_MINUS_22_50 -18874368 // hz = -22.4999999999988 +#define IQ_F_VALUE_MINUS_22_49 -18865980 // hz = -22.4899999999988 +#define IQ_F_VALUE_MINUS_22_48 -18857591 // hz = -22.4799999999988 +#define IQ_F_VALUE_MINUS_22_47 -18849203 // hz = -22.4699999999988 +#define IQ_F_VALUE_MINUS_22_46 -18840814 // hz = -22.4599999999988 +#define IQ_F_VALUE_MINUS_22_45 -18832425 // hz = -22.4499999999988 +#define IQ_F_VALUE_MINUS_22_44 -18824037 // hz = -22.4399999999988 +#define IQ_F_VALUE_MINUS_22_43 -18815648 // hz = -22.4299999999988 +#define IQ_F_VALUE_MINUS_22_42 -18807260 // hz = -22.4199999999988 +#define IQ_F_VALUE_MINUS_22_41 -18798871 // hz = -22.4099999999988 +#define IQ_F_VALUE_MINUS_22_40 -18790482 // hz = -22.3999999999988 +#define IQ_F_VALUE_MINUS_22_39 -18782094 // hz = -22.3899999999988 +#define IQ_F_VALUE_MINUS_22_38 -18773705 // hz = -22.3799999999988 +#define IQ_F_VALUE_MINUS_22_37 -18765317 // hz = -22.3699999999988 +#define IQ_F_VALUE_MINUS_22_36 -18756928 // hz = -22.3599999999988 +#define IQ_F_VALUE_MINUS_22_35 -18748539 // hz = -22.3499999999988 +#define IQ_F_VALUE_MINUS_22_34 -18740151 // hz = -22.3399999999988 +#define IQ_F_VALUE_MINUS_22_33 -18731762 // hz = -22.3299999999988 +#define IQ_F_VALUE_MINUS_22_32 -18723374 // hz = -22.3199999999988 +#define IQ_F_VALUE_MINUS_22_31 -18714985 // hz = -22.3099999999988 +#define IQ_F_VALUE_MINUS_22_30 -18706596 // hz = -22.2999999999988 +#define IQ_F_VALUE_MINUS_22_29 -18698208 // hz = -22.2899999999988 +#define IQ_F_VALUE_MINUS_22_28 -18689819 // hz = -22.2799999999988 +#define IQ_F_VALUE_MINUS_22_27 -18681431 // hz = -22.2699999999988 +#define IQ_F_VALUE_MINUS_22_26 -18673042 // hz = -22.2599999999988 +#define IQ_F_VALUE_MINUS_22_25 -18664653 // hz = -22.2499999999988 +#define IQ_F_VALUE_MINUS_22_24 -18656265 // hz = -22.2399999999988 +#define IQ_F_VALUE_MINUS_22_23 -18647876 // hz = -22.2299999999988 +#define IQ_F_VALUE_MINUS_22_22 -18639487 // hz = -22.2199999999988 +#define IQ_F_VALUE_MINUS_22_21 -18631099 // hz = -22.2099999999988 +#define IQ_F_VALUE_MINUS_22_20 -18622710 // hz = -22.1999999999988 +#define IQ_F_VALUE_MINUS_22_19 -18614322 // hz = -22.1899999999988 +#define IQ_F_VALUE_MINUS_22_18 -18605933 // hz = -22.1799999999988 +#define IQ_F_VALUE_MINUS_22_17 -18597544 // hz = -22.1699999999988 +#define IQ_F_VALUE_MINUS_22_16 -18589156 // hz = -22.1599999999988 +#define IQ_F_VALUE_MINUS_22_15 -18580767 // hz = -22.1499999999988 +#define IQ_F_VALUE_MINUS_22_14 -18572379 // hz = -22.1399999999988 +#define IQ_F_VALUE_MINUS_22_13 -18563990 // hz = -22.1299999999988 +#define IQ_F_VALUE_MINUS_22_12 -18555601 // hz = -22.1199999999988 +#define IQ_F_VALUE_MINUS_22_11 -18547213 // hz = -22.1099999999988 +#define IQ_F_VALUE_MINUS_22_10 -18538824 // hz = -22.0999999999988 +#define IQ_F_VALUE_MINUS_22_09 -18530436 // hz = -22.0899999999988 +#define IQ_F_VALUE_MINUS_22_08 -18522047 // hz = -22.0799999999988 +#define IQ_F_VALUE_MINUS_22_07 -18513658 // hz = -22.0699999999988 +#define IQ_F_VALUE_MINUS_22_06 -18505270 // hz = -22.0599999999988 +#define IQ_F_VALUE_MINUS_22_05 -18496881 // hz = -22.0499999999988 +#define IQ_F_VALUE_MINUS_22_04 -18488493 // hz = -22.0399999999988 +#define IQ_F_VALUE_MINUS_22_03 -18480104 // hz = -22.0299999999988 +#define IQ_F_VALUE_MINUS_22_02 -18471715 // hz = -22.0199999999987 +#define IQ_F_VALUE_MINUS_22_01 -18463327 // hz = -22.0099999999988 +#define IQ_F_VALUE_MINUS_22_00 -18454938 // hz = -21.9999999999987 +#define IQ_F_VALUE_MINUS_21_99 -18446549 // hz = -21.9899999999988 +#define IQ_F_VALUE_MINUS_21_98 -18438161 // hz = -21.9799999999987 +#define IQ_F_VALUE_MINUS_21_97 -18429772 // hz = -21.9699999999987 +#define IQ_F_VALUE_MINUS_21_96 -18421384 // hz = -21.9599999999987 +#define IQ_F_VALUE_MINUS_21_95 -18412995 // hz = -21.9499999999987 +#define IQ_F_VALUE_MINUS_21_94 -18404606 // hz = -21.9399999999987 +#define IQ_F_VALUE_MINUS_21_93 -18396218 // hz = -21.9299999999987 +#define IQ_F_VALUE_MINUS_21_92 -18387829 // hz = -21.9199999999987 +#define IQ_F_VALUE_MINUS_21_91 -18379441 // hz = -21.9099999999987 +#define IQ_F_VALUE_MINUS_21_90 -18371052 // hz = -21.8999999999987 +#define IQ_F_VALUE_MINUS_21_89 -18362663 // hz = -21.8899999999987 +#define IQ_F_VALUE_MINUS_21_88 -18354275 // hz = -21.8799999999987 +#define IQ_F_VALUE_MINUS_21_87 -18345886 // hz = -21.8699999999987 +#define IQ_F_VALUE_MINUS_21_86 -18337498 // hz = -21.8599999999987 +#define IQ_F_VALUE_MINUS_21_85 -18329109 // hz = -21.8499999999987 +#define IQ_F_VALUE_MINUS_21_84 -18320720 // hz = -21.8399999999987 +#define IQ_F_VALUE_MINUS_21_83 -18312332 // hz = -21.8299999999987 +#define IQ_F_VALUE_MINUS_21_82 -18303943 // hz = -21.8199999999987 +#define IQ_F_VALUE_MINUS_21_81 -18295555 // hz = -21.8099999999987 +#define IQ_F_VALUE_MINUS_21_80 -18287166 // hz = -21.7999999999987 +#define IQ_F_VALUE_MINUS_21_79 -18278777 // hz = -21.7899999999987 +#define IQ_F_VALUE_MINUS_21_78 -18270389 // hz = -21.7799999999987 +#define IQ_F_VALUE_MINUS_21_77 -18262000 // hz = -21.7699999999987 +#define IQ_F_VALUE_MINUS_21_76 -18253612 // hz = -21.7599999999987 +#define IQ_F_VALUE_MINUS_21_75 -18245223 // hz = -21.7499999999987 +#define IQ_F_VALUE_MINUS_21_74 -18236834 // hz = -21.7399999999987 +#define IQ_F_VALUE_MINUS_21_73 -18228446 // hz = -21.7299999999987 +#define IQ_F_VALUE_MINUS_21_72 -18220057 // hz = -21.7199999999987 +#define IQ_F_VALUE_MINUS_21_71 -18211668 // hz = -21.7099999999987 +#define IQ_F_VALUE_MINUS_21_70 -18203280 // hz = -21.6999999999987 +#define IQ_F_VALUE_MINUS_21_69 -18194891 // hz = -21.6899999999987 +#define IQ_F_VALUE_MINUS_21_68 -18186503 // hz = -21.6799999999987 +#define IQ_F_VALUE_MINUS_21_67 -18178114 // hz = -21.6699999999987 +#define IQ_F_VALUE_MINUS_21_66 -18169725 // hz = -21.6599999999987 +#define IQ_F_VALUE_MINUS_21_65 -18161337 // hz = -21.6499999999987 +#define IQ_F_VALUE_MINUS_21_64 -18152948 // hz = -21.6399999999987 +#define IQ_F_VALUE_MINUS_21_63 -18144560 // hz = -21.6299999999987 +#define IQ_F_VALUE_MINUS_21_62 -18136171 // hz = -21.6199999999987 +#define IQ_F_VALUE_MINUS_21_61 -18127782 // hz = -21.6099999999987 +#define IQ_F_VALUE_MINUS_21_60 -18119394 // hz = -21.5999999999987 +#define IQ_F_VALUE_MINUS_21_59 -18111005 // hz = -21.5899999999987 +#define IQ_F_VALUE_MINUS_21_58 -18102617 // hz = -21.5799999999987 +#define IQ_F_VALUE_MINUS_21_57 -18094228 // hz = -21.5699999999987 +#define IQ_F_VALUE_MINUS_21_56 -18085839 // hz = -21.5599999999987 +#define IQ_F_VALUE_MINUS_21_55 -18077451 // hz = -21.5499999999987 +#define IQ_F_VALUE_MINUS_21_54 -18069062 // hz = -21.5399999999987 +#define IQ_F_VALUE_MINUS_21_53 -18060674 // hz = -21.5299999999987 +#define IQ_F_VALUE_MINUS_21_52 -18052285 // hz = -21.5199999999987 +#define IQ_F_VALUE_MINUS_21_51 -18043896 // hz = -21.5099999999987 +#define IQ_F_VALUE_MINUS_21_50 -18035508 // hz = -21.4999999999987 +#define IQ_F_VALUE_MINUS_21_49 -18027119 // hz = -21.4899999999987 +#define IQ_F_VALUE_MINUS_21_48 -18018730 // hz = -21.4799999999987 +#define IQ_F_VALUE_MINUS_21_47 -18010342 // hz = -21.4699999999987 +#define IQ_F_VALUE_MINUS_21_46 -18001953 // hz = -21.4599999999987 +#define IQ_F_VALUE_MINUS_21_45 -17993565 // hz = -21.4499999999987 +#define IQ_F_VALUE_MINUS_21_44 -17985176 // hz = -21.4399999999987 +#define IQ_F_VALUE_MINUS_21_43 -17976787 // hz = -21.4299999999987 +#define IQ_F_VALUE_MINUS_21_42 -17968399 // hz = -21.4199999999987 +#define IQ_F_VALUE_MINUS_21_41 -17960010 // hz = -21.4099999999987 +#define IQ_F_VALUE_MINUS_21_40 -17951622 // hz = -21.3999999999987 +#define IQ_F_VALUE_MINUS_21_39 -17943233 // hz = -21.3899999999987 +#define IQ_F_VALUE_MINUS_21_38 -17934844 // hz = -21.3799999999987 +#define IQ_F_VALUE_MINUS_21_37 -17926456 // hz = -21.3699999999986 +#define IQ_F_VALUE_MINUS_21_36 -17918067 // hz = -21.3599999999986 +#define IQ_F_VALUE_MINUS_21_35 -17909679 // hz = -21.3499999999987 +#define IQ_F_VALUE_MINUS_21_34 -17901290 // hz = -21.3399999999986 +#define IQ_F_VALUE_MINUS_21_33 -17892901 // hz = -21.3299999999986 +#define IQ_F_VALUE_MINUS_21_32 -17884513 // hz = -21.3199999999986 +#define IQ_F_VALUE_MINUS_21_31 -17876124 // hz = -21.3099999999986 +#define IQ_F_VALUE_MINUS_21_30 -17867736 // hz = -21.2999999999986 +#define IQ_F_VALUE_MINUS_21_29 -17859347 // hz = -21.2899999999986 +#define IQ_F_VALUE_MINUS_21_28 -17850958 // hz = -21.2799999999986 +#define IQ_F_VALUE_MINUS_21_27 -17842570 // hz = -21.2699999999986 +#define IQ_F_VALUE_MINUS_21_26 -17834181 // hz = -21.2599999999986 +#define IQ_F_VALUE_MINUS_21_25 -17825792 // hz = -21.2499999999986 +#define IQ_F_VALUE_MINUS_21_24 -17817404 // hz = -21.2399999999986 +#define IQ_F_VALUE_MINUS_21_23 -17809015 // hz = -21.2299999999986 +#define IQ_F_VALUE_MINUS_21_22 -17800627 // hz = -21.2199999999986 +#define IQ_F_VALUE_MINUS_21_21 -17792238 // hz = -21.2099999999986 +#define IQ_F_VALUE_MINUS_21_20 -17783849 // hz = -21.1999999999986 +#define IQ_F_VALUE_MINUS_21_19 -17775461 // hz = -21.1899999999986 +#define IQ_F_VALUE_MINUS_21_18 -17767072 // hz = -21.1799999999986 +#define IQ_F_VALUE_MINUS_21_17 -17758684 // hz = -21.1699999999986 +#define IQ_F_VALUE_MINUS_21_16 -17750295 // hz = -21.1599999999986 +#define IQ_F_VALUE_MINUS_21_15 -17741906 // hz = -21.1499999999986 +#define IQ_F_VALUE_MINUS_21_14 -17733518 // hz = -21.1399999999986 +#define IQ_F_VALUE_MINUS_21_13 -17725129 // hz = -21.1299999999986 +#define IQ_F_VALUE_MINUS_21_12 -17716741 // hz = -21.1199999999986 +#define IQ_F_VALUE_MINUS_21_11 -17708352 // hz = -21.1099999999986 +#define IQ_F_VALUE_MINUS_21_10 -17699963 // hz = -21.0999999999986 +#define IQ_F_VALUE_MINUS_21_09 -17691575 // hz = -21.0899999999986 +#define IQ_F_VALUE_MINUS_21_08 -17683186 // hz = -21.0799999999986 +#define IQ_F_VALUE_MINUS_21_07 -17674798 // hz = -21.0699999999986 +#define IQ_F_VALUE_MINUS_21_06 -17666409 // hz = -21.0599999999986 +#define IQ_F_VALUE_MINUS_21_05 -17658020 // hz = -21.0499999999986 +#define IQ_F_VALUE_MINUS_21_04 -17649632 // hz = -21.0399999999986 +#define IQ_F_VALUE_MINUS_21_03 -17641243 // hz = -21.0299999999986 +#define IQ_F_VALUE_MINUS_21_02 -17632855 // hz = -21.0199999999986 +#define IQ_F_VALUE_MINUS_21_01 -17624466 // hz = -21.0099999999986 +#define IQ_F_VALUE_MINUS_21_00 -17616077 // hz = -20.9999999999986 +#define IQ_F_VALUE_MINUS_20_99 -17607689 // hz = -20.9899999999986 +#define IQ_F_VALUE_MINUS_20_98 -17599300 // hz = -20.9799999999986 +#define IQ_F_VALUE_MINUS_20_97 -17590911 // hz = -20.9699999999986 +#define IQ_F_VALUE_MINUS_20_96 -17582523 // hz = -20.9599999999986 +#define IQ_F_VALUE_MINUS_20_95 -17574134 // hz = -20.9499999999986 +#define IQ_F_VALUE_MINUS_20_94 -17565746 // hz = -20.9399999999986 +#define IQ_F_VALUE_MINUS_20_93 -17557357 // hz = -20.9299999999986 +#define IQ_F_VALUE_MINUS_20_92 -17548968 // hz = -20.9199999999986 +#define IQ_F_VALUE_MINUS_20_91 -17540580 // hz = -20.9099999999986 +#define IQ_F_VALUE_MINUS_20_90 -17532191 // hz = -20.8999999999986 +#define IQ_F_VALUE_MINUS_20_89 -17523803 // hz = -20.8899999999986 +#define IQ_F_VALUE_MINUS_20_88 -17515414 // hz = -20.8799999999986 +#define IQ_F_VALUE_MINUS_20_87 -17507025 // hz = -20.8699999999986 +#define IQ_F_VALUE_MINUS_20_86 -17498637 // hz = -20.8599999999986 +#define IQ_F_VALUE_MINUS_20_85 -17490248 // hz = -20.8499999999986 +#define IQ_F_VALUE_MINUS_20_84 -17481860 // hz = -20.8399999999986 +#define IQ_F_VALUE_MINUS_20_83 -17473471 // hz = -20.8299999999986 +#define IQ_F_VALUE_MINUS_20_82 -17465082 // hz = -20.8199999999986 +#define IQ_F_VALUE_MINUS_20_81 -17456694 // hz = -20.8099999999986 +#define IQ_F_VALUE_MINUS_20_80 -17448305 // hz = -20.7999999999986 +#define IQ_F_VALUE_MINUS_20_79 -17439917 // hz = -20.7899999999986 +#define IQ_F_VALUE_MINUS_20_78 -17431528 // hz = -20.7799999999986 +#define IQ_F_VALUE_MINUS_20_77 -17423139 // hz = -20.7699999999986 +#define IQ_F_VALUE_MINUS_20_76 -17414751 // hz = -20.7599999999986 +#define IQ_F_VALUE_MINUS_20_75 -17406362 // hz = -20.7499999999986 +#define IQ_F_VALUE_MINUS_20_74 -17397973 // hz = -20.7399999999986 +#define IQ_F_VALUE_MINUS_20_73 -17389585 // hz = -20.7299999999985 +#define IQ_F_VALUE_MINUS_20_72 -17381196 // hz = -20.7199999999985 +#define IQ_F_VALUE_MINUS_20_71 -17372808 // hz = -20.7099999999986 +#define IQ_F_VALUE_MINUS_20_70 -17364419 // hz = -20.6999999999985 +#define IQ_F_VALUE_MINUS_20_69 -17356030 // hz = -20.6899999999985 +#define IQ_F_VALUE_MINUS_20_68 -17347642 // hz = -20.6799999999985 +#define IQ_F_VALUE_MINUS_20_67 -17339253 // hz = -20.6699999999985 +#define IQ_F_VALUE_MINUS_20_66 -17330865 // hz = -20.6599999999985 +#define IQ_F_VALUE_MINUS_20_65 -17322476 // hz = -20.6499999999985 +#define IQ_F_VALUE_MINUS_20_64 -17314087 // hz = -20.6399999999985 +#define IQ_F_VALUE_MINUS_20_63 -17305699 // hz = -20.6299999999985 +#define IQ_F_VALUE_MINUS_20_62 -17297310 // hz = -20.6199999999985 +#define IQ_F_VALUE_MINUS_20_61 -17288922 // hz = -20.6099999999985 +#define IQ_F_VALUE_MINUS_20_60 -17280533 // hz = -20.5999999999985 +#define IQ_F_VALUE_MINUS_20_59 -17272144 // hz = -20.5899999999985 +#define IQ_F_VALUE_MINUS_20_58 -17263756 // hz = -20.5799999999985 +#define IQ_F_VALUE_MINUS_20_57 -17255367 // hz = -20.5699999999985 +#define IQ_F_VALUE_MINUS_20_56 -17246979 // hz = -20.5599999999985 +#define IQ_F_VALUE_MINUS_20_55 -17238590 // hz = -20.5499999999985 +#define IQ_F_VALUE_MINUS_20_54 -17230201 // hz = -20.5399999999985 +#define IQ_F_VALUE_MINUS_20_53 -17221813 // hz = -20.5299999999985 +#define IQ_F_VALUE_MINUS_20_52 -17213424 // hz = -20.5199999999985 +#define IQ_F_VALUE_MINUS_20_51 -17205036 // hz = -20.5099999999985 +#define IQ_F_VALUE_MINUS_20_50 -17196647 // hz = -20.4999999999985 +#define IQ_F_VALUE_MINUS_20_49 -17188258 // hz = -20.4899999999985 +#define IQ_F_VALUE_MINUS_20_48 -17179870 // hz = -20.4799999999985 +#define IQ_F_VALUE_MINUS_20_47 -17171481 // hz = -20.4699999999985 +#define IQ_F_VALUE_MINUS_20_46 -17163092 // hz = -20.4599999999985 +#define IQ_F_VALUE_MINUS_20_45 -17154704 // hz = -20.4499999999985 +#define IQ_F_VALUE_MINUS_20_44 -17146315 // hz = -20.4399999999985 +#define IQ_F_VALUE_MINUS_20_43 -17137927 // hz = -20.4299999999985 +#define IQ_F_VALUE_MINUS_20_42 -17129538 // hz = -20.4199999999985 +#define IQ_F_VALUE_MINUS_20_41 -17121149 // hz = -20.4099999999985 +#define IQ_F_VALUE_MINUS_20_40 -17112761 // hz = -20.3999999999985 +#define IQ_F_VALUE_MINUS_20_39 -17104372 // hz = -20.3899999999985 +#define IQ_F_VALUE_MINUS_20_38 -17095984 // hz = -20.3799999999985 +#define IQ_F_VALUE_MINUS_20_37 -17087595 // hz = -20.3699999999985 +#define IQ_F_VALUE_MINUS_20_36 -17079206 // hz = -20.3599999999985 +#define IQ_F_VALUE_MINUS_20_35 -17070818 // hz = -20.3499999999985 +#define IQ_F_VALUE_MINUS_20_34 -17062429 // hz = -20.3399999999985 +#define IQ_F_VALUE_MINUS_20_33 -17054041 // hz = -20.3299999999985 +#define IQ_F_VALUE_MINUS_20_32 -17045652 // hz = -20.3199999999985 +#define IQ_F_VALUE_MINUS_20_31 -17037263 // hz = -20.3099999999985 +#define IQ_F_VALUE_MINUS_20_30 -17028875 // hz = -20.2999999999985 +#define IQ_F_VALUE_MINUS_20_29 -17020486 // hz = -20.2899999999985 +#define IQ_F_VALUE_MINUS_20_28 -17012098 // hz = -20.2799999999985 +#define IQ_F_VALUE_MINUS_20_27 -17003709 // hz = -20.2699999999985 +#define IQ_F_VALUE_MINUS_20_26 -16995320 // hz = -20.2599999999985 +#define IQ_F_VALUE_MINUS_20_25 -16986932 // hz = -20.2499999999985 +#define IQ_F_VALUE_MINUS_20_24 -16978543 // hz = -20.2399999999985 +#define IQ_F_VALUE_MINUS_20_23 -16970154 // hz = -20.2299999999985 +#define IQ_F_VALUE_MINUS_20_22 -16961766 // hz = -20.2199999999985 +#define IQ_F_VALUE_MINUS_20_21 -16953377 // hz = -20.2099999999985 +#define IQ_F_VALUE_MINUS_20_20 -16944989 // hz = -20.1999999999985 +#define IQ_F_VALUE_MINUS_20_19 -16936600 // hz = -20.1899999999985 +#define IQ_F_VALUE_MINUS_20_18 -16928211 // hz = -20.1799999999985 +#define IQ_F_VALUE_MINUS_20_17 -16919823 // hz = -20.1699999999985 +#define IQ_F_VALUE_MINUS_20_16 -16911434 // hz = -20.1599999999985 +#define IQ_F_VALUE_MINUS_20_15 -16903046 // hz = -20.1499999999985 +#define IQ_F_VALUE_MINUS_20_14 -16894657 // hz = -20.1399999999985 +#define IQ_F_VALUE_MINUS_20_13 -16886268 // hz = -20.1299999999985 +#define IQ_F_VALUE_MINUS_20_12 -16877880 // hz = -20.1199999999985 +#define IQ_F_VALUE_MINUS_20_11 -16869491 // hz = -20.1099999999985 +#define IQ_F_VALUE_MINUS_20_10 -16861103 // hz = -20.0999999999985 +#define IQ_F_VALUE_MINUS_20_09 -16852714 // hz = -20.0899999999985 +#define IQ_F_VALUE_MINUS_20_08 -16844325 // hz = -20.0799999999984 +#define IQ_F_VALUE_MINUS_20_07 -16835937 // hz = -20.0699999999985 +#define IQ_F_VALUE_MINUS_20_06 -16827548 // hz = -20.0599999999984 +#define IQ_F_VALUE_MINUS_20_05 -16819160 // hz = -20.0499999999984 +#define IQ_F_VALUE_MINUS_20_04 -16810771 // hz = -20.0399999999984 +#define IQ_F_VALUE_MINUS_20_03 -16802382 // hz = -20.0299999999984 +#define IQ_F_VALUE_MINUS_20_02 -16793994 // hz = -20.0199999999984 +#define IQ_F_VALUE_MINUS_20_01 -16785605 // hz = -20.0099999999984 +#define IQ_F_VALUE_MINUS_20_00 -16777216 // hz = -19.9999999999984 +#define IQ_F_VALUE_MINUS_19_99 -16768828 // hz = -19.9899999999984 +#define IQ_F_VALUE_MINUS_19_98 -16760439 // hz = -19.9799999999984 +#define IQ_F_VALUE_MINUS_19_97 -16752051 // hz = -19.9699999999984 +#define IQ_F_VALUE_MINUS_19_96 -16743662 // hz = -19.9599999999984 +#define IQ_F_VALUE_MINUS_19_95 -16735273 // hz = -19.9499999999984 +#define IQ_F_VALUE_MINUS_19_94 -16726885 // hz = -19.9399999999984 +#define IQ_F_VALUE_MINUS_19_93 -16718496 // hz = -19.9299999999984 +#define IQ_F_VALUE_MINUS_19_92 -16710108 // hz = -19.9199999999984 +#define IQ_F_VALUE_MINUS_19_91 -16701719 // hz = -19.9099999999984 +#define IQ_F_VALUE_MINUS_19_90 -16693330 // hz = -19.8999999999984 +#define IQ_F_VALUE_MINUS_19_89 -16684942 // hz = -19.8899999999984 +#define IQ_F_VALUE_MINUS_19_88 -16676553 // hz = -19.8799999999984 +#define IQ_F_VALUE_MINUS_19_87 -16668165 // hz = -19.8699999999984 +#define IQ_F_VALUE_MINUS_19_86 -16659776 // hz = -19.8599999999984 +#define IQ_F_VALUE_MINUS_19_85 -16651387 // hz = -19.8499999999984 +#define IQ_F_VALUE_MINUS_19_84 -16642999 // hz = -19.8399999999984 +#define IQ_F_VALUE_MINUS_19_83 -16634610 // hz = -19.8299999999984 +#define IQ_F_VALUE_MINUS_19_82 -16626222 // hz = -19.8199999999984 +#define IQ_F_VALUE_MINUS_19_81 -16617833 // hz = -19.8099999999984 +#define IQ_F_VALUE_MINUS_19_80 -16609444 // hz = -19.7999999999984 +#define IQ_F_VALUE_MINUS_19_79 -16601056 // hz = -19.7899999999984 +#define IQ_F_VALUE_MINUS_19_78 -16592667 // hz = -19.7799999999984 +#define IQ_F_VALUE_MINUS_19_77 -16584279 // hz = -19.7699999999984 +#define IQ_F_VALUE_MINUS_19_76 -16575890 // hz = -19.7599999999984 +#define IQ_F_VALUE_MINUS_19_75 -16567501 // hz = -19.7499999999984 +#define IQ_F_VALUE_MINUS_19_74 -16559113 // hz = -19.7399999999984 +#define IQ_F_VALUE_MINUS_19_73 -16550724 // hz = -19.7299999999984 +#define IQ_F_VALUE_MINUS_19_72 -16542335 // hz = -19.7199999999984 +#define IQ_F_VALUE_MINUS_19_71 -16533947 // hz = -19.7099999999984 +#define IQ_F_VALUE_MINUS_19_70 -16525558 // hz = -19.6999999999984 +#define IQ_F_VALUE_MINUS_19_69 -16517170 // hz = -19.6899999999984 +#define IQ_F_VALUE_MINUS_19_68 -16508781 // hz = -19.6799999999984 +#define IQ_F_VALUE_MINUS_19_67 -16500392 // hz = -19.6699999999984 +#define IQ_F_VALUE_MINUS_19_66 -16492004 // hz = -19.6599999999984 +#define IQ_F_VALUE_MINUS_19_65 -16483615 // hz = -19.6499999999984 +#define IQ_F_VALUE_MINUS_19_64 -16475227 // hz = -19.6399999999984 +#define IQ_F_VALUE_MINUS_19_63 -16466838 // hz = -19.6299999999984 +#define IQ_F_VALUE_MINUS_19_62 -16458449 // hz = -19.6199999999984 +#define IQ_F_VALUE_MINUS_19_61 -16450061 // hz = -19.6099999999984 +#define IQ_F_VALUE_MINUS_19_60 -16441672 // hz = -19.5999999999984 +#define IQ_F_VALUE_MINUS_19_59 -16433284 // hz = -19.5899999999984 +#define IQ_F_VALUE_MINUS_19_58 -16424895 // hz = -19.5799999999984 +#define IQ_F_VALUE_MINUS_19_57 -16416506 // hz = -19.5699999999984 +#define IQ_F_VALUE_MINUS_19_56 -16408118 // hz = -19.5599999999984 +#define IQ_F_VALUE_MINUS_19_55 -16399729 // hz = -19.5499999999984 +#define IQ_F_VALUE_MINUS_19_54 -16391341 // hz = -19.5399999999984 +#define IQ_F_VALUE_MINUS_19_53 -16382952 // hz = -19.5299999999984 +#define IQ_F_VALUE_MINUS_19_52 -16374563 // hz = -19.5199999999984 +#define IQ_F_VALUE_MINUS_19_51 -16366175 // hz = -19.5099999999984 +#define IQ_F_VALUE_MINUS_19_50 -16357786 // hz = -19.4999999999984 +#define IQ_F_VALUE_MINUS_19_49 -16349397 // hz = -19.4899999999984 +#define IQ_F_VALUE_MINUS_19_48 -16341009 // hz = -19.4799999999984 +#define IQ_F_VALUE_MINUS_19_47 -16332620 // hz = -19.4699999999984 +#define IQ_F_VALUE_MINUS_19_46 -16324232 // hz = -19.4599999999984 +#define IQ_F_VALUE_MINUS_19_45 -16315843 // hz = -19.4499999999984 +#define IQ_F_VALUE_MINUS_19_44 -16307454 // hz = -19.4399999999983 +#define IQ_F_VALUE_MINUS_19_43 -16299066 // hz = -19.4299999999983 +#define IQ_F_VALUE_MINUS_19_42 -16290677 // hz = -19.4199999999983 +#define IQ_F_VALUE_MINUS_19_41 -16282289 // hz = -19.4099999999983 +#define IQ_F_VALUE_MINUS_19_40 -16273900 // hz = -19.3999999999983 +#define IQ_F_VALUE_MINUS_19_39 -16265511 // hz = -19.3899999999983 +#define IQ_F_VALUE_MINUS_19_38 -16257123 // hz = -19.3799999999983 +#define IQ_F_VALUE_MINUS_19_37 -16248734 // hz = -19.3699999999983 +#define IQ_F_VALUE_MINUS_19_36 -16240346 // hz = -19.3599999999983 +#define IQ_F_VALUE_MINUS_19_35 -16231957 // hz = -19.3499999999983 +#define IQ_F_VALUE_MINUS_19_34 -16223568 // hz = -19.3399999999983 +#define IQ_F_VALUE_MINUS_19_33 -16215180 // hz = -19.3299999999983 +#define IQ_F_VALUE_MINUS_19_32 -16206791 // hz = -19.3199999999983 +#define IQ_F_VALUE_MINUS_19_31 -16198403 // hz = -19.3099999999983 +#define IQ_F_VALUE_MINUS_19_30 -16190014 // hz = -19.2999999999983 +#define IQ_F_VALUE_MINUS_19_29 -16181625 // hz = -19.2899999999983 +#define IQ_F_VALUE_MINUS_19_28 -16173237 // hz = -19.2799999999983 +#define IQ_F_VALUE_MINUS_19_27 -16164848 // hz = -19.2699999999983 +#define IQ_F_VALUE_MINUS_19_26 -16156460 // hz = -19.2599999999983 +#define IQ_F_VALUE_MINUS_19_25 -16148071 // hz = -19.2499999999983 +#define IQ_F_VALUE_MINUS_19_24 -16139682 // hz = -19.2399999999983 +#define IQ_F_VALUE_MINUS_19_23 -16131294 // hz = -19.2299999999983 +#define IQ_F_VALUE_MINUS_19_22 -16122905 // hz = -19.2199999999983 +#define IQ_F_VALUE_MINUS_19_21 -16114516 // hz = -19.2099999999983 +#define IQ_F_VALUE_MINUS_19_20 -16106128 // hz = -19.1999999999983 +#define IQ_F_VALUE_MINUS_19_19 -16097739 // hz = -19.1899999999983 +#define IQ_F_VALUE_MINUS_19_18 -16089351 // hz = -19.1799999999983 +#define IQ_F_VALUE_MINUS_19_17 -16080962 // hz = -19.1699999999983 +#define IQ_F_VALUE_MINUS_19_16 -16072573 // hz = -19.1599999999983 +#define IQ_F_VALUE_MINUS_19_15 -16064185 // hz = -19.1499999999983 +#define IQ_F_VALUE_MINUS_19_14 -16055796 // hz = -19.1399999999983 +#define IQ_F_VALUE_MINUS_19_13 -16047408 // hz = -19.1299999999983 +#define IQ_F_VALUE_MINUS_19_12 -16039019 // hz = -19.1199999999983 +#define IQ_F_VALUE_MINUS_19_11 -16030630 // hz = -19.1099999999983 +#define IQ_F_VALUE_MINUS_19_10 -16022242 // hz = -19.0999999999983 +#define IQ_F_VALUE_MINUS_19_09 -16013853 // hz = -19.0899999999983 +#define IQ_F_VALUE_MINUS_19_08 -16005465 // hz = -19.0799999999983 +#define IQ_F_VALUE_MINUS_19_07 -15997076 // hz = -19.0699999999983 +#define IQ_F_VALUE_MINUS_19_06 -15988687 // hz = -19.0599999999983 +#define IQ_F_VALUE_MINUS_19_05 -15980299 // hz = -19.0499999999983 +#define IQ_F_VALUE_MINUS_19_04 -15971910 // hz = -19.0399999999983 +#define IQ_F_VALUE_MINUS_19_03 -15963522 // hz = -19.0299999999983 +#define IQ_F_VALUE_MINUS_19_02 -15955133 // hz = -19.0199999999983 +#define IQ_F_VALUE_MINUS_19_01 -15946744 // hz = -19.0099999999983 +#define IQ_F_VALUE_MINUS_19_00 -15938356 // hz = -18.9999999999983 +#define IQ_F_VALUE_MINUS_18_99 -15929967 // hz = -18.9899999999983 +#define IQ_F_VALUE_MINUS_18_98 -15921578 // hz = -18.9799999999983 +#define IQ_F_VALUE_MINUS_18_97 -15913190 // hz = -18.9699999999983 +#define IQ_F_VALUE_MINUS_18_96 -15904801 // hz = -18.9599999999983 +#define IQ_F_VALUE_MINUS_18_95 -15896413 // hz = -18.9499999999983 +#define IQ_F_VALUE_MINUS_18_94 -15888024 // hz = -18.9399999999983 +#define IQ_F_VALUE_MINUS_18_93 -15879635 // hz = -18.9299999999983 +#define IQ_F_VALUE_MINUS_18_92 -15871247 // hz = -18.9199999999983 +#define IQ_F_VALUE_MINUS_18_91 -15862858 // hz = -18.9099999999983 +#define IQ_F_VALUE_MINUS_18_90 -15854470 // hz = -18.8999999999983 +#define IQ_F_VALUE_MINUS_18_89 -15846081 // hz = -18.8899999999983 +#define IQ_F_VALUE_MINUS_18_88 -15837692 // hz = -18.8799999999983 +#define IQ_F_VALUE_MINUS_18_87 -15829304 // hz = -18.8699999999983 +#define IQ_F_VALUE_MINUS_18_86 -15820915 // hz = -18.8599999999983 +#define IQ_F_VALUE_MINUS_18_85 -15812527 // hz = -18.8499999999983 +#define IQ_F_VALUE_MINUS_18_84 -15804138 // hz = -18.8399999999983 +#define IQ_F_VALUE_MINUS_18_83 -15795749 // hz = -18.8299999999983 +#define IQ_F_VALUE_MINUS_18_82 -15787361 // hz = -18.8199999999983 +#define IQ_F_VALUE_MINUS_18_81 -15778972 // hz = -18.8099999999983 +#define IQ_F_VALUE_MINUS_18_80 -15770584 // hz = -18.7999999999982 +#define IQ_F_VALUE_MINUS_18_79 -15762195 // hz = -18.7899999999982 +#define IQ_F_VALUE_MINUS_18_78 -15753806 // hz = -18.7799999999982 +#define IQ_F_VALUE_MINUS_18_77 -15745418 // hz = -18.7699999999982 +#define IQ_F_VALUE_MINUS_18_76 -15737029 // hz = -18.7599999999982 +#define IQ_F_VALUE_MINUS_18_75 -15728640 // hz = -18.7499999999982 +#define IQ_F_VALUE_MINUS_18_74 -15720252 // hz = -18.7399999999982 +#define IQ_F_VALUE_MINUS_18_73 -15711863 // hz = -18.7299999999982 +#define IQ_F_VALUE_MINUS_18_72 -15703475 // hz = -18.7199999999982 +#define IQ_F_VALUE_MINUS_18_71 -15695086 // hz = -18.7099999999982 +#define IQ_F_VALUE_MINUS_18_70 -15686697 // hz = -18.6999999999982 +#define IQ_F_VALUE_MINUS_18_69 -15678309 // hz = -18.6899999999982 +#define IQ_F_VALUE_MINUS_18_68 -15669920 // hz = -18.6799999999982 +#define IQ_F_VALUE_MINUS_18_67 -15661532 // hz = -18.6699999999982 +#define IQ_F_VALUE_MINUS_18_66 -15653143 // hz = -18.6599999999982 +#define IQ_F_VALUE_MINUS_18_65 -15644754 // hz = -18.6499999999982 +#define IQ_F_VALUE_MINUS_18_64 -15636366 // hz = -18.6399999999982 +#define IQ_F_VALUE_MINUS_18_63 -15627977 // hz = -18.6299999999982 +#define IQ_F_VALUE_MINUS_18_62 -15619589 // hz = -18.6199999999982 +#define IQ_F_VALUE_MINUS_18_61 -15611200 // hz = -18.6099999999982 +#define IQ_F_VALUE_MINUS_18_60 -15602811 // hz = -18.5999999999982 +#define IQ_F_VALUE_MINUS_18_59 -15594423 // hz = -18.5899999999982 +#define IQ_F_VALUE_MINUS_18_58 -15586034 // hz = -18.5799999999982 +#define IQ_F_VALUE_MINUS_18_57 -15577646 // hz = -18.5699999999982 +#define IQ_F_VALUE_MINUS_18_56 -15569257 // hz = -18.5599999999982 +#define IQ_F_VALUE_MINUS_18_55 -15560868 // hz = -18.5499999999982 +#define IQ_F_VALUE_MINUS_18_54 -15552480 // hz = -18.5399999999982 +#define IQ_F_VALUE_MINUS_18_53 -15544091 // hz = -18.5299999999982 +#define IQ_F_VALUE_MINUS_18_52 -15535703 // hz = -18.5199999999982 +#define IQ_F_VALUE_MINUS_18_51 -15527314 // hz = -18.5099999999982 +#define IQ_F_VALUE_MINUS_18_50 -15518925 // hz = -18.4999999999982 +#define IQ_F_VALUE_MINUS_18_49 -15510537 // hz = -18.4899999999982 +#define IQ_F_VALUE_MINUS_18_48 -15502148 // hz = -18.4799999999982 +#define IQ_F_VALUE_MINUS_18_47 -15493759 // hz = -18.4699999999982 +#define IQ_F_VALUE_MINUS_18_46 -15485371 // hz = -18.4599999999982 +#define IQ_F_VALUE_MINUS_18_45 -15476982 // hz = -18.4499999999982 +#define IQ_F_VALUE_MINUS_18_44 -15468594 // hz = -18.4399999999982 +#define IQ_F_VALUE_MINUS_18_43 -15460205 // hz = -18.4299999999982 +#define IQ_F_VALUE_MINUS_18_42 -15451816 // hz = -18.4199999999982 +#define IQ_F_VALUE_MINUS_18_41 -15443428 // hz = -18.4099999999982 +#define IQ_F_VALUE_MINUS_18_40 -15435039 // hz = -18.3999999999982 +#define IQ_F_VALUE_MINUS_18_39 -15426651 // hz = -18.3899999999982 +#define IQ_F_VALUE_MINUS_18_38 -15418262 // hz = -18.3799999999982 +#define IQ_F_VALUE_MINUS_18_37 -15409873 // hz = -18.3699999999982 +#define IQ_F_VALUE_MINUS_18_36 -15401485 // hz = -18.3599999999982 +#define IQ_F_VALUE_MINUS_18_35 -15393096 // hz = -18.3499999999982 +#define IQ_F_VALUE_MINUS_18_34 -15384708 // hz = -18.3399999999982 +#define IQ_F_VALUE_MINUS_18_33 -15376319 // hz = -18.3299999999982 +#define IQ_F_VALUE_MINUS_18_32 -15367930 // hz = -18.3199999999982 +#define IQ_F_VALUE_MINUS_18_31 -15359542 // hz = -18.3099999999982 +#define IQ_F_VALUE_MINUS_18_30 -15351153 // hz = -18.2999999999982 +#define IQ_F_VALUE_MINUS_18_29 -15342765 // hz = -18.2899999999982 +#define IQ_F_VALUE_MINUS_18_28 -15334376 // hz = -18.2799999999982 +#define IQ_F_VALUE_MINUS_18_27 -15325987 // hz = -18.2699999999982 +#define IQ_F_VALUE_MINUS_18_26 -15317599 // hz = -18.2599999999982 +#define IQ_F_VALUE_MINUS_18_25 -15309210 // hz = -18.2499999999982 +#define IQ_F_VALUE_MINUS_18_24 -15300821 // hz = -18.2399999999982 +#define IQ_F_VALUE_MINUS_18_23 -15292433 // hz = -18.2299999999982 +#define IQ_F_VALUE_MINUS_18_22 -15284044 // hz = -18.2199999999982 +#define IQ_F_VALUE_MINUS_18_21 -15275656 // hz = -18.2099999999982 +#define IQ_F_VALUE_MINUS_18_20 -15267267 // hz = -18.1999999999982 +#define IQ_F_VALUE_MINUS_18_19 -15258878 // hz = -18.1899999999982 +#define IQ_F_VALUE_MINUS_18_18 -15250490 // hz = -18.1799999999982 +#define IQ_F_VALUE_MINUS_18_17 -15242101 // hz = -18.1699999999982 +#define IQ_F_VALUE_MINUS_18_16 -15233713 // hz = -18.1599999999981 +#define IQ_F_VALUE_MINUS_18_15 -15225324 // hz = -18.1499999999981 +#define IQ_F_VALUE_MINUS_18_14 -15216935 // hz = -18.1399999999981 +#define IQ_F_VALUE_MINUS_18_13 -15208547 // hz = -18.1299999999981 +#define IQ_F_VALUE_MINUS_18_12 -15200158 // hz = -18.1199999999981 +#define IQ_F_VALUE_MINUS_18_11 -15191770 // hz = -18.1099999999981 +#define IQ_F_VALUE_MINUS_18_10 -15183381 // hz = -18.0999999999981 +#define IQ_F_VALUE_MINUS_18_09 -15174992 // hz = -18.0899999999981 +#define IQ_F_VALUE_MINUS_18_08 -15166604 // hz = -18.0799999999981 +#define IQ_F_VALUE_MINUS_18_07 -15158215 // hz = -18.0699999999981 +#define IQ_F_VALUE_MINUS_18_06 -15149827 // hz = -18.0599999999981 +#define IQ_F_VALUE_MINUS_18_05 -15141438 // hz = -18.0499999999981 +#define IQ_F_VALUE_MINUS_18_04 -15133049 // hz = -18.0399999999981 +#define IQ_F_VALUE_MINUS_18_03 -15124661 // hz = -18.0299999999981 +#define IQ_F_VALUE_MINUS_18_02 -15116272 // hz = -18.0199999999981 +#define IQ_F_VALUE_MINUS_18_01 -15107884 // hz = -18.0099999999981 +#define IQ_F_VALUE_MINUS_18_00 -15099495 // hz = -17.9999999999981 +#define IQ_F_VALUE_MINUS_17_99 -15091106 // hz = -17.9899999999981 +#define IQ_F_VALUE_MINUS_17_98 -15082718 // hz = -17.9799999999981 +#define IQ_F_VALUE_MINUS_17_97 -15074329 // hz = -17.9699999999981 +#define IQ_F_VALUE_MINUS_17_96 -15065940 // hz = -17.9599999999981 +#define IQ_F_VALUE_MINUS_17_95 -15057552 // hz = -17.9499999999981 +#define IQ_F_VALUE_MINUS_17_94 -15049163 // hz = -17.9399999999981 +#define IQ_F_VALUE_MINUS_17_93 -15040775 // hz = -17.9299999999981 +#define IQ_F_VALUE_MINUS_17_92 -15032386 // hz = -17.9199999999981 +#define IQ_F_VALUE_MINUS_17_91 -15023997 // hz = -17.9099999999981 +#define IQ_F_VALUE_MINUS_17_90 -15015609 // hz = -17.8999999999981 +#define IQ_F_VALUE_MINUS_17_89 -15007220 // hz = -17.8899999999981 +#define IQ_F_VALUE_MINUS_17_88 -14998832 // hz = -17.8799999999981 +#define IQ_F_VALUE_MINUS_17_87 -14990443 // hz = -17.8699999999981 +#define IQ_F_VALUE_MINUS_17_86 -14982054 // hz = -17.8599999999981 +#define IQ_F_VALUE_MINUS_17_85 -14973666 // hz = -17.8499999999981 +#define IQ_F_VALUE_MINUS_17_84 -14965277 // hz = -17.8399999999981 +#define IQ_F_VALUE_MINUS_17_83 -14956889 // hz = -17.8299999999981 +#define IQ_F_VALUE_MINUS_17_82 -14948500 // hz = -17.8199999999981 +#define IQ_F_VALUE_MINUS_17_81 -14940111 // hz = -17.8099999999981 +#define IQ_F_VALUE_MINUS_17_80 -14931723 // hz = -17.7999999999981 +#define IQ_F_VALUE_MINUS_17_79 -14923334 // hz = -17.7899999999981 +#define IQ_F_VALUE_MINUS_17_78 -14914946 // hz = -17.7799999999981 +#define IQ_F_VALUE_MINUS_17_77 -14906557 // hz = -17.7699999999981 +#define IQ_F_VALUE_MINUS_17_76 -14898168 // hz = -17.7599999999981 +#define IQ_F_VALUE_MINUS_17_75 -14889780 // hz = -17.7499999999981 +#define IQ_F_VALUE_MINUS_17_74 -14881391 // hz = -17.7399999999981 +#define IQ_F_VALUE_MINUS_17_73 -14873002 // hz = -17.7299999999981 +#define IQ_F_VALUE_MINUS_17_72 -14864614 // hz = -17.7199999999981 +#define IQ_F_VALUE_MINUS_17_71 -14856225 // hz = -17.7099999999981 +#define IQ_F_VALUE_MINUS_17_70 -14847837 // hz = -17.6999999999981 +#define IQ_F_VALUE_MINUS_17_69 -14839448 // hz = -17.6899999999981 +#define IQ_F_VALUE_MINUS_17_68 -14831059 // hz = -17.6799999999981 +#define IQ_F_VALUE_MINUS_17_67 -14822671 // hz = -17.6699999999981 +#define IQ_F_VALUE_MINUS_17_66 -14814282 // hz = -17.6599999999981 +#define IQ_F_VALUE_MINUS_17_65 -14805894 // hz = -17.6499999999981 +#define IQ_F_VALUE_MINUS_17_64 -14797505 // hz = -17.6399999999981 +#define IQ_F_VALUE_MINUS_17_63 -14789116 // hz = -17.6299999999981 +#define IQ_F_VALUE_MINUS_17_62 -14780728 // hz = -17.6199999999981 +#define IQ_F_VALUE_MINUS_17_61 -14772339 // hz = -17.6099999999981 +#define IQ_F_VALUE_MINUS_17_60 -14763951 // hz = -17.5999999999981 +#define IQ_F_VALUE_MINUS_17_59 -14755562 // hz = -17.5899999999981 +#define IQ_F_VALUE_MINUS_17_58 -14747173 // hz = -17.5799999999981 +#define IQ_F_VALUE_MINUS_17_57 -14738785 // hz = -17.5699999999981 +#define IQ_F_VALUE_MINUS_17_56 -14730396 // hz = -17.5599999999981 +#define IQ_F_VALUE_MINUS_17_55 -14722008 // hz = -17.5499999999981 +#define IQ_F_VALUE_MINUS_17_54 -14713619 // hz = -17.5399999999981 +#define IQ_F_VALUE_MINUS_17_53 -14705230 // hz = -17.5299999999981 +#define IQ_F_VALUE_MINUS_17_52 -14696842 // hz = -17.519999999998 +#define IQ_F_VALUE_MINUS_17_51 -14688453 // hz = -17.509999999998 +#define IQ_F_VALUE_MINUS_17_50 -14680064 // hz = -17.499999999998 +#define IQ_F_VALUE_MINUS_17_49 -14671676 // hz = -17.489999999998 +#define IQ_F_VALUE_MINUS_17_48 -14663287 // hz = -17.479999999998 +#define IQ_F_VALUE_MINUS_17_47 -14654899 // hz = -17.469999999998 +#define IQ_F_VALUE_MINUS_17_46 -14646510 // hz = -17.459999999998 +#define IQ_F_VALUE_MINUS_17_45 -14638121 // hz = -17.449999999998 +#define IQ_F_VALUE_MINUS_17_44 -14629733 // hz = -17.439999999998 +#define IQ_F_VALUE_MINUS_17_43 -14621344 // hz = -17.429999999998 +#define IQ_F_VALUE_MINUS_17_42 -14612956 // hz = -17.419999999998 +#define IQ_F_VALUE_MINUS_17_41 -14604567 // hz = -17.409999999998 +#define IQ_F_VALUE_MINUS_17_40 -14596178 // hz = -17.399999999998 +#define IQ_F_VALUE_MINUS_17_39 -14587790 // hz = -17.389999999998 +#define IQ_F_VALUE_MINUS_17_38 -14579401 // hz = -17.379999999998 +#define IQ_F_VALUE_MINUS_17_37 -14571013 // hz = -17.369999999998 +#define IQ_F_VALUE_MINUS_17_36 -14562624 // hz = -17.359999999998 +#define IQ_F_VALUE_MINUS_17_35 -14554235 // hz = -17.349999999998 +#define IQ_F_VALUE_MINUS_17_34 -14545847 // hz = -17.339999999998 +#define IQ_F_VALUE_MINUS_17_33 -14537458 // hz = -17.329999999998 +#define IQ_F_VALUE_MINUS_17_32 -14529070 // hz = -17.319999999998 +#define IQ_F_VALUE_MINUS_17_31 -14520681 // hz = -17.309999999998 +#define IQ_F_VALUE_MINUS_17_30 -14512292 // hz = -17.299999999998 +#define IQ_F_VALUE_MINUS_17_29 -14503904 // hz = -17.289999999998 +#define IQ_F_VALUE_MINUS_17_28 -14495515 // hz = -17.279999999998 +#define IQ_F_VALUE_MINUS_17_27 -14487127 // hz = -17.269999999998 +#define IQ_F_VALUE_MINUS_17_26 -14478738 // hz = -17.259999999998 +#define IQ_F_VALUE_MINUS_17_25 -14470349 // hz = -17.249999999998 +#define IQ_F_VALUE_MINUS_17_24 -14461961 // hz = -17.239999999998 +#define IQ_F_VALUE_MINUS_17_23 -14453572 // hz = -17.229999999998 +#define IQ_F_VALUE_MINUS_17_22 -14445183 // hz = -17.219999999998 +#define IQ_F_VALUE_MINUS_17_21 -14436795 // hz = -17.209999999998 +#define IQ_F_VALUE_MINUS_17_20 -14428406 // hz = -17.199999999998 +#define IQ_F_VALUE_MINUS_17_19 -14420018 // hz = -17.189999999998 +#define IQ_F_VALUE_MINUS_17_18 -14411629 // hz = -17.179999999998 +#define IQ_F_VALUE_MINUS_17_17 -14403240 // hz = -17.169999999998 +#define IQ_F_VALUE_MINUS_17_16 -14394852 // hz = -17.159999999998 +#define IQ_F_VALUE_MINUS_17_15 -14386463 // hz = -17.149999999998 +#define IQ_F_VALUE_MINUS_17_14 -14378075 // hz = -17.139999999998 +#define IQ_F_VALUE_MINUS_17_13 -14369686 // hz = -17.129999999998 +#define IQ_F_VALUE_MINUS_17_12 -14361297 // hz = -17.119999999998 +#define IQ_F_VALUE_MINUS_17_11 -14352909 // hz = -17.109999999998 +#define IQ_F_VALUE_MINUS_17_10 -14344520 // hz = -17.099999999998 +#define IQ_F_VALUE_MINUS_17_09 -14336132 // hz = -17.089999999998 +#define IQ_F_VALUE_MINUS_17_08 -14327743 // hz = -17.079999999998 +#define IQ_F_VALUE_MINUS_17_07 -14319354 // hz = -17.069999999998 +#define IQ_F_VALUE_MINUS_17_06 -14310966 // hz = -17.059999999998 +#define IQ_F_VALUE_MINUS_17_05 -14302577 // hz = -17.049999999998 +#define IQ_F_VALUE_MINUS_17_04 -14294189 // hz = -17.039999999998 +#define IQ_F_VALUE_MINUS_17_03 -14285800 // hz = -17.029999999998 +#define IQ_F_VALUE_MINUS_17_02 -14277411 // hz = -17.019999999998 +#define IQ_F_VALUE_MINUS_17_01 -14269023 // hz = -17.009999999998 +#define IQ_F_VALUE_MINUS_17_00 -14260634 // hz = -16.999999999998 +#define IQ_F_VALUE_MINUS_16_99 -14252245 // hz = -16.989999999998 +#define IQ_F_VALUE_MINUS_16_98 -14243857 // hz = -16.979999999998 +#define IQ_F_VALUE_MINUS_16_97 -14235468 // hz = -16.969999999998 +#define IQ_F_VALUE_MINUS_16_96 -14227080 // hz = -16.959999999998 +#define IQ_F_VALUE_MINUS_16_95 -14218691 // hz = -16.949999999998 +#define IQ_F_VALUE_MINUS_16_94 -14210302 // hz = -16.939999999998 +#define IQ_F_VALUE_MINUS_16_93 -14201914 // hz = -16.929999999998 +#define IQ_F_VALUE_MINUS_16_92 -14193525 // hz = -16.919999999998 +#define IQ_F_VALUE_MINUS_16_91 -14185137 // hz = -16.909999999998 +#define IQ_F_VALUE_MINUS_16_90 -14176748 // hz = -16.899999999998 +#define IQ_F_VALUE_MINUS_16_89 -14168359 // hz = -16.889999999998 +#define IQ_F_VALUE_MINUS_16_88 -14159971 // hz = -16.8799999999979 +#define IQ_F_VALUE_MINUS_16_87 -14151582 // hz = -16.8699999999979 +#define IQ_F_VALUE_MINUS_16_86 -14143194 // hz = -16.8599999999979 +#define IQ_F_VALUE_MINUS_16_85 -14134805 // hz = -16.8499999999979 +#define IQ_F_VALUE_MINUS_16_84 -14126416 // hz = -16.8399999999979 +#define IQ_F_VALUE_MINUS_16_83 -14118028 // hz = -16.8299999999979 +#define IQ_F_VALUE_MINUS_16_82 -14109639 // hz = -16.8199999999979 +#define IQ_F_VALUE_MINUS_16_81 -14101251 // hz = -16.8099999999979 +#define IQ_F_VALUE_MINUS_16_80 -14092862 // hz = -16.7999999999979 +#define IQ_F_VALUE_MINUS_16_79 -14084473 // hz = -16.7899999999979 +#define IQ_F_VALUE_MINUS_16_78 -14076085 // hz = -16.7799999999979 +#define IQ_F_VALUE_MINUS_16_77 -14067696 // hz = -16.7699999999979 +#define IQ_F_VALUE_MINUS_16_76 -14059308 // hz = -16.7599999999979 +#define IQ_F_VALUE_MINUS_16_75 -14050919 // hz = -16.7499999999979 +#define IQ_F_VALUE_MINUS_16_74 -14042530 // hz = -16.7399999999979 +#define IQ_F_VALUE_MINUS_16_73 -14034142 // hz = -16.7299999999979 +#define IQ_F_VALUE_MINUS_16_72 -14025753 // hz = -16.7199999999979 +#define IQ_F_VALUE_MINUS_16_71 -14017364 // hz = -16.7099999999979 +#define IQ_F_VALUE_MINUS_16_70 -14008976 // hz = -16.6999999999979 +#define IQ_F_VALUE_MINUS_16_69 -14000587 // hz = -16.6899999999979 +#define IQ_F_VALUE_MINUS_16_68 -13992199 // hz = -16.6799999999979 +#define IQ_F_VALUE_MINUS_16_67 -13983810 // hz = -16.6699999999979 +#define IQ_F_VALUE_MINUS_16_66 -13975421 // hz = -16.6599999999979 +#define IQ_F_VALUE_MINUS_16_65 -13967033 // hz = -16.6499999999979 +#define IQ_F_VALUE_MINUS_16_64 -13958644 // hz = -16.6399999999979 +#define IQ_F_VALUE_MINUS_16_63 -13950256 // hz = -16.6299999999979 +#define IQ_F_VALUE_MINUS_16_62 -13941867 // hz = -16.6199999999979 +#define IQ_F_VALUE_MINUS_16_61 -13933478 // hz = -16.6099999999979 +#define IQ_F_VALUE_MINUS_16_60 -13925090 // hz = -16.5999999999979 +#define IQ_F_VALUE_MINUS_16_59 -13916701 // hz = -16.5899999999979 +#define IQ_F_VALUE_MINUS_16_58 -13908313 // hz = -16.5799999999979 +#define IQ_F_VALUE_MINUS_16_57 -13899924 // hz = -16.5699999999979 +#define IQ_F_VALUE_MINUS_16_56 -13891535 // hz = -16.5599999999979 +#define IQ_F_VALUE_MINUS_16_55 -13883147 // hz = -16.5499999999979 +#define IQ_F_VALUE_MINUS_16_54 -13874758 // hz = -16.5399999999979 +#define IQ_F_VALUE_MINUS_16_53 -13866370 // hz = -16.5299999999979 +#define IQ_F_VALUE_MINUS_16_52 -13857981 // hz = -16.5199999999979 +#define IQ_F_VALUE_MINUS_16_51 -13849592 // hz = -16.5099999999979 +#define IQ_F_VALUE_MINUS_16_50 -13841204 // hz = -16.4999999999979 +#define IQ_F_VALUE_MINUS_16_49 -13832815 // hz = -16.4899999999979 +#define IQ_F_VALUE_MINUS_16_48 -13824426 // hz = -16.4799999999979 +#define IQ_F_VALUE_MINUS_16_47 -13816038 // hz = -16.4699999999979 +#define IQ_F_VALUE_MINUS_16_46 -13807649 // hz = -16.4599999999979 +#define IQ_F_VALUE_MINUS_16_45 -13799261 // hz = -16.4499999999979 +#define IQ_F_VALUE_MINUS_16_44 -13790872 // hz = -16.4399999999979 +#define IQ_F_VALUE_MINUS_16_43 -13782483 // hz = -16.4299999999979 +#define IQ_F_VALUE_MINUS_16_42 -13774095 // hz = -16.4199999999979 +#define IQ_F_VALUE_MINUS_16_41 -13765706 // hz = -16.4099999999979 +#define IQ_F_VALUE_MINUS_16_40 -13757318 // hz = -16.3999999999979 +#define IQ_F_VALUE_MINUS_16_39 -13748929 // hz = -16.3899999999979 +#define IQ_F_VALUE_MINUS_16_38 -13740540 // hz = -16.3799999999979 +#define IQ_F_VALUE_MINUS_16_37 -13732152 // hz = -16.3699999999979 +#define IQ_F_VALUE_MINUS_16_36 -13723763 // hz = -16.3599999999979 +#define IQ_F_VALUE_MINUS_16_35 -13715375 // hz = -16.3499999999979 +#define IQ_F_VALUE_MINUS_16_34 -13706986 // hz = -16.3399999999979 +#define IQ_F_VALUE_MINUS_16_33 -13698597 // hz = -16.3299999999979 +#define IQ_F_VALUE_MINUS_16_32 -13690209 // hz = -16.3199999999979 +#define IQ_F_VALUE_MINUS_16_31 -13681820 // hz = -16.3099999999979 +#define IQ_F_VALUE_MINUS_16_30 -13673432 // hz = -16.2999999999979 +#define IQ_F_VALUE_MINUS_16_29 -13665043 // hz = -16.2899999999979 +#define IQ_F_VALUE_MINUS_16_28 -13656654 // hz = -16.2799999999979 +#define IQ_F_VALUE_MINUS_16_27 -13648266 // hz = -16.2699999999979 +#define IQ_F_VALUE_MINUS_16_26 -13639877 // hz = -16.2599999999979 +#define IQ_F_VALUE_MINUS_16_25 -13631488 // hz = -16.2499999999979 +#define IQ_F_VALUE_MINUS_16_24 -13623100 // hz = -16.2399999999978 +#define IQ_F_VALUE_MINUS_16_23 -13614711 // hz = -16.2299999999978 +#define IQ_F_VALUE_MINUS_16_22 -13606323 // hz = -16.2199999999978 +#define IQ_F_VALUE_MINUS_16_21 -13597934 // hz = -16.2099999999978 +#define IQ_F_VALUE_MINUS_16_20 -13589545 // hz = -16.1999999999978 +#define IQ_F_VALUE_MINUS_16_19 -13581157 // hz = -16.1899999999978 +#define IQ_F_VALUE_MINUS_16_18 -13572768 // hz = -16.1799999999978 +#define IQ_F_VALUE_MINUS_16_17 -13564380 // hz = -16.1699999999978 +#define IQ_F_VALUE_MINUS_16_16 -13555991 // hz = -16.1599999999978 +#define IQ_F_VALUE_MINUS_16_15 -13547602 // hz = -16.1499999999978 +#define IQ_F_VALUE_MINUS_16_14 -13539214 // hz = -16.1399999999978 +#define IQ_F_VALUE_MINUS_16_13 -13530825 // hz = -16.1299999999978 +#define IQ_F_VALUE_MINUS_16_12 -13522437 // hz = -16.1199999999978 +#define IQ_F_VALUE_MINUS_16_11 -13514048 // hz = -16.1099999999978 +#define IQ_F_VALUE_MINUS_16_10 -13505659 // hz = -16.0999999999978 +#define IQ_F_VALUE_MINUS_16_09 -13497271 // hz = -16.0899999999978 +#define IQ_F_VALUE_MINUS_16_08 -13488882 // hz = -16.0799999999978 +#define IQ_F_VALUE_MINUS_16_07 -13480494 // hz = -16.0699999999978 +#define IQ_F_VALUE_MINUS_16_06 -13472105 // hz = -16.0599999999978 +#define IQ_F_VALUE_MINUS_16_05 -13463716 // hz = -16.0499999999978 +#define IQ_F_VALUE_MINUS_16_04 -13455328 // hz = -16.0399999999978 +#define IQ_F_VALUE_MINUS_16_03 -13446939 // hz = -16.0299999999978 +#define IQ_F_VALUE_MINUS_16_02 -13438551 // hz = -16.0199999999978 +#define IQ_F_VALUE_MINUS_16_01 -13430162 // hz = -16.0099999999978 +#define IQ_F_VALUE_MINUS_16_00 -13421773 // hz = -15.9999999999978 +#define IQ_F_VALUE_MINUS_15_99 -13413385 // hz = -15.9899999999978 +#define IQ_F_VALUE_MINUS_15_98 -13404996 // hz = -15.9799999999978 +#define IQ_F_VALUE_MINUS_15_97 -13396607 // hz = -15.9699999999978 +#define IQ_F_VALUE_MINUS_15_96 -13388219 // hz = -15.9599999999978 +#define IQ_F_VALUE_MINUS_15_95 -13379830 // hz = -15.9499999999978 +#define IQ_F_VALUE_MINUS_15_94 -13371442 // hz = -15.9399999999978 +#define IQ_F_VALUE_MINUS_15_93 -13363053 // hz = -15.9299999999978 +#define IQ_F_VALUE_MINUS_15_92 -13354664 // hz = -15.9199999999978 +#define IQ_F_VALUE_MINUS_15_91 -13346276 // hz = -15.9099999999978 +#define IQ_F_VALUE_MINUS_15_90 -13337887 // hz = -15.8999999999978 +#define IQ_F_VALUE_MINUS_15_89 -13329499 // hz = -15.8899999999978 +#define IQ_F_VALUE_MINUS_15_88 -13321110 // hz = -15.8799999999978 +#define IQ_F_VALUE_MINUS_15_87 -13312721 // hz = -15.8699999999978 +#define IQ_F_VALUE_MINUS_15_86 -13304333 // hz = -15.8599999999978 +#define IQ_F_VALUE_MINUS_15_85 -13295944 // hz = -15.8499999999978 +#define IQ_F_VALUE_MINUS_15_84 -13287556 // hz = -15.8399999999978 +#define IQ_F_VALUE_MINUS_15_83 -13279167 // hz = -15.8299999999978 +#define IQ_F_VALUE_MINUS_15_82 -13270778 // hz = -15.8199999999978 +#define IQ_F_VALUE_MINUS_15_81 -13262390 // hz = -15.8099999999978 +#define IQ_F_VALUE_MINUS_15_80 -13254001 // hz = -15.7999999999978 +#define IQ_F_VALUE_MINUS_15_79 -13245613 // hz = -15.7899999999978 +#define IQ_F_VALUE_MINUS_15_78 -13237224 // hz = -15.7799999999978 +#define IQ_F_VALUE_MINUS_15_77 -13228835 // hz = -15.7699999999978 +#define IQ_F_VALUE_MINUS_15_76 -13220447 // hz = -15.7599999999978 +#define IQ_F_VALUE_MINUS_15_75 -13212058 // hz = -15.7499999999978 +#define IQ_F_VALUE_MINUS_15_74 -13203669 // hz = -15.7399999999978 +#define IQ_F_VALUE_MINUS_15_73 -13195281 // hz = -15.7299999999978 +#define IQ_F_VALUE_MINUS_15_72 -13186892 // hz = -15.7199999999978 +#define IQ_F_VALUE_MINUS_15_71 -13178504 // hz = -15.7099999999978 +#define IQ_F_VALUE_MINUS_15_70 -13170115 // hz = -15.6999999999978 +#define IQ_F_VALUE_MINUS_15_69 -13161726 // hz = -15.6899999999978 +#define IQ_F_VALUE_MINUS_15_68 -13153338 // hz = -15.6799999999978 +#define IQ_F_VALUE_MINUS_15_67 -13144949 // hz = -15.6699999999978 +#define IQ_F_VALUE_MINUS_15_66 -13136561 // hz = -15.6599999999978 +#define IQ_F_VALUE_MINUS_15_65 -13128172 // hz = -15.6499999999978 +#define IQ_F_VALUE_MINUS_15_64 -13119783 // hz = -15.6399999999978 +#define IQ_F_VALUE_MINUS_15_63 -13111395 // hz = -15.6299999999978 +#define IQ_F_VALUE_MINUS_15_62 -13103006 // hz = -15.6199999999978 +#define IQ_F_VALUE_MINUS_15_61 -13094618 // hz = -15.6099999999978 +#define IQ_F_VALUE_MINUS_15_60 -13086229 // hz = -15.5999999999977 +#define IQ_F_VALUE_MINUS_15_59 -13077840 // hz = -15.5899999999977 +#define IQ_F_VALUE_MINUS_15_58 -13069452 // hz = -15.5799999999977 +#define IQ_F_VALUE_MINUS_15_57 -13061063 // hz = -15.5699999999977 +#define IQ_F_VALUE_MINUS_15_56 -13052675 // hz = -15.5599999999977 +#define IQ_F_VALUE_MINUS_15_55 -13044286 // hz = -15.5499999999977 +#define IQ_F_VALUE_MINUS_15_54 -13035897 // hz = -15.5399999999977 +#define IQ_F_VALUE_MINUS_15_53 -13027509 // hz = -15.5299999999977 +#define IQ_F_VALUE_MINUS_15_52 -13019120 // hz = -15.5199999999977 +#define IQ_F_VALUE_MINUS_15_51 -13010732 // hz = -15.5099999999977 +#define IQ_F_VALUE_MINUS_15_50 -13002343 // hz = -15.4999999999977 +#define IQ_F_VALUE_MINUS_15_49 -12993954 // hz = -15.4899999999977 +#define IQ_F_VALUE_MINUS_15_48 -12985566 // hz = -15.4799999999977 +#define IQ_F_VALUE_MINUS_15_47 -12977177 // hz = -15.4699999999977 +#define IQ_F_VALUE_MINUS_15_46 -12968788 // hz = -15.4599999999977 +#define IQ_F_VALUE_MINUS_15_45 -12960400 // hz = -15.4499999999977 +#define IQ_F_VALUE_MINUS_15_44 -12952011 // hz = -15.4399999999977 +#define IQ_F_VALUE_MINUS_15_43 -12943623 // hz = -15.4299999999977 +#define IQ_F_VALUE_MINUS_15_42 -12935234 // hz = -15.4199999999977 +#define IQ_F_VALUE_MINUS_15_41 -12926845 // hz = -15.4099999999977 +#define IQ_F_VALUE_MINUS_15_40 -12918457 // hz = -15.3999999999977 +#define IQ_F_VALUE_MINUS_15_39 -12910068 // hz = -15.3899999999977 +#define IQ_F_VALUE_MINUS_15_38 -12901680 // hz = -15.3799999999977 +#define IQ_F_VALUE_MINUS_15_37 -12893291 // hz = -15.3699999999977 +#define IQ_F_VALUE_MINUS_15_36 -12884902 // hz = -15.3599999999977 +#define IQ_F_VALUE_MINUS_15_35 -12876514 // hz = -15.3499999999977 +#define IQ_F_VALUE_MINUS_15_34 -12868125 // hz = -15.3399999999977 +#define IQ_F_VALUE_MINUS_15_33 -12859737 // hz = -15.3299999999977 +#define IQ_F_VALUE_MINUS_15_32 -12851348 // hz = -15.3199999999977 +#define IQ_F_VALUE_MINUS_15_31 -12842959 // hz = -15.3099999999977 +#define IQ_F_VALUE_MINUS_15_30 -12834571 // hz = -15.2999999999977 +#define IQ_F_VALUE_MINUS_15_29 -12826182 // hz = -15.2899999999977 +#define IQ_F_VALUE_MINUS_15_28 -12817794 // hz = -15.2799999999977 +#define IQ_F_VALUE_MINUS_15_27 -12809405 // hz = -15.2699999999977 +#define IQ_F_VALUE_MINUS_15_26 -12801016 // hz = -15.2599999999977 +#define IQ_F_VALUE_MINUS_15_25 -12792628 // hz = -15.2499999999977 +#define IQ_F_VALUE_MINUS_15_24 -12784239 // hz = -15.2399999999977 +#define IQ_F_VALUE_MINUS_15_23 -12775850 // hz = -15.2299999999977 +#define IQ_F_VALUE_MINUS_15_22 -12767462 // hz = -15.2199999999977 +#define IQ_F_VALUE_MINUS_15_21 -12759073 // hz = -15.2099999999977 +#define IQ_F_VALUE_MINUS_15_20 -12750685 // hz = -15.1999999999977 +#define IQ_F_VALUE_MINUS_15_19 -12742296 // hz = -15.1899999999977 +#define IQ_F_VALUE_MINUS_15_18 -12733907 // hz = -15.1799999999977 +#define IQ_F_VALUE_MINUS_15_17 -12725519 // hz = -15.1699999999977 +#define IQ_F_VALUE_MINUS_15_16 -12717130 // hz = -15.1599999999977 +#define IQ_F_VALUE_MINUS_15_15 -12708742 // hz = -15.1499999999977 +#define IQ_F_VALUE_MINUS_15_14 -12700353 // hz = -15.1399999999977 +#define IQ_F_VALUE_MINUS_15_13 -12691964 // hz = -15.1299999999977 +#define IQ_F_VALUE_MINUS_15_12 -12683576 // hz = -15.1199999999977 +#define IQ_F_VALUE_MINUS_15_11 -12675187 // hz = -15.1099999999977 +#define IQ_F_VALUE_MINUS_15_10 -12666799 // hz = -15.0999999999977 +#define IQ_F_VALUE_MINUS_15_09 -12658410 // hz = -15.0899999999977 +#define IQ_F_VALUE_MINUS_15_08 -12650021 // hz = -15.0799999999977 +#define IQ_F_VALUE_MINUS_15_07 -12641633 // hz = -15.0699999999977 +#define IQ_F_VALUE_MINUS_15_06 -12633244 // hz = -15.0599999999977 +#define IQ_F_VALUE_MINUS_15_05 -12624856 // hz = -15.0499999999977 +#define IQ_F_VALUE_MINUS_15_04 -12616467 // hz = -15.0399999999977 +#define IQ_F_VALUE_MINUS_15_03 -12608078 // hz = -15.0299999999977 +#define IQ_F_VALUE_MINUS_15_02 -12599690 // hz = -15.0199999999977 +#define IQ_F_VALUE_MINUS_15_01 -12591301 // hz = -15.0099999999977 +#define IQ_F_VALUE_MINUS_15_00 -12582912 // hz = -14.9999999999977 +#define IQ_F_VALUE_MINUS_14_99 -12574524 // hz = -14.9899999999977 +#define IQ_F_VALUE_MINUS_14_98 -12566135 // hz = -14.9799999999977 +#define IQ_F_VALUE_MINUS_14_97 -12557747 // hz = -14.9699999999977 +#define IQ_F_VALUE_MINUS_14_96 -12549358 // hz = -14.9599999999976 +#define IQ_F_VALUE_MINUS_14_95 -12540969 // hz = -14.9499999999976 +#define IQ_F_VALUE_MINUS_14_94 -12532581 // hz = -14.9399999999976 +#define IQ_F_VALUE_MINUS_14_93 -12524192 // hz = -14.9299999999976 +#define IQ_F_VALUE_MINUS_14_92 -12515804 // hz = -14.9199999999976 +#define IQ_F_VALUE_MINUS_14_91 -12507415 // hz = -14.9099999999976 +#define IQ_F_VALUE_MINUS_14_90 -12499026 // hz = -14.8999999999976 +#define IQ_F_VALUE_MINUS_14_89 -12490638 // hz = -14.8899999999976 +#define IQ_F_VALUE_MINUS_14_88 -12482249 // hz = -14.8799999999976 +#define IQ_F_VALUE_MINUS_14_87 -12473861 // hz = -14.8699999999976 +#define IQ_F_VALUE_MINUS_14_86 -12465472 // hz = -14.8599999999976 +#define IQ_F_VALUE_MINUS_14_85 -12457083 // hz = -14.8499999999976 +#define IQ_F_VALUE_MINUS_14_84 -12448695 // hz = -14.8399999999976 +#define IQ_F_VALUE_MINUS_14_83 -12440306 // hz = -14.8299999999976 +#define IQ_F_VALUE_MINUS_14_82 -12431918 // hz = -14.8199999999976 +#define IQ_F_VALUE_MINUS_14_81 -12423529 // hz = -14.8099999999976 +#define IQ_F_VALUE_MINUS_14_80 -12415140 // hz = -14.7999999999976 +#define IQ_F_VALUE_MINUS_14_79 -12406752 // hz = -14.7899999999976 +#define IQ_F_VALUE_MINUS_14_78 -12398363 // hz = -14.7799999999976 +#define IQ_F_VALUE_MINUS_14_77 -12389975 // hz = -14.7699999999976 +#define IQ_F_VALUE_MINUS_14_76 -12381586 // hz = -14.7599999999976 +#define IQ_F_VALUE_MINUS_14_75 -12373197 // hz = -14.7499999999976 +#define IQ_F_VALUE_MINUS_14_74 -12364809 // hz = -14.7399999999976 +#define IQ_F_VALUE_MINUS_14_73 -12356420 // hz = -14.7299999999976 +#define IQ_F_VALUE_MINUS_14_72 -12348031 // hz = -14.7199999999976 +#define IQ_F_VALUE_MINUS_14_71 -12339643 // hz = -14.7099999999976 +#define IQ_F_VALUE_MINUS_14_70 -12331254 // hz = -14.6999999999976 +#define IQ_F_VALUE_MINUS_14_69 -12322866 // hz = -14.6899999999976 +#define IQ_F_VALUE_MINUS_14_68 -12314477 // hz = -14.6799999999976 +#define IQ_F_VALUE_MINUS_14_67 -12306088 // hz = -14.6699999999976 +#define IQ_F_VALUE_MINUS_14_66 -12297700 // hz = -14.6599999999976 +#define IQ_F_VALUE_MINUS_14_65 -12289311 // hz = -14.6499999999976 +#define IQ_F_VALUE_MINUS_14_64 -12280923 // hz = -14.6399999999976 +#define IQ_F_VALUE_MINUS_14_63 -12272534 // hz = -14.6299999999976 +#define IQ_F_VALUE_MINUS_14_62 -12264145 // hz = -14.6199999999976 +#define IQ_F_VALUE_MINUS_14_61 -12255757 // hz = -14.6099999999976 +#define IQ_F_VALUE_MINUS_14_60 -12247368 // hz = -14.5999999999976 +#define IQ_F_VALUE_MINUS_14_59 -12238980 // hz = -14.5899999999976 +#define IQ_F_VALUE_MINUS_14_58 -12230591 // hz = -14.5799999999976 +#define IQ_F_VALUE_MINUS_14_57 -12222202 // hz = -14.5699999999976 +#define IQ_F_VALUE_MINUS_14_56 -12213814 // hz = -14.5599999999976 +#define IQ_F_VALUE_MINUS_14_55 -12205425 // hz = -14.5499999999976 +#define IQ_F_VALUE_MINUS_14_54 -12197037 // hz = -14.5399999999976 +#define IQ_F_VALUE_MINUS_14_53 -12188648 // hz = -14.5299999999976 +#define IQ_F_VALUE_MINUS_14_52 -12180259 // hz = -14.5199999999976 +#define IQ_F_VALUE_MINUS_14_51 -12171871 // hz = -14.5099999999976 +#define IQ_F_VALUE_MINUS_14_50 -12163482 // hz = -14.4999999999976 +#define IQ_F_VALUE_MINUS_14_49 -12155093 // hz = -14.4899999999976 +#define IQ_F_VALUE_MINUS_14_48 -12146705 // hz = -14.4799999999976 +#define IQ_F_VALUE_MINUS_14_47 -12138316 // hz = -14.4699999999976 +#define IQ_F_VALUE_MINUS_14_46 -12129928 // hz = -14.4599999999976 +#define IQ_F_VALUE_MINUS_14_45 -12121539 // hz = -14.4499999999976 +#define IQ_F_VALUE_MINUS_14_44 -12113150 // hz = -14.4399999999976 +#define IQ_F_VALUE_MINUS_14_43 -12104762 // hz = -14.4299999999976 +#define IQ_F_VALUE_MINUS_14_42 -12096373 // hz = -14.4199999999976 +#define IQ_F_VALUE_MINUS_14_41 -12087985 // hz = -14.4099999999976 +#define IQ_F_VALUE_MINUS_14_40 -12079596 // hz = -14.3999999999976 +#define IQ_F_VALUE_MINUS_14_39 -12071207 // hz = -14.3899999999976 +#define IQ_F_VALUE_MINUS_14_38 -12062819 // hz = -14.3799999999976 +#define IQ_F_VALUE_MINUS_14_37 -12054430 // hz = -14.3699999999976 +#define IQ_F_VALUE_MINUS_14_36 -12046042 // hz = -14.3599999999976 +#define IQ_F_VALUE_MINUS_14_35 -12037653 // hz = -14.3499999999976 +#define IQ_F_VALUE_MINUS_14_34 -12029264 // hz = -14.3399999999976 +#define IQ_F_VALUE_MINUS_14_33 -12020876 // hz = -14.3299999999976 +#define IQ_F_VALUE_MINUS_14_32 -12012487 // hz = -14.3199999999975 +#define IQ_F_VALUE_MINUS_14_31 -12004099 // hz = -14.3099999999975 +#define IQ_F_VALUE_MINUS_14_30 -11995710 // hz = -14.2999999999975 +#define IQ_F_VALUE_MINUS_14_29 -11987321 // hz = -14.2899999999975 +#define IQ_F_VALUE_MINUS_14_28 -11978933 // hz = -14.2799999999975 +#define IQ_F_VALUE_MINUS_14_27 -11970544 // hz = -14.2699999999975 +#define IQ_F_VALUE_MINUS_14_26 -11962156 // hz = -14.2599999999975 +#define IQ_F_VALUE_MINUS_14_25 -11953767 // hz = -14.2499999999975 +#define IQ_F_VALUE_MINUS_14_24 -11945378 // hz = -14.2399999999975 +#define IQ_F_VALUE_MINUS_14_23 -11936990 // hz = -14.2299999999975 +#define IQ_F_VALUE_MINUS_14_22 -11928601 // hz = -14.2199999999975 +#define IQ_F_VALUE_MINUS_14_21 -11920212 // hz = -14.2099999999975 +#define IQ_F_VALUE_MINUS_14_20 -11911824 // hz = -14.1999999999975 +#define IQ_F_VALUE_MINUS_14_19 -11903435 // hz = -14.1899999999975 +#define IQ_F_VALUE_MINUS_14_18 -11895047 // hz = -14.1799999999975 +#define IQ_F_VALUE_MINUS_14_17 -11886658 // hz = -14.1699999999975 +#define IQ_F_VALUE_MINUS_14_16 -11878269 // hz = -14.1599999999975 +#define IQ_F_VALUE_MINUS_14_15 -11869881 // hz = -14.1499999999975 +#define IQ_F_VALUE_MINUS_14_14 -11861492 // hz = -14.1399999999975 +#define IQ_F_VALUE_MINUS_14_13 -11853104 // hz = -14.1299999999975 +#define IQ_F_VALUE_MINUS_14_12 -11844715 // hz = -14.1199999999975 +#define IQ_F_VALUE_MINUS_14_11 -11836326 // hz = -14.1099999999975 +#define IQ_F_VALUE_MINUS_14_10 -11827938 // hz = -14.0999999999975 +#define IQ_F_VALUE_MINUS_14_09 -11819549 // hz = -14.0899999999975 +#define IQ_F_VALUE_MINUS_14_08 -11811161 // hz = -14.0799999999975 +#define IQ_F_VALUE_MINUS_14_07 -11802772 // hz = -14.0699999999975 +#define IQ_F_VALUE_MINUS_14_06 -11794383 // hz = -14.0599999999975 +#define IQ_F_VALUE_MINUS_14_05 -11785995 // hz = -14.0499999999975 +#define IQ_F_VALUE_MINUS_14_04 -11777606 // hz = -14.0399999999975 +#define IQ_F_VALUE_MINUS_14_03 -11769218 // hz = -14.0299999999975 +#define IQ_F_VALUE_MINUS_14_02 -11760829 // hz = -14.0199999999975 +#define IQ_F_VALUE_MINUS_14_01 -11752440 // hz = -14.0099999999975 +#define IQ_F_VALUE_MINUS_14_00 -11744052 // hz = -13.9999999999975 +#define IQ_F_VALUE_MINUS_13_99 -11735663 // hz = -13.9899999999975 +#define IQ_F_VALUE_MINUS_13_98 -11727274 // hz = -13.9799999999975 +#define IQ_F_VALUE_MINUS_13_97 -11718886 // hz = -13.9699999999975 +#define IQ_F_VALUE_MINUS_13_96 -11710497 // hz = -13.9599999999975 +#define IQ_F_VALUE_MINUS_13_95 -11702109 // hz = -13.9499999999975 +#define IQ_F_VALUE_MINUS_13_94 -11693720 // hz = -13.9399999999975 +#define IQ_F_VALUE_MINUS_13_93 -11685331 // hz = -13.9299999999975 +#define IQ_F_VALUE_MINUS_13_92 -11676943 // hz = -13.9199999999975 +#define IQ_F_VALUE_MINUS_13_91 -11668554 // hz = -13.9099999999975 +#define IQ_F_VALUE_MINUS_13_90 -11660166 // hz = -13.8999999999975 +#define IQ_F_VALUE_MINUS_13_89 -11651777 // hz = -13.8899999999975 +#define IQ_F_VALUE_MINUS_13_88 -11643388 // hz = -13.8799999999975 +#define IQ_F_VALUE_MINUS_13_87 -11635000 // hz = -13.8699999999975 +#define IQ_F_VALUE_MINUS_13_86 -11626611 // hz = -13.8599999999975 +#define IQ_F_VALUE_MINUS_13_85 -11618223 // hz = -13.8499999999975 +#define IQ_F_VALUE_MINUS_13_84 -11609834 // hz = -13.8399999999975 +#define IQ_F_VALUE_MINUS_13_83 -11601445 // hz = -13.8299999999975 +#define IQ_F_VALUE_MINUS_13_82 -11593057 // hz = -13.8199999999975 +#define IQ_F_VALUE_MINUS_13_81 -11584668 // hz = -13.8099999999975 +#define IQ_F_VALUE_MINUS_13_80 -11576280 // hz = -13.7999999999975 +#define IQ_F_VALUE_MINUS_13_79 -11567891 // hz = -13.7899999999975 +#define IQ_F_VALUE_MINUS_13_78 -11559502 // hz = -13.7799999999975 +#define IQ_F_VALUE_MINUS_13_77 -11551114 // hz = -13.7699999999975 +#define IQ_F_VALUE_MINUS_13_76 -11542725 // hz = -13.7599999999975 +#define IQ_F_VALUE_MINUS_13_75 -11534336 // hz = -13.7499999999975 +#define IQ_F_VALUE_MINUS_13_74 -11525948 // hz = -13.7399999999975 +#define IQ_F_VALUE_MINUS_13_73 -11517559 // hz = -13.7299999999975 +#define IQ_F_VALUE_MINUS_13_72 -11509171 // hz = -13.7199999999975 +#define IQ_F_VALUE_MINUS_13_71 -11500782 // hz = -13.7099999999975 +#define IQ_F_VALUE_MINUS_13_70 -11492393 // hz = -13.6999999999975 +#define IQ_F_VALUE_MINUS_13_69 -11484005 // hz = -13.6899999999975 +#define IQ_F_VALUE_MINUS_13_68 -11475616 // hz = -13.6799999999974 +#define IQ_F_VALUE_MINUS_13_67 -11467228 // hz = -13.6699999999974 +#define IQ_F_VALUE_MINUS_13_66 -11458839 // hz = -13.6599999999974 +#define IQ_F_VALUE_MINUS_13_65 -11450450 // hz = -13.6499999999974 +#define IQ_F_VALUE_MINUS_13_64 -11442062 // hz = -13.6399999999974 +#define IQ_F_VALUE_MINUS_13_63 -11433673 // hz = -13.6299999999974 +#define IQ_F_VALUE_MINUS_13_62 -11425285 // hz = -13.6199999999974 +#define IQ_F_VALUE_MINUS_13_61 -11416896 // hz = -13.6099999999974 +#define IQ_F_VALUE_MINUS_13_60 -11408507 // hz = -13.5999999999974 +#define IQ_F_VALUE_MINUS_13_59 -11400119 // hz = -13.5899999999974 +#define IQ_F_VALUE_MINUS_13_58 -11391730 // hz = -13.5799999999974 +#define IQ_F_VALUE_MINUS_13_57 -11383342 // hz = -13.5699999999974 +#define IQ_F_VALUE_MINUS_13_56 -11374953 // hz = -13.5599999999974 +#define IQ_F_VALUE_MINUS_13_55 -11366564 // hz = -13.5499999999974 +#define IQ_F_VALUE_MINUS_13_54 -11358176 // hz = -13.5399999999974 +#define IQ_F_VALUE_MINUS_13_53 -11349787 // hz = -13.5299999999974 +#define IQ_F_VALUE_MINUS_13_52 -11341399 // hz = -13.5199999999974 +#define IQ_F_VALUE_MINUS_13_51 -11333010 // hz = -13.5099999999974 +#define IQ_F_VALUE_MINUS_13_50 -11324621 // hz = -13.4999999999974 +#define IQ_F_VALUE_MINUS_13_49 -11316233 // hz = -13.4899999999974 +#define IQ_F_VALUE_MINUS_13_48 -11307844 // hz = -13.4799999999974 +#define IQ_F_VALUE_MINUS_13_47 -11299455 // hz = -13.4699999999974 +#define IQ_F_VALUE_MINUS_13_46 -11291067 // hz = -13.4599999999974 +#define IQ_F_VALUE_MINUS_13_45 -11282678 // hz = -13.4499999999974 +#define IQ_F_VALUE_MINUS_13_44 -11274290 // hz = -13.4399999999974 +#define IQ_F_VALUE_MINUS_13_43 -11265901 // hz = -13.4299999999974 +#define IQ_F_VALUE_MINUS_13_42 -11257512 // hz = -13.4199999999974 +#define IQ_F_VALUE_MINUS_13_41 -11249124 // hz = -13.4099999999974 +#define IQ_F_VALUE_MINUS_13_40 -11240735 // hz = -13.3999999999974 +#define IQ_F_VALUE_MINUS_13_39 -11232347 // hz = -13.3899999999974 +#define IQ_F_VALUE_MINUS_13_38 -11223958 // hz = -13.3799999999974 +#define IQ_F_VALUE_MINUS_13_37 -11215569 // hz = -13.3699999999974 +#define IQ_F_VALUE_MINUS_13_36 -11207181 // hz = -13.3599999999974 +#define IQ_F_VALUE_MINUS_13_35 -11198792 // hz = -13.3499999999974 +#define IQ_F_VALUE_MINUS_13_34 -11190404 // hz = -13.3399999999974 +#define IQ_F_VALUE_MINUS_13_33 -11182015 // hz = -13.3299999999974 +#define IQ_F_VALUE_MINUS_13_32 -11173626 // hz = -13.3199999999974 +#define IQ_F_VALUE_MINUS_13_31 -11165238 // hz = -13.3099999999974 +#define IQ_F_VALUE_MINUS_13_30 -11156849 // hz = -13.2999999999974 +#define IQ_F_VALUE_MINUS_13_29 -11148461 // hz = -13.2899999999974 +#define IQ_F_VALUE_MINUS_13_28 -11140072 // hz = -13.2799999999974 +#define IQ_F_VALUE_MINUS_13_27 -11131683 // hz = -13.2699999999974 +#define IQ_F_VALUE_MINUS_13_26 -11123295 // hz = -13.2599999999974 +#define IQ_F_VALUE_MINUS_13_25 -11114906 // hz = -13.2499999999974 +#define IQ_F_VALUE_MINUS_13_24 -11106517 // hz = -13.2399999999974 +#define IQ_F_VALUE_MINUS_13_23 -11098129 // hz = -13.2299999999974 +#define IQ_F_VALUE_MINUS_13_22 -11089740 // hz = -13.2199999999974 +#define IQ_F_VALUE_MINUS_13_21 -11081352 // hz = -13.2099999999974 +#define IQ_F_VALUE_MINUS_13_20 -11072963 // hz = -13.1999999999974 +#define IQ_F_VALUE_MINUS_13_19 -11064574 // hz = -13.1899999999974 +#define IQ_F_VALUE_MINUS_13_18 -11056186 // hz = -13.1799999999974 +#define IQ_F_VALUE_MINUS_13_17 -11047797 // hz = -13.1699999999974 +#define IQ_F_VALUE_MINUS_13_16 -11039409 // hz = -13.1599999999974 +#define IQ_F_VALUE_MINUS_13_15 -11031020 // hz = -13.1499999999974 +#define IQ_F_VALUE_MINUS_13_14 -11022631 // hz = -13.1399999999974 +#define IQ_F_VALUE_MINUS_13_13 -11014243 // hz = -13.1299999999974 +#define IQ_F_VALUE_MINUS_13_12 -11005854 // hz = -13.1199999999974 +#define IQ_F_VALUE_MINUS_13_11 -10997466 // hz = -13.1099999999974 +#define IQ_F_VALUE_MINUS_13_10 -10989077 // hz = -13.0999999999974 +#define IQ_F_VALUE_MINUS_13_09 -10980688 // hz = -13.0899999999974 +#define IQ_F_VALUE_MINUS_13_08 -10972300 // hz = -13.0799999999974 +#define IQ_F_VALUE_MINUS_13_07 -10963911 // hz = -13.0699999999974 +#define IQ_F_VALUE_MINUS_13_06 -10955523 // hz = -13.0599999999974 +#define IQ_F_VALUE_MINUS_13_05 -10947134 // hz = -13.0499999999974 +#define IQ_F_VALUE_MINUS_13_04 -10938745 // hz = -13.0399999999973 +#define IQ_F_VALUE_MINUS_13_03 -10930357 // hz = -13.0299999999973 +#define IQ_F_VALUE_MINUS_13_02 -10921968 // hz = -13.0199999999973 +#define IQ_F_VALUE_MINUS_13_01 -10913580 // hz = -13.0099999999973 +#define IQ_F_VALUE_MINUS_13_00 -10905191 // hz = -12.9999999999973 +#define IQ_F_VALUE_MINUS_12_99 -10896802 // hz = -12.9899999999973 +#define IQ_F_VALUE_MINUS_12_98 -10888414 // hz = -12.9799999999973 +#define IQ_F_VALUE_MINUS_12_97 -10880025 // hz = -12.9699999999973 +#define IQ_F_VALUE_MINUS_12_96 -10871636 // hz = -12.9599999999973 +#define IQ_F_VALUE_MINUS_12_95 -10863248 // hz = -12.9499999999973 +#define IQ_F_VALUE_MINUS_12_94 -10854859 // hz = -12.9399999999973 +#define IQ_F_VALUE_MINUS_12_93 -10846471 // hz = -12.9299999999973 +#define IQ_F_VALUE_MINUS_12_92 -10838082 // hz = -12.9199999999973 +#define IQ_F_VALUE_MINUS_12_91 -10829693 // hz = -12.9099999999973 +#define IQ_F_VALUE_MINUS_12_90 -10821305 // hz = -12.8999999999973 +#define IQ_F_VALUE_MINUS_12_89 -10812916 // hz = -12.8899999999973 +#define IQ_F_VALUE_MINUS_12_88 -10804528 // hz = -12.8799999999973 +#define IQ_F_VALUE_MINUS_12_87 -10796139 // hz = -12.8699999999973 +#define IQ_F_VALUE_MINUS_12_86 -10787750 // hz = -12.8599999999973 +#define IQ_F_VALUE_MINUS_12_85 -10779362 // hz = -12.8499999999973 +#define IQ_F_VALUE_MINUS_12_84 -10770973 // hz = -12.8399999999973 +#define IQ_F_VALUE_MINUS_12_83 -10762585 // hz = -12.8299999999973 +#define IQ_F_VALUE_MINUS_12_82 -10754196 // hz = -12.8199999999973 +#define IQ_F_VALUE_MINUS_12_81 -10745807 // hz = -12.8099999999973 +#define IQ_F_VALUE_MINUS_12_80 -10737419 // hz = -12.7999999999973 +#define IQ_F_VALUE_MINUS_12_79 -10729030 // hz = -12.7899999999973 +#define IQ_F_VALUE_MINUS_12_78 -10720642 // hz = -12.7799999999973 +#define IQ_F_VALUE_MINUS_12_77 -10712253 // hz = -12.7699999999973 +#define IQ_F_VALUE_MINUS_12_76 -10703864 // hz = -12.7599999999973 +#define IQ_F_VALUE_MINUS_12_75 -10695476 // hz = -12.7499999999973 +#define IQ_F_VALUE_MINUS_12_74 -10687087 // hz = -12.7399999999973 +#define IQ_F_VALUE_MINUS_12_73 -10678698 // hz = -12.7299999999973 +#define IQ_F_VALUE_MINUS_12_72 -10670310 // hz = -12.7199999999973 +#define IQ_F_VALUE_MINUS_12_71 -10661921 // hz = -12.7099999999973 +#define IQ_F_VALUE_MINUS_12_70 -10653533 // hz = -12.6999999999973 +#define IQ_F_VALUE_MINUS_12_69 -10645144 // hz = -12.6899999999973 +#define IQ_F_VALUE_MINUS_12_68 -10636755 // hz = -12.6799999999973 +#define IQ_F_VALUE_MINUS_12_67 -10628367 // hz = -12.6699999999973 +#define IQ_F_VALUE_MINUS_12_66 -10619978 // hz = -12.6599999999973 +#define IQ_F_VALUE_MINUS_12_65 -10611590 // hz = -12.6499999999973 +#define IQ_F_VALUE_MINUS_12_64 -10603201 // hz = -12.6399999999973 +#define IQ_F_VALUE_MINUS_12_63 -10594812 // hz = -12.6299999999973 +#define IQ_F_VALUE_MINUS_12_62 -10586424 // hz = -12.6199999999973 +#define IQ_F_VALUE_MINUS_12_61 -10578035 // hz = -12.6099999999973 +#define IQ_F_VALUE_MINUS_12_60 -10569647 // hz = -12.5999999999973 +#define IQ_F_VALUE_MINUS_12_59 -10561258 // hz = -12.5899999999973 +#define IQ_F_VALUE_MINUS_12_58 -10552869 // hz = -12.5799999999973 +#define IQ_F_VALUE_MINUS_12_57 -10544481 // hz = -12.5699999999973 +#define IQ_F_VALUE_MINUS_12_56 -10536092 // hz = -12.5599999999973 +#define IQ_F_VALUE_MINUS_12_55 -10527704 // hz = -12.5499999999973 +#define IQ_F_VALUE_MINUS_12_54 -10519315 // hz = -12.5399999999973 +#define IQ_F_VALUE_MINUS_12_53 -10510926 // hz = -12.5299999999973 +#define IQ_F_VALUE_MINUS_12_52 -10502538 // hz = -12.5199999999973 +#define IQ_F_VALUE_MINUS_12_51 -10494149 // hz = -12.5099999999973 +#define IQ_F_VALUE_MINUS_12_50 -10485760 // hz = -12.4999999999973 +#define IQ_F_VALUE_MINUS_12_49 -10477372 // hz = -12.4899999999973 +#define IQ_F_VALUE_MINUS_12_48 -10468983 // hz = -12.4799999999973 +#define IQ_F_VALUE_MINUS_12_47 -10460595 // hz = -12.4699999999973 +#define IQ_F_VALUE_MINUS_12_46 -10452206 // hz = -12.4599999999973 +#define IQ_F_VALUE_MINUS_12_45 -10443817 // hz = -12.4499999999973 +#define IQ_F_VALUE_MINUS_12_44 -10435429 // hz = -12.4399999999973 +#define IQ_F_VALUE_MINUS_12_43 -10427040 // hz = -12.4299999999973 +#define IQ_F_VALUE_MINUS_12_42 -10418652 // hz = -12.4199999999973 +#define IQ_F_VALUE_MINUS_12_41 -10410263 // hz = -12.4099999999973 +#define IQ_F_VALUE_MINUS_12_40 -10401874 // hz = -12.3999999999972 +#define IQ_F_VALUE_MINUS_12_39 -10393486 // hz = -12.3899999999972 +#define IQ_F_VALUE_MINUS_12_38 -10385097 // hz = -12.3799999999972 +#define IQ_F_VALUE_MINUS_12_37 -10376709 // hz = -12.3699999999972 +#define IQ_F_VALUE_MINUS_12_36 -10368320 // hz = -12.3599999999972 +#define IQ_F_VALUE_MINUS_12_35 -10359931 // hz = -12.3499999999972 +#define IQ_F_VALUE_MINUS_12_34 -10351543 // hz = -12.3399999999972 +#define IQ_F_VALUE_MINUS_12_33 -10343154 // hz = -12.3299999999972 +#define IQ_F_VALUE_MINUS_12_32 -10334766 // hz = -12.3199999999972 +#define IQ_F_VALUE_MINUS_12_31 -10326377 // hz = -12.3099999999972 +#define IQ_F_VALUE_MINUS_12_30 -10317988 // hz = -12.2999999999972 +#define IQ_F_VALUE_MINUS_12_29 -10309600 // hz = -12.2899999999972 +#define IQ_F_VALUE_MINUS_12_28 -10301211 // hz = -12.2799999999972 +#define IQ_F_VALUE_MINUS_12_27 -10292823 // hz = -12.2699999999972 +#define IQ_F_VALUE_MINUS_12_26 -10284434 // hz = -12.2599999999972 +#define IQ_F_VALUE_MINUS_12_25 -10276045 // hz = -12.2499999999972 +#define IQ_F_VALUE_MINUS_12_24 -10267657 // hz = -12.2399999999972 +#define IQ_F_VALUE_MINUS_12_23 -10259268 // hz = -12.2299999999972 +#define IQ_F_VALUE_MINUS_12_22 -10250879 // hz = -12.2199999999972 +#define IQ_F_VALUE_MINUS_12_21 -10242491 // hz = -12.2099999999972 +#define IQ_F_VALUE_MINUS_12_20 -10234102 // hz = -12.1999999999972 +#define IQ_F_VALUE_MINUS_12_19 -10225714 // hz = -12.1899999999972 +#define IQ_F_VALUE_MINUS_12_18 -10217325 // hz = -12.1799999999972 +#define IQ_F_VALUE_MINUS_12_17 -10208936 // hz = -12.1699999999972 +#define IQ_F_VALUE_MINUS_12_16 -10200548 // hz = -12.1599999999972 +#define IQ_F_VALUE_MINUS_12_15 -10192159 // hz = -12.1499999999972 +#define IQ_F_VALUE_MINUS_12_14 -10183771 // hz = -12.1399999999972 +#define IQ_F_VALUE_MINUS_12_13 -10175382 // hz = -12.1299999999972 +#define IQ_F_VALUE_MINUS_12_12 -10166993 // hz = -12.1199999999972 +#define IQ_F_VALUE_MINUS_12_11 -10158605 // hz = -12.1099999999972 +#define IQ_F_VALUE_MINUS_12_10 -10150216 // hz = -12.0999999999972 +#define IQ_F_VALUE_MINUS_12_09 -10141828 // hz = -12.0899999999972 +#define IQ_F_VALUE_MINUS_12_08 -10133439 // hz = -12.0799999999972 +#define IQ_F_VALUE_MINUS_12_07 -10125050 // hz = -12.0699999999972 +#define IQ_F_VALUE_MINUS_12_06 -10116662 // hz = -12.0599999999972 +#define IQ_F_VALUE_MINUS_12_05 -10108273 // hz = -12.0499999999972 +#define IQ_F_VALUE_MINUS_12_04 -10099885 // hz = -12.0399999999972 +#define IQ_F_VALUE_MINUS_12_03 -10091496 // hz = -12.0299999999972 +#define IQ_F_VALUE_MINUS_12_02 -10083107 // hz = -12.0199999999972 +#define IQ_F_VALUE_MINUS_12_01 -10074719 // hz = -12.0099999999972 +#define IQ_F_VALUE_MINUS_12_00 -10066330 // hz = -11.9999999999972 +#define IQ_F_VALUE_MINUS_11_99 -10057941 // hz = -11.9899999999972 +#define IQ_F_VALUE_MINUS_11_98 -10049553 // hz = -11.9799999999972 +#define IQ_F_VALUE_MINUS_11_97 -10041164 // hz = -11.9699999999972 +#define IQ_F_VALUE_MINUS_11_96 -10032776 // hz = -11.9599999999972 +#define IQ_F_VALUE_MINUS_11_95 -10024387 // hz = -11.9499999999972 +#define IQ_F_VALUE_MINUS_11_94 -10015998 // hz = -11.9399999999972 +#define IQ_F_VALUE_MINUS_11_93 -10007610 // hz = -11.9299999999972 +#define IQ_F_VALUE_MINUS_11_92 -9999221 // hz = -11.9199999999972 +#define IQ_F_VALUE_MINUS_11_91 -9990833 // hz = -11.9099999999972 +#define IQ_F_VALUE_MINUS_11_90 -9982444 // hz = -11.8999999999972 +#define IQ_F_VALUE_MINUS_11_89 -9974055 // hz = -11.8899999999972 +#define IQ_F_VALUE_MINUS_11_88 -9965667 // hz = -11.8799999999972 +#define IQ_F_VALUE_MINUS_11_87 -9957278 // hz = -11.8699999999972 +#define IQ_F_VALUE_MINUS_11_86 -9948890 // hz = -11.8599999999972 +#define IQ_F_VALUE_MINUS_11_85 -9940501 // hz = -11.8499999999972 +#define IQ_F_VALUE_MINUS_11_84 -9932112 // hz = -11.8399999999972 +#define IQ_F_VALUE_MINUS_11_83 -9923724 // hz = -11.8299999999972 +#define IQ_F_VALUE_MINUS_11_82 -9915335 // hz = -11.8199999999972 +#define IQ_F_VALUE_MINUS_11_81 -9906947 // hz = -11.8099999999972 +#define IQ_F_VALUE_MINUS_11_80 -9898558 // hz = -11.7999999999972 +#define IQ_F_VALUE_MINUS_11_79 -9890169 // hz = -11.7899999999972 +#define IQ_F_VALUE_MINUS_11_78 -9881781 // hz = -11.7799999999972 +#define IQ_F_VALUE_MINUS_11_77 -9873392 // hz = -11.7699999999972 +#define IQ_F_VALUE_MINUS_11_76 -9865004 // hz = -11.7599999999971 +#define IQ_F_VALUE_MINUS_11_75 -9856615 // hz = -11.7499999999971 +#define IQ_F_VALUE_MINUS_11_74 -9848226 // hz = -11.7399999999971 +#define IQ_F_VALUE_MINUS_11_73 -9839838 // hz = -11.7299999999971 +#define IQ_F_VALUE_MINUS_11_72 -9831449 // hz = -11.7199999999971 +#define IQ_F_VALUE_MINUS_11_71 -9823060 // hz = -11.7099999999971 +#define IQ_F_VALUE_MINUS_11_70 -9814672 // hz = -11.6999999999971 +#define IQ_F_VALUE_MINUS_11_69 -9806283 // hz = -11.6899999999971 +#define IQ_F_VALUE_MINUS_11_68 -9797895 // hz = -11.6799999999971 +#define IQ_F_VALUE_MINUS_11_67 -9789506 // hz = -11.6699999999971 +#define IQ_F_VALUE_MINUS_11_66 -9781117 // hz = -11.6599999999971 +#define IQ_F_VALUE_MINUS_11_65 -9772729 // hz = -11.6499999999971 +#define IQ_F_VALUE_MINUS_11_64 -9764340 // hz = -11.6399999999971 +#define IQ_F_VALUE_MINUS_11_63 -9755952 // hz = -11.6299999999971 +#define IQ_F_VALUE_MINUS_11_62 -9747563 // hz = -11.6199999999971 +#define IQ_F_VALUE_MINUS_11_61 -9739174 // hz = -11.6099999999971 +#define IQ_F_VALUE_MINUS_11_60 -9730786 // hz = -11.5999999999971 +#define IQ_F_VALUE_MINUS_11_59 -9722397 // hz = -11.5899999999971 +#define IQ_F_VALUE_MINUS_11_58 -9714009 // hz = -11.5799999999971 +#define IQ_F_VALUE_MINUS_11_57 -9705620 // hz = -11.5699999999971 +#define IQ_F_VALUE_MINUS_11_56 -9697231 // hz = -11.5599999999971 +#define IQ_F_VALUE_MINUS_11_55 -9688843 // hz = -11.5499999999971 +#define IQ_F_VALUE_MINUS_11_54 -9680454 // hz = -11.5399999999971 +#define IQ_F_VALUE_MINUS_11_53 -9672066 // hz = -11.5299999999971 +#define IQ_F_VALUE_MINUS_11_52 -9663677 // hz = -11.5199999999971 +#define IQ_F_VALUE_MINUS_11_51 -9655288 // hz = -11.5099999999971 +#define IQ_F_VALUE_MINUS_11_50 -9646900 // hz = -11.4999999999971 +#define IQ_F_VALUE_MINUS_11_49 -9638511 // hz = -11.4899999999971 +#define IQ_F_VALUE_MINUS_11_48 -9630122 // hz = -11.4799999999971 +#define IQ_F_VALUE_MINUS_11_47 -9621734 // hz = -11.4699999999971 +#define IQ_F_VALUE_MINUS_11_46 -9613345 // hz = -11.4599999999971 +#define IQ_F_VALUE_MINUS_11_45 -9604957 // hz = -11.4499999999971 +#define IQ_F_VALUE_MINUS_11_44 -9596568 // hz = -11.4399999999971 +#define IQ_F_VALUE_MINUS_11_43 -9588179 // hz = -11.4299999999971 +#define IQ_F_VALUE_MINUS_11_42 -9579791 // hz = -11.4199999999971 +#define IQ_F_VALUE_MINUS_11_41 -9571402 // hz = -11.4099999999971 +#define IQ_F_VALUE_MINUS_11_40 -9563014 // hz = -11.3999999999971 +#define IQ_F_VALUE_MINUS_11_39 -9554625 // hz = -11.3899999999971 +#define IQ_F_VALUE_MINUS_11_38 -9546236 // hz = -11.3799999999971 +#define IQ_F_VALUE_MINUS_11_37 -9537848 // hz = -11.3699999999971 +#define IQ_F_VALUE_MINUS_11_36 -9529459 // hz = -11.3599999999971 +#define IQ_F_VALUE_MINUS_11_35 -9521071 // hz = -11.3499999999971 +#define IQ_F_VALUE_MINUS_11_34 -9512682 // hz = -11.3399999999971 +#define IQ_F_VALUE_MINUS_11_33 -9504293 // hz = -11.3299999999971 +#define IQ_F_VALUE_MINUS_11_32 -9495905 // hz = -11.3199999999971 +#define IQ_F_VALUE_MINUS_11_31 -9487516 // hz = -11.3099999999971 +#define IQ_F_VALUE_MINUS_11_30 -9479128 // hz = -11.2999999999971 +#define IQ_F_VALUE_MINUS_11_29 -9470739 // hz = -11.2899999999971 +#define IQ_F_VALUE_MINUS_11_28 -9462350 // hz = -11.2799999999971 +#define IQ_F_VALUE_MINUS_11_27 -9453962 // hz = -11.2699999999971 +#define IQ_F_VALUE_MINUS_11_26 -9445573 // hz = -11.2599999999971 +#define IQ_F_VALUE_MINUS_11_25 -9437184 // hz = -11.2499999999971 +#define IQ_F_VALUE_MINUS_11_24 -9428796 // hz = -11.2399999999971 +#define IQ_F_VALUE_MINUS_11_23 -9420407 // hz = -11.2299999999971 +#define IQ_F_VALUE_MINUS_11_22 -9412019 // hz = -11.2199999999971 +#define IQ_F_VALUE_MINUS_11_21 -9403630 // hz = -11.2099999999971 +#define IQ_F_VALUE_MINUS_11_20 -9395241 // hz = -11.1999999999971 +#define IQ_F_VALUE_MINUS_11_19 -9386853 // hz = -11.1899999999971 +#define IQ_F_VALUE_MINUS_11_18 -9378464 // hz = -11.1799999999971 +#define IQ_F_VALUE_MINUS_11_17 -9370076 // hz = -11.1699999999971 +#define IQ_F_VALUE_MINUS_11_16 -9361687 // hz = -11.1599999999971 +#define IQ_F_VALUE_MINUS_11_15 -9353298 // hz = -11.1499999999971 +#define IQ_F_VALUE_MINUS_11_14 -9344910 // hz = -11.1399999999971 +#define IQ_F_VALUE_MINUS_11_13 -9336521 // hz = -11.1299999999971 +#define IQ_F_VALUE_MINUS_11_12 -9328133 // hz = -11.119999999997 +#define IQ_F_VALUE_MINUS_11_11 -9319744 // hz = -11.109999999997 +#define IQ_F_VALUE_MINUS_11_10 -9311355 // hz = -11.099999999997 +#define IQ_F_VALUE_MINUS_11_09 -9302967 // hz = -11.089999999997 +#define IQ_F_VALUE_MINUS_11_08 -9294578 // hz = -11.079999999997 +#define IQ_F_VALUE_MINUS_11_07 -9286190 // hz = -11.069999999997 +#define IQ_F_VALUE_MINUS_11_06 -9277801 // hz = -11.059999999997 +#define IQ_F_VALUE_MINUS_11_05 -9269412 // hz = -11.049999999997 +#define IQ_F_VALUE_MINUS_11_04 -9261024 // hz = -11.039999999997 +#define IQ_F_VALUE_MINUS_11_03 -9252635 // hz = -11.029999999997 +#define IQ_F_VALUE_MINUS_11_02 -9244247 // hz = -11.019999999997 +#define IQ_F_VALUE_MINUS_11_01 -9235858 // hz = -11.009999999997 +#define IQ_F_VALUE_MINUS_11_00 -9227469 // hz = -10.999999999997 +#define IQ_F_VALUE_MINUS_10_99 -9219081 // hz = -10.989999999997 +#define IQ_F_VALUE_MINUS_10_98 -9210692 // hz = -10.979999999997 +#define IQ_F_VALUE_MINUS_10_97 -9202303 // hz = -10.969999999997 +#define IQ_F_VALUE_MINUS_10_96 -9193915 // hz = -10.959999999997 +#define IQ_F_VALUE_MINUS_10_95 -9185526 // hz = -10.949999999997 +#define IQ_F_VALUE_MINUS_10_94 -9177138 // hz = -10.939999999997 +#define IQ_F_VALUE_MINUS_10_93 -9168749 // hz = -10.929999999997 +#define IQ_F_VALUE_MINUS_10_92 -9160360 // hz = -10.919999999997 +#define IQ_F_VALUE_MINUS_10_91 -9151972 // hz = -10.909999999997 +#define IQ_F_VALUE_MINUS_10_90 -9143583 // hz = -10.899999999997 +#define IQ_F_VALUE_MINUS_10_89 -9135195 // hz = -10.889999999997 +#define IQ_F_VALUE_MINUS_10_88 -9126806 // hz = -10.879999999997 +#define IQ_F_VALUE_MINUS_10_87 -9118417 // hz = -10.869999999997 +#define IQ_F_VALUE_MINUS_10_86 -9110029 // hz = -10.859999999997 +#define IQ_F_VALUE_MINUS_10_85 -9101640 // hz = -10.849999999997 +#define IQ_F_VALUE_MINUS_10_84 -9093252 // hz = -10.839999999997 +#define IQ_F_VALUE_MINUS_10_83 -9084863 // hz = -10.829999999997 +#define IQ_F_VALUE_MINUS_10_82 -9076474 // hz = -10.819999999997 +#define IQ_F_VALUE_MINUS_10_81 -9068086 // hz = -10.809999999997 +#define IQ_F_VALUE_MINUS_10_80 -9059697 // hz = -10.799999999997 +#define IQ_F_VALUE_MINUS_10_79 -9051309 // hz = -10.789999999997 +#define IQ_F_VALUE_MINUS_10_78 -9042920 // hz = -10.779999999997 +#define IQ_F_VALUE_MINUS_10_77 -9034531 // hz = -10.769999999997 +#define IQ_F_VALUE_MINUS_10_76 -9026143 // hz = -10.759999999997 +#define IQ_F_VALUE_MINUS_10_75 -9017754 // hz = -10.749999999997 +#define IQ_F_VALUE_MINUS_10_74 -9009365 // hz = -10.739999999997 +#define IQ_F_VALUE_MINUS_10_73 -9000977 // hz = -10.729999999997 +#define IQ_F_VALUE_MINUS_10_72 -8992588 // hz = -10.719999999997 +#define IQ_F_VALUE_MINUS_10_71 -8984200 // hz = -10.709999999997 +#define IQ_F_VALUE_MINUS_10_70 -8975811 // hz = -10.699999999997 +#define IQ_F_VALUE_MINUS_10_69 -8967422 // hz = -10.689999999997 +#define IQ_F_VALUE_MINUS_10_68 -8959034 // hz = -10.679999999997 +#define IQ_F_VALUE_MINUS_10_67 -8950645 // hz = -10.669999999997 +#define IQ_F_VALUE_MINUS_10_66 -8942257 // hz = -10.659999999997 +#define IQ_F_VALUE_MINUS_10_65 -8933868 // hz = -10.649999999997 +#define IQ_F_VALUE_MINUS_10_64 -8925479 // hz = -10.639999999997 +#define IQ_F_VALUE_MINUS_10_63 -8917091 // hz = -10.629999999997 +#define IQ_F_VALUE_MINUS_10_62 -8908702 // hz = -10.619999999997 +#define IQ_F_VALUE_MINUS_10_61 -8900314 // hz = -10.609999999997 +#define IQ_F_VALUE_MINUS_10_60 -8891925 // hz = -10.599999999997 +#define IQ_F_VALUE_MINUS_10_59 -8883536 // hz = -10.589999999997 +#define IQ_F_VALUE_MINUS_10_58 -8875148 // hz = -10.579999999997 +#define IQ_F_VALUE_MINUS_10_57 -8866759 // hz = -10.569999999997 +#define IQ_F_VALUE_MINUS_10_56 -8858371 // hz = -10.559999999997 +#define IQ_F_VALUE_MINUS_10_55 -8849982 // hz = -10.549999999997 +#define IQ_F_VALUE_MINUS_10_54 -8841593 // hz = -10.539999999997 +#define IQ_F_VALUE_MINUS_10_53 -8833205 // hz = -10.529999999997 +#define IQ_F_VALUE_MINUS_10_52 -8824816 // hz = -10.519999999997 +#define IQ_F_VALUE_MINUS_10_51 -8816428 // hz = -10.509999999997 +#define IQ_F_VALUE_MINUS_10_50 -8808039 // hz = -10.499999999997 +#define IQ_F_VALUE_MINUS_10_49 -8799650 // hz = -10.489999999997 +#define IQ_F_VALUE_MINUS_10_48 -8791262 // hz = -10.4799999999969 +#define IQ_F_VALUE_MINUS_10_47 -8782873 // hz = -10.4699999999969 +#define IQ_F_VALUE_MINUS_10_46 -8774484 // hz = -10.4599999999969 +#define IQ_F_VALUE_MINUS_10_45 -8766096 // hz = -10.4499999999969 +#define IQ_F_VALUE_MINUS_10_44 -8757707 // hz = -10.4399999999969 +#define IQ_F_VALUE_MINUS_10_43 -8749319 // hz = -10.4299999999969 +#define IQ_F_VALUE_MINUS_10_42 -8740930 // hz = -10.4199999999969 +#define IQ_F_VALUE_MINUS_10_41 -8732541 // hz = -10.4099999999969 +#define IQ_F_VALUE_MINUS_10_40 -8724153 // hz = -10.3999999999969 +#define IQ_F_VALUE_MINUS_10_39 -8715764 // hz = -10.3899999999969 +#define IQ_F_VALUE_MINUS_10_38 -8707376 // hz = -10.3799999999969 +#define IQ_F_VALUE_MINUS_10_37 -8698987 // hz = -10.3699999999969 +#define IQ_F_VALUE_MINUS_10_36 -8690598 // hz = -10.3599999999969 +#define IQ_F_VALUE_MINUS_10_35 -8682210 // hz = -10.3499999999969 +#define IQ_F_VALUE_MINUS_10_34 -8673821 // hz = -10.3399999999969 +#define IQ_F_VALUE_MINUS_10_33 -8665433 // hz = -10.3299999999969 +#define IQ_F_VALUE_MINUS_10_32 -8657044 // hz = -10.3199999999969 +#define IQ_F_VALUE_MINUS_10_31 -8648655 // hz = -10.3099999999969 +#define IQ_F_VALUE_MINUS_10_30 -8640267 // hz = -10.2999999999969 +#define IQ_F_VALUE_MINUS_10_29 -8631878 // hz = -10.2899999999969 +#define IQ_F_VALUE_MINUS_10_28 -8623490 // hz = -10.2799999999969 +#define IQ_F_VALUE_MINUS_10_27 -8615101 // hz = -10.2699999999969 +#define IQ_F_VALUE_MINUS_10_26 -8606712 // hz = -10.2599999999969 +#define IQ_F_VALUE_MINUS_10_25 -8598324 // hz = -10.2499999999969 +#define IQ_F_VALUE_MINUS_10_24 -8589935 // hz = -10.2399999999969 +#define IQ_F_VALUE_MINUS_10_23 -8581546 // hz = -10.2299999999969 +#define IQ_F_VALUE_MINUS_10_22 -8573158 // hz = -10.2199999999969 +#define IQ_F_VALUE_MINUS_10_21 -8564769 // hz = -10.2099999999969 +#define IQ_F_VALUE_MINUS_10_20 -8556381 // hz = -10.1999999999969 +#define IQ_F_VALUE_MINUS_10_19 -8547992 // hz = -10.1899999999969 +#define IQ_F_VALUE_MINUS_10_18 -8539603 // hz = -10.1799999999969 +#define IQ_F_VALUE_MINUS_10_17 -8531215 // hz = -10.1699999999969 +#define IQ_F_VALUE_MINUS_10_16 -8522826 // hz = -10.1599999999969 +#define IQ_F_VALUE_MINUS_10_15 -8514438 // hz = -10.1499999999969 +#define IQ_F_VALUE_MINUS_10_14 -8506049 // hz = -10.1399999999969 +#define IQ_F_VALUE_MINUS_10_13 -8497660 // hz = -10.1299999999969 +#define IQ_F_VALUE_MINUS_10_12 -8489272 // hz = -10.1199999999969 +#define IQ_F_VALUE_MINUS_10_11 -8480883 // hz = -10.1099999999969 +#define IQ_F_VALUE_MINUS_10_10 -8472495 // hz = -10.0999999999969 +#define IQ_F_VALUE_MINUS_10_09 -8464106 // hz = -10.0899999999969 +#define IQ_F_VALUE_MINUS_10_08 -8455717 // hz = -10.0799999999969 +#define IQ_F_VALUE_MINUS_10_07 -8447329 // hz = -10.0699999999969 +#define IQ_F_VALUE_MINUS_10_06 -8438940 // hz = -10.0599999999969 +#define IQ_F_VALUE_MINUS_10_05 -8430552 // hz = -10.0499999999969 +#define IQ_F_VALUE_MINUS_10_04 -8422163 // hz = -10.0399999999969 +#define IQ_F_VALUE_MINUS_10_03 -8413774 // hz = -10.0299999999969 +#define IQ_F_VALUE_MINUS_10_02 -8405386 // hz = -10.0199999999969 +#define IQ_F_VALUE_MINUS_10_01 -8396997 // hz = -10.0099999999969 +#define IQ_F_VALUE_MINUS_10_00 -8388608 // hz = -9.9999999999969 +#define IQ_F_VALUE_MINUS_9_99 -8380220 // hz = -9.9899999999969 +#define IQ_F_VALUE_MINUS_9_98 -8371831 // hz = -9.9799999999969 +#define IQ_F_VALUE_MINUS_9_97 -8363443 // hz = -9.9699999999969 +#define IQ_F_VALUE_MINUS_9_96 -8355054 // hz = -9.9599999999969 +#define IQ_F_VALUE_MINUS_9_95 -8346665 // hz = -9.9499999999969 +#define IQ_F_VALUE_MINUS_9_94 -8338277 // hz = -9.9399999999969 +#define IQ_F_VALUE_MINUS_9_93 -8329888 // hz = -9.9299999999969 +#define IQ_F_VALUE_MINUS_9_92 -8321500 // hz = -9.9199999999969 +#define IQ_F_VALUE_MINUS_9_91 -8313111 // hz = -9.9099999999969 +#define IQ_F_VALUE_MINUS_9_90 -8304722 // hz = -9.8999999999969 +#define IQ_F_VALUE_MINUS_9_89 -8296334 // hz = -9.8899999999969 +#define IQ_F_VALUE_MINUS_9_88 -8287945 // hz = -9.8799999999969 +#define IQ_F_VALUE_MINUS_9_87 -8279557 // hz = -9.8699999999969 +#define IQ_F_VALUE_MINUS_9_86 -8271168 // hz = -9.8599999999969 +#define IQ_F_VALUE_MINUS_9_85 -8262779 // hz = -9.8499999999969 +#define IQ_F_VALUE_MINUS_9_84 -8254391 // hz = -9.8399999999968 +#define IQ_F_VALUE_MINUS_9_83 -8246002 // hz = -9.8299999999968 +#define IQ_F_VALUE_MINUS_9_82 -8237614 // hz = -9.8199999999968 +#define IQ_F_VALUE_MINUS_9_81 -8229225 // hz = -9.8099999999968 +#define IQ_F_VALUE_MINUS_9_80 -8220836 // hz = -9.7999999999968 +#define IQ_F_VALUE_MINUS_9_79 -8212448 // hz = -9.7899999999968 +#define IQ_F_VALUE_MINUS_9_78 -8204059 // hz = -9.7799999999968 +#define IQ_F_VALUE_MINUS_9_77 -8195671 // hz = -9.7699999999968 +#define IQ_F_VALUE_MINUS_9_76 -8187282 // hz = -9.7599999999968 +#define IQ_F_VALUE_MINUS_9_75 -8178893 // hz = -9.7499999999968 +#define IQ_F_VALUE_MINUS_9_74 -8170505 // hz = -9.7399999999968 +#define IQ_F_VALUE_MINUS_9_73 -8162116 // hz = -9.7299999999968 +#define IQ_F_VALUE_MINUS_9_72 -8153727 // hz = -9.7199999999968 +#define IQ_F_VALUE_MINUS_9_71 -8145339 // hz = -9.7099999999968 +#define IQ_F_VALUE_MINUS_9_70 -8136950 // hz = -9.6999999999968 +#define IQ_F_VALUE_MINUS_9_69 -8128562 // hz = -9.6899999999968 +#define IQ_F_VALUE_MINUS_9_68 -8120173 // hz = -9.6799999999968 +#define IQ_F_VALUE_MINUS_9_67 -8111784 // hz = -9.6699999999968 +#define IQ_F_VALUE_MINUS_9_66 -8103396 // hz = -9.6599999999968 +#define IQ_F_VALUE_MINUS_9_65 -8095007 // hz = -9.6499999999968 +#define IQ_F_VALUE_MINUS_9_64 -8086619 // hz = -9.6399999999968 +#define IQ_F_VALUE_MINUS_9_63 -8078230 // hz = -9.6299999999968 +#define IQ_F_VALUE_MINUS_9_62 -8069841 // hz = -9.6199999999968 +#define IQ_F_VALUE_MINUS_9_61 -8061453 // hz = -9.6099999999968 +#define IQ_F_VALUE_MINUS_9_60 -8053064 // hz = -9.5999999999968 +#define IQ_F_VALUE_MINUS_9_59 -8044676 // hz = -9.5899999999968 +#define IQ_F_VALUE_MINUS_9_58 -8036287 // hz = -9.5799999999968 +#define IQ_F_VALUE_MINUS_9_57 -8027898 // hz = -9.5699999999968 +#define IQ_F_VALUE_MINUS_9_56 -8019510 // hz = -9.5599999999968 +#define IQ_F_VALUE_MINUS_9_55 -8011121 // hz = -9.5499999999968 +#define IQ_F_VALUE_MINUS_9_54 -8002733 // hz = -9.5399999999968 +#define IQ_F_VALUE_MINUS_9_53 -7994344 // hz = -9.5299999999968 +#define IQ_F_VALUE_MINUS_9_52 -7985955 // hz = -9.5199999999968 +#define IQ_F_VALUE_MINUS_9_51 -7977567 // hz = -9.5099999999968 +#define IQ_F_VALUE_MINUS_9_50 -7969178 // hz = -9.4999999999968 +#define IQ_F_VALUE_MINUS_9_49 -7960789 // hz = -9.4899999999968 +#define IQ_F_VALUE_MINUS_9_48 -7952401 // hz = -9.4799999999968 +#define IQ_F_VALUE_MINUS_9_47 -7944012 // hz = -9.4699999999968 +#define IQ_F_VALUE_MINUS_9_46 -7935624 // hz = -9.4599999999968 +#define IQ_F_VALUE_MINUS_9_45 -7927235 // hz = -9.4499999999968 +#define IQ_F_VALUE_MINUS_9_44 -7918846 // hz = -9.4399999999968 +#define IQ_F_VALUE_MINUS_9_43 -7910458 // hz = -9.4299999999968 +#define IQ_F_VALUE_MINUS_9_42 -7902069 // hz = -9.4199999999968 +#define IQ_F_VALUE_MINUS_9_41 -7893681 // hz = -9.4099999999968 +#define IQ_F_VALUE_MINUS_9_40 -7885292 // hz = -9.3999999999968 +#define IQ_F_VALUE_MINUS_9_39 -7876903 // hz = -9.3899999999968 +#define IQ_F_VALUE_MINUS_9_38 -7868515 // hz = -9.3799999999968 +#define IQ_F_VALUE_MINUS_9_37 -7860126 // hz = -9.3699999999968 +#define IQ_F_VALUE_MINUS_9_36 -7851738 // hz = -9.3599999999968 +#define IQ_F_VALUE_MINUS_9_35 -7843349 // hz = -9.3499999999968 +#define IQ_F_VALUE_MINUS_9_34 -7834960 // hz = -9.3399999999968 +#define IQ_F_VALUE_MINUS_9_33 -7826572 // hz = -9.3299999999968 +#define IQ_F_VALUE_MINUS_9_32 -7818183 // hz = -9.3199999999968 +#define IQ_F_VALUE_MINUS_9_31 -7809795 // hz = -9.3099999999968 +#define IQ_F_VALUE_MINUS_9_30 -7801406 // hz = -9.2999999999968 +#define IQ_F_VALUE_MINUS_9_29 -7793017 // hz = -9.2899999999968 +#define IQ_F_VALUE_MINUS_9_28 -7784629 // hz = -9.2799999999968 +#define IQ_F_VALUE_MINUS_9_27 -7776240 // hz = -9.2699999999968 +#define IQ_F_VALUE_MINUS_9_26 -7767852 // hz = -9.2599999999968 +#define IQ_F_VALUE_MINUS_9_25 -7759463 // hz = -9.2499999999968 +#define IQ_F_VALUE_MINUS_9_24 -7751074 // hz = -9.2399999999968 +#define IQ_F_VALUE_MINUS_9_23 -7742686 // hz = -9.2299999999968 +#define IQ_F_VALUE_MINUS_9_22 -7734297 // hz = -9.2199999999968 +#define IQ_F_VALUE_MINUS_9_21 -7725908 // hz = -9.2099999999968 +#define IQ_F_VALUE_MINUS_9_20 -7717520 // hz = -9.1999999999967 +#define IQ_F_VALUE_MINUS_9_19 -7709131 // hz = -9.1899999999967 +#define IQ_F_VALUE_MINUS_9_18 -7700743 // hz = -9.1799999999967 +#define IQ_F_VALUE_MINUS_9_17 -7692354 // hz = -9.1699999999967 +#define IQ_F_VALUE_MINUS_9_16 -7683965 // hz = -9.1599999999967 +#define IQ_F_VALUE_MINUS_9_15 -7675577 // hz = -9.1499999999967 +#define IQ_F_VALUE_MINUS_9_14 -7667188 // hz = -9.1399999999967 +#define IQ_F_VALUE_MINUS_9_13 -7658800 // hz = -9.1299999999967 +#define IQ_F_VALUE_MINUS_9_12 -7650411 // hz = -9.1199999999967 +#define IQ_F_VALUE_MINUS_9_11 -7642022 // hz = -9.1099999999967 +#define IQ_F_VALUE_MINUS_9_10 -7633634 // hz = -9.0999999999967 +#define IQ_F_VALUE_MINUS_9_09 -7625245 // hz = -9.0899999999967 +#define IQ_F_VALUE_MINUS_9_08 -7616857 // hz = -9.0799999999967 +#define IQ_F_VALUE_MINUS_9_07 -7608468 // hz = -9.0699999999967 +#define IQ_F_VALUE_MINUS_9_06 -7600079 // hz = -9.0599999999967 +#define IQ_F_VALUE_MINUS_9_05 -7591691 // hz = -9.0499999999967 +#define IQ_F_VALUE_MINUS_9_04 -7583302 // hz = -9.0399999999967 +#define IQ_F_VALUE_MINUS_9_03 -7574914 // hz = -9.0299999999967 +#define IQ_F_VALUE_MINUS_9_02 -7566525 // hz = -9.0199999999967 +#define IQ_F_VALUE_MINUS_9_01 -7558136 // hz = -9.0099999999967 +#define IQ_F_VALUE_MINUS_9_00 -7549748 // hz = -8.9999999999967 +#define IQ_F_VALUE_MINUS_8_99 -7541359 // hz = -8.9899999999967 +#define IQ_F_VALUE_MINUS_8_98 -7532970 // hz = -8.9799999999967 +#define IQ_F_VALUE_MINUS_8_97 -7524582 // hz = -8.9699999999967 +#define IQ_F_VALUE_MINUS_8_96 -7516193 // hz = -8.9599999999967 +#define IQ_F_VALUE_MINUS_8_95 -7507805 // hz = -8.9499999999967 +#define IQ_F_VALUE_MINUS_8_94 -7499416 // hz = -8.9399999999967 +#define IQ_F_VALUE_MINUS_8_93 -7491027 // hz = -8.9299999999967 +#define IQ_F_VALUE_MINUS_8_92 -7482639 // hz = -8.9199999999967 +#define IQ_F_VALUE_MINUS_8_91 -7474250 // hz = -8.9099999999967 +#define IQ_F_VALUE_MINUS_8_90 -7465862 // hz = -8.8999999999967 +#define IQ_F_VALUE_MINUS_8_89 -7457473 // hz = -8.8899999999967 +#define IQ_F_VALUE_MINUS_8_88 -7449084 // hz = -8.8799999999967 +#define IQ_F_VALUE_MINUS_8_87 -7440696 // hz = -8.8699999999967 +#define IQ_F_VALUE_MINUS_8_86 -7432307 // hz = -8.8599999999967 +#define IQ_F_VALUE_MINUS_8_85 -7423919 // hz = -8.8499999999967 +#define IQ_F_VALUE_MINUS_8_84 -7415530 // hz = -8.8399999999967 +#define IQ_F_VALUE_MINUS_8_83 -7407141 // hz = -8.8299999999967 +#define IQ_F_VALUE_MINUS_8_82 -7398753 // hz = -8.8199999999967 +#define IQ_F_VALUE_MINUS_8_81 -7390364 // hz = -8.8099999999967 +#define IQ_F_VALUE_MINUS_8_80 -7381976 // hz = -8.7999999999967 +#define IQ_F_VALUE_MINUS_8_79 -7373587 // hz = -8.7899999999967 +#define IQ_F_VALUE_MINUS_8_78 -7365198 // hz = -8.7799999999967 +#define IQ_F_VALUE_MINUS_8_77 -7356810 // hz = -8.7699999999967 +#define IQ_F_VALUE_MINUS_8_76 -7348421 // hz = -8.7599999999967 +#define IQ_F_VALUE_MINUS_8_75 -7340032 // hz = -8.7499999999967 +#define IQ_F_VALUE_MINUS_8_74 -7331644 // hz = -8.7399999999967 +#define IQ_F_VALUE_MINUS_8_73 -7323255 // hz = -8.7299999999967 +#define IQ_F_VALUE_MINUS_8_72 -7314867 // hz = -8.7199999999967 +#define IQ_F_VALUE_MINUS_8_71 -7306478 // hz = -8.7099999999967 +#define IQ_F_VALUE_MINUS_8_70 -7298089 // hz = -8.6999999999967 +#define IQ_F_VALUE_MINUS_8_69 -7289701 // hz = -8.6899999999967 +#define IQ_F_VALUE_MINUS_8_68 -7281312 // hz = -8.6799999999967 +#define IQ_F_VALUE_MINUS_8_67 -7272924 // hz = -8.6699999999967 +#define IQ_F_VALUE_MINUS_8_66 -7264535 // hz = -8.6599999999967 +#define IQ_F_VALUE_MINUS_8_65 -7256146 // hz = -8.6499999999967 +#define IQ_F_VALUE_MINUS_8_64 -7247758 // hz = -8.6399999999967 +#define IQ_F_VALUE_MINUS_8_63 -7239369 // hz = -8.6299999999967 +#define IQ_F_VALUE_MINUS_8_62 -7230981 // hz = -8.6199999999967 +#define IQ_F_VALUE_MINUS_8_61 -7222592 // hz = -8.6099999999967 +#define IQ_F_VALUE_MINUS_8_60 -7214203 // hz = -8.5999999999967 +#define IQ_F_VALUE_MINUS_8_59 -7205815 // hz = -8.5899999999967 +#define IQ_F_VALUE_MINUS_8_58 -7197426 // hz = -8.5799999999967 +#define IQ_F_VALUE_MINUS_8_57 -7189038 // hz = -8.5699999999967 +#define IQ_F_VALUE_MINUS_8_56 -7180649 // hz = -8.5599999999966 +#define IQ_F_VALUE_MINUS_8_55 -7172260 // hz = -8.5499999999966 +#define IQ_F_VALUE_MINUS_8_54 -7163872 // hz = -8.5399999999966 +#define IQ_F_VALUE_MINUS_8_53 -7155483 // hz = -8.5299999999966 +#define IQ_F_VALUE_MINUS_8_52 -7147095 // hz = -8.5199999999966 +#define IQ_F_VALUE_MINUS_8_51 -7138706 // hz = -8.5099999999966 +#define IQ_F_VALUE_MINUS_8_50 -7130317 // hz = -8.4999999999966 +#define IQ_F_VALUE_MINUS_8_49 -7121929 // hz = -8.4899999999966 +#define IQ_F_VALUE_MINUS_8_48 -7113540 // hz = -8.4799999999966 +#define IQ_F_VALUE_MINUS_8_47 -7105151 // hz = -8.4699999999966 +#define IQ_F_VALUE_MINUS_8_46 -7096763 // hz = -8.4599999999966 +#define IQ_F_VALUE_MINUS_8_45 -7088374 // hz = -8.4499999999966 +#define IQ_F_VALUE_MINUS_8_44 -7079986 // hz = -8.4399999999966 +#define IQ_F_VALUE_MINUS_8_43 -7071597 // hz = -8.4299999999966 +#define IQ_F_VALUE_MINUS_8_42 -7063208 // hz = -8.4199999999966 +#define IQ_F_VALUE_MINUS_8_41 -7054820 // hz = -8.4099999999966 +#define IQ_F_VALUE_MINUS_8_40 -7046431 // hz = -8.3999999999966 +#define IQ_F_VALUE_MINUS_8_39 -7038043 // hz = -8.3899999999966 +#define IQ_F_VALUE_MINUS_8_38 -7029654 // hz = -8.3799999999966 +#define IQ_F_VALUE_MINUS_8_37 -7021265 // hz = -8.3699999999966 +#define IQ_F_VALUE_MINUS_8_36 -7012877 // hz = -8.3599999999966 +#define IQ_F_VALUE_MINUS_8_35 -7004488 // hz = -8.3499999999966 +#define IQ_F_VALUE_MINUS_8_34 -6996100 // hz = -8.3399999999966 +#define IQ_F_VALUE_MINUS_8_33 -6987711 // hz = -8.3299999999966 +#define IQ_F_VALUE_MINUS_8_32 -6979322 // hz = -8.3199999999966 +#define IQ_F_VALUE_MINUS_8_31 -6970934 // hz = -8.3099999999966 +#define IQ_F_VALUE_MINUS_8_30 -6962545 // hz = -8.2999999999966 +#define IQ_F_VALUE_MINUS_8_29 -6954157 // hz = -8.2899999999966 +#define IQ_F_VALUE_MINUS_8_28 -6945768 // hz = -8.2799999999966 +#define IQ_F_VALUE_MINUS_8_27 -6937379 // hz = -8.2699999999966 +#define IQ_F_VALUE_MINUS_8_26 -6928991 // hz = -8.2599999999966 +#define IQ_F_VALUE_MINUS_8_25 -6920602 // hz = -8.2499999999966 +#define IQ_F_VALUE_MINUS_8_24 -6912213 // hz = -8.2399999999966 +#define IQ_F_VALUE_MINUS_8_23 -6903825 // hz = -8.2299999999966 +#define IQ_F_VALUE_MINUS_8_22 -6895436 // hz = -8.2199999999966 +#define IQ_F_VALUE_MINUS_8_21 -6887048 // hz = -8.2099999999966 +#define IQ_F_VALUE_MINUS_8_20 -6878659 // hz = -8.1999999999966 +#define IQ_F_VALUE_MINUS_8_19 -6870270 // hz = -8.1899999999966 +#define IQ_F_VALUE_MINUS_8_18 -6861882 // hz = -8.1799999999966 +#define IQ_F_VALUE_MINUS_8_17 -6853493 // hz = -8.1699999999966 +#define IQ_F_VALUE_MINUS_8_16 -6845105 // hz = -8.1599999999966 +#define IQ_F_VALUE_MINUS_8_15 -6836716 // hz = -8.1499999999966 +#define IQ_F_VALUE_MINUS_8_14 -6828327 // hz = -8.1399999999966 +#define IQ_F_VALUE_MINUS_8_13 -6819939 // hz = -8.1299999999966 +#define IQ_F_VALUE_MINUS_8_12 -6811550 // hz = -8.1199999999966 +#define IQ_F_VALUE_MINUS_8_11 -6803162 // hz = -8.1099999999966 +#define IQ_F_VALUE_MINUS_8_10 -6794773 // hz = -8.0999999999966 +#define IQ_F_VALUE_MINUS_8_09 -6786384 // hz = -8.0899999999966 +#define IQ_F_VALUE_MINUS_8_08 -6777996 // hz = -8.0799999999966 +#define IQ_F_VALUE_MINUS_8_07 -6769607 // hz = -8.0699999999966 +#define IQ_F_VALUE_MINUS_8_06 -6761219 // hz = -8.0599999999966 +#define IQ_F_VALUE_MINUS_8_05 -6752830 // hz = -8.0499999999966 +#define IQ_F_VALUE_MINUS_8_04 -6744441 // hz = -8.0399999999966 +#define IQ_F_VALUE_MINUS_8_03 -6736053 // hz = -8.0299999999966 +#define IQ_F_VALUE_MINUS_8_02 -6727664 // hz = -8.0199999999966 +#define IQ_F_VALUE_MINUS_8_01 -6719276 // hz = -8.0099999999966 +#define IQ_F_VALUE_MINUS_8_00 -6710887 // hz = -7.9999999999966 +#define IQ_F_VALUE_MINUS_7_99 -6702498 // hz = -7.9899999999966 +#define IQ_F_VALUE_MINUS_7_98 -6694110 // hz = -7.9799999999966 +#define IQ_F_VALUE_MINUS_7_97 -6685721 // hz = -7.9699999999966 +#define IQ_F_VALUE_MINUS_7_96 -6677332 // hz = -7.9599999999966 +#define IQ_F_VALUE_MINUS_7_95 -6668944 // hz = -7.9499999999966 +#define IQ_F_VALUE_MINUS_7_94 -6660555 // hz = -7.9399999999966 +#define IQ_F_VALUE_MINUS_7_93 -6652167 // hz = -7.9299999999966 +#define IQ_F_VALUE_MINUS_7_92 -6643778 // hz = -7.9199999999965 +#define IQ_F_VALUE_MINUS_7_91 -6635389 // hz = -7.9099999999965 +#define IQ_F_VALUE_MINUS_7_90 -6627001 // hz = -7.8999999999965 +#define IQ_F_VALUE_MINUS_7_89 -6618612 // hz = -7.8899999999965 +#define IQ_F_VALUE_MINUS_7_88 -6610224 // hz = -7.8799999999965 +#define IQ_F_VALUE_MINUS_7_87 -6601835 // hz = -7.8699999999965 +#define IQ_F_VALUE_MINUS_7_86 -6593446 // hz = -7.8599999999965 +#define IQ_F_VALUE_MINUS_7_85 -6585058 // hz = -7.8499999999965 +#define IQ_F_VALUE_MINUS_7_84 -6576669 // hz = -7.8399999999965 +#define IQ_F_VALUE_MINUS_7_83 -6568281 // hz = -7.8299999999965 +#define IQ_F_VALUE_MINUS_7_82 -6559892 // hz = -7.8199999999965 +#define IQ_F_VALUE_MINUS_7_81 -6551503 // hz = -7.8099999999965 +#define IQ_F_VALUE_MINUS_7_80 -6543115 // hz = -7.7999999999965 +#define IQ_F_VALUE_MINUS_7_79 -6534726 // hz = -7.7899999999965 +#define IQ_F_VALUE_MINUS_7_78 -6526338 // hz = -7.7799999999965 +#define IQ_F_VALUE_MINUS_7_77 -6517949 // hz = -7.7699999999965 +#define IQ_F_VALUE_MINUS_7_76 -6509560 // hz = -7.7599999999965 +#define IQ_F_VALUE_MINUS_7_75 -6501172 // hz = -7.7499999999965 +#define IQ_F_VALUE_MINUS_7_74 -6492783 // hz = -7.7399999999965 +#define IQ_F_VALUE_MINUS_7_73 -6484394 // hz = -7.7299999999965 +#define IQ_F_VALUE_MINUS_7_72 -6476006 // hz = -7.7199999999965 +#define IQ_F_VALUE_MINUS_7_71 -6467617 // hz = -7.7099999999965 +#define IQ_F_VALUE_MINUS_7_70 -6459229 // hz = -7.6999999999965 +#define IQ_F_VALUE_MINUS_7_69 -6450840 // hz = -7.6899999999965 +#define IQ_F_VALUE_MINUS_7_68 -6442451 // hz = -7.6799999999965 +#define IQ_F_VALUE_MINUS_7_67 -6434063 // hz = -7.6699999999965 +#define IQ_F_VALUE_MINUS_7_66 -6425674 // hz = -7.6599999999965 +#define IQ_F_VALUE_MINUS_7_65 -6417286 // hz = -7.6499999999965 +#define IQ_F_VALUE_MINUS_7_64 -6408897 // hz = -7.6399999999965 +#define IQ_F_VALUE_MINUS_7_63 -6400508 // hz = -7.6299999999965 +#define IQ_F_VALUE_MINUS_7_62 -6392120 // hz = -7.6199999999965 +#define IQ_F_VALUE_MINUS_7_61 -6383731 // hz = -7.6099999999965 +#define IQ_F_VALUE_MINUS_7_60 -6375343 // hz = -7.5999999999965 +#define IQ_F_VALUE_MINUS_7_59 -6366954 // hz = -7.5899999999965 +#define IQ_F_VALUE_MINUS_7_58 -6358565 // hz = -7.5799999999965 +#define IQ_F_VALUE_MINUS_7_57 -6350177 // hz = -7.5699999999965 +#define IQ_F_VALUE_MINUS_7_56 -6341788 // hz = -7.5599999999965 +#define IQ_F_VALUE_MINUS_7_55 -6333400 // hz = -7.5499999999965 +#define IQ_F_VALUE_MINUS_7_54 -6325011 // hz = -7.5399999999965 +#define IQ_F_VALUE_MINUS_7_53 -6316622 // hz = -7.5299999999965 +#define IQ_F_VALUE_MINUS_7_52 -6308234 // hz = -7.5199999999965 +#define IQ_F_VALUE_MINUS_7_51 -6299845 // hz = -7.5099999999965 +#define IQ_F_VALUE_MINUS_7_50 -6291456 // hz = -7.4999999999965 +#define IQ_F_VALUE_MINUS_7_49 -6283068 // hz = -7.4899999999965 +#define IQ_F_VALUE_MINUS_7_48 -6274679 // hz = -7.4799999999965 +#define IQ_F_VALUE_MINUS_7_47 -6266291 // hz = -7.4699999999965 +#define IQ_F_VALUE_MINUS_7_46 -6257902 // hz = -7.4599999999965 +#define IQ_F_VALUE_MINUS_7_45 -6249513 // hz = -7.4499999999965 +#define IQ_F_VALUE_MINUS_7_44 -6241125 // hz = -7.4399999999965 +#define IQ_F_VALUE_MINUS_7_43 -6232736 // hz = -7.4299999999965 +#define IQ_F_VALUE_MINUS_7_42 -6224348 // hz = -7.4199999999965 +#define IQ_F_VALUE_MINUS_7_41 -6215959 // hz = -7.4099999999965 +#define IQ_F_VALUE_MINUS_7_40 -6207570 // hz = -7.3999999999965 +#define IQ_F_VALUE_MINUS_7_39 -6199182 // hz = -7.3899999999965 +#define IQ_F_VALUE_MINUS_7_38 -6190793 // hz = -7.3799999999965 +#define IQ_F_VALUE_MINUS_7_37 -6182405 // hz = -7.3699999999965 +#define IQ_F_VALUE_MINUS_7_36 -6174016 // hz = -7.3599999999965 +#define IQ_F_VALUE_MINUS_7_35 -6165627 // hz = -7.3499999999965 +#define IQ_F_VALUE_MINUS_7_34 -6157239 // hz = -7.3399999999965 +#define IQ_F_VALUE_MINUS_7_33 -6148850 // hz = -7.3299999999965 +#define IQ_F_VALUE_MINUS_7_32 -6140462 // hz = -7.3199999999965 +#define IQ_F_VALUE_MINUS_7_31 -6132073 // hz = -7.3099999999965 +#define IQ_F_VALUE_MINUS_7_30 -6123684 // hz = -7.2999999999965 +#define IQ_F_VALUE_MINUS_7_29 -6115296 // hz = -7.2899999999964 +#define IQ_F_VALUE_MINUS_7_28 -6106907 // hz = -7.2799999999964 +#define IQ_F_VALUE_MINUS_7_27 -6098519 // hz = -7.2699999999964 +#define IQ_F_VALUE_MINUS_7_26 -6090130 // hz = -7.2599999999964 +#define IQ_F_VALUE_MINUS_7_25 -6081741 // hz = -7.2499999999964 +#define IQ_F_VALUE_MINUS_7_24 -6073353 // hz = -7.2399999999964 +#define IQ_F_VALUE_MINUS_7_23 -6064964 // hz = -7.2299999999964 +#define IQ_F_VALUE_MINUS_7_22 -6056575 // hz = -7.2199999999964 +#define IQ_F_VALUE_MINUS_7_21 -6048187 // hz = -7.2099999999964 +#define IQ_F_VALUE_MINUS_7_20 -6039798 // hz = -7.1999999999964 +#define IQ_F_VALUE_MINUS_7_19 -6031410 // hz = -7.1899999999964 +#define IQ_F_VALUE_MINUS_7_18 -6023021 // hz = -7.1799999999964 +#define IQ_F_VALUE_MINUS_7_17 -6014632 // hz = -7.1699999999964 +#define IQ_F_VALUE_MINUS_7_16 -6006244 // hz = -7.1599999999964 +#define IQ_F_VALUE_MINUS_7_15 -5997855 // hz = -7.1499999999964 +#define IQ_F_VALUE_MINUS_7_14 -5989467 // hz = -7.1399999999964 +#define IQ_F_VALUE_MINUS_7_13 -5981078 // hz = -7.1299999999964 +#define IQ_F_VALUE_MINUS_7_12 -5972689 // hz = -7.1199999999964 +#define IQ_F_VALUE_MINUS_7_11 -5964301 // hz = -7.1099999999964 +#define IQ_F_VALUE_MINUS_7_10 -5955912 // hz = -7.0999999999964 +#define IQ_F_VALUE_MINUS_7_09 -5947524 // hz = -7.0899999999964 +#define IQ_F_VALUE_MINUS_7_08 -5939135 // hz = -7.0799999999964 +#define IQ_F_VALUE_MINUS_7_07 -5930746 // hz = -7.0699999999964 +#define IQ_F_VALUE_MINUS_7_06 -5922358 // hz = -7.0599999999964 +#define IQ_F_VALUE_MINUS_7_05 -5913969 // hz = -7.0499999999964 +#define IQ_F_VALUE_MINUS_7_04 -5905581 // hz = -7.0399999999964 +#define IQ_F_VALUE_MINUS_7_03 -5897192 // hz = -7.0299999999964 +#define IQ_F_VALUE_MINUS_7_02 -5888803 // hz = -7.0199999999964 +#define IQ_F_VALUE_MINUS_7_01 -5880415 // hz = -7.0099999999964 +#define IQ_F_VALUE_MINUS_7_00 -5872026 // hz = -6.9999999999964 +#define IQ_F_VALUE_MINUS_6_99 -5863637 // hz = -6.9899999999964 +#define IQ_F_VALUE_MINUS_6_98 -5855249 // hz = -6.9799999999964 +#define IQ_F_VALUE_MINUS_6_97 -5846860 // hz = -6.9699999999964 +#define IQ_F_VALUE_MINUS_6_96 -5838472 // hz = -6.9599999999964 +#define IQ_F_VALUE_MINUS_6_95 -5830083 // hz = -6.9499999999964 +#define IQ_F_VALUE_MINUS_6_94 -5821694 // hz = -6.9399999999964 +#define IQ_F_VALUE_MINUS_6_93 -5813306 // hz = -6.9299999999964 +#define IQ_F_VALUE_MINUS_6_92 -5804917 // hz = -6.9199999999964 +#define IQ_F_VALUE_MINUS_6_91 -5796529 // hz = -6.9099999999964 +#define IQ_F_VALUE_MINUS_6_90 -5788140 // hz = -6.8999999999964 +#define IQ_F_VALUE_MINUS_6_89 -5779751 // hz = -6.8899999999964 +#define IQ_F_VALUE_MINUS_6_88 -5771363 // hz = -6.8799999999964 +#define IQ_F_VALUE_MINUS_6_87 -5762974 // hz = -6.8699999999964 +#define IQ_F_VALUE_MINUS_6_86 -5754586 // hz = -6.8599999999964 +#define IQ_F_VALUE_MINUS_6_85 -5746197 // hz = -6.8499999999964 +#define IQ_F_VALUE_MINUS_6_84 -5737808 // hz = -6.8399999999964 +#define IQ_F_VALUE_MINUS_6_83 -5729420 // hz = -6.8299999999964 +#define IQ_F_VALUE_MINUS_6_82 -5721031 // hz = -6.8199999999964 +#define IQ_F_VALUE_MINUS_6_81 -5712643 // hz = -6.8099999999964 +#define IQ_F_VALUE_MINUS_6_80 -5704254 // hz = -6.7999999999964 +#define IQ_F_VALUE_MINUS_6_79 -5695865 // hz = -6.7899999999964 +#define IQ_F_VALUE_MINUS_6_78 -5687477 // hz = -6.7799999999964 +#define IQ_F_VALUE_MINUS_6_77 -5679088 // hz = -6.7699999999964 +#define IQ_F_VALUE_MINUS_6_76 -5670700 // hz = -6.7599999999964 +#define IQ_F_VALUE_MINUS_6_75 -5662311 // hz = -6.7499999999964 +#define IQ_F_VALUE_MINUS_6_74 -5653922 // hz = -6.7399999999964 +#define IQ_F_VALUE_MINUS_6_73 -5645534 // hz = -6.7299999999964 +#define IQ_F_VALUE_MINUS_6_72 -5637145 // hz = -6.7199999999964 +#define IQ_F_VALUE_MINUS_6_71 -5628756 // hz = -6.7099999999964 +#define IQ_F_VALUE_MINUS_6_70 -5620368 // hz = -6.6999999999964 +#define IQ_F_VALUE_MINUS_6_69 -5611979 // hz = -6.6899999999964 +#define IQ_F_VALUE_MINUS_6_68 -5603591 // hz = -6.6799999999964 +#define IQ_F_VALUE_MINUS_6_67 -5595202 // hz = -6.6699999999964 +#define IQ_F_VALUE_MINUS_6_66 -5586813 // hz = -6.6599999999964 +#define IQ_F_VALUE_MINUS_6_65 -5578425 // hz = -6.6499999999963 +#define IQ_F_VALUE_MINUS_6_64 -5570036 // hz = -6.6399999999963 +#define IQ_F_VALUE_MINUS_6_63 -5561648 // hz = -6.6299999999963 +#define IQ_F_VALUE_MINUS_6_62 -5553259 // hz = -6.6199999999963 +#define IQ_F_VALUE_MINUS_6_61 -5544870 // hz = -6.6099999999963 +#define IQ_F_VALUE_MINUS_6_60 -5536482 // hz = -6.5999999999963 +#define IQ_F_VALUE_MINUS_6_59 -5528093 // hz = -6.5899999999963 +#define IQ_F_VALUE_MINUS_6_58 -5519705 // hz = -6.5799999999963 +#define IQ_F_VALUE_MINUS_6_57 -5511316 // hz = -6.5699999999963 +#define IQ_F_VALUE_MINUS_6_56 -5502927 // hz = -6.5599999999963 +#define IQ_F_VALUE_MINUS_6_55 -5494539 // hz = -6.5499999999963 +#define IQ_F_VALUE_MINUS_6_54 -5486150 // hz = -6.5399999999963 +#define IQ_F_VALUE_MINUS_6_53 -5477762 // hz = -6.5299999999963 +#define IQ_F_VALUE_MINUS_6_52 -5469373 // hz = -6.5199999999963 +#define IQ_F_VALUE_MINUS_6_51 -5460984 // hz = -6.5099999999963 +#define IQ_F_VALUE_MINUS_6_50 -5452596 // hz = -6.4999999999963 +#define IQ_F_VALUE_MINUS_6_49 -5444207 // hz = -6.4899999999963 +#define IQ_F_VALUE_MINUS_6_48 -5435818 // hz = -6.4799999999963 +#define IQ_F_VALUE_MINUS_6_47 -5427430 // hz = -6.4699999999963 +#define IQ_F_VALUE_MINUS_6_46 -5419041 // hz = -6.4599999999963 +#define IQ_F_VALUE_MINUS_6_45 -5410653 // hz = -6.4499999999963 +#define IQ_F_VALUE_MINUS_6_44 -5402264 // hz = -6.4399999999963 +#define IQ_F_VALUE_MINUS_6_43 -5393875 // hz = -6.4299999999963 +#define IQ_F_VALUE_MINUS_6_42 -5385487 // hz = -6.4199999999963 +#define IQ_F_VALUE_MINUS_6_41 -5377098 // hz = -6.4099999999963 +#define IQ_F_VALUE_MINUS_6_40 -5368710 // hz = -6.3999999999963 +#define IQ_F_VALUE_MINUS_6_39 -5360321 // hz = -6.3899999999963 +#define IQ_F_VALUE_MINUS_6_38 -5351932 // hz = -6.3799999999963 +#define IQ_F_VALUE_MINUS_6_37 -5343544 // hz = -6.3699999999963 +#define IQ_F_VALUE_MINUS_6_36 -5335155 // hz = -6.3599999999963 +#define IQ_F_VALUE_MINUS_6_35 -5326767 // hz = -6.3499999999963 +#define IQ_F_VALUE_MINUS_6_34 -5318378 // hz = -6.3399999999963 +#define IQ_F_VALUE_MINUS_6_33 -5309989 // hz = -6.3299999999963 +#define IQ_F_VALUE_MINUS_6_32 -5301601 // hz = -6.3199999999963 +#define IQ_F_VALUE_MINUS_6_31 -5293212 // hz = -6.3099999999963 +#define IQ_F_VALUE_MINUS_6_30 -5284824 // hz = -6.2999999999963 +#define IQ_F_VALUE_MINUS_6_29 -5276435 // hz = -6.2899999999963 +#define IQ_F_VALUE_MINUS_6_28 -5268046 // hz = -6.2799999999963 +#define IQ_F_VALUE_MINUS_6_27 -5259658 // hz = -6.2699999999963 +#define IQ_F_VALUE_MINUS_6_26 -5251269 // hz = -6.2599999999963 +#define IQ_F_VALUE_MINUS_6_25 -5242880 // hz = -6.2499999999963 +#define IQ_F_VALUE_MINUS_6_24 -5234492 // hz = -6.2399999999963 +#define IQ_F_VALUE_MINUS_6_23 -5226103 // hz = -6.2299999999963 +#define IQ_F_VALUE_MINUS_6_22 -5217715 // hz = -6.2199999999963 +#define IQ_F_VALUE_MINUS_6_21 -5209326 // hz = -6.2099999999963 +#define IQ_F_VALUE_MINUS_6_20 -5200937 // hz = -6.1999999999963 +#define IQ_F_VALUE_MINUS_6_19 -5192549 // hz = -6.1899999999963 +#define IQ_F_VALUE_MINUS_6_18 -5184160 // hz = -6.1799999999963 +#define IQ_F_VALUE_MINUS_6_17 -5175772 // hz = -6.1699999999963 +#define IQ_F_VALUE_MINUS_6_16 -5167383 // hz = -6.1599999999963 +#define IQ_F_VALUE_MINUS_6_15 -5158994 // hz = -6.1499999999963 +#define IQ_F_VALUE_MINUS_6_14 -5150606 // hz = -6.1399999999963 +#define IQ_F_VALUE_MINUS_6_13 -5142217 // hz = -6.1299999999963 +#define IQ_F_VALUE_MINUS_6_12 -5133829 // hz = -6.1199999999963 +#define IQ_F_VALUE_MINUS_6_11 -5125440 // hz = -6.1099999999963 +#define IQ_F_VALUE_MINUS_6_10 -5117051 // hz = -6.0999999999963 +#define IQ_F_VALUE_MINUS_6_09 -5108663 // hz = -6.0899999999963 +#define IQ_F_VALUE_MINUS_6_08 -5100274 // hz = -6.0799999999963 +#define IQ_F_VALUE_MINUS_6_07 -5091886 // hz = -6.0699999999963 +#define IQ_F_VALUE_MINUS_6_06 -5083497 // hz = -6.0599999999963 +#define IQ_F_VALUE_MINUS_6_05 -5075108 // hz = -6.0499999999963 +#define IQ_F_VALUE_MINUS_6_04 -5066720 // hz = -6.0399999999963 +#define IQ_F_VALUE_MINUS_6_03 -5058331 // hz = -6.0299999999963 +#define IQ_F_VALUE_MINUS_6_02 -5049943 // hz = -6.0199999999963 +#define IQ_F_VALUE_MINUS_6_01 -5041554 // hz = -6.0099999999962 +#define IQ_F_VALUE_MINUS_6_00 -5033165 // hz = -5.9999999999962 +#define IQ_F_VALUE_MINUS_5_99 -5024777 // hz = -5.9899999999962 +#define IQ_F_VALUE_MINUS_5_98 -5016388 // hz = -5.9799999999962 +#define IQ_F_VALUE_MINUS_5_97 -5007999 // hz = -5.9699999999962 +#define IQ_F_VALUE_MINUS_5_96 -4999611 // hz = -5.9599999999962 +#define IQ_F_VALUE_MINUS_5_95 -4991222 // hz = -5.9499999999962 +#define IQ_F_VALUE_MINUS_5_94 -4982834 // hz = -5.9399999999962 +#define IQ_F_VALUE_MINUS_5_93 -4974445 // hz = -5.9299999999962 +#define IQ_F_VALUE_MINUS_5_92 -4966056 // hz = -5.9199999999962 +#define IQ_F_VALUE_MINUS_5_91 -4957668 // hz = -5.9099999999962 +#define IQ_F_VALUE_MINUS_5_90 -4949279 // hz = -5.8999999999962 +#define IQ_F_VALUE_MINUS_5_89 -4940891 // hz = -5.8899999999962 +#define IQ_F_VALUE_MINUS_5_88 -4932502 // hz = -5.8799999999962 +#define IQ_F_VALUE_MINUS_5_87 -4924113 // hz = -5.8699999999962 +#define IQ_F_VALUE_MINUS_5_86 -4915725 // hz = -5.8599999999962 +#define IQ_F_VALUE_MINUS_5_85 -4907336 // hz = -5.8499999999962 +#define IQ_F_VALUE_MINUS_5_84 -4898948 // hz = -5.8399999999962 +#define IQ_F_VALUE_MINUS_5_83 -4890559 // hz = -5.8299999999962 +#define IQ_F_VALUE_MINUS_5_82 -4882170 // hz = -5.8199999999962 +#define IQ_F_VALUE_MINUS_5_81 -4873782 // hz = -5.8099999999962 +#define IQ_F_VALUE_MINUS_5_80 -4865393 // hz = -5.7999999999962 +#define IQ_F_VALUE_MINUS_5_79 -4857005 // hz = -5.7899999999962 +#define IQ_F_VALUE_MINUS_5_78 -4848616 // hz = -5.7799999999962 +#define IQ_F_VALUE_MINUS_5_77 -4840227 // hz = -5.7699999999962 +#define IQ_F_VALUE_MINUS_5_76 -4831839 // hz = -5.7599999999962 +#define IQ_F_VALUE_MINUS_5_75 -4823450 // hz = -5.7499999999962 +#define IQ_F_VALUE_MINUS_5_74 -4815061 // hz = -5.7399999999962 +#define IQ_F_VALUE_MINUS_5_73 -4806673 // hz = -5.7299999999962 +#define IQ_F_VALUE_MINUS_5_72 -4798284 // hz = -5.7199999999962 +#define IQ_F_VALUE_MINUS_5_71 -4789896 // hz = -5.7099999999962 +#define IQ_F_VALUE_MINUS_5_70 -4781507 // hz = -5.6999999999962 +#define IQ_F_VALUE_MINUS_5_69 -4773118 // hz = -5.6899999999962 +#define IQ_F_VALUE_MINUS_5_68 -4764730 // hz = -5.6799999999962 +#define IQ_F_VALUE_MINUS_5_67 -4756341 // hz = -5.6699999999962 +#define IQ_F_VALUE_MINUS_5_66 -4747953 // hz = -5.6599999999962 +#define IQ_F_VALUE_MINUS_5_65 -4739564 // hz = -5.6499999999962 +#define IQ_F_VALUE_MINUS_5_64 -4731175 // hz = -5.6399999999962 +#define IQ_F_VALUE_MINUS_5_63 -4722787 // hz = -5.6299999999962 +#define IQ_F_VALUE_MINUS_5_62 -4714398 // hz = -5.6199999999962 +#define IQ_F_VALUE_MINUS_5_61 -4706010 // hz = -5.6099999999962 +#define IQ_F_VALUE_MINUS_5_60 -4697621 // hz = -5.5999999999962 +#define IQ_F_VALUE_MINUS_5_59 -4689232 // hz = -5.5899999999962 +#define IQ_F_VALUE_MINUS_5_58 -4680844 // hz = -5.5799999999962 +#define IQ_F_VALUE_MINUS_5_57 -4672455 // hz = -5.5699999999962 +#define IQ_F_VALUE_MINUS_5_56 -4664067 // hz = -5.5599999999962 +#define IQ_F_VALUE_MINUS_5_55 -4655678 // hz = -5.5499999999962 +#define IQ_F_VALUE_MINUS_5_54 -4647289 // hz = -5.5399999999962 +#define IQ_F_VALUE_MINUS_5_53 -4638901 // hz = -5.5299999999962 +#define IQ_F_VALUE_MINUS_5_52 -4630512 // hz = -5.5199999999962 +#define IQ_F_VALUE_MINUS_5_51 -4622124 // hz = -5.5099999999962 +#define IQ_F_VALUE_MINUS_5_50 -4613735 // hz = -5.4999999999962 +#define IQ_F_VALUE_MINUS_5_49 -4605346 // hz = -5.4899999999962 +#define IQ_F_VALUE_MINUS_5_48 -4596958 // hz = -5.4799999999962 +#define IQ_F_VALUE_MINUS_5_47 -4588569 // hz = -5.4699999999962 +#define IQ_F_VALUE_MINUS_5_46 -4580180 // hz = -5.4599999999962 +#define IQ_F_VALUE_MINUS_5_45 -4571792 // hz = -5.4499999999962 +#define IQ_F_VALUE_MINUS_5_44 -4563403 // hz = -5.4399999999962 +#define IQ_F_VALUE_MINUS_5_43 -4555015 // hz = -5.4299999999962 +#define IQ_F_VALUE_MINUS_5_42 -4546626 // hz = -5.4199999999962 +#define IQ_F_VALUE_MINUS_5_41 -4538237 // hz = -5.4099999999962 +#define IQ_F_VALUE_MINUS_5_40 -4529849 // hz = -5.3999999999962 +#define IQ_F_VALUE_MINUS_5_39 -4521460 // hz = -5.3899999999962 +#define IQ_F_VALUE_MINUS_5_38 -4513072 // hz = -5.3799999999962 +#define IQ_F_VALUE_MINUS_5_37 -4504683 // hz = -5.3699999999961 +#define IQ_F_VALUE_MINUS_5_36 -4496294 // hz = -5.3599999999961 +#define IQ_F_VALUE_MINUS_5_35 -4487906 // hz = -5.3499999999961 +#define IQ_F_VALUE_MINUS_5_34 -4479517 // hz = -5.3399999999961 +#define IQ_F_VALUE_MINUS_5_33 -4471129 // hz = -5.3299999999961 +#define IQ_F_VALUE_MINUS_5_32 -4462740 // hz = -5.3199999999961 +#define IQ_F_VALUE_MINUS_5_31 -4454351 // hz = -5.3099999999961 +#define IQ_F_VALUE_MINUS_5_30 -4445963 // hz = -5.2999999999961 +#define IQ_F_VALUE_MINUS_5_29 -4437574 // hz = -5.2899999999961 +#define IQ_F_VALUE_MINUS_5_28 -4429186 // hz = -5.2799999999961 +#define IQ_F_VALUE_MINUS_5_27 -4420797 // hz = -5.2699999999961 +#define IQ_F_VALUE_MINUS_5_26 -4412408 // hz = -5.2599999999961 +#define IQ_F_VALUE_MINUS_5_25 -4404020 // hz = -5.2499999999961 +#define IQ_F_VALUE_MINUS_5_24 -4395631 // hz = -5.2399999999961 +#define IQ_F_VALUE_MINUS_5_23 -4387242 // hz = -5.2299999999961 +#define IQ_F_VALUE_MINUS_5_22 -4378854 // hz = -5.2199999999961 +#define IQ_F_VALUE_MINUS_5_21 -4370465 // hz = -5.2099999999961 +#define IQ_F_VALUE_MINUS_5_20 -4362077 // hz = -5.1999999999961 +#define IQ_F_VALUE_MINUS_5_19 -4353688 // hz = -5.1899999999961 +#define IQ_F_VALUE_MINUS_5_18 -4345299 // hz = -5.1799999999961 +#define IQ_F_VALUE_MINUS_5_17 -4336911 // hz = -5.1699999999961 +#define IQ_F_VALUE_MINUS_5_16 -4328522 // hz = -5.1599999999961 +#define IQ_F_VALUE_MINUS_5_15 -4320134 // hz = -5.1499999999961 +#define IQ_F_VALUE_MINUS_5_14 -4311745 // hz = -5.1399999999961 +#define IQ_F_VALUE_MINUS_5_13 -4303356 // hz = -5.1299999999961 +#define IQ_F_VALUE_MINUS_5_12 -4294968 // hz = -5.1199999999961 +#define IQ_F_VALUE_MINUS_5_11 -4286579 // hz = -5.1099999999961 +#define IQ_F_VALUE_MINUS_5_10 -4278191 // hz = -5.0999999999961 +#define IQ_F_VALUE_MINUS_5_09 -4269802 // hz = -5.0899999999961 +#define IQ_F_VALUE_MINUS_5_08 -4261413 // hz = -5.0799999999961 +#define IQ_F_VALUE_MINUS_5_07 -4253025 // hz = -5.0699999999961 +#define IQ_F_VALUE_MINUS_5_06 -4244636 // hz = -5.0599999999961 +#define IQ_F_VALUE_MINUS_5_05 -4236248 // hz = -5.0499999999961 +#define IQ_F_VALUE_MINUS_5_04 -4227859 // hz = -5.0399999999961 +#define IQ_F_VALUE_MINUS_5_03 -4219470 // hz = -5.0299999999961 +#define IQ_F_VALUE_MINUS_5_02 -4211082 // hz = -5.0199999999961 +#define IQ_F_VALUE_MINUS_5_01 -4202693 // hz = -5.0099999999961 +#define IQ_F_VALUE_MINUS_5_00 -4194304 // hz = -4.9999999999961 +#define IQ_F_VALUE_MINUS_4_99 -4185916 // hz = -4.9899999999961 +#define IQ_F_VALUE_MINUS_4_98 -4177527 // hz = -4.9799999999961 +#define IQ_F_VALUE_MINUS_4_97 -4169139 // hz = -4.9699999999961 +#define IQ_F_VALUE_MINUS_4_96 -4160750 // hz = -4.9599999999961 +#define IQ_F_VALUE_MINUS_4_95 -4152361 // hz = -4.9499999999961 +#define IQ_F_VALUE_MINUS_4_94 -4143973 // hz = -4.9399999999961 +#define IQ_F_VALUE_MINUS_4_93 -4135584 // hz = -4.9299999999961 +#define IQ_F_VALUE_MINUS_4_92 -4127196 // hz = -4.9199999999961 +#define IQ_F_VALUE_MINUS_4_91 -4118807 // hz = -4.9099999999961 +#define IQ_F_VALUE_MINUS_4_90 -4110418 // hz = -4.8999999999961 +#define IQ_F_VALUE_MINUS_4_89 -4102030 // hz = -4.8899999999961 +#define IQ_F_VALUE_MINUS_4_88 -4093641 // hz = -4.8799999999961 +#define IQ_F_VALUE_MINUS_4_87 -4085253 // hz = -4.8699999999961 +#define IQ_F_VALUE_MINUS_4_86 -4076864 // hz = -4.8599999999961 +#define IQ_F_VALUE_MINUS_4_85 -4068475 // hz = -4.8499999999961 +#define IQ_F_VALUE_MINUS_4_84 -4060087 // hz = -4.8399999999961 +#define IQ_F_VALUE_MINUS_4_83 -4051698 // hz = -4.8299999999961 +#define IQ_F_VALUE_MINUS_4_82 -4043310 // hz = -4.8199999999961 +#define IQ_F_VALUE_MINUS_4_81 -4034921 // hz = -4.8099999999961 +#define IQ_F_VALUE_MINUS_4_80 -4026532 // hz = -4.7999999999961 +#define IQ_F_VALUE_MINUS_4_79 -4018144 // hz = -4.7899999999961 +#define IQ_F_VALUE_MINUS_4_78 -4009755 // hz = -4.7799999999961 +#define IQ_F_VALUE_MINUS_4_77 -4001367 // hz = -4.7699999999961 +#define IQ_F_VALUE_MINUS_4_76 -3992978 // hz = -4.7599999999961 +#define IQ_F_VALUE_MINUS_4_75 -3984589 // hz = -4.7499999999961 +#define IQ_F_VALUE_MINUS_4_74 -3976201 // hz = -4.7399999999961 +#define IQ_F_VALUE_MINUS_4_73 -3967812 // hz = -4.729999999996 +#define IQ_F_VALUE_MINUS_4_72 -3959423 // hz = -4.719999999996 +#define IQ_F_VALUE_MINUS_4_71 -3951035 // hz = -4.709999999996 +#define IQ_F_VALUE_MINUS_4_70 -3942646 // hz = -4.699999999996 +#define IQ_F_VALUE_MINUS_4_69 -3934258 // hz = -4.689999999996 +#define IQ_F_VALUE_MINUS_4_68 -3925869 // hz = -4.679999999996 +#define IQ_F_VALUE_MINUS_4_67 -3917480 // hz = -4.669999999996 +#define IQ_F_VALUE_MINUS_4_66 -3909092 // hz = -4.659999999996 +#define IQ_F_VALUE_MINUS_4_65 -3900703 // hz = -4.649999999996 +#define IQ_F_VALUE_MINUS_4_64 -3892315 // hz = -4.639999999996 +#define IQ_F_VALUE_MINUS_4_63 -3883926 // hz = -4.629999999996 +#define IQ_F_VALUE_MINUS_4_62 -3875537 // hz = -4.619999999996 +#define IQ_F_VALUE_MINUS_4_61 -3867149 // hz = -4.609999999996 +#define IQ_F_VALUE_MINUS_4_60 -3858760 // hz = -4.599999999996 +#define IQ_F_VALUE_MINUS_4_59 -3850372 // hz = -4.589999999996 +#define IQ_F_VALUE_MINUS_4_58 -3841983 // hz = -4.579999999996 +#define IQ_F_VALUE_MINUS_4_57 -3833594 // hz = -4.569999999996 +#define IQ_F_VALUE_MINUS_4_56 -3825206 // hz = -4.559999999996 +#define IQ_F_VALUE_MINUS_4_55 -3816817 // hz = -4.549999999996 +#define IQ_F_VALUE_MINUS_4_54 -3808429 // hz = -4.539999999996 +#define IQ_F_VALUE_MINUS_4_53 -3800040 // hz = -4.529999999996 +#define IQ_F_VALUE_MINUS_4_52 -3791651 // hz = -4.519999999996 +#define IQ_F_VALUE_MINUS_4_51 -3783263 // hz = -4.509999999996 +#define IQ_F_VALUE_MINUS_4_50 -3774874 // hz = -4.499999999996 +#define IQ_F_VALUE_MINUS_4_49 -3766485 // hz = -4.489999999996 +#define IQ_F_VALUE_MINUS_4_48 -3758097 // hz = -4.479999999996 +#define IQ_F_VALUE_MINUS_4_47 -3749708 // hz = -4.469999999996 +#define IQ_F_VALUE_MINUS_4_46 -3741320 // hz = -4.459999999996 +#define IQ_F_VALUE_MINUS_4_45 -3732931 // hz = -4.449999999996 +#define IQ_F_VALUE_MINUS_4_44 -3724542 // hz = -4.439999999996 +#define IQ_F_VALUE_MINUS_4_43 -3716154 // hz = -4.429999999996 +#define IQ_F_VALUE_MINUS_4_42 -3707765 // hz = -4.419999999996 +#define IQ_F_VALUE_MINUS_4_41 -3699377 // hz = -4.409999999996 +#define IQ_F_VALUE_MINUS_4_40 -3690988 // hz = -4.399999999996 +#define IQ_F_VALUE_MINUS_4_39 -3682599 // hz = -4.389999999996 +#define IQ_F_VALUE_MINUS_4_38 -3674211 // hz = -4.379999999996 +#define IQ_F_VALUE_MINUS_4_37 -3665822 // hz = -4.369999999996 +#define IQ_F_VALUE_MINUS_4_36 -3657434 // hz = -4.359999999996 +#define IQ_F_VALUE_MINUS_4_35 -3649045 // hz = -4.349999999996 +#define IQ_F_VALUE_MINUS_4_34 -3640656 // hz = -4.339999999996 +#define IQ_F_VALUE_MINUS_4_33 -3632268 // hz = -4.329999999996 +#define IQ_F_VALUE_MINUS_4_32 -3623879 // hz = -4.319999999996 +#define IQ_F_VALUE_MINUS_4_31 -3615491 // hz = -4.309999999996 +#define IQ_F_VALUE_MINUS_4_30 -3607102 // hz = -4.299999999996 +#define IQ_F_VALUE_MINUS_4_29 -3598713 // hz = -4.289999999996 +#define IQ_F_VALUE_MINUS_4_28 -3590325 // hz = -4.279999999996 +#define IQ_F_VALUE_MINUS_4_27 -3581936 // hz = -4.269999999996 +#define IQ_F_VALUE_MINUS_4_26 -3573548 // hz = -4.259999999996 +#define IQ_F_VALUE_MINUS_4_25 -3565159 // hz = -4.249999999996 +#define IQ_F_VALUE_MINUS_4_24 -3556770 // hz = -4.239999999996 +#define IQ_F_VALUE_MINUS_4_23 -3548382 // hz = -4.229999999996 +#define IQ_F_VALUE_MINUS_4_22 -3539993 // hz = -4.219999999996 +#define IQ_F_VALUE_MINUS_4_21 -3531604 // hz = -4.209999999996 +#define IQ_F_VALUE_MINUS_4_20 -3523216 // hz = -4.199999999996 +#define IQ_F_VALUE_MINUS_4_19 -3514827 // hz = -4.189999999996 +#define IQ_F_VALUE_MINUS_4_18 -3506439 // hz = -4.179999999996 +#define IQ_F_VALUE_MINUS_4_17 -3498050 // hz = -4.169999999996 +#define IQ_F_VALUE_MINUS_4_16 -3489661 // hz = -4.159999999996 +#define IQ_F_VALUE_MINUS_4_15 -3481273 // hz = -4.149999999996 +#define IQ_F_VALUE_MINUS_4_14 -3472884 // hz = -4.139999999996 +#define IQ_F_VALUE_MINUS_4_13 -3464496 // hz = -4.129999999996 +#define IQ_F_VALUE_MINUS_4_12 -3456107 // hz = -4.119999999996 +#define IQ_F_VALUE_MINUS_4_11 -3447718 // hz = -4.109999999996 +#define IQ_F_VALUE_MINUS_4_10 -3439330 // hz = -4.099999999996 +#define IQ_F_VALUE_MINUS_4_09 -3430941 // hz = -4.0899999999959 +#define IQ_F_VALUE_MINUS_4_08 -3422553 // hz = -4.0799999999959 +#define IQ_F_VALUE_MINUS_4_07 -3414164 // hz = -4.0699999999959 +#define IQ_F_VALUE_MINUS_4_06 -3405775 // hz = -4.0599999999959 +#define IQ_F_VALUE_MINUS_4_05 -3397387 // hz = -4.0499999999959 +#define IQ_F_VALUE_MINUS_4_04 -3388998 // hz = -4.0399999999959 +#define IQ_F_VALUE_MINUS_4_03 -3380610 // hz = -4.0299999999959 +#define IQ_F_VALUE_MINUS_4_02 -3372221 // hz = -4.0199999999959 +#define IQ_F_VALUE_MINUS_4_01 -3363832 // hz = -4.0099999999959 +#define IQ_F_VALUE_MINUS_4_00 -3355444 // hz = -3.9999999999959 +#define IQ_F_VALUE_MINUS_3_99 -3347055 // hz = -3.9899999999959 +#define IQ_F_VALUE_MINUS_3_98 -3338666 // hz = -3.9799999999959 +#define IQ_F_VALUE_MINUS_3_97 -3330278 // hz = -3.9699999999959 +#define IQ_F_VALUE_MINUS_3_96 -3321889 // hz = -3.9599999999959 +#define IQ_F_VALUE_MINUS_3_95 -3313501 // hz = -3.9499999999959 +#define IQ_F_VALUE_MINUS_3_94 -3305112 // hz = -3.9399999999959 +#define IQ_F_VALUE_MINUS_3_93 -3296723 // hz = -3.9299999999959 +#define IQ_F_VALUE_MINUS_3_92 -3288335 // hz = -3.9199999999959 +#define IQ_F_VALUE_MINUS_3_91 -3279946 // hz = -3.9099999999959 +#define IQ_F_VALUE_MINUS_3_90 -3271558 // hz = -3.8999999999959 +#define IQ_F_VALUE_MINUS_3_89 -3263169 // hz = -3.8899999999959 +#define IQ_F_VALUE_MINUS_3_88 -3254780 // hz = -3.8799999999959 +#define IQ_F_VALUE_MINUS_3_87 -3246392 // hz = -3.8699999999959 +#define IQ_F_VALUE_MINUS_3_86 -3238003 // hz = -3.8599999999959 +#define IQ_F_VALUE_MINUS_3_85 -3229615 // hz = -3.8499999999959 +#define IQ_F_VALUE_MINUS_3_84 -3221226 // hz = -3.8399999999959 +#define IQ_F_VALUE_MINUS_3_83 -3212837 // hz = -3.8299999999959 +#define IQ_F_VALUE_MINUS_3_82 -3204449 // hz = -3.8199999999959 +#define IQ_F_VALUE_MINUS_3_81 -3196060 // hz = -3.8099999999959 +#define IQ_F_VALUE_MINUS_3_80 -3187672 // hz = -3.7999999999959 +#define IQ_F_VALUE_MINUS_3_79 -3179283 // hz = -3.7899999999959 +#define IQ_F_VALUE_MINUS_3_78 -3170894 // hz = -3.7799999999959 +#define IQ_F_VALUE_MINUS_3_77 -3162506 // hz = -3.7699999999959 +#define IQ_F_VALUE_MINUS_3_76 -3154117 // hz = -3.7599999999959 +#define IQ_F_VALUE_MINUS_3_75 -3145728 // hz = -3.7499999999959 +#define IQ_F_VALUE_MINUS_3_74 -3137340 // hz = -3.7399999999959 +#define IQ_F_VALUE_MINUS_3_73 -3128951 // hz = -3.7299999999959 +#define IQ_F_VALUE_MINUS_3_72 -3120563 // hz = -3.7199999999959 +#define IQ_F_VALUE_MINUS_3_71 -3112174 // hz = -3.7099999999959 +#define IQ_F_VALUE_MINUS_3_70 -3103785 // hz = -3.6999999999959 +#define IQ_F_VALUE_MINUS_3_69 -3095397 // hz = -3.6899999999959 +#define IQ_F_VALUE_MINUS_3_68 -3087008 // hz = -3.6799999999959 +#define IQ_F_VALUE_MINUS_3_67 -3078620 // hz = -3.6699999999959 +#define IQ_F_VALUE_MINUS_3_66 -3070231 // hz = -3.6599999999959 +#define IQ_F_VALUE_MINUS_3_65 -3061842 // hz = -3.6499999999959 +#define IQ_F_VALUE_MINUS_3_64 -3053454 // hz = -3.6399999999959 +#define IQ_F_VALUE_MINUS_3_63 -3045065 // hz = -3.6299999999959 +#define IQ_F_VALUE_MINUS_3_62 -3036677 // hz = -3.6199999999959 +#define IQ_F_VALUE_MINUS_3_61 -3028288 // hz = -3.6099999999959 +#define IQ_F_VALUE_MINUS_3_60 -3019899 // hz = -3.5999999999959 +#define IQ_F_VALUE_MINUS_3_59 -3011511 // hz = -3.5899999999959 +#define IQ_F_VALUE_MINUS_3_58 -3003122 // hz = -3.5799999999959 +#define IQ_F_VALUE_MINUS_3_57 -2994734 // hz = -3.5699999999959 +#define IQ_F_VALUE_MINUS_3_56 -2986345 // hz = -3.5599999999959 +#define IQ_F_VALUE_MINUS_3_55 -2977956 // hz = -3.5499999999959 +#define IQ_F_VALUE_MINUS_3_54 -2969568 // hz = -3.5399999999959 +#define IQ_F_VALUE_MINUS_3_53 -2961179 // hz = -3.5299999999959 +#define IQ_F_VALUE_MINUS_3_52 -2952791 // hz = -3.5199999999959 +#define IQ_F_VALUE_MINUS_3_51 -2944402 // hz = -3.5099999999959 +#define IQ_F_VALUE_MINUS_3_50 -2936013 // hz = -3.4999999999959 +#define IQ_F_VALUE_MINUS_3_49 -2927625 // hz = -3.4899999999959 +#define IQ_F_VALUE_MINUS_3_48 -2919236 // hz = -3.4799999999959 +#define IQ_F_VALUE_MINUS_3_47 -2910847 // hz = -3.4699999999959 +#define IQ_F_VALUE_MINUS_3_46 -2902459 // hz = -3.4599999999959 +#define IQ_F_VALUE_MINUS_3_45 -2894070 // hz = -3.4499999999958 +#define IQ_F_VALUE_MINUS_3_44 -2885682 // hz = -3.4399999999958 +#define IQ_F_VALUE_MINUS_3_43 -2877293 // hz = -3.4299999999958 +#define IQ_F_VALUE_MINUS_3_42 -2868904 // hz = -3.4199999999958 +#define IQ_F_VALUE_MINUS_3_41 -2860516 // hz = -3.4099999999958 +#define IQ_F_VALUE_MINUS_3_40 -2852127 // hz = -3.3999999999958 +#define IQ_F_VALUE_MINUS_3_39 -2843739 // hz = -3.3899999999958 +#define IQ_F_VALUE_MINUS_3_38 -2835350 // hz = -3.3799999999958 +#define IQ_F_VALUE_MINUS_3_37 -2826961 // hz = -3.3699999999958 +#define IQ_F_VALUE_MINUS_3_36 -2818573 // hz = -3.3599999999958 +#define IQ_F_VALUE_MINUS_3_35 -2810184 // hz = -3.3499999999958 +#define IQ_F_VALUE_MINUS_3_34 -2801796 // hz = -3.3399999999958 +#define IQ_F_VALUE_MINUS_3_33 -2793407 // hz = -3.3299999999958 +#define IQ_F_VALUE_MINUS_3_32 -2785018 // hz = -3.3199999999958 +#define IQ_F_VALUE_MINUS_3_31 -2776630 // hz = -3.3099999999958 +#define IQ_F_VALUE_MINUS_3_30 -2768241 // hz = -3.2999999999958 +#define IQ_F_VALUE_MINUS_3_29 -2759853 // hz = -3.2899999999958 +#define IQ_F_VALUE_MINUS_3_28 -2751464 // hz = -3.2799999999958 +#define IQ_F_VALUE_MINUS_3_27 -2743075 // hz = -3.2699999999958 +#define IQ_F_VALUE_MINUS_3_26 -2734687 // hz = -3.2599999999958 +#define IQ_F_VALUE_MINUS_3_25 -2726298 // hz = -3.2499999999958 +#define IQ_F_VALUE_MINUS_3_24 -2717909 // hz = -3.2399999999958 +#define IQ_F_VALUE_MINUS_3_23 -2709521 // hz = -3.2299999999958 +#define IQ_F_VALUE_MINUS_3_22 -2701132 // hz = -3.2199999999958 +#define IQ_F_VALUE_MINUS_3_21 -2692744 // hz = -3.2099999999958 +#define IQ_F_VALUE_MINUS_3_20 -2684355 // hz = -3.1999999999958 +#define IQ_F_VALUE_MINUS_3_19 -2675966 // hz = -3.1899999999958 +#define IQ_F_VALUE_MINUS_3_18 -2667578 // hz = -3.1799999999958 +#define IQ_F_VALUE_MINUS_3_17 -2659189 // hz = -3.1699999999958 +#define IQ_F_VALUE_MINUS_3_16 -2650801 // hz = -3.1599999999958 +#define IQ_F_VALUE_MINUS_3_15 -2642412 // hz = -3.1499999999958 +#define IQ_F_VALUE_MINUS_3_14 -2634023 // hz = -3.1399999999958 +#define IQ_F_VALUE_MINUS_3_13 -2625635 // hz = -3.1299999999958 +#define IQ_F_VALUE_MINUS_3_12 -2617246 // hz = -3.1199999999958 +#define IQ_F_VALUE_MINUS_3_11 -2608858 // hz = -3.1099999999958 +#define IQ_F_VALUE_MINUS_3_10 -2600469 // hz = -3.0999999999958 +#define IQ_F_VALUE_MINUS_3_09 -2592080 // hz = -3.0899999999958 +#define IQ_F_VALUE_MINUS_3_08 -2583692 // hz = -3.0799999999958 +#define IQ_F_VALUE_MINUS_3_07 -2575303 // hz = -3.0699999999958 +#define IQ_F_VALUE_MINUS_3_06 -2566915 // hz = -3.0599999999958 +#define IQ_F_VALUE_MINUS_3_05 -2558526 // hz = -3.0499999999958 +#define IQ_F_VALUE_MINUS_3_04 -2550137 // hz = -3.0399999999958 +#define IQ_F_VALUE_MINUS_3_03 -2541749 // hz = -3.0299999999958 +#define IQ_F_VALUE_MINUS_3_02 -2533360 // hz = -3.0199999999958 +#define IQ_F_VALUE_MINUS_3_01 -2524972 // hz = -3.0099999999958 +#define IQ_F_VALUE_MINUS_3_00 -2516583 // hz = -2.9999999999958 +#define IQ_F_VALUE_MINUS_2_99 -2508194 // hz = -2.9899999999958 +#define IQ_F_VALUE_MINUS_2_98 -2499806 // hz = -2.9799999999958 +#define IQ_F_VALUE_MINUS_2_97 -2491417 // hz = -2.9699999999958 +#define IQ_F_VALUE_MINUS_2_96 -2483028 // hz = -2.9599999999958 +#define IQ_F_VALUE_MINUS_2_95 -2474640 // hz = -2.9499999999958 +#define IQ_F_VALUE_MINUS_2_94 -2466251 // hz = -2.9399999999958 +#define IQ_F_VALUE_MINUS_2_93 -2457863 // hz = -2.9299999999958 +#define IQ_F_VALUE_MINUS_2_92 -2449474 // hz = -2.9199999999958 +#define IQ_F_VALUE_MINUS_2_91 -2441085 // hz = -2.9099999999958 +#define IQ_F_VALUE_MINUS_2_90 -2432697 // hz = -2.8999999999958 +#define IQ_F_VALUE_MINUS_2_89 -2424308 // hz = -2.8899999999958 +#define IQ_F_VALUE_MINUS_2_88 -2415920 // hz = -2.8799999999958 +#define IQ_F_VALUE_MINUS_2_87 -2407531 // hz = -2.8699999999958 +#define IQ_F_VALUE_MINUS_2_86 -2399142 // hz = -2.8599999999958 +#define IQ_F_VALUE_MINUS_2_85 -2390754 // hz = -2.8499999999958 +#define IQ_F_VALUE_MINUS_2_84 -2382365 // hz = -2.8399999999958 +#define IQ_F_VALUE_MINUS_2_83 -2373977 // hz = -2.8299999999958 +#define IQ_F_VALUE_MINUS_2_82 -2365588 // hz = -2.8199999999958 +#define IQ_F_VALUE_MINUS_2_81 -2357199 // hz = -2.8099999999957 +#define IQ_F_VALUE_MINUS_2_80 -2348811 // hz = -2.7999999999957 +#define IQ_F_VALUE_MINUS_2_79 -2340422 // hz = -2.7899999999957 +#define IQ_F_VALUE_MINUS_2_78 -2332034 // hz = -2.7799999999957 +#define IQ_F_VALUE_MINUS_2_77 -2323645 // hz = -2.7699999999957 +#define IQ_F_VALUE_MINUS_2_76 -2315256 // hz = -2.7599999999957 +#define IQ_F_VALUE_MINUS_2_75 -2306868 // hz = -2.7499999999957 +#define IQ_F_VALUE_MINUS_2_74 -2298479 // hz = -2.7399999999957 +#define IQ_F_VALUE_MINUS_2_73 -2290090 // hz = -2.7299999999957 +#define IQ_F_VALUE_MINUS_2_72 -2281702 // hz = -2.7199999999957 +#define IQ_F_VALUE_MINUS_2_71 -2273313 // hz = -2.7099999999957 +#define IQ_F_VALUE_MINUS_2_70 -2264925 // hz = -2.6999999999957 +#define IQ_F_VALUE_MINUS_2_69 -2256536 // hz = -2.6899999999957 +#define IQ_F_VALUE_MINUS_2_68 -2248147 // hz = -2.6799999999957 +#define IQ_F_VALUE_MINUS_2_67 -2239759 // hz = -2.6699999999957 +#define IQ_F_VALUE_MINUS_2_66 -2231370 // hz = -2.6599999999957 +#define IQ_F_VALUE_MINUS_2_65 -2222982 // hz = -2.6499999999957 +#define IQ_F_VALUE_MINUS_2_64 -2214593 // hz = -2.6399999999957 +#define IQ_F_VALUE_MINUS_2_63 -2206204 // hz = -2.6299999999957 +#define IQ_F_VALUE_MINUS_2_62 -2197816 // hz = -2.6199999999957 +#define IQ_F_VALUE_MINUS_2_61 -2189427 // hz = -2.6099999999957 +#define IQ_F_VALUE_MINUS_2_60 -2181039 // hz = -2.5999999999957 +#define IQ_F_VALUE_MINUS_2_59 -2172650 // hz = -2.5899999999957 +#define IQ_F_VALUE_MINUS_2_58 -2164261 // hz = -2.5799999999957 +#define IQ_F_VALUE_MINUS_2_57 -2155873 // hz = -2.5699999999957 +#define IQ_F_VALUE_MINUS_2_56 -2147484 // hz = -2.5599999999957 +#define IQ_F_VALUE_MINUS_2_55 -2139096 // hz = -2.5499999999957 +#define IQ_F_VALUE_MINUS_2_54 -2130707 // hz = -2.5399999999957 +#define IQ_F_VALUE_MINUS_2_53 -2122318 // hz = -2.5299999999957 +#define IQ_F_VALUE_MINUS_2_52 -2113930 // hz = -2.5199999999957 +#define IQ_F_VALUE_MINUS_2_51 -2105541 // hz = -2.5099999999957 +#define IQ_F_VALUE_MINUS_2_50 -2097152 // hz = -2.4999999999957 +#define IQ_F_VALUE_MINUS_2_49 -2088764 // hz = -2.4899999999957 +#define IQ_F_VALUE_MINUS_2_48 -2080375 // hz = -2.4799999999957 +#define IQ_F_VALUE_MINUS_2_47 -2071987 // hz = -2.4699999999957 +#define IQ_F_VALUE_MINUS_2_46 -2063598 // hz = -2.4599999999957 +#define IQ_F_VALUE_MINUS_2_45 -2055209 // hz = -2.4499999999957 +#define IQ_F_VALUE_MINUS_2_44 -2046821 // hz = -2.4399999999957 +#define IQ_F_VALUE_MINUS_2_43 -2038432 // hz = -2.4299999999957 +#define IQ_F_VALUE_MINUS_2_42 -2030044 // hz = -2.4199999999957 +#define IQ_F_VALUE_MINUS_2_41 -2021655 // hz = -2.4099999999957 +#define IQ_F_VALUE_MINUS_2_40 -2013266 // hz = -2.3999999999957 +#define IQ_F_VALUE_MINUS_2_39 -2004878 // hz = -2.3899999999957 +#define IQ_F_VALUE_MINUS_2_38 -1996489 // hz = -2.3799999999957 +#define IQ_F_VALUE_MINUS_2_37 -1988101 // hz = -2.3699999999957 +#define IQ_F_VALUE_MINUS_2_36 -1979712 // hz = -2.3599999999957 +#define IQ_F_VALUE_MINUS_2_35 -1971323 // hz = -2.3499999999957 +#define IQ_F_VALUE_MINUS_2_34 -1962935 // hz = -2.3399999999957 +#define IQ_F_VALUE_MINUS_2_33 -1954546 // hz = -2.3299999999957 +#define IQ_F_VALUE_MINUS_2_32 -1946158 // hz = -2.3199999999957 +#define IQ_F_VALUE_MINUS_2_31 -1937769 // hz = -2.3099999999957 +#define IQ_F_VALUE_MINUS_2_30 -1929380 // hz = -2.2999999999957 +#define IQ_F_VALUE_MINUS_2_29 -1920992 // hz = -2.2899999999957 +#define IQ_F_VALUE_MINUS_2_28 -1912603 // hz = -2.2799999999957 +#define IQ_F_VALUE_MINUS_2_27 -1904215 // hz = -2.2699999999957 +#define IQ_F_VALUE_MINUS_2_26 -1895826 // hz = -2.2599999999957 +#define IQ_F_VALUE_MINUS_2_25 -1887437 // hz = -2.2499999999957 +#define IQ_F_VALUE_MINUS_2_24 -1879049 // hz = -2.2399999999957 +#define IQ_F_VALUE_MINUS_2_23 -1870660 // hz = -2.2299999999957 +#define IQ_F_VALUE_MINUS_2_22 -1862271 // hz = -2.2199999999957 +#define IQ_F_VALUE_MINUS_2_21 -1853883 // hz = -2.2099999999957 +#define IQ_F_VALUE_MINUS_2_20 -1845494 // hz = -2.1999999999957 +#define IQ_F_VALUE_MINUS_2_19 -1837106 // hz = -2.1899999999957 +#define IQ_F_VALUE_MINUS_2_18 -1828717 // hz = -2.1799999999957 +#define IQ_F_VALUE_MINUS_2_17 -1820328 // hz = -2.1699999999956 +#define IQ_F_VALUE_MINUS_2_16 -1811940 // hz = -2.1599999999956 +#define IQ_F_VALUE_MINUS_2_15 -1803551 // hz = -2.1499999999956 +#define IQ_F_VALUE_MINUS_2_14 -1795163 // hz = -2.1399999999956 +#define IQ_F_VALUE_MINUS_2_13 -1786774 // hz = -2.1299999999956 +#define IQ_F_VALUE_MINUS_2_12 -1778385 // hz = -2.1199999999956 +#define IQ_F_VALUE_MINUS_2_11 -1769997 // hz = -2.1099999999956 +#define IQ_F_VALUE_MINUS_2_10 -1761608 // hz = -2.0999999999956 +#define IQ_F_VALUE_MINUS_2_09 -1753220 // hz = -2.0899999999956 +#define IQ_F_VALUE_MINUS_2_08 -1744831 // hz = -2.0799999999956 +#define IQ_F_VALUE_MINUS_2_07 -1736442 // hz = -2.0699999999956 +#define IQ_F_VALUE_MINUS_2_06 -1728054 // hz = -2.0599999999956 +#define IQ_F_VALUE_MINUS_2_05 -1719665 // hz = -2.0499999999956 +#define IQ_F_VALUE_MINUS_2_04 -1711277 // hz = -2.0399999999956 +#define IQ_F_VALUE_MINUS_2_03 -1702888 // hz = -2.0299999999956 +#define IQ_F_VALUE_MINUS_2_02 -1694499 // hz = -2.0199999999956 +#define IQ_F_VALUE_MINUS_2_01 -1686111 // hz = -2.0099999999956 +#define IQ_F_VALUE_MINUS_2_00 -1677722 // hz = -1.9999999999956 +#define IQ_F_VALUE_MINUS_1_99 -1669333 // hz = -1.9899999999956 +#define IQ_F_VALUE_MINUS_1_98 -1660945 // hz = -1.9799999999956 +#define IQ_F_VALUE_MINUS_1_97 -1652556 // hz = -1.9699999999956 +#define IQ_F_VALUE_MINUS_1_96 -1644168 // hz = -1.9599999999956 +#define IQ_F_VALUE_MINUS_1_95 -1635779 // hz = -1.9499999999956 +#define IQ_F_VALUE_MINUS_1_94 -1627390 // hz = -1.9399999999956 +#define IQ_F_VALUE_MINUS_1_93 -1619002 // hz = -1.9299999999956 +#define IQ_F_VALUE_MINUS_1_92 -1610613 // hz = -1.9199999999956 +#define IQ_F_VALUE_MINUS_1_91 -1602225 // hz = -1.9099999999956 +#define IQ_F_VALUE_MINUS_1_90 -1593836 // hz = -1.8999999999956 +#define IQ_F_VALUE_MINUS_1_89 -1585447 // hz = -1.8899999999956 +#define IQ_F_VALUE_MINUS_1_88 -1577059 // hz = -1.8799999999956 +#define IQ_F_VALUE_MINUS_1_87 -1568670 // hz = -1.8699999999956 +#define IQ_F_VALUE_MINUS_1_86 -1560282 // hz = -1.8599999999956 +#define IQ_F_VALUE_MINUS_1_85 -1551893 // hz = -1.8499999999956 +#define IQ_F_VALUE_MINUS_1_84 -1543504 // hz = -1.8399999999956 +#define IQ_F_VALUE_MINUS_1_83 -1535116 // hz = -1.8299999999956 +#define IQ_F_VALUE_MINUS_1_82 -1526727 // hz = -1.8199999999956 +#define IQ_F_VALUE_MINUS_1_81 -1518339 // hz = -1.8099999999956 +#define IQ_F_VALUE_MINUS_1_80 -1509950 // hz = -1.7999999999956 +#define IQ_F_VALUE_MINUS_1_79 -1501561 // hz = -1.7899999999956 +#define IQ_F_VALUE_MINUS_1_78 -1493173 // hz = -1.7799999999956 +#define IQ_F_VALUE_MINUS_1_77 -1484784 // hz = -1.7699999999956 +#define IQ_F_VALUE_MINUS_1_76 -1476396 // hz = -1.7599999999956 +#define IQ_F_VALUE_MINUS_1_75 -1468007 // hz = -1.7499999999956 +#define IQ_F_VALUE_MINUS_1_74 -1459618 // hz = -1.7399999999956 +#define IQ_F_VALUE_MINUS_1_73 -1451230 // hz = -1.7299999999956 +#define IQ_F_VALUE_MINUS_1_72 -1442841 // hz = -1.7199999999956 +#define IQ_F_VALUE_MINUS_1_71 -1434452 // hz = -1.7099999999956 +#define IQ_F_VALUE_MINUS_1_70 -1426064 // hz = -1.6999999999956 +#define IQ_F_VALUE_MINUS_1_69 -1417675 // hz = -1.6899999999956 +#define IQ_F_VALUE_MINUS_1_68 -1409287 // hz = -1.6799999999956 +#define IQ_F_VALUE_MINUS_1_67 -1400898 // hz = -1.6699999999956 +#define IQ_F_VALUE_MINUS_1_66 -1392509 // hz = -1.6599999999956 +#define IQ_F_VALUE_MINUS_1_65 -1384121 // hz = -1.6499999999956 +#define IQ_F_VALUE_MINUS_1_64 -1375732 // hz = -1.6399999999956 +#define IQ_F_VALUE_MINUS_1_63 -1367344 // hz = -1.6299999999956 +#define IQ_F_VALUE_MINUS_1_62 -1358955 // hz = -1.6199999999956 +#define IQ_F_VALUE_MINUS_1_61 -1350566 // hz = -1.6099999999956 +#define IQ_F_VALUE_MINUS_1_60 -1342178 // hz = -1.5999999999956 +#define IQ_F_VALUE_MINUS_1_59 -1333789 // hz = -1.5899999999956 +#define IQ_F_VALUE_MINUS_1_58 -1325401 // hz = -1.5799999999956 +#define IQ_F_VALUE_MINUS_1_57 -1317012 // hz = -1.5699999999956 +#define IQ_F_VALUE_MINUS_1_56 -1308623 // hz = -1.5599999999956 +#define IQ_F_VALUE_MINUS_1_55 -1300235 // hz = -1.5499999999956 +#define IQ_F_VALUE_MINUS_1_54 -1291846 // hz = -1.5399999999956 +#define IQ_F_VALUE_MINUS_1_53 -1283458 // hz = -1.5299999999955 +#define IQ_F_VALUE_MINUS_1_52 -1275069 // hz = -1.5199999999955 +#define IQ_F_VALUE_MINUS_1_51 -1266680 // hz = -1.5099999999955 +#define IQ_F_VALUE_MINUS_1_50 -1258292 // hz = -1.4999999999955 +#define IQ_F_VALUE_MINUS_1_49 -1249903 // hz = -1.4899999999955 +#define IQ_F_VALUE_MINUS_1_48 -1241514 // hz = -1.4799999999955 +#define IQ_F_VALUE_MINUS_1_47 -1233126 // hz = -1.4699999999955 +#define IQ_F_VALUE_MINUS_1_46 -1224737 // hz = -1.4599999999955 +#define IQ_F_VALUE_MINUS_1_45 -1216349 // hz = -1.4499999999955 +#define IQ_F_VALUE_MINUS_1_44 -1207960 // hz = -1.4399999999955 +#define IQ_F_VALUE_MINUS_1_43 -1199571 // hz = -1.4299999999955 +#define IQ_F_VALUE_MINUS_1_42 -1191183 // hz = -1.4199999999955 +#define IQ_F_VALUE_MINUS_1_41 -1182794 // hz = -1.4099999999955 +#define IQ_F_VALUE_MINUS_1_40 -1174406 // hz = -1.3999999999955 +#define IQ_F_VALUE_MINUS_1_39 -1166017 // hz = -1.3899999999955 +#define IQ_F_VALUE_MINUS_1_38 -1157628 // hz = -1.3799999999955 +#define IQ_F_VALUE_MINUS_1_37 -1149240 // hz = -1.3699999999955 +#define IQ_F_VALUE_MINUS_1_36 -1140851 // hz = -1.3599999999955 +#define IQ_F_VALUE_MINUS_1_35 -1132463 // hz = -1.3499999999955 +#define IQ_F_VALUE_MINUS_1_34 -1124074 // hz = -1.3399999999955 +#define IQ_F_VALUE_MINUS_1_33 -1115685 // hz = -1.3299999999955 +#define IQ_F_VALUE_MINUS_1_32 -1107297 // hz = -1.3199999999955 +#define IQ_F_VALUE_MINUS_1_31 -1098908 // hz = -1.3099999999955 +#define IQ_F_VALUE_MINUS_1_30 -1090520 // hz = -1.2999999999955 +#define IQ_F_VALUE_MINUS_1_29 -1082131 // hz = -1.2899999999955 +#define IQ_F_VALUE_MINUS_1_28 -1073742 // hz = -1.2799999999955 +#define IQ_F_VALUE_MINUS_1_27 -1065354 // hz = -1.2699999999955 +#define IQ_F_VALUE_MINUS_1_26 -1056965 // hz = -1.2599999999955 +#define IQ_F_VALUE_MINUS_1_25 -1048576 // hz = -1.2499999999955 +#define IQ_F_VALUE_MINUS_1_24 -1040188 // hz = -1.2399999999955 +#define IQ_F_VALUE_MINUS_1_23 -1031799 // hz = -1.2299999999955 +#define IQ_F_VALUE_MINUS_1_22 -1023411 // hz = -1.2199999999955 +#define IQ_F_VALUE_MINUS_1_21 -1015022 // hz = -1.2099999999955 +#define IQ_F_VALUE_MINUS_1_20 -1006633 // hz = -1.1999999999955 +#define IQ_F_VALUE_MINUS_1_19 -998245 // hz = -1.1899999999955 +#define IQ_F_VALUE_MINUS_1_18 -989856 // hz = -1.1799999999955 +#define IQ_F_VALUE_MINUS_1_17 -981468 // hz = -1.1699999999955 +#define IQ_F_VALUE_MINUS_1_16 -973079 // hz = -1.1599999999955 +#define IQ_F_VALUE_MINUS_1_15 -964690 // hz = -1.1499999999955 +#define IQ_F_VALUE_MINUS_1_14 -956302 // hz = -1.1399999999955 +#define IQ_F_VALUE_MINUS_1_13 -947913 // hz = -1.1299999999955 +#define IQ_F_VALUE_MINUS_1_12 -939525 // hz = -1.1199999999955 +#define IQ_F_VALUE_MINUS_1_11 -931136 // hz = -1.1099999999955 +#define IQ_F_VALUE_MINUS_1_10 -922747 // hz = -1.0999999999955 +#define IQ_F_VALUE_MINUS_1_09 -914359 // hz = -1.0899999999955 +#define IQ_F_VALUE_MINUS_1_08 -905970 // hz = -1.0799999999955 +#define IQ_F_VALUE_MINUS_1_07 -897582 // hz = -1.0699999999955 +#define IQ_F_VALUE_MINUS_1_06 -889193 // hz = -1.0599999999955 +#define IQ_F_VALUE_MINUS_1_05 -880804 // hz = -1.0499999999955 +#define IQ_F_VALUE_MINUS_1_04 -872416 // hz = -1.0399999999955 +#define IQ_F_VALUE_MINUS_1_03 -864027 // hz = -1.0299999999955 +#define IQ_F_VALUE_MINUS_1_02 -855639 // hz = -1.0199999999955 +#define IQ_F_VALUE_MINUS_1_01 -847250 // hz = -1.0099999999955 +#define IQ_F_VALUE_MINUS_1_00 -838861 // hz = -0.999999999995499 +#define IQ_F_VALUE_MINUS_0_99 -830473 // hz = -0.989999999995501 +#define IQ_F_VALUE_MINUS_0_98 -822084 // hz = -0.979999999995499 +#define IQ_F_VALUE_MINUS_0_97 -813695 // hz = -0.969999999995501 +#define IQ_F_VALUE_MINUS_0_96 -805307 // hz = -0.9599999999955 +#define IQ_F_VALUE_MINUS_0_95 -796918 // hz = -0.949999999995502 +#define IQ_F_VALUE_MINUS_0_94 -788530 // hz = -0.9399999999955 +#define IQ_F_VALUE_MINUS_0_93 -780141 // hz = -0.929999999995498 +#define IQ_F_VALUE_MINUS_0_92 -771752 // hz = -0.9199999999955 +#define IQ_F_VALUE_MINUS_0_91 -763364 // hz = -0.909999999995499 +#define IQ_F_VALUE_MINUS_0_90 -754975 // hz = -0.899999999995501 +#define IQ_F_VALUE_MINUS_0_89 -746587 // hz = -0.8899999999954 +#define IQ_F_VALUE_MINUS_0_88 -738198 // hz = -0.879999999995398 +#define IQ_F_VALUE_MINUS_0_87 -729809 // hz = -0.8699999999954 +#define IQ_F_VALUE_MINUS_0_86 -721421 // hz = -0.859999999995399 +#define IQ_F_VALUE_MINUS_0_85 -713032 // hz = -0.849999999995401 +#define IQ_F_VALUE_MINUS_0_84 -704644 // hz = -0.839999999995399 +#define IQ_F_VALUE_MINUS_0_83 -696255 // hz = -0.829999999995401 +#define IQ_F_VALUE_MINUS_0_82 -687866 // hz = -0.8199999999954 +#define IQ_F_VALUE_MINUS_0_81 -679478 // hz = -0.809999999995402 +#define IQ_F_VALUE_MINUS_0_80 -671089 // hz = -0.7999999999954 +#define IQ_F_VALUE_MINUS_0_79 -662701 // hz = -0.789999999995398 +#define IQ_F_VALUE_MINUS_0_78 -654312 // hz = -0.7799999999954 +#define IQ_F_VALUE_MINUS_0_77 -645923 // hz = -0.769999999995399 +#define IQ_F_VALUE_MINUS_0_76 -637535 // hz = -0.759999999995401 +#define IQ_F_VALUE_MINUS_0_75 -629146 // hz = -0.749999999995399 +#define IQ_F_VALUE_MINUS_0_74 -620757 // hz = -0.739999999995401 +#define IQ_F_VALUE_MINUS_0_73 -612369 // hz = -0.7299999999954 +#define IQ_F_VALUE_MINUS_0_72 -603980 // hz = -0.719999999995402 +#define IQ_F_VALUE_MINUS_0_71 -595592 // hz = -0.7099999999954 +#define IQ_F_VALUE_MINUS_0_70 -587203 // hz = -0.699999999995399 +#define IQ_F_VALUE_MINUS_0_69 -578814 // hz = -0.689999999995401 +#define IQ_F_VALUE_MINUS_0_68 -570426 // hz = -0.679999999995399 +#define IQ_F_VALUE_MINUS_0_67 -562037 // hz = -0.669999999995401 +#define IQ_F_VALUE_MINUS_0_66 -553649 // hz = -0.659999999995399 +#define IQ_F_VALUE_MINUS_0_65 -545260 // hz = -0.649999999995401 +#define IQ_F_VALUE_MINUS_0_64 -536871 // hz = -0.6399999999954 +#define IQ_F_VALUE_MINUS_0_63 -528483 // hz = -0.629999999995398 +#define IQ_F_VALUE_MINUS_0_62 -520094 // hz = -0.6199999999954 +#define IQ_F_VALUE_MINUS_0_61 -511706 // hz = -0.609999999995399 +#define IQ_F_VALUE_MINUS_0_60 -503317 // hz = -0.599999999995401 +#define IQ_F_VALUE_MINUS_0_59 -494928 // hz = -0.589999999995399 +#define IQ_F_VALUE_MINUS_0_58 -486540 // hz = -0.579999999995401 +#define IQ_F_VALUE_MINUS_0_57 -478151 // hz = -0.5699999999954 +#define IQ_F_VALUE_MINUS_0_56 -469763 // hz = -0.559999999995402 +#define IQ_F_VALUE_MINUS_0_55 -461374 // hz = -0.5499999999954 +#define IQ_F_VALUE_MINUS_0_54 -452985 // hz = -0.539999999995398 +#define IQ_F_VALUE_MINUS_0_53 -444597 // hz = -0.5299999999954 +#define IQ_F_VALUE_MINUS_0_52 -436208 // hz = -0.519999999995399 +#define IQ_F_VALUE_MINUS_0_51 -427820 // hz = -0.509999999995401 +#define IQ_F_VALUE_MINUS_0_50 -419431 // hz = -0.499999999995399 +#define IQ_F_VALUE_MINUS_0_49 -411042 // hz = -0.489999999995401 +#define IQ_F_VALUE_MINUS_0_48 -402654 // hz = -0.4799999999954 +#define IQ_F_VALUE_MINUS_0_47 -394265 // hz = -0.469999999995402 +#define IQ_F_VALUE_MINUS_0_46 -385876 // hz = -0.4599999999954 +#define IQ_F_VALUE_MINUS_0_45 -377488 // hz = -0.449999999995399 +#define IQ_F_VALUE_MINUS_0_44 -369099 // hz = -0.439999999995401 +#define IQ_F_VALUE_MINUS_0_43 -360711 // hz = -0.429999999995399 +#define IQ_F_VALUE_MINUS_0_42 -352322 // hz = -0.419999999995401 +#define IQ_F_VALUE_MINUS_0_41 -343933 // hz = -0.409999999995399 +#define IQ_F_VALUE_MINUS_0_40 -335545 // hz = -0.399999999995401 +#define IQ_F_VALUE_MINUS_0_39 -327156 // hz = -0.3899999999954 +#define IQ_F_VALUE_MINUS_0_38 -318768 // hz = -0.379999999995398 +#define IQ_F_VALUE_MINUS_0_37 -310379 // hz = -0.3699999999954 +#define IQ_F_VALUE_MINUS_0_36 -301990 // hz = -0.359999999995399 +#define IQ_F_VALUE_MINUS_0_35 -293602 // hz = -0.349999999995401 +#define IQ_F_VALUE_MINUS_0_34 -285213 // hz = -0.339999999995399 +#define IQ_F_VALUE_MINUS_0_33 -276825 // hz = -0.329999999995401 +#define IQ_F_VALUE_MINUS_0_32 -268436 // hz = -0.3199999999954 +#define IQ_F_VALUE_MINUS_0_31 -260047 // hz = -0.309999999995402 +#define IQ_F_VALUE_MINUS_0_30 -251659 // hz = -0.2999999999954 +#define IQ_F_VALUE_MINUS_0_29 -243270 // hz = -0.289999999995398 +#define IQ_F_VALUE_MINUS_0_28 -234882 // hz = -0.2799999999954 +#define IQ_F_VALUE_MINUS_0_27 -226493 // hz = -0.269999999995399 +#define IQ_F_VALUE_MINUS_0_26 -218104 // hz = -0.259999999995401 +#define IQ_F_VALUE_MINUS_0_25 -209716 // hz = -0.2499999999953 +#define IQ_F_VALUE_MINUS_0_24 -201327 // hz = -0.239999999995302 +#define IQ_F_VALUE_MINUS_0_23 -192938 // hz = -0.2299999999953 +#define IQ_F_VALUE_MINUS_0_22 -184550 // hz = -0.219999999995299 +#define IQ_F_VALUE_MINUS_0_21 -176161 // hz = -0.209999999995301 +#define IQ_F_VALUE_MINUS_0_20 -167773 // hz = -0.199999999995299 +#define IQ_F_VALUE_MINUS_0_19 -159384 // hz = -0.189999999995301 +#define IQ_F_VALUE_MINUS_0_18 -150995 // hz = -0.179999999995299 +#define IQ_F_VALUE_MINUS_0_17 -142607 // hz = -0.169999999995301 +#define IQ_F_VALUE_MINUS_0_16 -134218 // hz = -0.1599999999953 +#define IQ_F_VALUE_MINUS_0_15 -125830 // hz = -0.149999999995298 +#define IQ_F_VALUE_MINUS_0_14 -117441 // hz = -0.1399999999953 +#define IQ_F_VALUE_MINUS_0_13 -109052 // hz = -0.129999999995299 +#define IQ_F_VALUE_MINUS_0_12 -100664 // hz = -0.119999999995301 +#define IQ_F_VALUE_MINUS_0_11 -92275 // hz = -0.109999999995299 +#define IQ_F_VALUE_MINUS_0_10 -83887 // hz = -0.0999999999953012 +#define IQ_F_VALUE_MINUS_0_09 -75498 // hz = -0.0899999999952996 +#define IQ_F_VALUE_MINUS_0_08 -67109 // hz = -0.0799999999953016 +#define IQ_F_VALUE_MINUS_0_07 -58721 // hz = -0.0699999999953 +#define IQ_F_VALUE_MINUS_0_06 -50332 // hz = -0.0599999999952985 +#define IQ_F_VALUE_MINUS_0_05 -41944 // hz = -0.0499999999953005 +#define IQ_F_VALUE_MINUS_0_04 -33555 // hz = -0.0399999999952989 +#define IQ_F_VALUE_MINUS_0_03 -25166 // hz = -0.0299999999953009 +#define IQ_F_VALUE_MINUS_0_02 -16778 // hz = -0.0199999999952993 +#define IQ_F_VALUE_MINUS_0_01 -8389 // hz = -0.00999999999530132 +#define IQ_F_VALUE_PLUS_0_00 0 // hz = 4.70024019705306E-12 +#define IQ_F_VALUE_PLUS_0_01 8388 // hz = 0.0100000000046983 +#define IQ_F_VALUE_PLUS_0_02 16777 // hz = 0.0200000000046998 +#define IQ_F_VALUE_PLUS_0_03 25165 // hz = 0.0300000000047014 +#define IQ_F_VALUE_PLUS_0_04 33554 // hz = 0.0400000000046994 +#define IQ_F_VALUE_PLUS_0_05 41943 // hz = 0.050000000004701 +#define IQ_F_VALUE_PLUS_0_06 50331 // hz = 0.060000000004699 +#define IQ_F_VALUE_PLUS_0_07 58720 // hz = 0.0700000000047005 +#define IQ_F_VALUE_PLUS_0_08 67108 // hz = 0.0800000000046985 +#define IQ_F_VALUE_PLUS_0_09 75497 // hz = 0.0900000000047001 +#define IQ_F_VALUE_PLUS_0_10 83886 // hz = 0.100000000004702 +#define IQ_F_VALUE_PLUS_0_11 92274 // hz = 0.1100000000047 +#define IQ_F_VALUE_PLUS_0_12 100663 // hz = 0.120000000004701 +#define IQ_F_VALUE_PLUS_0_13 109051 // hz = 0.130000000004699 +#define IQ_F_VALUE_PLUS_0_14 117440 // hz = 0.140000000004701 +#define IQ_F_VALUE_PLUS_0_15 125829 // hz = 0.150000000004699 +#define IQ_F_VALUE_PLUS_0_16 134217 // hz = 0.1600000000047 +#define IQ_F_VALUE_PLUS_0_17 142606 // hz = 0.170000000004698 +#define IQ_F_VALUE_PLUS_0_18 150994 // hz = 0.1800000000047 +#define IQ_F_VALUE_PLUS_0_19 159383 // hz = 0.190000000004702 +#define IQ_F_VALUE_PLUS_0_20 167772 // hz = 0.2000000000047 +#define IQ_F_VALUE_PLUS_0_21 176160 // hz = 0.210000000004701 +#define IQ_F_VALUE_PLUS_0_22 184549 // hz = 0.220000000004699 +#define IQ_F_VALUE_PLUS_0_23 192937 // hz = 0.230000000004701 +#define IQ_F_VALUE_PLUS_0_24 201326 // hz = 0.240000000004699 +#define IQ_F_VALUE_PLUS_0_25 209715 // hz = 0.2500000000047 +#define IQ_F_VALUE_PLUS_0_26 218103 // hz = 0.260000000004698 +#define IQ_F_VALUE_PLUS_0_27 226492 // hz = 0.2700000000047 +#define IQ_F_VALUE_PLUS_0_28 234881 // hz = 0.280000000004701 +#define IQ_F_VALUE_PLUS_0_29 243269 // hz = 0.290000000004699 +#define IQ_F_VALUE_PLUS_0_30 251658 // hz = 0.300000000004701 +#define IQ_F_VALUE_PLUS_0_31 260046 // hz = 0.310000000004699 +#define IQ_F_VALUE_PLUS_0_32 268435 // hz = 0.320000000004701 +#define IQ_F_VALUE_PLUS_0_33 276824 // hz = 0.330000000004699 +#define IQ_F_VALUE_PLUS_0_34 285212 // hz = 0.3400000000047 +#define IQ_F_VALUE_PLUS_0_35 293601 // hz = 0.350000000004702 +#define IQ_F_VALUE_PLUS_0_36 301989 // hz = 0.3600000000047 +#define IQ_F_VALUE_PLUS_0_37 310378 // hz = 0.370000000004701 +#define IQ_F_VALUE_PLUS_0_38 318767 // hz = 0.380000000004699 +#define IQ_F_VALUE_PLUS_0_39 327155 // hz = 0.3900000000048 +#define IQ_F_VALUE_PLUS_0_40 335544 // hz = 0.400000000004798 +#define IQ_F_VALUE_PLUS_0_41 343932 // hz = 0.4100000000048 +#define IQ_F_VALUE_PLUS_0_42 352321 // hz = 0.420000000004801 +#define IQ_F_VALUE_PLUS_0_43 360710 // hz = 0.430000000004799 +#define IQ_F_VALUE_PLUS_0_44 369098 // hz = 0.440000000004801 +#define IQ_F_VALUE_PLUS_0_45 377487 // hz = 0.450000000004799 +#define IQ_F_VALUE_PLUS_0_46 385875 // hz = 0.460000000004801 +#define IQ_F_VALUE_PLUS_0_47 394264 // hz = 0.470000000004799 +#define IQ_F_VALUE_PLUS_0_48 402653 // hz = 0.4800000000048 +#define IQ_F_VALUE_PLUS_0_49 411041 // hz = 0.490000000004802 +#define IQ_F_VALUE_PLUS_0_50 419430 // hz = 0.5000000000048 +#define IQ_F_VALUE_PLUS_0_51 427819 // hz = 0.510000000004801 +#define IQ_F_VALUE_PLUS_0_52 436207 // hz = 0.520000000004799 +#define IQ_F_VALUE_PLUS_0_53 444596 // hz = 0.530000000004801 +#define IQ_F_VALUE_PLUS_0_54 452984 // hz = 0.540000000004799 +#define IQ_F_VALUE_PLUS_0_55 461373 // hz = 0.5500000000048 +#define IQ_F_VALUE_PLUS_0_56 469762 // hz = 0.560000000004798 +#define IQ_F_VALUE_PLUS_0_57 478150 // hz = 0.5700000000048 +#define IQ_F_VALUE_PLUS_0_58 486539 // hz = 0.580000000004802 +#define IQ_F_VALUE_PLUS_0_59 494927 // hz = 0.5900000000048 +#define IQ_F_VALUE_PLUS_0_60 503316 // hz = 0.600000000004801 +#define IQ_F_VALUE_PLUS_0_61 511705 // hz = 0.610000000004799 +#define IQ_F_VALUE_PLUS_0_62 520093 // hz = 0.620000000004801 +#define IQ_F_VALUE_PLUS_0_63 528482 // hz = 0.630000000004799 +#define IQ_F_VALUE_PLUS_0_64 536870 // hz = 0.6400000000048 +#define IQ_F_VALUE_PLUS_0_65 545259 // hz = 0.650000000004798 +#define IQ_F_VALUE_PLUS_0_66 553648 // hz = 0.6600000000048 +#define IQ_F_VALUE_PLUS_0_67 562036 // hz = 0.670000000004801 +#define IQ_F_VALUE_PLUS_0_68 570425 // hz = 0.680000000004799 +#define IQ_F_VALUE_PLUS_0_69 578813 // hz = 0.690000000004801 +#define IQ_F_VALUE_PLUS_0_70 587202 // hz = 0.700000000004799 +#define IQ_F_VALUE_PLUS_0_71 595591 // hz = 0.710000000004801 +#define IQ_F_VALUE_PLUS_0_72 603979 // hz = 0.720000000004799 +#define IQ_F_VALUE_PLUS_0_73 612368 // hz = 0.7300000000048 +#define IQ_F_VALUE_PLUS_0_74 620756 // hz = 0.740000000004802 +#define IQ_F_VALUE_PLUS_0_75 629145 // hz = 0.7500000000048 +#define IQ_F_VALUE_PLUS_0_76 637534 // hz = 0.760000000004801 +#define IQ_F_VALUE_PLUS_0_77 645922 // hz = 0.770000000004799 +#define IQ_F_VALUE_PLUS_0_78 654311 // hz = 0.780000000004801 +#define IQ_F_VALUE_PLUS_0_79 662700 // hz = 0.790000000004799 +#define IQ_F_VALUE_PLUS_0_80 671088 // hz = 0.8000000000048 +#define IQ_F_VALUE_PLUS_0_81 679477 // hz = 0.810000000004798 +#define IQ_F_VALUE_PLUS_0_82 687865 // hz = 0.8200000000048 +#define IQ_F_VALUE_PLUS_0_83 696254 // hz = 0.830000000004802 +#define IQ_F_VALUE_PLUS_0_84 704643 // hz = 0.8400000000048 +#define IQ_F_VALUE_PLUS_0_85 713031 // hz = 0.850000000004801 +#define IQ_F_VALUE_PLUS_0_86 721420 // hz = 0.860000000004799 +#define IQ_F_VALUE_PLUS_0_87 729808 // hz = 0.870000000004801 +#define IQ_F_VALUE_PLUS_0_88 738197 // hz = 0.880000000004799 +#define IQ_F_VALUE_PLUS_0_89 746586 // hz = 0.8900000000048 +#define IQ_F_VALUE_PLUS_0_90 754974 // hz = 0.900000000004798 +#define IQ_F_VALUE_PLUS_0_91 763363 // hz = 0.9100000000048 +#define IQ_F_VALUE_PLUS_0_92 771751 // hz = 0.920000000004801 +#define IQ_F_VALUE_PLUS_0_93 780140 // hz = 0.930000000004799 +#define IQ_F_VALUE_PLUS_0_94 788529 // hz = 0.940000000004801 +#define IQ_F_VALUE_PLUS_0_95 796917 // hz = 0.950000000004799 +#define IQ_F_VALUE_PLUS_0_96 805306 // hz = 0.960000000004801 +#define IQ_F_VALUE_PLUS_0_97 813694 // hz = 0.970000000004799 +#define IQ_F_VALUE_PLUS_0_98 822083 // hz = 0.9800000000048 +#define IQ_F_VALUE_PLUS_0_99 830472 // hz = 0.990000000004802 +#define IQ_F_VALUE_PLUS_1_00 838860 // hz = 1.0000000000048 +#define IQ_F_VALUE_PLUS_1_01 847249 // hz = 1.0100000000048 +#define IQ_F_VALUE_PLUS_1_02 855638 // hz = 1.0200000000048 +#define IQ_F_VALUE_PLUS_1_03 864026 // hz = 1.0300000000049 +#define IQ_F_VALUE_PLUS_1_04 872415 // hz = 1.0400000000049 +#define IQ_F_VALUE_PLUS_1_05 880803 // hz = 1.0500000000049 +#define IQ_F_VALUE_PLUS_1_06 889192 // hz = 1.0600000000049 +#define IQ_F_VALUE_PLUS_1_07 897581 // hz = 1.0700000000049 +#define IQ_F_VALUE_PLUS_1_08 905969 // hz = 1.0800000000049 +#define IQ_F_VALUE_PLUS_1_09 914358 // hz = 1.0900000000049 +#define IQ_F_VALUE_PLUS_1_10 922746 // hz = 1.1000000000049 +#define IQ_F_VALUE_PLUS_1_11 931135 // hz = 1.1100000000049 +#define IQ_F_VALUE_PLUS_1_12 939524 // hz = 1.1200000000049 +#define IQ_F_VALUE_PLUS_1_13 947912 // hz = 1.1300000000049 +#define IQ_F_VALUE_PLUS_1_14 956301 // hz = 1.1400000000049 +#define IQ_F_VALUE_PLUS_1_15 964689 // hz = 1.1500000000049 +#define IQ_F_VALUE_PLUS_1_16 973078 // hz = 1.1600000000049 +#define IQ_F_VALUE_PLUS_1_17 981467 // hz = 1.1700000000049 +#define IQ_F_VALUE_PLUS_1_18 989855 // hz = 1.1800000000049 +#define IQ_F_VALUE_PLUS_1_19 998244 // hz = 1.1900000000049 +#define IQ_F_VALUE_PLUS_1_20 1006632 // hz = 1.2000000000049 +#define IQ_F_VALUE_PLUS_1_21 1015021 // hz = 1.2100000000049 +#define IQ_F_VALUE_PLUS_1_22 1023410 // hz = 1.2200000000049 +#define IQ_F_VALUE_PLUS_1_23 1031798 // hz = 1.2300000000049 +#define IQ_F_VALUE_PLUS_1_24 1040187 // hz = 1.2400000000049 +#define IQ_F_VALUE_PLUS_1_25 1048576 // hz = 1.2500000000049 +#define IQ_F_VALUE_PLUS_1_26 1056964 // hz = 1.2600000000049 +#define IQ_F_VALUE_PLUS_1_27 1065353 // hz = 1.2700000000049 +#define IQ_F_VALUE_PLUS_1_28 1073741 // hz = 1.2800000000049 +#define IQ_F_VALUE_PLUS_1_29 1082130 // hz = 1.2900000000049 +#define IQ_F_VALUE_PLUS_1_30 1090519 // hz = 1.3000000000049 +#define IQ_F_VALUE_PLUS_1_31 1098907 // hz = 1.3100000000049 +#define IQ_F_VALUE_PLUS_1_32 1107296 // hz = 1.3200000000049 +#define IQ_F_VALUE_PLUS_1_33 1115684 // hz = 1.3300000000049 +#define IQ_F_VALUE_PLUS_1_34 1124073 // hz = 1.3400000000049 +#define IQ_F_VALUE_PLUS_1_35 1132462 // hz = 1.3500000000049 +#define IQ_F_VALUE_PLUS_1_36 1140850 // hz = 1.3600000000049 +#define IQ_F_VALUE_PLUS_1_37 1149239 // hz = 1.3700000000049 +#define IQ_F_VALUE_PLUS_1_38 1157627 // hz = 1.3800000000049 +#define IQ_F_VALUE_PLUS_1_39 1166016 // hz = 1.3900000000049 +#define IQ_F_VALUE_PLUS_1_40 1174405 // hz = 1.4000000000049 +#define IQ_F_VALUE_PLUS_1_41 1182793 // hz = 1.4100000000049 +#define IQ_F_VALUE_PLUS_1_42 1191182 // hz = 1.4200000000049 +#define IQ_F_VALUE_PLUS_1_43 1199570 // hz = 1.4300000000049 +#define IQ_F_VALUE_PLUS_1_44 1207959 // hz = 1.4400000000049 +#define IQ_F_VALUE_PLUS_1_45 1216348 // hz = 1.4500000000049 +#define IQ_F_VALUE_PLUS_1_46 1224736 // hz = 1.4600000000049 +#define IQ_F_VALUE_PLUS_1_47 1233125 // hz = 1.4700000000049 +#define IQ_F_VALUE_PLUS_1_48 1241513 // hz = 1.4800000000049 +#define IQ_F_VALUE_PLUS_1_49 1249902 // hz = 1.4900000000049 +#define IQ_F_VALUE_PLUS_1_50 1258291 // hz = 1.5000000000049 +#define IQ_F_VALUE_PLUS_1_51 1266679 // hz = 1.5100000000049 +#define IQ_F_VALUE_PLUS_1_52 1275068 // hz = 1.5200000000049 +#define IQ_F_VALUE_PLUS_1_53 1283457 // hz = 1.5300000000049 +#define IQ_F_VALUE_PLUS_1_54 1291845 // hz = 1.5400000000049 +#define IQ_F_VALUE_PLUS_1_55 1300234 // hz = 1.5500000000049 +#define IQ_F_VALUE_PLUS_1_56 1308622 // hz = 1.5600000000049 +#define IQ_F_VALUE_PLUS_1_57 1317011 // hz = 1.5700000000049 +#define IQ_F_VALUE_PLUS_1_58 1325400 // hz = 1.5800000000049 +#define IQ_F_VALUE_PLUS_1_59 1333788 // hz = 1.5900000000049 +#define IQ_F_VALUE_PLUS_1_60 1342177 // hz = 1.6000000000049 +#define IQ_F_VALUE_PLUS_1_61 1350565 // hz = 1.6100000000049 +#define IQ_F_VALUE_PLUS_1_62 1358954 // hz = 1.6200000000049 +#define IQ_F_VALUE_PLUS_1_63 1367343 // hz = 1.6300000000049 +#define IQ_F_VALUE_PLUS_1_64 1375731 // hz = 1.6400000000049 +#define IQ_F_VALUE_PLUS_1_65 1384120 // hz = 1.6500000000049 +#define IQ_F_VALUE_PLUS_1_66 1392508 // hz = 1.6600000000049 +#define IQ_F_VALUE_PLUS_1_67 1400897 // hz = 1.670000000005 +#define IQ_F_VALUE_PLUS_1_68 1409286 // hz = 1.680000000005 +#define IQ_F_VALUE_PLUS_1_69 1417674 // hz = 1.690000000005 +#define IQ_F_VALUE_PLUS_1_70 1426063 // hz = 1.700000000005 +#define IQ_F_VALUE_PLUS_1_71 1434451 // hz = 1.710000000005 +#define IQ_F_VALUE_PLUS_1_72 1442840 // hz = 1.720000000005 +#define IQ_F_VALUE_PLUS_1_73 1451229 // hz = 1.730000000005 +#define IQ_F_VALUE_PLUS_1_74 1459617 // hz = 1.740000000005 +#define IQ_F_VALUE_PLUS_1_75 1468006 // hz = 1.750000000005 +#define IQ_F_VALUE_PLUS_1_76 1476395 // hz = 1.760000000005 +#define IQ_F_VALUE_PLUS_1_77 1484783 // hz = 1.770000000005 +#define IQ_F_VALUE_PLUS_1_78 1493172 // hz = 1.780000000005 +#define IQ_F_VALUE_PLUS_1_79 1501560 // hz = 1.790000000005 +#define IQ_F_VALUE_PLUS_1_80 1509949 // hz = 1.800000000005 +#define IQ_F_VALUE_PLUS_1_81 1518338 // hz = 1.810000000005 +#define IQ_F_VALUE_PLUS_1_82 1526726 // hz = 1.820000000005 +#define IQ_F_VALUE_PLUS_1_83 1535115 // hz = 1.830000000005 +#define IQ_F_VALUE_PLUS_1_84 1543503 // hz = 1.840000000005 +#define IQ_F_VALUE_PLUS_1_85 1551892 // hz = 1.850000000005 +#define IQ_F_VALUE_PLUS_1_86 1560281 // hz = 1.860000000005 +#define IQ_F_VALUE_PLUS_1_87 1568669 // hz = 1.870000000005 +#define IQ_F_VALUE_PLUS_1_88 1577058 // hz = 1.880000000005 +#define IQ_F_VALUE_PLUS_1_89 1585446 // hz = 1.890000000005 +#define IQ_F_VALUE_PLUS_1_90 1593835 // hz = 1.900000000005 +#define IQ_F_VALUE_PLUS_1_91 1602224 // hz = 1.910000000005 +#define IQ_F_VALUE_PLUS_1_92 1610612 // hz = 1.920000000005 +#define IQ_F_VALUE_PLUS_1_93 1619001 // hz = 1.930000000005 +#define IQ_F_VALUE_PLUS_1_94 1627389 // hz = 1.940000000005 +#define IQ_F_VALUE_PLUS_1_95 1635778 // hz = 1.950000000005 +#define IQ_F_VALUE_PLUS_1_96 1644167 // hz = 1.960000000005 +#define IQ_F_VALUE_PLUS_1_97 1652555 // hz = 1.970000000005 +#define IQ_F_VALUE_PLUS_1_98 1660944 // hz = 1.980000000005 +#define IQ_F_VALUE_PLUS_1_99 1669332 // hz = 1.990000000005 +#define IQ_F_VALUE_PLUS_2_00 1677721 // hz = 2.000000000005 +#define IQ_F_VALUE_PLUS_2_01 1686110 // hz = 2.010000000005 +#define IQ_F_VALUE_PLUS_2_02 1694498 // hz = 2.020000000005 +#define IQ_F_VALUE_PLUS_2_03 1702887 // hz = 2.030000000005 +#define IQ_F_VALUE_PLUS_2_04 1711276 // hz = 2.040000000005 +#define IQ_F_VALUE_PLUS_2_05 1719664 // hz = 2.050000000005 +#define IQ_F_VALUE_PLUS_2_06 1728053 // hz = 2.060000000005 +#define IQ_F_VALUE_PLUS_2_07 1736441 // hz = 2.070000000005 +#define IQ_F_VALUE_PLUS_2_08 1744830 // hz = 2.080000000005 +#define IQ_F_VALUE_PLUS_2_09 1753219 // hz = 2.090000000005 +#define IQ_F_VALUE_PLUS_2_10 1761607 // hz = 2.100000000005 +#define IQ_F_VALUE_PLUS_2_11 1769996 // hz = 2.110000000005 +#define IQ_F_VALUE_PLUS_2_12 1778384 // hz = 2.120000000005 +#define IQ_F_VALUE_PLUS_2_13 1786773 // hz = 2.130000000005 +#define IQ_F_VALUE_PLUS_2_14 1795162 // hz = 2.140000000005 +#define IQ_F_VALUE_PLUS_2_15 1803550 // hz = 2.150000000005 +#define IQ_F_VALUE_PLUS_2_16 1811939 // hz = 2.160000000005 +#define IQ_F_VALUE_PLUS_2_17 1820327 // hz = 2.170000000005 +#define IQ_F_VALUE_PLUS_2_18 1828716 // hz = 2.180000000005 +#define IQ_F_VALUE_PLUS_2_19 1837105 // hz = 2.190000000005 +#define IQ_F_VALUE_PLUS_2_20 1845493 // hz = 2.200000000005 +#define IQ_F_VALUE_PLUS_2_21 1853882 // hz = 2.210000000005 +#define IQ_F_VALUE_PLUS_2_22 1862270 // hz = 2.220000000005 +#define IQ_F_VALUE_PLUS_2_23 1870659 // hz = 2.230000000005 +#define IQ_F_VALUE_PLUS_2_24 1879048 // hz = 2.240000000005 +#define IQ_F_VALUE_PLUS_2_25 1887436 // hz = 2.250000000005 +#define IQ_F_VALUE_PLUS_2_26 1895825 // hz = 2.260000000005 +#define IQ_F_VALUE_PLUS_2_27 1904214 // hz = 2.270000000005 +#define IQ_F_VALUE_PLUS_2_28 1912602 // hz = 2.280000000005 +#define IQ_F_VALUE_PLUS_2_29 1920991 // hz = 2.2900000000051 +#define IQ_F_VALUE_PLUS_2_30 1929379 // hz = 2.300000000005 +#define IQ_F_VALUE_PLUS_2_31 1937768 // hz = 2.310000000005 +#define IQ_F_VALUE_PLUS_2_32 1946157 // hz = 2.3200000000051 +#define IQ_F_VALUE_PLUS_2_33 1954545 // hz = 2.3300000000051 +#define IQ_F_VALUE_PLUS_2_34 1962934 // hz = 2.3400000000051 +#define IQ_F_VALUE_PLUS_2_35 1971322 // hz = 2.3500000000051 +#define IQ_F_VALUE_PLUS_2_36 1979711 // hz = 2.3600000000051 +#define IQ_F_VALUE_PLUS_2_37 1988100 // hz = 2.3700000000051 +#define IQ_F_VALUE_PLUS_2_38 1996488 // hz = 2.3800000000051 +#define IQ_F_VALUE_PLUS_2_39 2004877 // hz = 2.3900000000051 +#define IQ_F_VALUE_PLUS_2_40 2013265 // hz = 2.4000000000051 +#define IQ_F_VALUE_PLUS_2_41 2021654 // hz = 2.4100000000051 +#define IQ_F_VALUE_PLUS_2_42 2030043 // hz = 2.4200000000051 +#define IQ_F_VALUE_PLUS_2_43 2038431 // hz = 2.4300000000051 +#define IQ_F_VALUE_PLUS_2_44 2046820 // hz = 2.4400000000051 +#define IQ_F_VALUE_PLUS_2_45 2055208 // hz = 2.4500000000051 +#define IQ_F_VALUE_PLUS_2_46 2063597 // hz = 2.4600000000051 +#define IQ_F_VALUE_PLUS_2_47 2071986 // hz = 2.4700000000051 +#define IQ_F_VALUE_PLUS_2_48 2080374 // hz = 2.4800000000051 +#define IQ_F_VALUE_PLUS_2_49 2088763 // hz = 2.4900000000051 +#define IQ_F_VALUE_PLUS_2_50 2097152 // hz = 2.5000000000051 +#define IQ_F_VALUE_PLUS_2_51 2105540 // hz = 2.5100000000051 +#define IQ_F_VALUE_PLUS_2_52 2113929 // hz = 2.5200000000051 +#define IQ_F_VALUE_PLUS_2_53 2122317 // hz = 2.5300000000051 +#define IQ_F_VALUE_PLUS_2_54 2130706 // hz = 2.5400000000051 +#define IQ_F_VALUE_PLUS_2_55 2139095 // hz = 2.5500000000051 +#define IQ_F_VALUE_PLUS_2_56 2147483 // hz = 2.5600000000051 +#define IQ_F_VALUE_PLUS_2_57 2155872 // hz = 2.5700000000051 +#define IQ_F_VALUE_PLUS_2_58 2164260 // hz = 2.5800000000051 +#define IQ_F_VALUE_PLUS_2_59 2172649 // hz = 2.5900000000051 +#define IQ_F_VALUE_PLUS_2_60 2181038 // hz = 2.6000000000051 +#define IQ_F_VALUE_PLUS_2_61 2189426 // hz = 2.6100000000051 +#define IQ_F_VALUE_PLUS_2_62 2197815 // hz = 2.6200000000051 +#define IQ_F_VALUE_PLUS_2_63 2206203 // hz = 2.6300000000051 +#define IQ_F_VALUE_PLUS_2_64 2214592 // hz = 2.6400000000051 +#define IQ_F_VALUE_PLUS_2_65 2222981 // hz = 2.6500000000051 +#define IQ_F_VALUE_PLUS_2_66 2231369 // hz = 2.6600000000051 +#define IQ_F_VALUE_PLUS_2_67 2239758 // hz = 2.6700000000051 +#define IQ_F_VALUE_PLUS_2_68 2248146 // hz = 2.6800000000051 +#define IQ_F_VALUE_PLUS_2_69 2256535 // hz = 2.6900000000051 +#define IQ_F_VALUE_PLUS_2_70 2264924 // hz = 2.7000000000051 +#define IQ_F_VALUE_PLUS_2_71 2273312 // hz = 2.7100000000051 +#define IQ_F_VALUE_PLUS_2_72 2281701 // hz = 2.7200000000051 +#define IQ_F_VALUE_PLUS_2_73 2290089 // hz = 2.7300000000051 +#define IQ_F_VALUE_PLUS_2_74 2298478 // hz = 2.7400000000051 +#define IQ_F_VALUE_PLUS_2_75 2306867 // hz = 2.7500000000051 +#define IQ_F_VALUE_PLUS_2_76 2315255 // hz = 2.7600000000051 +#define IQ_F_VALUE_PLUS_2_77 2323644 // hz = 2.7700000000051 +#define IQ_F_VALUE_PLUS_2_78 2332033 // hz = 2.7800000000051 +#define IQ_F_VALUE_PLUS_2_79 2340421 // hz = 2.7900000000051 +#define IQ_F_VALUE_PLUS_2_80 2348810 // hz = 2.8000000000051 +#define IQ_F_VALUE_PLUS_2_81 2357198 // hz = 2.8100000000051 +#define IQ_F_VALUE_PLUS_2_82 2365587 // hz = 2.8200000000051 +#define IQ_F_VALUE_PLUS_2_83 2373976 // hz = 2.8300000000051 +#define IQ_F_VALUE_PLUS_2_84 2382364 // hz = 2.8400000000051 +#define IQ_F_VALUE_PLUS_2_85 2390753 // hz = 2.8500000000051 +#define IQ_F_VALUE_PLUS_2_86 2399141 // hz = 2.8600000000051 +#define IQ_F_VALUE_PLUS_2_87 2407530 // hz = 2.8700000000051 +#define IQ_F_VALUE_PLUS_2_88 2415919 // hz = 2.8800000000051 +#define IQ_F_VALUE_PLUS_2_89 2424307 // hz = 2.8900000000051 +#define IQ_F_VALUE_PLUS_2_90 2432696 // hz = 2.9000000000051 +#define IQ_F_VALUE_PLUS_2_91 2441084 // hz = 2.9100000000051 +#define IQ_F_VALUE_PLUS_2_92 2449473 // hz = 2.9200000000051 +#define IQ_F_VALUE_PLUS_2_93 2457862 // hz = 2.9300000000052 +#define IQ_F_VALUE_PLUS_2_94 2466250 // hz = 2.9400000000051 +#define IQ_F_VALUE_PLUS_2_95 2474639 // hz = 2.9500000000051 +#define IQ_F_VALUE_PLUS_2_96 2483027 // hz = 2.9600000000052 +#define IQ_F_VALUE_PLUS_2_97 2491416 // hz = 2.9700000000052 +#define IQ_F_VALUE_PLUS_2_98 2499805 // hz = 2.9800000000052 +#define IQ_F_VALUE_PLUS_2_99 2508193 // hz = 2.9900000000052 +#define IQ_F_VALUE_PLUS_3_00 2516582 // hz = 3.0000000000052 +#define IQ_F_VALUE_PLUS_3_01 2524971 // hz = 3.0100000000052 +#define IQ_F_VALUE_PLUS_3_02 2533359 // hz = 3.0200000000052 +#define IQ_F_VALUE_PLUS_3_03 2541748 // hz = 3.0300000000052 +#define IQ_F_VALUE_PLUS_3_04 2550136 // hz = 3.0400000000052 +#define IQ_F_VALUE_PLUS_3_05 2558525 // hz = 3.0500000000052 +#define IQ_F_VALUE_PLUS_3_06 2566914 // hz = 3.0600000000052 +#define IQ_F_VALUE_PLUS_3_07 2575302 // hz = 3.0700000000052 +#define IQ_F_VALUE_PLUS_3_08 2583691 // hz = 3.0800000000052 +#define IQ_F_VALUE_PLUS_3_09 2592079 // hz = 3.0900000000052 +#define IQ_F_VALUE_PLUS_3_10 2600468 // hz = 3.1000000000052 +#define IQ_F_VALUE_PLUS_3_11 2608857 // hz = 3.1100000000052 +#define IQ_F_VALUE_PLUS_3_12 2617245 // hz = 3.1200000000052 +#define IQ_F_VALUE_PLUS_3_13 2625634 // hz = 3.1300000000052 +#define IQ_F_VALUE_PLUS_3_14 2634022 // hz = 3.1400000000052 +#define IQ_F_VALUE_PLUS_3_15 2642411 // hz = 3.1500000000052 +#define IQ_F_VALUE_PLUS_3_16 2650800 // hz = 3.1600000000052 +#define IQ_F_VALUE_PLUS_3_17 2659188 // hz = 3.1700000000052 +#define IQ_F_VALUE_PLUS_3_18 2667577 // hz = 3.1800000000052 +#define IQ_F_VALUE_PLUS_3_19 2675965 // hz = 3.1900000000052 +#define IQ_F_VALUE_PLUS_3_20 2684354 // hz = 3.2000000000052 +#define IQ_F_VALUE_PLUS_3_21 2692743 // hz = 3.2100000000052 +#define IQ_F_VALUE_PLUS_3_22 2701131 // hz = 3.2200000000052 +#define IQ_F_VALUE_PLUS_3_23 2709520 // hz = 3.2300000000052 +#define IQ_F_VALUE_PLUS_3_24 2717908 // hz = 3.2400000000052 +#define IQ_F_VALUE_PLUS_3_25 2726297 // hz = 3.2500000000052 +#define IQ_F_VALUE_PLUS_3_26 2734686 // hz = 3.2600000000052 +#define IQ_F_VALUE_PLUS_3_27 2743074 // hz = 3.2700000000052 +#define IQ_F_VALUE_PLUS_3_28 2751463 // hz = 3.2800000000052 +#define IQ_F_VALUE_PLUS_3_29 2759852 // hz = 3.2900000000052 +#define IQ_F_VALUE_PLUS_3_30 2768240 // hz = 3.3000000000052 +#define IQ_F_VALUE_PLUS_3_31 2776629 // hz = 3.3100000000052 +#define IQ_F_VALUE_PLUS_3_32 2785017 // hz = 3.3200000000052 +#define IQ_F_VALUE_PLUS_3_33 2793406 // hz = 3.3300000000052 +#define IQ_F_VALUE_PLUS_3_34 2801795 // hz = 3.3400000000052 +#define IQ_F_VALUE_PLUS_3_35 2810183 // hz = 3.3500000000052 +#define IQ_F_VALUE_PLUS_3_36 2818572 // hz = 3.3600000000052 +#define IQ_F_VALUE_PLUS_3_37 2826960 // hz = 3.3700000000052 +#define IQ_F_VALUE_PLUS_3_38 2835349 // hz = 3.3800000000052 +#define IQ_F_VALUE_PLUS_3_39 2843738 // hz = 3.3900000000052 +#define IQ_F_VALUE_PLUS_3_40 2852126 // hz = 3.4000000000052 +#define IQ_F_VALUE_PLUS_3_41 2860515 // hz = 3.4100000000052 +#define IQ_F_VALUE_PLUS_3_42 2868903 // hz = 3.4200000000052 +#define IQ_F_VALUE_PLUS_3_43 2877292 // hz = 3.4300000000052 +#define IQ_F_VALUE_PLUS_3_44 2885681 // hz = 3.4400000000052 +#define IQ_F_VALUE_PLUS_3_45 2894069 // hz = 3.4500000000052 +#define IQ_F_VALUE_PLUS_3_46 2902458 // hz = 3.4600000000052 +#define IQ_F_VALUE_PLUS_3_47 2910846 // hz = 3.4700000000052 +#define IQ_F_VALUE_PLUS_3_48 2919235 // hz = 3.4800000000052 +#define IQ_F_VALUE_PLUS_3_49 2927624 // hz = 3.4900000000052 +#define IQ_F_VALUE_PLUS_3_50 2936012 // hz = 3.5000000000052 +#define IQ_F_VALUE_PLUS_3_51 2944401 // hz = 3.5100000000052 +#define IQ_F_VALUE_PLUS_3_52 2952790 // hz = 3.5200000000052 +#define IQ_F_VALUE_PLUS_3_53 2961178 // hz = 3.5300000000052 +#define IQ_F_VALUE_PLUS_3_54 2969567 // hz = 3.5400000000052 +#define IQ_F_VALUE_PLUS_3_55 2977955 // hz = 3.5500000000052 +#define IQ_F_VALUE_PLUS_3_56 2986344 // hz = 3.5600000000052 +#define IQ_F_VALUE_PLUS_3_57 2994733 // hz = 3.5700000000053 +#define IQ_F_VALUE_PLUS_3_58 3003121 // hz = 3.5800000000052 +#define IQ_F_VALUE_PLUS_3_59 3011510 // hz = 3.5900000000052 +#define IQ_F_VALUE_PLUS_3_60 3019898 // hz = 3.6000000000053 +#define IQ_F_VALUE_PLUS_3_61 3028287 // hz = 3.6100000000053 +#define IQ_F_VALUE_PLUS_3_62 3036676 // hz = 3.6200000000053 +#define IQ_F_VALUE_PLUS_3_63 3045064 // hz = 3.6300000000053 +#define IQ_F_VALUE_PLUS_3_64 3053453 // hz = 3.6400000000053 +#define IQ_F_VALUE_PLUS_3_65 3061841 // hz = 3.6500000000053 +#define IQ_F_VALUE_PLUS_3_66 3070230 // hz = 3.6600000000053 +#define IQ_F_VALUE_PLUS_3_67 3078619 // hz = 3.6700000000053 +#define IQ_F_VALUE_PLUS_3_68 3087007 // hz = 3.6800000000053 +#define IQ_F_VALUE_PLUS_3_69 3095396 // hz = 3.6900000000053 +#define IQ_F_VALUE_PLUS_3_70 3103784 // hz = 3.7000000000053 +#define IQ_F_VALUE_PLUS_3_71 3112173 // hz = 3.7100000000053 +#define IQ_F_VALUE_PLUS_3_72 3120562 // hz = 3.7200000000053 +#define IQ_F_VALUE_PLUS_3_73 3128950 // hz = 3.7300000000053 +#define IQ_F_VALUE_PLUS_3_74 3137339 // hz = 3.7400000000053 +#define IQ_F_VALUE_PLUS_3_75 3145728 // hz = 3.7500000000053 +#define IQ_F_VALUE_PLUS_3_76 3154116 // hz = 3.7600000000053 +#define IQ_F_VALUE_PLUS_3_77 3162505 // hz = 3.7700000000053 +#define IQ_F_VALUE_PLUS_3_78 3170893 // hz = 3.7800000000053 +#define IQ_F_VALUE_PLUS_3_79 3179282 // hz = 3.7900000000053 +#define IQ_F_VALUE_PLUS_3_80 3187671 // hz = 3.8000000000053 +#define IQ_F_VALUE_PLUS_3_81 3196059 // hz = 3.8100000000053 +#define IQ_F_VALUE_PLUS_3_82 3204448 // hz = 3.8200000000053 +#define IQ_F_VALUE_PLUS_3_83 3212836 // hz = 3.8300000000053 +#define IQ_F_VALUE_PLUS_3_84 3221225 // hz = 3.8400000000053 +#define IQ_F_VALUE_PLUS_3_85 3229614 // hz = 3.8500000000053 +#define IQ_F_VALUE_PLUS_3_86 3238002 // hz = 3.8600000000053 +#define IQ_F_VALUE_PLUS_3_87 3246391 // hz = 3.8700000000053 +#define IQ_F_VALUE_PLUS_3_88 3254779 // hz = 3.8800000000053 +#define IQ_F_VALUE_PLUS_3_89 3263168 // hz = 3.8900000000053 +#define IQ_F_VALUE_PLUS_3_90 3271557 // hz = 3.9000000000053 +#define IQ_F_VALUE_PLUS_3_91 3279945 // hz = 3.9100000000053 +#define IQ_F_VALUE_PLUS_3_92 3288334 // hz = 3.9200000000053 +#define IQ_F_VALUE_PLUS_3_93 3296722 // hz = 3.9300000000053 +#define IQ_F_VALUE_PLUS_3_94 3305111 // hz = 3.9400000000053 +#define IQ_F_VALUE_PLUS_3_95 3313500 // hz = 3.9500000000053 +#define IQ_F_VALUE_PLUS_3_96 3321888 // hz = 3.9600000000053 +#define IQ_F_VALUE_PLUS_3_97 3330277 // hz = 3.9700000000053 +#define IQ_F_VALUE_PLUS_3_98 3338665 // hz = 3.9800000000053 +#define IQ_F_VALUE_PLUS_3_99 3347054 // hz = 3.9900000000053 +#define IQ_F_VALUE_PLUS_4_00 3355443 // hz = 4.0000000000053 +#define IQ_F_VALUE_PLUS_4_01 3363831 // hz = 4.0100000000053 +#define IQ_F_VALUE_PLUS_4_02 3372220 // hz = 4.0200000000053 +#define IQ_F_VALUE_PLUS_4_03 3380609 // hz = 4.0300000000053 +#define IQ_F_VALUE_PLUS_4_04 3388997 // hz = 4.0400000000053 +#define IQ_F_VALUE_PLUS_4_05 3397386 // hz = 4.0500000000053 +#define IQ_F_VALUE_PLUS_4_06 3405774 // hz = 4.0600000000053 +#define IQ_F_VALUE_PLUS_4_07 3414163 // hz = 4.0700000000053 +#define IQ_F_VALUE_PLUS_4_08 3422552 // hz = 4.0800000000053 +#define IQ_F_VALUE_PLUS_4_09 3430940 // hz = 4.0900000000053 +#define IQ_F_VALUE_PLUS_4_10 3439329 // hz = 4.1000000000053 +#define IQ_F_VALUE_PLUS_4_11 3447717 // hz = 4.1100000000053 +#define IQ_F_VALUE_PLUS_4_12 3456106 // hz = 4.1200000000053 +#define IQ_F_VALUE_PLUS_4_13 3464495 // hz = 4.1300000000053 +#define IQ_F_VALUE_PLUS_4_14 3472883 // hz = 4.1400000000053 +#define IQ_F_VALUE_PLUS_4_15 3481272 // hz = 4.1500000000053 +#define IQ_F_VALUE_PLUS_4_16 3489660 // hz = 4.1600000000053 +#define IQ_F_VALUE_PLUS_4_17 3498049 // hz = 4.1700000000053 +#define IQ_F_VALUE_PLUS_4_18 3506438 // hz = 4.1800000000053 +#define IQ_F_VALUE_PLUS_4_19 3514826 // hz = 4.1900000000053 +#define IQ_F_VALUE_PLUS_4_20 3523215 // hz = 4.2000000000053 +#define IQ_F_VALUE_PLUS_4_21 3531603 // hz = 4.2100000000054 +#define IQ_F_VALUE_PLUS_4_22 3539992 // hz = 4.2200000000053 +#define IQ_F_VALUE_PLUS_4_23 3548381 // hz = 4.2300000000053 +#define IQ_F_VALUE_PLUS_4_24 3556769 // hz = 4.2400000000054 +#define IQ_F_VALUE_PLUS_4_25 3565158 // hz = 4.2500000000054 +#define IQ_F_VALUE_PLUS_4_26 3573547 // hz = 4.2600000000054 +#define IQ_F_VALUE_PLUS_4_27 3581935 // hz = 4.2700000000054 +#define IQ_F_VALUE_PLUS_4_28 3590324 // hz = 4.2800000000054 +#define IQ_F_VALUE_PLUS_4_29 3598712 // hz = 4.2900000000054 +#define IQ_F_VALUE_PLUS_4_30 3607101 // hz = 4.3000000000054 +#define IQ_F_VALUE_PLUS_4_31 3615490 // hz = 4.3100000000054 +#define IQ_F_VALUE_PLUS_4_32 3623878 // hz = 4.3200000000054 +#define IQ_F_VALUE_PLUS_4_33 3632267 // hz = 4.3300000000054 +#define IQ_F_VALUE_PLUS_4_34 3640655 // hz = 4.3400000000054 +#define IQ_F_VALUE_PLUS_4_35 3649044 // hz = 4.3500000000054 +#define IQ_F_VALUE_PLUS_4_36 3657433 // hz = 4.3600000000054 +#define IQ_F_VALUE_PLUS_4_37 3665821 // hz = 4.3700000000054 +#define IQ_F_VALUE_PLUS_4_38 3674210 // hz = 4.3800000000054 +#define IQ_F_VALUE_PLUS_4_39 3682598 // hz = 4.3900000000054 +#define IQ_F_VALUE_PLUS_4_40 3690987 // hz = 4.4000000000054 +#define IQ_F_VALUE_PLUS_4_41 3699376 // hz = 4.4100000000054 +#define IQ_F_VALUE_PLUS_4_42 3707764 // hz = 4.4200000000054 +#define IQ_F_VALUE_PLUS_4_43 3716153 // hz = 4.4300000000054 +#define IQ_F_VALUE_PLUS_4_44 3724541 // hz = 4.4400000000054 +#define IQ_F_VALUE_PLUS_4_45 3732930 // hz = 4.4500000000054 +#define IQ_F_VALUE_PLUS_4_46 3741319 // hz = 4.4600000000054 +#define IQ_F_VALUE_PLUS_4_47 3749707 // hz = 4.4700000000054 +#define IQ_F_VALUE_PLUS_4_48 3758096 // hz = 4.4800000000054 +#define IQ_F_VALUE_PLUS_4_49 3766484 // hz = 4.4900000000054 +#define IQ_F_VALUE_PLUS_4_50 3774873 // hz = 4.5000000000054 +#define IQ_F_VALUE_PLUS_4_51 3783262 // hz = 4.5100000000054 +#define IQ_F_VALUE_PLUS_4_52 3791650 // hz = 4.5200000000054 +#define IQ_F_VALUE_PLUS_4_53 3800039 // hz = 4.5300000000054 +#define IQ_F_VALUE_PLUS_4_54 3808428 // hz = 4.5400000000054 +#define IQ_F_VALUE_PLUS_4_55 3816816 // hz = 4.5500000000054 +#define IQ_F_VALUE_PLUS_4_56 3825205 // hz = 4.5600000000054 +#define IQ_F_VALUE_PLUS_4_57 3833593 // hz = 4.5700000000054 +#define IQ_F_VALUE_PLUS_4_58 3841982 // hz = 4.5800000000054 +#define IQ_F_VALUE_PLUS_4_59 3850371 // hz = 4.5900000000054 +#define IQ_F_VALUE_PLUS_4_60 3858759 // hz = 4.6000000000054 +#define IQ_F_VALUE_PLUS_4_61 3867148 // hz = 4.6100000000054 +#define IQ_F_VALUE_PLUS_4_62 3875536 // hz = 4.6200000000054 +#define IQ_F_VALUE_PLUS_4_63 3883925 // hz = 4.6300000000054 +#define IQ_F_VALUE_PLUS_4_64 3892314 // hz = 4.6400000000054 +#define IQ_F_VALUE_PLUS_4_65 3900702 // hz = 4.6500000000054 +#define IQ_F_VALUE_PLUS_4_66 3909091 // hz = 4.6600000000054 +#define IQ_F_VALUE_PLUS_4_67 3917479 // hz = 4.6700000000054 +#define IQ_F_VALUE_PLUS_4_68 3925868 // hz = 4.6800000000054 +#define IQ_F_VALUE_PLUS_4_69 3934257 // hz = 4.6900000000054 +#define IQ_F_VALUE_PLUS_4_70 3942645 // hz = 4.7000000000054 +#define IQ_F_VALUE_PLUS_4_71 3951034 // hz = 4.7100000000054 +#define IQ_F_VALUE_PLUS_4_72 3959422 // hz = 4.7200000000054 +#define IQ_F_VALUE_PLUS_4_73 3967811 // hz = 4.7300000000054 +#define IQ_F_VALUE_PLUS_4_74 3976200 // hz = 4.7400000000054 +#define IQ_F_VALUE_PLUS_4_75 3984588 // hz = 4.7500000000054 +#define IQ_F_VALUE_PLUS_4_76 3992977 // hz = 4.7600000000054 +#define IQ_F_VALUE_PLUS_4_77 4001366 // hz = 4.7700000000054 +#define IQ_F_VALUE_PLUS_4_78 4009754 // hz = 4.7800000000054 +#define IQ_F_VALUE_PLUS_4_79 4018143 // hz = 4.7900000000054 +#define IQ_F_VALUE_PLUS_4_80 4026531 // hz = 4.8000000000054 +#define IQ_F_VALUE_PLUS_4_81 4034920 // hz = 4.8100000000054 +#define IQ_F_VALUE_PLUS_4_82 4043309 // hz = 4.8200000000054 +#define IQ_F_VALUE_PLUS_4_83 4051697 // hz = 4.8300000000054 +#define IQ_F_VALUE_PLUS_4_84 4060086 // hz = 4.8400000000054 +#define IQ_F_VALUE_PLUS_4_85 4068474 // hz = 4.8500000000055 +#define IQ_F_VALUE_PLUS_4_86 4076863 // hz = 4.8600000000054 +#define IQ_F_VALUE_PLUS_4_87 4085252 // hz = 4.8700000000054 +#define IQ_F_VALUE_PLUS_4_88 4093640 // hz = 4.8800000000055 +#define IQ_F_VALUE_PLUS_4_89 4102029 // hz = 4.8900000000055 +#define IQ_F_VALUE_PLUS_4_90 4110417 // hz = 4.9000000000055 +#define IQ_F_VALUE_PLUS_4_91 4118806 // hz = 4.9100000000055 +#define IQ_F_VALUE_PLUS_4_92 4127195 // hz = 4.9200000000055 +#define IQ_F_VALUE_PLUS_4_93 4135583 // hz = 4.9300000000055 +#define IQ_F_VALUE_PLUS_4_94 4143972 // hz = 4.9400000000055 +#define IQ_F_VALUE_PLUS_4_95 4152360 // hz = 4.9500000000055 +#define IQ_F_VALUE_PLUS_4_96 4160749 // hz = 4.9600000000055 +#define IQ_F_VALUE_PLUS_4_97 4169138 // hz = 4.9700000000055 +#define IQ_F_VALUE_PLUS_4_98 4177526 // hz = 4.9800000000055 +#define IQ_F_VALUE_PLUS_4_99 4185915 // hz = 4.9900000000055 +#define IQ_F_VALUE_PLUS_5_00 4194304 // hz = 5.0000000000055 +#define IQ_F_VALUE_PLUS_5_01 4202692 // hz = 5.0100000000055 +#define IQ_F_VALUE_PLUS_5_02 4211081 // hz = 5.0200000000055 +#define IQ_F_VALUE_PLUS_5_03 4219469 // hz = 5.0300000000055 +#define IQ_F_VALUE_PLUS_5_04 4227858 // hz = 5.0400000000055 +#define IQ_F_VALUE_PLUS_5_05 4236247 // hz = 5.0500000000055 +#define IQ_F_VALUE_PLUS_5_06 4244635 // hz = 5.0600000000055 +#define IQ_F_VALUE_PLUS_5_07 4253024 // hz = 5.0700000000055 +#define IQ_F_VALUE_PLUS_5_08 4261412 // hz = 5.0800000000055 +#define IQ_F_VALUE_PLUS_5_09 4269801 // hz = 5.0900000000055 +#define IQ_F_VALUE_PLUS_5_10 4278190 // hz = 5.1000000000055 +#define IQ_F_VALUE_PLUS_5_11 4286578 // hz = 5.1100000000055 +#define IQ_F_VALUE_PLUS_5_12 4294967 // hz = 5.1200000000055 +#define IQ_F_VALUE_PLUS_5_13 4303355 // hz = 5.1300000000055 +#define IQ_F_VALUE_PLUS_5_14 4311744 // hz = 5.1400000000055 +#define IQ_F_VALUE_PLUS_5_15 4320133 // hz = 5.1500000000055 +#define IQ_F_VALUE_PLUS_5_16 4328521 // hz = 5.1600000000055 +#define IQ_F_VALUE_PLUS_5_17 4336910 // hz = 5.1700000000055 +#define IQ_F_VALUE_PLUS_5_18 4345298 // hz = 5.1800000000055 +#define IQ_F_VALUE_PLUS_5_19 4353687 // hz = 5.1900000000055 +#define IQ_F_VALUE_PLUS_5_20 4362076 // hz = 5.2000000000055 +#define IQ_F_VALUE_PLUS_5_21 4370464 // hz = 5.2100000000055 +#define IQ_F_VALUE_PLUS_5_22 4378853 // hz = 5.2200000000055 +#define IQ_F_VALUE_PLUS_5_23 4387241 // hz = 5.2300000000055 +#define IQ_F_VALUE_PLUS_5_24 4395630 // hz = 5.2400000000055 +#define IQ_F_VALUE_PLUS_5_25 4404019 // hz = 5.2500000000055 +#define IQ_F_VALUE_PLUS_5_26 4412407 // hz = 5.2600000000055 +#define IQ_F_VALUE_PLUS_5_27 4420796 // hz = 5.2700000000055 +#define IQ_F_VALUE_PLUS_5_28 4429185 // hz = 5.2800000000055 +#define IQ_F_VALUE_PLUS_5_29 4437573 // hz = 5.2900000000055 +#define IQ_F_VALUE_PLUS_5_30 4445962 // hz = 5.3000000000055 +#define IQ_F_VALUE_PLUS_5_31 4454350 // hz = 5.3100000000055 +#define IQ_F_VALUE_PLUS_5_32 4462739 // hz = 5.3200000000055 +#define IQ_F_VALUE_PLUS_5_33 4471128 // hz = 5.3300000000055 +#define IQ_F_VALUE_PLUS_5_34 4479516 // hz = 5.3400000000055 +#define IQ_F_VALUE_PLUS_5_35 4487905 // hz = 5.3500000000055 +#define IQ_F_VALUE_PLUS_5_36 4496293 // hz = 5.3600000000055 +#define IQ_F_VALUE_PLUS_5_37 4504682 // hz = 5.3700000000055 +#define IQ_F_VALUE_PLUS_5_38 4513071 // hz = 5.3800000000055 +#define IQ_F_VALUE_PLUS_5_39 4521459 // hz = 5.3900000000055 +#define IQ_F_VALUE_PLUS_5_40 4529848 // hz = 5.4000000000055 +#define IQ_F_VALUE_PLUS_5_41 4538236 // hz = 5.4100000000055 +#define IQ_F_VALUE_PLUS_5_42 4546625 // hz = 5.4200000000055 +#define IQ_F_VALUE_PLUS_5_43 4555014 // hz = 5.4300000000055 +#define IQ_F_VALUE_PLUS_5_44 4563402 // hz = 5.4400000000055 +#define IQ_F_VALUE_PLUS_5_45 4571791 // hz = 5.4500000000055 +#define IQ_F_VALUE_PLUS_5_46 4580179 // hz = 5.4600000000055 +#define IQ_F_VALUE_PLUS_5_47 4588568 // hz = 5.4700000000055 +#define IQ_F_VALUE_PLUS_5_48 4596957 // hz = 5.4800000000055 +#define IQ_F_VALUE_PLUS_5_49 4605345 // hz = 5.4900000000056 +#define IQ_F_VALUE_PLUS_5_50 4613734 // hz = 5.5000000000055 +#define IQ_F_VALUE_PLUS_5_51 4622123 // hz = 5.5100000000055 +#define IQ_F_VALUE_PLUS_5_52 4630511 // hz = 5.5200000000056 +#define IQ_F_VALUE_PLUS_5_53 4638900 // hz = 5.5300000000056 +#define IQ_F_VALUE_PLUS_5_54 4647288 // hz = 5.5400000000056 +#define IQ_F_VALUE_PLUS_5_55 4655677 // hz = 5.5500000000056 +#define IQ_F_VALUE_PLUS_5_56 4664066 // hz = 5.5600000000056 +#define IQ_F_VALUE_PLUS_5_57 4672454 // hz = 5.5700000000056 +#define IQ_F_VALUE_PLUS_5_58 4680843 // hz = 5.5800000000056 +#define IQ_F_VALUE_PLUS_5_59 4689231 // hz = 5.5900000000056 +#define IQ_F_VALUE_PLUS_5_60 4697620 // hz = 5.6000000000056 +#define IQ_F_VALUE_PLUS_5_61 4706009 // hz = 5.6100000000056 +#define IQ_F_VALUE_PLUS_5_62 4714397 // hz = 5.6200000000056 +#define IQ_F_VALUE_PLUS_5_63 4722786 // hz = 5.6300000000056 +#define IQ_F_VALUE_PLUS_5_64 4731174 // hz = 5.6400000000056 +#define IQ_F_VALUE_PLUS_5_65 4739563 // hz = 5.6500000000056 +#define IQ_F_VALUE_PLUS_5_66 4747952 // hz = 5.6600000000056 +#define IQ_F_VALUE_PLUS_5_67 4756340 // hz = 5.6700000000056 +#define IQ_F_VALUE_PLUS_5_68 4764729 // hz = 5.6800000000056 +#define IQ_F_VALUE_PLUS_5_69 4773117 // hz = 5.6900000000056 +#define IQ_F_VALUE_PLUS_5_70 4781506 // hz = 5.7000000000056 +#define IQ_F_VALUE_PLUS_5_71 4789895 // hz = 5.7100000000056 +#define IQ_F_VALUE_PLUS_5_72 4798283 // hz = 5.7200000000056 +#define IQ_F_VALUE_PLUS_5_73 4806672 // hz = 5.7300000000056 +#define IQ_F_VALUE_PLUS_5_74 4815060 // hz = 5.7400000000056 +#define IQ_F_VALUE_PLUS_5_75 4823449 // hz = 5.7500000000056 +#define IQ_F_VALUE_PLUS_5_76 4831838 // hz = 5.7600000000056 +#define IQ_F_VALUE_PLUS_5_77 4840226 // hz = 5.7700000000056 +#define IQ_F_VALUE_PLUS_5_78 4848615 // hz = 5.7800000000056 +#define IQ_F_VALUE_PLUS_5_79 4857004 // hz = 5.7900000000056 +#define IQ_F_VALUE_PLUS_5_80 4865392 // hz = 5.8000000000056 +#define IQ_F_VALUE_PLUS_5_81 4873781 // hz = 5.8100000000056 +#define IQ_F_VALUE_PLUS_5_82 4882169 // hz = 5.8200000000056 +#define IQ_F_VALUE_PLUS_5_83 4890558 // hz = 5.8300000000056 +#define IQ_F_VALUE_PLUS_5_84 4898947 // hz = 5.8400000000056 +#define IQ_F_VALUE_PLUS_5_85 4907335 // hz = 5.8500000000056 +#define IQ_F_VALUE_PLUS_5_86 4915724 // hz = 5.8600000000056 +#define IQ_F_VALUE_PLUS_5_87 4924112 // hz = 5.8700000000056 +#define IQ_F_VALUE_PLUS_5_88 4932501 // hz = 5.8800000000056 +#define IQ_F_VALUE_PLUS_5_89 4940890 // hz = 5.8900000000056 +#define IQ_F_VALUE_PLUS_5_90 4949278 // hz = 5.9000000000056 +#define IQ_F_VALUE_PLUS_5_91 4957667 // hz = 5.9100000000056 +#define IQ_F_VALUE_PLUS_5_92 4966055 // hz = 5.9200000000056 +#define IQ_F_VALUE_PLUS_5_93 4974444 // hz = 5.9300000000056 +#define IQ_F_VALUE_PLUS_5_94 4982833 // hz = 5.9400000000056 +#define IQ_F_VALUE_PLUS_5_95 4991221 // hz = 5.9500000000056 +#define IQ_F_VALUE_PLUS_5_96 4999610 // hz = 5.9600000000056 +#define IQ_F_VALUE_PLUS_5_97 5007998 // hz = 5.9700000000056 +#define IQ_F_VALUE_PLUS_5_98 5016387 // hz = 5.9800000000056 +#define IQ_F_VALUE_PLUS_5_99 5024776 // hz = 5.9900000000056 +#define IQ_F_VALUE_PLUS_6_00 5033164 // hz = 6.0000000000056 +#define IQ_F_VALUE_PLUS_6_01 5041553 // hz = 6.0100000000056 +#define IQ_F_VALUE_PLUS_6_02 5049942 // hz = 6.0200000000056 +#define IQ_F_VALUE_PLUS_6_03 5058330 // hz = 6.0300000000056 +#define IQ_F_VALUE_PLUS_6_04 5066719 // hz = 6.0400000000056 +#define IQ_F_VALUE_PLUS_6_05 5075107 // hz = 6.0500000000056 +#define IQ_F_VALUE_PLUS_6_06 5083496 // hz = 6.0600000000056 +#define IQ_F_VALUE_PLUS_6_07 5091885 // hz = 6.0700000000056 +#define IQ_F_VALUE_PLUS_6_08 5100273 // hz = 6.0800000000056 +#define IQ_F_VALUE_PLUS_6_09 5108662 // hz = 6.0900000000056 +#define IQ_F_VALUE_PLUS_6_10 5117050 // hz = 6.1000000000056 +#define IQ_F_VALUE_PLUS_6_11 5125439 // hz = 6.1100000000056 +#define IQ_F_VALUE_PLUS_6_12 5133828 // hz = 6.1200000000056 +#define IQ_F_VALUE_PLUS_6_13 5142216 // hz = 6.1300000000057 +#define IQ_F_VALUE_PLUS_6_14 5150605 // hz = 6.1400000000056 +#define IQ_F_VALUE_PLUS_6_15 5158993 // hz = 6.1500000000056 +#define IQ_F_VALUE_PLUS_6_16 5167382 // hz = 6.1600000000057 +#define IQ_F_VALUE_PLUS_6_17 5175771 // hz = 6.1700000000057 +#define IQ_F_VALUE_PLUS_6_18 5184159 // hz = 6.1800000000057 +#define IQ_F_VALUE_PLUS_6_19 5192548 // hz = 6.1900000000057 +#define IQ_F_VALUE_PLUS_6_20 5200936 // hz = 6.2000000000057 +#define IQ_F_VALUE_PLUS_6_21 5209325 // hz = 6.2100000000057 +#define IQ_F_VALUE_PLUS_6_22 5217714 // hz = 6.2200000000057 +#define IQ_F_VALUE_PLUS_6_23 5226102 // hz = 6.2300000000057 +#define IQ_F_VALUE_PLUS_6_24 5234491 // hz = 6.2400000000057 +#define IQ_F_VALUE_PLUS_6_25 5242880 // hz = 6.2500000000057 +#define IQ_F_VALUE_PLUS_6_26 5251268 // hz = 6.2600000000057 +#define IQ_F_VALUE_PLUS_6_27 5259657 // hz = 6.2700000000057 +#define IQ_F_VALUE_PLUS_6_28 5268045 // hz = 6.2800000000057 +#define IQ_F_VALUE_PLUS_6_29 5276434 // hz = 6.2900000000057 +#define IQ_F_VALUE_PLUS_6_30 5284823 // hz = 6.3000000000057 +#define IQ_F_VALUE_PLUS_6_31 5293211 // hz = 6.3100000000057 +#define IQ_F_VALUE_PLUS_6_32 5301600 // hz = 6.3200000000057 +#define IQ_F_VALUE_PLUS_6_33 5309988 // hz = 6.3300000000057 +#define IQ_F_VALUE_PLUS_6_34 5318377 // hz = 6.3400000000057 +#define IQ_F_VALUE_PLUS_6_35 5326766 // hz = 6.3500000000057 +#define IQ_F_VALUE_PLUS_6_36 5335154 // hz = 6.3600000000057 +#define IQ_F_VALUE_PLUS_6_37 5343543 // hz = 6.3700000000057 +#define IQ_F_VALUE_PLUS_6_38 5351931 // hz = 6.3800000000057 +#define IQ_F_VALUE_PLUS_6_39 5360320 // hz = 6.3900000000057 +#define IQ_F_VALUE_PLUS_6_40 5368709 // hz = 6.4000000000057 +#define IQ_F_VALUE_PLUS_6_41 5377097 // hz = 6.4100000000057 +#define IQ_F_VALUE_PLUS_6_42 5385486 // hz = 6.4200000000057 +#define IQ_F_VALUE_PLUS_6_43 5393874 // hz = 6.4300000000057 +#define IQ_F_VALUE_PLUS_6_44 5402263 // hz = 6.4400000000057 +#define IQ_F_VALUE_PLUS_6_45 5410652 // hz = 6.4500000000057 +#define IQ_F_VALUE_PLUS_6_46 5419040 // hz = 6.4600000000057 +#define IQ_F_VALUE_PLUS_6_47 5427429 // hz = 6.4700000000057 +#define IQ_F_VALUE_PLUS_6_48 5435817 // hz = 6.4800000000057 +#define IQ_F_VALUE_PLUS_6_49 5444206 // hz = 6.4900000000057 +#define IQ_F_VALUE_PLUS_6_50 5452595 // hz = 6.5000000000057 +#define IQ_F_VALUE_PLUS_6_51 5460983 // hz = 6.5100000000057 +#define IQ_F_VALUE_PLUS_6_52 5469372 // hz = 6.5200000000057 +#define IQ_F_VALUE_PLUS_6_53 5477761 // hz = 6.5300000000057 +#define IQ_F_VALUE_PLUS_6_54 5486149 // hz = 6.5400000000057 +#define IQ_F_VALUE_PLUS_6_55 5494538 // hz = 6.5500000000057 +#define IQ_F_VALUE_PLUS_6_56 5502926 // hz = 6.5600000000057 +#define IQ_F_VALUE_PLUS_6_57 5511315 // hz = 6.5700000000057 +#define IQ_F_VALUE_PLUS_6_58 5519704 // hz = 6.5800000000057 +#define IQ_F_VALUE_PLUS_6_59 5528092 // hz = 6.5900000000057 +#define IQ_F_VALUE_PLUS_6_60 5536481 // hz = 6.6000000000057 +#define IQ_F_VALUE_PLUS_6_61 5544869 // hz = 6.6100000000057 +#define IQ_F_VALUE_PLUS_6_62 5553258 // hz = 6.6200000000057 +#define IQ_F_VALUE_PLUS_6_63 5561647 // hz = 6.6300000000057 +#define IQ_F_VALUE_PLUS_6_64 5570035 // hz = 6.6400000000057 +#define IQ_F_VALUE_PLUS_6_65 5578424 // hz = 6.6500000000057 +#define IQ_F_VALUE_PLUS_6_66 5586812 // hz = 6.6600000000057 +#define IQ_F_VALUE_PLUS_6_67 5595201 // hz = 6.6700000000057 +#define IQ_F_VALUE_PLUS_6_68 5603590 // hz = 6.6800000000057 +#define IQ_F_VALUE_PLUS_6_69 5611978 // hz = 6.6900000000057 +#define IQ_F_VALUE_PLUS_6_70 5620367 // hz = 6.7000000000057 +#define IQ_F_VALUE_PLUS_6_71 5628755 // hz = 6.7100000000057 +#define IQ_F_VALUE_PLUS_6_72 5637144 // hz = 6.7200000000057 +#define IQ_F_VALUE_PLUS_6_73 5645533 // hz = 6.7300000000057 +#define IQ_F_VALUE_PLUS_6_74 5653921 // hz = 6.7400000000057 +#define IQ_F_VALUE_PLUS_6_75 5662310 // hz = 6.7500000000057 +#define IQ_F_VALUE_PLUS_6_76 5670699 // hz = 6.7600000000057 +#define IQ_F_VALUE_PLUS_6_77 5679087 // hz = 6.7700000000058 +#define IQ_F_VALUE_PLUS_6_78 5687476 // hz = 6.7800000000057 +#define IQ_F_VALUE_PLUS_6_79 5695864 // hz = 6.7900000000057 +#define IQ_F_VALUE_PLUS_6_80 5704253 // hz = 6.8000000000058 +#define IQ_F_VALUE_PLUS_6_81 5712642 // hz = 6.8100000000058 +#define IQ_F_VALUE_PLUS_6_82 5721030 // hz = 6.8200000000058 +#define IQ_F_VALUE_PLUS_6_83 5729419 // hz = 6.8300000000058 +#define IQ_F_VALUE_PLUS_6_84 5737807 // hz = 6.8400000000058 +#define IQ_F_VALUE_PLUS_6_85 5746196 // hz = 6.8500000000058 +#define IQ_F_VALUE_PLUS_6_86 5754585 // hz = 6.8600000000058 +#define IQ_F_VALUE_PLUS_6_87 5762973 // hz = 6.8700000000058 +#define IQ_F_VALUE_PLUS_6_88 5771362 // hz = 6.8800000000058 +#define IQ_F_VALUE_PLUS_6_89 5779750 // hz = 6.8900000000058 +#define IQ_F_VALUE_PLUS_6_90 5788139 // hz = 6.9000000000058 +#define IQ_F_VALUE_PLUS_6_91 5796528 // hz = 6.9100000000058 +#define IQ_F_VALUE_PLUS_6_92 5804916 // hz = 6.9200000000058 +#define IQ_F_VALUE_PLUS_6_93 5813305 // hz = 6.9300000000058 +#define IQ_F_VALUE_PLUS_6_94 5821693 // hz = 6.9400000000058 +#define IQ_F_VALUE_PLUS_6_95 5830082 // hz = 6.9500000000058 +#define IQ_F_VALUE_PLUS_6_96 5838471 // hz = 6.9600000000058 +#define IQ_F_VALUE_PLUS_6_97 5846859 // hz = 6.9700000000058 +#define IQ_F_VALUE_PLUS_6_98 5855248 // hz = 6.9800000000058 +#define IQ_F_VALUE_PLUS_6_99 5863636 // hz = 6.9900000000058 +#define IQ_F_VALUE_PLUS_7_00 5872025 // hz = 7.0000000000058 +#define IQ_F_VALUE_PLUS_7_01 5880414 // hz = 7.0100000000058 +#define IQ_F_VALUE_PLUS_7_02 5888802 // hz = 7.0200000000058 +#define IQ_F_VALUE_PLUS_7_03 5897191 // hz = 7.0300000000058 +#define IQ_F_VALUE_PLUS_7_04 5905580 // hz = 7.0400000000058 +#define IQ_F_VALUE_PLUS_7_05 5913968 // hz = 7.0500000000058 +#define IQ_F_VALUE_PLUS_7_06 5922357 // hz = 7.0600000000058 +#define IQ_F_VALUE_PLUS_7_07 5930745 // hz = 7.0700000000058 +#define IQ_F_VALUE_PLUS_7_08 5939134 // hz = 7.0800000000058 +#define IQ_F_VALUE_PLUS_7_09 5947523 // hz = 7.0900000000058 +#define IQ_F_VALUE_PLUS_7_10 5955911 // hz = 7.1000000000058 +#define IQ_F_VALUE_PLUS_7_11 5964300 // hz = 7.1100000000058 +#define IQ_F_VALUE_PLUS_7_12 5972688 // hz = 7.1200000000058 +#define IQ_F_VALUE_PLUS_7_13 5981077 // hz = 7.1300000000058 +#define IQ_F_VALUE_PLUS_7_14 5989466 // hz = 7.1400000000058 +#define IQ_F_VALUE_PLUS_7_15 5997854 // hz = 7.1500000000058 +#define IQ_F_VALUE_PLUS_7_16 6006243 // hz = 7.1600000000058 +#define IQ_F_VALUE_PLUS_7_17 6014631 // hz = 7.1700000000058 +#define IQ_F_VALUE_PLUS_7_18 6023020 // hz = 7.1800000000058 +#define IQ_F_VALUE_PLUS_7_19 6031409 // hz = 7.1900000000058 +#define IQ_F_VALUE_PLUS_7_20 6039797 // hz = 7.2000000000058 +#define IQ_F_VALUE_PLUS_7_21 6048186 // hz = 7.2100000000058 +#define IQ_F_VALUE_PLUS_7_22 6056574 // hz = 7.2200000000058 +#define IQ_F_VALUE_PLUS_7_23 6064963 // hz = 7.2300000000058 +#define IQ_F_VALUE_PLUS_7_24 6073352 // hz = 7.2400000000058 +#define IQ_F_VALUE_PLUS_7_25 6081740 // hz = 7.2500000000058 +#define IQ_F_VALUE_PLUS_7_26 6090129 // hz = 7.2600000000058 +#define IQ_F_VALUE_PLUS_7_27 6098518 // hz = 7.2700000000058 +#define IQ_F_VALUE_PLUS_7_28 6106906 // hz = 7.2800000000058 +#define IQ_F_VALUE_PLUS_7_29 6115295 // hz = 7.2900000000058 +#define IQ_F_VALUE_PLUS_7_30 6123683 // hz = 7.3000000000058 +#define IQ_F_VALUE_PLUS_7_31 6132072 // hz = 7.3100000000058 +#define IQ_F_VALUE_PLUS_7_32 6140461 // hz = 7.3200000000058 +#define IQ_F_VALUE_PLUS_7_33 6148849 // hz = 7.3300000000058 +#define IQ_F_VALUE_PLUS_7_34 6157238 // hz = 7.3400000000058 +#define IQ_F_VALUE_PLUS_7_35 6165626 // hz = 7.3500000000058 +#define IQ_F_VALUE_PLUS_7_36 6174015 // hz = 7.3600000000058 +#define IQ_F_VALUE_PLUS_7_37 6182404 // hz = 7.3700000000058 +#define IQ_F_VALUE_PLUS_7_38 6190792 // hz = 7.3800000000058 +#define IQ_F_VALUE_PLUS_7_39 6199181 // hz = 7.3900000000058 +#define IQ_F_VALUE_PLUS_7_40 6207569 // hz = 7.4000000000058 +#define IQ_F_VALUE_PLUS_7_41 6215958 // hz = 7.4100000000059 +#define IQ_F_VALUE_PLUS_7_42 6224347 // hz = 7.4200000000058 +#define IQ_F_VALUE_PLUS_7_43 6232735 // hz = 7.4300000000058 +#define IQ_F_VALUE_PLUS_7_44 6241124 // hz = 7.4400000000059 +#define IQ_F_VALUE_PLUS_7_45 6249512 // hz = 7.4500000000059 +#define IQ_F_VALUE_PLUS_7_46 6257901 // hz = 7.4600000000059 +#define IQ_F_VALUE_PLUS_7_47 6266290 // hz = 7.4700000000059 +#define IQ_F_VALUE_PLUS_7_48 6274678 // hz = 7.4800000000059 +#define IQ_F_VALUE_PLUS_7_49 6283067 // hz = 7.4900000000059 +#define IQ_F_VALUE_PLUS_7_50 6291456 // hz = 7.5000000000059 +#define IQ_F_VALUE_PLUS_7_51 6299844 // hz = 7.5100000000059 +#define IQ_F_VALUE_PLUS_7_52 6308233 // hz = 7.5200000000059 +#define IQ_F_VALUE_PLUS_7_53 6316621 // hz = 7.5300000000059 +#define IQ_F_VALUE_PLUS_7_54 6325010 // hz = 7.5400000000059 +#define IQ_F_VALUE_PLUS_7_55 6333399 // hz = 7.5500000000059 +#define IQ_F_VALUE_PLUS_7_56 6341787 // hz = 7.5600000000059 +#define IQ_F_VALUE_PLUS_7_57 6350176 // hz = 7.5700000000059 +#define IQ_F_VALUE_PLUS_7_58 6358564 // hz = 7.5800000000059 +#define IQ_F_VALUE_PLUS_7_59 6366953 // hz = 7.5900000000059 +#define IQ_F_VALUE_PLUS_7_60 6375342 // hz = 7.6000000000059 +#define IQ_F_VALUE_PLUS_7_61 6383730 // hz = 7.6100000000059 +#define IQ_F_VALUE_PLUS_7_62 6392119 // hz = 7.6200000000059 +#define IQ_F_VALUE_PLUS_7_63 6400507 // hz = 7.6300000000059 +#define IQ_F_VALUE_PLUS_7_64 6408896 // hz = 7.6400000000059 +#define IQ_F_VALUE_PLUS_7_65 6417285 // hz = 7.6500000000059 +#define IQ_F_VALUE_PLUS_7_66 6425673 // hz = 7.6600000000059 +#define IQ_F_VALUE_PLUS_7_67 6434062 // hz = 7.6700000000059 +#define IQ_F_VALUE_PLUS_7_68 6442450 // hz = 7.6800000000059 +#define IQ_F_VALUE_PLUS_7_69 6450839 // hz = 7.6900000000059 +#define IQ_F_VALUE_PLUS_7_70 6459228 // hz = 7.7000000000059 +#define IQ_F_VALUE_PLUS_7_71 6467616 // hz = 7.7100000000059 +#define IQ_F_VALUE_PLUS_7_72 6476005 // hz = 7.7200000000059 +#define IQ_F_VALUE_PLUS_7_73 6484393 // hz = 7.7300000000059 +#define IQ_F_VALUE_PLUS_7_74 6492782 // hz = 7.7400000000059 +#define IQ_F_VALUE_PLUS_7_75 6501171 // hz = 7.7500000000059 +#define IQ_F_VALUE_PLUS_7_76 6509559 // hz = 7.7600000000059 +#define IQ_F_VALUE_PLUS_7_77 6517948 // hz = 7.7700000000059 +#define IQ_F_VALUE_PLUS_7_78 6526337 // hz = 7.7800000000059 +#define IQ_F_VALUE_PLUS_7_79 6534725 // hz = 7.7900000000059 +#define IQ_F_VALUE_PLUS_7_80 6543114 // hz = 7.8000000000059 +#define IQ_F_VALUE_PLUS_7_81 6551502 // hz = 7.8100000000059 +#define IQ_F_VALUE_PLUS_7_82 6559891 // hz = 7.8200000000059 +#define IQ_F_VALUE_PLUS_7_83 6568280 // hz = 7.8300000000059 +#define IQ_F_VALUE_PLUS_7_84 6576668 // hz = 7.8400000000059 +#define IQ_F_VALUE_PLUS_7_85 6585057 // hz = 7.8500000000059 +#define IQ_F_VALUE_PLUS_7_86 6593445 // hz = 7.8600000000059 +#define IQ_F_VALUE_PLUS_7_87 6601834 // hz = 7.8700000000059 +#define IQ_F_VALUE_PLUS_7_88 6610223 // hz = 7.8800000000059 +#define IQ_F_VALUE_PLUS_7_89 6618611 // hz = 7.8900000000059 +#define IQ_F_VALUE_PLUS_7_90 6627000 // hz = 7.9000000000059 +#define IQ_F_VALUE_PLUS_7_91 6635388 // hz = 7.9100000000059 +#define IQ_F_VALUE_PLUS_7_92 6643777 // hz = 7.9200000000059 +#define IQ_F_VALUE_PLUS_7_93 6652166 // hz = 7.9300000000059 +#define IQ_F_VALUE_PLUS_7_94 6660554 // hz = 7.9400000000059 +#define IQ_F_VALUE_PLUS_7_95 6668943 // hz = 7.9500000000059 +#define IQ_F_VALUE_PLUS_7_96 6677331 // hz = 7.9600000000059 +#define IQ_F_VALUE_PLUS_7_97 6685720 // hz = 7.9700000000059 +#define IQ_F_VALUE_PLUS_7_98 6694109 // hz = 7.9800000000059 +#define IQ_F_VALUE_PLUS_7_99 6702497 // hz = 7.9900000000059 +#define IQ_F_VALUE_PLUS_8_00 6710886 // hz = 8.0000000000059 +#define IQ_F_VALUE_PLUS_8_01 6719275 // hz = 8.0100000000059 +#define IQ_F_VALUE_PLUS_8_02 6727663 // hz = 8.0200000000059 +#define IQ_F_VALUE_PLUS_8_03 6736052 // hz = 8.0300000000059 +#define IQ_F_VALUE_PLUS_8_04 6744440 // hz = 8.0400000000059 +#define IQ_F_VALUE_PLUS_8_05 6752829 // hz = 8.050000000006 +#define IQ_F_VALUE_PLUS_8_06 6761218 // hz = 8.0600000000059 +#define IQ_F_VALUE_PLUS_8_07 6769606 // hz = 8.0700000000059 +#define IQ_F_VALUE_PLUS_8_08 6777995 // hz = 8.080000000006 +#define IQ_F_VALUE_PLUS_8_09 6786383 // hz = 8.090000000006 +#define IQ_F_VALUE_PLUS_8_10 6794772 // hz = 8.100000000006 +#define IQ_F_VALUE_PLUS_8_11 6803161 // hz = 8.110000000006 +#define IQ_F_VALUE_PLUS_8_12 6811549 // hz = 8.120000000006 +#define IQ_F_VALUE_PLUS_8_13 6819938 // hz = 8.130000000006 +#define IQ_F_VALUE_PLUS_8_14 6828326 // hz = 8.140000000006 +#define IQ_F_VALUE_PLUS_8_15 6836715 // hz = 8.150000000006 +#define IQ_F_VALUE_PLUS_8_16 6845104 // hz = 8.160000000006 +#define IQ_F_VALUE_PLUS_8_17 6853492 // hz = 8.170000000006 +#define IQ_F_VALUE_PLUS_8_18 6861881 // hz = 8.180000000006 +#define IQ_F_VALUE_PLUS_8_19 6870269 // hz = 8.190000000006 +#define IQ_F_VALUE_PLUS_8_20 6878658 // hz = 8.200000000006 +#define IQ_F_VALUE_PLUS_8_21 6887047 // hz = 8.210000000006 +#define IQ_F_VALUE_PLUS_8_22 6895435 // hz = 8.220000000006 +#define IQ_F_VALUE_PLUS_8_23 6903824 // hz = 8.230000000006 +#define IQ_F_VALUE_PLUS_8_24 6912212 // hz = 8.240000000006 +#define IQ_F_VALUE_PLUS_8_25 6920601 // hz = 8.250000000006 +#define IQ_F_VALUE_PLUS_8_26 6928990 // hz = 8.260000000006 +#define IQ_F_VALUE_PLUS_8_27 6937378 // hz = 8.270000000006 +#define IQ_F_VALUE_PLUS_8_28 6945767 // hz = 8.280000000006 +#define IQ_F_VALUE_PLUS_8_29 6954156 // hz = 8.290000000006 +#define IQ_F_VALUE_PLUS_8_30 6962544 // hz = 8.300000000006 +#define IQ_F_VALUE_PLUS_8_31 6970933 // hz = 8.310000000006 +#define IQ_F_VALUE_PLUS_8_32 6979321 // hz = 8.320000000006 +#define IQ_F_VALUE_PLUS_8_33 6987710 // hz = 8.330000000006 +#define IQ_F_VALUE_PLUS_8_34 6996099 // hz = 8.340000000006 +#define IQ_F_VALUE_PLUS_8_35 7004487 // hz = 8.350000000006 +#define IQ_F_VALUE_PLUS_8_36 7012876 // hz = 8.360000000006 +#define IQ_F_VALUE_PLUS_8_37 7021264 // hz = 8.370000000006 +#define IQ_F_VALUE_PLUS_8_38 7029653 // hz = 8.380000000006 +#define IQ_F_VALUE_PLUS_8_39 7038042 // hz = 8.390000000006 +#define IQ_F_VALUE_PLUS_8_40 7046430 // hz = 8.400000000006 +#define IQ_F_VALUE_PLUS_8_41 7054819 // hz = 8.410000000006 +#define IQ_F_VALUE_PLUS_8_42 7063207 // hz = 8.420000000006 +#define IQ_F_VALUE_PLUS_8_43 7071596 // hz = 8.430000000006 +#define IQ_F_VALUE_PLUS_8_44 7079985 // hz = 8.440000000006 +#define IQ_F_VALUE_PLUS_8_45 7088373 // hz = 8.450000000006 +#define IQ_F_VALUE_PLUS_8_46 7096762 // hz = 8.460000000006 +#define IQ_F_VALUE_PLUS_8_47 7105150 // hz = 8.470000000006 +#define IQ_F_VALUE_PLUS_8_48 7113539 // hz = 8.480000000006 +#define IQ_F_VALUE_PLUS_8_49 7121928 // hz = 8.490000000006 +#define IQ_F_VALUE_PLUS_8_50 7130316 // hz = 8.500000000006 +#define IQ_F_VALUE_PLUS_8_51 7138705 // hz = 8.510000000006 +#define IQ_F_VALUE_PLUS_8_52 7147094 // hz = 8.520000000006 +#define IQ_F_VALUE_PLUS_8_53 7155482 // hz = 8.530000000006 +#define IQ_F_VALUE_PLUS_8_54 7163871 // hz = 8.540000000006 +#define IQ_F_VALUE_PLUS_8_55 7172259 // hz = 8.550000000006 +#define IQ_F_VALUE_PLUS_8_56 7180648 // hz = 8.560000000006 +#define IQ_F_VALUE_PLUS_8_57 7189037 // hz = 8.570000000006 +#define IQ_F_VALUE_PLUS_8_58 7197425 // hz = 8.580000000006 +#define IQ_F_VALUE_PLUS_8_59 7205814 // hz = 8.590000000006 +#define IQ_F_VALUE_PLUS_8_60 7214202 // hz = 8.600000000006 +#define IQ_F_VALUE_PLUS_8_61 7222591 // hz = 8.610000000006 +#define IQ_F_VALUE_PLUS_8_62 7230980 // hz = 8.620000000006 +#define IQ_F_VALUE_PLUS_8_63 7239368 // hz = 8.630000000006 +#define IQ_F_VALUE_PLUS_8_64 7247757 // hz = 8.640000000006 +#define IQ_F_VALUE_PLUS_8_65 7256145 // hz = 8.650000000006 +#define IQ_F_VALUE_PLUS_8_66 7264534 // hz = 8.660000000006 +#define IQ_F_VALUE_PLUS_8_67 7272923 // hz = 8.670000000006 +#define IQ_F_VALUE_PLUS_8_68 7281311 // hz = 8.680000000006 +#define IQ_F_VALUE_PLUS_8_69 7289700 // hz = 8.6900000000061 +#define IQ_F_VALUE_PLUS_8_70 7298088 // hz = 8.700000000006 +#define IQ_F_VALUE_PLUS_8_71 7306477 // hz = 8.710000000006 +#define IQ_F_VALUE_PLUS_8_72 7314866 // hz = 8.7200000000061 +#define IQ_F_VALUE_PLUS_8_73 7323254 // hz = 8.7300000000061 +#define IQ_F_VALUE_PLUS_8_74 7331643 // hz = 8.7400000000061 +#define IQ_F_VALUE_PLUS_8_75 7340032 // hz = 8.7500000000061 +#define IQ_F_VALUE_PLUS_8_76 7348420 // hz = 8.7600000000061 +#define IQ_F_VALUE_PLUS_8_77 7356809 // hz = 8.7700000000061 +#define IQ_F_VALUE_PLUS_8_78 7365197 // hz = 8.7800000000061 +#define IQ_F_VALUE_PLUS_8_79 7373586 // hz = 8.7900000000061 +#define IQ_F_VALUE_PLUS_8_80 7381975 // hz = 8.8000000000061 +#define IQ_F_VALUE_PLUS_8_81 7390363 // hz = 8.8100000000061 +#define IQ_F_VALUE_PLUS_8_82 7398752 // hz = 8.8200000000061 +#define IQ_F_VALUE_PLUS_8_83 7407140 // hz = 8.8300000000061 +#define IQ_F_VALUE_PLUS_8_84 7415529 // hz = 8.8400000000061 +#define IQ_F_VALUE_PLUS_8_85 7423918 // hz = 8.8500000000061 +#define IQ_F_VALUE_PLUS_8_86 7432306 // hz = 8.8600000000061 +#define IQ_F_VALUE_PLUS_8_87 7440695 // hz = 8.8700000000061 +#define IQ_F_VALUE_PLUS_8_88 7449083 // hz = 8.8800000000061 +#define IQ_F_VALUE_PLUS_8_89 7457472 // hz = 8.8900000000061 +#define IQ_F_VALUE_PLUS_8_90 7465861 // hz = 8.9000000000061 +#define IQ_F_VALUE_PLUS_8_91 7474249 // hz = 8.9100000000061 +#define IQ_F_VALUE_PLUS_8_92 7482638 // hz = 8.9200000000061 +#define IQ_F_VALUE_PLUS_8_93 7491026 // hz = 8.9300000000061 +#define IQ_F_VALUE_PLUS_8_94 7499415 // hz = 8.9400000000061 +#define IQ_F_VALUE_PLUS_8_95 7507804 // hz = 8.9500000000061 +#define IQ_F_VALUE_PLUS_8_96 7516192 // hz = 8.9600000000061 +#define IQ_F_VALUE_PLUS_8_97 7524581 // hz = 8.9700000000061 +#define IQ_F_VALUE_PLUS_8_98 7532969 // hz = 8.9800000000061 +#define IQ_F_VALUE_PLUS_8_99 7541358 // hz = 8.9900000000061 +#define IQ_F_VALUE_PLUS_9_00 7549747 // hz = 9.0000000000061 +#define IQ_F_VALUE_PLUS_9_01 7558135 // hz = 9.0100000000061 +#define IQ_F_VALUE_PLUS_9_02 7566524 // hz = 9.0200000000061 +#define IQ_F_VALUE_PLUS_9_03 7574913 // hz = 9.0300000000061 +#define IQ_F_VALUE_PLUS_9_04 7583301 // hz = 9.0400000000061 +#define IQ_F_VALUE_PLUS_9_05 7591690 // hz = 9.0500000000061 +#define IQ_F_VALUE_PLUS_9_06 7600078 // hz = 9.0600000000061 +#define IQ_F_VALUE_PLUS_9_07 7608467 // hz = 9.0700000000061 +#define IQ_F_VALUE_PLUS_9_08 7616856 // hz = 9.0800000000061 +#define IQ_F_VALUE_PLUS_9_09 7625244 // hz = 9.0900000000061 +#define IQ_F_VALUE_PLUS_9_10 7633633 // hz = 9.1000000000061 +#define IQ_F_VALUE_PLUS_9_11 7642021 // hz = 9.1100000000061 +#define IQ_F_VALUE_PLUS_9_12 7650410 // hz = 9.1200000000061 +#define IQ_F_VALUE_PLUS_9_13 7658799 // hz = 9.1300000000061 +#define IQ_F_VALUE_PLUS_9_14 7667187 // hz = 9.1400000000061 +#define IQ_F_VALUE_PLUS_9_15 7675576 // hz = 9.1500000000061 +#define IQ_F_VALUE_PLUS_9_16 7683964 // hz = 9.1600000000061 +#define IQ_F_VALUE_PLUS_9_17 7692353 // hz = 9.1700000000061 +#define IQ_F_VALUE_PLUS_9_18 7700742 // hz = 9.1800000000061 +#define IQ_F_VALUE_PLUS_9_19 7709130 // hz = 9.1900000000061 +#define IQ_F_VALUE_PLUS_9_20 7717519 // hz = 9.2000000000061 +#define IQ_F_VALUE_PLUS_9_21 7725907 // hz = 9.2100000000061 +#define IQ_F_VALUE_PLUS_9_22 7734296 // hz = 9.2200000000061 +#define IQ_F_VALUE_PLUS_9_23 7742685 // hz = 9.2300000000061 +#define IQ_F_VALUE_PLUS_9_24 7751073 // hz = 9.2400000000061 +#define IQ_F_VALUE_PLUS_9_25 7759462 // hz = 9.2500000000061 +#define IQ_F_VALUE_PLUS_9_26 7767851 // hz = 9.2600000000061 +#define IQ_F_VALUE_PLUS_9_27 7776239 // hz = 9.2700000000061 +#define IQ_F_VALUE_PLUS_9_28 7784628 // hz = 9.2800000000061 +#define IQ_F_VALUE_PLUS_9_29 7793016 // hz = 9.2900000000061 +#define IQ_F_VALUE_PLUS_9_30 7801405 // hz = 9.3000000000061 +#define IQ_F_VALUE_PLUS_9_31 7809794 // hz = 9.3100000000061 +#define IQ_F_VALUE_PLUS_9_32 7818182 // hz = 9.3200000000061 +#define IQ_F_VALUE_PLUS_9_33 7826571 // hz = 9.3300000000062 +#define IQ_F_VALUE_PLUS_9_34 7834959 // hz = 9.3400000000061 +#define IQ_F_VALUE_PLUS_9_35 7843348 // hz = 9.3500000000061 +#define IQ_F_VALUE_PLUS_9_36 7851737 // hz = 9.3600000000062 +#define IQ_F_VALUE_PLUS_9_37 7860125 // hz = 9.3700000000062 +#define IQ_F_VALUE_PLUS_9_38 7868514 // hz = 9.3800000000062 +#define IQ_F_VALUE_PLUS_9_39 7876902 // hz = 9.3900000000062 +#define IQ_F_VALUE_PLUS_9_40 7885291 // hz = 9.4000000000062 +#define IQ_F_VALUE_PLUS_9_41 7893680 // hz = 9.4100000000062 +#define IQ_F_VALUE_PLUS_9_42 7902068 // hz = 9.4200000000062 +#define IQ_F_VALUE_PLUS_9_43 7910457 // hz = 9.4300000000062 +#define IQ_F_VALUE_PLUS_9_44 7918845 // hz = 9.4400000000062 +#define IQ_F_VALUE_PLUS_9_45 7927234 // hz = 9.4500000000062 +#define IQ_F_VALUE_PLUS_9_46 7935623 // hz = 9.4600000000062 +#define IQ_F_VALUE_PLUS_9_47 7944011 // hz = 9.4700000000062 +#define IQ_F_VALUE_PLUS_9_48 7952400 // hz = 9.4800000000062 +#define IQ_F_VALUE_PLUS_9_49 7960788 // hz = 9.4900000000062 +#define IQ_F_VALUE_PLUS_9_50 7969177 // hz = 9.5000000000062 +#define IQ_F_VALUE_PLUS_9_51 7977566 // hz = 9.5100000000062 +#define IQ_F_VALUE_PLUS_9_52 7985954 // hz = 9.5200000000062 +#define IQ_F_VALUE_PLUS_9_53 7994343 // hz = 9.5300000000062 +#define IQ_F_VALUE_PLUS_9_54 8002732 // hz = 9.5400000000062 +#define IQ_F_VALUE_PLUS_9_55 8011120 // hz = 9.5500000000062 +#define IQ_F_VALUE_PLUS_9_56 8019509 // hz = 9.5600000000062 +#define IQ_F_VALUE_PLUS_9_57 8027897 // hz = 9.5700000000062 +#define IQ_F_VALUE_PLUS_9_58 8036286 // hz = 9.5800000000062 +#define IQ_F_VALUE_PLUS_9_59 8044675 // hz = 9.5900000000062 +#define IQ_F_VALUE_PLUS_9_60 8053063 // hz = 9.6000000000062 +#define IQ_F_VALUE_PLUS_9_61 8061452 // hz = 9.6100000000062 +#define IQ_F_VALUE_PLUS_9_62 8069840 // hz = 9.6200000000062 +#define IQ_F_VALUE_PLUS_9_63 8078229 // hz = 9.6300000000062 +#define IQ_F_VALUE_PLUS_9_64 8086618 // hz = 9.6400000000062 +#define IQ_F_VALUE_PLUS_9_65 8095006 // hz = 9.6500000000062 +#define IQ_F_VALUE_PLUS_9_66 8103395 // hz = 9.6600000000062 +#define IQ_F_VALUE_PLUS_9_67 8111783 // hz = 9.6700000000062 +#define IQ_F_VALUE_PLUS_9_68 8120172 // hz = 9.6800000000062 +#define IQ_F_VALUE_PLUS_9_69 8128561 // hz = 9.6900000000062 +#define IQ_F_VALUE_PLUS_9_70 8136949 // hz = 9.7000000000062 +#define IQ_F_VALUE_PLUS_9_71 8145338 // hz = 9.7100000000062 +#define IQ_F_VALUE_PLUS_9_72 8153726 // hz = 9.7200000000062 +#define IQ_F_VALUE_PLUS_9_73 8162115 // hz = 9.7300000000062 +#define IQ_F_VALUE_PLUS_9_74 8170504 // hz = 9.7400000000062 +#define IQ_F_VALUE_PLUS_9_75 8178892 // hz = 9.7500000000062 +#define IQ_F_VALUE_PLUS_9_76 8187281 // hz = 9.7600000000062 +#define IQ_F_VALUE_PLUS_9_77 8195670 // hz = 9.7700000000062 +#define IQ_F_VALUE_PLUS_9_78 8204058 // hz = 9.7800000000062 +#define IQ_F_VALUE_PLUS_9_79 8212447 // hz = 9.7900000000062 +#define IQ_F_VALUE_PLUS_9_80 8220835 // hz = 9.8000000000062 +#define IQ_F_VALUE_PLUS_9_81 8229224 // hz = 9.8100000000062 +#define IQ_F_VALUE_PLUS_9_82 8237613 // hz = 9.8200000000062 +#define IQ_F_VALUE_PLUS_9_83 8246001 // hz = 9.8300000000062 +#define IQ_F_VALUE_PLUS_9_84 8254390 // hz = 9.8400000000062 +#define IQ_F_VALUE_PLUS_9_85 8262778 // hz = 9.8500000000062 +#define IQ_F_VALUE_PLUS_9_86 8271167 // hz = 9.8600000000062 +#define IQ_F_VALUE_PLUS_9_87 8279556 // hz = 9.8700000000062 +#define IQ_F_VALUE_PLUS_9_88 8287944 // hz = 9.8800000000062 +#define IQ_F_VALUE_PLUS_9_89 8296333 // hz = 9.8900000000062 +#define IQ_F_VALUE_PLUS_9_90 8304721 // hz = 9.9000000000062 +#define IQ_F_VALUE_PLUS_9_91 8313110 // hz = 9.9100000000062 +#define IQ_F_VALUE_PLUS_9_92 8321499 // hz = 9.9200000000062 +#define IQ_F_VALUE_PLUS_9_93 8329887 // hz = 9.9300000000062 +#define IQ_F_VALUE_PLUS_9_94 8338276 // hz = 9.9400000000062 +#define IQ_F_VALUE_PLUS_9_95 8346664 // hz = 9.9500000000062 +#define IQ_F_VALUE_PLUS_9_96 8355053 // hz = 9.9600000000062 +#define IQ_F_VALUE_PLUS_9_97 8363442 // hz = 9.9700000000063 +#define IQ_F_VALUE_PLUS_9_98 8371830 // hz = 9.9800000000062 +#define IQ_F_VALUE_PLUS_9_99 8380219 // hz = 9.9900000000062 +#define IQ_F_VALUE_PLUS_10_00 8388608 // hz = 10.0000000000063 +#define IQ_F_VALUE_PLUS_10_01 8396996 // hz = 10.0100000000063 +#define IQ_F_VALUE_PLUS_10_02 8405385 // hz = 10.0200000000063 +#define IQ_F_VALUE_PLUS_10_03 8413773 // hz = 10.0300000000063 +#define IQ_F_VALUE_PLUS_10_04 8422162 // hz = 10.0400000000063 +#define IQ_F_VALUE_PLUS_10_05 8430551 // hz = 10.0500000000063 +#define IQ_F_VALUE_PLUS_10_06 8438939 // hz = 10.0600000000063 +#define IQ_F_VALUE_PLUS_10_07 8447328 // hz = 10.0700000000063 +#define IQ_F_VALUE_PLUS_10_08 8455716 // hz = 10.0800000000063 +#define IQ_F_VALUE_PLUS_10_09 8464105 // hz = 10.0900000000063 +#define IQ_F_VALUE_PLUS_10_10 8472494 // hz = 10.1000000000063 +#define IQ_F_VALUE_PLUS_10_11 8480882 // hz = 10.1100000000063 +#define IQ_F_VALUE_PLUS_10_12 8489271 // hz = 10.1200000000063 +#define IQ_F_VALUE_PLUS_10_13 8497659 // hz = 10.1300000000063 +#define IQ_F_VALUE_PLUS_10_14 8506048 // hz = 10.1400000000063 +#define IQ_F_VALUE_PLUS_10_15 8514437 // hz = 10.1500000000063 +#define IQ_F_VALUE_PLUS_10_16 8522825 // hz = 10.1600000000063 +#define IQ_F_VALUE_PLUS_10_17 8531214 // hz = 10.1700000000063 +#define IQ_F_VALUE_PLUS_10_18 8539602 // hz = 10.1800000000063 +#define IQ_F_VALUE_PLUS_10_19 8547991 // hz = 10.1900000000063 +#define IQ_F_VALUE_PLUS_10_20 8556380 // hz = 10.2000000000063 +#define IQ_F_VALUE_PLUS_10_21 8564768 // hz = 10.2100000000063 +#define IQ_F_VALUE_PLUS_10_22 8573157 // hz = 10.2200000000063 +#define IQ_F_VALUE_PLUS_10_23 8581545 // hz = 10.2300000000063 +#define IQ_F_VALUE_PLUS_10_24 8589934 // hz = 10.2400000000063 +#define IQ_F_VALUE_PLUS_10_25 8598323 // hz = 10.2500000000063 +#define IQ_F_VALUE_PLUS_10_26 8606711 // hz = 10.2600000000063 +#define IQ_F_VALUE_PLUS_10_27 8615100 // hz = 10.2700000000063 +#define IQ_F_VALUE_PLUS_10_28 8623489 // hz = 10.2800000000063 +#define IQ_F_VALUE_PLUS_10_29 8631877 // hz = 10.2900000000063 +#define IQ_F_VALUE_PLUS_10_30 8640266 // hz = 10.3000000000063 +#define IQ_F_VALUE_PLUS_10_31 8648654 // hz = 10.3100000000063 +#define IQ_F_VALUE_PLUS_10_32 8657043 // hz = 10.3200000000063 +#define IQ_F_VALUE_PLUS_10_33 8665432 // hz = 10.3300000000063 +#define IQ_F_VALUE_PLUS_10_34 8673820 // hz = 10.3400000000063 +#define IQ_F_VALUE_PLUS_10_35 8682209 // hz = 10.3500000000063 +#define IQ_F_VALUE_PLUS_10_36 8690597 // hz = 10.3600000000063 +#define IQ_F_VALUE_PLUS_10_37 8698986 // hz = 10.3700000000063 +#define IQ_F_VALUE_PLUS_10_38 8707375 // hz = 10.3800000000063 +#define IQ_F_VALUE_PLUS_10_39 8715763 // hz = 10.3900000000063 +#define IQ_F_VALUE_PLUS_10_40 8724152 // hz = 10.4000000000063 +#define IQ_F_VALUE_PLUS_10_41 8732540 // hz = 10.4100000000063 +#define IQ_F_VALUE_PLUS_10_42 8740929 // hz = 10.4200000000063 +#define IQ_F_VALUE_PLUS_10_43 8749318 // hz = 10.4300000000063 +#define IQ_F_VALUE_PLUS_10_44 8757706 // hz = 10.4400000000063 +#define IQ_F_VALUE_PLUS_10_45 8766095 // hz = 10.4500000000063 +#define IQ_F_VALUE_PLUS_10_46 8774483 // hz = 10.4600000000063 +#define IQ_F_VALUE_PLUS_10_47 8782872 // hz = 10.4700000000063 +#define IQ_F_VALUE_PLUS_10_48 8791261 // hz = 10.4800000000063 +#define IQ_F_VALUE_PLUS_10_49 8799649 // hz = 10.4900000000063 +#define IQ_F_VALUE_PLUS_10_50 8808038 // hz = 10.5000000000063 +#define IQ_F_VALUE_PLUS_10_51 8816427 // hz = 10.5100000000063 +#define IQ_F_VALUE_PLUS_10_52 8824815 // hz = 10.5200000000063 +#define IQ_F_VALUE_PLUS_10_53 8833204 // hz = 10.5300000000063 +#define IQ_F_VALUE_PLUS_10_54 8841592 // hz = 10.5400000000063 +#define IQ_F_VALUE_PLUS_10_55 8849981 // hz = 10.5500000000063 +#define IQ_F_VALUE_PLUS_10_56 8858370 // hz = 10.5600000000063 +#define IQ_F_VALUE_PLUS_10_57 8866758 // hz = 10.5700000000063 +#define IQ_F_VALUE_PLUS_10_58 8875147 // hz = 10.5800000000063 +#define IQ_F_VALUE_PLUS_10_59 8883535 // hz = 10.5900000000063 +#define IQ_F_VALUE_PLUS_10_60 8891924 // hz = 10.6000000000063 +#define IQ_F_VALUE_PLUS_10_61 8900313 // hz = 10.6100000000064 +#define IQ_F_VALUE_PLUS_10_62 8908701 // hz = 10.6200000000063 +#define IQ_F_VALUE_PLUS_10_63 8917090 // hz = 10.6300000000063 +#define IQ_F_VALUE_PLUS_10_64 8925478 // hz = 10.6400000000064 +#define IQ_F_VALUE_PLUS_10_65 8933867 // hz = 10.6500000000064 +#define IQ_F_VALUE_PLUS_10_66 8942256 // hz = 10.6600000000064 +#define IQ_F_VALUE_PLUS_10_67 8950644 // hz = 10.6700000000064 +#define IQ_F_VALUE_PLUS_10_68 8959033 // hz = 10.6800000000064 +#define IQ_F_VALUE_PLUS_10_69 8967421 // hz = 10.6900000000064 +#define IQ_F_VALUE_PLUS_10_70 8975810 // hz = 10.7000000000064 +#define IQ_F_VALUE_PLUS_10_71 8984199 // hz = 10.7100000000064 +#define IQ_F_VALUE_PLUS_10_72 8992587 // hz = 10.7200000000064 +#define IQ_F_VALUE_PLUS_10_73 9000976 // hz = 10.7300000000064 +#define IQ_F_VALUE_PLUS_10_74 9009364 // hz = 10.7400000000064 +#define IQ_F_VALUE_PLUS_10_75 9017753 // hz = 10.7500000000064 +#define IQ_F_VALUE_PLUS_10_76 9026142 // hz = 10.7600000000064 +#define IQ_F_VALUE_PLUS_10_77 9034530 // hz = 10.7700000000064 +#define IQ_F_VALUE_PLUS_10_78 9042919 // hz = 10.7800000000064 +#define IQ_F_VALUE_PLUS_10_79 9051308 // hz = 10.7900000000064 +#define IQ_F_VALUE_PLUS_10_80 9059696 // hz = 10.8000000000064 +#define IQ_F_VALUE_PLUS_10_81 9068085 // hz = 10.8100000000064 +#define IQ_F_VALUE_PLUS_10_82 9076473 // hz = 10.8200000000064 +#define IQ_F_VALUE_PLUS_10_83 9084862 // hz = 10.8300000000064 +#define IQ_F_VALUE_PLUS_10_84 9093251 // hz = 10.8400000000064 +#define IQ_F_VALUE_PLUS_10_85 9101639 // hz = 10.8500000000064 +#define IQ_F_VALUE_PLUS_10_86 9110028 // hz = 10.8600000000064 +#define IQ_F_VALUE_PLUS_10_87 9118416 // hz = 10.8700000000064 +#define IQ_F_VALUE_PLUS_10_88 9126805 // hz = 10.8800000000064 +#define IQ_F_VALUE_PLUS_10_89 9135194 // hz = 10.8900000000064 +#define IQ_F_VALUE_PLUS_10_90 9143582 // hz = 10.9000000000064 +#define IQ_F_VALUE_PLUS_10_91 9151971 // hz = 10.9100000000064 +#define IQ_F_VALUE_PLUS_10_92 9160359 // hz = 10.9200000000064 +#define IQ_F_VALUE_PLUS_10_93 9168748 // hz = 10.9300000000064 +#define IQ_F_VALUE_PLUS_10_94 9177137 // hz = 10.9400000000064 +#define IQ_F_VALUE_PLUS_10_95 9185525 // hz = 10.9500000000064 +#define IQ_F_VALUE_PLUS_10_96 9193914 // hz = 10.9600000000064 +#define IQ_F_VALUE_PLUS_10_97 9202302 // hz = 10.9700000000064 +#define IQ_F_VALUE_PLUS_10_98 9210691 // hz = 10.9800000000064 +#define IQ_F_VALUE_PLUS_10_99 9219080 // hz = 10.9900000000064 +#define IQ_F_VALUE_PLUS_11_00 9227468 // hz = 11.0000000000064 +#define IQ_F_VALUE_PLUS_11_01 9235857 // hz = 11.0100000000064 +#define IQ_F_VALUE_PLUS_11_02 9244246 // hz = 11.0200000000064 +#define IQ_F_VALUE_PLUS_11_03 9252634 // hz = 11.0300000000064 +#define IQ_F_VALUE_PLUS_11_04 9261023 // hz = 11.0400000000064 +#define IQ_F_VALUE_PLUS_11_05 9269411 // hz = 11.0500000000064 +#define IQ_F_VALUE_PLUS_11_06 9277800 // hz = 11.0600000000064 +#define IQ_F_VALUE_PLUS_11_07 9286189 // hz = 11.0700000000064 +#define IQ_F_VALUE_PLUS_11_08 9294577 // hz = 11.0800000000064 +#define IQ_F_VALUE_PLUS_11_09 9302966 // hz = 11.0900000000064 +#define IQ_F_VALUE_PLUS_11_10 9311354 // hz = 11.1000000000064 +#define IQ_F_VALUE_PLUS_11_11 9319743 // hz = 11.1100000000064 +#define IQ_F_VALUE_PLUS_11_12 9328132 // hz = 11.1200000000064 +#define IQ_F_VALUE_PLUS_11_13 9336520 // hz = 11.1300000000064 +#define IQ_F_VALUE_PLUS_11_14 9344909 // hz = 11.1400000000064 +#define IQ_F_VALUE_PLUS_11_15 9353297 // hz = 11.1500000000064 +#define IQ_F_VALUE_PLUS_11_16 9361686 // hz = 11.1600000000064 +#define IQ_F_VALUE_PLUS_11_17 9370075 // hz = 11.1700000000064 +#define IQ_F_VALUE_PLUS_11_18 9378463 // hz = 11.1800000000064 +#define IQ_F_VALUE_PLUS_11_19 9386852 // hz = 11.1900000000064 +#define IQ_F_VALUE_PLUS_11_20 9395240 // hz = 11.2000000000064 +#define IQ_F_VALUE_PLUS_11_21 9403629 // hz = 11.2100000000064 +#define IQ_F_VALUE_PLUS_11_22 9412018 // hz = 11.2200000000064 +#define IQ_F_VALUE_PLUS_11_23 9420406 // hz = 11.2300000000064 +#define IQ_F_VALUE_PLUS_11_24 9428795 // hz = 11.2400000000064 +#define IQ_F_VALUE_PLUS_11_25 9437184 // hz = 11.2500000000065 +#define IQ_F_VALUE_PLUS_11_26 9445572 // hz = 11.2600000000064 +#define IQ_F_VALUE_PLUS_11_27 9453961 // hz = 11.2700000000064 +#define IQ_F_VALUE_PLUS_11_28 9462349 // hz = 11.2800000000065 +#define IQ_F_VALUE_PLUS_11_29 9470738 // hz = 11.2900000000065 +#define IQ_F_VALUE_PLUS_11_30 9479127 // hz = 11.3000000000065 +#define IQ_F_VALUE_PLUS_11_31 9487515 // hz = 11.3100000000065 +#define IQ_F_VALUE_PLUS_11_32 9495904 // hz = 11.3200000000065 +#define IQ_F_VALUE_PLUS_11_33 9504292 // hz = 11.3300000000065 +#define IQ_F_VALUE_PLUS_11_34 9512681 // hz = 11.3400000000065 +#define IQ_F_VALUE_PLUS_11_35 9521070 // hz = 11.3500000000065 +#define IQ_F_VALUE_PLUS_11_36 9529458 // hz = 11.3600000000065 +#define IQ_F_VALUE_PLUS_11_37 9537847 // hz = 11.3700000000065 +#define IQ_F_VALUE_PLUS_11_38 9546235 // hz = 11.3800000000065 +#define IQ_F_VALUE_PLUS_11_39 9554624 // hz = 11.3900000000065 +#define IQ_F_VALUE_PLUS_11_40 9563013 // hz = 11.4000000000065 +#define IQ_F_VALUE_PLUS_11_41 9571401 // hz = 11.4100000000065 +#define IQ_F_VALUE_PLUS_11_42 9579790 // hz = 11.4200000000065 +#define IQ_F_VALUE_PLUS_11_43 9588178 // hz = 11.4300000000065 +#define IQ_F_VALUE_PLUS_11_44 9596567 // hz = 11.4400000000065 +#define IQ_F_VALUE_PLUS_11_45 9604956 // hz = 11.4500000000065 +#define IQ_F_VALUE_PLUS_11_46 9613344 // hz = 11.4600000000065 +#define IQ_F_VALUE_PLUS_11_47 9621733 // hz = 11.4700000000065 +#define IQ_F_VALUE_PLUS_11_48 9630121 // hz = 11.4800000000065 +#define IQ_F_VALUE_PLUS_11_49 9638510 // hz = 11.4900000000065 +#define IQ_F_VALUE_PLUS_11_50 9646899 // hz = 11.5000000000065 +#define IQ_F_VALUE_PLUS_11_51 9655287 // hz = 11.5100000000065 +#define IQ_F_VALUE_PLUS_11_52 9663676 // hz = 11.5200000000065 +#define IQ_F_VALUE_PLUS_11_53 9672065 // hz = 11.5300000000065 +#define IQ_F_VALUE_PLUS_11_54 9680453 // hz = 11.5400000000065 +#define IQ_F_VALUE_PLUS_11_55 9688842 // hz = 11.5500000000065 +#define IQ_F_VALUE_PLUS_11_56 9697230 // hz = 11.5600000000065 +#define IQ_F_VALUE_PLUS_11_57 9705619 // hz = 11.5700000000065 +#define IQ_F_VALUE_PLUS_11_58 9714008 // hz = 11.5800000000065 +#define IQ_F_VALUE_PLUS_11_59 9722396 // hz = 11.5900000000065 +#define IQ_F_VALUE_PLUS_11_60 9730785 // hz = 11.6000000000065 +#define IQ_F_VALUE_PLUS_11_61 9739173 // hz = 11.6100000000065 +#define IQ_F_VALUE_PLUS_11_62 9747562 // hz = 11.6200000000065 +#define IQ_F_VALUE_PLUS_11_63 9755951 // hz = 11.6300000000065 +#define IQ_F_VALUE_PLUS_11_64 9764339 // hz = 11.6400000000065 +#define IQ_F_VALUE_PLUS_11_65 9772728 // hz = 11.6500000000065 +#define IQ_F_VALUE_PLUS_11_66 9781116 // hz = 11.6600000000065 +#define IQ_F_VALUE_PLUS_11_67 9789505 // hz = 11.6700000000065 +#define IQ_F_VALUE_PLUS_11_68 9797894 // hz = 11.6800000000065 +#define IQ_F_VALUE_PLUS_11_69 9806282 // hz = 11.6900000000065 +#define IQ_F_VALUE_PLUS_11_70 9814671 // hz = 11.7000000000065 +#define IQ_F_VALUE_PLUS_11_71 9823059 // hz = 11.7100000000065 +#define IQ_F_VALUE_PLUS_11_72 9831448 // hz = 11.7200000000065 +#define IQ_F_VALUE_PLUS_11_73 9839837 // hz = 11.7300000000065 +#define IQ_F_VALUE_PLUS_11_74 9848225 // hz = 11.7400000000065 +#define IQ_F_VALUE_PLUS_11_75 9856614 // hz = 11.7500000000065 +#define IQ_F_VALUE_PLUS_11_76 9865003 // hz = 11.7600000000065 +#define IQ_F_VALUE_PLUS_11_77 9873391 // hz = 11.7700000000065 +#define IQ_F_VALUE_PLUS_11_78 9881780 // hz = 11.7800000000065 +#define IQ_F_VALUE_PLUS_11_79 9890168 // hz = 11.7900000000065 +#define IQ_F_VALUE_PLUS_11_80 9898557 // hz = 11.8000000000065 +#define IQ_F_VALUE_PLUS_11_81 9906946 // hz = 11.8100000000065 +#define IQ_F_VALUE_PLUS_11_82 9915334 // hz = 11.8200000000065 +#define IQ_F_VALUE_PLUS_11_83 9923723 // hz = 11.8300000000065 +#define IQ_F_VALUE_PLUS_11_84 9932111 // hz = 11.8400000000065 +#define IQ_F_VALUE_PLUS_11_85 9940500 // hz = 11.8500000000065 +#define IQ_F_VALUE_PLUS_11_86 9948889 // hz = 11.8600000000065 +#define IQ_F_VALUE_PLUS_11_87 9957277 // hz = 11.8700000000065 +#define IQ_F_VALUE_PLUS_11_88 9965666 // hz = 11.8800000000065 +#define IQ_F_VALUE_PLUS_11_89 9974054 // hz = 11.8900000000066 +#define IQ_F_VALUE_PLUS_11_90 9982443 // hz = 11.9000000000065 +#define IQ_F_VALUE_PLUS_11_91 9990832 // hz = 11.9100000000065 +#define IQ_F_VALUE_PLUS_11_92 9999220 // hz = 11.9200000000066 +#define IQ_F_VALUE_PLUS_11_93 10007609 // hz = 11.9300000000066 +#define IQ_F_VALUE_PLUS_11_94 10015997 // hz = 11.9400000000066 +#define IQ_F_VALUE_PLUS_11_95 10024386 // hz = 11.9500000000066 +#define IQ_F_VALUE_PLUS_11_96 10032775 // hz = 11.9600000000066 +#define IQ_F_VALUE_PLUS_11_97 10041163 // hz = 11.9700000000066 +#define IQ_F_VALUE_PLUS_11_98 10049552 // hz = 11.9800000000066 +#define IQ_F_VALUE_PLUS_11_99 10057940 // hz = 11.9900000000066 +#define IQ_F_VALUE_PLUS_12_00 10066329 // hz = 12.0000000000066 +#define IQ_F_VALUE_PLUS_12_01 10074718 // hz = 12.0100000000066 +#define IQ_F_VALUE_PLUS_12_02 10083106 // hz = 12.0200000000066 +#define IQ_F_VALUE_PLUS_12_03 10091495 // hz = 12.0300000000066 +#define IQ_F_VALUE_PLUS_12_04 10099884 // hz = 12.0400000000066 +#define IQ_F_VALUE_PLUS_12_05 10108272 // hz = 12.0500000000066 +#define IQ_F_VALUE_PLUS_12_06 10116661 // hz = 12.0600000000066 +#define IQ_F_VALUE_PLUS_12_07 10125049 // hz = 12.0700000000066 +#define IQ_F_VALUE_PLUS_12_08 10133438 // hz = 12.0800000000066 +#define IQ_F_VALUE_PLUS_12_09 10141827 // hz = 12.0900000000066 +#define IQ_F_VALUE_PLUS_12_10 10150215 // hz = 12.1000000000066 +#define IQ_F_VALUE_PLUS_12_11 10158604 // hz = 12.1100000000066 +#define IQ_F_VALUE_PLUS_12_12 10166992 // hz = 12.1200000000066 +#define IQ_F_VALUE_PLUS_12_13 10175381 // hz = 12.1300000000066 +#define IQ_F_VALUE_PLUS_12_14 10183770 // hz = 12.1400000000066 +#define IQ_F_VALUE_PLUS_12_15 10192158 // hz = 12.1500000000066 +#define IQ_F_VALUE_PLUS_12_16 10200547 // hz = 12.1600000000066 +#define IQ_F_VALUE_PLUS_12_17 10208935 // hz = 12.1700000000066 +#define IQ_F_VALUE_PLUS_12_18 10217324 // hz = 12.1800000000066 +#define IQ_F_VALUE_PLUS_12_19 10225713 // hz = 12.1900000000066 +#define IQ_F_VALUE_PLUS_12_20 10234101 // hz = 12.2000000000066 +#define IQ_F_VALUE_PLUS_12_21 10242490 // hz = 12.2100000000066 +#define IQ_F_VALUE_PLUS_12_22 10250878 // hz = 12.2200000000066 +#define IQ_F_VALUE_PLUS_12_23 10259267 // hz = 12.2300000000066 +#define IQ_F_VALUE_PLUS_12_24 10267656 // hz = 12.2400000000066 +#define IQ_F_VALUE_PLUS_12_25 10276044 // hz = 12.2500000000066 +#define IQ_F_VALUE_PLUS_12_26 10284433 // hz = 12.2600000000066 +#define IQ_F_VALUE_PLUS_12_27 10292822 // hz = 12.2700000000066 +#define IQ_F_VALUE_PLUS_12_28 10301210 // hz = 12.2800000000066 +#define IQ_F_VALUE_PLUS_12_29 10309599 // hz = 12.2900000000066 +#define IQ_F_VALUE_PLUS_12_30 10317987 // hz = 12.3000000000066 +#define IQ_F_VALUE_PLUS_12_31 10326376 // hz = 12.3100000000066 +#define IQ_F_VALUE_PLUS_12_32 10334765 // hz = 12.3200000000066 +#define IQ_F_VALUE_PLUS_12_33 10343153 // hz = 12.3300000000066 +#define IQ_F_VALUE_PLUS_12_34 10351542 // hz = 12.3400000000066 +#define IQ_F_VALUE_PLUS_12_35 10359930 // hz = 12.3500000000066 +#define IQ_F_VALUE_PLUS_12_36 10368319 // hz = 12.3600000000066 +#define IQ_F_VALUE_PLUS_12_37 10376708 // hz = 12.3700000000066 +#define IQ_F_VALUE_PLUS_12_38 10385096 // hz = 12.3800000000066 +#define IQ_F_VALUE_PLUS_12_39 10393485 // hz = 12.3900000000066 +#define IQ_F_VALUE_PLUS_12_40 10401873 // hz = 12.4000000000066 +#define IQ_F_VALUE_PLUS_12_41 10410262 // hz = 12.4100000000066 +#define IQ_F_VALUE_PLUS_12_42 10418651 // hz = 12.4200000000066 +#define IQ_F_VALUE_PLUS_12_43 10427039 // hz = 12.4300000000066 +#define IQ_F_VALUE_PLUS_12_44 10435428 // hz = 12.4400000000066 +#define IQ_F_VALUE_PLUS_12_45 10443816 // hz = 12.4500000000066 +#define IQ_F_VALUE_PLUS_12_46 10452205 // hz = 12.4600000000066 +#define IQ_F_VALUE_PLUS_12_47 10460594 // hz = 12.4700000000066 +#define IQ_F_VALUE_PLUS_12_48 10468982 // hz = 12.4800000000066 +#define IQ_F_VALUE_PLUS_12_49 10477371 // hz = 12.4900000000066 +#define IQ_F_VALUE_PLUS_12_50 10485760 // hz = 12.5000000000066 +#define IQ_F_VALUE_PLUS_12_51 10494148 // hz = 12.5100000000066 +#define IQ_F_VALUE_PLUS_12_52 10502537 // hz = 12.5200000000066 +#define IQ_F_VALUE_PLUS_12_53 10510925 // hz = 12.5300000000067 +#define IQ_F_VALUE_PLUS_12_54 10519314 // hz = 12.5400000000066 +#define IQ_F_VALUE_PLUS_12_55 10527703 // hz = 12.5500000000066 +#define IQ_F_VALUE_PLUS_12_56 10536091 // hz = 12.5600000000067 +#define IQ_F_VALUE_PLUS_12_57 10544480 // hz = 12.5700000000067 +#define IQ_F_VALUE_PLUS_12_58 10552868 // hz = 12.5800000000067 +#define IQ_F_VALUE_PLUS_12_59 10561257 // hz = 12.5900000000067 +#define IQ_F_VALUE_PLUS_12_60 10569646 // hz = 12.6000000000067 +#define IQ_F_VALUE_PLUS_12_61 10578034 // hz = 12.6100000000067 +#define IQ_F_VALUE_PLUS_12_62 10586423 // hz = 12.6200000000067 +#define IQ_F_VALUE_PLUS_12_63 10594811 // hz = 12.6300000000067 +#define IQ_F_VALUE_PLUS_12_64 10603200 // hz = 12.6400000000067 +#define IQ_F_VALUE_PLUS_12_65 10611589 // hz = 12.6500000000067 +#define IQ_F_VALUE_PLUS_12_66 10619977 // hz = 12.6600000000067 +#define IQ_F_VALUE_PLUS_12_67 10628366 // hz = 12.6700000000067 +#define IQ_F_VALUE_PLUS_12_68 10636754 // hz = 12.6800000000067 +#define IQ_F_VALUE_PLUS_12_69 10645143 // hz = 12.6900000000067 +#define IQ_F_VALUE_PLUS_12_70 10653532 // hz = 12.7000000000067 +#define IQ_F_VALUE_PLUS_12_71 10661920 // hz = 12.7100000000067 +#define IQ_F_VALUE_PLUS_12_72 10670309 // hz = 12.7200000000067 +#define IQ_F_VALUE_PLUS_12_73 10678697 // hz = 12.7300000000067 +#define IQ_F_VALUE_PLUS_12_74 10687086 // hz = 12.7400000000067 +#define IQ_F_VALUE_PLUS_12_75 10695475 // hz = 12.7500000000067 +#define IQ_F_VALUE_PLUS_12_76 10703863 // hz = 12.7600000000067 +#define IQ_F_VALUE_PLUS_12_77 10712252 // hz = 12.7700000000067 +#define IQ_F_VALUE_PLUS_12_78 10720641 // hz = 12.7800000000067 +#define IQ_F_VALUE_PLUS_12_79 10729029 // hz = 12.7900000000067 +#define IQ_F_VALUE_PLUS_12_80 10737418 // hz = 12.8000000000067 +#define IQ_F_VALUE_PLUS_12_81 10745806 // hz = 12.8100000000067 +#define IQ_F_VALUE_PLUS_12_82 10754195 // hz = 12.8200000000067 +#define IQ_F_VALUE_PLUS_12_83 10762584 // hz = 12.8300000000067 +#define IQ_F_VALUE_PLUS_12_84 10770972 // hz = 12.8400000000067 +#define IQ_F_VALUE_PLUS_12_85 10779361 // hz = 12.8500000000067 +#define IQ_F_VALUE_PLUS_12_86 10787749 // hz = 12.8600000000067 +#define IQ_F_VALUE_PLUS_12_87 10796138 // hz = 12.8700000000067 +#define IQ_F_VALUE_PLUS_12_88 10804527 // hz = 12.8800000000067 +#define IQ_F_VALUE_PLUS_12_89 10812915 // hz = 12.8900000000067 +#define IQ_F_VALUE_PLUS_12_90 10821304 // hz = 12.9000000000067 +#define IQ_F_VALUE_PLUS_12_91 10829692 // hz = 12.9100000000067 +#define IQ_F_VALUE_PLUS_12_92 10838081 // hz = 12.9200000000067 +#define IQ_F_VALUE_PLUS_12_93 10846470 // hz = 12.9300000000067 +#define IQ_F_VALUE_PLUS_12_94 10854858 // hz = 12.9400000000067 +#define IQ_F_VALUE_PLUS_12_95 10863247 // hz = 12.9500000000067 +#define IQ_F_VALUE_PLUS_12_96 10871635 // hz = 12.9600000000067 +#define IQ_F_VALUE_PLUS_12_97 10880024 // hz = 12.9700000000067 +#define IQ_F_VALUE_PLUS_12_98 10888413 // hz = 12.9800000000067 +#define IQ_F_VALUE_PLUS_12_99 10896801 // hz = 12.9900000000067 +#define IQ_F_VALUE_PLUS_13_00 10905190 // hz = 13.0000000000067 +#define IQ_F_VALUE_PLUS_13_01 10913579 // hz = 13.0100000000067 +#define IQ_F_VALUE_PLUS_13_02 10921967 // hz = 13.0200000000067 +#define IQ_F_VALUE_PLUS_13_03 10930356 // hz = 13.0300000000067 +#define IQ_F_VALUE_PLUS_13_04 10938744 // hz = 13.0400000000067 +#define IQ_F_VALUE_PLUS_13_05 10947133 // hz = 13.0500000000067 +#define IQ_F_VALUE_PLUS_13_06 10955522 // hz = 13.0600000000067 +#define IQ_F_VALUE_PLUS_13_07 10963910 // hz = 13.0700000000067 +#define IQ_F_VALUE_PLUS_13_08 10972299 // hz = 13.0800000000067 +#define IQ_F_VALUE_PLUS_13_09 10980687 // hz = 13.0900000000067 +#define IQ_F_VALUE_PLUS_13_10 10989076 // hz = 13.1000000000067 +#define IQ_F_VALUE_PLUS_13_11 10997465 // hz = 13.1100000000067 +#define IQ_F_VALUE_PLUS_13_12 11005853 // hz = 13.1200000000067 +#define IQ_F_VALUE_PLUS_13_13 11014242 // hz = 13.1300000000067 +#define IQ_F_VALUE_PLUS_13_14 11022630 // hz = 13.1400000000067 +#define IQ_F_VALUE_PLUS_13_15 11031019 // hz = 13.1500000000067 +#define IQ_F_VALUE_PLUS_13_16 11039408 // hz = 13.1600000000067 +#define IQ_F_VALUE_PLUS_13_17 11047796 // hz = 13.1700000000068 +#define IQ_F_VALUE_PLUS_13_18 11056185 // hz = 13.1800000000067 +#define IQ_F_VALUE_PLUS_13_19 11064573 // hz = 13.1900000000067 +#define IQ_F_VALUE_PLUS_13_20 11072962 // hz = 13.2000000000068 +#define IQ_F_VALUE_PLUS_13_21 11081351 // hz = 13.2100000000068 +#define IQ_F_VALUE_PLUS_13_22 11089739 // hz = 13.2200000000068 +#define IQ_F_VALUE_PLUS_13_23 11098128 // hz = 13.2300000000068 +#define IQ_F_VALUE_PLUS_13_24 11106516 // hz = 13.2400000000068 +#define IQ_F_VALUE_PLUS_13_25 11114905 // hz = 13.2500000000068 +#define IQ_F_VALUE_PLUS_13_26 11123294 // hz = 13.2600000000068 +#define IQ_F_VALUE_PLUS_13_27 11131682 // hz = 13.2700000000068 +#define IQ_F_VALUE_PLUS_13_28 11140071 // hz = 13.2800000000068 +#define IQ_F_VALUE_PLUS_13_29 11148460 // hz = 13.2900000000068 +#define IQ_F_VALUE_PLUS_13_30 11156848 // hz = 13.3000000000068 +#define IQ_F_VALUE_PLUS_13_31 11165237 // hz = 13.3100000000068 +#define IQ_F_VALUE_PLUS_13_32 11173625 // hz = 13.3200000000068 +#define IQ_F_VALUE_PLUS_13_33 11182014 // hz = 13.3300000000068 +#define IQ_F_VALUE_PLUS_13_34 11190403 // hz = 13.3400000000068 +#define IQ_F_VALUE_PLUS_13_35 11198791 // hz = 13.3500000000068 +#define IQ_F_VALUE_PLUS_13_36 11207180 // hz = 13.3600000000068 +#define IQ_F_VALUE_PLUS_13_37 11215568 // hz = 13.3700000000068 +#define IQ_F_VALUE_PLUS_13_38 11223957 // hz = 13.3800000000068 +#define IQ_F_VALUE_PLUS_13_39 11232346 // hz = 13.3900000000068 +#define IQ_F_VALUE_PLUS_13_40 11240734 // hz = 13.4000000000068 +#define IQ_F_VALUE_PLUS_13_41 11249123 // hz = 13.4100000000068 +#define IQ_F_VALUE_PLUS_13_42 11257511 // hz = 13.4200000000068 +#define IQ_F_VALUE_PLUS_13_43 11265900 // hz = 13.4300000000068 +#define IQ_F_VALUE_PLUS_13_44 11274289 // hz = 13.4400000000068 +#define IQ_F_VALUE_PLUS_13_45 11282677 // hz = 13.4500000000068 +#define IQ_F_VALUE_PLUS_13_46 11291066 // hz = 13.4600000000068 +#define IQ_F_VALUE_PLUS_13_47 11299454 // hz = 13.4700000000068 +#define IQ_F_VALUE_PLUS_13_48 11307843 // hz = 13.4800000000068 +#define IQ_F_VALUE_PLUS_13_49 11316232 // hz = 13.4900000000068 +#define IQ_F_VALUE_PLUS_13_50 11324620 // hz = 13.5000000000068 +#define IQ_F_VALUE_PLUS_13_51 11333009 // hz = 13.5100000000068 +#define IQ_F_VALUE_PLUS_13_52 11341398 // hz = 13.5200000000068 +#define IQ_F_VALUE_PLUS_13_53 11349786 // hz = 13.5300000000068 +#define IQ_F_VALUE_PLUS_13_54 11358175 // hz = 13.5400000000068 +#define IQ_F_VALUE_PLUS_13_55 11366563 // hz = 13.5500000000068 +#define IQ_F_VALUE_PLUS_13_56 11374952 // hz = 13.5600000000068 +#define IQ_F_VALUE_PLUS_13_57 11383341 // hz = 13.5700000000068 +#define IQ_F_VALUE_PLUS_13_58 11391729 // hz = 13.5800000000068 +#define IQ_F_VALUE_PLUS_13_59 11400118 // hz = 13.5900000000068 +#define IQ_F_VALUE_PLUS_13_60 11408506 // hz = 13.6000000000068 +#define IQ_F_VALUE_PLUS_13_61 11416895 // hz = 13.6100000000068 +#define IQ_F_VALUE_PLUS_13_62 11425284 // hz = 13.6200000000068 +#define IQ_F_VALUE_PLUS_13_63 11433672 // hz = 13.6300000000068 +#define IQ_F_VALUE_PLUS_13_64 11442061 // hz = 13.6400000000068 +#define IQ_F_VALUE_PLUS_13_65 11450449 // hz = 13.6500000000068 +#define IQ_F_VALUE_PLUS_13_66 11458838 // hz = 13.6600000000068 +#define IQ_F_VALUE_PLUS_13_67 11467227 // hz = 13.6700000000068 +#define IQ_F_VALUE_PLUS_13_68 11475615 // hz = 13.6800000000068 +#define IQ_F_VALUE_PLUS_13_69 11484004 // hz = 13.6900000000068 +#define IQ_F_VALUE_PLUS_13_70 11492392 // hz = 13.7000000000068 +#define IQ_F_VALUE_PLUS_13_71 11500781 // hz = 13.7100000000068 +#define IQ_F_VALUE_PLUS_13_72 11509170 // hz = 13.7200000000068 +#define IQ_F_VALUE_PLUS_13_73 11517558 // hz = 13.7300000000068 +#define IQ_F_VALUE_PLUS_13_74 11525947 // hz = 13.7400000000068 +#define IQ_F_VALUE_PLUS_13_75 11534336 // hz = 13.7500000000068 +#define IQ_F_VALUE_PLUS_13_76 11542724 // hz = 13.7600000000068 +#define IQ_F_VALUE_PLUS_13_77 11551113 // hz = 13.7700000000068 +#define IQ_F_VALUE_PLUS_13_78 11559501 // hz = 13.7800000000068 +#define IQ_F_VALUE_PLUS_13_79 11567890 // hz = 13.7900000000068 +#define IQ_F_VALUE_PLUS_13_80 11576279 // hz = 13.8000000000068 +#define IQ_F_VALUE_PLUS_13_81 11584667 // hz = 13.8100000000069 +#define IQ_F_VALUE_PLUS_13_82 11593056 // hz = 13.8200000000068 +#define IQ_F_VALUE_PLUS_13_83 11601444 // hz = 13.8300000000068 +#define IQ_F_VALUE_PLUS_13_84 11609833 // hz = 13.8400000000069 +#define IQ_F_VALUE_PLUS_13_85 11618222 // hz = 13.8500000000069 +#define IQ_F_VALUE_PLUS_13_86 11626610 // hz = 13.8600000000069 +#define IQ_F_VALUE_PLUS_13_87 11634999 // hz = 13.8700000000069 +#define IQ_F_VALUE_PLUS_13_88 11643387 // hz = 13.8800000000069 +#define IQ_F_VALUE_PLUS_13_89 11651776 // hz = 13.8900000000069 +#define IQ_F_VALUE_PLUS_13_90 11660165 // hz = 13.9000000000069 +#define IQ_F_VALUE_PLUS_13_91 11668553 // hz = 13.9100000000069 +#define IQ_F_VALUE_PLUS_13_92 11676942 // hz = 13.9200000000069 +#define IQ_F_VALUE_PLUS_13_93 11685330 // hz = 13.9300000000069 +#define IQ_F_VALUE_PLUS_13_94 11693719 // hz = 13.9400000000069 +#define IQ_F_VALUE_PLUS_13_95 11702108 // hz = 13.9500000000069 +#define IQ_F_VALUE_PLUS_13_96 11710496 // hz = 13.9600000000069 +#define IQ_F_VALUE_PLUS_13_97 11718885 // hz = 13.9700000000069 +#define IQ_F_VALUE_PLUS_13_98 11727273 // hz = 13.9800000000069 +#define IQ_F_VALUE_PLUS_13_99 11735662 // hz = 13.9900000000069 +#define IQ_F_VALUE_PLUS_14_00 11744051 // hz = 14.0000000000069 +#define IQ_F_VALUE_PLUS_14_01 11752439 // hz = 14.0100000000069 +#define IQ_F_VALUE_PLUS_14_02 11760828 // hz = 14.0200000000069 +#define IQ_F_VALUE_PLUS_14_03 11769217 // hz = 14.0300000000069 +#define IQ_F_VALUE_PLUS_14_04 11777605 // hz = 14.0400000000069 +#define IQ_F_VALUE_PLUS_14_05 11785994 // hz = 14.0500000000069 +#define IQ_F_VALUE_PLUS_14_06 11794382 // hz = 14.0600000000069 +#define IQ_F_VALUE_PLUS_14_07 11802771 // hz = 14.0700000000069 +#define IQ_F_VALUE_PLUS_14_08 11811160 // hz = 14.0800000000069 +#define IQ_F_VALUE_PLUS_14_09 11819548 // hz = 14.0900000000069 +#define IQ_F_VALUE_PLUS_14_10 11827937 // hz = 14.1000000000069 +#define IQ_F_VALUE_PLUS_14_11 11836325 // hz = 14.1100000000069 +#define IQ_F_VALUE_PLUS_14_12 11844714 // hz = 14.1200000000069 +#define IQ_F_VALUE_PLUS_14_13 11853103 // hz = 14.1300000000069 +#define IQ_F_VALUE_PLUS_14_14 11861491 // hz = 14.1400000000069 +#define IQ_F_VALUE_PLUS_14_15 11869880 // hz = 14.1500000000069 +#define IQ_F_VALUE_PLUS_14_16 11878268 // hz = 14.1600000000069 +#define IQ_F_VALUE_PLUS_14_17 11886657 // hz = 14.1700000000069 +#define IQ_F_VALUE_PLUS_14_18 11895046 // hz = 14.1800000000069 +#define IQ_F_VALUE_PLUS_14_19 11903434 // hz = 14.1900000000069 +#define IQ_F_VALUE_PLUS_14_20 11911823 // hz = 14.2000000000069 +#define IQ_F_VALUE_PLUS_14_21 11920211 // hz = 14.2100000000069 +#define IQ_F_VALUE_PLUS_14_22 11928600 // hz = 14.2200000000069 +#define IQ_F_VALUE_PLUS_14_23 11936989 // hz = 14.2300000000069 +#define IQ_F_VALUE_PLUS_14_24 11945377 // hz = 14.2400000000069 +#define IQ_F_VALUE_PLUS_14_25 11953766 // hz = 14.2500000000069 +#define IQ_F_VALUE_PLUS_14_26 11962155 // hz = 14.2600000000069 +#define IQ_F_VALUE_PLUS_14_27 11970543 // hz = 14.2700000000069 +#define IQ_F_VALUE_PLUS_14_28 11978932 // hz = 14.2800000000069 +#define IQ_F_VALUE_PLUS_14_29 11987320 // hz = 14.2900000000069 +#define IQ_F_VALUE_PLUS_14_30 11995709 // hz = 14.3000000000069 +#define IQ_F_VALUE_PLUS_14_31 12004098 // hz = 14.3100000000069 +#define IQ_F_VALUE_PLUS_14_32 12012486 // hz = 14.3200000000069 +#define IQ_F_VALUE_PLUS_14_33 12020875 // hz = 14.3300000000069 +#define IQ_F_VALUE_PLUS_14_34 12029263 // hz = 14.3400000000069 +#define IQ_F_VALUE_PLUS_14_35 12037652 // hz = 14.3500000000069 +#define IQ_F_VALUE_PLUS_14_36 12046041 // hz = 14.3600000000069 +#define IQ_F_VALUE_PLUS_14_37 12054429 // hz = 14.3700000000069 +#define IQ_F_VALUE_PLUS_14_38 12062818 // hz = 14.3800000000069 +#define IQ_F_VALUE_PLUS_14_39 12071206 // hz = 14.3900000000069 +#define IQ_F_VALUE_PLUS_14_40 12079595 // hz = 14.4000000000069 +#define IQ_F_VALUE_PLUS_14_41 12087984 // hz = 14.4100000000069 +#define IQ_F_VALUE_PLUS_14_42 12096372 // hz = 14.4200000000069 +#define IQ_F_VALUE_PLUS_14_43 12104761 // hz = 14.4300000000069 +#define IQ_F_VALUE_PLUS_14_44 12113149 // hz = 14.4400000000069 +#define IQ_F_VALUE_PLUS_14_45 12121538 // hz = 14.450000000007 +#define IQ_F_VALUE_PLUS_14_46 12129927 // hz = 14.4600000000069 +#define IQ_F_VALUE_PLUS_14_47 12138315 // hz = 14.4700000000069 +#define IQ_F_VALUE_PLUS_14_48 12146704 // hz = 14.480000000007 +#define IQ_F_VALUE_PLUS_14_49 12155092 // hz = 14.490000000007 +#define IQ_F_VALUE_PLUS_14_50 12163481 // hz = 14.500000000007 +#define IQ_F_VALUE_PLUS_14_51 12171870 // hz = 14.510000000007 +#define IQ_F_VALUE_PLUS_14_52 12180258 // hz = 14.520000000007 +#define IQ_F_VALUE_PLUS_14_53 12188647 // hz = 14.530000000007 +#define IQ_F_VALUE_PLUS_14_54 12197036 // hz = 14.540000000007 +#define IQ_F_VALUE_PLUS_14_55 12205424 // hz = 14.550000000007 +#define IQ_F_VALUE_PLUS_14_56 12213813 // hz = 14.560000000007 +#define IQ_F_VALUE_PLUS_14_57 12222201 // hz = 14.570000000007 +#define IQ_F_VALUE_PLUS_14_58 12230590 // hz = 14.580000000007 +#define IQ_F_VALUE_PLUS_14_59 12238979 // hz = 14.590000000007 +#define IQ_F_VALUE_PLUS_14_60 12247367 // hz = 14.600000000007 +#define IQ_F_VALUE_PLUS_14_61 12255756 // hz = 14.610000000007 +#define IQ_F_VALUE_PLUS_14_62 12264144 // hz = 14.620000000007 +#define IQ_F_VALUE_PLUS_14_63 12272533 // hz = 14.630000000007 +#define IQ_F_VALUE_PLUS_14_64 12280922 // hz = 14.640000000007 +#define IQ_F_VALUE_PLUS_14_65 12289310 // hz = 14.650000000007 +#define IQ_F_VALUE_PLUS_14_66 12297699 // hz = 14.660000000007 +#define IQ_F_VALUE_PLUS_14_67 12306087 // hz = 14.670000000007 +#define IQ_F_VALUE_PLUS_14_68 12314476 // hz = 14.680000000007 +#define IQ_F_VALUE_PLUS_14_69 12322865 // hz = 14.690000000007 +#define IQ_F_VALUE_PLUS_14_70 12331253 // hz = 14.700000000007 +#define IQ_F_VALUE_PLUS_14_71 12339642 // hz = 14.710000000007 +#define IQ_F_VALUE_PLUS_14_72 12348030 // hz = 14.720000000007 +#define IQ_F_VALUE_PLUS_14_73 12356419 // hz = 14.730000000007 +#define IQ_F_VALUE_PLUS_14_74 12364808 // hz = 14.740000000007 +#define IQ_F_VALUE_PLUS_14_75 12373196 // hz = 14.750000000007 +#define IQ_F_VALUE_PLUS_14_76 12381585 // hz = 14.760000000007 +#define IQ_F_VALUE_PLUS_14_77 12389974 // hz = 14.770000000007 +#define IQ_F_VALUE_PLUS_14_78 12398362 // hz = 14.780000000007 +#define IQ_F_VALUE_PLUS_14_79 12406751 // hz = 14.790000000007 +#define IQ_F_VALUE_PLUS_14_80 12415139 // hz = 14.800000000007 +#define IQ_F_VALUE_PLUS_14_81 12423528 // hz = 14.810000000007 +#define IQ_F_VALUE_PLUS_14_82 12431917 // hz = 14.820000000007 +#define IQ_F_VALUE_PLUS_14_83 12440305 // hz = 14.830000000007 +#define IQ_F_VALUE_PLUS_14_84 12448694 // hz = 14.840000000007 +#define IQ_F_VALUE_PLUS_14_85 12457082 // hz = 14.850000000007 +#define IQ_F_VALUE_PLUS_14_86 12465471 // hz = 14.860000000007 +#define IQ_F_VALUE_PLUS_14_87 12473860 // hz = 14.870000000007 +#define IQ_F_VALUE_PLUS_14_88 12482248 // hz = 14.880000000007 +#define IQ_F_VALUE_PLUS_14_89 12490637 // hz = 14.890000000007 +#define IQ_F_VALUE_PLUS_14_90 12499025 // hz = 14.900000000007 +#define IQ_F_VALUE_PLUS_14_91 12507414 // hz = 14.910000000007 +#define IQ_F_VALUE_PLUS_14_92 12515803 // hz = 14.920000000007 +#define IQ_F_VALUE_PLUS_14_93 12524191 // hz = 14.930000000007 +#define IQ_F_VALUE_PLUS_14_94 12532580 // hz = 14.940000000007 +#define IQ_F_VALUE_PLUS_14_95 12540968 // hz = 14.950000000007 +#define IQ_F_VALUE_PLUS_14_96 12549357 // hz = 14.960000000007 +#define IQ_F_VALUE_PLUS_14_97 12557746 // hz = 14.970000000007 +#define IQ_F_VALUE_PLUS_14_98 12566134 // hz = 14.980000000007 +#define IQ_F_VALUE_PLUS_14_99 12574523 // hz = 14.990000000007 +#define IQ_F_VALUE_PLUS_15_00 12582912 // hz = 15.000000000007 +#define IQ_F_VALUE_PLUS_15_01 12591300 // hz = 15.010000000007 +#define IQ_F_VALUE_PLUS_15_02 12599689 // hz = 15.020000000007 +#define IQ_F_VALUE_PLUS_15_03 12608077 // hz = 15.030000000007 +#define IQ_F_VALUE_PLUS_15_04 12616466 // hz = 15.040000000007 +#define IQ_F_VALUE_PLUS_15_05 12624855 // hz = 15.050000000007 +#define IQ_F_VALUE_PLUS_15_06 12633243 // hz = 15.060000000007 +#define IQ_F_VALUE_PLUS_15_07 12641632 // hz = 15.070000000007 +#define IQ_F_VALUE_PLUS_15_08 12650020 // hz = 15.080000000007 +#define IQ_F_VALUE_PLUS_15_09 12658409 // hz = 15.0900000000071 +#define IQ_F_VALUE_PLUS_15_10 12666798 // hz = 15.1000000000071 +#define IQ_F_VALUE_PLUS_15_11 12675186 // hz = 15.110000000007 +#define IQ_F_VALUE_PLUS_15_12 12683575 // hz = 15.1200000000071 +#define IQ_F_VALUE_PLUS_15_13 12691963 // hz = 15.1300000000071 +#define IQ_F_VALUE_PLUS_15_14 12700352 // hz = 15.1400000000071 +#define IQ_F_VALUE_PLUS_15_15 12708741 // hz = 15.1500000000071 +#define IQ_F_VALUE_PLUS_15_16 12717129 // hz = 15.1600000000071 +#define IQ_F_VALUE_PLUS_15_17 12725518 // hz = 15.1700000000071 +#define IQ_F_VALUE_PLUS_15_18 12733906 // hz = 15.1800000000071 +#define IQ_F_VALUE_PLUS_15_19 12742295 // hz = 15.1900000000071 +#define IQ_F_VALUE_PLUS_15_20 12750684 // hz = 15.2000000000071 +#define IQ_F_VALUE_PLUS_15_21 12759072 // hz = 15.2100000000071 +#define IQ_F_VALUE_PLUS_15_22 12767461 // hz = 15.2200000000071 +#define IQ_F_VALUE_PLUS_15_23 12775849 // hz = 15.2300000000071 +#define IQ_F_VALUE_PLUS_15_24 12784238 // hz = 15.2400000000071 +#define IQ_F_VALUE_PLUS_15_25 12792627 // hz = 15.2500000000071 +#define IQ_F_VALUE_PLUS_15_26 12801015 // hz = 15.2600000000071 +#define IQ_F_VALUE_PLUS_15_27 12809404 // hz = 15.2700000000071 +#define IQ_F_VALUE_PLUS_15_28 12817793 // hz = 15.2800000000071 +#define IQ_F_VALUE_PLUS_15_29 12826181 // hz = 15.2900000000071 +#define IQ_F_VALUE_PLUS_15_30 12834570 // hz = 15.3000000000071 +#define IQ_F_VALUE_PLUS_15_31 12842958 // hz = 15.3100000000071 +#define IQ_F_VALUE_PLUS_15_32 12851347 // hz = 15.3200000000071 +#define IQ_F_VALUE_PLUS_15_33 12859736 // hz = 15.3300000000071 +#define IQ_F_VALUE_PLUS_15_34 12868124 // hz = 15.3400000000071 +#define IQ_F_VALUE_PLUS_15_35 12876513 // hz = 15.3500000000071 +#define IQ_F_VALUE_PLUS_15_36 12884901 // hz = 15.3600000000071 +#define IQ_F_VALUE_PLUS_15_37 12893290 // hz = 15.3700000000071 +#define IQ_F_VALUE_PLUS_15_38 12901679 // hz = 15.3800000000071 +#define IQ_F_VALUE_PLUS_15_39 12910067 // hz = 15.3900000000071 +#define IQ_F_VALUE_PLUS_15_40 12918456 // hz = 15.4000000000071 +#define IQ_F_VALUE_PLUS_15_41 12926844 // hz = 15.4100000000071 +#define IQ_F_VALUE_PLUS_15_42 12935233 // hz = 15.4200000000071 +#define IQ_F_VALUE_PLUS_15_43 12943622 // hz = 15.4300000000071 +#define IQ_F_VALUE_PLUS_15_44 12952010 // hz = 15.4400000000071 +#define IQ_F_VALUE_PLUS_15_45 12960399 // hz = 15.4500000000071 +#define IQ_F_VALUE_PLUS_15_46 12968787 // hz = 15.4600000000071 +#define IQ_F_VALUE_PLUS_15_47 12977176 // hz = 15.4700000000071 +#define IQ_F_VALUE_PLUS_15_48 12985565 // hz = 15.4800000000071 +#define IQ_F_VALUE_PLUS_15_49 12993953 // hz = 15.4900000000071 +#define IQ_F_VALUE_PLUS_15_50 13002342 // hz = 15.5000000000071 +#define IQ_F_VALUE_PLUS_15_51 13010731 // hz = 15.5100000000071 +#define IQ_F_VALUE_PLUS_15_52 13019119 // hz = 15.5200000000071 +#define IQ_F_VALUE_PLUS_15_53 13027508 // hz = 15.5300000000071 +#define IQ_F_VALUE_PLUS_15_54 13035896 // hz = 15.5400000000071 +#define IQ_F_VALUE_PLUS_15_55 13044285 // hz = 15.5500000000071 +#define IQ_F_VALUE_PLUS_15_56 13052674 // hz = 15.5600000000071 +#define IQ_F_VALUE_PLUS_15_57 13061062 // hz = 15.5700000000071 +#define IQ_F_VALUE_PLUS_15_58 13069451 // hz = 15.5800000000071 +#define IQ_F_VALUE_PLUS_15_59 13077839 // hz = 15.5900000000071 +#define IQ_F_VALUE_PLUS_15_60 13086228 // hz = 15.6000000000071 +#define IQ_F_VALUE_PLUS_15_61 13094617 // hz = 15.6100000000071 +#define IQ_F_VALUE_PLUS_15_62 13103005 // hz = 15.6200000000071 +#define IQ_F_VALUE_PLUS_15_63 13111394 // hz = 15.6300000000071 +#define IQ_F_VALUE_PLUS_15_64 13119782 // hz = 15.6400000000071 +#define IQ_F_VALUE_PLUS_15_65 13128171 // hz = 15.6500000000071 +#define IQ_F_VALUE_PLUS_15_66 13136560 // hz = 15.6600000000071 +#define IQ_F_VALUE_PLUS_15_67 13144948 // hz = 15.6700000000071 +#define IQ_F_VALUE_PLUS_15_68 13153337 // hz = 15.6800000000071 +#define IQ_F_VALUE_PLUS_15_69 13161725 // hz = 15.6900000000071 +#define IQ_F_VALUE_PLUS_15_70 13170114 // hz = 15.7000000000071 +#define IQ_F_VALUE_PLUS_15_71 13178503 // hz = 15.7100000000071 +#define IQ_F_VALUE_PLUS_15_72 13186891 // hz = 15.7200000000071 +#define IQ_F_VALUE_PLUS_15_73 13195280 // hz = 15.7300000000072 +#define IQ_F_VALUE_PLUS_15_74 13203668 // hz = 15.7400000000072 +#define IQ_F_VALUE_PLUS_15_75 13212057 // hz = 15.7500000000071 +#define IQ_F_VALUE_PLUS_15_76 13220446 // hz = 15.7600000000072 +#define IQ_F_VALUE_PLUS_15_77 13228834 // hz = 15.7700000000072 +#define IQ_F_VALUE_PLUS_15_78 13237223 // hz = 15.7800000000072 +#define IQ_F_VALUE_PLUS_15_79 13245612 // hz = 15.7900000000072 +#define IQ_F_VALUE_PLUS_15_80 13254000 // hz = 15.8000000000072 +#define IQ_F_VALUE_PLUS_15_81 13262389 // hz = 15.8100000000072 +#define IQ_F_VALUE_PLUS_15_82 13270777 // hz = 15.8200000000072 +#define IQ_F_VALUE_PLUS_15_83 13279166 // hz = 15.8300000000072 +#define IQ_F_VALUE_PLUS_15_84 13287555 // hz = 15.8400000000072 +#define IQ_F_VALUE_PLUS_15_85 13295943 // hz = 15.8500000000072 +#define IQ_F_VALUE_PLUS_15_86 13304332 // hz = 15.8600000000072 +#define IQ_F_VALUE_PLUS_15_87 13312720 // hz = 15.8700000000072 +#define IQ_F_VALUE_PLUS_15_88 13321109 // hz = 15.8800000000072 +#define IQ_F_VALUE_PLUS_15_89 13329498 // hz = 15.8900000000072 +#define IQ_F_VALUE_PLUS_15_90 13337886 // hz = 15.9000000000072 +#define IQ_F_VALUE_PLUS_15_91 13346275 // hz = 15.9100000000072 +#define IQ_F_VALUE_PLUS_15_92 13354663 // hz = 15.9200000000072 +#define IQ_F_VALUE_PLUS_15_93 13363052 // hz = 15.9300000000072 +#define IQ_F_VALUE_PLUS_15_94 13371441 // hz = 15.9400000000072 +#define IQ_F_VALUE_PLUS_15_95 13379829 // hz = 15.9500000000072 +#define IQ_F_VALUE_PLUS_15_96 13388218 // hz = 15.9600000000072 +#define IQ_F_VALUE_PLUS_15_97 13396606 // hz = 15.9700000000072 +#define IQ_F_VALUE_PLUS_15_98 13404995 // hz = 15.9800000000072 +#define IQ_F_VALUE_PLUS_15_99 13413384 // hz = 15.9900000000072 +#define IQ_F_VALUE_PLUS_16_00 13421772 // hz = 16.0000000000072 +#define IQ_F_VALUE_PLUS_16_01 13430161 // hz = 16.0100000000072 +#define IQ_F_VALUE_PLUS_16_02 13438550 // hz = 16.0200000000072 +#define IQ_F_VALUE_PLUS_16_03 13446938 // hz = 16.0300000000072 +#define IQ_F_VALUE_PLUS_16_04 13455327 // hz = 16.0400000000072 +#define IQ_F_VALUE_PLUS_16_05 13463715 // hz = 16.0500000000072 +#define IQ_F_VALUE_PLUS_16_06 13472104 // hz = 16.0600000000072 +#define IQ_F_VALUE_PLUS_16_07 13480493 // hz = 16.0700000000072 +#define IQ_F_VALUE_PLUS_16_08 13488881 // hz = 16.0800000000072 +#define IQ_F_VALUE_PLUS_16_09 13497270 // hz = 16.0900000000072 +#define IQ_F_VALUE_PLUS_16_10 13505658 // hz = 16.1000000000072 +#define IQ_F_VALUE_PLUS_16_11 13514047 // hz = 16.1100000000072 +#define IQ_F_VALUE_PLUS_16_12 13522436 // hz = 16.1200000000072 +#define IQ_F_VALUE_PLUS_16_13 13530824 // hz = 16.1300000000072 +#define IQ_F_VALUE_PLUS_16_14 13539213 // hz = 16.1400000000072 +#define IQ_F_VALUE_PLUS_16_15 13547601 // hz = 16.1500000000072 +#define IQ_F_VALUE_PLUS_16_16 13555990 // hz = 16.1600000000072 +#define IQ_F_VALUE_PLUS_16_17 13564379 // hz = 16.1700000000072 +#define IQ_F_VALUE_PLUS_16_18 13572767 // hz = 16.1800000000072 +#define IQ_F_VALUE_PLUS_16_19 13581156 // hz = 16.1900000000072 +#define IQ_F_VALUE_PLUS_16_20 13589544 // hz = 16.2000000000072 +#define IQ_F_VALUE_PLUS_16_21 13597933 // hz = 16.2100000000072 +#define IQ_F_VALUE_PLUS_16_22 13606322 // hz = 16.2200000000072 +#define IQ_F_VALUE_PLUS_16_23 13614710 // hz = 16.2300000000072 +#define IQ_F_VALUE_PLUS_16_24 13623099 // hz = 16.2400000000072 +#define IQ_F_VALUE_PLUS_16_25 13631488 // hz = 16.2500000000072 +#define IQ_F_VALUE_PLUS_16_26 13639876 // hz = 16.2600000000072 +#define IQ_F_VALUE_PLUS_16_27 13648265 // hz = 16.2700000000072 +#define IQ_F_VALUE_PLUS_16_28 13656653 // hz = 16.2800000000072 +#define IQ_F_VALUE_PLUS_16_29 13665042 // hz = 16.2900000000072 +#define IQ_F_VALUE_PLUS_16_30 13673431 // hz = 16.3000000000072 +#define IQ_F_VALUE_PLUS_16_31 13681819 // hz = 16.3100000000072 +#define IQ_F_VALUE_PLUS_16_32 13690208 // hz = 16.3200000000072 +#define IQ_F_VALUE_PLUS_16_33 13698596 // hz = 16.3300000000072 +#define IQ_F_VALUE_PLUS_16_34 13706985 // hz = 16.3400000000072 +#define IQ_F_VALUE_PLUS_16_35 13715374 // hz = 16.3500000000072 +#define IQ_F_VALUE_PLUS_16_36 13723762 // hz = 16.3600000000072 +#define IQ_F_VALUE_PLUS_16_37 13732151 // hz = 16.3700000000073 +#define IQ_F_VALUE_PLUS_16_38 13740539 // hz = 16.3800000000073 +#define IQ_F_VALUE_PLUS_16_39 13748928 // hz = 16.3900000000072 +#define IQ_F_VALUE_PLUS_16_40 13757317 // hz = 16.4000000000073 +#define IQ_F_VALUE_PLUS_16_41 13765705 // hz = 16.4100000000073 +#define IQ_F_VALUE_PLUS_16_42 13774094 // hz = 16.4200000000073 +#define IQ_F_VALUE_PLUS_16_43 13782482 // hz = 16.4300000000073 +#define IQ_F_VALUE_PLUS_16_44 13790871 // hz = 16.4400000000073 +#define IQ_F_VALUE_PLUS_16_45 13799260 // hz = 16.4500000000073 +#define IQ_F_VALUE_PLUS_16_46 13807648 // hz = 16.4600000000073 +#define IQ_F_VALUE_PLUS_16_47 13816037 // hz = 16.4700000000073 +#define IQ_F_VALUE_PLUS_16_48 13824425 // hz = 16.4800000000073 +#define IQ_F_VALUE_PLUS_16_49 13832814 // hz = 16.4900000000073 +#define IQ_F_VALUE_PLUS_16_50 13841203 // hz = 16.5000000000073 +#define IQ_F_VALUE_PLUS_16_51 13849591 // hz = 16.5100000000073 +#define IQ_F_VALUE_PLUS_16_52 13857980 // hz = 16.5200000000073 +#define IQ_F_VALUE_PLUS_16_53 13866369 // hz = 16.5300000000073 +#define IQ_F_VALUE_PLUS_16_54 13874757 // hz = 16.5400000000073 +#define IQ_F_VALUE_PLUS_16_55 13883146 // hz = 16.5500000000073 +#define IQ_F_VALUE_PLUS_16_56 13891534 // hz = 16.5600000000073 +#define IQ_F_VALUE_PLUS_16_57 13899923 // hz = 16.5700000000073 +#define IQ_F_VALUE_PLUS_16_58 13908312 // hz = 16.5800000000073 +#define IQ_F_VALUE_PLUS_16_59 13916700 // hz = 16.5900000000073 +#define IQ_F_VALUE_PLUS_16_60 13925089 // hz = 16.6000000000073 +#define IQ_F_VALUE_PLUS_16_61 13933477 // hz = 16.6100000000073 +#define IQ_F_VALUE_PLUS_16_62 13941866 // hz = 16.6200000000073 +#define IQ_F_VALUE_PLUS_16_63 13950255 // hz = 16.6300000000073 +#define IQ_F_VALUE_PLUS_16_64 13958643 // hz = 16.6400000000073 +#define IQ_F_VALUE_PLUS_16_65 13967032 // hz = 16.6500000000073 +#define IQ_F_VALUE_PLUS_16_66 13975420 // hz = 16.6600000000073 +#define IQ_F_VALUE_PLUS_16_67 13983809 // hz = 16.6700000000073 +#define IQ_F_VALUE_PLUS_16_68 13992198 // hz = 16.6800000000073 +#define IQ_F_VALUE_PLUS_16_69 14000586 // hz = 16.6900000000073 +#define IQ_F_VALUE_PLUS_16_70 14008975 // hz = 16.7000000000073 +#define IQ_F_VALUE_PLUS_16_71 14017363 // hz = 16.7100000000073 +#define IQ_F_VALUE_PLUS_16_72 14025752 // hz = 16.7200000000073 +#define IQ_F_VALUE_PLUS_16_73 14034141 // hz = 16.7300000000073 +#define IQ_F_VALUE_PLUS_16_74 14042529 // hz = 16.7400000000073 +#define IQ_F_VALUE_PLUS_16_75 14050918 // hz = 16.7500000000073 +#define IQ_F_VALUE_PLUS_16_76 14059307 // hz = 16.7600000000073 +#define IQ_F_VALUE_PLUS_16_77 14067695 // hz = 16.7700000000073 +#define IQ_F_VALUE_PLUS_16_78 14076084 // hz = 16.7800000000073 +#define IQ_F_VALUE_PLUS_16_79 14084472 // hz = 16.7900000000073 +#define IQ_F_VALUE_PLUS_16_80 14092861 // hz = 16.8000000000073 +#define IQ_F_VALUE_PLUS_16_81 14101250 // hz = 16.8100000000073 +#define IQ_F_VALUE_PLUS_16_82 14109638 // hz = 16.8200000000073 +#define IQ_F_VALUE_PLUS_16_83 14118027 // hz = 16.8300000000073 +#define IQ_F_VALUE_PLUS_16_84 14126415 // hz = 16.8400000000073 +#define IQ_F_VALUE_PLUS_16_85 14134804 // hz = 16.8500000000073 +#define IQ_F_VALUE_PLUS_16_86 14143193 // hz = 16.8600000000073 +#define IQ_F_VALUE_PLUS_16_87 14151581 // hz = 16.8700000000073 +#define IQ_F_VALUE_PLUS_16_88 14159970 // hz = 16.8800000000073 +#define IQ_F_VALUE_PLUS_16_89 14168358 // hz = 16.8900000000073 +#define IQ_F_VALUE_PLUS_16_90 14176747 // hz = 16.9000000000073 +#define IQ_F_VALUE_PLUS_16_91 14185136 // hz = 16.9100000000073 +#define IQ_F_VALUE_PLUS_16_92 14193524 // hz = 16.9200000000073 +#define IQ_F_VALUE_PLUS_16_93 14201913 // hz = 16.9300000000073 +#define IQ_F_VALUE_PLUS_16_94 14210301 // hz = 16.9400000000073 +#define IQ_F_VALUE_PLUS_16_95 14218690 // hz = 16.9500000000073 +#define IQ_F_VALUE_PLUS_16_96 14227079 // hz = 16.9600000000073 +#define IQ_F_VALUE_PLUS_16_97 14235467 // hz = 16.9700000000073 +#define IQ_F_VALUE_PLUS_16_98 14243856 // hz = 16.9800000000073 +#define IQ_F_VALUE_PLUS_16_99 14252244 // hz = 16.9900000000073 +#define IQ_F_VALUE_PLUS_17_00 14260633 // hz = 17.0000000000073 +#define IQ_F_VALUE_PLUS_17_01 14269022 // hz = 17.0100000000074 +#define IQ_F_VALUE_PLUS_17_02 14277410 // hz = 17.0200000000074 +#define IQ_F_VALUE_PLUS_17_03 14285799 // hz = 17.0300000000073 +#define IQ_F_VALUE_PLUS_17_04 14294188 // hz = 17.0400000000074 +#define IQ_F_VALUE_PLUS_17_05 14302576 // hz = 17.0500000000074 +#define IQ_F_VALUE_PLUS_17_06 14310965 // hz = 17.0600000000074 +#define IQ_F_VALUE_PLUS_17_07 14319353 // hz = 17.0700000000074 +#define IQ_F_VALUE_PLUS_17_08 14327742 // hz = 17.0800000000074 +#define IQ_F_VALUE_PLUS_17_09 14336131 // hz = 17.0900000000074 +#define IQ_F_VALUE_PLUS_17_10 14344519 // hz = 17.1000000000074 +#define IQ_F_VALUE_PLUS_17_11 14352908 // hz = 17.1100000000074 +#define IQ_F_VALUE_PLUS_17_12 14361296 // hz = 17.1200000000074 +#define IQ_F_VALUE_PLUS_17_13 14369685 // hz = 17.1300000000074 +#define IQ_F_VALUE_PLUS_17_14 14378074 // hz = 17.1400000000074 +#define IQ_F_VALUE_PLUS_17_15 14386462 // hz = 17.1500000000074 +#define IQ_F_VALUE_PLUS_17_16 14394851 // hz = 17.1600000000074 +#define IQ_F_VALUE_PLUS_17_17 14403239 // hz = 17.1700000000074 +#define IQ_F_VALUE_PLUS_17_18 14411628 // hz = 17.1800000000074 +#define IQ_F_VALUE_PLUS_17_19 14420017 // hz = 17.1900000000074 +#define IQ_F_VALUE_PLUS_17_20 14428405 // hz = 17.2000000000074 +#define IQ_F_VALUE_PLUS_17_21 14436794 // hz = 17.2100000000074 +#define IQ_F_VALUE_PLUS_17_22 14445182 // hz = 17.2200000000074 +#define IQ_F_VALUE_PLUS_17_23 14453571 // hz = 17.2300000000074 +#define IQ_F_VALUE_PLUS_17_24 14461960 // hz = 17.2400000000074 +#define IQ_F_VALUE_PLUS_17_25 14470348 // hz = 17.2500000000074 +#define IQ_F_VALUE_PLUS_17_26 14478737 // hz = 17.2600000000074 +#define IQ_F_VALUE_PLUS_17_27 14487126 // hz = 17.2700000000074 +#define IQ_F_VALUE_PLUS_17_28 14495514 // hz = 17.2800000000074 +#define IQ_F_VALUE_PLUS_17_29 14503903 // hz = 17.2900000000074 +#define IQ_F_VALUE_PLUS_17_30 14512291 // hz = 17.3000000000074 +#define IQ_F_VALUE_PLUS_17_31 14520680 // hz = 17.3100000000074 +#define IQ_F_VALUE_PLUS_17_32 14529069 // hz = 17.3200000000074 +#define IQ_F_VALUE_PLUS_17_33 14537457 // hz = 17.3300000000074 +#define IQ_F_VALUE_PLUS_17_34 14545846 // hz = 17.3400000000074 +#define IQ_F_VALUE_PLUS_17_35 14554234 // hz = 17.3500000000074 +#define IQ_F_VALUE_PLUS_17_36 14562623 // hz = 17.3600000000074 +#define IQ_F_VALUE_PLUS_17_37 14571012 // hz = 17.3700000000074 +#define IQ_F_VALUE_PLUS_17_38 14579400 // hz = 17.3800000000074 +#define IQ_F_VALUE_PLUS_17_39 14587789 // hz = 17.3900000000074 +#define IQ_F_VALUE_PLUS_17_40 14596177 // hz = 17.4000000000074 +#define IQ_F_VALUE_PLUS_17_41 14604566 // hz = 17.4100000000074 +#define IQ_F_VALUE_PLUS_17_42 14612955 // hz = 17.4200000000074 +#define IQ_F_VALUE_PLUS_17_43 14621343 // hz = 17.4300000000074 +#define IQ_F_VALUE_PLUS_17_44 14629732 // hz = 17.4400000000074 +#define IQ_F_VALUE_PLUS_17_45 14638120 // hz = 17.4500000000074 +#define IQ_F_VALUE_PLUS_17_46 14646509 // hz = 17.4600000000074 +#define IQ_F_VALUE_PLUS_17_47 14654898 // hz = 17.4700000000074 +#define IQ_F_VALUE_PLUS_17_48 14663286 // hz = 17.4800000000074 +#define IQ_F_VALUE_PLUS_17_49 14671675 // hz = 17.4900000000074 +#define IQ_F_VALUE_PLUS_17_50 14680064 // hz = 17.5000000000074 +#define IQ_F_VALUE_PLUS_17_51 14688452 // hz = 17.5100000000074 +#define IQ_F_VALUE_PLUS_17_52 14696841 // hz = 17.5200000000074 +#define IQ_F_VALUE_PLUS_17_53 14705229 // hz = 17.5300000000074 +#define IQ_F_VALUE_PLUS_17_54 14713618 // hz = 17.5400000000074 +#define IQ_F_VALUE_PLUS_17_55 14722007 // hz = 17.5500000000074 +#define IQ_F_VALUE_PLUS_17_56 14730395 // hz = 17.5600000000074 +#define IQ_F_VALUE_PLUS_17_57 14738784 // hz = 17.5700000000074 +#define IQ_F_VALUE_PLUS_17_58 14747172 // hz = 17.5800000000074 +#define IQ_F_VALUE_PLUS_17_59 14755561 // hz = 17.5900000000074 +#define IQ_F_VALUE_PLUS_17_60 14763950 // hz = 17.6000000000074 +#define IQ_F_VALUE_PLUS_17_61 14772338 // hz = 17.6100000000074 +#define IQ_F_VALUE_PLUS_17_62 14780727 // hz = 17.6200000000074 +#define IQ_F_VALUE_PLUS_17_63 14789115 // hz = 17.6300000000074 +#define IQ_F_VALUE_PLUS_17_64 14797504 // hz = 17.6400000000074 +#define IQ_F_VALUE_PLUS_17_65 14805893 // hz = 17.6500000000075 +#define IQ_F_VALUE_PLUS_17_66 14814281 // hz = 17.6600000000075 +#define IQ_F_VALUE_PLUS_17_67 14822670 // hz = 17.6700000000074 +#define IQ_F_VALUE_PLUS_17_68 14831058 // hz = 17.6800000000075 +#define IQ_F_VALUE_PLUS_17_69 14839447 // hz = 17.6900000000075 +#define IQ_F_VALUE_PLUS_17_70 14847836 // hz = 17.7000000000075 +#define IQ_F_VALUE_PLUS_17_71 14856224 // hz = 17.7100000000075 +#define IQ_F_VALUE_PLUS_17_72 14864613 // hz = 17.7200000000075 +#define IQ_F_VALUE_PLUS_17_73 14873001 // hz = 17.7300000000075 +#define IQ_F_VALUE_PLUS_17_74 14881390 // hz = 17.7400000000075 +#define IQ_F_VALUE_PLUS_17_75 14889779 // hz = 17.7500000000075 +#define IQ_F_VALUE_PLUS_17_76 14898167 // hz = 17.7600000000075 +#define IQ_F_VALUE_PLUS_17_77 14906556 // hz = 17.7700000000075 +#define IQ_F_VALUE_PLUS_17_78 14914945 // hz = 17.7800000000075 +#define IQ_F_VALUE_PLUS_17_79 14923333 // hz = 17.7900000000075 +#define IQ_F_VALUE_PLUS_17_80 14931722 // hz = 17.8000000000075 +#define IQ_F_VALUE_PLUS_17_81 14940110 // hz = 17.8100000000075 +#define IQ_F_VALUE_PLUS_17_82 14948499 // hz = 17.8200000000075 +#define IQ_F_VALUE_PLUS_17_83 14956888 // hz = 17.8300000000075 +#define IQ_F_VALUE_PLUS_17_84 14965276 // hz = 17.8400000000075 +#define IQ_F_VALUE_PLUS_17_85 14973665 // hz = 17.8500000000075 +#define IQ_F_VALUE_PLUS_17_86 14982053 // hz = 17.8600000000075 +#define IQ_F_VALUE_PLUS_17_87 14990442 // hz = 17.8700000000075 +#define IQ_F_VALUE_PLUS_17_88 14998831 // hz = 17.8800000000075 +#define IQ_F_VALUE_PLUS_17_89 15007219 // hz = 17.8900000000075 +#define IQ_F_VALUE_PLUS_17_90 15015608 // hz = 17.9000000000075 +#define IQ_F_VALUE_PLUS_17_91 15023996 // hz = 17.9100000000075 +#define IQ_F_VALUE_PLUS_17_92 15032385 // hz = 17.9200000000075 +#define IQ_F_VALUE_PLUS_17_93 15040774 // hz = 17.9300000000075 +#define IQ_F_VALUE_PLUS_17_94 15049162 // hz = 17.9400000000075 +#define IQ_F_VALUE_PLUS_17_95 15057551 // hz = 17.9500000000075 +#define IQ_F_VALUE_PLUS_17_96 15065939 // hz = 17.9600000000075 +#define IQ_F_VALUE_PLUS_17_97 15074328 // hz = 17.9700000000075 +#define IQ_F_VALUE_PLUS_17_98 15082717 // hz = 17.9800000000075 +#define IQ_F_VALUE_PLUS_17_99 15091105 // hz = 17.9900000000075 +#define IQ_F_VALUE_PLUS_18_00 15099494 // hz = 18.0000000000075 +#define IQ_F_VALUE_PLUS_18_01 15107883 // hz = 18.0100000000075 +#define IQ_F_VALUE_PLUS_18_02 15116271 // hz = 18.0200000000075 +#define IQ_F_VALUE_PLUS_18_03 15124660 // hz = 18.0300000000075 +#define IQ_F_VALUE_PLUS_18_04 15133048 // hz = 18.0400000000075 +#define IQ_F_VALUE_PLUS_18_05 15141437 // hz = 18.0500000000075 +#define IQ_F_VALUE_PLUS_18_06 15149826 // hz = 18.0600000000075 +#define IQ_F_VALUE_PLUS_18_07 15158214 // hz = 18.0700000000075 +#define IQ_F_VALUE_PLUS_18_08 15166603 // hz = 18.0800000000075 +#define IQ_F_VALUE_PLUS_18_09 15174991 // hz = 18.0900000000075 +#define IQ_F_VALUE_PLUS_18_10 15183380 // hz = 18.1000000000075 +#define IQ_F_VALUE_PLUS_18_11 15191769 // hz = 18.1100000000075 +#define IQ_F_VALUE_PLUS_18_12 15200157 // hz = 18.1200000000075 +#define IQ_F_VALUE_PLUS_18_13 15208546 // hz = 18.1300000000075 +#define IQ_F_VALUE_PLUS_18_14 15216934 // hz = 18.1400000000075 +#define IQ_F_VALUE_PLUS_18_15 15225323 // hz = 18.1500000000075 +#define IQ_F_VALUE_PLUS_18_16 15233712 // hz = 18.1600000000075 +#define IQ_F_VALUE_PLUS_18_17 15242100 // hz = 18.1700000000075 +#define IQ_F_VALUE_PLUS_18_18 15250489 // hz = 18.1800000000075 +#define IQ_F_VALUE_PLUS_18_19 15258877 // hz = 18.1900000000075 +#define IQ_F_VALUE_PLUS_18_20 15267266 // hz = 18.2000000000075 +#define IQ_F_VALUE_PLUS_18_21 15275655 // hz = 18.2100000000075 +#define IQ_F_VALUE_PLUS_18_22 15284043 // hz = 18.2200000000075 +#define IQ_F_VALUE_PLUS_18_23 15292432 // hz = 18.2300000000075 +#define IQ_F_VALUE_PLUS_18_24 15300820 // hz = 18.2400000000075 +#define IQ_F_VALUE_PLUS_18_25 15309209 // hz = 18.2500000000075 +#define IQ_F_VALUE_PLUS_18_26 15317598 // hz = 18.2600000000075 +#define IQ_F_VALUE_PLUS_18_27 15325986 // hz = 18.2700000000075 +#define IQ_F_VALUE_PLUS_18_28 15334375 // hz = 18.2800000000075 +#define IQ_F_VALUE_PLUS_18_29 15342764 // hz = 18.2900000000076 +#define IQ_F_VALUE_PLUS_18_30 15351152 // hz = 18.3000000000076 +#define IQ_F_VALUE_PLUS_18_31 15359541 // hz = 18.3100000000075 +#define IQ_F_VALUE_PLUS_18_32 15367929 // hz = 18.3200000000076 +#define IQ_F_VALUE_PLUS_18_33 15376318 // hz = 18.3300000000076 +#define IQ_F_VALUE_PLUS_18_34 15384707 // hz = 18.3400000000076 +#define IQ_F_VALUE_PLUS_18_35 15393095 // hz = 18.3500000000076 +#define IQ_F_VALUE_PLUS_18_36 15401484 // hz = 18.3600000000076 +#define IQ_F_VALUE_PLUS_18_37 15409872 // hz = 18.3700000000076 +#define IQ_F_VALUE_PLUS_18_38 15418261 // hz = 18.3800000000076 +#define IQ_F_VALUE_PLUS_18_39 15426650 // hz = 18.3900000000076 +#define IQ_F_VALUE_PLUS_18_40 15435038 // hz = 18.4000000000076 +#define IQ_F_VALUE_PLUS_18_41 15443427 // hz = 18.4100000000076 +#define IQ_F_VALUE_PLUS_18_42 15451815 // hz = 18.4200000000076 +#define IQ_F_VALUE_PLUS_18_43 15460204 // hz = 18.4300000000076 +#define IQ_F_VALUE_PLUS_18_44 15468593 // hz = 18.4400000000076 +#define IQ_F_VALUE_PLUS_18_45 15476981 // hz = 18.4500000000076 +#define IQ_F_VALUE_PLUS_18_46 15485370 // hz = 18.4600000000076 +#define IQ_F_VALUE_PLUS_18_47 15493758 // hz = 18.4700000000076 +#define IQ_F_VALUE_PLUS_18_48 15502147 // hz = 18.4800000000076 +#define IQ_F_VALUE_PLUS_18_49 15510536 // hz = 18.4900000000076 +#define IQ_F_VALUE_PLUS_18_50 15518924 // hz = 18.5000000000076 +#define IQ_F_VALUE_PLUS_18_51 15527313 // hz = 18.5100000000076 +#define IQ_F_VALUE_PLUS_18_52 15535702 // hz = 18.5200000000076 +#define IQ_F_VALUE_PLUS_18_53 15544090 // hz = 18.5300000000076 +#define IQ_F_VALUE_PLUS_18_54 15552479 // hz = 18.5400000000076 +#define IQ_F_VALUE_PLUS_18_55 15560867 // hz = 18.5500000000076 +#define IQ_F_VALUE_PLUS_18_56 15569256 // hz = 18.5600000000076 +#define IQ_F_VALUE_PLUS_18_57 15577645 // hz = 18.5700000000076 +#define IQ_F_VALUE_PLUS_18_58 15586033 // hz = 18.5800000000076 +#define IQ_F_VALUE_PLUS_18_59 15594422 // hz = 18.5900000000076 +#define IQ_F_VALUE_PLUS_18_60 15602810 // hz = 18.6000000000076 +#define IQ_F_VALUE_PLUS_18_61 15611199 // hz = 18.6100000000076 +#define IQ_F_VALUE_PLUS_18_62 15619588 // hz = 18.6200000000076 +#define IQ_F_VALUE_PLUS_18_63 15627976 // hz = 18.6300000000076 +#define IQ_F_VALUE_PLUS_18_64 15636365 // hz = 18.6400000000076 +#define IQ_F_VALUE_PLUS_18_65 15644753 // hz = 18.6500000000076 +#define IQ_F_VALUE_PLUS_18_66 15653142 // hz = 18.6600000000076 +#define IQ_F_VALUE_PLUS_18_67 15661531 // hz = 18.6700000000076 +#define IQ_F_VALUE_PLUS_18_68 15669919 // hz = 18.6800000000076 +#define IQ_F_VALUE_PLUS_18_69 15678308 // hz = 18.6900000000076 +#define IQ_F_VALUE_PLUS_18_70 15686696 // hz = 18.7000000000076 +#define IQ_F_VALUE_PLUS_18_71 15695085 // hz = 18.7100000000076 +#define IQ_F_VALUE_PLUS_18_72 15703474 // hz = 18.7200000000076 +#define IQ_F_VALUE_PLUS_18_73 15711862 // hz = 18.7300000000076 +#define IQ_F_VALUE_PLUS_18_74 15720251 // hz = 18.7400000000076 +#define IQ_F_VALUE_PLUS_18_75 15728640 // hz = 18.7500000000076 +#define IQ_F_VALUE_PLUS_18_76 15737028 // hz = 18.7600000000076 +#define IQ_F_VALUE_PLUS_18_77 15745417 // hz = 18.7700000000076 +#define IQ_F_VALUE_PLUS_18_78 15753805 // hz = 18.7800000000076 +#define IQ_F_VALUE_PLUS_18_79 15762194 // hz = 18.7900000000076 +#define IQ_F_VALUE_PLUS_18_80 15770583 // hz = 18.8000000000076 +#define IQ_F_VALUE_PLUS_18_81 15778971 // hz = 18.8100000000076 +#define IQ_F_VALUE_PLUS_18_82 15787360 // hz = 18.8200000000076 +#define IQ_F_VALUE_PLUS_18_83 15795748 // hz = 18.8300000000076 +#define IQ_F_VALUE_PLUS_18_84 15804137 // hz = 18.8400000000076 +#define IQ_F_VALUE_PLUS_18_85 15812526 // hz = 18.8500000000076 +#define IQ_F_VALUE_PLUS_18_86 15820914 // hz = 18.8600000000076 +#define IQ_F_VALUE_PLUS_18_87 15829303 // hz = 18.8700000000076 +#define IQ_F_VALUE_PLUS_18_88 15837691 // hz = 18.8800000000076 +#define IQ_F_VALUE_PLUS_18_89 15846080 // hz = 18.8900000000076 +#define IQ_F_VALUE_PLUS_18_90 15854469 // hz = 18.9000000000076 +#define IQ_F_VALUE_PLUS_18_91 15862857 // hz = 18.9100000000076 +#define IQ_F_VALUE_PLUS_18_92 15871246 // hz = 18.9200000000076 +#define IQ_F_VALUE_PLUS_18_93 15879634 // hz = 18.9300000000077 +#define IQ_F_VALUE_PLUS_18_94 15888023 // hz = 18.9400000000077 +#define IQ_F_VALUE_PLUS_18_95 15896412 // hz = 18.9500000000076 +#define IQ_F_VALUE_PLUS_18_96 15904800 // hz = 18.9600000000077 +#define IQ_F_VALUE_PLUS_18_97 15913189 // hz = 18.9700000000077 +#define IQ_F_VALUE_PLUS_18_98 15921577 // hz = 18.9800000000077 +#define IQ_F_VALUE_PLUS_18_99 15929966 // hz = 18.9900000000077 +#define IQ_F_VALUE_PLUS_19_00 15938355 // hz = 19.0000000000077 +#define IQ_F_VALUE_PLUS_19_01 15946743 // hz = 19.0100000000077 +#define IQ_F_VALUE_PLUS_19_02 15955132 // hz = 19.0200000000077 +#define IQ_F_VALUE_PLUS_19_03 15963521 // hz = 19.0300000000077 +#define IQ_F_VALUE_PLUS_19_04 15971909 // hz = 19.0400000000077 +#define IQ_F_VALUE_PLUS_19_05 15980298 // hz = 19.0500000000077 +#define IQ_F_VALUE_PLUS_19_06 15988686 // hz = 19.0600000000077 +#define IQ_F_VALUE_PLUS_19_07 15997075 // hz = 19.0700000000077 +#define IQ_F_VALUE_PLUS_19_08 16005464 // hz = 19.0800000000077 +#define IQ_F_VALUE_PLUS_19_09 16013852 // hz = 19.0900000000077 +#define IQ_F_VALUE_PLUS_19_10 16022241 // hz = 19.1000000000077 +#define IQ_F_VALUE_PLUS_19_11 16030629 // hz = 19.1100000000077 +#define IQ_F_VALUE_PLUS_19_12 16039018 // hz = 19.1200000000077 +#define IQ_F_VALUE_PLUS_19_13 16047407 // hz = 19.1300000000077 +#define IQ_F_VALUE_PLUS_19_14 16055795 // hz = 19.1400000000077 +#define IQ_F_VALUE_PLUS_19_15 16064184 // hz = 19.1500000000077 +#define IQ_F_VALUE_PLUS_19_16 16072572 // hz = 19.1600000000077 +#define IQ_F_VALUE_PLUS_19_17 16080961 // hz = 19.1700000000077 +#define IQ_F_VALUE_PLUS_19_18 16089350 // hz = 19.1800000000077 +#define IQ_F_VALUE_PLUS_19_19 16097738 // hz = 19.1900000000077 +#define IQ_F_VALUE_PLUS_19_20 16106127 // hz = 19.2000000000077 +#define IQ_F_VALUE_PLUS_19_21 16114515 // hz = 19.2100000000077 +#define IQ_F_VALUE_PLUS_19_22 16122904 // hz = 19.2200000000077 +#define IQ_F_VALUE_PLUS_19_23 16131293 // hz = 19.2300000000077 +#define IQ_F_VALUE_PLUS_19_24 16139681 // hz = 19.2400000000077 +#define IQ_F_VALUE_PLUS_19_25 16148070 // hz = 19.2500000000077 +#define IQ_F_VALUE_PLUS_19_26 16156459 // hz = 19.2600000000077 +#define IQ_F_VALUE_PLUS_19_27 16164847 // hz = 19.2700000000077 +#define IQ_F_VALUE_PLUS_19_28 16173236 // hz = 19.2800000000077 +#define IQ_F_VALUE_PLUS_19_29 16181624 // hz = 19.2900000000077 +#define IQ_F_VALUE_PLUS_19_30 16190013 // hz = 19.3000000000077 +#define IQ_F_VALUE_PLUS_19_31 16198402 // hz = 19.3100000000077 +#define IQ_F_VALUE_PLUS_19_32 16206790 // hz = 19.3200000000077 +#define IQ_F_VALUE_PLUS_19_33 16215179 // hz = 19.3300000000077 +#define IQ_F_VALUE_PLUS_19_34 16223567 // hz = 19.3400000000077 +#define IQ_F_VALUE_PLUS_19_35 16231956 // hz = 19.3500000000077 +#define IQ_F_VALUE_PLUS_19_36 16240345 // hz = 19.3600000000077 +#define IQ_F_VALUE_PLUS_19_37 16248733 // hz = 19.3700000000077 +#define IQ_F_VALUE_PLUS_19_38 16257122 // hz = 19.3800000000077 +#define IQ_F_VALUE_PLUS_19_39 16265510 // hz = 19.3900000000077 +#define IQ_F_VALUE_PLUS_19_40 16273899 // hz = 19.4000000000077 +#define IQ_F_VALUE_PLUS_19_41 16282288 // hz = 19.4100000000077 +#define IQ_F_VALUE_PLUS_19_42 16290676 // hz = 19.4200000000077 +#define IQ_F_VALUE_PLUS_19_43 16299065 // hz = 19.4300000000077 +#define IQ_F_VALUE_PLUS_19_44 16307453 // hz = 19.4400000000077 +#define IQ_F_VALUE_PLUS_19_45 16315842 // hz = 19.4500000000077 +#define IQ_F_VALUE_PLUS_19_46 16324231 // hz = 19.4600000000077 +#define IQ_F_VALUE_PLUS_19_47 16332619 // hz = 19.4700000000077 +#define IQ_F_VALUE_PLUS_19_48 16341008 // hz = 19.4800000000077 +#define IQ_F_VALUE_PLUS_19_49 16349396 // hz = 19.4900000000077 +#define IQ_F_VALUE_PLUS_19_50 16357785 // hz = 19.5000000000077 +#define IQ_F_VALUE_PLUS_19_51 16366174 // hz = 19.5100000000077 +#define IQ_F_VALUE_PLUS_19_52 16374562 // hz = 19.5200000000077 +#define IQ_F_VALUE_PLUS_19_53 16382951 // hz = 19.5300000000077 +#define IQ_F_VALUE_PLUS_19_54 16391340 // hz = 19.5400000000077 +#define IQ_F_VALUE_PLUS_19_55 16399728 // hz = 19.5500000000077 +#define IQ_F_VALUE_PLUS_19_56 16408117 // hz = 19.5600000000077 +#define IQ_F_VALUE_PLUS_19_57 16416505 // hz = 19.5700000000078 +#define IQ_F_VALUE_PLUS_19_58 16424894 // hz = 19.5800000000078 +#define IQ_F_VALUE_PLUS_19_59 16433283 // hz = 19.5900000000077 +#define IQ_F_VALUE_PLUS_19_60 16441671 // hz = 19.6000000000078 +#define IQ_F_VALUE_PLUS_19_61 16450060 // hz = 19.6100000000078 +#define IQ_F_VALUE_PLUS_19_62 16458448 // hz = 19.6200000000078 +#define IQ_F_VALUE_PLUS_19_63 16466837 // hz = 19.6300000000078 +#define IQ_F_VALUE_PLUS_19_64 16475226 // hz = 19.6400000000078 +#define IQ_F_VALUE_PLUS_19_65 16483614 // hz = 19.6500000000078 +#define IQ_F_VALUE_PLUS_19_66 16492003 // hz = 19.6600000000078 +#define IQ_F_VALUE_PLUS_19_67 16500391 // hz = 19.6700000000078 +#define IQ_F_VALUE_PLUS_19_68 16508780 // hz = 19.6800000000078 +#define IQ_F_VALUE_PLUS_19_69 16517169 // hz = 19.6900000000078 +#define IQ_F_VALUE_PLUS_19_70 16525557 // hz = 19.7000000000078 +#define IQ_F_VALUE_PLUS_19_71 16533946 // hz = 19.7100000000078 +#define IQ_F_VALUE_PLUS_19_72 16542334 // hz = 19.7200000000078 +#define IQ_F_VALUE_PLUS_19_73 16550723 // hz = 19.7300000000078 +#define IQ_F_VALUE_PLUS_19_74 16559112 // hz = 19.7400000000078 +#define IQ_F_VALUE_PLUS_19_75 16567500 // hz = 19.7500000000078 +#define IQ_F_VALUE_PLUS_19_76 16575889 // hz = 19.7600000000078 +#define IQ_F_VALUE_PLUS_19_77 16584278 // hz = 19.7700000000078 +#define IQ_F_VALUE_PLUS_19_78 16592666 // hz = 19.7800000000078 +#define IQ_F_VALUE_PLUS_19_79 16601055 // hz = 19.7900000000078 +#define IQ_F_VALUE_PLUS_19_80 16609443 // hz = 19.8000000000078 +#define IQ_F_VALUE_PLUS_19_81 16617832 // hz = 19.8100000000078 +#define IQ_F_VALUE_PLUS_19_82 16626221 // hz = 19.8200000000078 +#define IQ_F_VALUE_PLUS_19_83 16634609 // hz = 19.8300000000078 +#define IQ_F_VALUE_PLUS_19_84 16642998 // hz = 19.8400000000078 +#define IQ_F_VALUE_PLUS_19_85 16651386 // hz = 19.8500000000078 +#define IQ_F_VALUE_PLUS_19_86 16659775 // hz = 19.8600000000078 +#define IQ_F_VALUE_PLUS_19_87 16668164 // hz = 19.8700000000078 +#define IQ_F_VALUE_PLUS_19_88 16676552 // hz = 19.8800000000078 +#define IQ_F_VALUE_PLUS_19_89 16684941 // hz = 19.8900000000078 +#define IQ_F_VALUE_PLUS_19_90 16693329 // hz = 19.9000000000078 +#define IQ_F_VALUE_PLUS_19_91 16701718 // hz = 19.9100000000078 +#define IQ_F_VALUE_PLUS_19_92 16710107 // hz = 19.9200000000078 +#define IQ_F_VALUE_PLUS_19_93 16718495 // hz = 19.9300000000078 +#define IQ_F_VALUE_PLUS_19_94 16726884 // hz = 19.9400000000078 +#define IQ_F_VALUE_PLUS_19_95 16735272 // hz = 19.9500000000078 +#define IQ_F_VALUE_PLUS_19_96 16743661 // hz = 19.9600000000078 +#define IQ_F_VALUE_PLUS_19_97 16752050 // hz = 19.9700000000078 +#define IQ_F_VALUE_PLUS_19_98 16760438 // hz = 19.9800000000078 +#define IQ_F_VALUE_PLUS_19_99 16768827 // hz = 19.9900000000078 +#define IQ_F_VALUE_PLUS_20_00 16777216 // hz = 20.0000000000078 +#define IQ_F_VALUE_PLUS_20_01 16785604 // hz = 20.0100000000078 +#define IQ_F_VALUE_PLUS_20_02 16793993 // hz = 20.0200000000078 +#define IQ_F_VALUE_PLUS_20_03 16802381 // hz = 20.0300000000078 +#define IQ_F_VALUE_PLUS_20_04 16810770 // hz = 20.0400000000078 +#define IQ_F_VALUE_PLUS_20_05 16819159 // hz = 20.0500000000078 +#define IQ_F_VALUE_PLUS_20_06 16827547 // hz = 20.0600000000078 +#define IQ_F_VALUE_PLUS_20_07 16835936 // hz = 20.0700000000078 +#define IQ_F_VALUE_PLUS_20_08 16844324 // hz = 20.0800000000078 +#define IQ_F_VALUE_PLUS_20_09 16852713 // hz = 20.0900000000078 +#define IQ_F_VALUE_PLUS_20_10 16861102 // hz = 20.1000000000078 +#define IQ_F_VALUE_PLUS_20_11 16869490 // hz = 20.1100000000078 +#define IQ_F_VALUE_PLUS_20_12 16877879 // hz = 20.1200000000078 +#define IQ_F_VALUE_PLUS_20_13 16886267 // hz = 20.1300000000078 +#define IQ_F_VALUE_PLUS_20_14 16894656 // hz = 20.1400000000078 +#define IQ_F_VALUE_PLUS_20_15 16903045 // hz = 20.1500000000078 +#define IQ_F_VALUE_PLUS_20_16 16911433 // hz = 20.1600000000078 +#define IQ_F_VALUE_PLUS_20_17 16919822 // hz = 20.1700000000078 +#define IQ_F_VALUE_PLUS_20_18 16928210 // hz = 20.1800000000078 +#define IQ_F_VALUE_PLUS_20_19 16936599 // hz = 20.1900000000078 +#define IQ_F_VALUE_PLUS_20_20 16944988 // hz = 20.2000000000078 +#define IQ_F_VALUE_PLUS_20_21 16953376 // hz = 20.2100000000079 +#define IQ_F_VALUE_PLUS_20_22 16961765 // hz = 20.2200000000079 +#define IQ_F_VALUE_PLUS_20_23 16970153 // hz = 20.2300000000078 +#define IQ_F_VALUE_PLUS_20_24 16978542 // hz = 20.2400000000079 +#define IQ_F_VALUE_PLUS_20_25 16986931 // hz = 20.2500000000079 +#define IQ_F_VALUE_PLUS_20_26 16995319 // hz = 20.2600000000079 +#define IQ_F_VALUE_PLUS_20_27 17003708 // hz = 20.2700000000079 +#define IQ_F_VALUE_PLUS_20_28 17012097 // hz = 20.2800000000079 +#define IQ_F_VALUE_PLUS_20_29 17020485 // hz = 20.2900000000079 +#define IQ_F_VALUE_PLUS_20_30 17028874 // hz = 20.3000000000079 +#define IQ_F_VALUE_PLUS_20_31 17037262 // hz = 20.3100000000079 +#define IQ_F_VALUE_PLUS_20_32 17045651 // hz = 20.3200000000079 +#define IQ_F_VALUE_PLUS_20_33 17054040 // hz = 20.3300000000079 +#define IQ_F_VALUE_PLUS_20_34 17062428 // hz = 20.3400000000079 +#define IQ_F_VALUE_PLUS_20_35 17070817 // hz = 20.3500000000079 +#define IQ_F_VALUE_PLUS_20_36 17079205 // hz = 20.3600000000079 +#define IQ_F_VALUE_PLUS_20_37 17087594 // hz = 20.3700000000079 +#define IQ_F_VALUE_PLUS_20_38 17095983 // hz = 20.3800000000079 +#define IQ_F_VALUE_PLUS_20_39 17104371 // hz = 20.3900000000079 +#define IQ_F_VALUE_PLUS_20_40 17112760 // hz = 20.4000000000079 +#define IQ_F_VALUE_PLUS_20_41 17121148 // hz = 20.4100000000079 +#define IQ_F_VALUE_PLUS_20_42 17129537 // hz = 20.4200000000079 +#define IQ_F_VALUE_PLUS_20_43 17137926 // hz = 20.4300000000079 +#define IQ_F_VALUE_PLUS_20_44 17146314 // hz = 20.4400000000079 +#define IQ_F_VALUE_PLUS_20_45 17154703 // hz = 20.4500000000079 +#define IQ_F_VALUE_PLUS_20_46 17163091 // hz = 20.4600000000079 +#define IQ_F_VALUE_PLUS_20_47 17171480 // hz = 20.4700000000079 +#define IQ_F_VALUE_PLUS_20_48 17179869 // hz = 20.4800000000079 +#define IQ_F_VALUE_PLUS_20_49 17188257 // hz = 20.4900000000079 +#define IQ_F_VALUE_PLUS_20_50 17196646 // hz = 20.5000000000079 +#define IQ_F_VALUE_PLUS_20_51 17205035 // hz = 20.5100000000079 +#define IQ_F_VALUE_PLUS_20_52 17213423 // hz = 20.5200000000079 +#define IQ_F_VALUE_PLUS_20_53 17221812 // hz = 20.5300000000079 +#define IQ_F_VALUE_PLUS_20_54 17230200 // hz = 20.5400000000079 +#define IQ_F_VALUE_PLUS_20_55 17238589 // hz = 20.5500000000079 +#define IQ_F_VALUE_PLUS_20_56 17246978 // hz = 20.5600000000079 +#define IQ_F_VALUE_PLUS_20_57 17255366 // hz = 20.5700000000079 +#define IQ_F_VALUE_PLUS_20_58 17263755 // hz = 20.5800000000079 +#define IQ_F_VALUE_PLUS_20_59 17272143 // hz = 20.5900000000079 +#define IQ_F_VALUE_PLUS_20_60 17280532 // hz = 20.6000000000079 +#define IQ_F_VALUE_PLUS_20_61 17288921 // hz = 20.6100000000079 +#define IQ_F_VALUE_PLUS_20_62 17297309 // hz = 20.6200000000079 +#define IQ_F_VALUE_PLUS_20_63 17305698 // hz = 20.6300000000079 +#define IQ_F_VALUE_PLUS_20_64 17314086 // hz = 20.6400000000079 +#define IQ_F_VALUE_PLUS_20_65 17322475 // hz = 20.6500000000079 +#define IQ_F_VALUE_PLUS_20_66 17330864 // hz = 20.6600000000079 +#define IQ_F_VALUE_PLUS_20_67 17339252 // hz = 20.6700000000079 +#define IQ_F_VALUE_PLUS_20_68 17347641 // hz = 20.6800000000079 +#define IQ_F_VALUE_PLUS_20_69 17356029 // hz = 20.6900000000079 +#define IQ_F_VALUE_PLUS_20_70 17364418 // hz = 20.7000000000079 +#define IQ_F_VALUE_PLUS_20_71 17372807 // hz = 20.7100000000079 +#define IQ_F_VALUE_PLUS_20_72 17381195 // hz = 20.7200000000079 +#define IQ_F_VALUE_PLUS_20_73 17389584 // hz = 20.7300000000079 +#define IQ_F_VALUE_PLUS_20_74 17397972 // hz = 20.7400000000079 +#define IQ_F_VALUE_PLUS_20_75 17406361 // hz = 20.7500000000079 +#define IQ_F_VALUE_PLUS_20_76 17414750 // hz = 20.7600000000079 +#define IQ_F_VALUE_PLUS_20_77 17423138 // hz = 20.7700000000079 +#define IQ_F_VALUE_PLUS_20_78 17431527 // hz = 20.7800000000079 +#define IQ_F_VALUE_PLUS_20_79 17439916 // hz = 20.7900000000079 +#define IQ_F_VALUE_PLUS_20_80 17448304 // hz = 20.8000000000079 +#define IQ_F_VALUE_PLUS_20_81 17456693 // hz = 20.8100000000079 +#define IQ_F_VALUE_PLUS_20_82 17465081 // hz = 20.8200000000079 +#define IQ_F_VALUE_PLUS_20_83 17473470 // hz = 20.8300000000079 +#define IQ_F_VALUE_PLUS_20_84 17481859 // hz = 20.8400000000079 +#define IQ_F_VALUE_PLUS_20_85 17490247 // hz = 20.850000000008 +#define IQ_F_VALUE_PLUS_20_86 17498636 // hz = 20.860000000008 +#define IQ_F_VALUE_PLUS_20_87 17507024 // hz = 20.8700000000079 +#define IQ_F_VALUE_PLUS_20_88 17515413 // hz = 20.880000000008 +#define IQ_F_VALUE_PLUS_20_89 17523802 // hz = 20.890000000008 +#define IQ_F_VALUE_PLUS_20_90 17532190 // hz = 20.900000000008 +#define IQ_F_VALUE_PLUS_20_91 17540579 // hz = 20.910000000008 +#define IQ_F_VALUE_PLUS_20_92 17548967 // hz = 20.920000000008 +#define IQ_F_VALUE_PLUS_20_93 17557356 // hz = 20.930000000008 +#define IQ_F_VALUE_PLUS_20_94 17565745 // hz = 20.940000000008 +#define IQ_F_VALUE_PLUS_20_95 17574133 // hz = 20.950000000008 +#define IQ_F_VALUE_PLUS_20_96 17582522 // hz = 20.960000000008 +#define IQ_F_VALUE_PLUS_20_97 17590910 // hz = 20.970000000008 +#define IQ_F_VALUE_PLUS_20_98 17599299 // hz = 20.980000000008 +#define IQ_F_VALUE_PLUS_20_99 17607688 // hz = 20.990000000008 +#define IQ_F_VALUE_PLUS_21_00 17616076 // hz = 21.000000000008 +#define IQ_F_VALUE_PLUS_21_01 17624465 // hz = 21.010000000008 +#define IQ_F_VALUE_PLUS_21_02 17632854 // hz = 21.020000000008 +#define IQ_F_VALUE_PLUS_21_03 17641242 // hz = 21.030000000008 +#define IQ_F_VALUE_PLUS_21_04 17649631 // hz = 21.040000000008 +#define IQ_F_VALUE_PLUS_21_05 17658019 // hz = 21.050000000008 +#define IQ_F_VALUE_PLUS_21_06 17666408 // hz = 21.060000000008 +#define IQ_F_VALUE_PLUS_21_07 17674797 // hz = 21.070000000008 +#define IQ_F_VALUE_PLUS_21_08 17683185 // hz = 21.080000000008 +#define IQ_F_VALUE_PLUS_21_09 17691574 // hz = 21.090000000008 +#define IQ_F_VALUE_PLUS_21_10 17699962 // hz = 21.100000000008 +#define IQ_F_VALUE_PLUS_21_11 17708351 // hz = 21.110000000008 +#define IQ_F_VALUE_PLUS_21_12 17716740 // hz = 21.120000000008 +#define IQ_F_VALUE_PLUS_21_13 17725128 // hz = 21.130000000008 +#define IQ_F_VALUE_PLUS_21_14 17733517 // hz = 21.140000000008 +#define IQ_F_VALUE_PLUS_21_15 17741905 // hz = 21.150000000008 +#define IQ_F_VALUE_PLUS_21_16 17750294 // hz = 21.160000000008 +#define IQ_F_VALUE_PLUS_21_17 17758683 // hz = 21.170000000008 +#define IQ_F_VALUE_PLUS_21_18 17767071 // hz = 21.180000000008 +#define IQ_F_VALUE_PLUS_21_19 17775460 // hz = 21.190000000008 +#define IQ_F_VALUE_PLUS_21_20 17783848 // hz = 21.200000000008 +#define IQ_F_VALUE_PLUS_21_21 17792237 // hz = 21.210000000008 +#define IQ_F_VALUE_PLUS_21_22 17800626 // hz = 21.220000000008 +#define IQ_F_VALUE_PLUS_21_23 17809014 // hz = 21.230000000008 +#define IQ_F_VALUE_PLUS_21_24 17817403 // hz = 21.240000000008 +#define IQ_F_VALUE_PLUS_21_25 17825792 // hz = 21.250000000008 +#define IQ_F_VALUE_PLUS_21_26 17834180 // hz = 21.260000000008 +#define IQ_F_VALUE_PLUS_21_27 17842569 // hz = 21.270000000008 +#define IQ_F_VALUE_PLUS_21_28 17850957 // hz = 21.280000000008 +#define IQ_F_VALUE_PLUS_21_29 17859346 // hz = 21.290000000008 +#define IQ_F_VALUE_PLUS_21_30 17867735 // hz = 21.300000000008 +#define IQ_F_VALUE_PLUS_21_31 17876123 // hz = 21.310000000008 +#define IQ_F_VALUE_PLUS_21_32 17884512 // hz = 21.320000000008 +#define IQ_F_VALUE_PLUS_21_33 17892900 // hz = 21.330000000008 +#define IQ_F_VALUE_PLUS_21_34 17901289 // hz = 21.340000000008 +#define IQ_F_VALUE_PLUS_21_35 17909678 // hz = 21.350000000008 +#define IQ_F_VALUE_PLUS_21_36 17918066 // hz = 21.360000000008 +#define IQ_F_VALUE_PLUS_21_37 17926455 // hz = 21.370000000008 +#define IQ_F_VALUE_PLUS_21_38 17934843 // hz = 21.380000000008 +#define IQ_F_VALUE_PLUS_21_39 17943232 // hz = 21.390000000008 +#define IQ_F_VALUE_PLUS_21_40 17951621 // hz = 21.400000000008 +#define IQ_F_VALUE_PLUS_21_41 17960009 // hz = 21.410000000008 +#define IQ_F_VALUE_PLUS_21_42 17968398 // hz = 21.420000000008 +#define IQ_F_VALUE_PLUS_21_43 17976786 // hz = 21.430000000008 +#define IQ_F_VALUE_PLUS_21_44 17985175 // hz = 21.440000000008 +#define IQ_F_VALUE_PLUS_21_45 17993564 // hz = 21.450000000008 +#define IQ_F_VALUE_PLUS_21_46 18001952 // hz = 21.460000000008 +#define IQ_F_VALUE_PLUS_21_47 18010341 // hz = 21.470000000008 +#define IQ_F_VALUE_PLUS_21_48 18018729 // hz = 21.480000000008 +#define IQ_F_VALUE_PLUS_21_49 18027118 // hz = 21.4900000000081 +#define IQ_F_VALUE_PLUS_21_50 18035507 // hz = 21.5000000000081 +#define IQ_F_VALUE_PLUS_21_51 18043895 // hz = 21.510000000008 +#define IQ_F_VALUE_PLUS_21_52 18052284 // hz = 21.5200000000081 +#define IQ_F_VALUE_PLUS_21_53 18060673 // hz = 21.5300000000081 +#define IQ_F_VALUE_PLUS_21_54 18069061 // hz = 21.5400000000081 +#define IQ_F_VALUE_PLUS_21_55 18077450 // hz = 21.5500000000081 +#define IQ_F_VALUE_PLUS_21_56 18085838 // hz = 21.5600000000081 +#define IQ_F_VALUE_PLUS_21_57 18094227 // hz = 21.5700000000081 +#define IQ_F_VALUE_PLUS_21_58 18102616 // hz = 21.5800000000081 +#define IQ_F_VALUE_PLUS_21_59 18111004 // hz = 21.5900000000081 +#define IQ_F_VALUE_PLUS_21_60 18119393 // hz = 21.6000000000081 +#define IQ_F_VALUE_PLUS_21_61 18127781 // hz = 21.6100000000081 +#define IQ_F_VALUE_PLUS_21_62 18136170 // hz = 21.6200000000081 +#define IQ_F_VALUE_PLUS_21_63 18144559 // hz = 21.6300000000081 +#define IQ_F_VALUE_PLUS_21_64 18152947 // hz = 21.6400000000081 +#define IQ_F_VALUE_PLUS_21_65 18161336 // hz = 21.6500000000081 +#define IQ_F_VALUE_PLUS_21_66 18169724 // hz = 21.6600000000081 +#define IQ_F_VALUE_PLUS_21_67 18178113 // hz = 21.6700000000081 +#define IQ_F_VALUE_PLUS_21_68 18186502 // hz = 21.6800000000081 +#define IQ_F_VALUE_PLUS_21_69 18194890 // hz = 21.6900000000081 +#define IQ_F_VALUE_PLUS_21_70 18203279 // hz = 21.7000000000081 +#define IQ_F_VALUE_PLUS_21_71 18211667 // hz = 21.7100000000081 +#define IQ_F_VALUE_PLUS_21_72 18220056 // hz = 21.7200000000081 +#define IQ_F_VALUE_PLUS_21_73 18228445 // hz = 21.7300000000081 +#define IQ_F_VALUE_PLUS_21_74 18236833 // hz = 21.7400000000081 +#define IQ_F_VALUE_PLUS_21_75 18245222 // hz = 21.7500000000081 +#define IQ_F_VALUE_PLUS_21_76 18253611 // hz = 21.7600000000081 +#define IQ_F_VALUE_PLUS_21_77 18261999 // hz = 21.7700000000081 +#define IQ_F_VALUE_PLUS_21_78 18270388 // hz = 21.7800000000081 +#define IQ_F_VALUE_PLUS_21_79 18278776 // hz = 21.7900000000081 +#define IQ_F_VALUE_PLUS_21_80 18287165 // hz = 21.8000000000081 +#define IQ_F_VALUE_PLUS_21_81 18295554 // hz = 21.8100000000081 +#define IQ_F_VALUE_PLUS_21_82 18303942 // hz = 21.8200000000081 +#define IQ_F_VALUE_PLUS_21_83 18312331 // hz = 21.8300000000081 +#define IQ_F_VALUE_PLUS_21_84 18320719 // hz = 21.8400000000081 +#define IQ_F_VALUE_PLUS_21_85 18329108 // hz = 21.8500000000081 +#define IQ_F_VALUE_PLUS_21_86 18337497 // hz = 21.8600000000081 +#define IQ_F_VALUE_PLUS_21_87 18345885 // hz = 21.8700000000081 +#define IQ_F_VALUE_PLUS_21_88 18354274 // hz = 21.8800000000081 +#define IQ_F_VALUE_PLUS_21_89 18362662 // hz = 21.8900000000081 +#define IQ_F_VALUE_PLUS_21_90 18371051 // hz = 21.9000000000081 +#define IQ_F_VALUE_PLUS_21_91 18379440 // hz = 21.9100000000081 +#define IQ_F_VALUE_PLUS_21_92 18387828 // hz = 21.9200000000081 +#define IQ_F_VALUE_PLUS_21_93 18396217 // hz = 21.9300000000081 +#define IQ_F_VALUE_PLUS_21_94 18404605 // hz = 21.9400000000081 +#define IQ_F_VALUE_PLUS_21_95 18412994 // hz = 21.9500000000081 +#define IQ_F_VALUE_PLUS_21_96 18421383 // hz = 21.9600000000081 +#define IQ_F_VALUE_PLUS_21_97 18429771 // hz = 21.9700000000081 +#define IQ_F_VALUE_PLUS_21_98 18438160 // hz = 21.9800000000081 +#define IQ_F_VALUE_PLUS_21_99 18446548 // hz = 21.9900000000081 +#define IQ_F_VALUE_PLUS_22_00 18454937 // hz = 22.0000000000081 +#define IQ_F_VALUE_PLUS_22_01 18463326 // hz = 22.0100000000081 +#define IQ_F_VALUE_PLUS_22_02 18471714 // hz = 22.0200000000081 +#define IQ_F_VALUE_PLUS_22_03 18480103 // hz = 22.0300000000081 +#define IQ_F_VALUE_PLUS_22_04 18488492 // hz = 22.0400000000081 +#define IQ_F_VALUE_PLUS_22_05 18496880 // hz = 22.0500000000081 +#define IQ_F_VALUE_PLUS_22_06 18505269 // hz = 22.0600000000081 +#define IQ_F_VALUE_PLUS_22_07 18513657 // hz = 22.0700000000081 +#define IQ_F_VALUE_PLUS_22_08 18522046 // hz = 22.0800000000081 +#define IQ_F_VALUE_PLUS_22_09 18530435 // hz = 22.0900000000081 +#define IQ_F_VALUE_PLUS_22_10 18538823 // hz = 22.1000000000081 +#define IQ_F_VALUE_PLUS_22_11 18547212 // hz = 22.1100000000081 +#define IQ_F_VALUE_PLUS_22_12 18555600 // hz = 22.1200000000081 +#define IQ_F_VALUE_PLUS_22_13 18563989 // hz = 22.1300000000082 +#define IQ_F_VALUE_PLUS_22_14 18572378 // hz = 22.1400000000082 +#define IQ_F_VALUE_PLUS_22_15 18580766 // hz = 22.1500000000081 +#define IQ_F_VALUE_PLUS_22_16 18589155 // hz = 22.1600000000082 +#define IQ_F_VALUE_PLUS_22_17 18597543 // hz = 22.1700000000082 +#define IQ_F_VALUE_PLUS_22_18 18605932 // hz = 22.1800000000082 +#define IQ_F_VALUE_PLUS_22_19 18614321 // hz = 22.1900000000082 +#define IQ_F_VALUE_PLUS_22_20 18622709 // hz = 22.2000000000082 +#define IQ_F_VALUE_PLUS_22_21 18631098 // hz = 22.2100000000082 +#define IQ_F_VALUE_PLUS_22_22 18639486 // hz = 22.2200000000082 +#define IQ_F_VALUE_PLUS_22_23 18647875 // hz = 22.2300000000082 +#define IQ_F_VALUE_PLUS_22_24 18656264 // hz = 22.2400000000082 +#define IQ_F_VALUE_PLUS_22_25 18664652 // hz = 22.2500000000082 +#define IQ_F_VALUE_PLUS_22_26 18673041 // hz = 22.2600000000082 +#define IQ_F_VALUE_PLUS_22_27 18681430 // hz = 22.2700000000082 +#define IQ_F_VALUE_PLUS_22_28 18689818 // hz = 22.2800000000082 +#define IQ_F_VALUE_PLUS_22_29 18698207 // hz = 22.2900000000082 +#define IQ_F_VALUE_PLUS_22_30 18706595 // hz = 22.3000000000082 +#define IQ_F_VALUE_PLUS_22_31 18714984 // hz = 22.3100000000082 +#define IQ_F_VALUE_PLUS_22_32 18723373 // hz = 22.3200000000082 +#define IQ_F_VALUE_PLUS_22_33 18731761 // hz = 22.3300000000082 +#define IQ_F_VALUE_PLUS_22_34 18740150 // hz = 22.3400000000082 +#define IQ_F_VALUE_PLUS_22_35 18748538 // hz = 22.3500000000082 +#define IQ_F_VALUE_PLUS_22_36 18756927 // hz = 22.3600000000082 +#define IQ_F_VALUE_PLUS_22_37 18765316 // hz = 22.3700000000082 +#define IQ_F_VALUE_PLUS_22_38 18773704 // hz = 22.3800000000082 +#define IQ_F_VALUE_PLUS_22_39 18782093 // hz = 22.3900000000082 +#define IQ_F_VALUE_PLUS_22_40 18790481 // hz = 22.4000000000082 +#define IQ_F_VALUE_PLUS_22_41 18798870 // hz = 22.4100000000082 +#define IQ_F_VALUE_PLUS_22_42 18807259 // hz = 22.4200000000082 +#define IQ_F_VALUE_PLUS_22_43 18815647 // hz = 22.4300000000082 +#define IQ_F_VALUE_PLUS_22_44 18824036 // hz = 22.4400000000082 +#define IQ_F_VALUE_PLUS_22_45 18832424 // hz = 22.4500000000082 +#define IQ_F_VALUE_PLUS_22_46 18840813 // hz = 22.4600000000082 +#define IQ_F_VALUE_PLUS_22_47 18849202 // hz = 22.4700000000082 +#define IQ_F_VALUE_PLUS_22_48 18857590 // hz = 22.4800000000082 +#define IQ_F_VALUE_PLUS_22_49 18865979 // hz = 22.4900000000082 +#define IQ_F_VALUE_PLUS_22_50 18874368 // hz = 22.5000000000082 +#define IQ_F_VALUE_PLUS_22_51 18882756 // hz = 22.5100000000082 +#define IQ_F_VALUE_PLUS_22_52 18891145 // hz = 22.5200000000082 +#define IQ_F_VALUE_PLUS_22_53 18899533 // hz = 22.5300000000082 +#define IQ_F_VALUE_PLUS_22_54 18907922 // hz = 22.5400000000082 +#define IQ_F_VALUE_PLUS_22_55 18916311 // hz = 22.5500000000082 +#define IQ_F_VALUE_PLUS_22_56 18924699 // hz = 22.5600000000082 +#define IQ_F_VALUE_PLUS_22_57 18933088 // hz = 22.5700000000082 +#define IQ_F_VALUE_PLUS_22_58 18941476 // hz = 22.5800000000082 +#define IQ_F_VALUE_PLUS_22_59 18949865 // hz = 22.5900000000082 +#define IQ_F_VALUE_PLUS_22_60 18958254 // hz = 22.6000000000082 +#define IQ_F_VALUE_PLUS_22_61 18966642 // hz = 22.6100000000082 +#define IQ_F_VALUE_PLUS_22_62 18975031 // hz = 22.6200000000082 +#define IQ_F_VALUE_PLUS_22_63 18983419 // hz = 22.6300000000082 +#define IQ_F_VALUE_PLUS_22_64 18991808 // hz = 22.6400000000082 +#define IQ_F_VALUE_PLUS_22_65 19000197 // hz = 22.6500000000082 +#define IQ_F_VALUE_PLUS_22_66 19008585 // hz = 22.6600000000082 +#define IQ_F_VALUE_PLUS_22_67 19016974 // hz = 22.6700000000082 +#define IQ_F_VALUE_PLUS_22_68 19025362 // hz = 22.6800000000082 +#define IQ_F_VALUE_PLUS_22_69 19033751 // hz = 22.6900000000082 +#define IQ_F_VALUE_PLUS_22_70 19042140 // hz = 22.7000000000082 +#define IQ_F_VALUE_PLUS_22_71 19050528 // hz = 22.7100000000082 +#define IQ_F_VALUE_PLUS_22_72 19058917 // hz = 22.7200000000082 +#define IQ_F_VALUE_PLUS_22_73 19067305 // hz = 22.7300000000082 +#define IQ_F_VALUE_PLUS_22_74 19075694 // hz = 22.7400000000082 +#define IQ_F_VALUE_PLUS_22_75 19084083 // hz = 22.7500000000082 +#define IQ_F_VALUE_PLUS_22_76 19092471 // hz = 22.7600000000082 +#define IQ_F_VALUE_PLUS_22_77 19100860 // hz = 22.7700000000083 +#define IQ_F_VALUE_PLUS_22_78 19109249 // hz = 22.7800000000083 +#define IQ_F_VALUE_PLUS_22_79 19117637 // hz = 22.7900000000082 +#define IQ_F_VALUE_PLUS_22_80 19126026 // hz = 22.8000000000083 +#define IQ_F_VALUE_PLUS_22_81 19134414 // hz = 22.8100000000083 +#define IQ_F_VALUE_PLUS_22_82 19142803 // hz = 22.8200000000083 +#define IQ_F_VALUE_PLUS_22_83 19151192 // hz = 22.8300000000083 +#define IQ_F_VALUE_PLUS_22_84 19159580 // hz = 22.8400000000083 +#define IQ_F_VALUE_PLUS_22_85 19167969 // hz = 22.8500000000083 +#define IQ_F_VALUE_PLUS_22_86 19176357 // hz = 22.8600000000083 +#define IQ_F_VALUE_PLUS_22_87 19184746 // hz = 22.8700000000083 +#define IQ_F_VALUE_PLUS_22_88 19193135 // hz = 22.8800000000083 +#define IQ_F_VALUE_PLUS_22_89 19201523 // hz = 22.8900000000083 +#define IQ_F_VALUE_PLUS_22_90 19209912 // hz = 22.9000000000083 +#define IQ_F_VALUE_PLUS_22_91 19218300 // hz = 22.9100000000083 +#define IQ_F_VALUE_PLUS_22_92 19226689 // hz = 22.9200000000083 +#define IQ_F_VALUE_PLUS_22_93 19235078 // hz = 22.9300000000083 +#define IQ_F_VALUE_PLUS_22_94 19243466 // hz = 22.9400000000083 +#define IQ_F_VALUE_PLUS_22_95 19251855 // hz = 22.9500000000083 +#define IQ_F_VALUE_PLUS_22_96 19260243 // hz = 22.9600000000083 +#define IQ_F_VALUE_PLUS_22_97 19268632 // hz = 22.9700000000083 +#define IQ_F_VALUE_PLUS_22_98 19277021 // hz = 22.9800000000083 +#define IQ_F_VALUE_PLUS_22_99 19285409 // hz = 22.9900000000083 +#define IQ_F_VALUE_PLUS_23_00 19293798 // hz = 23.0000000000083 +#define IQ_F_VALUE_PLUS_23_01 19302187 // hz = 23.0100000000083 +#define IQ_F_VALUE_PLUS_23_02 19310575 // hz = 23.0200000000083 +#define IQ_F_VALUE_PLUS_23_03 19318964 // hz = 23.0300000000083 +#define IQ_F_VALUE_PLUS_23_04 19327352 // hz = 23.0400000000083 +#define IQ_F_VALUE_PLUS_23_05 19335741 // hz = 23.0500000000083 +#define IQ_F_VALUE_PLUS_23_06 19344130 // hz = 23.0600000000083 +#define IQ_F_VALUE_PLUS_23_07 19352518 // hz = 23.0700000000083 +#define IQ_F_VALUE_PLUS_23_08 19360907 // hz = 23.0800000000083 +#define IQ_F_VALUE_PLUS_23_09 19369295 // hz = 23.0900000000083 +#define IQ_F_VALUE_PLUS_23_10 19377684 // hz = 23.1000000000083 +#define IQ_F_VALUE_PLUS_23_11 19386073 // hz = 23.1100000000083 +#define IQ_F_VALUE_PLUS_23_12 19394461 // hz = 23.1200000000083 +#define IQ_F_VALUE_PLUS_23_13 19402850 // hz = 23.1300000000083 +#define IQ_F_VALUE_PLUS_23_14 19411238 // hz = 23.1400000000083 +#define IQ_F_VALUE_PLUS_23_15 19419627 // hz = 23.1500000000083 +#define IQ_F_VALUE_PLUS_23_16 19428016 // hz = 23.1600000000083 +#define IQ_F_VALUE_PLUS_23_17 19436404 // hz = 23.1700000000083 +#define IQ_F_VALUE_PLUS_23_18 19444793 // hz = 23.1800000000083 +#define IQ_F_VALUE_PLUS_23_19 19453181 // hz = 23.1900000000083 +#define IQ_F_VALUE_PLUS_23_20 19461570 // hz = 23.2000000000083 +#define IQ_F_VALUE_PLUS_23_21 19469959 // hz = 23.2100000000083 +#define IQ_F_VALUE_PLUS_23_22 19478347 // hz = 23.2200000000083 +#define IQ_F_VALUE_PLUS_23_23 19486736 // hz = 23.2300000000083 +#define IQ_F_VALUE_PLUS_23_24 19495124 // hz = 23.2400000000083 +#define IQ_F_VALUE_PLUS_23_25 19503513 // hz = 23.2500000000083 +#define IQ_F_VALUE_PLUS_23_26 19511902 // hz = 23.2600000000083 +#define IQ_F_VALUE_PLUS_23_27 19520290 // hz = 23.2700000000083 +#define IQ_F_VALUE_PLUS_23_28 19528679 // hz = 23.2800000000083 +#define IQ_F_VALUE_PLUS_23_29 19537068 // hz = 23.2900000000083 +#define IQ_F_VALUE_PLUS_23_30 19545456 // hz = 23.3000000000083 +#define IQ_F_VALUE_PLUS_23_31 19553845 // hz = 23.3100000000083 +#define IQ_F_VALUE_PLUS_23_32 19562233 // hz = 23.3200000000083 +#define IQ_F_VALUE_PLUS_23_33 19570622 // hz = 23.3300000000083 +#define IQ_F_VALUE_PLUS_23_34 19579011 // hz = 23.3400000000083 +#define IQ_F_VALUE_PLUS_23_35 19587399 // hz = 23.3500000000083 +#define IQ_F_VALUE_PLUS_23_36 19595788 // hz = 23.3600000000083 +#define IQ_F_VALUE_PLUS_23_37 19604176 // hz = 23.3700000000083 +#define IQ_F_VALUE_PLUS_23_38 19612565 // hz = 23.3800000000083 +#define IQ_F_VALUE_PLUS_23_39 19620954 // hz = 23.3900000000083 +#define IQ_F_VALUE_PLUS_23_40 19629342 // hz = 23.4000000000083 +#define IQ_F_VALUE_PLUS_23_41 19637731 // hz = 23.4100000000084 +#define IQ_F_VALUE_PLUS_23_42 19646119 // hz = 23.4200000000084 +#define IQ_F_VALUE_PLUS_23_43 19654508 // hz = 23.4300000000083 +#define IQ_F_VALUE_PLUS_23_44 19662897 // hz = 23.4400000000084 +#define IQ_F_VALUE_PLUS_23_45 19671285 // hz = 23.4500000000084 +#define IQ_F_VALUE_PLUS_23_46 19679674 // hz = 23.4600000000084 +#define IQ_F_VALUE_PLUS_23_47 19688062 // hz = 23.4700000000084 +#define IQ_F_VALUE_PLUS_23_48 19696451 // hz = 23.4800000000084 +#define IQ_F_VALUE_PLUS_23_49 19704840 // hz = 23.4900000000084 +#define IQ_F_VALUE_PLUS_23_50 19713228 // hz = 23.5000000000084 +#define IQ_F_VALUE_PLUS_23_51 19721617 // hz = 23.5100000000084 +#define IQ_F_VALUE_PLUS_23_52 19730006 // hz = 23.5200000000084 +#define IQ_F_VALUE_PLUS_23_53 19738394 // hz = 23.5300000000084 +#define IQ_F_VALUE_PLUS_23_54 19746783 // hz = 23.5400000000084 +#define IQ_F_VALUE_PLUS_23_55 19755171 // hz = 23.5500000000084 +#define IQ_F_VALUE_PLUS_23_56 19763560 // hz = 23.5600000000084 +#define IQ_F_VALUE_PLUS_23_57 19771949 // hz = 23.5700000000084 +#define IQ_F_VALUE_PLUS_23_58 19780337 // hz = 23.5800000000084 +#define IQ_F_VALUE_PLUS_23_59 19788726 // hz = 23.5900000000084 +#define IQ_F_VALUE_PLUS_23_60 19797114 // hz = 23.6000000000084 +#define IQ_F_VALUE_PLUS_23_61 19805503 // hz = 23.6100000000084 +#define IQ_F_VALUE_PLUS_23_62 19813892 // hz = 23.6200000000084 +#define IQ_F_VALUE_PLUS_23_63 19822280 // hz = 23.6300000000084 +#define IQ_F_VALUE_PLUS_23_64 19830669 // hz = 23.6400000000084 +#define IQ_F_VALUE_PLUS_23_65 19839057 // hz = 23.6500000000084 +#define IQ_F_VALUE_PLUS_23_66 19847446 // hz = 23.6600000000084 +#define IQ_F_VALUE_PLUS_23_67 19855835 // hz = 23.6700000000084 +#define IQ_F_VALUE_PLUS_23_68 19864223 // hz = 23.6800000000084 +#define IQ_F_VALUE_PLUS_23_69 19872612 // hz = 23.6900000000084 +#define IQ_F_VALUE_PLUS_23_70 19881000 // hz = 23.7000000000084 +#define IQ_F_VALUE_PLUS_23_71 19889389 // hz = 23.7100000000084 +#define IQ_F_VALUE_PLUS_23_72 19897778 // hz = 23.7200000000084 +#define IQ_F_VALUE_PLUS_23_73 19906166 // hz = 23.7300000000084 +#define IQ_F_VALUE_PLUS_23_74 19914555 // hz = 23.7400000000084 +#define IQ_F_VALUE_PLUS_23_75 19922944 // hz = 23.7500000000084 +#define IQ_F_VALUE_PLUS_23_76 19931332 // hz = 23.7600000000084 +#define IQ_F_VALUE_PLUS_23_77 19939721 // hz = 23.7700000000084 +#define IQ_F_VALUE_PLUS_23_78 19948109 // hz = 23.7800000000084 +#define IQ_F_VALUE_PLUS_23_79 19956498 // hz = 23.7900000000084 +#define IQ_F_VALUE_PLUS_23_80 19964887 // hz = 23.8000000000084 +#define IQ_F_VALUE_PLUS_23_81 19973275 // hz = 23.8100000000084 +#define IQ_F_VALUE_PLUS_23_82 19981664 // hz = 23.8200000000084 +#define IQ_F_VALUE_PLUS_23_83 19990052 // hz = 23.8300000000084 +#define IQ_F_VALUE_PLUS_23_84 19998441 // hz = 23.8400000000084 +#define IQ_F_VALUE_PLUS_23_85 20006830 // hz = 23.8500000000084 +#define IQ_F_VALUE_PLUS_23_86 20015218 // hz = 23.8600000000084 +#define IQ_F_VALUE_PLUS_23_87 20023607 // hz = 23.8700000000084 +#define IQ_F_VALUE_PLUS_23_88 20031995 // hz = 23.8800000000084 +#define IQ_F_VALUE_PLUS_23_89 20040384 // hz = 23.8900000000084 +#define IQ_F_VALUE_PLUS_23_90 20048773 // hz = 23.9000000000084 +#define IQ_F_VALUE_PLUS_23_91 20057161 // hz = 23.9100000000084 +#define IQ_F_VALUE_PLUS_23_92 20065550 // hz = 23.9200000000084 +#define IQ_F_VALUE_PLUS_23_93 20073938 // hz = 23.9300000000084 +#define IQ_F_VALUE_PLUS_23_94 20082327 // hz = 23.9400000000084 +#define IQ_F_VALUE_PLUS_23_95 20090716 // hz = 23.9500000000084 +#define IQ_F_VALUE_PLUS_23_96 20099104 // hz = 23.9600000000084 +#define IQ_F_VALUE_PLUS_23_97 20107493 // hz = 23.9700000000084 +#define IQ_F_VALUE_PLUS_23_98 20115881 // hz = 23.9800000000084 +#define IQ_F_VALUE_PLUS_23_99 20124270 // hz = 23.9900000000084 +#define IQ_F_VALUE_PLUS_24_00 20132659 // hz = 24.0000000000084 +#define IQ_F_VALUE_PLUS_24_01 20141047 // hz = 24.0100000000084 +#define IQ_F_VALUE_PLUS_24_02 20149436 // hz = 24.0200000000084 +#define IQ_F_VALUE_PLUS_24_03 20157825 // hz = 24.0300000000084 +#define IQ_F_VALUE_PLUS_24_04 20166213 // hz = 24.0400000000084 +#define IQ_F_VALUE_PLUS_24_05 20174602 // hz = 24.0500000000085 +#define IQ_F_VALUE_PLUS_24_06 20182990 // hz = 24.0600000000085 +#define IQ_F_VALUE_PLUS_24_07 20191379 // hz = 24.0700000000084 +#define IQ_F_VALUE_PLUS_24_08 20199768 // hz = 24.0800000000085 +#define IQ_F_VALUE_PLUS_24_09 20208156 // hz = 24.0900000000085 +#define IQ_F_VALUE_PLUS_24_10 20216545 // hz = 24.1000000000085 +#define IQ_F_VALUE_PLUS_24_11 20224933 // hz = 24.1100000000085 +#define IQ_F_VALUE_PLUS_24_12 20233322 // hz = 24.1200000000085 +#define IQ_F_VALUE_PLUS_24_13 20241711 // hz = 24.1300000000085 +#define IQ_F_VALUE_PLUS_24_14 20250099 // hz = 24.1400000000085 +#define IQ_F_VALUE_PLUS_24_15 20258488 // hz = 24.1500000000085 +#define IQ_F_VALUE_PLUS_24_16 20266876 // hz = 24.1600000000085 +#define IQ_F_VALUE_PLUS_24_17 20275265 // hz = 24.1700000000085 +#define IQ_F_VALUE_PLUS_24_18 20283654 // hz = 24.1800000000085 +#define IQ_F_VALUE_PLUS_24_19 20292042 // hz = 24.1900000000085 +#define IQ_F_VALUE_PLUS_24_20 20300431 // hz = 24.2000000000085 +#define IQ_F_VALUE_PLUS_24_21 20308819 // hz = 24.2100000000085 +#define IQ_F_VALUE_PLUS_24_22 20317208 // hz = 24.2200000000085 +#define IQ_F_VALUE_PLUS_24_23 20325597 // hz = 24.2300000000085 +#define IQ_F_VALUE_PLUS_24_24 20333985 // hz = 24.2400000000085 +#define IQ_F_VALUE_PLUS_24_25 20342374 // hz = 24.2500000000085 +#define IQ_F_VALUE_PLUS_24_26 20350763 // hz = 24.2600000000085 +#define IQ_F_VALUE_PLUS_24_27 20359151 // hz = 24.2700000000085 +#define IQ_F_VALUE_PLUS_24_28 20367540 // hz = 24.2800000000085 +#define IQ_F_VALUE_PLUS_24_29 20375928 // hz = 24.2900000000085 +#define IQ_F_VALUE_PLUS_24_30 20384317 // hz = 24.3000000000085 +#define IQ_F_VALUE_PLUS_24_31 20392706 // hz = 24.3100000000085 +#define IQ_F_VALUE_PLUS_24_32 20401094 // hz = 24.3200000000085 +#define IQ_F_VALUE_PLUS_24_33 20409483 // hz = 24.3300000000085 +#define IQ_F_VALUE_PLUS_24_34 20417871 // hz = 24.3400000000085 +#define IQ_F_VALUE_PLUS_24_35 20426260 // hz = 24.3500000000085 +#define IQ_F_VALUE_PLUS_24_36 20434649 // hz = 24.3600000000085 +#define IQ_F_VALUE_PLUS_24_37 20443037 // hz = 24.3700000000085 +#define IQ_F_VALUE_PLUS_24_38 20451426 // hz = 24.3800000000085 +#define IQ_F_VALUE_PLUS_24_39 20459814 // hz = 24.3900000000085 +#define IQ_F_VALUE_PLUS_24_40 20468203 // hz = 24.4000000000085 +#define IQ_F_VALUE_PLUS_24_41 20476592 // hz = 24.4100000000085 +#define IQ_F_VALUE_PLUS_24_42 20484980 // hz = 24.4200000000085 +#define IQ_F_VALUE_PLUS_24_43 20493369 // hz = 24.4300000000085 +#define IQ_F_VALUE_PLUS_24_44 20501757 // hz = 24.4400000000085 +#define IQ_F_VALUE_PLUS_24_45 20510146 // hz = 24.4500000000085 +#define IQ_F_VALUE_PLUS_24_46 20518535 // hz = 24.4600000000085 +#define IQ_F_VALUE_PLUS_24_47 20526923 // hz = 24.4700000000085 +#define IQ_F_VALUE_PLUS_24_48 20535312 // hz = 24.4800000000085 +#define IQ_F_VALUE_PLUS_24_49 20543700 // hz = 24.4900000000085 +#define IQ_F_VALUE_PLUS_24_50 20552089 // hz = 24.5000000000085 +#define IQ_F_VALUE_PLUS_24_51 20560478 // hz = 24.5100000000085 +#define IQ_F_VALUE_PLUS_24_52 20568866 // hz = 24.5200000000085 +#define IQ_F_VALUE_PLUS_24_53 20577255 // hz = 24.5300000000085 +#define IQ_F_VALUE_PLUS_24_54 20585644 // hz = 24.5400000000085 +#define IQ_F_VALUE_PLUS_24_55 20594032 // hz = 24.5500000000085 +#define IQ_F_VALUE_PLUS_24_56 20602421 // hz = 24.5600000000085 +#define IQ_F_VALUE_PLUS_24_57 20610809 // hz = 24.5700000000085 +#define IQ_F_VALUE_PLUS_24_58 20619198 // hz = 24.5800000000085 +#define IQ_F_VALUE_PLUS_24_59 20627587 // hz = 24.5900000000085 +#define IQ_F_VALUE_PLUS_24_60 20635975 // hz = 24.6000000000085 +#define IQ_F_VALUE_PLUS_24_61 20644364 // hz = 24.6100000000085 +#define IQ_F_VALUE_PLUS_24_62 20652752 // hz = 24.6200000000085 +#define IQ_F_VALUE_PLUS_24_63 20661141 // hz = 24.6300000000085 +#define IQ_F_VALUE_PLUS_24_64 20669530 // hz = 24.6400000000085 +#define IQ_F_VALUE_PLUS_24_65 20677918 // hz = 24.6500000000085 +#define IQ_F_VALUE_PLUS_24_66 20686307 // hz = 24.6600000000085 +#define IQ_F_VALUE_PLUS_24_67 20694695 // hz = 24.6700000000085 +#define IQ_F_VALUE_PLUS_24_68 20703084 // hz = 24.6800000000085 +#define IQ_F_VALUE_PLUS_24_69 20711473 // hz = 24.6900000000086 +#define IQ_F_VALUE_PLUS_24_70 20719861 // hz = 24.7000000000086 +#define IQ_F_VALUE_PLUS_24_71 20728250 // hz = 24.7100000000085 +#define IQ_F_VALUE_PLUS_24_72 20736638 // hz = 24.7200000000086 +#define IQ_F_VALUE_PLUS_24_73 20745027 // hz = 24.7300000000086 +#define IQ_F_VALUE_PLUS_24_74 20753416 // hz = 24.7400000000086 +#define IQ_F_VALUE_PLUS_24_75 20761804 // hz = 24.7500000000086 +#define IQ_F_VALUE_PLUS_24_76 20770193 // hz = 24.7600000000086 +#define IQ_F_VALUE_PLUS_24_77 20778582 // hz = 24.7700000000086 +#define IQ_F_VALUE_PLUS_24_78 20786970 // hz = 24.7800000000086 +#define IQ_F_VALUE_PLUS_24_79 20795359 // hz = 24.7900000000086 +#define IQ_F_VALUE_PLUS_24_80 20803747 // hz = 24.8000000000086 +#define IQ_F_VALUE_PLUS_24_81 20812136 // hz = 24.8100000000086 +#define IQ_F_VALUE_PLUS_24_82 20820525 // hz = 24.8200000000086 +#define IQ_F_VALUE_PLUS_24_83 20828913 // hz = 24.8300000000086 +#define IQ_F_VALUE_PLUS_24_84 20837302 // hz = 24.8400000000086 +#define IQ_F_VALUE_PLUS_24_85 20845690 // hz = 24.8500000000086 +#define IQ_F_VALUE_PLUS_24_86 20854079 // hz = 24.8600000000086 +#define IQ_F_VALUE_PLUS_24_87 20862468 // hz = 24.8700000000086 +#define IQ_F_VALUE_PLUS_24_88 20870856 // hz = 24.8800000000086 +#define IQ_F_VALUE_PLUS_24_89 20879245 // hz = 24.8900000000086 +#define IQ_F_VALUE_PLUS_24_90 20887633 // hz = 24.9000000000086 +#define IQ_F_VALUE_PLUS_24_91 20896022 // hz = 24.9100000000086 +#define IQ_F_VALUE_PLUS_24_92 20904411 // hz = 24.9200000000086 +#define IQ_F_VALUE_PLUS_24_93 20912799 // hz = 24.9300000000086 +#define IQ_F_VALUE_PLUS_24_94 20921188 // hz = 24.9400000000086 +#define IQ_F_VALUE_PLUS_24_95 20929576 // hz = 24.9500000000086 +#define IQ_F_VALUE_PLUS_24_96 20937965 // hz = 24.9600000000086 +#define IQ_F_VALUE_PLUS_24_97 20946354 // hz = 24.9700000000086 +#define IQ_F_VALUE_PLUS_24_98 20954742 // hz = 24.9800000000086 +#define IQ_F_VALUE_PLUS_24_99 20963131 // hz = 24.9900000000086 +#define IQ_F_VALUE_PLUS_25_00 20971520 // hz = 25.0000000000086 +#define IQ_F_VALUE_PLUS_25_01 20979908 // hz = 25.0100000000086 +#define IQ_F_VALUE_PLUS_25_02 20988297 // hz = 25.0200000000086 +#define IQ_F_VALUE_PLUS_25_03 20996685 // hz = 25.0300000000086 +#define IQ_F_VALUE_PLUS_25_04 21005074 // hz = 25.0400000000086 +#define IQ_F_VALUE_PLUS_25_05 21013463 // hz = 25.0500000000086 +#define IQ_F_VALUE_PLUS_25_06 21021851 // hz = 25.0600000000086 +#define IQ_F_VALUE_PLUS_25_07 21030240 // hz = 25.0700000000086 +#define IQ_F_VALUE_PLUS_25_08 21038628 // hz = 25.0800000000086 +#define IQ_F_VALUE_PLUS_25_09 21047017 // hz = 25.0900000000086 +#define IQ_F_VALUE_PLUS_25_10 21055406 // hz = 25.1000000000086 +#define IQ_F_VALUE_PLUS_25_11 21063794 // hz = 25.1100000000086 +#define IQ_F_VALUE_PLUS_25_12 21072183 // hz = 25.1200000000086 +#define IQ_F_VALUE_PLUS_25_13 21080571 // hz = 25.1300000000086 +#define IQ_F_VALUE_PLUS_25_14 21088960 // hz = 25.1400000000086 +#define IQ_F_VALUE_PLUS_25_15 21097349 // hz = 25.1500000000086 +#define IQ_F_VALUE_PLUS_25_16 21105737 // hz = 25.1600000000086 +#define IQ_F_VALUE_PLUS_25_17 21114126 // hz = 25.1700000000086 +#define IQ_F_VALUE_PLUS_25_18 21122514 // hz = 25.1800000000086 +#define IQ_F_VALUE_PLUS_25_19 21130903 // hz = 25.1900000000086 +#define IQ_F_VALUE_PLUS_25_20 21139292 // hz = 25.2000000000086 +#define IQ_F_VALUE_PLUS_25_21 21147680 // hz = 25.2100000000086 +#define IQ_F_VALUE_PLUS_25_22 21156069 // hz = 25.2200000000086 +#define IQ_F_VALUE_PLUS_25_23 21164457 // hz = 25.2300000000086 +#define IQ_F_VALUE_PLUS_25_24 21172846 // hz = 25.2400000000086 +#define IQ_F_VALUE_PLUS_25_25 21181235 // hz = 25.2500000000086 +#define IQ_F_VALUE_PLUS_25_26 21189623 // hz = 25.2600000000086 +#define IQ_F_VALUE_PLUS_25_27 21198012 // hz = 25.2700000000086 +#define IQ_F_VALUE_PLUS_25_28 21206401 // hz = 25.2800000000086 +#define IQ_F_VALUE_PLUS_25_29 21214789 // hz = 25.2900000000086 +#define IQ_F_VALUE_PLUS_25_30 21223178 // hz = 25.3000000000086 +#define IQ_F_VALUE_PLUS_25_31 21231566 // hz = 25.3100000000086 +#define IQ_F_VALUE_PLUS_25_32 21239955 // hz = 25.3200000000086 +#define IQ_F_VALUE_PLUS_25_33 21248344 // hz = 25.3300000000087 +#define IQ_F_VALUE_PLUS_25_34 21256732 // hz = 25.3400000000087 +#define IQ_F_VALUE_PLUS_25_35 21265121 // hz = 25.3500000000086 +#define IQ_F_VALUE_PLUS_25_36 21273509 // hz = 25.3600000000087 +#define IQ_F_VALUE_PLUS_25_37 21281898 // hz = 25.3700000000087 +#define IQ_F_VALUE_PLUS_25_38 21290287 // hz = 25.3800000000087 +#define IQ_F_VALUE_PLUS_25_39 21298675 // hz = 25.3900000000087 +#define IQ_F_VALUE_PLUS_25_40 21307064 // hz = 25.4000000000087 +#define IQ_F_VALUE_PLUS_25_41 21315452 // hz = 25.4100000000087 +#define IQ_F_VALUE_PLUS_25_42 21323841 // hz = 25.4200000000087 +#define IQ_F_VALUE_PLUS_25_43 21332230 // hz = 25.4300000000087 +#define IQ_F_VALUE_PLUS_25_44 21340618 // hz = 25.4400000000087 +#define IQ_F_VALUE_PLUS_25_45 21349007 // hz = 25.4500000000087 +#define IQ_F_VALUE_PLUS_25_46 21357395 // hz = 25.4600000000087 +#define IQ_F_VALUE_PLUS_25_47 21365784 // hz = 25.4700000000087 +#define IQ_F_VALUE_PLUS_25_48 21374173 // hz = 25.4800000000087 +#define IQ_F_VALUE_PLUS_25_49 21382561 // hz = 25.4900000000087 +#define IQ_F_VALUE_PLUS_25_50 21390950 // hz = 25.5000000000087 +#define IQ_F_VALUE_PLUS_25_51 21399339 // hz = 25.5100000000087 +#define IQ_F_VALUE_PLUS_25_52 21407727 // hz = 25.5200000000087 +#define IQ_F_VALUE_PLUS_25_53 21416116 // hz = 25.5300000000087 +#define IQ_F_VALUE_PLUS_25_54 21424504 // hz = 25.5400000000087 +#define IQ_F_VALUE_PLUS_25_55 21432893 // hz = 25.5500000000087 +#define IQ_F_VALUE_PLUS_25_56 21441282 // hz = 25.5600000000087 +#define IQ_F_VALUE_PLUS_25_57 21449670 // hz = 25.5700000000087 +#define IQ_F_VALUE_PLUS_25_58 21458059 // hz = 25.5800000000087 +#define IQ_F_VALUE_PLUS_25_59 21466447 // hz = 25.5900000000087 +#define IQ_F_VALUE_PLUS_25_60 21474836 // hz = 25.6000000000087 +#define IQ_F_VALUE_PLUS_25_61 21483225 // hz = 25.6100000000087 +#define IQ_F_VALUE_PLUS_25_62 21491613 // hz = 25.6200000000087 +#define IQ_F_VALUE_PLUS_25_63 21500002 // hz = 25.6300000000087 +#define IQ_F_VALUE_PLUS_25_64 21508390 // hz = 25.6400000000087 +#define IQ_F_VALUE_PLUS_25_65 21516779 // hz = 25.6500000000087 +#define IQ_F_VALUE_PLUS_25_66 21525168 // hz = 25.6600000000087 +#define IQ_F_VALUE_PLUS_25_67 21533556 // hz = 25.6700000000087 +#define IQ_F_VALUE_PLUS_25_68 21541945 // hz = 25.6800000000087 +#define IQ_F_VALUE_PLUS_25_69 21550333 // hz = 25.6900000000087 +#define IQ_F_VALUE_PLUS_25_70 21558722 // hz = 25.7000000000087 +#define IQ_F_VALUE_PLUS_25_71 21567111 // hz = 25.7100000000087 +#define IQ_F_VALUE_PLUS_25_72 21575499 // hz = 25.7200000000087 +#define IQ_F_VALUE_PLUS_25_73 21583888 // hz = 25.7300000000087 +#define IQ_F_VALUE_PLUS_25_74 21592276 // hz = 25.7400000000087 +#define IQ_F_VALUE_PLUS_25_75 21600665 // hz = 25.7500000000087 +#define IQ_F_VALUE_PLUS_25_76 21609054 // hz = 25.7600000000087 +#define IQ_F_VALUE_PLUS_25_77 21617442 // hz = 25.7700000000087 +#define IQ_F_VALUE_PLUS_25_78 21625831 // hz = 25.7800000000087 +#define IQ_F_VALUE_PLUS_25_79 21634220 // hz = 25.7900000000087 +#define IQ_F_VALUE_PLUS_25_80 21642608 // hz = 25.8000000000087 +#define IQ_F_VALUE_PLUS_25_81 21650997 // hz = 25.8100000000087 +#define IQ_F_VALUE_PLUS_25_82 21659385 // hz = 25.8200000000087 +#define IQ_F_VALUE_PLUS_25_83 21667774 // hz = 25.8300000000087 +#define IQ_F_VALUE_PLUS_25_84 21676163 // hz = 25.8400000000087 +#define IQ_F_VALUE_PLUS_25_85 21684551 // hz = 25.8500000000087 +#define IQ_F_VALUE_PLUS_25_86 21692940 // hz = 25.8600000000087 +#define IQ_F_VALUE_PLUS_25_87 21701328 // hz = 25.8700000000087 +#define IQ_F_VALUE_PLUS_25_88 21709717 // hz = 25.8800000000087 +#define IQ_F_VALUE_PLUS_25_89 21718106 // hz = 25.8900000000087 +#define IQ_F_VALUE_PLUS_25_90 21726494 // hz = 25.9000000000087 +#define IQ_F_VALUE_PLUS_25_91 21734883 // hz = 25.9100000000087 +#define IQ_F_VALUE_PLUS_25_92 21743271 // hz = 25.9200000000087 +#define IQ_F_VALUE_PLUS_25_93 21751660 // hz = 25.9300000000087 +#define IQ_F_VALUE_PLUS_25_94 21760049 // hz = 25.9400000000087 +#define IQ_F_VALUE_PLUS_25_95 21768437 // hz = 25.9500000000087 +#define IQ_F_VALUE_PLUS_25_96 21776826 // hz = 25.9600000000087 +#define IQ_F_VALUE_PLUS_25_97 21785214 // hz = 25.9700000000088 +#define IQ_F_VALUE_PLUS_25_98 21793603 // hz = 25.9800000000088 +#define IQ_F_VALUE_PLUS_25_99 21801992 // hz = 25.9900000000087 +#define IQ_F_VALUE_PLUS_26_00 21810380 // hz = 26.0000000000088 +#define IQ_F_VALUE_PLUS_26_01 21818769 // hz = 26.0100000000088 +#define IQ_F_VALUE_PLUS_26_02 21827158 // hz = 26.0200000000088 +#define IQ_F_VALUE_PLUS_26_03 21835546 // hz = 26.0300000000088 +#define IQ_F_VALUE_PLUS_26_04 21843935 // hz = 26.0400000000088 +#define IQ_F_VALUE_PLUS_26_05 21852323 // hz = 26.0500000000088 +#define IQ_F_VALUE_PLUS_26_06 21860712 // hz = 26.0600000000088 +#define IQ_F_VALUE_PLUS_26_07 21869101 // hz = 26.0700000000088 +#define IQ_F_VALUE_PLUS_26_08 21877489 // hz = 26.0800000000088 +#define IQ_F_VALUE_PLUS_26_09 21885878 // hz = 26.0900000000088 +#define IQ_F_VALUE_PLUS_26_10 21894266 // hz = 26.1000000000088 +#define IQ_F_VALUE_PLUS_26_11 21902655 // hz = 26.1100000000088 +#define IQ_F_VALUE_PLUS_26_12 21911044 // hz = 26.1200000000088 +#define IQ_F_VALUE_PLUS_26_13 21919432 // hz = 26.1300000000088 +#define IQ_F_VALUE_PLUS_26_14 21927821 // hz = 26.1400000000088 +#define IQ_F_VALUE_PLUS_26_15 21936209 // hz = 26.1500000000088 +#define IQ_F_VALUE_PLUS_26_16 21944598 // hz = 26.1600000000088 +#define IQ_F_VALUE_PLUS_26_17 21952987 // hz = 26.1700000000088 +#define IQ_F_VALUE_PLUS_26_18 21961375 // hz = 26.1800000000088 +#define IQ_F_VALUE_PLUS_26_19 21969764 // hz = 26.1900000000088 +#define IQ_F_VALUE_PLUS_26_20 21978152 // hz = 26.2000000000088 +#define IQ_F_VALUE_PLUS_26_21 21986541 // hz = 26.2100000000088 +#define IQ_F_VALUE_PLUS_26_22 21994930 // hz = 26.2200000000088 +#define IQ_F_VALUE_PLUS_26_23 22003318 // hz = 26.2300000000088 +#define IQ_F_VALUE_PLUS_26_24 22011707 // hz = 26.2400000000088 +#define IQ_F_VALUE_PLUS_26_25 22020096 // hz = 26.2500000000088 +#define IQ_F_VALUE_PLUS_26_26 22028484 // hz = 26.2600000000088 +#define IQ_F_VALUE_PLUS_26_27 22036873 // hz = 26.2700000000088 +#define IQ_F_VALUE_PLUS_26_28 22045261 // hz = 26.2800000000088 +#define IQ_F_VALUE_PLUS_26_29 22053650 // hz = 26.2900000000088 +#define IQ_F_VALUE_PLUS_26_30 22062039 // hz = 26.3000000000088 +#define IQ_F_VALUE_PLUS_26_31 22070427 // hz = 26.3100000000088 +#define IQ_F_VALUE_PLUS_26_32 22078816 // hz = 26.3200000000088 +#define IQ_F_VALUE_PLUS_26_33 22087204 // hz = 26.3300000000088 +#define IQ_F_VALUE_PLUS_26_34 22095593 // hz = 26.3400000000088 +#define IQ_F_VALUE_PLUS_26_35 22103982 // hz = 26.3500000000088 +#define IQ_F_VALUE_PLUS_26_36 22112370 // hz = 26.3600000000088 +#define IQ_F_VALUE_PLUS_26_37 22120759 // hz = 26.3700000000088 +#define IQ_F_VALUE_PLUS_26_38 22129147 // hz = 26.3800000000088 +#define IQ_F_VALUE_PLUS_26_39 22137536 // hz = 26.3900000000088 +#define IQ_F_VALUE_PLUS_26_40 22145925 // hz = 26.4000000000088 +#define IQ_F_VALUE_PLUS_26_41 22154313 // hz = 26.4100000000088 +#define IQ_F_VALUE_PLUS_26_42 22162702 // hz = 26.4200000000088 +#define IQ_F_VALUE_PLUS_26_43 22171090 // hz = 26.4300000000088 +#define IQ_F_VALUE_PLUS_26_44 22179479 // hz = 26.4400000000088 +#define IQ_F_VALUE_PLUS_26_45 22187868 // hz = 26.4500000000088 +#define IQ_F_VALUE_PLUS_26_46 22196256 // hz = 26.4600000000088 +#define IQ_F_VALUE_PLUS_26_47 22204645 // hz = 26.4700000000088 +#define IQ_F_VALUE_PLUS_26_48 22213033 // hz = 26.4800000000088 +#define IQ_F_VALUE_PLUS_26_49 22221422 // hz = 26.4900000000088 +#define IQ_F_VALUE_PLUS_26_50 22229811 // hz = 26.5000000000088 +#define IQ_F_VALUE_PLUS_26_51 22238199 // hz = 26.5100000000088 +#define IQ_F_VALUE_PLUS_26_52 22246588 // hz = 26.5200000000088 +#define IQ_F_VALUE_PLUS_26_53 22254977 // hz = 26.5300000000088 +#define IQ_F_VALUE_PLUS_26_54 22263365 // hz = 26.5400000000088 +#define IQ_F_VALUE_PLUS_26_55 22271754 // hz = 26.5500000000088 +#define IQ_F_VALUE_PLUS_26_56 22280142 // hz = 26.5600000000088 +#define IQ_F_VALUE_PLUS_26_57 22288531 // hz = 26.5700000000088 +#define IQ_F_VALUE_PLUS_26_58 22296920 // hz = 26.5800000000088 +#define IQ_F_VALUE_PLUS_26_59 22305308 // hz = 26.5900000000088 +#define IQ_F_VALUE_PLUS_26_60 22313697 // hz = 26.6000000000088 +#define IQ_F_VALUE_PLUS_26_61 22322085 // hz = 26.6100000000089 +#define IQ_F_VALUE_PLUS_26_62 22330474 // hz = 26.6200000000089 +#define IQ_F_VALUE_PLUS_26_63 22338863 // hz = 26.6300000000088 +#define IQ_F_VALUE_PLUS_26_64 22347251 // hz = 26.6400000000089 +#define IQ_F_VALUE_PLUS_26_65 22355640 // hz = 26.6500000000089 +#define IQ_F_VALUE_PLUS_26_66 22364028 // hz = 26.6600000000089 +#define IQ_F_VALUE_PLUS_26_67 22372417 // hz = 26.6700000000089 +#define IQ_F_VALUE_PLUS_26_68 22380806 // hz = 26.6800000000089 +#define IQ_F_VALUE_PLUS_26_69 22389194 // hz = 26.6900000000089 +#define IQ_F_VALUE_PLUS_26_70 22397583 // hz = 26.7000000000089 +#define IQ_F_VALUE_PLUS_26_71 22405971 // hz = 26.7100000000089 +#define IQ_F_VALUE_PLUS_26_72 22414360 // hz = 26.7200000000089 +#define IQ_F_VALUE_PLUS_26_73 22422749 // hz = 26.7300000000089 +#define IQ_F_VALUE_PLUS_26_74 22431137 // hz = 26.7400000000089 +#define IQ_F_VALUE_PLUS_26_75 22439526 // hz = 26.7500000000089 +#define IQ_F_VALUE_PLUS_26_76 22447915 // hz = 26.7600000000089 +#define IQ_F_VALUE_PLUS_26_77 22456303 // hz = 26.7700000000089 +#define IQ_F_VALUE_PLUS_26_78 22464692 // hz = 26.7800000000089 +#define IQ_F_VALUE_PLUS_26_79 22473080 // hz = 26.7900000000089 +#define IQ_F_VALUE_PLUS_26_80 22481469 // hz = 26.8000000000089 +#define IQ_F_VALUE_PLUS_26_81 22489858 // hz = 26.8100000000089 +#define IQ_F_VALUE_PLUS_26_82 22498246 // hz = 26.8200000000089 +#define IQ_F_VALUE_PLUS_26_83 22506635 // hz = 26.8300000000089 +#define IQ_F_VALUE_PLUS_26_84 22515023 // hz = 26.8400000000089 +#define IQ_F_VALUE_PLUS_26_85 22523412 // hz = 26.8500000000089 +#define IQ_F_VALUE_PLUS_26_86 22531801 // hz = 26.8600000000089 +#define IQ_F_VALUE_PLUS_26_87 22540189 // hz = 26.8700000000089 +#define IQ_F_VALUE_PLUS_26_88 22548578 // hz = 26.8800000000089 +#define IQ_F_VALUE_PLUS_26_89 22556966 // hz = 26.8900000000089 +#define IQ_F_VALUE_PLUS_26_90 22565355 // hz = 26.9000000000089 +#define IQ_F_VALUE_PLUS_26_91 22573744 // hz = 26.9100000000089 +#define IQ_F_VALUE_PLUS_26_92 22582132 // hz = 26.9200000000089 +#define IQ_F_VALUE_PLUS_26_93 22590521 // hz = 26.9300000000089 +#define IQ_F_VALUE_PLUS_26_94 22598909 // hz = 26.9400000000089 +#define IQ_F_VALUE_PLUS_26_95 22607298 // hz = 26.9500000000089 +#define IQ_F_VALUE_PLUS_26_96 22615687 // hz = 26.9600000000089 +#define IQ_F_VALUE_PLUS_26_97 22624075 // hz = 26.9700000000089 +#define IQ_F_VALUE_PLUS_26_98 22632464 // hz = 26.9800000000089 +#define IQ_F_VALUE_PLUS_26_99 22640852 // hz = 26.9900000000089 +#define IQ_F_VALUE_PLUS_27_00 22649241 // hz = 27.0000000000089 +#define IQ_F_VALUE_PLUS_27_01 22657630 // hz = 27.0100000000089 +#define IQ_F_VALUE_PLUS_27_02 22666018 // hz = 27.0200000000089 +#define IQ_F_VALUE_PLUS_27_03 22674407 // hz = 27.0300000000089 +#define IQ_F_VALUE_PLUS_27_04 22682796 // hz = 27.0400000000089 +#define IQ_F_VALUE_PLUS_27_05 22691184 // hz = 27.0500000000089 +#define IQ_F_VALUE_PLUS_27_06 22699573 // hz = 27.0600000000089 +#define IQ_F_VALUE_PLUS_27_07 22707961 // hz = 27.0700000000089 +#define IQ_F_VALUE_PLUS_27_08 22716350 // hz = 27.0800000000089 +#define IQ_F_VALUE_PLUS_27_09 22724739 // hz = 27.0900000000089 +#define IQ_F_VALUE_PLUS_27_10 22733127 // hz = 27.1000000000089 +#define IQ_F_VALUE_PLUS_27_11 22741516 // hz = 27.1100000000089 +#define IQ_F_VALUE_PLUS_27_12 22749904 // hz = 27.1200000000089 +#define IQ_F_VALUE_PLUS_27_13 22758293 // hz = 27.1300000000089 +#define IQ_F_VALUE_PLUS_27_14 22766682 // hz = 27.1400000000089 +#define IQ_F_VALUE_PLUS_27_15 22775070 // hz = 27.1500000000089 +#define IQ_F_VALUE_PLUS_27_16 22783459 // hz = 27.1600000000089 +#define IQ_F_VALUE_PLUS_27_17 22791847 // hz = 27.1700000000089 +#define IQ_F_VALUE_PLUS_27_18 22800236 // hz = 27.1800000000089 +#define IQ_F_VALUE_PLUS_27_19 22808625 // hz = 27.1900000000089 +#define IQ_F_VALUE_PLUS_27_20 22817013 // hz = 27.2000000000089 +#define IQ_F_VALUE_PLUS_27_21 22825402 // hz = 27.2100000000089 +#define IQ_F_VALUE_PLUS_27_22 22833790 // hz = 27.2200000000089 +#define IQ_F_VALUE_PLUS_27_23 22842179 // hz = 27.2300000000089 +#define IQ_F_VALUE_PLUS_27_24 22850568 // hz = 27.2400000000089 +#define IQ_F_VALUE_PLUS_27_25 22858956 // hz = 27.250000000009 +#define IQ_F_VALUE_PLUS_27_26 22867345 // hz = 27.260000000009 +#define IQ_F_VALUE_PLUS_27_27 22875734 // hz = 27.2700000000089 +#define IQ_F_VALUE_PLUS_27_28 22884122 // hz = 27.280000000009 +#define IQ_F_VALUE_PLUS_27_29 22892511 // hz = 27.290000000009 +#define IQ_F_VALUE_PLUS_27_30 22900899 // hz = 27.300000000009 +#define IQ_F_VALUE_PLUS_27_31 22909288 // hz = 27.310000000009 +#define IQ_F_VALUE_PLUS_27_32 22917677 // hz = 27.320000000009 +#define IQ_F_VALUE_PLUS_27_33 22926065 // hz = 27.330000000009 +#define IQ_F_VALUE_PLUS_27_34 22934454 // hz = 27.340000000009 +#define IQ_F_VALUE_PLUS_27_35 22942842 // hz = 27.350000000009 +#define IQ_F_VALUE_PLUS_27_36 22951231 // hz = 27.360000000009 +#define IQ_F_VALUE_PLUS_27_37 22959620 // hz = 27.370000000009 +#define IQ_F_VALUE_PLUS_27_38 22968008 // hz = 27.380000000009 +#define IQ_F_VALUE_PLUS_27_39 22976397 // hz = 27.390000000009 +#define IQ_F_VALUE_PLUS_27_40 22984785 // hz = 27.400000000009 +#define IQ_F_VALUE_PLUS_27_41 22993174 // hz = 27.410000000009 +#define IQ_F_VALUE_PLUS_27_42 23001563 // hz = 27.420000000009 +#define IQ_F_VALUE_PLUS_27_43 23009951 // hz = 27.430000000009 +#define IQ_F_VALUE_PLUS_27_44 23018340 // hz = 27.440000000009 +#define IQ_F_VALUE_PLUS_27_45 23026728 // hz = 27.450000000009 +#define IQ_F_VALUE_PLUS_27_46 23035117 // hz = 27.460000000009 +#define IQ_F_VALUE_PLUS_27_47 23043506 // hz = 27.470000000009 +#define IQ_F_VALUE_PLUS_27_48 23051894 // hz = 27.480000000009 +#define IQ_F_VALUE_PLUS_27_49 23060283 // hz = 27.490000000009 +#define IQ_F_VALUE_PLUS_27_50 23068672 // hz = 27.500000000009 +#define IQ_F_VALUE_PLUS_27_51 23077060 // hz = 27.510000000009 +#define IQ_F_VALUE_PLUS_27_52 23085449 // hz = 27.520000000009 +#define IQ_F_VALUE_PLUS_27_53 23093837 // hz = 27.530000000009 +#define IQ_F_VALUE_PLUS_27_54 23102226 // hz = 27.540000000009 +#define IQ_F_VALUE_PLUS_27_55 23110615 // hz = 27.550000000009 +#define IQ_F_VALUE_PLUS_27_56 23119003 // hz = 27.560000000009 +#define IQ_F_VALUE_PLUS_27_57 23127392 // hz = 27.570000000009 +#define IQ_F_VALUE_PLUS_27_58 23135780 // hz = 27.580000000009 +#define IQ_F_VALUE_PLUS_27_59 23144169 // hz = 27.590000000009 +#define IQ_F_VALUE_PLUS_27_60 23152558 // hz = 27.600000000009 +#define IQ_F_VALUE_PLUS_27_61 23160946 // hz = 27.610000000009 +#define IQ_F_VALUE_PLUS_27_62 23169335 // hz = 27.620000000009 +#define IQ_F_VALUE_PLUS_27_63 23177723 // hz = 27.630000000009 +#define IQ_F_VALUE_PLUS_27_64 23186112 // hz = 27.640000000009 +#define IQ_F_VALUE_PLUS_27_65 23194501 // hz = 27.650000000009 +#define IQ_F_VALUE_PLUS_27_66 23202889 // hz = 27.660000000009 +#define IQ_F_VALUE_PLUS_27_67 23211278 // hz = 27.670000000009 +#define IQ_F_VALUE_PLUS_27_68 23219666 // hz = 27.680000000009 +#define IQ_F_VALUE_PLUS_27_69 23228055 // hz = 27.690000000009 +#define IQ_F_VALUE_PLUS_27_70 23236444 // hz = 27.700000000009 +#define IQ_F_VALUE_PLUS_27_71 23244832 // hz = 27.710000000009 +#define IQ_F_VALUE_PLUS_27_72 23253221 // hz = 27.720000000009 +#define IQ_F_VALUE_PLUS_27_73 23261609 // hz = 27.730000000009 +#define IQ_F_VALUE_PLUS_27_74 23269998 // hz = 27.740000000009 +#define IQ_F_VALUE_PLUS_27_75 23278387 // hz = 27.750000000009 +#define IQ_F_VALUE_PLUS_27_76 23286775 // hz = 27.760000000009 +#define IQ_F_VALUE_PLUS_27_77 23295164 // hz = 27.770000000009 +#define IQ_F_VALUE_PLUS_27_78 23303553 // hz = 27.780000000009 +#define IQ_F_VALUE_PLUS_27_79 23311941 // hz = 27.790000000009 +#define IQ_F_VALUE_PLUS_27_80 23320330 // hz = 27.800000000009 +#define IQ_F_VALUE_PLUS_27_81 23328718 // hz = 27.810000000009 +#define IQ_F_VALUE_PLUS_27_82 23337107 // hz = 27.820000000009 +#define IQ_F_VALUE_PLUS_27_83 23345496 // hz = 27.830000000009 +#define IQ_F_VALUE_PLUS_27_84 23353884 // hz = 27.840000000009 +#define IQ_F_VALUE_PLUS_27_85 23362273 // hz = 27.850000000009 +#define IQ_F_VALUE_PLUS_27_86 23370661 // hz = 27.860000000009 +#define IQ_F_VALUE_PLUS_27_87 23379050 // hz = 27.870000000009 +#define IQ_F_VALUE_PLUS_27_88 23387439 // hz = 27.880000000009 +#define IQ_F_VALUE_PLUS_27_89 23395827 // hz = 27.8900000000091 +#define IQ_F_VALUE_PLUS_27_90 23404216 // hz = 27.9000000000091 +#define IQ_F_VALUE_PLUS_27_91 23412604 // hz = 27.910000000009 +#define IQ_F_VALUE_PLUS_27_92 23420993 // hz = 27.9200000000091 +#define IQ_F_VALUE_PLUS_27_93 23429382 // hz = 27.9300000000091 +#define IQ_F_VALUE_PLUS_27_94 23437770 // hz = 27.9400000000091 +#define IQ_F_VALUE_PLUS_27_95 23446159 // hz = 27.9500000000091 +#define IQ_F_VALUE_PLUS_27_96 23454547 // hz = 27.9600000000091 +#define IQ_F_VALUE_PLUS_27_97 23462936 // hz = 27.9700000000091 +#define IQ_F_VALUE_PLUS_27_98 23471325 // hz = 27.9800000000091 +#define IQ_F_VALUE_PLUS_27_99 23479713 // hz = 27.9900000000091 +#define IQ_F_VALUE_PLUS_28_00 23488102 // hz = 28.0000000000091 +#define IQ_F_VALUE_PLUS_28_01 23496491 // hz = 28.0100000000091 +#define IQ_F_VALUE_PLUS_28_02 23504879 // hz = 28.0200000000091 +#define IQ_F_VALUE_PLUS_28_03 23513268 // hz = 28.0300000000091 +#define IQ_F_VALUE_PLUS_28_04 23521656 // hz = 28.0400000000091 +#define IQ_F_VALUE_PLUS_28_05 23530045 // hz = 28.0500000000091 +#define IQ_F_VALUE_PLUS_28_06 23538434 // hz = 28.0600000000091 +#define IQ_F_VALUE_PLUS_28_07 23546822 // hz = 28.0700000000091 +#define IQ_F_VALUE_PLUS_28_08 23555211 // hz = 28.0800000000091 +#define IQ_F_VALUE_PLUS_28_09 23563599 // hz = 28.0900000000091 +#define IQ_F_VALUE_PLUS_28_10 23571988 // hz = 28.1000000000091 +#define IQ_F_VALUE_PLUS_28_11 23580377 // hz = 28.1100000000091 +#define IQ_F_VALUE_PLUS_28_12 23588765 // hz = 28.1200000000091 +#define IQ_F_VALUE_PLUS_28_13 23597154 // hz = 28.1300000000091 +#define IQ_F_VALUE_PLUS_28_14 23605542 // hz = 28.1400000000091 +#define IQ_F_VALUE_PLUS_28_15 23613931 // hz = 28.1500000000091 +#define IQ_F_VALUE_PLUS_28_16 23622320 // hz = 28.1600000000091 +#define IQ_F_VALUE_PLUS_28_17 23630708 // hz = 28.1700000000091 +#define IQ_F_VALUE_PLUS_28_18 23639097 // hz = 28.1800000000091 +#define IQ_F_VALUE_PLUS_28_19 23647485 // hz = 28.1900000000091 +#define IQ_F_VALUE_PLUS_28_20 23655874 // hz = 28.2000000000091 +#define IQ_F_VALUE_PLUS_28_21 23664263 // hz = 28.2100000000091 +#define IQ_F_VALUE_PLUS_28_22 23672651 // hz = 28.2200000000091 +#define IQ_F_VALUE_PLUS_28_23 23681040 // hz = 28.2300000000091 +#define IQ_F_VALUE_PLUS_28_24 23689428 // hz = 28.2400000000091 +#define IQ_F_VALUE_PLUS_28_25 23697817 // hz = 28.2500000000091 +#define IQ_F_VALUE_PLUS_28_26 23706206 // hz = 28.2600000000091 +#define IQ_F_VALUE_PLUS_28_27 23714594 // hz = 28.2700000000091 +#define IQ_F_VALUE_PLUS_28_28 23722983 // hz = 28.2800000000091 +#define IQ_F_VALUE_PLUS_28_29 23731372 // hz = 28.2900000000091 +#define IQ_F_VALUE_PLUS_28_30 23739760 // hz = 28.3000000000091 +#define IQ_F_VALUE_PLUS_28_31 23748149 // hz = 28.3100000000091 +#define IQ_F_VALUE_PLUS_28_32 23756537 // hz = 28.3200000000091 +#define IQ_F_VALUE_PLUS_28_33 23764926 // hz = 28.3300000000091 +#define IQ_F_VALUE_PLUS_28_34 23773315 // hz = 28.3400000000091 +#define IQ_F_VALUE_PLUS_28_35 23781703 // hz = 28.3500000000091 +#define IQ_F_VALUE_PLUS_28_36 23790092 // hz = 28.3600000000091 +#define IQ_F_VALUE_PLUS_28_37 23798480 // hz = 28.3700000000091 +#define IQ_F_VALUE_PLUS_28_38 23806869 // hz = 28.3800000000091 +#define IQ_F_VALUE_PLUS_28_39 23815258 // hz = 28.3900000000091 +#define IQ_F_VALUE_PLUS_28_40 23823646 // hz = 28.4000000000091 +#define IQ_F_VALUE_PLUS_28_41 23832035 // hz = 28.4100000000091 +#define IQ_F_VALUE_PLUS_28_42 23840423 // hz = 28.4200000000091 +#define IQ_F_VALUE_PLUS_28_43 23848812 // hz = 28.4300000000091 +#define IQ_F_VALUE_PLUS_28_44 23857201 // hz = 28.4400000000091 +#define IQ_F_VALUE_PLUS_28_45 23865589 // hz = 28.4500000000091 +#define IQ_F_VALUE_PLUS_28_46 23873978 // hz = 28.4600000000091 +#define IQ_F_VALUE_PLUS_28_47 23882366 // hz = 28.4700000000091 +#define IQ_F_VALUE_PLUS_28_48 23890755 // hz = 28.4800000000091 +#define IQ_F_VALUE_PLUS_28_49 23899144 // hz = 28.4900000000091 +#define IQ_F_VALUE_PLUS_28_50 23907532 // hz = 28.5000000000091 +#define IQ_F_VALUE_PLUS_28_51 23915921 // hz = 28.5100000000091 +#define IQ_F_VALUE_PLUS_28_52 23924310 // hz = 28.5200000000091 +#define IQ_F_VALUE_PLUS_28_53 23932698 // hz = 28.5300000000092 +#define IQ_F_VALUE_PLUS_28_54 23941087 // hz = 28.5400000000092 +#define IQ_F_VALUE_PLUS_28_55 23949475 // hz = 28.5500000000091 +#define IQ_F_VALUE_PLUS_28_56 23957864 // hz = 28.5600000000092 +#define IQ_F_VALUE_PLUS_28_57 23966253 // hz = 28.5700000000092 +#define IQ_F_VALUE_PLUS_28_58 23974641 // hz = 28.5800000000092 +#define IQ_F_VALUE_PLUS_28_59 23983030 // hz = 28.5900000000092 +#define IQ_F_VALUE_PLUS_28_60 23991418 // hz = 28.6000000000092 +#define IQ_F_VALUE_PLUS_28_61 23999807 // hz = 28.6100000000092 +#define IQ_F_VALUE_PLUS_28_62 24008196 // hz = 28.6200000000092 +#define IQ_F_VALUE_PLUS_28_63 24016584 // hz = 28.6300000000092 +#define IQ_F_VALUE_PLUS_28_64 24024973 // hz = 28.6400000000092 +#define IQ_F_VALUE_PLUS_28_65 24033361 // hz = 28.6500000000092 +#define IQ_F_VALUE_PLUS_28_66 24041750 // hz = 28.6600000000092 +#define IQ_F_VALUE_PLUS_28_67 24050139 // hz = 28.6700000000092 +#define IQ_F_VALUE_PLUS_28_68 24058527 // hz = 28.6800000000092 +#define IQ_F_VALUE_PLUS_28_69 24066916 // hz = 28.6900000000092 +#define IQ_F_VALUE_PLUS_28_70 24075304 // hz = 28.7000000000092 +#define IQ_F_VALUE_PLUS_28_71 24083693 // hz = 28.7100000000092 +#define IQ_F_VALUE_PLUS_28_72 24092082 // hz = 28.7200000000092 +#define IQ_F_VALUE_PLUS_28_73 24100470 // hz = 28.7300000000092 +#define IQ_F_VALUE_PLUS_28_74 24108859 // hz = 28.7400000000092 +#define IQ_F_VALUE_PLUS_28_75 24117248 // hz = 28.7500000000092 +#define IQ_F_VALUE_PLUS_28_76 24125636 // hz = 28.7600000000092 +#define IQ_F_VALUE_PLUS_28_77 24134025 // hz = 28.7700000000092 +#define IQ_F_VALUE_PLUS_28_78 24142413 // hz = 28.7800000000092 +#define IQ_F_VALUE_PLUS_28_79 24150802 // hz = 28.7900000000092 +#define IQ_F_VALUE_PLUS_28_80 24159191 // hz = 28.8000000000092 +#define IQ_F_VALUE_PLUS_28_81 24167579 // hz = 28.8100000000092 +#define IQ_F_VALUE_PLUS_28_82 24175968 // hz = 28.8200000000092 +#define IQ_F_VALUE_PLUS_28_83 24184356 // hz = 28.8300000000092 +#define IQ_F_VALUE_PLUS_28_84 24192745 // hz = 28.8400000000092 +#define IQ_F_VALUE_PLUS_28_85 24201134 // hz = 28.8500000000092 +#define IQ_F_VALUE_PLUS_28_86 24209522 // hz = 28.8600000000092 +#define IQ_F_VALUE_PLUS_28_87 24217911 // hz = 28.8700000000092 +#define IQ_F_VALUE_PLUS_28_88 24226299 // hz = 28.8800000000092 +#define IQ_F_VALUE_PLUS_28_89 24234688 // hz = 28.8900000000092 +#define IQ_F_VALUE_PLUS_28_90 24243077 // hz = 28.9000000000092 +#define IQ_F_VALUE_PLUS_28_91 24251465 // hz = 28.9100000000092 +#define IQ_F_VALUE_PLUS_28_92 24259854 // hz = 28.9200000000092 +#define IQ_F_VALUE_PLUS_28_93 24268242 // hz = 28.9300000000092 +#define IQ_F_VALUE_PLUS_28_94 24276631 // hz = 28.9400000000092 +#define IQ_F_VALUE_PLUS_28_95 24285020 // hz = 28.9500000000092 +#define IQ_F_VALUE_PLUS_28_96 24293408 // hz = 28.9600000000092 +#define IQ_F_VALUE_PLUS_28_97 24301797 // hz = 28.9700000000092 +#define IQ_F_VALUE_PLUS_28_98 24310185 // hz = 28.9800000000092 +#define IQ_F_VALUE_PLUS_28_99 24318574 // hz = 28.9900000000092 +#define IQ_F_VALUE_PLUS_29_00 24326963 // hz = 29.0000000000092 +#define IQ_F_VALUE_PLUS_29_01 24335351 // hz = 29.0100000000092 +#define IQ_F_VALUE_PLUS_29_02 24343740 // hz = 29.0200000000092 +#define IQ_F_VALUE_PLUS_29_03 24352129 // hz = 29.0300000000092 +#define IQ_F_VALUE_PLUS_29_04 24360517 // hz = 29.0400000000092 +#define IQ_F_VALUE_PLUS_29_05 24368906 // hz = 29.0500000000092 +#define IQ_F_VALUE_PLUS_29_06 24377294 // hz = 29.0600000000092 +#define IQ_F_VALUE_PLUS_29_07 24385683 // hz = 29.0700000000092 +#define IQ_F_VALUE_PLUS_29_08 24394072 // hz = 29.0800000000092 +#define IQ_F_VALUE_PLUS_29_09 24402460 // hz = 29.0900000000092 +#define IQ_F_VALUE_PLUS_29_10 24410849 // hz = 29.1000000000092 +#define IQ_F_VALUE_PLUS_29_11 24419237 // hz = 29.1100000000092 +#define IQ_F_VALUE_PLUS_29_12 24427626 // hz = 29.1200000000092 +#define IQ_F_VALUE_PLUS_29_13 24436015 // hz = 29.1300000000092 +#define IQ_F_VALUE_PLUS_29_14 24444403 // hz = 29.1400000000092 +#define IQ_F_VALUE_PLUS_29_15 24452792 // hz = 29.1500000000092 +#define IQ_F_VALUE_PLUS_29_16 24461180 // hz = 29.1600000000092 +#define IQ_F_VALUE_PLUS_29_17 24469569 // hz = 29.1700000000093 +#define IQ_F_VALUE_PLUS_29_18 24477958 // hz = 29.1800000000093 +#define IQ_F_VALUE_PLUS_29_19 24486346 // hz = 29.1900000000092 +#define IQ_F_VALUE_PLUS_29_20 24494735 // hz = 29.2000000000093 +#define IQ_F_VALUE_PLUS_29_21 24503123 // hz = 29.2100000000093 +#define IQ_F_VALUE_PLUS_29_22 24511512 // hz = 29.2200000000093 +#define IQ_F_VALUE_PLUS_29_23 24519901 // hz = 29.2300000000093 +#define IQ_F_VALUE_PLUS_29_24 24528289 // hz = 29.2400000000093 +#define IQ_F_VALUE_PLUS_29_25 24536678 // hz = 29.2500000000093 +#define IQ_F_VALUE_PLUS_29_26 24545067 // hz = 29.2600000000093 +#define IQ_F_VALUE_PLUS_29_27 24553455 // hz = 29.2700000000093 +#define IQ_F_VALUE_PLUS_29_28 24561844 // hz = 29.2800000000093 +#define IQ_F_VALUE_PLUS_29_29 24570232 // hz = 29.2900000000093 +#define IQ_F_VALUE_PLUS_29_30 24578621 // hz = 29.3000000000093 +#define IQ_F_VALUE_PLUS_29_31 24587010 // hz = 29.3100000000093 +#define IQ_F_VALUE_PLUS_29_32 24595398 // hz = 29.3200000000093 +#define IQ_F_VALUE_PLUS_29_33 24603787 // hz = 29.3300000000093 +#define IQ_F_VALUE_PLUS_29_34 24612175 // hz = 29.3400000000093 +#define IQ_F_VALUE_PLUS_29_35 24620564 // hz = 29.3500000000093 +#define IQ_F_VALUE_PLUS_29_36 24628953 // hz = 29.3600000000093 +#define IQ_F_VALUE_PLUS_29_37 24637341 // hz = 29.3700000000093 +#define IQ_F_VALUE_PLUS_29_38 24645730 // hz = 29.3800000000093 +#define IQ_F_VALUE_PLUS_29_39 24654118 // hz = 29.3900000000093 +#define IQ_F_VALUE_PLUS_29_40 24662507 // hz = 29.4000000000093 +#define IQ_F_VALUE_PLUS_29_41 24670896 // hz = 29.4100000000093 +#define IQ_F_VALUE_PLUS_29_42 24679284 // hz = 29.4200000000093 +#define IQ_F_VALUE_PLUS_29_43 24687673 // hz = 29.4300000000093 +#define IQ_F_VALUE_PLUS_29_44 24696061 // hz = 29.4400000000093 +#define IQ_F_VALUE_PLUS_29_45 24704450 // hz = 29.4500000000093 +#define IQ_F_VALUE_PLUS_29_46 24712839 // hz = 29.4600000000093 +#define IQ_F_VALUE_PLUS_29_47 24721227 // hz = 29.4700000000093 +#define IQ_F_VALUE_PLUS_29_48 24729616 // hz = 29.4800000000093 +#define IQ_F_VALUE_PLUS_29_49 24738004 // hz = 29.4900000000093 +#define IQ_F_VALUE_PLUS_29_50 24746393 // hz = 29.5000000000093 +#define IQ_F_VALUE_PLUS_29_51 24754782 // hz = 29.5100000000093 +#define IQ_F_VALUE_PLUS_29_52 24763170 // hz = 29.5200000000093 +#define IQ_F_VALUE_PLUS_29_53 24771559 // hz = 29.5300000000093 +#define IQ_F_VALUE_PLUS_29_54 24779948 // hz = 29.5400000000093 +#define IQ_F_VALUE_PLUS_29_55 24788336 // hz = 29.5500000000093 +#define IQ_F_VALUE_PLUS_29_56 24796725 // hz = 29.5600000000093 +#define IQ_F_VALUE_PLUS_29_57 24805113 // hz = 29.5700000000093 +#define IQ_F_VALUE_PLUS_29_58 24813502 // hz = 29.5800000000093 +#define IQ_F_VALUE_PLUS_29_59 24821891 // hz = 29.5900000000093 +#define IQ_F_VALUE_PLUS_29_60 24830279 // hz = 29.6000000000093 +#define IQ_F_VALUE_PLUS_29_61 24838668 // hz = 29.6100000000093 +#define IQ_F_VALUE_PLUS_29_62 24847056 // hz = 29.6200000000093 +#define IQ_F_VALUE_PLUS_29_63 24855445 // hz = 29.6300000000093 +#define IQ_F_VALUE_PLUS_29_64 24863834 // hz = 29.6400000000093 +#define IQ_F_VALUE_PLUS_29_65 24872222 // hz = 29.6500000000093 +#define IQ_F_VALUE_PLUS_29_66 24880611 // hz = 29.6600000000093 +#define IQ_F_VALUE_PLUS_29_67 24888999 // hz = 29.6700000000093 +#define IQ_F_VALUE_PLUS_29_68 24897388 // hz = 29.6800000000093 +#define IQ_F_VALUE_PLUS_29_69 24905777 // hz = 29.6900000000093 +#define IQ_F_VALUE_PLUS_29_70 24914165 // hz = 29.7000000000093 +#define IQ_F_VALUE_PLUS_29_71 24922554 // hz = 29.7100000000093 +#define IQ_F_VALUE_PLUS_29_72 24930942 // hz = 29.7200000000093 +#define IQ_F_VALUE_PLUS_29_73 24939331 // hz = 29.7300000000093 +#define IQ_F_VALUE_PLUS_29_74 24947720 // hz = 29.7400000000093 +#define IQ_F_VALUE_PLUS_29_75 24956108 // hz = 29.7500000000093 +#define IQ_F_VALUE_PLUS_29_76 24964497 // hz = 29.7600000000093 +#define IQ_F_VALUE_PLUS_29_77 24972886 // hz = 29.7700000000093 +#define IQ_F_VALUE_PLUS_29_78 24981274 // hz = 29.7800000000093 +#define IQ_F_VALUE_PLUS_29_79 24989663 // hz = 29.7900000000093 +#define IQ_F_VALUE_PLUS_29_80 24998051 // hz = 29.8000000000093 +#define IQ_F_VALUE_PLUS_29_81 25006440 // hz = 29.8100000000094 +#define IQ_F_VALUE_PLUS_29_82 25014829 // hz = 29.8200000000094 +#define IQ_F_VALUE_PLUS_29_83 25023217 // hz = 29.8300000000093 +#define IQ_F_VALUE_PLUS_29_84 25031606 // hz = 29.8400000000094 +#define IQ_F_VALUE_PLUS_29_85 25039994 // hz = 29.8500000000094 +#define IQ_F_VALUE_PLUS_29_86 25048383 // hz = 29.8600000000094 +#define IQ_F_VALUE_PLUS_29_87 25056772 // hz = 29.8700000000094 +#define IQ_F_VALUE_PLUS_29_88 25065160 // hz = 29.8800000000094 +#define IQ_F_VALUE_PLUS_29_89 25073549 // hz = 29.8900000000094 +#define IQ_F_VALUE_PLUS_29_90 25081937 // hz = 29.9000000000094 +#define IQ_F_VALUE_PLUS_29_91 25090326 // hz = 29.9100000000094 +#define IQ_F_VALUE_PLUS_29_92 25098715 // hz = 29.9200000000094 +#define IQ_F_VALUE_PLUS_29_93 25107103 // hz = 29.9300000000094 +#define IQ_F_VALUE_PLUS_29_94 25115492 // hz = 29.9400000000094 +#define IQ_F_VALUE_PLUS_29_95 25123880 // hz = 29.9500000000094 +#define IQ_F_VALUE_PLUS_29_96 25132269 // hz = 29.9600000000094 +#define IQ_F_VALUE_PLUS_29_97 25140658 // hz = 29.9700000000094 +#define IQ_F_VALUE_PLUS_29_98 25149046 // hz = 29.9800000000094 +#define IQ_F_VALUE_PLUS_29_99 25157435 // hz = 29.9900000000094 +#define IQ_F_VALUE_PLUS_30_00 25165824 // hz = 30.0000000000094 + + +#endif + + + + + +#endif /* _IQ_VALUES_NORMA_F_H_ */ diff --git a/Inu/Src/N12_Libs/iq_values_norma_iu.h b/Inu/Src/N12_Libs/iq_values_norma_iu.h new file mode 100644 index 0000000..fb8eb46 --- /dev/null +++ b/Inu/Src/N12_Libs/iq_values_norma_iu.h @@ -0,0 +1,7025 @@ +/* + * iq_values_norma.h + * + * Created on: 9 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef _IQ_VALUES_IU_H_ +#define _IQ_VALUES_IU_H_ + +#include "params_norma.h" + + +#if (NORMA_MZZ_INT==3000) + +#define IQ_I_U_VALUE_MINUS_3500 -19573419 // = -3500 +#define IQ_I_U_VALUE_MINUS_3499 -19567827 // = -3499 +#define IQ_I_U_VALUE_MINUS_3498 -19562234 // = -3498 +#define IQ_I_U_VALUE_MINUS_3497 -19556642 // = -3497 +#define IQ_I_U_VALUE_MINUS_3496 -19551050 // = -3496 +#define IQ_I_U_VALUE_MINUS_3495 -19545457 // = -3495 +#define IQ_I_U_VALUE_MINUS_3494 -19539865 // = -3494 +#define IQ_I_U_VALUE_MINUS_3493 -19534272 // = -3493 +#define IQ_I_U_VALUE_MINUS_3492 -19528680 // = -3492 +#define IQ_I_U_VALUE_MINUS_3491 -19523088 // = -3491 +#define IQ_I_U_VALUE_MINUS_3490 -19517495 // = -3490 +#define IQ_I_U_VALUE_MINUS_3489 -19511903 // = -3489 +#define IQ_I_U_VALUE_MINUS_3488 -19506310 // = -3488 +#define IQ_I_U_VALUE_MINUS_3487 -19500718 // = -3487 +#define IQ_I_U_VALUE_MINUS_3486 -19495125 // = -3486 +#define IQ_I_U_VALUE_MINUS_3485 -19489533 // = -3485 +#define IQ_I_U_VALUE_MINUS_3484 -19483941 // = -3484 +#define IQ_I_U_VALUE_MINUS_3483 -19478348 // = -3483 +#define IQ_I_U_VALUE_MINUS_3482 -19472756 // = -3482 +#define IQ_I_U_VALUE_MINUS_3481 -19467163 // = -3481 +#define IQ_I_U_VALUE_MINUS_3480 -19461571 // = -3480 +#define IQ_I_U_VALUE_MINUS_3479 -19455979 // = -3479 +#define IQ_I_U_VALUE_MINUS_3478 -19450386 // = -3478 +#define IQ_I_U_VALUE_MINUS_3477 -19444794 // = -3477 +#define IQ_I_U_VALUE_MINUS_3476 -19439201 // = -3476 +#define IQ_I_U_VALUE_MINUS_3475 -19433609 // = -3475 +#define IQ_I_U_VALUE_MINUS_3474 -19428017 // = -3474 +#define IQ_I_U_VALUE_MINUS_3473 -19422424 // = -3473 +#define IQ_I_U_VALUE_MINUS_3472 -19416832 // = -3472 +#define IQ_I_U_VALUE_MINUS_3471 -19411239 // = -3471 +#define IQ_I_U_VALUE_MINUS_3470 -19405647 // = -3470 +#define IQ_I_U_VALUE_MINUS_3469 -19400055 // = -3469 +#define IQ_I_U_VALUE_MINUS_3468 -19394462 // = -3468 +#define IQ_I_U_VALUE_MINUS_3467 -19388870 // = -3467 +#define IQ_I_U_VALUE_MINUS_3466 -19383277 // = -3466 +#define IQ_I_U_VALUE_MINUS_3465 -19377685 // = -3465 +#define IQ_I_U_VALUE_MINUS_3464 -19372093 // = -3464 +#define IQ_I_U_VALUE_MINUS_3463 -19366500 // = -3463 +#define IQ_I_U_VALUE_MINUS_3462 -19360908 // = -3462 +#define IQ_I_U_VALUE_MINUS_3461 -19355315 // = -3461 +#define IQ_I_U_VALUE_MINUS_3460 -19349723 // = -3460 +#define IQ_I_U_VALUE_MINUS_3459 -19344131 // = -3459 +#define IQ_I_U_VALUE_MINUS_3458 -19338538 // = -3458 +#define IQ_I_U_VALUE_MINUS_3457 -19332946 // = -3457 +#define IQ_I_U_VALUE_MINUS_3456 -19327353 // = -3456 +#define IQ_I_U_VALUE_MINUS_3455 -19321761 // = -3455 +#define IQ_I_U_VALUE_MINUS_3454 -19316169 // = -3454 +#define IQ_I_U_VALUE_MINUS_3453 -19310576 // = -3453 +#define IQ_I_U_VALUE_MINUS_3452 -19304984 // = -3452 +#define IQ_I_U_VALUE_MINUS_3451 -19299391 // = -3451 +#define IQ_I_U_VALUE_MINUS_3450 -19293799 // = -3450 +#define IQ_I_U_VALUE_MINUS_3449 -19288206 // = -3449 +#define IQ_I_U_VALUE_MINUS_3448 -19282614 // = -3448 +#define IQ_I_U_VALUE_MINUS_3447 -19277022 // = -3447 +#define IQ_I_U_VALUE_MINUS_3446 -19271429 // = -3446 +#define IQ_I_U_VALUE_MINUS_3445 -19265837 // = -3445 +#define IQ_I_U_VALUE_MINUS_3444 -19260244 // = -3444 +#define IQ_I_U_VALUE_MINUS_3443 -19254652 // = -3443 +#define IQ_I_U_VALUE_MINUS_3442 -19249060 // = -3442 +#define IQ_I_U_VALUE_MINUS_3441 -19243467 // = -3441 +#define IQ_I_U_VALUE_MINUS_3440 -19237875 // = -3440 +#define IQ_I_U_VALUE_MINUS_3439 -19232282 // = -3439 +#define IQ_I_U_VALUE_MINUS_3438 -19226690 // = -3438 +#define IQ_I_U_VALUE_MINUS_3437 -19221098 // = -3437 +#define IQ_I_U_VALUE_MINUS_3436 -19215505 // = -3436 +#define IQ_I_U_VALUE_MINUS_3435 -19209913 // = -3435 +#define IQ_I_U_VALUE_MINUS_3434 -19204320 // = -3434 +#define IQ_I_U_VALUE_MINUS_3433 -19198728 // = -3433 +#define IQ_I_U_VALUE_MINUS_3432 -19193136 // = -3432 +#define IQ_I_U_VALUE_MINUS_3431 -19187543 // = -3431 +#define IQ_I_U_VALUE_MINUS_3430 -19181951 // = -3430 +#define IQ_I_U_VALUE_MINUS_3429 -19176358 // = -3429 +#define IQ_I_U_VALUE_MINUS_3428 -19170766 // = -3428 +#define IQ_I_U_VALUE_MINUS_3427 -19165174 // = -3427 +#define IQ_I_U_VALUE_MINUS_3426 -19159581 // = -3426 +#define IQ_I_U_VALUE_MINUS_3425 -19153989 // = -3425 +#define IQ_I_U_VALUE_MINUS_3424 -19148396 // = -3424 +#define IQ_I_U_VALUE_MINUS_3423 -19142804 // = -3423 +#define IQ_I_U_VALUE_MINUS_3422 -19137212 // = -3422 +#define IQ_I_U_VALUE_MINUS_3421 -19131619 // = -3421 +#define IQ_I_U_VALUE_MINUS_3420 -19126027 // = -3420 +#define IQ_I_U_VALUE_MINUS_3419 -19120434 // = -3419 +#define IQ_I_U_VALUE_MINUS_3418 -19114842 // = -3418 +#define IQ_I_U_VALUE_MINUS_3417 -19109250 // = -3417 +#define IQ_I_U_VALUE_MINUS_3416 -19103657 // = -3416 +#define IQ_I_U_VALUE_MINUS_3415 -19098065 // = -3415 +#define IQ_I_U_VALUE_MINUS_3414 -19092472 // = -3414 +#define IQ_I_U_VALUE_MINUS_3413 -19086880 // = -3413 +#define IQ_I_U_VALUE_MINUS_3412 -19081287 // = -3412 +#define IQ_I_U_VALUE_MINUS_3411 -19075695 // = -3411 +#define IQ_I_U_VALUE_MINUS_3410 -19070103 // = -3410 +#define IQ_I_U_VALUE_MINUS_3409 -19064510 // = -3409 +#define IQ_I_U_VALUE_MINUS_3408 -19058918 // = -3408 +#define IQ_I_U_VALUE_MINUS_3407 -19053325 // = -3407 +#define IQ_I_U_VALUE_MINUS_3406 -19047733 // = -3406 +#define IQ_I_U_VALUE_MINUS_3405 -19042141 // = -3405 +#define IQ_I_U_VALUE_MINUS_3404 -19036548 // = -3404 +#define IQ_I_U_VALUE_MINUS_3403 -19030956 // = -3403 +#define IQ_I_U_VALUE_MINUS_3402 -19025363 // = -3402 +#define IQ_I_U_VALUE_MINUS_3401 -19019771 // = -3401 +#define IQ_I_U_VALUE_MINUS_3400 -19014179 // = -3400 +#define IQ_I_U_VALUE_MINUS_3399 -19008586 // = -3399 +#define IQ_I_U_VALUE_MINUS_3398 -19002994 // = -3398 +#define IQ_I_U_VALUE_MINUS_3397 -18997401 // = -3397 +#define IQ_I_U_VALUE_MINUS_3396 -18991809 // = -3396 +#define IQ_I_U_VALUE_MINUS_3395 -18986217 // = -3395 +#define IQ_I_U_VALUE_MINUS_3394 -18980624 // = -3394 +#define IQ_I_U_VALUE_MINUS_3393 -18975032 // = -3393 +#define IQ_I_U_VALUE_MINUS_3392 -18969439 // = -3392 +#define IQ_I_U_VALUE_MINUS_3391 -18963847 // = -3391 +#define IQ_I_U_VALUE_MINUS_3390 -18958255 // = -3390 +#define IQ_I_U_VALUE_MINUS_3389 -18952662 // = -3389 +#define IQ_I_U_VALUE_MINUS_3388 -18947070 // = -3388 +#define IQ_I_U_VALUE_MINUS_3387 -18941477 // = -3387 +#define IQ_I_U_VALUE_MINUS_3386 -18935885 // = -3386 +#define IQ_I_U_VALUE_MINUS_3385 -18930293 // = -3385 +#define IQ_I_U_VALUE_MINUS_3384 -18924700 // = -3384 +#define IQ_I_U_VALUE_MINUS_3383 -18919108 // = -3383 +#define IQ_I_U_VALUE_MINUS_3382 -18913515 // = -3382 +#define IQ_I_U_VALUE_MINUS_3381 -18907923 // = -3381 +#define IQ_I_U_VALUE_MINUS_3380 -18902331 // = -3380 +#define IQ_I_U_VALUE_MINUS_3379 -18896738 // = -3379 +#define IQ_I_U_VALUE_MINUS_3378 -18891146 // = -3378 +#define IQ_I_U_VALUE_MINUS_3377 -18885553 // = -3377 +#define IQ_I_U_VALUE_MINUS_3376 -18879961 // = -3376 +#define IQ_I_U_VALUE_MINUS_3375 -18874368 // = -3375 +#define IQ_I_U_VALUE_MINUS_3374 -18868776 // = -3374 +#define IQ_I_U_VALUE_MINUS_3373 -18863184 // = -3373 +#define IQ_I_U_VALUE_MINUS_3372 -18857591 // = -3372 +#define IQ_I_U_VALUE_MINUS_3371 -18851999 // = -3371 +#define IQ_I_U_VALUE_MINUS_3370 -18846406 // = -3370 +#define IQ_I_U_VALUE_MINUS_3369 -18840814 // = -3369 +#define IQ_I_U_VALUE_MINUS_3368 -18835222 // = -3368 +#define IQ_I_U_VALUE_MINUS_3367 -18829629 // = -3367 +#define IQ_I_U_VALUE_MINUS_3366 -18824037 // = -3366 +#define IQ_I_U_VALUE_MINUS_3365 -18818444 // = -3365 +#define IQ_I_U_VALUE_MINUS_3364 -18812852 // = -3364 +#define IQ_I_U_VALUE_MINUS_3363 -18807260 // = -3363 +#define IQ_I_U_VALUE_MINUS_3362 -18801667 // = -3362 +#define IQ_I_U_VALUE_MINUS_3361 -18796075 // = -3361 +#define IQ_I_U_VALUE_MINUS_3360 -18790482 // = -3360 +#define IQ_I_U_VALUE_MINUS_3359 -18784890 // = -3359 +#define IQ_I_U_VALUE_MINUS_3358 -18779298 // = -3358 +#define IQ_I_U_VALUE_MINUS_3357 -18773705 // = -3357 +#define IQ_I_U_VALUE_MINUS_3356 -18768113 // = -3356 +#define IQ_I_U_VALUE_MINUS_3355 -18762520 // = -3355 +#define IQ_I_U_VALUE_MINUS_3354 -18756928 // = -3354 +#define IQ_I_U_VALUE_MINUS_3353 -18751336 // = -3353 +#define IQ_I_U_VALUE_MINUS_3352 -18745743 // = -3352 +#define IQ_I_U_VALUE_MINUS_3351 -18740151 // = -3351 +#define IQ_I_U_VALUE_MINUS_3350 -18734558 // = -3350 +#define IQ_I_U_VALUE_MINUS_3349 -18728966 // = -3349 +#define IQ_I_U_VALUE_MINUS_3348 -18723374 // = -3348 +#define IQ_I_U_VALUE_MINUS_3347 -18717781 // = -3347 +#define IQ_I_U_VALUE_MINUS_3346 -18712189 // = -3346 +#define IQ_I_U_VALUE_MINUS_3345 -18706596 // = -3345 +#define IQ_I_U_VALUE_MINUS_3344 -18701004 // = -3344 +#define IQ_I_U_VALUE_MINUS_3343 -18695412 // = -3343 +#define IQ_I_U_VALUE_MINUS_3342 -18689819 // = -3342 +#define IQ_I_U_VALUE_MINUS_3341 -18684227 // = -3341 +#define IQ_I_U_VALUE_MINUS_3340 -18678634 // = -3340 +#define IQ_I_U_VALUE_MINUS_3339 -18673042 // = -3339 +#define IQ_I_U_VALUE_MINUS_3338 -18667450 // = -3338 +#define IQ_I_U_VALUE_MINUS_3337 -18661857 // = -3337 +#define IQ_I_U_VALUE_MINUS_3336 -18656265 // = -3336 +#define IQ_I_U_VALUE_MINUS_3335 -18650672 // = -3335 +#define IQ_I_U_VALUE_MINUS_3334 -18645080 // = -3334 +#define IQ_I_U_VALUE_MINUS_3333 -18639487 // = -3333 +#define IQ_I_U_VALUE_MINUS_3332 -18633895 // = -3332 +#define IQ_I_U_VALUE_MINUS_3331 -18628303 // = -3331 +#define IQ_I_U_VALUE_MINUS_3330 -18622710 // = -3330 +#define IQ_I_U_VALUE_MINUS_3329 -18617118 // = -3329 +#define IQ_I_U_VALUE_MINUS_3328 -18611525 // = -3328 +#define IQ_I_U_VALUE_MINUS_3327 -18605933 // = -3327 +#define IQ_I_U_VALUE_MINUS_3326 -18600341 // = -3326 +#define IQ_I_U_VALUE_MINUS_3325 -18594748 // = -3325 +#define IQ_I_U_VALUE_MINUS_3324 -18589156 // = -3324 +#define IQ_I_U_VALUE_MINUS_3323 -18583563 // = -3323 +#define IQ_I_U_VALUE_MINUS_3322 -18577971 // = -3322 +#define IQ_I_U_VALUE_MINUS_3321 -18572379 // = -3321 +#define IQ_I_U_VALUE_MINUS_3320 -18566786 // = -3320 +#define IQ_I_U_VALUE_MINUS_3319 -18561194 // = -3319 +#define IQ_I_U_VALUE_MINUS_3318 -18555601 // = -3318 +#define IQ_I_U_VALUE_MINUS_3317 -18550009 // = -3317 +#define IQ_I_U_VALUE_MINUS_3316 -18544417 // = -3316 +#define IQ_I_U_VALUE_MINUS_3315 -18538824 // = -3315 +#define IQ_I_U_VALUE_MINUS_3314 -18533232 // = -3314 +#define IQ_I_U_VALUE_MINUS_3313 -18527639 // = -3313 +#define IQ_I_U_VALUE_MINUS_3312 -18522047 // = -3312 +#define IQ_I_U_VALUE_MINUS_3311 -18516455 // = -3311 +#define IQ_I_U_VALUE_MINUS_3310 -18510862 // = -3310 +#define IQ_I_U_VALUE_MINUS_3309 -18505270 // = -3309 +#define IQ_I_U_VALUE_MINUS_3308 -18499677 // = -3308 +#define IQ_I_U_VALUE_MINUS_3307 -18494085 // = -3307 +#define IQ_I_U_VALUE_MINUS_3306 -18488493 // = -3306 +#define IQ_I_U_VALUE_MINUS_3305 -18482900 // = -3305 +#define IQ_I_U_VALUE_MINUS_3304 -18477308 // = -3304 +#define IQ_I_U_VALUE_MINUS_3303 -18471715 // = -3303 +#define IQ_I_U_VALUE_MINUS_3302 -18466123 // = -3302 +#define IQ_I_U_VALUE_MINUS_3301 -18460531 // = -3301 +#define IQ_I_U_VALUE_MINUS_3300 -18454938 // = -3300 +#define IQ_I_U_VALUE_MINUS_3299 -18449346 // = -3299 +#define IQ_I_U_VALUE_MINUS_3298 -18443753 // = -3298 +#define IQ_I_U_VALUE_MINUS_3297 -18438161 // = -3297 +#define IQ_I_U_VALUE_MINUS_3296 -18432568 // = -3296 +#define IQ_I_U_VALUE_MINUS_3295 -18426976 // = -3295 +#define IQ_I_U_VALUE_MINUS_3294 -18421384 // = -3294 +#define IQ_I_U_VALUE_MINUS_3293 -18415791 // = -3293 +#define IQ_I_U_VALUE_MINUS_3292 -18410199 // = -3292 +#define IQ_I_U_VALUE_MINUS_3291 -18404606 // = -3291 +#define IQ_I_U_VALUE_MINUS_3290 -18399014 // = -3290 +#define IQ_I_U_VALUE_MINUS_3289 -18393422 // = -3289 +#define IQ_I_U_VALUE_MINUS_3288 -18387829 // = -3288 +#define IQ_I_U_VALUE_MINUS_3287 -18382237 // = -3287 +#define IQ_I_U_VALUE_MINUS_3286 -18376644 // = -3286 +#define IQ_I_U_VALUE_MINUS_3285 -18371052 // = -3285 +#define IQ_I_U_VALUE_MINUS_3284 -18365460 // = -3284 +#define IQ_I_U_VALUE_MINUS_3283 -18359867 // = -3283 +#define IQ_I_U_VALUE_MINUS_3282 -18354275 // = -3282 +#define IQ_I_U_VALUE_MINUS_3281 -18348682 // = -3281 +#define IQ_I_U_VALUE_MINUS_3280 -18343090 // = -3280 +#define IQ_I_U_VALUE_MINUS_3279 -18337498 // = -3279 +#define IQ_I_U_VALUE_MINUS_3278 -18331905 // = -3278 +#define IQ_I_U_VALUE_MINUS_3277 -18326313 // = -3277 +#define IQ_I_U_VALUE_MINUS_3276 -18320720 // = -3276 +#define IQ_I_U_VALUE_MINUS_3275 -18315128 // = -3275 +#define IQ_I_U_VALUE_MINUS_3274 -18309536 // = -3274 +#define IQ_I_U_VALUE_MINUS_3273 -18303943 // = -3273 +#define IQ_I_U_VALUE_MINUS_3272 -18298351 // = -3272 +#define IQ_I_U_VALUE_MINUS_3271 -18292758 // = -3271 +#define IQ_I_U_VALUE_MINUS_3270 -18287166 // = -3270 +#define IQ_I_U_VALUE_MINUS_3269 -18281574 // = -3269 +#define IQ_I_U_VALUE_MINUS_3268 -18275981 // = -3268 +#define IQ_I_U_VALUE_MINUS_3267 -18270389 // = -3267 +#define IQ_I_U_VALUE_MINUS_3266 -18264796 // = -3266 +#define IQ_I_U_VALUE_MINUS_3265 -18259204 // = -3265 +#define IQ_I_U_VALUE_MINUS_3264 -18253612 // = -3264 +#define IQ_I_U_VALUE_MINUS_3263 -18248019 // = -3263 +#define IQ_I_U_VALUE_MINUS_3262 -18242427 // = -3262 +#define IQ_I_U_VALUE_MINUS_3261 -18236834 // = -3261 +#define IQ_I_U_VALUE_MINUS_3260 -18231242 // = -3260 +#define IQ_I_U_VALUE_MINUS_3259 -18225649 // = -3259 +#define IQ_I_U_VALUE_MINUS_3258 -18220057 // = -3258 +#define IQ_I_U_VALUE_MINUS_3257 -18214465 // = -3257 +#define IQ_I_U_VALUE_MINUS_3256 -18208872 // = -3256 +#define IQ_I_U_VALUE_MINUS_3255 -18203280 // = -3255 +#define IQ_I_U_VALUE_MINUS_3254 -18197687 // = -3254 +#define IQ_I_U_VALUE_MINUS_3253 -18192095 // = -3253 +#define IQ_I_U_VALUE_MINUS_3252 -18186503 // = -3252 +#define IQ_I_U_VALUE_MINUS_3251 -18180910 // = -3251 +#define IQ_I_U_VALUE_MINUS_3250 -18175318 // = -3250 +#define IQ_I_U_VALUE_MINUS_3249 -18169725 // = -3249 +#define IQ_I_U_VALUE_MINUS_3248 -18164133 // = -3248 +#define IQ_I_U_VALUE_MINUS_3247 -18158541 // = -3247 +#define IQ_I_U_VALUE_MINUS_3246 -18152948 // = -3246 +#define IQ_I_U_VALUE_MINUS_3245 -18147356 // = -3245 +#define IQ_I_U_VALUE_MINUS_3244 -18141763 // = -3244 +#define IQ_I_U_VALUE_MINUS_3243 -18136171 // = -3243 +#define IQ_I_U_VALUE_MINUS_3242 -18130579 // = -3242 +#define IQ_I_U_VALUE_MINUS_3241 -18124986 // = -3241 +#define IQ_I_U_VALUE_MINUS_3240 -18119394 // = -3240 +#define IQ_I_U_VALUE_MINUS_3239 -18113801 // = -3239 +#define IQ_I_U_VALUE_MINUS_3238 -18108209 // = -3238 +#define IQ_I_U_VALUE_MINUS_3237 -18102617 // = -3237 +#define IQ_I_U_VALUE_MINUS_3236 -18097024 // = -3236 +#define IQ_I_U_VALUE_MINUS_3235 -18091432 // = -3235 +#define IQ_I_U_VALUE_MINUS_3234 -18085839 // = -3234 +#define IQ_I_U_VALUE_MINUS_3233 -18080247 // = -3233 +#define IQ_I_U_VALUE_MINUS_3232 -18074655 // = -3232 +#define IQ_I_U_VALUE_MINUS_3231 -18069062 // = -3231 +#define IQ_I_U_VALUE_MINUS_3230 -18063470 // = -3230 +#define IQ_I_U_VALUE_MINUS_3229 -18057877 // = -3229 +#define IQ_I_U_VALUE_MINUS_3228 -18052285 // = -3228 +#define IQ_I_U_VALUE_MINUS_3227 -18046693 // = -3227 +#define IQ_I_U_VALUE_MINUS_3226 -18041100 // = -3226 +#define IQ_I_U_VALUE_MINUS_3225 -18035508 // = -3225 +#define IQ_I_U_VALUE_MINUS_3224 -18029915 // = -3224 +#define IQ_I_U_VALUE_MINUS_3223 -18024323 // = -3223 +#define IQ_I_U_VALUE_MINUS_3222 -18018730 // = -3222 +#define IQ_I_U_VALUE_MINUS_3221 -18013138 // = -3221 +#define IQ_I_U_VALUE_MINUS_3220 -18007546 // = -3220 +#define IQ_I_U_VALUE_MINUS_3219 -18001953 // = -3219 +#define IQ_I_U_VALUE_MINUS_3218 -17996361 // = -3218 +#define IQ_I_U_VALUE_MINUS_3217 -17990768 // = -3217 +#define IQ_I_U_VALUE_MINUS_3216 -17985176 // = -3216 +#define IQ_I_U_VALUE_MINUS_3215 -17979584 // = -3215 +#define IQ_I_U_VALUE_MINUS_3214 -17973991 // = -3214 +#define IQ_I_U_VALUE_MINUS_3213 -17968399 // = -3213 +#define IQ_I_U_VALUE_MINUS_3212 -17962806 // = -3212 +#define IQ_I_U_VALUE_MINUS_3211 -17957214 // = -3211 +#define IQ_I_U_VALUE_MINUS_3210 -17951622 // = -3210 +#define IQ_I_U_VALUE_MINUS_3209 -17946029 // = -3209 +#define IQ_I_U_VALUE_MINUS_3208 -17940437 // = -3208 +#define IQ_I_U_VALUE_MINUS_3207 -17934844 // = -3207 +#define IQ_I_U_VALUE_MINUS_3206 -17929252 // = -3206 +#define IQ_I_U_VALUE_MINUS_3205 -17923660 // = -3205 +#define IQ_I_U_VALUE_MINUS_3204 -17918067 // = -3204 +#define IQ_I_U_VALUE_MINUS_3203 -17912475 // = -3203 +#define IQ_I_U_VALUE_MINUS_3202 -17906882 // = -3202 +#define IQ_I_U_VALUE_MINUS_3201 -17901290 // = -3201 +#define IQ_I_U_VALUE_MINUS_3200 -17895698 // = -3200 +#define IQ_I_U_VALUE_MINUS_3199 -17890105 // = -3199 +#define IQ_I_U_VALUE_MINUS_3198 -17884513 // = -3198 +#define IQ_I_U_VALUE_MINUS_3197 -17878920 // = -3197 +#define IQ_I_U_VALUE_MINUS_3196 -17873328 // = -3196 +#define IQ_I_U_VALUE_MINUS_3195 -17867736 // = -3195 +#define IQ_I_U_VALUE_MINUS_3194 -17862143 // = -3194 +#define IQ_I_U_VALUE_MINUS_3193 -17856551 // = -3193 +#define IQ_I_U_VALUE_MINUS_3192 -17850958 // = -3192 +#define IQ_I_U_VALUE_MINUS_3191 -17845366 // = -3191 +#define IQ_I_U_VALUE_MINUS_3190 -17839774 // = -3190 +#define IQ_I_U_VALUE_MINUS_3189 -17834181 // = -3189 +#define IQ_I_U_VALUE_MINUS_3188 -17828589 // = -3188 +#define IQ_I_U_VALUE_MINUS_3187 -17822996 // = -3187 +#define IQ_I_U_VALUE_MINUS_3186 -17817404 // = -3186 +#define IQ_I_U_VALUE_MINUS_3185 -17811811 // = -3185 +#define IQ_I_U_VALUE_MINUS_3184 -17806219 // = -3184 +#define IQ_I_U_VALUE_MINUS_3183 -17800627 // = -3183 +#define IQ_I_U_VALUE_MINUS_3182 -17795034 // = -3182 +#define IQ_I_U_VALUE_MINUS_3181 -17789442 // = -3181 +#define IQ_I_U_VALUE_MINUS_3180 -17783849 // = -3180 +#define IQ_I_U_VALUE_MINUS_3179 -17778257 // = -3179 +#define IQ_I_U_VALUE_MINUS_3178 -17772665 // = -3178 +#define IQ_I_U_VALUE_MINUS_3177 -17767072 // = -3177 +#define IQ_I_U_VALUE_MINUS_3176 -17761480 // = -3176 +#define IQ_I_U_VALUE_MINUS_3175 -17755887 // = -3175 +#define IQ_I_U_VALUE_MINUS_3174 -17750295 // = -3174 +#define IQ_I_U_VALUE_MINUS_3173 -17744703 // = -3173 +#define IQ_I_U_VALUE_MINUS_3172 -17739110 // = -3172 +#define IQ_I_U_VALUE_MINUS_3171 -17733518 // = -3171 +#define IQ_I_U_VALUE_MINUS_3170 -17727925 // = -3170 +#define IQ_I_U_VALUE_MINUS_3169 -17722333 // = -3169 +#define IQ_I_U_VALUE_MINUS_3168 -17716741 // = -3168 +#define IQ_I_U_VALUE_MINUS_3167 -17711148 // = -3167 +#define IQ_I_U_VALUE_MINUS_3166 -17705556 // = -3166 +#define IQ_I_U_VALUE_MINUS_3165 -17699963 // = -3165 +#define IQ_I_U_VALUE_MINUS_3164 -17694371 // = -3164 +#define IQ_I_U_VALUE_MINUS_3163 -17688779 // = -3163 +#define IQ_I_U_VALUE_MINUS_3162 -17683186 // = -3162 +#define IQ_I_U_VALUE_MINUS_3161 -17677594 // = -3161 +#define IQ_I_U_VALUE_MINUS_3160 -17672001 // = -3160 +#define IQ_I_U_VALUE_MINUS_3159 -17666409 // = -3159 +#define IQ_I_U_VALUE_MINUS_3158 -17660817 // = -3158 +#define IQ_I_U_VALUE_MINUS_3157 -17655224 // = -3157 +#define IQ_I_U_VALUE_MINUS_3156 -17649632 // = -3156 +#define IQ_I_U_VALUE_MINUS_3155 -17644039 // = -3155 +#define IQ_I_U_VALUE_MINUS_3154 -17638447 // = -3154 +#define IQ_I_U_VALUE_MINUS_3153 -17632855 // = -3153 +#define IQ_I_U_VALUE_MINUS_3152 -17627262 // = -3152 +#define IQ_I_U_VALUE_MINUS_3151 -17621670 // = -3151 +#define IQ_I_U_VALUE_MINUS_3150 -17616077 // = -3150 +#define IQ_I_U_VALUE_MINUS_3149 -17610485 // = -3149 +#define IQ_I_U_VALUE_MINUS_3148 -17604892 // = -3148 +#define IQ_I_U_VALUE_MINUS_3147 -17599300 // = -3147 +#define IQ_I_U_VALUE_MINUS_3146 -17593708 // = -3146 +#define IQ_I_U_VALUE_MINUS_3145 -17588115 // = -3145 +#define IQ_I_U_VALUE_MINUS_3144 -17582523 // = -3144 +#define IQ_I_U_VALUE_MINUS_3143 -17576930 // = -3143 +#define IQ_I_U_VALUE_MINUS_3142 -17571338 // = -3142 +#define IQ_I_U_VALUE_MINUS_3141 -17565746 // = -3141 +#define IQ_I_U_VALUE_MINUS_3140 -17560153 // = -3140 +#define IQ_I_U_VALUE_MINUS_3139 -17554561 // = -3139 +#define IQ_I_U_VALUE_MINUS_3138 -17548968 // = -3138 +#define IQ_I_U_VALUE_MINUS_3137 -17543376 // = -3137 +#define IQ_I_U_VALUE_MINUS_3136 -17537784 // = -3136 +#define IQ_I_U_VALUE_MINUS_3135 -17532191 // = -3135 +#define IQ_I_U_VALUE_MINUS_3134 -17526599 // = -3134 +#define IQ_I_U_VALUE_MINUS_3133 -17521006 // = -3133 +#define IQ_I_U_VALUE_MINUS_3132 -17515414 // = -3132 +#define IQ_I_U_VALUE_MINUS_3131 -17509822 // = -3131 +#define IQ_I_U_VALUE_MINUS_3130 -17504229 // = -3130 +#define IQ_I_U_VALUE_MINUS_3129 -17498637 // = -3129 +#define IQ_I_U_VALUE_MINUS_3128 -17493044 // = -3128 +#define IQ_I_U_VALUE_MINUS_3127 -17487452 // = -3127 +#define IQ_I_U_VALUE_MINUS_3126 -17481860 // = -3126 +#define IQ_I_U_VALUE_MINUS_3125 -17476267 // = -3125 +#define IQ_I_U_VALUE_MINUS_3124 -17470675 // = -3124 +#define IQ_I_U_VALUE_MINUS_3123 -17465082 // = -3123 +#define IQ_I_U_VALUE_MINUS_3122 -17459490 // = -3122 +#define IQ_I_U_VALUE_MINUS_3121 -17453898 // = -3121 +#define IQ_I_U_VALUE_MINUS_3120 -17448305 // = -3120 +#define IQ_I_U_VALUE_MINUS_3119 -17442713 // = -3119 +#define IQ_I_U_VALUE_MINUS_3118 -17437120 // = -3118 +#define IQ_I_U_VALUE_MINUS_3117 -17431528 // = -3117 +#define IQ_I_U_VALUE_MINUS_3116 -17425936 // = -3116 +#define IQ_I_U_VALUE_MINUS_3115 -17420343 // = -3115 +#define IQ_I_U_VALUE_MINUS_3114 -17414751 // = -3114 +#define IQ_I_U_VALUE_MINUS_3113 -17409158 // = -3113 +#define IQ_I_U_VALUE_MINUS_3112 -17403566 // = -3112 +#define IQ_I_U_VALUE_MINUS_3111 -17397973 // = -3111 +#define IQ_I_U_VALUE_MINUS_3110 -17392381 // = -3110 +#define IQ_I_U_VALUE_MINUS_3109 -17386789 // = -3109 +#define IQ_I_U_VALUE_MINUS_3108 -17381196 // = -3108 +#define IQ_I_U_VALUE_MINUS_3107 -17375604 // = -3107 +#define IQ_I_U_VALUE_MINUS_3106 -17370011 // = -3106 +#define IQ_I_U_VALUE_MINUS_3105 -17364419 // = -3105 +#define IQ_I_U_VALUE_MINUS_3104 -17358827 // = -3104 +#define IQ_I_U_VALUE_MINUS_3103 -17353234 // = -3103 +#define IQ_I_U_VALUE_MINUS_3102 -17347642 // = -3102 +#define IQ_I_U_VALUE_MINUS_3101 -17342049 // = -3101 +#define IQ_I_U_VALUE_MINUS_3100 -17336457 // = -3100 +#define IQ_I_U_VALUE_MINUS_3099 -17330865 // = -3099 +#define IQ_I_U_VALUE_MINUS_3098 -17325272 // = -3098 +#define IQ_I_U_VALUE_MINUS_3097 -17319680 // = -3097 +#define IQ_I_U_VALUE_MINUS_3096 -17314087 // = -3096 +#define IQ_I_U_VALUE_MINUS_3095 -17308495 // = -3095 +#define IQ_I_U_VALUE_MINUS_3094 -17302903 // = -3094 +#define IQ_I_U_VALUE_MINUS_3093 -17297310 // = -3093 +#define IQ_I_U_VALUE_MINUS_3092 -17291718 // = -3092 +#define IQ_I_U_VALUE_MINUS_3091 -17286125 // = -3091 +#define IQ_I_U_VALUE_MINUS_3090 -17280533 // = -3090 +#define IQ_I_U_VALUE_MINUS_3089 -17274941 // = -3089 +#define IQ_I_U_VALUE_MINUS_3088 -17269348 // = -3088 +#define IQ_I_U_VALUE_MINUS_3087 -17263756 // = -3087 +#define IQ_I_U_VALUE_MINUS_3086 -17258163 // = -3086 +#define IQ_I_U_VALUE_MINUS_3085 -17252571 // = -3085 +#define IQ_I_U_VALUE_MINUS_3084 -17246979 // = -3084 +#define IQ_I_U_VALUE_MINUS_3083 -17241386 // = -3083 +#define IQ_I_U_VALUE_MINUS_3082 -17235794 // = -3082 +#define IQ_I_U_VALUE_MINUS_3081 -17230201 // = -3081 +#define IQ_I_U_VALUE_MINUS_3080 -17224609 // = -3080 +#define IQ_I_U_VALUE_MINUS_3079 -17219017 // = -3079 +#define IQ_I_U_VALUE_MINUS_3078 -17213424 // = -3078 +#define IQ_I_U_VALUE_MINUS_3077 -17207832 // = -3077 +#define IQ_I_U_VALUE_MINUS_3076 -17202239 // = -3076 +#define IQ_I_U_VALUE_MINUS_3075 -17196647 // = -3075 +#define IQ_I_U_VALUE_MINUS_3074 -17191054 // = -3074 +#define IQ_I_U_VALUE_MINUS_3073 -17185462 // = -3073 +#define IQ_I_U_VALUE_MINUS_3072 -17179870 // = -3072 +#define IQ_I_U_VALUE_MINUS_3071 -17174277 // = -3071 +#define IQ_I_U_VALUE_MINUS_3070 -17168685 // = -3070 +#define IQ_I_U_VALUE_MINUS_3069 -17163092 // = -3069 +#define IQ_I_U_VALUE_MINUS_3068 -17157500 // = -3068 +#define IQ_I_U_VALUE_MINUS_3067 -17151908 // = -3067 +#define IQ_I_U_VALUE_MINUS_3066 -17146315 // = -3066 +#define IQ_I_U_VALUE_MINUS_3065 -17140723 // = -3065 +#define IQ_I_U_VALUE_MINUS_3064 -17135130 // = -3064 +#define IQ_I_U_VALUE_MINUS_3063 -17129538 // = -3063 +#define IQ_I_U_VALUE_MINUS_3062 -17123946 // = -3062 +#define IQ_I_U_VALUE_MINUS_3061 -17118353 // = -3061 +#define IQ_I_U_VALUE_MINUS_3060 -17112761 // = -3060 +#define IQ_I_U_VALUE_MINUS_3059 -17107168 // = -3059 +#define IQ_I_U_VALUE_MINUS_3058 -17101576 // = -3058 +#define IQ_I_U_VALUE_MINUS_3057 -17095984 // = -3057 +#define IQ_I_U_VALUE_MINUS_3056 -17090391 // = -3056 +#define IQ_I_U_VALUE_MINUS_3055 -17084799 // = -3055 +#define IQ_I_U_VALUE_MINUS_3054 -17079206 // = -3054 +#define IQ_I_U_VALUE_MINUS_3053 -17073614 // = -3053 +#define IQ_I_U_VALUE_MINUS_3052 -17068022 // = -3052 +#define IQ_I_U_VALUE_MINUS_3051 -17062429 // = -3051 +#define IQ_I_U_VALUE_MINUS_3050 -17056837 // = -3050 +#define IQ_I_U_VALUE_MINUS_3049 -17051244 // = -3049 +#define IQ_I_U_VALUE_MINUS_3048 -17045652 // = -3048 +#define IQ_I_U_VALUE_MINUS_3047 -17040060 // = -3047 +#define IQ_I_U_VALUE_MINUS_3046 -17034467 // = -3046 +#define IQ_I_U_VALUE_MINUS_3045 -17028875 // = -3045 +#define IQ_I_U_VALUE_MINUS_3044 -17023282 // = -3044 +#define IQ_I_U_VALUE_MINUS_3043 -17017690 // = -3043 +#define IQ_I_U_VALUE_MINUS_3042 -17012098 // = -3042 +#define IQ_I_U_VALUE_MINUS_3041 -17006505 // = -3041 +#define IQ_I_U_VALUE_MINUS_3040 -17000913 // = -3040 +#define IQ_I_U_VALUE_MINUS_3039 -16995320 // = -3039 +#define IQ_I_U_VALUE_MINUS_3038 -16989728 // = -3038 +#define IQ_I_U_VALUE_MINUS_3037 -16984135 // = -3037 +#define IQ_I_U_VALUE_MINUS_3036 -16978543 // = -3036 +#define IQ_I_U_VALUE_MINUS_3035 -16972951 // = -3035 +#define IQ_I_U_VALUE_MINUS_3034 -16967358 // = -3034 +#define IQ_I_U_VALUE_MINUS_3033 -16961766 // = -3033 +#define IQ_I_U_VALUE_MINUS_3032 -16956173 // = -3032 +#define IQ_I_U_VALUE_MINUS_3031 -16950581 // = -3031 +#define IQ_I_U_VALUE_MINUS_3030 -16944989 // = -3030 +#define IQ_I_U_VALUE_MINUS_3029 -16939396 // = -3029 +#define IQ_I_U_VALUE_MINUS_3028 -16933804 // = -3028 +#define IQ_I_U_VALUE_MINUS_3027 -16928211 // = -3027 +#define IQ_I_U_VALUE_MINUS_3026 -16922619 // = -3026 +#define IQ_I_U_VALUE_MINUS_3025 -16917027 // = -3025 +#define IQ_I_U_VALUE_MINUS_3024 -16911434 // = -3024 +#define IQ_I_U_VALUE_MINUS_3023 -16905842 // = -3023 +#define IQ_I_U_VALUE_MINUS_3022 -16900249 // = -3022 +#define IQ_I_U_VALUE_MINUS_3021 -16894657 // = -3021 +#define IQ_I_U_VALUE_MINUS_3020 -16889065 // = -3020 +#define IQ_I_U_VALUE_MINUS_3019 -16883472 // = -3019 +#define IQ_I_U_VALUE_MINUS_3018 -16877880 // = -3018 +#define IQ_I_U_VALUE_MINUS_3017 -16872287 // = -3017 +#define IQ_I_U_VALUE_MINUS_3016 -16866695 // = -3016 +#define IQ_I_U_VALUE_MINUS_3015 -16861103 // = -3015 +#define IQ_I_U_VALUE_MINUS_3014 -16855510 // = -3014 +#define IQ_I_U_VALUE_MINUS_3013 -16849918 // = -3013 +#define IQ_I_U_VALUE_MINUS_3012 -16844325 // = -3012 +#define IQ_I_U_VALUE_MINUS_3011 -16838733 // = -3011 +#define IQ_I_U_VALUE_MINUS_3010 -16833141 // = -3010 +#define IQ_I_U_VALUE_MINUS_3009 -16827548 // = -3009 +#define IQ_I_U_VALUE_MINUS_3008 -16821956 // = -3008 +#define IQ_I_U_VALUE_MINUS_3007 -16816363 // = -3007 +#define IQ_I_U_VALUE_MINUS_3006 -16810771 // = -3006 +#define IQ_I_U_VALUE_MINUS_3005 -16805179 // = -3005 +#define IQ_I_U_VALUE_MINUS_3004 -16799586 // = -3004 +#define IQ_I_U_VALUE_MINUS_3003 -16793994 // = -3003 +#define IQ_I_U_VALUE_MINUS_3002 -16788401 // = -3002 +#define IQ_I_U_VALUE_MINUS_3001 -16782809 // = -3001 +#define IQ_I_U_VALUE_MINUS_3000 -16777216 // = -3000 +#define IQ_I_U_VALUE_MINUS_2999 -16771624 // = -2999 +#define IQ_I_U_VALUE_MINUS_2998 -16766032 // = -2998 +#define IQ_I_U_VALUE_MINUS_2997 -16760439 // = -2997 +#define IQ_I_U_VALUE_MINUS_2996 -16754847 // = -2996 +#define IQ_I_U_VALUE_MINUS_2995 -16749254 // = -2995 +#define IQ_I_U_VALUE_MINUS_2994 -16743662 // = -2994 +#define IQ_I_U_VALUE_MINUS_2993 -16738070 // = -2993 +#define IQ_I_U_VALUE_MINUS_2992 -16732477 // = -2992 +#define IQ_I_U_VALUE_MINUS_2991 -16726885 // = -2991 +#define IQ_I_U_VALUE_MINUS_2990 -16721292 // = -2990 +#define IQ_I_U_VALUE_MINUS_2989 -16715700 // = -2989 +#define IQ_I_U_VALUE_MINUS_2988 -16710108 // = -2988 +#define IQ_I_U_VALUE_MINUS_2987 -16704515 // = -2987 +#define IQ_I_U_VALUE_MINUS_2986 -16698923 // = -2986 +#define IQ_I_U_VALUE_MINUS_2985 -16693330 // = -2985 +#define IQ_I_U_VALUE_MINUS_2984 -16687738 // = -2984 +#define IQ_I_U_VALUE_MINUS_2983 -16682146 // = -2983 +#define IQ_I_U_VALUE_MINUS_2982 -16676553 // = -2982 +#define IQ_I_U_VALUE_MINUS_2981 -16670961 // = -2981 +#define IQ_I_U_VALUE_MINUS_2980 -16665368 // = -2980 +#define IQ_I_U_VALUE_MINUS_2979 -16659776 // = -2979 +#define IQ_I_U_VALUE_MINUS_2978 -16654184 // = -2978 +#define IQ_I_U_VALUE_MINUS_2977 -16648591 // = -2977 +#define IQ_I_U_VALUE_MINUS_2976 -16642999 // = -2976 +#define IQ_I_U_VALUE_MINUS_2975 -16637406 // = -2975 +#define IQ_I_U_VALUE_MINUS_2974 -16631814 // = -2974 +#define IQ_I_U_VALUE_MINUS_2973 -16626222 // = -2973 +#define IQ_I_U_VALUE_MINUS_2972 -16620629 // = -2972 +#define IQ_I_U_VALUE_MINUS_2971 -16615037 // = -2971 +#define IQ_I_U_VALUE_MINUS_2970 -16609444 // = -2970 +#define IQ_I_U_VALUE_MINUS_2969 -16603852 // = -2969 +#define IQ_I_U_VALUE_MINUS_2968 -16598260 // = -2968 +#define IQ_I_U_VALUE_MINUS_2967 -16592667 // = -2967 +#define IQ_I_U_VALUE_MINUS_2966 -16587075 // = -2966 +#define IQ_I_U_VALUE_MINUS_2965 -16581482 // = -2965 +#define IQ_I_U_VALUE_MINUS_2964 -16575890 // = -2964 +#define IQ_I_U_VALUE_MINUS_2963 -16570298 // = -2963 +#define IQ_I_U_VALUE_MINUS_2962 -16564705 // = -2962 +#define IQ_I_U_VALUE_MINUS_2961 -16559113 // = -2961 +#define IQ_I_U_VALUE_MINUS_2960 -16553520 // = -2960 +#define IQ_I_U_VALUE_MINUS_2959 -16547928 // = -2959 +#define IQ_I_U_VALUE_MINUS_2958 -16542335 // = -2958 +#define IQ_I_U_VALUE_MINUS_2957 -16536743 // = -2957 +#define IQ_I_U_VALUE_MINUS_2956 -16531151 // = -2956 +#define IQ_I_U_VALUE_MINUS_2955 -16525558 // = -2955 +#define IQ_I_U_VALUE_MINUS_2954 -16519966 // = -2954 +#define IQ_I_U_VALUE_MINUS_2953 -16514373 // = -2953 +#define IQ_I_U_VALUE_MINUS_2952 -16508781 // = -2952 +#define IQ_I_U_VALUE_MINUS_2951 -16503189 // = -2951 +#define IQ_I_U_VALUE_MINUS_2950 -16497596 // = -2950 +#define IQ_I_U_VALUE_MINUS_2949 -16492004 // = -2949 +#define IQ_I_U_VALUE_MINUS_2948 -16486411 // = -2948 +#define IQ_I_U_VALUE_MINUS_2947 -16480819 // = -2947 +#define IQ_I_U_VALUE_MINUS_2946 -16475227 // = -2946 +#define IQ_I_U_VALUE_MINUS_2945 -16469634 // = -2945 +#define IQ_I_U_VALUE_MINUS_2944 -16464042 // = -2944 +#define IQ_I_U_VALUE_MINUS_2943 -16458449 // = -2943 +#define IQ_I_U_VALUE_MINUS_2942 -16452857 // = -2942 +#define IQ_I_U_VALUE_MINUS_2941 -16447265 // = -2941 +#define IQ_I_U_VALUE_MINUS_2940 -16441672 // = -2940 +#define IQ_I_U_VALUE_MINUS_2939 -16436080 // = -2939 +#define IQ_I_U_VALUE_MINUS_2938 -16430487 // = -2938 +#define IQ_I_U_VALUE_MINUS_2937 -16424895 // = -2937 +#define IQ_I_U_VALUE_MINUS_2936 -16419303 // = -2936 +#define IQ_I_U_VALUE_MINUS_2935 -16413710 // = -2935 +#define IQ_I_U_VALUE_MINUS_2934 -16408118 // = -2934 +#define IQ_I_U_VALUE_MINUS_2933 -16402525 // = -2933 +#define IQ_I_U_VALUE_MINUS_2932 -16396933 // = -2932 +#define IQ_I_U_VALUE_MINUS_2931 -16391341 // = -2931 +#define IQ_I_U_VALUE_MINUS_2930 -16385748 // = -2930 +#define IQ_I_U_VALUE_MINUS_2929 -16380156 // = -2929 +#define IQ_I_U_VALUE_MINUS_2928 -16374563 // = -2928 +#define IQ_I_U_VALUE_MINUS_2927 -16368971 // = -2927 +#define IQ_I_U_VALUE_MINUS_2926 -16363379 // = -2926 +#define IQ_I_U_VALUE_MINUS_2925 -16357786 // = -2925 +#define IQ_I_U_VALUE_MINUS_2924 -16352194 // = -2924 +#define IQ_I_U_VALUE_MINUS_2923 -16346601 // = -2923 +#define IQ_I_U_VALUE_MINUS_2922 -16341009 // = -2922 +#define IQ_I_U_VALUE_MINUS_2921 -16335416 // = -2921 +#define IQ_I_U_VALUE_MINUS_2920 -16329824 // = -2920 +#define IQ_I_U_VALUE_MINUS_2919 -16324232 // = -2919 +#define IQ_I_U_VALUE_MINUS_2918 -16318639 // = -2918 +#define IQ_I_U_VALUE_MINUS_2917 -16313047 // = -2917 +#define IQ_I_U_VALUE_MINUS_2916 -16307454 // = -2916 +#define IQ_I_U_VALUE_MINUS_2915 -16301862 // = -2915 +#define IQ_I_U_VALUE_MINUS_2914 -16296270 // = -2914 +#define IQ_I_U_VALUE_MINUS_2913 -16290677 // = -2913 +#define IQ_I_U_VALUE_MINUS_2912 -16285085 // = -2912 +#define IQ_I_U_VALUE_MINUS_2911 -16279492 // = -2911 +#define IQ_I_U_VALUE_MINUS_2910 -16273900 // = -2910 +#define IQ_I_U_VALUE_MINUS_2909 -16268308 // = -2909 +#define IQ_I_U_VALUE_MINUS_2908 -16262715 // = -2908 +#define IQ_I_U_VALUE_MINUS_2907 -16257123 // = -2907 +#define IQ_I_U_VALUE_MINUS_2906 -16251530 // = -2906 +#define IQ_I_U_VALUE_MINUS_2905 -16245938 // = -2905 +#define IQ_I_U_VALUE_MINUS_2904 -16240346 // = -2904 +#define IQ_I_U_VALUE_MINUS_2903 -16234753 // = -2903 +#define IQ_I_U_VALUE_MINUS_2902 -16229161 // = -2902 +#define IQ_I_U_VALUE_MINUS_2901 -16223568 // = -2901 +#define IQ_I_U_VALUE_MINUS_2900 -16217976 // = -2900 +#define IQ_I_U_VALUE_MINUS_2899 -16212384 // = -2899 +#define IQ_I_U_VALUE_MINUS_2898 -16206791 // = -2898 +#define IQ_I_U_VALUE_MINUS_2897 -16201199 // = -2897 +#define IQ_I_U_VALUE_MINUS_2896 -16195606 // = -2896 +#define IQ_I_U_VALUE_MINUS_2895 -16190014 // = -2895 +#define IQ_I_U_VALUE_MINUS_2894 -16184422 // = -2894 +#define IQ_I_U_VALUE_MINUS_2893 -16178829 // = -2893 +#define IQ_I_U_VALUE_MINUS_2892 -16173237 // = -2892 +#define IQ_I_U_VALUE_MINUS_2891 -16167644 // = -2891 +#define IQ_I_U_VALUE_MINUS_2890 -16162052 // = -2890 +#define IQ_I_U_VALUE_MINUS_2889 -16156460 // = -2889 +#define IQ_I_U_VALUE_MINUS_2888 -16150867 // = -2888 +#define IQ_I_U_VALUE_MINUS_2887 -16145275 // = -2887 +#define IQ_I_U_VALUE_MINUS_2886 -16139682 // = -2886 +#define IQ_I_U_VALUE_MINUS_2885 -16134090 // = -2885 +#define IQ_I_U_VALUE_MINUS_2884 -16128497 // = -2884 +#define IQ_I_U_VALUE_MINUS_2883 -16122905 // = -2883 +#define IQ_I_U_VALUE_MINUS_2882 -16117313 // = -2882 +#define IQ_I_U_VALUE_MINUS_2881 -16111720 // = -2881 +#define IQ_I_U_VALUE_MINUS_2880 -16106128 // = -2880 +#define IQ_I_U_VALUE_MINUS_2879 -16100535 // = -2879 +#define IQ_I_U_VALUE_MINUS_2878 -16094943 // = -2878 +#define IQ_I_U_VALUE_MINUS_2877 -16089351 // = -2877 +#define IQ_I_U_VALUE_MINUS_2876 -16083758 // = -2876 +#define IQ_I_U_VALUE_MINUS_2875 -16078166 // = -2875 +#define IQ_I_U_VALUE_MINUS_2874 -16072573 // = -2874 +#define IQ_I_U_VALUE_MINUS_2873 -16066981 // = -2873 +#define IQ_I_U_VALUE_MINUS_2872 -16061389 // = -2872 +#define IQ_I_U_VALUE_MINUS_2871 -16055796 // = -2871 +#define IQ_I_U_VALUE_MINUS_2870 -16050204 // = -2870 +#define IQ_I_U_VALUE_MINUS_2869 -16044611 // = -2869 +#define IQ_I_U_VALUE_MINUS_2868 -16039019 // = -2868 +#define IQ_I_U_VALUE_MINUS_2867 -16033427 // = -2867 +#define IQ_I_U_VALUE_MINUS_2866 -16027834 // = -2866 +#define IQ_I_U_VALUE_MINUS_2865 -16022242 // = -2865 +#define IQ_I_U_VALUE_MINUS_2864 -16016649 // = -2864 +#define IQ_I_U_VALUE_MINUS_2863 -16011057 // = -2863 +#define IQ_I_U_VALUE_MINUS_2862 -16005465 // = -2862 +#define IQ_I_U_VALUE_MINUS_2861 -15999872 // = -2861 +#define IQ_I_U_VALUE_MINUS_2860 -15994280 // = -2860 +#define IQ_I_U_VALUE_MINUS_2859 -15988687 // = -2859 +#define IQ_I_U_VALUE_MINUS_2858 -15983095 // = -2858 +#define IQ_I_U_VALUE_MINUS_2857 -15977503 // = -2857 +#define IQ_I_U_VALUE_MINUS_2856 -15971910 // = -2856 +#define IQ_I_U_VALUE_MINUS_2855 -15966318 // = -2855 +#define IQ_I_U_VALUE_MINUS_2854 -15960725 // = -2854 +#define IQ_I_U_VALUE_MINUS_2853 -15955133 // = -2853 +#define IQ_I_U_VALUE_MINUS_2852 -15949541 // = -2852 +#define IQ_I_U_VALUE_MINUS_2851 -15943948 // = -2851 +#define IQ_I_U_VALUE_MINUS_2850 -15938356 // = -2850 +#define IQ_I_U_VALUE_MINUS_2849 -15932763 // = -2849 +#define IQ_I_U_VALUE_MINUS_2848 -15927171 // = -2848 +#define IQ_I_U_VALUE_MINUS_2847 -15921578 // = -2847 +#define IQ_I_U_VALUE_MINUS_2846 -15915986 // = -2846 +#define IQ_I_U_VALUE_MINUS_2845 -15910394 // = -2845 +#define IQ_I_U_VALUE_MINUS_2844 -15904801 // = -2844 +#define IQ_I_U_VALUE_MINUS_2843 -15899209 // = -2843 +#define IQ_I_U_VALUE_MINUS_2842 -15893616 // = -2842 +#define IQ_I_U_VALUE_MINUS_2841 -15888024 // = -2841 +#define IQ_I_U_VALUE_MINUS_2840 -15882432 // = -2840 +#define IQ_I_U_VALUE_MINUS_2839 -15876839 // = -2839 +#define IQ_I_U_VALUE_MINUS_2838 -15871247 // = -2838 +#define IQ_I_U_VALUE_MINUS_2837 -15865654 // = -2837 +#define IQ_I_U_VALUE_MINUS_2836 -15860062 // = -2836 +#define IQ_I_U_VALUE_MINUS_2835 -15854470 // = -2835 +#define IQ_I_U_VALUE_MINUS_2834 -15848877 // = -2834 +#define IQ_I_U_VALUE_MINUS_2833 -15843285 // = -2833 +#define IQ_I_U_VALUE_MINUS_2832 -15837692 // = -2832 +#define IQ_I_U_VALUE_MINUS_2831 -15832100 // = -2831 +#define IQ_I_U_VALUE_MINUS_2830 -15826508 // = -2830 +#define IQ_I_U_VALUE_MINUS_2829 -15820915 // = -2829 +#define IQ_I_U_VALUE_MINUS_2828 -15815323 // = -2828 +#define IQ_I_U_VALUE_MINUS_2827 -15809730 // = -2827 +#define IQ_I_U_VALUE_MINUS_2826 -15804138 // = -2826 +#define IQ_I_U_VALUE_MINUS_2825 -15798546 // = -2825 +#define IQ_I_U_VALUE_MINUS_2824 -15792953 // = -2824 +#define IQ_I_U_VALUE_MINUS_2823 -15787361 // = -2823 +#define IQ_I_U_VALUE_MINUS_2822 -15781768 // = -2822 +#define IQ_I_U_VALUE_MINUS_2821 -15776176 // = -2821 +#define IQ_I_U_VALUE_MINUS_2820 -15770584 // = -2820 +#define IQ_I_U_VALUE_MINUS_2819 -15764991 // = -2819 +#define IQ_I_U_VALUE_MINUS_2818 -15759399 // = -2818 +#define IQ_I_U_VALUE_MINUS_2817 -15753806 // = -2817 +#define IQ_I_U_VALUE_MINUS_2816 -15748214 // = -2816 +#define IQ_I_U_VALUE_MINUS_2815 -15742622 // = -2815 +#define IQ_I_U_VALUE_MINUS_2814 -15737029 // = -2814 +#define IQ_I_U_VALUE_MINUS_2813 -15731437 // = -2813 +#define IQ_I_U_VALUE_MINUS_2812 -15725844 // = -2812 +#define IQ_I_U_VALUE_MINUS_2811 -15720252 // = -2811 +#define IQ_I_U_VALUE_MINUS_2810 -15714659 // = -2810 +#define IQ_I_U_VALUE_MINUS_2809 -15709067 // = -2809 +#define IQ_I_U_VALUE_MINUS_2808 -15703475 // = -2808 +#define IQ_I_U_VALUE_MINUS_2807 -15697882 // = -2807 +#define IQ_I_U_VALUE_MINUS_2806 -15692290 // = -2806 +#define IQ_I_U_VALUE_MINUS_2805 -15686697 // = -2805 +#define IQ_I_U_VALUE_MINUS_2804 -15681105 // = -2804 +#define IQ_I_U_VALUE_MINUS_2803 -15675513 // = -2803 +#define IQ_I_U_VALUE_MINUS_2802 -15669920 // = -2802 +#define IQ_I_U_VALUE_MINUS_2801 -15664328 // = -2801 +#define IQ_I_U_VALUE_MINUS_2800 -15658735 // = -2800 +#define IQ_I_U_VALUE_MINUS_2799 -15653143 // = -2799 +#define IQ_I_U_VALUE_MINUS_2798 -15647551 // = -2798 +#define IQ_I_U_VALUE_MINUS_2797 -15641958 // = -2797 +#define IQ_I_U_VALUE_MINUS_2796 -15636366 // = -2796 +#define IQ_I_U_VALUE_MINUS_2795 -15630773 // = -2795 +#define IQ_I_U_VALUE_MINUS_2794 -15625181 // = -2794 +#define IQ_I_U_VALUE_MINUS_2793 -15619589 // = -2793 +#define IQ_I_U_VALUE_MINUS_2792 -15613996 // = -2792 +#define IQ_I_U_VALUE_MINUS_2791 -15608404 // = -2791 +#define IQ_I_U_VALUE_MINUS_2790 -15602811 // = -2790 +#define IQ_I_U_VALUE_MINUS_2789 -15597219 // = -2789 +#define IQ_I_U_VALUE_MINUS_2788 -15591627 // = -2788 +#define IQ_I_U_VALUE_MINUS_2787 -15586034 // = -2787 +#define IQ_I_U_VALUE_MINUS_2786 -15580442 // = -2786 +#define IQ_I_U_VALUE_MINUS_2785 -15574849 // = -2785 +#define IQ_I_U_VALUE_MINUS_2784 -15569257 // = -2784 +#define IQ_I_U_VALUE_MINUS_2783 -15563665 // = -2783 +#define IQ_I_U_VALUE_MINUS_2782 -15558072 // = -2782 +#define IQ_I_U_VALUE_MINUS_2781 -15552480 // = -2781 +#define IQ_I_U_VALUE_MINUS_2780 -15546887 // = -2780 +#define IQ_I_U_VALUE_MINUS_2779 -15541295 // = -2779 +#define IQ_I_U_VALUE_MINUS_2778 -15535703 // = -2778 +#define IQ_I_U_VALUE_MINUS_2777 -15530110 // = -2777 +#define IQ_I_U_VALUE_MINUS_2776 -15524518 // = -2776 +#define IQ_I_U_VALUE_MINUS_2775 -15518925 // = -2775 +#define IQ_I_U_VALUE_MINUS_2774 -15513333 // = -2774 +#define IQ_I_U_VALUE_MINUS_2773 -15507740 // = -2773 +#define IQ_I_U_VALUE_MINUS_2772 -15502148 // = -2772 +#define IQ_I_U_VALUE_MINUS_2771 -15496556 // = -2771 +#define IQ_I_U_VALUE_MINUS_2770 -15490963 // = -2770 +#define IQ_I_U_VALUE_MINUS_2769 -15485371 // = -2769 +#define IQ_I_U_VALUE_MINUS_2768 -15479778 // = -2768 +#define IQ_I_U_VALUE_MINUS_2767 -15474186 // = -2767 +#define IQ_I_U_VALUE_MINUS_2766 -15468594 // = -2766 +#define IQ_I_U_VALUE_MINUS_2765 -15463001 // = -2765 +#define IQ_I_U_VALUE_MINUS_2764 -15457409 // = -2764 +#define IQ_I_U_VALUE_MINUS_2763 -15451816 // = -2763 +#define IQ_I_U_VALUE_MINUS_2762 -15446224 // = -2762 +#define IQ_I_U_VALUE_MINUS_2761 -15440632 // = -2761 +#define IQ_I_U_VALUE_MINUS_2760 -15435039 // = -2760 +#define IQ_I_U_VALUE_MINUS_2759 -15429447 // = -2759 +#define IQ_I_U_VALUE_MINUS_2758 -15423854 // = -2758 +#define IQ_I_U_VALUE_MINUS_2757 -15418262 // = -2757 +#define IQ_I_U_VALUE_MINUS_2756 -15412670 // = -2756 +#define IQ_I_U_VALUE_MINUS_2755 -15407077 // = -2755 +#define IQ_I_U_VALUE_MINUS_2754 -15401485 // = -2754 +#define IQ_I_U_VALUE_MINUS_2753 -15395892 // = -2753 +#define IQ_I_U_VALUE_MINUS_2752 -15390300 // = -2752 +#define IQ_I_U_VALUE_MINUS_2751 -15384708 // = -2751 +#define IQ_I_U_VALUE_MINUS_2750 -15379115 // = -2750 +#define IQ_I_U_VALUE_MINUS_2749 -15373523 // = -2749 +#define IQ_I_U_VALUE_MINUS_2748 -15367930 // = -2748 +#define IQ_I_U_VALUE_MINUS_2747 -15362338 // = -2747 +#define IQ_I_U_VALUE_MINUS_2746 -15356746 // = -2746 +#define IQ_I_U_VALUE_MINUS_2745 -15351153 // = -2745 +#define IQ_I_U_VALUE_MINUS_2744 -15345561 // = -2744 +#define IQ_I_U_VALUE_MINUS_2743 -15339968 // = -2743 +#define IQ_I_U_VALUE_MINUS_2742 -15334376 // = -2742 +#define IQ_I_U_VALUE_MINUS_2741 -15328784 // = -2741 +#define IQ_I_U_VALUE_MINUS_2740 -15323191 // = -2740 +#define IQ_I_U_VALUE_MINUS_2739 -15317599 // = -2739 +#define IQ_I_U_VALUE_MINUS_2738 -15312006 // = -2738 +#define IQ_I_U_VALUE_MINUS_2737 -15306414 // = -2737 +#define IQ_I_U_VALUE_MINUS_2736 -15300821 // = -2736 +#define IQ_I_U_VALUE_MINUS_2735 -15295229 // = -2735 +#define IQ_I_U_VALUE_MINUS_2734 -15289637 // = -2734 +#define IQ_I_U_VALUE_MINUS_2733 -15284044 // = -2733 +#define IQ_I_U_VALUE_MINUS_2732 -15278452 // = -2732 +#define IQ_I_U_VALUE_MINUS_2731 -15272859 // = -2731 +#define IQ_I_U_VALUE_MINUS_2730 -15267267 // = -2730 +#define IQ_I_U_VALUE_MINUS_2729 -15261675 // = -2729 +#define IQ_I_U_VALUE_MINUS_2728 -15256082 // = -2728 +#define IQ_I_U_VALUE_MINUS_2727 -15250490 // = -2727 +#define IQ_I_U_VALUE_MINUS_2726 -15244897 // = -2726 +#define IQ_I_U_VALUE_MINUS_2725 -15239305 // = -2725 +#define IQ_I_U_VALUE_MINUS_2724 -15233713 // = -2724 +#define IQ_I_U_VALUE_MINUS_2723 -15228120 // = -2723 +#define IQ_I_U_VALUE_MINUS_2722 -15222528 // = -2722 +#define IQ_I_U_VALUE_MINUS_2721 -15216935 // = -2721 +#define IQ_I_U_VALUE_MINUS_2720 -15211343 // = -2720 +#define IQ_I_U_VALUE_MINUS_2719 -15205751 // = -2719 +#define IQ_I_U_VALUE_MINUS_2718 -15200158 // = -2718 +#define IQ_I_U_VALUE_MINUS_2717 -15194566 // = -2717 +#define IQ_I_U_VALUE_MINUS_2716 -15188973 // = -2716 +#define IQ_I_U_VALUE_MINUS_2715 -15183381 // = -2715 +#define IQ_I_U_VALUE_MINUS_2714 -15177789 // = -2714 +#define IQ_I_U_VALUE_MINUS_2713 -15172196 // = -2713 +#define IQ_I_U_VALUE_MINUS_2712 -15166604 // = -2712 +#define IQ_I_U_VALUE_MINUS_2711 -15161011 // = -2711 +#define IQ_I_U_VALUE_MINUS_2710 -15155419 // = -2710 +#define IQ_I_U_VALUE_MINUS_2709 -15149827 // = -2709 +#define IQ_I_U_VALUE_MINUS_2708 -15144234 // = -2708 +#define IQ_I_U_VALUE_MINUS_2707 -15138642 // = -2707 +#define IQ_I_U_VALUE_MINUS_2706 -15133049 // = -2706 +#define IQ_I_U_VALUE_MINUS_2705 -15127457 // = -2705 +#define IQ_I_U_VALUE_MINUS_2704 -15121865 // = -2704 +#define IQ_I_U_VALUE_MINUS_2703 -15116272 // = -2703 +#define IQ_I_U_VALUE_MINUS_2702 -15110680 // = -2702 +#define IQ_I_U_VALUE_MINUS_2701 -15105087 // = -2701 +#define IQ_I_U_VALUE_MINUS_2700 -15099495 // = -2700 +#define IQ_I_U_VALUE_MINUS_2699 -15093902 // = -2699 +#define IQ_I_U_VALUE_MINUS_2698 -15088310 // = -2698 +#define IQ_I_U_VALUE_MINUS_2697 -15082718 // = -2697 +#define IQ_I_U_VALUE_MINUS_2696 -15077125 // = -2696 +#define IQ_I_U_VALUE_MINUS_2695 -15071533 // = -2695 +#define IQ_I_U_VALUE_MINUS_2694 -15065940 // = -2694 +#define IQ_I_U_VALUE_MINUS_2693 -15060348 // = -2693 +#define IQ_I_U_VALUE_MINUS_2692 -15054756 // = -2692 +#define IQ_I_U_VALUE_MINUS_2691 -15049163 // = -2691 +#define IQ_I_U_VALUE_MINUS_2690 -15043571 // = -2690 +#define IQ_I_U_VALUE_MINUS_2689 -15037978 // = -2689 +#define IQ_I_U_VALUE_MINUS_2688 -15032386 // = -2688 +#define IQ_I_U_VALUE_MINUS_2687 -15026794 // = -2687 +#define IQ_I_U_VALUE_MINUS_2686 -15021201 // = -2686 +#define IQ_I_U_VALUE_MINUS_2685 -15015609 // = -2685 +#define IQ_I_U_VALUE_MINUS_2684 -15010016 // = -2684 +#define IQ_I_U_VALUE_MINUS_2683 -15004424 // = -2683 +#define IQ_I_U_VALUE_MINUS_2682 -14998832 // = -2682 +#define IQ_I_U_VALUE_MINUS_2681 -14993239 // = -2681 +#define IQ_I_U_VALUE_MINUS_2680 -14987647 // = -2680 +#define IQ_I_U_VALUE_MINUS_2679 -14982054 // = -2679 +#define IQ_I_U_VALUE_MINUS_2678 -14976462 // = -2678 +#define IQ_I_U_VALUE_MINUS_2677 -14970870 // = -2677 +#define IQ_I_U_VALUE_MINUS_2676 -14965277 // = -2676 +#define IQ_I_U_VALUE_MINUS_2675 -14959685 // = -2675 +#define IQ_I_U_VALUE_MINUS_2674 -14954092 // = -2674 +#define IQ_I_U_VALUE_MINUS_2673 -14948500 // = -2673 +#define IQ_I_U_VALUE_MINUS_2672 -14942908 // = -2672 +#define IQ_I_U_VALUE_MINUS_2671 -14937315 // = -2671 +#define IQ_I_U_VALUE_MINUS_2670 -14931723 // = -2670 +#define IQ_I_U_VALUE_MINUS_2669 -14926130 // = -2669 +#define IQ_I_U_VALUE_MINUS_2668 -14920538 // = -2668 +#define IQ_I_U_VALUE_MINUS_2667 -14914946 // = -2667 +#define IQ_I_U_VALUE_MINUS_2666 -14909353 // = -2666 +#define IQ_I_U_VALUE_MINUS_2665 -14903761 // = -2665 +#define IQ_I_U_VALUE_MINUS_2664 -14898168 // = -2664 +#define IQ_I_U_VALUE_MINUS_2663 -14892576 // = -2663 +#define IQ_I_U_VALUE_MINUS_2662 -14886983 // = -2662 +#define IQ_I_U_VALUE_MINUS_2661 -14881391 // = -2661 +#define IQ_I_U_VALUE_MINUS_2660 -14875799 // = -2660 +#define IQ_I_U_VALUE_MINUS_2659 -14870206 // = -2659 +#define IQ_I_U_VALUE_MINUS_2658 -14864614 // = -2658 +#define IQ_I_U_VALUE_MINUS_2657 -14859021 // = -2657 +#define IQ_I_U_VALUE_MINUS_2656 -14853429 // = -2656 +#define IQ_I_U_VALUE_MINUS_2655 -14847837 // = -2655 +#define IQ_I_U_VALUE_MINUS_2654 -14842244 // = -2654 +#define IQ_I_U_VALUE_MINUS_2653 -14836652 // = -2653 +#define IQ_I_U_VALUE_MINUS_2652 -14831059 // = -2652 +#define IQ_I_U_VALUE_MINUS_2651 -14825467 // = -2651 +#define IQ_I_U_VALUE_MINUS_2650 -14819875 // = -2650 +#define IQ_I_U_VALUE_MINUS_2649 -14814282 // = -2649 +#define IQ_I_U_VALUE_MINUS_2648 -14808690 // = -2648 +#define IQ_I_U_VALUE_MINUS_2647 -14803097 // = -2647 +#define IQ_I_U_VALUE_MINUS_2646 -14797505 // = -2646 +#define IQ_I_U_VALUE_MINUS_2645 -14791913 // = -2645 +#define IQ_I_U_VALUE_MINUS_2644 -14786320 // = -2644 +#define IQ_I_U_VALUE_MINUS_2643 -14780728 // = -2643 +#define IQ_I_U_VALUE_MINUS_2642 -14775135 // = -2642 +#define IQ_I_U_VALUE_MINUS_2641 -14769543 // = -2641 +#define IQ_I_U_VALUE_MINUS_2640 -14763951 // = -2640 +#define IQ_I_U_VALUE_MINUS_2639 -14758358 // = -2639 +#define IQ_I_U_VALUE_MINUS_2638 -14752766 // = -2638 +#define IQ_I_U_VALUE_MINUS_2637 -14747173 // = -2637 +#define IQ_I_U_VALUE_MINUS_2636 -14741581 // = -2636 +#define IQ_I_U_VALUE_MINUS_2635 -14735989 // = -2635 +#define IQ_I_U_VALUE_MINUS_2634 -14730396 // = -2634 +#define IQ_I_U_VALUE_MINUS_2633 -14724804 // = -2633 +#define IQ_I_U_VALUE_MINUS_2632 -14719211 // = -2632 +#define IQ_I_U_VALUE_MINUS_2631 -14713619 // = -2631 +#define IQ_I_U_VALUE_MINUS_2630 -14708027 // = -2630 +#define IQ_I_U_VALUE_MINUS_2629 -14702434 // = -2629 +#define IQ_I_U_VALUE_MINUS_2628 -14696842 // = -2628 +#define IQ_I_U_VALUE_MINUS_2627 -14691249 // = -2627 +#define IQ_I_U_VALUE_MINUS_2626 -14685657 // = -2626 +#define IQ_I_U_VALUE_MINUS_2625 -14680064 // = -2625 +#define IQ_I_U_VALUE_MINUS_2624 -14674472 // = -2624 +#define IQ_I_U_VALUE_MINUS_2623 -14668880 // = -2623 +#define IQ_I_U_VALUE_MINUS_2622 -14663287 // = -2622 +#define IQ_I_U_VALUE_MINUS_2621 -14657695 // = -2621 +#define IQ_I_U_VALUE_MINUS_2620 -14652102 // = -2620 +#define IQ_I_U_VALUE_MINUS_2619 -14646510 // = -2619 +#define IQ_I_U_VALUE_MINUS_2618 -14640918 // = -2618 +#define IQ_I_U_VALUE_MINUS_2617 -14635325 // = -2617 +#define IQ_I_U_VALUE_MINUS_2616 -14629733 // = -2616 +#define IQ_I_U_VALUE_MINUS_2615 -14624140 // = -2615 +#define IQ_I_U_VALUE_MINUS_2614 -14618548 // = -2614 +#define IQ_I_U_VALUE_MINUS_2613 -14612956 // = -2613 +#define IQ_I_U_VALUE_MINUS_2612 -14607363 // = -2612 +#define IQ_I_U_VALUE_MINUS_2611 -14601771 // = -2611 +#define IQ_I_U_VALUE_MINUS_2610 -14596178 // = -2610 +#define IQ_I_U_VALUE_MINUS_2609 -14590586 // = -2609 +#define IQ_I_U_VALUE_MINUS_2608 -14584994 // = -2608 +#define IQ_I_U_VALUE_MINUS_2607 -14579401 // = -2607 +#define IQ_I_U_VALUE_MINUS_2606 -14573809 // = -2606 +#define IQ_I_U_VALUE_MINUS_2605 -14568216 // = -2605 +#define IQ_I_U_VALUE_MINUS_2604 -14562624 // = -2604 +#define IQ_I_U_VALUE_MINUS_2603 -14557032 // = -2603 +#define IQ_I_U_VALUE_MINUS_2602 -14551439 // = -2602 +#define IQ_I_U_VALUE_MINUS_2601 -14545847 // = -2601 +#define IQ_I_U_VALUE_MINUS_2600 -14540254 // = -2600 +#define IQ_I_U_VALUE_MINUS_2599 -14534662 // = -2599 +#define IQ_I_U_VALUE_MINUS_2598 -14529070 // = -2598 +#define IQ_I_U_VALUE_MINUS_2597 -14523477 // = -2597 +#define IQ_I_U_VALUE_MINUS_2596 -14517885 // = -2596 +#define IQ_I_U_VALUE_MINUS_2595 -14512292 // = -2595 +#define IQ_I_U_VALUE_MINUS_2594 -14506700 // = -2594 +#define IQ_I_U_VALUE_MINUS_2593 -14501108 // = -2593 +#define IQ_I_U_VALUE_MINUS_2592 -14495515 // = -2592 +#define IQ_I_U_VALUE_MINUS_2591 -14489923 // = -2591 +#define IQ_I_U_VALUE_MINUS_2590 -14484330 // = -2590 +#define IQ_I_U_VALUE_MINUS_2589 -14478738 // = -2589 +#define IQ_I_U_VALUE_MINUS_2588 -14473146 // = -2588 +#define IQ_I_U_VALUE_MINUS_2587 -14467553 // = -2587 +#define IQ_I_U_VALUE_MINUS_2586 -14461961 // = -2586 +#define IQ_I_U_VALUE_MINUS_2585 -14456368 // = -2585 +#define IQ_I_U_VALUE_MINUS_2584 -14450776 // = -2584 +#define IQ_I_U_VALUE_MINUS_2583 -14445183 // = -2583 +#define IQ_I_U_VALUE_MINUS_2582 -14439591 // = -2582 +#define IQ_I_U_VALUE_MINUS_2581 -14433999 // = -2581 +#define IQ_I_U_VALUE_MINUS_2580 -14428406 // = -2580 +#define IQ_I_U_VALUE_MINUS_2579 -14422814 // = -2579 +#define IQ_I_U_VALUE_MINUS_2578 -14417221 // = -2578 +#define IQ_I_U_VALUE_MINUS_2577 -14411629 // = -2577 +#define IQ_I_U_VALUE_MINUS_2576 -14406037 // = -2576 +#define IQ_I_U_VALUE_MINUS_2575 -14400444 // = -2575 +#define IQ_I_U_VALUE_MINUS_2574 -14394852 // = -2574 +#define IQ_I_U_VALUE_MINUS_2573 -14389259 // = -2573 +#define IQ_I_U_VALUE_MINUS_2572 -14383667 // = -2572 +#define IQ_I_U_VALUE_MINUS_2571 -14378075 // = -2571 +#define IQ_I_U_VALUE_MINUS_2570 -14372482 // = -2570 +#define IQ_I_U_VALUE_MINUS_2569 -14366890 // = -2569 +#define IQ_I_U_VALUE_MINUS_2568 -14361297 // = -2568 +#define IQ_I_U_VALUE_MINUS_2567 -14355705 // = -2567 +#define IQ_I_U_VALUE_MINUS_2566 -14350113 // = -2566 +#define IQ_I_U_VALUE_MINUS_2565 -14344520 // = -2565 +#define IQ_I_U_VALUE_MINUS_2564 -14338928 // = -2564 +#define IQ_I_U_VALUE_MINUS_2563 -14333335 // = -2563 +#define IQ_I_U_VALUE_MINUS_2562 -14327743 // = -2562 +#define IQ_I_U_VALUE_MINUS_2561 -14322151 // = -2561 +#define IQ_I_U_VALUE_MINUS_2560 -14316558 // = -2560 +#define IQ_I_U_VALUE_MINUS_2559 -14310966 // = -2559 +#define IQ_I_U_VALUE_MINUS_2558 -14305373 // = -2558 +#define IQ_I_U_VALUE_MINUS_2557 -14299781 // = -2557 +#define IQ_I_U_VALUE_MINUS_2556 -14294189 // = -2556 +#define IQ_I_U_VALUE_MINUS_2555 -14288596 // = -2555 +#define IQ_I_U_VALUE_MINUS_2554 -14283004 // = -2554 +#define IQ_I_U_VALUE_MINUS_2553 -14277411 // = -2553 +#define IQ_I_U_VALUE_MINUS_2552 -14271819 // = -2552 +#define IQ_I_U_VALUE_MINUS_2551 -14266227 // = -2551 +#define IQ_I_U_VALUE_MINUS_2550 -14260634 // = -2550 +#define IQ_I_U_VALUE_MINUS_2549 -14255042 // = -2549 +#define IQ_I_U_VALUE_MINUS_2548 -14249449 // = -2548 +#define IQ_I_U_VALUE_MINUS_2547 -14243857 // = -2547 +#define IQ_I_U_VALUE_MINUS_2546 -14238264 // = -2546 +#define IQ_I_U_VALUE_MINUS_2545 -14232672 // = -2545 +#define IQ_I_U_VALUE_MINUS_2544 -14227080 // = -2544 +#define IQ_I_U_VALUE_MINUS_2543 -14221487 // = -2543 +#define IQ_I_U_VALUE_MINUS_2542 -14215895 // = -2542 +#define IQ_I_U_VALUE_MINUS_2541 -14210302 // = -2541 +#define IQ_I_U_VALUE_MINUS_2540 -14204710 // = -2540 +#define IQ_I_U_VALUE_MINUS_2539 -14199118 // = -2539 +#define IQ_I_U_VALUE_MINUS_2538 -14193525 // = -2538 +#define IQ_I_U_VALUE_MINUS_2537 -14187933 // = -2537 +#define IQ_I_U_VALUE_MINUS_2536 -14182340 // = -2536 +#define IQ_I_U_VALUE_MINUS_2535 -14176748 // = -2535 +#define IQ_I_U_VALUE_MINUS_2534 -14171156 // = -2534 +#define IQ_I_U_VALUE_MINUS_2533 -14165563 // = -2533 +#define IQ_I_U_VALUE_MINUS_2532 -14159971 // = -2532 +#define IQ_I_U_VALUE_MINUS_2531 -14154378 // = -2531 +#define IQ_I_U_VALUE_MINUS_2530 -14148786 // = -2530 +#define IQ_I_U_VALUE_MINUS_2529 -14143194 // = -2529 +#define IQ_I_U_VALUE_MINUS_2528 -14137601 // = -2528 +#define IQ_I_U_VALUE_MINUS_2527 -14132009 // = -2527 +#define IQ_I_U_VALUE_MINUS_2526 -14126416 // = -2526 +#define IQ_I_U_VALUE_MINUS_2525 -14120824 // = -2525 +#define IQ_I_U_VALUE_MINUS_2524 -14115232 // = -2524 +#define IQ_I_U_VALUE_MINUS_2523 -14109639 // = -2523 +#define IQ_I_U_VALUE_MINUS_2522 -14104047 // = -2522 +#define IQ_I_U_VALUE_MINUS_2521 -14098454 // = -2521 +#define IQ_I_U_VALUE_MINUS_2520 -14092862 // = -2520 +#define IQ_I_U_VALUE_MINUS_2519 -14087270 // = -2519 +#define IQ_I_U_VALUE_MINUS_2518 -14081677 // = -2518 +#define IQ_I_U_VALUE_MINUS_2517 -14076085 // = -2517 +#define IQ_I_U_VALUE_MINUS_2516 -14070492 // = -2516 +#define IQ_I_U_VALUE_MINUS_2515 -14064900 // = -2515 +#define IQ_I_U_VALUE_MINUS_2514 -14059308 // = -2514 +#define IQ_I_U_VALUE_MINUS_2513 -14053715 // = -2513 +#define IQ_I_U_VALUE_MINUS_2512 -14048123 // = -2512 +#define IQ_I_U_VALUE_MINUS_2511 -14042530 // = -2511 +#define IQ_I_U_VALUE_MINUS_2510 -14036938 // = -2510 +#define IQ_I_U_VALUE_MINUS_2509 -14031345 // = -2509 +#define IQ_I_U_VALUE_MINUS_2508 -14025753 // = -2508 +#define IQ_I_U_VALUE_MINUS_2507 -14020161 // = -2507 +#define IQ_I_U_VALUE_MINUS_2506 -14014568 // = -2506 +#define IQ_I_U_VALUE_MINUS_2505 -14008976 // = -2505 +#define IQ_I_U_VALUE_MINUS_2504 -14003383 // = -2504 +#define IQ_I_U_VALUE_MINUS_2503 -13997791 // = -2503 +#define IQ_I_U_VALUE_MINUS_2502 -13992199 // = -2502 +#define IQ_I_U_VALUE_MINUS_2501 -13986606 // = -2501 +#define IQ_I_U_VALUE_MINUS_2500 -13981014 // = -2500 +#define IQ_I_U_VALUE_MINUS_2499 -13975421 // = -2499 +#define IQ_I_U_VALUE_MINUS_2498 -13969829 // = -2498 +#define IQ_I_U_VALUE_MINUS_2497 -13964237 // = -2497 +#define IQ_I_U_VALUE_MINUS_2496 -13958644 // = -2496 +#define IQ_I_U_VALUE_MINUS_2495 -13953052 // = -2495 +#define IQ_I_U_VALUE_MINUS_2494 -13947459 // = -2494 +#define IQ_I_U_VALUE_MINUS_2493 -13941867 // = -2493 +#define IQ_I_U_VALUE_MINUS_2492 -13936275 // = -2492 +#define IQ_I_U_VALUE_MINUS_2491 -13930682 // = -2491 +#define IQ_I_U_VALUE_MINUS_2490 -13925090 // = -2490 +#define IQ_I_U_VALUE_MINUS_2489 -13919497 // = -2489 +#define IQ_I_U_VALUE_MINUS_2488 -13913905 // = -2488 +#define IQ_I_U_VALUE_MINUS_2487 -13908313 // = -2487 +#define IQ_I_U_VALUE_MINUS_2486 -13902720 // = -2486 +#define IQ_I_U_VALUE_MINUS_2485 -13897128 // = -2485 +#define IQ_I_U_VALUE_MINUS_2484 -13891535 // = -2484 +#define IQ_I_U_VALUE_MINUS_2483 -13885943 // = -2483 +#define IQ_I_U_VALUE_MINUS_2482 -13880351 // = -2482 +#define IQ_I_U_VALUE_MINUS_2481 -13874758 // = -2481 +#define IQ_I_U_VALUE_MINUS_2480 -13869166 // = -2480 +#define IQ_I_U_VALUE_MINUS_2479 -13863573 // = -2479 +#define IQ_I_U_VALUE_MINUS_2478 -13857981 // = -2478 +#define IQ_I_U_VALUE_MINUS_2477 -13852389 // = -2477 +#define IQ_I_U_VALUE_MINUS_2476 -13846796 // = -2476 +#define IQ_I_U_VALUE_MINUS_2475 -13841204 // = -2475 +#define IQ_I_U_VALUE_MINUS_2474 -13835611 // = -2474 +#define IQ_I_U_VALUE_MINUS_2473 -13830019 // = -2473 +#define IQ_I_U_VALUE_MINUS_2472 -13824426 // = -2472 +#define IQ_I_U_VALUE_MINUS_2471 -13818834 // = -2471 +#define IQ_I_U_VALUE_MINUS_2470 -13813242 // = -2470 +#define IQ_I_U_VALUE_MINUS_2469 -13807649 // = -2469 +#define IQ_I_U_VALUE_MINUS_2468 -13802057 // = -2468 +#define IQ_I_U_VALUE_MINUS_2467 -13796464 // = -2467 +#define IQ_I_U_VALUE_MINUS_2466 -13790872 // = -2466 +#define IQ_I_U_VALUE_MINUS_2465 -13785280 // = -2465 +#define IQ_I_U_VALUE_MINUS_2464 -13779687 // = -2464 +#define IQ_I_U_VALUE_MINUS_2463 -13774095 // = -2463 +#define IQ_I_U_VALUE_MINUS_2462 -13768502 // = -2462 +#define IQ_I_U_VALUE_MINUS_2461 -13762910 // = -2461 +#define IQ_I_U_VALUE_MINUS_2460 -13757318 // = -2460 +#define IQ_I_U_VALUE_MINUS_2459 -13751725 // = -2459 +#define IQ_I_U_VALUE_MINUS_2458 -13746133 // = -2458 +#define IQ_I_U_VALUE_MINUS_2457 -13740540 // = -2457 +#define IQ_I_U_VALUE_MINUS_2456 -13734948 // = -2456 +#define IQ_I_U_VALUE_MINUS_2455 -13729356 // = -2455 +#define IQ_I_U_VALUE_MINUS_2454 -13723763 // = -2454 +#define IQ_I_U_VALUE_MINUS_2453 -13718171 // = -2453 +#define IQ_I_U_VALUE_MINUS_2452 -13712578 // = -2452 +#define IQ_I_U_VALUE_MINUS_2451 -13706986 // = -2451 +#define IQ_I_U_VALUE_MINUS_2450 -13701394 // = -2450 +#define IQ_I_U_VALUE_MINUS_2449 -13695801 // = -2449 +#define IQ_I_U_VALUE_MINUS_2448 -13690209 // = -2448 +#define IQ_I_U_VALUE_MINUS_2447 -13684616 // = -2447 +#define IQ_I_U_VALUE_MINUS_2446 -13679024 // = -2446 +#define IQ_I_U_VALUE_MINUS_2445 -13673432 // = -2445 +#define IQ_I_U_VALUE_MINUS_2444 -13667839 // = -2444 +#define IQ_I_U_VALUE_MINUS_2443 -13662247 // = -2443 +#define IQ_I_U_VALUE_MINUS_2442 -13656654 // = -2442 +#define IQ_I_U_VALUE_MINUS_2441 -13651062 // = -2441 +#define IQ_I_U_VALUE_MINUS_2440 -13645470 // = -2440 +#define IQ_I_U_VALUE_MINUS_2439 -13639877 // = -2439 +#define IQ_I_U_VALUE_MINUS_2438 -13634285 // = -2438 +#define IQ_I_U_VALUE_MINUS_2437 -13628692 // = -2437 +#define IQ_I_U_VALUE_MINUS_2436 -13623100 // = -2436 +#define IQ_I_U_VALUE_MINUS_2435 -13617507 // = -2435 +#define IQ_I_U_VALUE_MINUS_2434 -13611915 // = -2434 +#define IQ_I_U_VALUE_MINUS_2433 -13606323 // = -2433 +#define IQ_I_U_VALUE_MINUS_2432 -13600730 // = -2432 +#define IQ_I_U_VALUE_MINUS_2431 -13595138 // = -2431 +#define IQ_I_U_VALUE_MINUS_2430 -13589545 // = -2430 +#define IQ_I_U_VALUE_MINUS_2429 -13583953 // = -2429 +#define IQ_I_U_VALUE_MINUS_2428 -13578361 // = -2428 +#define IQ_I_U_VALUE_MINUS_2427 -13572768 // = -2427 +#define IQ_I_U_VALUE_MINUS_2426 -13567176 // = -2426 +#define IQ_I_U_VALUE_MINUS_2425 -13561583 // = -2425 +#define IQ_I_U_VALUE_MINUS_2424 -13555991 // = -2424 +#define IQ_I_U_VALUE_MINUS_2423 -13550399 // = -2423 +#define IQ_I_U_VALUE_MINUS_2422 -13544806 // = -2422 +#define IQ_I_U_VALUE_MINUS_2421 -13539214 // = -2421 +#define IQ_I_U_VALUE_MINUS_2420 -13533621 // = -2420 +#define IQ_I_U_VALUE_MINUS_2419 -13528029 // = -2419 +#define IQ_I_U_VALUE_MINUS_2418 -13522437 // = -2418 +#define IQ_I_U_VALUE_MINUS_2417 -13516844 // = -2417 +#define IQ_I_U_VALUE_MINUS_2416 -13511252 // = -2416 +#define IQ_I_U_VALUE_MINUS_2415 -13505659 // = -2415 +#define IQ_I_U_VALUE_MINUS_2414 -13500067 // = -2414 +#define IQ_I_U_VALUE_MINUS_2413 -13494475 // = -2413 +#define IQ_I_U_VALUE_MINUS_2412 -13488882 // = -2412 +#define IQ_I_U_VALUE_MINUS_2411 -13483290 // = -2411 +#define IQ_I_U_VALUE_MINUS_2410 -13477697 // = -2410 +#define IQ_I_U_VALUE_MINUS_2409 -13472105 // = -2409 +#define IQ_I_U_VALUE_MINUS_2408 -13466513 // = -2408 +#define IQ_I_U_VALUE_MINUS_2407 -13460920 // = -2407 +#define IQ_I_U_VALUE_MINUS_2406 -13455328 // = -2406 +#define IQ_I_U_VALUE_MINUS_2405 -13449735 // = -2405 +#define IQ_I_U_VALUE_MINUS_2404 -13444143 // = -2404 +#define IQ_I_U_VALUE_MINUS_2403 -13438551 // = -2403 +#define IQ_I_U_VALUE_MINUS_2402 -13432958 // = -2402 +#define IQ_I_U_VALUE_MINUS_2401 -13427366 // = -2401 +#define IQ_I_U_VALUE_MINUS_2400 -13421773 // = -2400 +#define IQ_I_U_VALUE_MINUS_2399 -13416181 // = -2399 +#define IQ_I_U_VALUE_MINUS_2398 -13410588 // = -2398 +#define IQ_I_U_VALUE_MINUS_2397 -13404996 // = -2397 +#define IQ_I_U_VALUE_MINUS_2396 -13399404 // = -2396 +#define IQ_I_U_VALUE_MINUS_2395 -13393811 // = -2395 +#define IQ_I_U_VALUE_MINUS_2394 -13388219 // = -2394 +#define IQ_I_U_VALUE_MINUS_2393 -13382626 // = -2393 +#define IQ_I_U_VALUE_MINUS_2392 -13377034 // = -2392 +#define IQ_I_U_VALUE_MINUS_2391 -13371442 // = -2391 +#define IQ_I_U_VALUE_MINUS_2390 -13365849 // = -2390 +#define IQ_I_U_VALUE_MINUS_2389 -13360257 // = -2389 +#define IQ_I_U_VALUE_MINUS_2388 -13354664 // = -2388 +#define IQ_I_U_VALUE_MINUS_2387 -13349072 // = -2387 +#define IQ_I_U_VALUE_MINUS_2386 -13343480 // = -2386 +#define IQ_I_U_VALUE_MINUS_2385 -13337887 // = -2385 +#define IQ_I_U_VALUE_MINUS_2384 -13332295 // = -2384 +#define IQ_I_U_VALUE_MINUS_2383 -13326702 // = -2383 +#define IQ_I_U_VALUE_MINUS_2382 -13321110 // = -2382 +#define IQ_I_U_VALUE_MINUS_2381 -13315518 // = -2381 +#define IQ_I_U_VALUE_MINUS_2380 -13309925 // = -2380 +#define IQ_I_U_VALUE_MINUS_2379 -13304333 // = -2379 +#define IQ_I_U_VALUE_MINUS_2378 -13298740 // = -2378 +#define IQ_I_U_VALUE_MINUS_2377 -13293148 // = -2377 +#define IQ_I_U_VALUE_MINUS_2376 -13287556 // = -2376 +#define IQ_I_U_VALUE_MINUS_2375 -13281963 // = -2375 +#define IQ_I_U_VALUE_MINUS_2374 -13276371 // = -2374 +#define IQ_I_U_VALUE_MINUS_2373 -13270778 // = -2373 +#define IQ_I_U_VALUE_MINUS_2372 -13265186 // = -2372 +#define IQ_I_U_VALUE_MINUS_2371 -13259594 // = -2371 +#define IQ_I_U_VALUE_MINUS_2370 -13254001 // = -2370 +#define IQ_I_U_VALUE_MINUS_2369 -13248409 // = -2369 +#define IQ_I_U_VALUE_MINUS_2368 -13242816 // = -2368 +#define IQ_I_U_VALUE_MINUS_2367 -13237224 // = -2367 +#define IQ_I_U_VALUE_MINUS_2366 -13231632 // = -2366 +#define IQ_I_U_VALUE_MINUS_2365 -13226039 // = -2365 +#define IQ_I_U_VALUE_MINUS_2364 -13220447 // = -2364 +#define IQ_I_U_VALUE_MINUS_2363 -13214854 // = -2363 +#define IQ_I_U_VALUE_MINUS_2362 -13209262 // = -2362 +#define IQ_I_U_VALUE_MINUS_2361 -13203669 // = -2361 +#define IQ_I_U_VALUE_MINUS_2360 -13198077 // = -2360 +#define IQ_I_U_VALUE_MINUS_2359 -13192485 // = -2359 +#define IQ_I_U_VALUE_MINUS_2358 -13186892 // = -2358 +#define IQ_I_U_VALUE_MINUS_2357 -13181300 // = -2357 +#define IQ_I_U_VALUE_MINUS_2356 -13175707 // = -2356 +#define IQ_I_U_VALUE_MINUS_2355 -13170115 // = -2355 +#define IQ_I_U_VALUE_MINUS_2354 -13164523 // = -2354 +#define IQ_I_U_VALUE_MINUS_2353 -13158930 // = -2353 +#define IQ_I_U_VALUE_MINUS_2352 -13153338 // = -2352 +#define IQ_I_U_VALUE_MINUS_2351 -13147745 // = -2351 +#define IQ_I_U_VALUE_MINUS_2350 -13142153 // = -2350 +#define IQ_I_U_VALUE_MINUS_2349 -13136561 // = -2349 +#define IQ_I_U_VALUE_MINUS_2348 -13130968 // = -2348 +#define IQ_I_U_VALUE_MINUS_2347 -13125376 // = -2347 +#define IQ_I_U_VALUE_MINUS_2346 -13119783 // = -2346 +#define IQ_I_U_VALUE_MINUS_2345 -13114191 // = -2345 +#define IQ_I_U_VALUE_MINUS_2344 -13108599 // = -2344 +#define IQ_I_U_VALUE_MINUS_2343 -13103006 // = -2343 +#define IQ_I_U_VALUE_MINUS_2342 -13097414 // = -2342 +#define IQ_I_U_VALUE_MINUS_2341 -13091821 // = -2341 +#define IQ_I_U_VALUE_MINUS_2340 -13086229 // = -2340 +#define IQ_I_U_VALUE_MINUS_2339 -13080637 // = -2339 +#define IQ_I_U_VALUE_MINUS_2338 -13075044 // = -2338 +#define IQ_I_U_VALUE_MINUS_2337 -13069452 // = -2337 +#define IQ_I_U_VALUE_MINUS_2336 -13063859 // = -2336 +#define IQ_I_U_VALUE_MINUS_2335 -13058267 // = -2335 +#define IQ_I_U_VALUE_MINUS_2334 -13052675 // = -2334 +#define IQ_I_U_VALUE_MINUS_2333 -13047082 // = -2333 +#define IQ_I_U_VALUE_MINUS_2332 -13041490 // = -2332 +#define IQ_I_U_VALUE_MINUS_2331 -13035897 // = -2331 +#define IQ_I_U_VALUE_MINUS_2330 -13030305 // = -2330 +#define IQ_I_U_VALUE_MINUS_2329 -13024713 // = -2329 +#define IQ_I_U_VALUE_MINUS_2328 -13019120 // = -2328 +#define IQ_I_U_VALUE_MINUS_2327 -13013528 // = -2327 +#define IQ_I_U_VALUE_MINUS_2326 -13007935 // = -2326 +#define IQ_I_U_VALUE_MINUS_2325 -13002343 // = -2325 +#define IQ_I_U_VALUE_MINUS_2324 -12996750 // = -2324 +#define IQ_I_U_VALUE_MINUS_2323 -12991158 // = -2323 +#define IQ_I_U_VALUE_MINUS_2322 -12985566 // = -2322 +#define IQ_I_U_VALUE_MINUS_2321 -12979973 // = -2321 +#define IQ_I_U_VALUE_MINUS_2320 -12974381 // = -2320 +#define IQ_I_U_VALUE_MINUS_2319 -12968788 // = -2319 +#define IQ_I_U_VALUE_MINUS_2318 -12963196 // = -2318 +#define IQ_I_U_VALUE_MINUS_2317 -12957604 // = -2317 +#define IQ_I_U_VALUE_MINUS_2316 -12952011 // = -2316 +#define IQ_I_U_VALUE_MINUS_2315 -12946419 // = -2315 +#define IQ_I_U_VALUE_MINUS_2314 -12940826 // = -2314 +#define IQ_I_U_VALUE_MINUS_2313 -12935234 // = -2313 +#define IQ_I_U_VALUE_MINUS_2312 -12929642 // = -2312 +#define IQ_I_U_VALUE_MINUS_2311 -12924049 // = -2311 +#define IQ_I_U_VALUE_MINUS_2310 -12918457 // = -2310 +#define IQ_I_U_VALUE_MINUS_2309 -12912864 // = -2309 +#define IQ_I_U_VALUE_MINUS_2308 -12907272 // = -2308 +#define IQ_I_U_VALUE_MINUS_2307 -12901680 // = -2307 +#define IQ_I_U_VALUE_MINUS_2306 -12896087 // = -2306 +#define IQ_I_U_VALUE_MINUS_2305 -12890495 // = -2305 +#define IQ_I_U_VALUE_MINUS_2304 -12884902 // = -2304 +#define IQ_I_U_VALUE_MINUS_2303 -12879310 // = -2303 +#define IQ_I_U_VALUE_MINUS_2302 -12873718 // = -2302 +#define IQ_I_U_VALUE_MINUS_2301 -12868125 // = -2301 +#define IQ_I_U_VALUE_MINUS_2300 -12862533 // = -2300 +#define IQ_I_U_VALUE_MINUS_2299 -12856940 // = -2299 +#define IQ_I_U_VALUE_MINUS_2298 -12851348 // = -2298 +#define IQ_I_U_VALUE_MINUS_2297 -12845756 // = -2297 +#define IQ_I_U_VALUE_MINUS_2296 -12840163 // = -2296 +#define IQ_I_U_VALUE_MINUS_2295 -12834571 // = -2295 +#define IQ_I_U_VALUE_MINUS_2294 -12828978 // = -2294 +#define IQ_I_U_VALUE_MINUS_2293 -12823386 // = -2293 +#define IQ_I_U_VALUE_MINUS_2292 -12817794 // = -2292 +#define IQ_I_U_VALUE_MINUS_2291 -12812201 // = -2291 +#define IQ_I_U_VALUE_MINUS_2290 -12806609 // = -2290 +#define IQ_I_U_VALUE_MINUS_2289 -12801016 // = -2289 +#define IQ_I_U_VALUE_MINUS_2288 -12795424 // = -2288 +#define IQ_I_U_VALUE_MINUS_2287 -12789831 // = -2287 +#define IQ_I_U_VALUE_MINUS_2286 -12784239 // = -2286 +#define IQ_I_U_VALUE_MINUS_2285 -12778647 // = -2285 +#define IQ_I_U_VALUE_MINUS_2284 -12773054 // = -2284 +#define IQ_I_U_VALUE_MINUS_2283 -12767462 // = -2283 +#define IQ_I_U_VALUE_MINUS_2282 -12761869 // = -2282 +#define IQ_I_U_VALUE_MINUS_2281 -12756277 // = -2281 +#define IQ_I_U_VALUE_MINUS_2280 -12750685 // = -2280 +#define IQ_I_U_VALUE_MINUS_2279 -12745092 // = -2279 +#define IQ_I_U_VALUE_MINUS_2278 -12739500 // = -2278 +#define IQ_I_U_VALUE_MINUS_2277 -12733907 // = -2277 +#define IQ_I_U_VALUE_MINUS_2276 -12728315 // = -2276 +#define IQ_I_U_VALUE_MINUS_2275 -12722723 // = -2275 +#define IQ_I_U_VALUE_MINUS_2274 -12717130 // = -2274 +#define IQ_I_U_VALUE_MINUS_2273 -12711538 // = -2273 +#define IQ_I_U_VALUE_MINUS_2272 -12705945 // = -2272 +#define IQ_I_U_VALUE_MINUS_2271 -12700353 // = -2271 +#define IQ_I_U_VALUE_MINUS_2270 -12694761 // = -2270 +#define IQ_I_U_VALUE_MINUS_2269 -12689168 // = -2269 +#define IQ_I_U_VALUE_MINUS_2268 -12683576 // = -2268 +#define IQ_I_U_VALUE_MINUS_2267 -12677983 // = -2267 +#define IQ_I_U_VALUE_MINUS_2266 -12672391 // = -2266 +#define IQ_I_U_VALUE_MINUS_2265 -12666799 // = -2265 +#define IQ_I_U_VALUE_MINUS_2264 -12661206 // = -2264 +#define IQ_I_U_VALUE_MINUS_2263 -12655614 // = -2263 +#define IQ_I_U_VALUE_MINUS_2262 -12650021 // = -2262 +#define IQ_I_U_VALUE_MINUS_2261 -12644429 // = -2261 +#define IQ_I_U_VALUE_MINUS_2260 -12638837 // = -2260 +#define IQ_I_U_VALUE_MINUS_2259 -12633244 // = -2259 +#define IQ_I_U_VALUE_MINUS_2258 -12627652 // = -2258 +#define IQ_I_U_VALUE_MINUS_2257 -12622059 // = -2257 +#define IQ_I_U_VALUE_MINUS_2256 -12616467 // = -2256 +#define IQ_I_U_VALUE_MINUS_2255 -12610875 // = -2255 +#define IQ_I_U_VALUE_MINUS_2254 -12605282 // = -2254 +#define IQ_I_U_VALUE_MINUS_2253 -12599690 // = -2253 +#define IQ_I_U_VALUE_MINUS_2252 -12594097 // = -2252 +#define IQ_I_U_VALUE_MINUS_2251 -12588505 // = -2251 +#define IQ_I_U_VALUE_MINUS_2250 -12582912 // = -2250 +#define IQ_I_U_VALUE_MINUS_2249 -12577320 // = -2249 +#define IQ_I_U_VALUE_MINUS_2248 -12571728 // = -2248 +#define IQ_I_U_VALUE_MINUS_2247 -12566135 // = -2247 +#define IQ_I_U_VALUE_MINUS_2246 -12560543 // = -2246 +#define IQ_I_U_VALUE_MINUS_2245 -12554950 // = -2245 +#define IQ_I_U_VALUE_MINUS_2244 -12549358 // = -2244 +#define IQ_I_U_VALUE_MINUS_2243 -12543766 // = -2243 +#define IQ_I_U_VALUE_MINUS_2242 -12538173 // = -2242 +#define IQ_I_U_VALUE_MINUS_2241 -12532581 // = -2241 +#define IQ_I_U_VALUE_MINUS_2240 -12526988 // = -2240 +#define IQ_I_U_VALUE_MINUS_2239 -12521396 // = -2239 +#define IQ_I_U_VALUE_MINUS_2238 -12515804 // = -2238 +#define IQ_I_U_VALUE_MINUS_2237 -12510211 // = -2237 +#define IQ_I_U_VALUE_MINUS_2236 -12504619 // = -2236 +#define IQ_I_U_VALUE_MINUS_2235 -12499026 // = -2235 +#define IQ_I_U_VALUE_MINUS_2234 -12493434 // = -2234 +#define IQ_I_U_VALUE_MINUS_2233 -12487842 // = -2233 +#define IQ_I_U_VALUE_MINUS_2232 -12482249 // = -2232 +#define IQ_I_U_VALUE_MINUS_2231 -12476657 // = -2231 +#define IQ_I_U_VALUE_MINUS_2230 -12471064 // = -2230 +#define IQ_I_U_VALUE_MINUS_2229 -12465472 // = -2229 +#define IQ_I_U_VALUE_MINUS_2228 -12459880 // = -2228 +#define IQ_I_U_VALUE_MINUS_2227 -12454287 // = -2227 +#define IQ_I_U_VALUE_MINUS_2226 -12448695 // = -2226 +#define IQ_I_U_VALUE_MINUS_2225 -12443102 // = -2225 +#define IQ_I_U_VALUE_MINUS_2224 -12437510 // = -2224 +#define IQ_I_U_VALUE_MINUS_2223 -12431918 // = -2223 +#define IQ_I_U_VALUE_MINUS_2222 -12426325 // = -2222 +#define IQ_I_U_VALUE_MINUS_2221 -12420733 // = -2221 +#define IQ_I_U_VALUE_MINUS_2220 -12415140 // = -2220 +#define IQ_I_U_VALUE_MINUS_2219 -12409548 // = -2219 +#define IQ_I_U_VALUE_MINUS_2218 -12403956 // = -2218 +#define IQ_I_U_VALUE_MINUS_2217 -12398363 // = -2217 +#define IQ_I_U_VALUE_MINUS_2216 -12392771 // = -2216 +#define IQ_I_U_VALUE_MINUS_2215 -12387178 // = -2215 +#define IQ_I_U_VALUE_MINUS_2214 -12381586 // = -2214 +#define IQ_I_U_VALUE_MINUS_2213 -12375994 // = -2213 +#define IQ_I_U_VALUE_MINUS_2212 -12370401 // = -2212 +#define IQ_I_U_VALUE_MINUS_2211 -12364809 // = -2211 +#define IQ_I_U_VALUE_MINUS_2210 -12359216 // = -2210 +#define IQ_I_U_VALUE_MINUS_2209 -12353624 // = -2209 +#define IQ_I_U_VALUE_MINUS_2208 -12348031 // = -2208 +#define IQ_I_U_VALUE_MINUS_2207 -12342439 // = -2207 +#define IQ_I_U_VALUE_MINUS_2206 -12336847 // = -2206 +#define IQ_I_U_VALUE_MINUS_2205 -12331254 // = -2205 +#define IQ_I_U_VALUE_MINUS_2204 -12325662 // = -2204 +#define IQ_I_U_VALUE_MINUS_2203 -12320069 // = -2203 +#define IQ_I_U_VALUE_MINUS_2202 -12314477 // = -2202 +#define IQ_I_U_VALUE_MINUS_2201 -12308885 // = -2201 +#define IQ_I_U_VALUE_MINUS_2200 -12303292 // = -2200 +#define IQ_I_U_VALUE_MINUS_2199 -12297700 // = -2199 +#define IQ_I_U_VALUE_MINUS_2198 -12292107 // = -2198 +#define IQ_I_U_VALUE_MINUS_2197 -12286515 // = -2197 +#define IQ_I_U_VALUE_MINUS_2196 -12280923 // = -2196 +#define IQ_I_U_VALUE_MINUS_2195 -12275330 // = -2195 +#define IQ_I_U_VALUE_MINUS_2194 -12269738 // = -2194 +#define IQ_I_U_VALUE_MINUS_2193 -12264145 // = -2193 +#define IQ_I_U_VALUE_MINUS_2192 -12258553 // = -2192 +#define IQ_I_U_VALUE_MINUS_2191 -12252961 // = -2191 +#define IQ_I_U_VALUE_MINUS_2190 -12247368 // = -2190 +#define IQ_I_U_VALUE_MINUS_2189 -12241776 // = -2189 +#define IQ_I_U_VALUE_MINUS_2188 -12236183 // = -2188 +#define IQ_I_U_VALUE_MINUS_2187 -12230591 // = -2187 +#define IQ_I_U_VALUE_MINUS_2186 -12224999 // = -2186 +#define IQ_I_U_VALUE_MINUS_2185 -12219406 // = -2185 +#define IQ_I_U_VALUE_MINUS_2184 -12213814 // = -2184 +#define IQ_I_U_VALUE_MINUS_2183 -12208221 // = -2183 +#define IQ_I_U_VALUE_MINUS_2182 -12202629 // = -2182 +#define IQ_I_U_VALUE_MINUS_2181 -12197037 // = -2181 +#define IQ_I_U_VALUE_MINUS_2180 -12191444 // = -2180 +#define IQ_I_U_VALUE_MINUS_2179 -12185852 // = -2179 +#define IQ_I_U_VALUE_MINUS_2178 -12180259 // = -2178 +#define IQ_I_U_VALUE_MINUS_2177 -12174667 // = -2177 +#define IQ_I_U_VALUE_MINUS_2176 -12169075 // = -2176 +#define IQ_I_U_VALUE_MINUS_2175 -12163482 // = -2175 +#define IQ_I_U_VALUE_MINUS_2174 -12157890 // = -2174 +#define IQ_I_U_VALUE_MINUS_2173 -12152297 // = -2173 +#define IQ_I_U_VALUE_MINUS_2172 -12146705 // = -2172 +#define IQ_I_U_VALUE_MINUS_2171 -12141112 // = -2171 +#define IQ_I_U_VALUE_MINUS_2170 -12135520 // = -2170 +#define IQ_I_U_VALUE_MINUS_2169 -12129928 // = -2169 +#define IQ_I_U_VALUE_MINUS_2168 -12124335 // = -2168 +#define IQ_I_U_VALUE_MINUS_2167 -12118743 // = -2167 +#define IQ_I_U_VALUE_MINUS_2166 -12113150 // = -2166 +#define IQ_I_U_VALUE_MINUS_2165 -12107558 // = -2165 +#define IQ_I_U_VALUE_MINUS_2164 -12101966 // = -2164 +#define IQ_I_U_VALUE_MINUS_2163 -12096373 // = -2163 +#define IQ_I_U_VALUE_MINUS_2162 -12090781 // = -2162 +#define IQ_I_U_VALUE_MINUS_2161 -12085188 // = -2161 +#define IQ_I_U_VALUE_MINUS_2160 -12079596 // = -2160 +#define IQ_I_U_VALUE_MINUS_2159 -12074004 // = -2159 +#define IQ_I_U_VALUE_MINUS_2158 -12068411 // = -2158 +#define IQ_I_U_VALUE_MINUS_2157 -12062819 // = -2157 +#define IQ_I_U_VALUE_MINUS_2156 -12057226 // = -2156 +#define IQ_I_U_VALUE_MINUS_2155 -12051634 // = -2155 +#define IQ_I_U_VALUE_MINUS_2154 -12046042 // = -2154 +#define IQ_I_U_VALUE_MINUS_2153 -12040449 // = -2153 +#define IQ_I_U_VALUE_MINUS_2152 -12034857 // = -2152 +#define IQ_I_U_VALUE_MINUS_2151 -12029264 // = -2151 +#define IQ_I_U_VALUE_MINUS_2150 -12023672 // = -2150 +#define IQ_I_U_VALUE_MINUS_2149 -12018080 // = -2149 +#define IQ_I_U_VALUE_MINUS_2148 -12012487 // = -2148 +#define IQ_I_U_VALUE_MINUS_2147 -12006895 // = -2147 +#define IQ_I_U_VALUE_MINUS_2146 -12001302 // = -2146 +#define IQ_I_U_VALUE_MINUS_2145 -11995710 // = -2145 +#define IQ_I_U_VALUE_MINUS_2144 -11990118 // = -2144 +#define IQ_I_U_VALUE_MINUS_2143 -11984525 // = -2143 +#define IQ_I_U_VALUE_MINUS_2142 -11978933 // = -2142 +#define IQ_I_U_VALUE_MINUS_2141 -11973340 // = -2141 +#define IQ_I_U_VALUE_MINUS_2140 -11967748 // = -2140 +#define IQ_I_U_VALUE_MINUS_2139 -11962156 // = -2139 +#define IQ_I_U_VALUE_MINUS_2138 -11956563 // = -2138 +#define IQ_I_U_VALUE_MINUS_2137 -11950971 // = -2137 +#define IQ_I_U_VALUE_MINUS_2136 -11945378 // = -2136 +#define IQ_I_U_VALUE_MINUS_2135 -11939786 // = -2135 +#define IQ_I_U_VALUE_MINUS_2134 -11934193 // = -2134 +#define IQ_I_U_VALUE_MINUS_2133 -11928601 // = -2133 +#define IQ_I_U_VALUE_MINUS_2132 -11923009 // = -2132 +#define IQ_I_U_VALUE_MINUS_2131 -11917416 // = -2131 +#define IQ_I_U_VALUE_MINUS_2130 -11911824 // = -2130 +#define IQ_I_U_VALUE_MINUS_2129 -11906231 // = -2129 +#define IQ_I_U_VALUE_MINUS_2128 -11900639 // = -2128 +#define IQ_I_U_VALUE_MINUS_2127 -11895047 // = -2127 +#define IQ_I_U_VALUE_MINUS_2126 -11889454 // = -2126 +#define IQ_I_U_VALUE_MINUS_2125 -11883862 // = -2125 +#define IQ_I_U_VALUE_MINUS_2124 -11878269 // = -2124 +#define IQ_I_U_VALUE_MINUS_2123 -11872677 // = -2123 +#define IQ_I_U_VALUE_MINUS_2122 -11867085 // = -2122 +#define IQ_I_U_VALUE_MINUS_2121 -11861492 // = -2121 +#define IQ_I_U_VALUE_MINUS_2120 -11855900 // = -2120 +#define IQ_I_U_VALUE_MINUS_2119 -11850307 // = -2119 +#define IQ_I_U_VALUE_MINUS_2118 -11844715 // = -2118 +#define IQ_I_U_VALUE_MINUS_2117 -11839123 // = -2117 +#define IQ_I_U_VALUE_MINUS_2116 -11833530 // = -2116 +#define IQ_I_U_VALUE_MINUS_2115 -11827938 // = -2115 +#define IQ_I_U_VALUE_MINUS_2114 -11822345 // = -2114 +#define IQ_I_U_VALUE_MINUS_2113 -11816753 // = -2113 +#define IQ_I_U_VALUE_MINUS_2112 -11811161 // = -2112 +#define IQ_I_U_VALUE_MINUS_2111 -11805568 // = -2111 +#define IQ_I_U_VALUE_MINUS_2110 -11799976 // = -2110 +#define IQ_I_U_VALUE_MINUS_2109 -11794383 // = -2109 +#define IQ_I_U_VALUE_MINUS_2108 -11788791 // = -2108 +#define IQ_I_U_VALUE_MINUS_2107 -11783199 // = -2107 +#define IQ_I_U_VALUE_MINUS_2106 -11777606 // = -2106 +#define IQ_I_U_VALUE_MINUS_2105 -11772014 // = -2105 +#define IQ_I_U_VALUE_MINUS_2104 -11766421 // = -2104 +#define IQ_I_U_VALUE_MINUS_2103 -11760829 // = -2103 +#define IQ_I_U_VALUE_MINUS_2102 -11755237 // = -2102 +#define IQ_I_U_VALUE_MINUS_2101 -11749644 // = -2101 +#define IQ_I_U_VALUE_MINUS_2100 -11744052 // = -2100 +#define IQ_I_U_VALUE_MINUS_2099 -11738459 // = -2099 +#define IQ_I_U_VALUE_MINUS_2098 -11732867 // = -2098 +#define IQ_I_U_VALUE_MINUS_2097 -11727274 // = -2097 +#define IQ_I_U_VALUE_MINUS_2096 -11721682 // = -2096 +#define IQ_I_U_VALUE_MINUS_2095 -11716090 // = -2095 +#define IQ_I_U_VALUE_MINUS_2094 -11710497 // = -2094 +#define IQ_I_U_VALUE_MINUS_2093 -11704905 // = -2093 +#define IQ_I_U_VALUE_MINUS_2092 -11699312 // = -2092 +#define IQ_I_U_VALUE_MINUS_2091 -11693720 // = -2091 +#define IQ_I_U_VALUE_MINUS_2090 -11688128 // = -2090 +#define IQ_I_U_VALUE_MINUS_2089 -11682535 // = -2089 +#define IQ_I_U_VALUE_MINUS_2088 -11676943 // = -2088 +#define IQ_I_U_VALUE_MINUS_2087 -11671350 // = -2087 +#define IQ_I_U_VALUE_MINUS_2086 -11665758 // = -2086 +#define IQ_I_U_VALUE_MINUS_2085 -11660166 // = -2085 +#define IQ_I_U_VALUE_MINUS_2084 -11654573 // = -2084 +#define IQ_I_U_VALUE_MINUS_2083 -11648981 // = -2083 +#define IQ_I_U_VALUE_MINUS_2082 -11643388 // = -2082 +#define IQ_I_U_VALUE_MINUS_2081 -11637796 // = -2081 +#define IQ_I_U_VALUE_MINUS_2080 -11632204 // = -2080 +#define IQ_I_U_VALUE_MINUS_2079 -11626611 // = -2079 +#define IQ_I_U_VALUE_MINUS_2078 -11621019 // = -2078 +#define IQ_I_U_VALUE_MINUS_2077 -11615426 // = -2077 +#define IQ_I_U_VALUE_MINUS_2076 -11609834 // = -2076 +#define IQ_I_U_VALUE_MINUS_2075 -11604242 // = -2075 +#define IQ_I_U_VALUE_MINUS_2074 -11598649 // = -2074 +#define IQ_I_U_VALUE_MINUS_2073 -11593057 // = -2073 +#define IQ_I_U_VALUE_MINUS_2072 -11587464 // = -2072 +#define IQ_I_U_VALUE_MINUS_2071 -11581872 // = -2071 +#define IQ_I_U_VALUE_MINUS_2070 -11576280 // = -2070 +#define IQ_I_U_VALUE_MINUS_2069 -11570687 // = -2069 +#define IQ_I_U_VALUE_MINUS_2068 -11565095 // = -2068 +#define IQ_I_U_VALUE_MINUS_2067 -11559502 // = -2067 +#define IQ_I_U_VALUE_MINUS_2066 -11553910 // = -2066 +#define IQ_I_U_VALUE_MINUS_2065 -11548318 // = -2065 +#define IQ_I_U_VALUE_MINUS_2064 -11542725 // = -2064 +#define IQ_I_U_VALUE_MINUS_2063 -11537133 // = -2063 +#define IQ_I_U_VALUE_MINUS_2062 -11531540 // = -2062 +#define IQ_I_U_VALUE_MINUS_2061 -11525948 // = -2061 +#define IQ_I_U_VALUE_MINUS_2060 -11520355 // = -2060 +#define IQ_I_U_VALUE_MINUS_2059 -11514763 // = -2059 +#define IQ_I_U_VALUE_MINUS_2058 -11509171 // = -2058 +#define IQ_I_U_VALUE_MINUS_2057 -11503578 // = -2057 +#define IQ_I_U_VALUE_MINUS_2056 -11497986 // = -2056 +#define IQ_I_U_VALUE_MINUS_2055 -11492393 // = -2055 +#define IQ_I_U_VALUE_MINUS_2054 -11486801 // = -2054 +#define IQ_I_U_VALUE_MINUS_2053 -11481209 // = -2053 +#define IQ_I_U_VALUE_MINUS_2052 -11475616 // = -2052 +#define IQ_I_U_VALUE_MINUS_2051 -11470024 // = -2051 +#define IQ_I_U_VALUE_MINUS_2050 -11464431 // = -2050 +#define IQ_I_U_VALUE_MINUS_2049 -11458839 // = -2049 +#define IQ_I_U_VALUE_MINUS_2048 -11453247 // = -2048 +#define IQ_I_U_VALUE_MINUS_2047 -11447654 // = -2047 +#define IQ_I_U_VALUE_MINUS_2046 -11442062 // = -2046 +#define IQ_I_U_VALUE_MINUS_2045 -11436469 // = -2045 +#define IQ_I_U_VALUE_MINUS_2044 -11430877 // = -2044 +#define IQ_I_U_VALUE_MINUS_2043 -11425285 // = -2043 +#define IQ_I_U_VALUE_MINUS_2042 -11419692 // = -2042 +#define IQ_I_U_VALUE_MINUS_2041 -11414100 // = -2041 +#define IQ_I_U_VALUE_MINUS_2040 -11408507 // = -2040 +#define IQ_I_U_VALUE_MINUS_2039 -11402915 // = -2039 +#define IQ_I_U_VALUE_MINUS_2038 -11397323 // = -2038 +#define IQ_I_U_VALUE_MINUS_2037 -11391730 // = -2037 +#define IQ_I_U_VALUE_MINUS_2036 -11386138 // = -2036 +#define IQ_I_U_VALUE_MINUS_2035 -11380545 // = -2035 +#define IQ_I_U_VALUE_MINUS_2034 -11374953 // = -2034 +#define IQ_I_U_VALUE_MINUS_2033 -11369361 // = -2033 +#define IQ_I_U_VALUE_MINUS_2032 -11363768 // = -2032 +#define IQ_I_U_VALUE_MINUS_2031 -11358176 // = -2031 +#define IQ_I_U_VALUE_MINUS_2030 -11352583 // = -2030 +#define IQ_I_U_VALUE_MINUS_2029 -11346991 // = -2029 +#define IQ_I_U_VALUE_MINUS_2028 -11341399 // = -2028 +#define IQ_I_U_VALUE_MINUS_2027 -11335806 // = -2027 +#define IQ_I_U_VALUE_MINUS_2026 -11330214 // = -2026 +#define IQ_I_U_VALUE_MINUS_2025 -11324621 // = -2025 +#define IQ_I_U_VALUE_MINUS_2024 -11319029 // = -2024 +#define IQ_I_U_VALUE_MINUS_2023 -11313436 // = -2023 +#define IQ_I_U_VALUE_MINUS_2022 -11307844 // = -2022 +#define IQ_I_U_VALUE_MINUS_2021 -11302252 // = -2021 +#define IQ_I_U_VALUE_MINUS_2020 -11296659 // = -2020 +#define IQ_I_U_VALUE_MINUS_2019 -11291067 // = -2019 +#define IQ_I_U_VALUE_MINUS_2018 -11285474 // = -2018 +#define IQ_I_U_VALUE_MINUS_2017 -11279882 // = -2017 +#define IQ_I_U_VALUE_MINUS_2016 -11274290 // = -2016 +#define IQ_I_U_VALUE_MINUS_2015 -11268697 // = -2015 +#define IQ_I_U_VALUE_MINUS_2014 -11263105 // = -2014 +#define IQ_I_U_VALUE_MINUS_2013 -11257512 // = -2013 +#define IQ_I_U_VALUE_MINUS_2012 -11251920 // = -2012 +#define IQ_I_U_VALUE_MINUS_2011 -11246328 // = -2011 +#define IQ_I_U_VALUE_MINUS_2010 -11240735 // = -2010 +#define IQ_I_U_VALUE_MINUS_2009 -11235143 // = -2009 +#define IQ_I_U_VALUE_MINUS_2008 -11229550 // = -2008 +#define IQ_I_U_VALUE_MINUS_2007 -11223958 // = -2007 +#define IQ_I_U_VALUE_MINUS_2006 -11218366 // = -2006 +#define IQ_I_U_VALUE_MINUS_2005 -11212773 // = -2005 +#define IQ_I_U_VALUE_MINUS_2004 -11207181 // = -2004 +#define IQ_I_U_VALUE_MINUS_2003 -11201588 // = -2003 +#define IQ_I_U_VALUE_MINUS_2002 -11195996 // = -2002 +#define IQ_I_U_VALUE_MINUS_2001 -11190404 // = -2001 +#define IQ_I_U_VALUE_MINUS_2000 -11184811 // = -2000 +#define IQ_I_U_VALUE_MINUS_1999 -11179219 // = -1999 +#define IQ_I_U_VALUE_MINUS_1998 -11173626 // = -1998 +#define IQ_I_U_VALUE_MINUS_1997 -11168034 // = -1997 +#define IQ_I_U_VALUE_MINUS_1996 -11162442 // = -1996 +#define IQ_I_U_VALUE_MINUS_1995 -11156849 // = -1995 +#define IQ_I_U_VALUE_MINUS_1994 -11151257 // = -1994 +#define IQ_I_U_VALUE_MINUS_1993 -11145664 // = -1993 +#define IQ_I_U_VALUE_MINUS_1992 -11140072 // = -1992 +#define IQ_I_U_VALUE_MINUS_1991 -11134480 // = -1991 +#define IQ_I_U_VALUE_MINUS_1990 -11128887 // = -1990 +#define IQ_I_U_VALUE_MINUS_1989 -11123295 // = -1989 +#define IQ_I_U_VALUE_MINUS_1988 -11117702 // = -1988 +#define IQ_I_U_VALUE_MINUS_1987 -11112110 // = -1987 +#define IQ_I_U_VALUE_MINUS_1986 -11106517 // = -1986 +#define IQ_I_U_VALUE_MINUS_1985 -11100925 // = -1985 +#define IQ_I_U_VALUE_MINUS_1984 -11095333 // = -1984 +#define IQ_I_U_VALUE_MINUS_1983 -11089740 // = -1983 +#define IQ_I_U_VALUE_MINUS_1982 -11084148 // = -1982 +#define IQ_I_U_VALUE_MINUS_1981 -11078555 // = -1981 +#define IQ_I_U_VALUE_MINUS_1980 -11072963 // = -1980 +#define IQ_I_U_VALUE_MINUS_1979 -11067371 // = -1979 +#define IQ_I_U_VALUE_MINUS_1978 -11061778 // = -1978 +#define IQ_I_U_VALUE_MINUS_1977 -11056186 // = -1977 +#define IQ_I_U_VALUE_MINUS_1976 -11050593 // = -1976 +#define IQ_I_U_VALUE_MINUS_1975 -11045001 // = -1975 +#define IQ_I_U_VALUE_MINUS_1974 -11039409 // = -1974 +#define IQ_I_U_VALUE_MINUS_1973 -11033816 // = -1973 +#define IQ_I_U_VALUE_MINUS_1972 -11028224 // = -1972 +#define IQ_I_U_VALUE_MINUS_1971 -11022631 // = -1971 +#define IQ_I_U_VALUE_MINUS_1970 -11017039 // = -1970 +#define IQ_I_U_VALUE_MINUS_1969 -11011447 // = -1969 +#define IQ_I_U_VALUE_MINUS_1968 -11005854 // = -1968 +#define IQ_I_U_VALUE_MINUS_1967 -11000262 // = -1967 +#define IQ_I_U_VALUE_MINUS_1966 -10994669 // = -1966 +#define IQ_I_U_VALUE_MINUS_1965 -10989077 // = -1965 +#define IQ_I_U_VALUE_MINUS_1964 -10983485 // = -1964 +#define IQ_I_U_VALUE_MINUS_1963 -10977892 // = -1963 +#define IQ_I_U_VALUE_MINUS_1962 -10972300 // = -1962 +#define IQ_I_U_VALUE_MINUS_1961 -10966707 // = -1961 +#define IQ_I_U_VALUE_MINUS_1960 -10961115 // = -1960 +#define IQ_I_U_VALUE_MINUS_1959 -10955523 // = -1959 +#define IQ_I_U_VALUE_MINUS_1958 -10949930 // = -1958 +#define IQ_I_U_VALUE_MINUS_1957 -10944338 // = -1957 +#define IQ_I_U_VALUE_MINUS_1956 -10938745 // = -1956 +#define IQ_I_U_VALUE_MINUS_1955 -10933153 // = -1955 +#define IQ_I_U_VALUE_MINUS_1954 -10927561 // = -1954 +#define IQ_I_U_VALUE_MINUS_1953 -10921968 // = -1953 +#define IQ_I_U_VALUE_MINUS_1952 -10916376 // = -1952 +#define IQ_I_U_VALUE_MINUS_1951 -10910783 // = -1951 +#define IQ_I_U_VALUE_MINUS_1950 -10905191 // = -1950 +#define IQ_I_U_VALUE_MINUS_1949 -10899598 // = -1949 +#define IQ_I_U_VALUE_MINUS_1948 -10894006 // = -1948 +#define IQ_I_U_VALUE_MINUS_1947 -10888414 // = -1947 +#define IQ_I_U_VALUE_MINUS_1946 -10882821 // = -1946 +#define IQ_I_U_VALUE_MINUS_1945 -10877229 // = -1945 +#define IQ_I_U_VALUE_MINUS_1944 -10871636 // = -1944 +#define IQ_I_U_VALUE_MINUS_1943 -10866044 // = -1943 +#define IQ_I_U_VALUE_MINUS_1942 -10860452 // = -1942 +#define IQ_I_U_VALUE_MINUS_1941 -10854859 // = -1941 +#define IQ_I_U_VALUE_MINUS_1940 -10849267 // = -1940 +#define IQ_I_U_VALUE_MINUS_1939 -10843674 // = -1939 +#define IQ_I_U_VALUE_MINUS_1938 -10838082 // = -1938 +#define IQ_I_U_VALUE_MINUS_1937 -10832490 // = -1937 +#define IQ_I_U_VALUE_MINUS_1936 -10826897 // = -1936 +#define IQ_I_U_VALUE_MINUS_1935 -10821305 // = -1935 +#define IQ_I_U_VALUE_MINUS_1934 -10815712 // = -1934 +#define IQ_I_U_VALUE_MINUS_1933 -10810120 // = -1933 +#define IQ_I_U_VALUE_MINUS_1932 -10804528 // = -1932 +#define IQ_I_U_VALUE_MINUS_1931 -10798935 // = -1931 +#define IQ_I_U_VALUE_MINUS_1930 -10793343 // = -1930 +#define IQ_I_U_VALUE_MINUS_1929 -10787750 // = -1929 +#define IQ_I_U_VALUE_MINUS_1928 -10782158 // = -1928 +#define IQ_I_U_VALUE_MINUS_1927 -10776566 // = -1927 +#define IQ_I_U_VALUE_MINUS_1926 -10770973 // = -1926 +#define IQ_I_U_VALUE_MINUS_1925 -10765381 // = -1925 +#define IQ_I_U_VALUE_MINUS_1924 -10759788 // = -1924 +#define IQ_I_U_VALUE_MINUS_1923 -10754196 // = -1923 +#define IQ_I_U_VALUE_MINUS_1922 -10748604 // = -1922 +#define IQ_I_U_VALUE_MINUS_1921 -10743011 // = -1921 +#define IQ_I_U_VALUE_MINUS_1920 -10737419 // = -1920 +#define IQ_I_U_VALUE_MINUS_1919 -10731826 // = -1919 +#define IQ_I_U_VALUE_MINUS_1918 -10726234 // = -1918 +#define IQ_I_U_VALUE_MINUS_1917 -10720642 // = -1917 +#define IQ_I_U_VALUE_MINUS_1916 -10715049 // = -1916 +#define IQ_I_U_VALUE_MINUS_1915 -10709457 // = -1915 +#define IQ_I_U_VALUE_MINUS_1914 -10703864 // = -1914 +#define IQ_I_U_VALUE_MINUS_1913 -10698272 // = -1913 +#define IQ_I_U_VALUE_MINUS_1912 -10692679 // = -1912 +#define IQ_I_U_VALUE_MINUS_1911 -10687087 // = -1911 +#define IQ_I_U_VALUE_MINUS_1910 -10681495 // = -1910 +#define IQ_I_U_VALUE_MINUS_1909 -10675902 // = -1909 +#define IQ_I_U_VALUE_MINUS_1908 -10670310 // = -1908 +#define IQ_I_U_VALUE_MINUS_1907 -10664717 // = -1907 +#define IQ_I_U_VALUE_MINUS_1906 -10659125 // = -1906 +#define IQ_I_U_VALUE_MINUS_1905 -10653533 // = -1905 +#define IQ_I_U_VALUE_MINUS_1904 -10647940 // = -1904 +#define IQ_I_U_VALUE_MINUS_1903 -10642348 // = -1903 +#define IQ_I_U_VALUE_MINUS_1902 -10636755 // = -1902 +#define IQ_I_U_VALUE_MINUS_1901 -10631163 // = -1901 +#define IQ_I_U_VALUE_MINUS_1900 -10625571 // = -1900 +#define IQ_I_U_VALUE_MINUS_1899 -10619978 // = -1899 +#define IQ_I_U_VALUE_MINUS_1898 -10614386 // = -1898 +#define IQ_I_U_VALUE_MINUS_1897 -10608793 // = -1897 +#define IQ_I_U_VALUE_MINUS_1896 -10603201 // = -1896 +#define IQ_I_U_VALUE_MINUS_1895 -10597609 // = -1895 +#define IQ_I_U_VALUE_MINUS_1894 -10592016 // = -1894 +#define IQ_I_U_VALUE_MINUS_1893 -10586424 // = -1893 +#define IQ_I_U_VALUE_MINUS_1892 -10580831 // = -1892 +#define IQ_I_U_VALUE_MINUS_1891 -10575239 // = -1891 +#define IQ_I_U_VALUE_MINUS_1890 -10569647 // = -1890 +#define IQ_I_U_VALUE_MINUS_1889 -10564054 // = -1889 +#define IQ_I_U_VALUE_MINUS_1888 -10558462 // = -1888 +#define IQ_I_U_VALUE_MINUS_1887 -10552869 // = -1887 +#define IQ_I_U_VALUE_MINUS_1886 -10547277 // = -1886 +#define IQ_I_U_VALUE_MINUS_1885 -10541685 // = -1885 +#define IQ_I_U_VALUE_MINUS_1884 -10536092 // = -1884 +#define IQ_I_U_VALUE_MINUS_1883 -10530500 // = -1883 +#define IQ_I_U_VALUE_MINUS_1882 -10524907 // = -1882 +#define IQ_I_U_VALUE_MINUS_1881 -10519315 // = -1881 +#define IQ_I_U_VALUE_MINUS_1880 -10513723 // = -1880 +#define IQ_I_U_VALUE_MINUS_1879 -10508130 // = -1879 +#define IQ_I_U_VALUE_MINUS_1878 -10502538 // = -1878 +#define IQ_I_U_VALUE_MINUS_1877 -10496945 // = -1877 +#define IQ_I_U_VALUE_MINUS_1876 -10491353 // = -1876 +#define IQ_I_U_VALUE_MINUS_1875 -10485760 // = -1875 +#define IQ_I_U_VALUE_MINUS_1874 -10480168 // = -1874 +#define IQ_I_U_VALUE_MINUS_1873 -10474576 // = -1873 +#define IQ_I_U_VALUE_MINUS_1872 -10468983 // = -1872 +#define IQ_I_U_VALUE_MINUS_1871 -10463391 // = -1871 +#define IQ_I_U_VALUE_MINUS_1870 -10457798 // = -1870 +#define IQ_I_U_VALUE_MINUS_1869 -10452206 // = -1869 +#define IQ_I_U_VALUE_MINUS_1868 -10446614 // = -1868 +#define IQ_I_U_VALUE_MINUS_1867 -10441021 // = -1867 +#define IQ_I_U_VALUE_MINUS_1866 -10435429 // = -1866 +#define IQ_I_U_VALUE_MINUS_1865 -10429836 // = -1865 +#define IQ_I_U_VALUE_MINUS_1864 -10424244 // = -1864 +#define IQ_I_U_VALUE_MINUS_1863 -10418652 // = -1863 +#define IQ_I_U_VALUE_MINUS_1862 -10413059 // = -1862 +#define IQ_I_U_VALUE_MINUS_1861 -10407467 // = -1861 +#define IQ_I_U_VALUE_MINUS_1860 -10401874 // = -1860 +#define IQ_I_U_VALUE_MINUS_1859 -10396282 // = -1859 +#define IQ_I_U_VALUE_MINUS_1858 -10390690 // = -1858 +#define IQ_I_U_VALUE_MINUS_1857 -10385097 // = -1857 +#define IQ_I_U_VALUE_MINUS_1856 -10379505 // = -1856 +#define IQ_I_U_VALUE_MINUS_1855 -10373912 // = -1855 +#define IQ_I_U_VALUE_MINUS_1854 -10368320 // = -1854 +#define IQ_I_U_VALUE_MINUS_1853 -10362728 // = -1853 +#define IQ_I_U_VALUE_MINUS_1852 -10357135 // = -1852 +#define IQ_I_U_VALUE_MINUS_1851 -10351543 // = -1851 +#define IQ_I_U_VALUE_MINUS_1850 -10345950 // = -1850 +#define IQ_I_U_VALUE_MINUS_1849 -10340358 // = -1849 +#define IQ_I_U_VALUE_MINUS_1848 -10334766 // = -1848 +#define IQ_I_U_VALUE_MINUS_1847 -10329173 // = -1847 +#define IQ_I_U_VALUE_MINUS_1846 -10323581 // = -1846 +#define IQ_I_U_VALUE_MINUS_1845 -10317988 // = -1845 +#define IQ_I_U_VALUE_MINUS_1844 -10312396 // = -1844 +#define IQ_I_U_VALUE_MINUS_1843 -10306804 // = -1843 +#define IQ_I_U_VALUE_MINUS_1842 -10301211 // = -1842 +#define IQ_I_U_VALUE_MINUS_1841 -10295619 // = -1841 +#define IQ_I_U_VALUE_MINUS_1840 -10290026 // = -1840 +#define IQ_I_U_VALUE_MINUS_1839 -10284434 // = -1839 +#define IQ_I_U_VALUE_MINUS_1838 -10278842 // = -1838 +#define IQ_I_U_VALUE_MINUS_1837 -10273249 // = -1837 +#define IQ_I_U_VALUE_MINUS_1836 -10267657 // = -1836 +#define IQ_I_U_VALUE_MINUS_1835 -10262064 // = -1835 +#define IQ_I_U_VALUE_MINUS_1834 -10256472 // = -1834 +#define IQ_I_U_VALUE_MINUS_1833 -10250879 // = -1833 +#define IQ_I_U_VALUE_MINUS_1832 -10245287 // = -1832 +#define IQ_I_U_VALUE_MINUS_1831 -10239695 // = -1831 +#define IQ_I_U_VALUE_MINUS_1830 -10234102 // = -1830 +#define IQ_I_U_VALUE_MINUS_1829 -10228510 // = -1829 +#define IQ_I_U_VALUE_MINUS_1828 -10222917 // = -1828 +#define IQ_I_U_VALUE_MINUS_1827 -10217325 // = -1827 +#define IQ_I_U_VALUE_MINUS_1826 -10211733 // = -1826 +#define IQ_I_U_VALUE_MINUS_1825 -10206140 // = -1825 +#define IQ_I_U_VALUE_MINUS_1824 -10200548 // = -1824 +#define IQ_I_U_VALUE_MINUS_1823 -10194955 // = -1823 +#define IQ_I_U_VALUE_MINUS_1822 -10189363 // = -1822 +#define IQ_I_U_VALUE_MINUS_1821 -10183771 // = -1821 +#define IQ_I_U_VALUE_MINUS_1820 -10178178 // = -1820 +#define IQ_I_U_VALUE_MINUS_1819 -10172586 // = -1819 +#define IQ_I_U_VALUE_MINUS_1818 -10166993 // = -1818 +#define IQ_I_U_VALUE_MINUS_1817 -10161401 // = -1817 +#define IQ_I_U_VALUE_MINUS_1816 -10155809 // = -1816 +#define IQ_I_U_VALUE_MINUS_1815 -10150216 // = -1815 +#define IQ_I_U_VALUE_MINUS_1814 -10144624 // = -1814 +#define IQ_I_U_VALUE_MINUS_1813 -10139031 // = -1813 +#define IQ_I_U_VALUE_MINUS_1812 -10133439 // = -1812 +#define IQ_I_U_VALUE_MINUS_1811 -10127847 // = -1811 +#define IQ_I_U_VALUE_MINUS_1810 -10122254 // = -1810 +#define IQ_I_U_VALUE_MINUS_1809 -10116662 // = -1809 +#define IQ_I_U_VALUE_MINUS_1808 -10111069 // = -1808 +#define IQ_I_U_VALUE_MINUS_1807 -10105477 // = -1807 +#define IQ_I_U_VALUE_MINUS_1806 -10099885 // = -1806 +#define IQ_I_U_VALUE_MINUS_1805 -10094292 // = -1805 +#define IQ_I_U_VALUE_MINUS_1804 -10088700 // = -1804 +#define IQ_I_U_VALUE_MINUS_1803 -10083107 // = -1803 +#define IQ_I_U_VALUE_MINUS_1802 -10077515 // = -1802 +#define IQ_I_U_VALUE_MINUS_1801 -10071923 // = -1801 +#define IQ_I_U_VALUE_MINUS_1800 -10066330 // = -1800 +#define IQ_I_U_VALUE_MINUS_1799 -10060738 // = -1799 +#define IQ_I_U_VALUE_MINUS_1798 -10055145 // = -1798 +#define IQ_I_U_VALUE_MINUS_1797 -10049553 // = -1797 +#define IQ_I_U_VALUE_MINUS_1796 -10043960 // = -1796 +#define IQ_I_U_VALUE_MINUS_1795 -10038368 // = -1795 +#define IQ_I_U_VALUE_MINUS_1794 -10032776 // = -1794 +#define IQ_I_U_VALUE_MINUS_1793 -10027183 // = -1793 +#define IQ_I_U_VALUE_MINUS_1792 -10021591 // = -1792 +#define IQ_I_U_VALUE_MINUS_1791 -10015998 // = -1791 +#define IQ_I_U_VALUE_MINUS_1790 -10010406 // = -1790 +#define IQ_I_U_VALUE_MINUS_1789 -10004814 // = -1789 +#define IQ_I_U_VALUE_MINUS_1788 -9999221 // = -1788 +#define IQ_I_U_VALUE_MINUS_1787 -9993629 // = -1787 +#define IQ_I_U_VALUE_MINUS_1786 -9988036 // = -1786 +#define IQ_I_U_VALUE_MINUS_1785 -9982444 // = -1785 +#define IQ_I_U_VALUE_MINUS_1784 -9976852 // = -1784 +#define IQ_I_U_VALUE_MINUS_1783 -9971259 // = -1783 +#define IQ_I_U_VALUE_MINUS_1782 -9965667 // = -1782 +#define IQ_I_U_VALUE_MINUS_1781 -9960074 // = -1781 +#define IQ_I_U_VALUE_MINUS_1780 -9954482 // = -1780 +#define IQ_I_U_VALUE_MINUS_1779 -9948890 // = -1779 +#define IQ_I_U_VALUE_MINUS_1778 -9943297 // = -1778 +#define IQ_I_U_VALUE_MINUS_1777 -9937705 // = -1777 +#define IQ_I_U_VALUE_MINUS_1776 -9932112 // = -1776 +#define IQ_I_U_VALUE_MINUS_1775 -9926520 // = -1775 +#define IQ_I_U_VALUE_MINUS_1774 -9920928 // = -1774 +#define IQ_I_U_VALUE_MINUS_1773 -9915335 // = -1773 +#define IQ_I_U_VALUE_MINUS_1772 -9909743 // = -1772 +#define IQ_I_U_VALUE_MINUS_1771 -9904150 // = -1771 +#define IQ_I_U_VALUE_MINUS_1770 -9898558 // = -1770 +#define IQ_I_U_VALUE_MINUS_1769 -9892966 // = -1769 +#define IQ_I_U_VALUE_MINUS_1768 -9887373 // = -1768 +#define IQ_I_U_VALUE_MINUS_1767 -9881781 // = -1767 +#define IQ_I_U_VALUE_MINUS_1766 -9876188 // = -1766 +#define IQ_I_U_VALUE_MINUS_1765 -9870596 // = -1765 +#define IQ_I_U_VALUE_MINUS_1764 -9865004 // = -1764 +#define IQ_I_U_VALUE_MINUS_1763 -9859411 // = -1763 +#define IQ_I_U_VALUE_MINUS_1762 -9853819 // = -1762 +#define IQ_I_U_VALUE_MINUS_1761 -9848226 // = -1761 +#define IQ_I_U_VALUE_MINUS_1760 -9842634 // = -1760 +#define IQ_I_U_VALUE_MINUS_1759 -9837041 // = -1759 +#define IQ_I_U_VALUE_MINUS_1758 -9831449 // = -1758 +#define IQ_I_U_VALUE_MINUS_1757 -9825857 // = -1757 +#define IQ_I_U_VALUE_MINUS_1756 -9820264 // = -1756 +#define IQ_I_U_VALUE_MINUS_1755 -9814672 // = -1755 +#define IQ_I_U_VALUE_MINUS_1754 -9809079 // = -1754 +#define IQ_I_U_VALUE_MINUS_1753 -9803487 // = -1753 +#define IQ_I_U_VALUE_MINUS_1752 -9797895 // = -1752 +#define IQ_I_U_VALUE_MINUS_1751 -9792302 // = -1751 +#define IQ_I_U_VALUE_MINUS_1750 -9786710 // = -1750 +#define IQ_I_U_VALUE_MINUS_1749 -9781117 // = -1749 +#define IQ_I_U_VALUE_MINUS_1748 -9775525 // = -1748 +#define IQ_I_U_VALUE_MINUS_1747 -9769933 // = -1747 +#define IQ_I_U_VALUE_MINUS_1746 -9764340 // = -1746 +#define IQ_I_U_VALUE_MINUS_1745 -9758748 // = -1745 +#define IQ_I_U_VALUE_MINUS_1744 -9753155 // = -1744 +#define IQ_I_U_VALUE_MINUS_1743 -9747563 // = -1743 +#define IQ_I_U_VALUE_MINUS_1742 -9741971 // = -1742 +#define IQ_I_U_VALUE_MINUS_1741 -9736378 // = -1741 +#define IQ_I_U_VALUE_MINUS_1740 -9730786 // = -1740 +#define IQ_I_U_VALUE_MINUS_1739 -9725193 // = -1739 +#define IQ_I_U_VALUE_MINUS_1738 -9719601 // = -1738 +#define IQ_I_U_VALUE_MINUS_1737 -9714009 // = -1737 +#define IQ_I_U_VALUE_MINUS_1736 -9708416 // = -1736 +#define IQ_I_U_VALUE_MINUS_1735 -9702824 // = -1735 +#define IQ_I_U_VALUE_MINUS_1734 -9697231 // = -1734 +#define IQ_I_U_VALUE_MINUS_1733 -9691639 // = -1733 +#define IQ_I_U_VALUE_MINUS_1732 -9686047 // = -1732 +#define IQ_I_U_VALUE_MINUS_1731 -9680454 // = -1731 +#define IQ_I_U_VALUE_MINUS_1730 -9674862 // = -1730 +#define IQ_I_U_VALUE_MINUS_1729 -9669269 // = -1729 +#define IQ_I_U_VALUE_MINUS_1728 -9663677 // = -1728 +#define IQ_I_U_VALUE_MINUS_1727 -9658085 // = -1727 +#define IQ_I_U_VALUE_MINUS_1726 -9652492 // = -1726 +#define IQ_I_U_VALUE_MINUS_1725 -9646900 // = -1725 +#define IQ_I_U_VALUE_MINUS_1724 -9641307 // = -1724 +#define IQ_I_U_VALUE_MINUS_1723 -9635715 // = -1723 +#define IQ_I_U_VALUE_MINUS_1722 -9630122 // = -1722 +#define IQ_I_U_VALUE_MINUS_1721 -9624530 // = -1721 +#define IQ_I_U_VALUE_MINUS_1720 -9618938 // = -1720 +#define IQ_I_U_VALUE_MINUS_1719 -9613345 // = -1719 +#define IQ_I_U_VALUE_MINUS_1718 -9607753 // = -1718 +#define IQ_I_U_VALUE_MINUS_1717 -9602160 // = -1717 +#define IQ_I_U_VALUE_MINUS_1716 -9596568 // = -1716 +#define IQ_I_U_VALUE_MINUS_1715 -9590976 // = -1715 +#define IQ_I_U_VALUE_MINUS_1714 -9585383 // = -1714 +#define IQ_I_U_VALUE_MINUS_1713 -9579791 // = -1713 +#define IQ_I_U_VALUE_MINUS_1712 -9574198 // = -1712 +#define IQ_I_U_VALUE_MINUS_1711 -9568606 // = -1711 +#define IQ_I_U_VALUE_MINUS_1710 -9563014 // = -1710 +#define IQ_I_U_VALUE_MINUS_1709 -9557421 // = -1709 +#define IQ_I_U_VALUE_MINUS_1708 -9551829 // = -1708 +#define IQ_I_U_VALUE_MINUS_1707 -9546236 // = -1707 +#define IQ_I_U_VALUE_MINUS_1706 -9540644 // = -1706 +#define IQ_I_U_VALUE_MINUS_1705 -9535052 // = -1705 +#define IQ_I_U_VALUE_MINUS_1704 -9529459 // = -1704 +#define IQ_I_U_VALUE_MINUS_1703 -9523867 // = -1703 +#define IQ_I_U_VALUE_MINUS_1702 -9518274 // = -1702 +#define IQ_I_U_VALUE_MINUS_1701 -9512682 // = -1701 +#define IQ_I_U_VALUE_MINUS_1700 -9507090 // = -1700 +#define IQ_I_U_VALUE_MINUS_1699 -9501497 // = -1699 +#define IQ_I_U_VALUE_MINUS_1698 -9495905 // = -1698 +#define IQ_I_U_VALUE_MINUS_1697 -9490312 // = -1697 +#define IQ_I_U_VALUE_MINUS_1696 -9484720 // = -1696 +#define IQ_I_U_VALUE_MINUS_1695 -9479128 // = -1695 +#define IQ_I_U_VALUE_MINUS_1694 -9473535 // = -1694 +#define IQ_I_U_VALUE_MINUS_1693 -9467943 // = -1693 +#define IQ_I_U_VALUE_MINUS_1692 -9462350 // = -1692 +#define IQ_I_U_VALUE_MINUS_1691 -9456758 // = -1691 +#define IQ_I_U_VALUE_MINUS_1690 -9451166 // = -1690 +#define IQ_I_U_VALUE_MINUS_1689 -9445573 // = -1689 +#define IQ_I_U_VALUE_MINUS_1688 -9439981 // = -1688 +#define IQ_I_U_VALUE_MINUS_1687 -9434388 // = -1687 +#define IQ_I_U_VALUE_MINUS_1686 -9428796 // = -1686 +#define IQ_I_U_VALUE_MINUS_1685 -9423203 // = -1685 +#define IQ_I_U_VALUE_MINUS_1684 -9417611 // = -1684 +#define IQ_I_U_VALUE_MINUS_1683 -9412019 // = -1683 +#define IQ_I_U_VALUE_MINUS_1682 -9406426 // = -1682 +#define IQ_I_U_VALUE_MINUS_1681 -9400834 // = -1681 +#define IQ_I_U_VALUE_MINUS_1680 -9395241 // = -1680 +#define IQ_I_U_VALUE_MINUS_1679 -9389649 // = -1679 +#define IQ_I_U_VALUE_MINUS_1678 -9384057 // = -1678 +#define IQ_I_U_VALUE_MINUS_1677 -9378464 // = -1677 +#define IQ_I_U_VALUE_MINUS_1676 -9372872 // = -1676 +#define IQ_I_U_VALUE_MINUS_1675 -9367279 // = -1675 +#define IQ_I_U_VALUE_MINUS_1674 -9361687 // = -1674 +#define IQ_I_U_VALUE_MINUS_1673 -9356095 // = -1673 +#define IQ_I_U_VALUE_MINUS_1672 -9350502 // = -1672 +#define IQ_I_U_VALUE_MINUS_1671 -9344910 // = -1671 +#define IQ_I_U_VALUE_MINUS_1670 -9339317 // = -1670 +#define IQ_I_U_VALUE_MINUS_1669 -9333725 // = -1669 +#define IQ_I_U_VALUE_MINUS_1668 -9328133 // = -1668 +#define IQ_I_U_VALUE_MINUS_1667 -9322540 // = -1667 +#define IQ_I_U_VALUE_MINUS_1666 -9316948 // = -1666 +#define IQ_I_U_VALUE_MINUS_1665 -9311355 // = -1665 +#define IQ_I_U_VALUE_MINUS_1664 -9305763 // = -1664 +#define IQ_I_U_VALUE_MINUS_1663 -9300171 // = -1663 +#define IQ_I_U_VALUE_MINUS_1662 -9294578 // = -1662 +#define IQ_I_U_VALUE_MINUS_1661 -9288986 // = -1661 +#define IQ_I_U_VALUE_MINUS_1660 -9283393 // = -1660 +#define IQ_I_U_VALUE_MINUS_1659 -9277801 // = -1659 +#define IQ_I_U_VALUE_MINUS_1658 -9272209 // = -1658 +#define IQ_I_U_VALUE_MINUS_1657 -9266616 // = -1657 +#define IQ_I_U_VALUE_MINUS_1656 -9261024 // = -1656 +#define IQ_I_U_VALUE_MINUS_1655 -9255431 // = -1655 +#define IQ_I_U_VALUE_MINUS_1654 -9249839 // = -1654 +#define IQ_I_U_VALUE_MINUS_1653 -9244247 // = -1653 +#define IQ_I_U_VALUE_MINUS_1652 -9238654 // = -1652 +#define IQ_I_U_VALUE_MINUS_1651 -9233062 // = -1651 +#define IQ_I_U_VALUE_MINUS_1650 -9227469 // = -1650 +#define IQ_I_U_VALUE_MINUS_1649 -9221877 // = -1649 +#define IQ_I_U_VALUE_MINUS_1648 -9216284 // = -1648 +#define IQ_I_U_VALUE_MINUS_1647 -9210692 // = -1647 +#define IQ_I_U_VALUE_MINUS_1646 -9205100 // = -1646 +#define IQ_I_U_VALUE_MINUS_1645 -9199507 // = -1645 +#define IQ_I_U_VALUE_MINUS_1644 -9193915 // = -1644 +#define IQ_I_U_VALUE_MINUS_1643 -9188322 // = -1643 +#define IQ_I_U_VALUE_MINUS_1642 -9182730 // = -1642 +#define IQ_I_U_VALUE_MINUS_1641 -9177138 // = -1641 +#define IQ_I_U_VALUE_MINUS_1640 -9171545 // = -1640 +#define IQ_I_U_VALUE_MINUS_1639 -9165953 // = -1639 +#define IQ_I_U_VALUE_MINUS_1638 -9160360 // = -1638 +#define IQ_I_U_VALUE_MINUS_1637 -9154768 // = -1637 +#define IQ_I_U_VALUE_MINUS_1636 -9149176 // = -1636 +#define IQ_I_U_VALUE_MINUS_1635 -9143583 // = -1635 +#define IQ_I_U_VALUE_MINUS_1634 -9137991 // = -1634 +#define IQ_I_U_VALUE_MINUS_1633 -9132398 // = -1633 +#define IQ_I_U_VALUE_MINUS_1632 -9126806 // = -1632 +#define IQ_I_U_VALUE_MINUS_1631 -9121214 // = -1631 +#define IQ_I_U_VALUE_MINUS_1630 -9115621 // = -1630 +#define IQ_I_U_VALUE_MINUS_1629 -9110029 // = -1629 +#define IQ_I_U_VALUE_MINUS_1628 -9104436 // = -1628 +#define IQ_I_U_VALUE_MINUS_1627 -9098844 // = -1627 +#define IQ_I_U_VALUE_MINUS_1626 -9093252 // = -1626 +#define IQ_I_U_VALUE_MINUS_1625 -9087659 // = -1625 +#define IQ_I_U_VALUE_MINUS_1624 -9082067 // = -1624 +#define IQ_I_U_VALUE_MINUS_1623 -9076474 // = -1623 +#define IQ_I_U_VALUE_MINUS_1622 -9070882 // = -1622 +#define IQ_I_U_VALUE_MINUS_1621 -9065290 // = -1621 +#define IQ_I_U_VALUE_MINUS_1620 -9059697 // = -1620 +#define IQ_I_U_VALUE_MINUS_1619 -9054105 // = -1619 +#define IQ_I_U_VALUE_MINUS_1618 -9048512 // = -1618 +#define IQ_I_U_VALUE_MINUS_1617 -9042920 // = -1617 +#define IQ_I_U_VALUE_MINUS_1616 -9037328 // = -1616 +#define IQ_I_U_VALUE_MINUS_1615 -9031735 // = -1615 +#define IQ_I_U_VALUE_MINUS_1614 -9026143 // = -1614 +#define IQ_I_U_VALUE_MINUS_1613 -9020550 // = -1613 +#define IQ_I_U_VALUE_MINUS_1612 -9014958 // = -1612 +#define IQ_I_U_VALUE_MINUS_1611 -9009365 // = -1611 +#define IQ_I_U_VALUE_MINUS_1610 -9003773 // = -1610 +#define IQ_I_U_VALUE_MINUS_1609 -8998181 // = -1609 +#define IQ_I_U_VALUE_MINUS_1608 -8992588 // = -1608 +#define IQ_I_U_VALUE_MINUS_1607 -8986996 // = -1607 +#define IQ_I_U_VALUE_MINUS_1606 -8981403 // = -1606 +#define IQ_I_U_VALUE_MINUS_1605 -8975811 // = -1605 +#define IQ_I_U_VALUE_MINUS_1604 -8970219 // = -1604 +#define IQ_I_U_VALUE_MINUS_1603 -8964626 // = -1603 +#define IQ_I_U_VALUE_MINUS_1602 -8959034 // = -1602 +#define IQ_I_U_VALUE_MINUS_1601 -8953441 // = -1601 +#define IQ_I_U_VALUE_MINUS_1600 -8947849 // = -1600 +#define IQ_I_U_VALUE_MINUS_1599 -8942257 // = -1599 +#define IQ_I_U_VALUE_MINUS_1598 -8936664 // = -1598 +#define IQ_I_U_VALUE_MINUS_1597 -8931072 // = -1597 +#define IQ_I_U_VALUE_MINUS_1596 -8925479 // = -1596 +#define IQ_I_U_VALUE_MINUS_1595 -8919887 // = -1595 +#define IQ_I_U_VALUE_MINUS_1594 -8914295 // = -1594 +#define IQ_I_U_VALUE_MINUS_1593 -8908702 // = -1593 +#define IQ_I_U_VALUE_MINUS_1592 -8903110 // = -1592 +#define IQ_I_U_VALUE_MINUS_1591 -8897517 // = -1591 +#define IQ_I_U_VALUE_MINUS_1590 -8891925 // = -1590 +#define IQ_I_U_VALUE_MINUS_1589 -8886333 // = -1589 +#define IQ_I_U_VALUE_MINUS_1588 -8880740 // = -1588 +#define IQ_I_U_VALUE_MINUS_1587 -8875148 // = -1587 +#define IQ_I_U_VALUE_MINUS_1586 -8869555 // = -1586 +#define IQ_I_U_VALUE_MINUS_1585 -8863963 // = -1585 +#define IQ_I_U_VALUE_MINUS_1584 -8858371 // = -1584 +#define IQ_I_U_VALUE_MINUS_1583 -8852778 // = -1583 +#define IQ_I_U_VALUE_MINUS_1582 -8847186 // = -1582 +#define IQ_I_U_VALUE_MINUS_1581 -8841593 // = -1581 +#define IQ_I_U_VALUE_MINUS_1580 -8836001 // = -1580 +#define IQ_I_U_VALUE_MINUS_1579 -8830409 // = -1579 +#define IQ_I_U_VALUE_MINUS_1578 -8824816 // = -1578 +#define IQ_I_U_VALUE_MINUS_1577 -8819224 // = -1577 +#define IQ_I_U_VALUE_MINUS_1576 -8813631 // = -1576 +#define IQ_I_U_VALUE_MINUS_1575 -8808039 // = -1575 +#define IQ_I_U_VALUE_MINUS_1574 -8802446 // = -1574 +#define IQ_I_U_VALUE_MINUS_1573 -8796854 // = -1573 +#define IQ_I_U_VALUE_MINUS_1572 -8791262 // = -1572 +#define IQ_I_U_VALUE_MINUS_1571 -8785669 // = -1571 +#define IQ_I_U_VALUE_MINUS_1570 -8780077 // = -1570 +#define IQ_I_U_VALUE_MINUS_1569 -8774484 // = -1569 +#define IQ_I_U_VALUE_MINUS_1568 -8768892 // = -1568 +#define IQ_I_U_VALUE_MINUS_1567 -8763300 // = -1567 +#define IQ_I_U_VALUE_MINUS_1566 -8757707 // = -1566 +#define IQ_I_U_VALUE_MINUS_1565 -8752115 // = -1565 +#define IQ_I_U_VALUE_MINUS_1564 -8746522 // = -1564 +#define IQ_I_U_VALUE_MINUS_1563 -8740930 // = -1563 +#define IQ_I_U_VALUE_MINUS_1562 -8735338 // = -1562 +#define IQ_I_U_VALUE_MINUS_1561 -8729745 // = -1561 +#define IQ_I_U_VALUE_MINUS_1560 -8724153 // = -1560 +#define IQ_I_U_VALUE_MINUS_1559 -8718560 // = -1559 +#define IQ_I_U_VALUE_MINUS_1558 -8712968 // = -1558 +#define IQ_I_U_VALUE_MINUS_1557 -8707376 // = -1557 +#define IQ_I_U_VALUE_MINUS_1556 -8701783 // = -1556 +#define IQ_I_U_VALUE_MINUS_1555 -8696191 // = -1555 +#define IQ_I_U_VALUE_MINUS_1554 -8690598 // = -1554 +#define IQ_I_U_VALUE_MINUS_1553 -8685006 // = -1553 +#define IQ_I_U_VALUE_MINUS_1552 -8679414 // = -1552 +#define IQ_I_U_VALUE_MINUS_1551 -8673821 // = -1551 +#define IQ_I_U_VALUE_MINUS_1550 -8668229 // = -1550 +#define IQ_I_U_VALUE_MINUS_1549 -8662636 // = -1549 +#define IQ_I_U_VALUE_MINUS_1548 -8657044 // = -1548 +#define IQ_I_U_VALUE_MINUS_1547 -8651452 // = -1547 +#define IQ_I_U_VALUE_MINUS_1546 -8645859 // = -1546 +#define IQ_I_U_VALUE_MINUS_1545 -8640267 // = -1545 +#define IQ_I_U_VALUE_MINUS_1544 -8634674 // = -1544 +#define IQ_I_U_VALUE_MINUS_1543 -8629082 // = -1543 +#define IQ_I_U_VALUE_MINUS_1542 -8623490 // = -1542 +#define IQ_I_U_VALUE_MINUS_1541 -8617897 // = -1541 +#define IQ_I_U_VALUE_MINUS_1540 -8612305 // = -1540 +#define IQ_I_U_VALUE_MINUS_1539 -8606712 // = -1539 +#define IQ_I_U_VALUE_MINUS_1538 -8601120 // = -1538 +#define IQ_I_U_VALUE_MINUS_1537 -8595527 // = -1537 +#define IQ_I_U_VALUE_MINUS_1536 -8589935 // = -1536 +#define IQ_I_U_VALUE_MINUS_1535 -8584343 // = -1535 +#define IQ_I_U_VALUE_MINUS_1534 -8578750 // = -1534 +#define IQ_I_U_VALUE_MINUS_1533 -8573158 // = -1533 +#define IQ_I_U_VALUE_MINUS_1532 -8567565 // = -1532 +#define IQ_I_U_VALUE_MINUS_1531 -8561973 // = -1531 +#define IQ_I_U_VALUE_MINUS_1530 -8556381 // = -1530 +#define IQ_I_U_VALUE_MINUS_1529 -8550788 // = -1529 +#define IQ_I_U_VALUE_MINUS_1528 -8545196 // = -1528 +#define IQ_I_U_VALUE_MINUS_1527 -8539603 // = -1527 +#define IQ_I_U_VALUE_MINUS_1526 -8534011 // = -1526 +#define IQ_I_U_VALUE_MINUS_1525 -8528419 // = -1525 +#define IQ_I_U_VALUE_MINUS_1524 -8522826 // = -1524 +#define IQ_I_U_VALUE_MINUS_1523 -8517234 // = -1523 +#define IQ_I_U_VALUE_MINUS_1522 -8511641 // = -1522 +#define IQ_I_U_VALUE_MINUS_1521 -8506049 // = -1521 +#define IQ_I_U_VALUE_MINUS_1520 -8500457 // = -1520 +#define IQ_I_U_VALUE_MINUS_1519 -8494864 // = -1519 +#define IQ_I_U_VALUE_MINUS_1518 -8489272 // = -1518 +#define IQ_I_U_VALUE_MINUS_1517 -8483679 // = -1517 +#define IQ_I_U_VALUE_MINUS_1516 -8478087 // = -1516 +#define IQ_I_U_VALUE_MINUS_1515 -8472495 // = -1515 +#define IQ_I_U_VALUE_MINUS_1514 -8466902 // = -1514 +#define IQ_I_U_VALUE_MINUS_1513 -8461310 // = -1513 +#define IQ_I_U_VALUE_MINUS_1512 -8455717 // = -1512 +#define IQ_I_U_VALUE_MINUS_1511 -8450125 // = -1511 +#define IQ_I_U_VALUE_MINUS_1510 -8444533 // = -1510 +#define IQ_I_U_VALUE_MINUS_1509 -8438940 // = -1509 +#define IQ_I_U_VALUE_MINUS_1508 -8433348 // = -1508 +#define IQ_I_U_VALUE_MINUS_1507 -8427755 // = -1507 +#define IQ_I_U_VALUE_MINUS_1506 -8422163 // = -1506 +#define IQ_I_U_VALUE_MINUS_1505 -8416571 // = -1505 +#define IQ_I_U_VALUE_MINUS_1504 -8410978 // = -1504 +#define IQ_I_U_VALUE_MINUS_1503 -8405386 // = -1503 +#define IQ_I_U_VALUE_MINUS_1502 -8399793 // = -1502 +#define IQ_I_U_VALUE_MINUS_1501 -8394201 // = -1501 +#define IQ_I_U_VALUE_MINUS_1500 -8388608 // = -1500 +#define IQ_I_U_VALUE_MINUS_1499 -8383016 // = -1499 +#define IQ_I_U_VALUE_MINUS_1498 -8377424 // = -1498 +#define IQ_I_U_VALUE_MINUS_1497 -8371831 // = -1497 +#define IQ_I_U_VALUE_MINUS_1496 -8366239 // = -1496 +#define IQ_I_U_VALUE_MINUS_1495 -8360646 // = -1495 +#define IQ_I_U_VALUE_MINUS_1494 -8355054 // = -1494 +#define IQ_I_U_VALUE_MINUS_1493 -8349462 // = -1493 +#define IQ_I_U_VALUE_MINUS_1492 -8343869 // = -1492 +#define IQ_I_U_VALUE_MINUS_1491 -8338277 // = -1491 +#define IQ_I_U_VALUE_MINUS_1490 -8332684 // = -1490 +#define IQ_I_U_VALUE_MINUS_1489 -8327092 // = -1489 +#define IQ_I_U_VALUE_MINUS_1488 -8321500 // = -1488 +#define IQ_I_U_VALUE_MINUS_1487 -8315907 // = -1487 +#define IQ_I_U_VALUE_MINUS_1486 -8310315 // = -1486 +#define IQ_I_U_VALUE_MINUS_1485 -8304722 // = -1485 +#define IQ_I_U_VALUE_MINUS_1484 -8299130 // = -1484 +#define IQ_I_U_VALUE_MINUS_1483 -8293538 // = -1483 +#define IQ_I_U_VALUE_MINUS_1482 -8287945 // = -1482 +#define IQ_I_U_VALUE_MINUS_1481 -8282353 // = -1481 +#define IQ_I_U_VALUE_MINUS_1480 -8276760 // = -1480 +#define IQ_I_U_VALUE_MINUS_1479 -8271168 // = -1479 +#define IQ_I_U_VALUE_MINUS_1478 -8265576 // = -1478 +#define IQ_I_U_VALUE_MINUS_1477 -8259983 // = -1477 +#define IQ_I_U_VALUE_MINUS_1476 -8254391 // = -1476 +#define IQ_I_U_VALUE_MINUS_1475 -8248798 // = -1475 +#define IQ_I_U_VALUE_MINUS_1474 -8243206 // = -1474 +#define IQ_I_U_VALUE_MINUS_1473 -8237614 // = -1473 +#define IQ_I_U_VALUE_MINUS_1472 -8232021 // = -1472 +#define IQ_I_U_VALUE_MINUS_1471 -8226429 // = -1471 +#define IQ_I_U_VALUE_MINUS_1470 -8220836 // = -1470 +#define IQ_I_U_VALUE_MINUS_1469 -8215244 // = -1469 +#define IQ_I_U_VALUE_MINUS_1468 -8209652 // = -1468 +#define IQ_I_U_VALUE_MINUS_1467 -8204059 // = -1467 +#define IQ_I_U_VALUE_MINUS_1466 -8198467 // = -1466 +#define IQ_I_U_VALUE_MINUS_1465 -8192874 // = -1465 +#define IQ_I_U_VALUE_MINUS_1464 -8187282 // = -1464 +#define IQ_I_U_VALUE_MINUS_1463 -8181690 // = -1463 +#define IQ_I_U_VALUE_MINUS_1462 -8176097 // = -1462 +#define IQ_I_U_VALUE_MINUS_1461 -8170505 // = -1461 +#define IQ_I_U_VALUE_MINUS_1460 -8164912 // = -1460 +#define IQ_I_U_VALUE_MINUS_1459 -8159320 // = -1459 +#define IQ_I_U_VALUE_MINUS_1458 -8153727 // = -1458 +#define IQ_I_U_VALUE_MINUS_1457 -8148135 // = -1457 +#define IQ_I_U_VALUE_MINUS_1456 -8142543 // = -1456 +#define IQ_I_U_VALUE_MINUS_1455 -8136950 // = -1455 +#define IQ_I_U_VALUE_MINUS_1454 -8131358 // = -1454 +#define IQ_I_U_VALUE_MINUS_1453 -8125765 // = -1453 +#define IQ_I_U_VALUE_MINUS_1452 -8120173 // = -1452 +#define IQ_I_U_VALUE_MINUS_1451 -8114581 // = -1451 +#define IQ_I_U_VALUE_MINUS_1450 -8108988 // = -1450 +#define IQ_I_U_VALUE_MINUS_1449 -8103396 // = -1449 +#define IQ_I_U_VALUE_MINUS_1448 -8097803 // = -1448 +#define IQ_I_U_VALUE_MINUS_1447 -8092211 // = -1447 +#define IQ_I_U_VALUE_MINUS_1446 -8086619 // = -1446 +#define IQ_I_U_VALUE_MINUS_1445 -8081026 // = -1445 +#define IQ_I_U_VALUE_MINUS_1444 -8075434 // = -1444 +#define IQ_I_U_VALUE_MINUS_1443 -8069841 // = -1443 +#define IQ_I_U_VALUE_MINUS_1442 -8064249 // = -1442 +#define IQ_I_U_VALUE_MINUS_1441 -8058657 // = -1441 +#define IQ_I_U_VALUE_MINUS_1440 -8053064 // = -1440 +#define IQ_I_U_VALUE_MINUS_1439 -8047472 // = -1439 +#define IQ_I_U_VALUE_MINUS_1438 -8041879 // = -1438 +#define IQ_I_U_VALUE_MINUS_1437 -8036287 // = -1437 +#define IQ_I_U_VALUE_MINUS_1436 -8030695 // = -1436 +#define IQ_I_U_VALUE_MINUS_1435 -8025102 // = -1435 +#define IQ_I_U_VALUE_MINUS_1434 -8019510 // = -1434 +#define IQ_I_U_VALUE_MINUS_1433 -8013917 // = -1433 +#define IQ_I_U_VALUE_MINUS_1432 -8008325 // = -1432 +#define IQ_I_U_VALUE_MINUS_1431 -8002733 // = -1431 +#define IQ_I_U_VALUE_MINUS_1430 -7997140 // = -1430 +#define IQ_I_U_VALUE_MINUS_1429 -7991548 // = -1429 +#define IQ_I_U_VALUE_MINUS_1428 -7985955 // = -1428 +#define IQ_I_U_VALUE_MINUS_1427 -7980363 // = -1427 +#define IQ_I_U_VALUE_MINUS_1426 -7974771 // = -1426 +#define IQ_I_U_VALUE_MINUS_1425 -7969178 // = -1425 +#define IQ_I_U_VALUE_MINUS_1424 -7963586 // = -1424 +#define IQ_I_U_VALUE_MINUS_1423 -7957993 // = -1423 +#define IQ_I_U_VALUE_MINUS_1422 -7952401 // = -1422 +#define IQ_I_U_VALUE_MINUS_1421 -7946808 // = -1421 +#define IQ_I_U_VALUE_MINUS_1420 -7941216 // = -1420 +#define IQ_I_U_VALUE_MINUS_1419 -7935624 // = -1419 +#define IQ_I_U_VALUE_MINUS_1418 -7930031 // = -1418 +#define IQ_I_U_VALUE_MINUS_1417 -7924439 // = -1417 +#define IQ_I_U_VALUE_MINUS_1416 -7918846 // = -1416 +#define IQ_I_U_VALUE_MINUS_1415 -7913254 // = -1415 +#define IQ_I_U_VALUE_MINUS_1414 -7907662 // = -1414 +#define IQ_I_U_VALUE_MINUS_1413 -7902069 // = -1413 +#define IQ_I_U_VALUE_MINUS_1412 -7896477 // = -1412 +#define IQ_I_U_VALUE_MINUS_1411 -7890884 // = -1411 +#define IQ_I_U_VALUE_MINUS_1410 -7885292 // = -1410 +#define IQ_I_U_VALUE_MINUS_1409 -7879700 // = -1409 +#define IQ_I_U_VALUE_MINUS_1408 -7874107 // = -1408 +#define IQ_I_U_VALUE_MINUS_1407 -7868515 // = -1407 +#define IQ_I_U_VALUE_MINUS_1406 -7862922 // = -1406 +#define IQ_I_U_VALUE_MINUS_1405 -7857330 // = -1405 +#define IQ_I_U_VALUE_MINUS_1404 -7851738 // = -1404 +#define IQ_I_U_VALUE_MINUS_1403 -7846145 // = -1403 +#define IQ_I_U_VALUE_MINUS_1402 -7840553 // = -1402 +#define IQ_I_U_VALUE_MINUS_1401 -7834960 // = -1401 +#define IQ_I_U_VALUE_MINUS_1400 -7829368 // = -1400 +#define IQ_I_U_VALUE_MINUS_1399 -7823776 // = -1399 +#define IQ_I_U_VALUE_MINUS_1398 -7818183 // = -1398 +#define IQ_I_U_VALUE_MINUS_1397 -7812591 // = -1397 +#define IQ_I_U_VALUE_MINUS_1396 -7806998 // = -1396 +#define IQ_I_U_VALUE_MINUS_1395 -7801406 // = -1395 +#define IQ_I_U_VALUE_MINUS_1394 -7795814 // = -1394 +#define IQ_I_U_VALUE_MINUS_1393 -7790221 // = -1393 +#define IQ_I_U_VALUE_MINUS_1392 -7784629 // = -1392 +#define IQ_I_U_VALUE_MINUS_1391 -7779036 // = -1391 +#define IQ_I_U_VALUE_MINUS_1390 -7773444 // = -1390 +#define IQ_I_U_VALUE_MINUS_1389 -7767852 // = -1389 +#define IQ_I_U_VALUE_MINUS_1388 -7762259 // = -1388 +#define IQ_I_U_VALUE_MINUS_1387 -7756667 // = -1387 +#define IQ_I_U_VALUE_MINUS_1386 -7751074 // = -1386 +#define IQ_I_U_VALUE_MINUS_1385 -7745482 // = -1385 +#define IQ_I_U_VALUE_MINUS_1384 -7739889 // = -1384 +#define IQ_I_U_VALUE_MINUS_1383 -7734297 // = -1383 +#define IQ_I_U_VALUE_MINUS_1382 -7728705 // = -1382 +#define IQ_I_U_VALUE_MINUS_1381 -7723112 // = -1381 +#define IQ_I_U_VALUE_MINUS_1380 -7717520 // = -1380 +#define IQ_I_U_VALUE_MINUS_1379 -7711927 // = -1379 +#define IQ_I_U_VALUE_MINUS_1378 -7706335 // = -1378 +#define IQ_I_U_VALUE_MINUS_1377 -7700743 // = -1377 +#define IQ_I_U_VALUE_MINUS_1376 -7695150 // = -1376 +#define IQ_I_U_VALUE_MINUS_1375 -7689558 // = -1375 +#define IQ_I_U_VALUE_MINUS_1374 -7683965 // = -1374 +#define IQ_I_U_VALUE_MINUS_1373 -7678373 // = -1373 +#define IQ_I_U_VALUE_MINUS_1372 -7672781 // = -1372 +#define IQ_I_U_VALUE_MINUS_1371 -7667188 // = -1371 +#define IQ_I_U_VALUE_MINUS_1370 -7661596 // = -1370 +#define IQ_I_U_VALUE_MINUS_1369 -7656003 // = -1369 +#define IQ_I_U_VALUE_MINUS_1368 -7650411 // = -1368 +#define IQ_I_U_VALUE_MINUS_1367 -7644819 // = -1367 +#define IQ_I_U_VALUE_MINUS_1366 -7639226 // = -1366 +#define IQ_I_U_VALUE_MINUS_1365 -7633634 // = -1365 +#define IQ_I_U_VALUE_MINUS_1364 -7628041 // = -1364 +#define IQ_I_U_VALUE_MINUS_1363 -7622449 // = -1363 +#define IQ_I_U_VALUE_MINUS_1362 -7616857 // = -1362 +#define IQ_I_U_VALUE_MINUS_1361 -7611264 // = -1361 +#define IQ_I_U_VALUE_MINUS_1360 -7605672 // = -1360 +#define IQ_I_U_VALUE_MINUS_1359 -7600079 // = -1359 +#define IQ_I_U_VALUE_MINUS_1358 -7594487 // = -1358 +#define IQ_I_U_VALUE_MINUS_1357 -7588895 // = -1357 +#define IQ_I_U_VALUE_MINUS_1356 -7583302 // = -1356 +#define IQ_I_U_VALUE_MINUS_1355 -7577710 // = -1355 +#define IQ_I_U_VALUE_MINUS_1354 -7572117 // = -1354 +#define IQ_I_U_VALUE_MINUS_1353 -7566525 // = -1353 +#define IQ_I_U_VALUE_MINUS_1352 -7560933 // = -1352 +#define IQ_I_U_VALUE_MINUS_1351 -7555340 // = -1351 +#define IQ_I_U_VALUE_MINUS_1350 -7549748 // = -1350 +#define IQ_I_U_VALUE_MINUS_1349 -7544155 // = -1349 +#define IQ_I_U_VALUE_MINUS_1348 -7538563 // = -1348 +#define IQ_I_U_VALUE_MINUS_1347 -7532970 // = -1347 +#define IQ_I_U_VALUE_MINUS_1346 -7527378 // = -1346 +#define IQ_I_U_VALUE_MINUS_1345 -7521786 // = -1345 +#define IQ_I_U_VALUE_MINUS_1344 -7516193 // = -1344 +#define IQ_I_U_VALUE_MINUS_1343 -7510601 // = -1343 +#define IQ_I_U_VALUE_MINUS_1342 -7505008 // = -1342 +#define IQ_I_U_VALUE_MINUS_1341 -7499416 // = -1341 +#define IQ_I_U_VALUE_MINUS_1340 -7493824 // = -1340 +#define IQ_I_U_VALUE_MINUS_1339 -7488231 // = -1339 +#define IQ_I_U_VALUE_MINUS_1338 -7482639 // = -1338 +#define IQ_I_U_VALUE_MINUS_1337 -7477046 // = -1337 +#define IQ_I_U_VALUE_MINUS_1336 -7471454 // = -1336 +#define IQ_I_U_VALUE_MINUS_1335 -7465862 // = -1335 +#define IQ_I_U_VALUE_MINUS_1334 -7460269 // = -1334 +#define IQ_I_U_VALUE_MINUS_1333 -7454677 // = -1333 +#define IQ_I_U_VALUE_MINUS_1332 -7449084 // = -1332 +#define IQ_I_U_VALUE_MINUS_1331 -7443492 // = -1331 +#define IQ_I_U_VALUE_MINUS_1330 -7437900 // = -1330 +#define IQ_I_U_VALUE_MINUS_1329 -7432307 // = -1329 +#define IQ_I_U_VALUE_MINUS_1328 -7426715 // = -1328 +#define IQ_I_U_VALUE_MINUS_1327 -7421122 // = -1327 +#define IQ_I_U_VALUE_MINUS_1326 -7415530 // = -1326 +#define IQ_I_U_VALUE_MINUS_1325 -7409938 // = -1325 +#define IQ_I_U_VALUE_MINUS_1324 -7404345 // = -1324 +#define IQ_I_U_VALUE_MINUS_1323 -7398753 // = -1323 +#define IQ_I_U_VALUE_MINUS_1322 -7393160 // = -1322 +#define IQ_I_U_VALUE_MINUS_1321 -7387568 // = -1321 +#define IQ_I_U_VALUE_MINUS_1320 -7381976 // = -1320 +#define IQ_I_U_VALUE_MINUS_1319 -7376383 // = -1319 +#define IQ_I_U_VALUE_MINUS_1318 -7370791 // = -1318 +#define IQ_I_U_VALUE_MINUS_1317 -7365198 // = -1317 +#define IQ_I_U_VALUE_MINUS_1316 -7359606 // = -1316 +#define IQ_I_U_VALUE_MINUS_1315 -7354014 // = -1315 +#define IQ_I_U_VALUE_MINUS_1314 -7348421 // = -1314 +#define IQ_I_U_VALUE_MINUS_1313 -7342829 // = -1313 +#define IQ_I_U_VALUE_MINUS_1312 -7337236 // = -1312 +#define IQ_I_U_VALUE_MINUS_1311 -7331644 // = -1311 +#define IQ_I_U_VALUE_MINUS_1310 -7326051 // = -1310 +#define IQ_I_U_VALUE_MINUS_1309 -7320459 // = -1309 +#define IQ_I_U_VALUE_MINUS_1308 -7314867 // = -1308 +#define IQ_I_U_VALUE_MINUS_1307 -7309274 // = -1307 +#define IQ_I_U_VALUE_MINUS_1306 -7303682 // = -1306 +#define IQ_I_U_VALUE_MINUS_1305 -7298089 // = -1305 +#define IQ_I_U_VALUE_MINUS_1304 -7292497 // = -1304 +#define IQ_I_U_VALUE_MINUS_1303 -7286905 // = -1303 +#define IQ_I_U_VALUE_MINUS_1302 -7281312 // = -1302 +#define IQ_I_U_VALUE_MINUS_1301 -7275720 // = -1301 +#define IQ_I_U_VALUE_MINUS_1300 -7270127 // = -1300 +#define IQ_I_U_VALUE_MINUS_1299 -7264535 // = -1299 +#define IQ_I_U_VALUE_MINUS_1298 -7258943 // = -1298 +#define IQ_I_U_VALUE_MINUS_1297 -7253350 // = -1297 +#define IQ_I_U_VALUE_MINUS_1296 -7247758 // = -1296 +#define IQ_I_U_VALUE_MINUS_1295 -7242165 // = -1295 +#define IQ_I_U_VALUE_MINUS_1294 -7236573 // = -1294 +#define IQ_I_U_VALUE_MINUS_1293 -7230981 // = -1293 +#define IQ_I_U_VALUE_MINUS_1292 -7225388 // = -1292 +#define IQ_I_U_VALUE_MINUS_1291 -7219796 // = -1291 +#define IQ_I_U_VALUE_MINUS_1290 -7214203 // = -1290 +#define IQ_I_U_VALUE_MINUS_1289 -7208611 // = -1289 +#define IQ_I_U_VALUE_MINUS_1288 -7203019 // = -1288 +#define IQ_I_U_VALUE_MINUS_1287 -7197426 // = -1287 +#define IQ_I_U_VALUE_MINUS_1286 -7191834 // = -1286 +#define IQ_I_U_VALUE_MINUS_1285 -7186241 // = -1285 +#define IQ_I_U_VALUE_MINUS_1284 -7180649 // = -1284 +#define IQ_I_U_VALUE_MINUS_1283 -7175057 // = -1283 +#define IQ_I_U_VALUE_MINUS_1282 -7169464 // = -1282 +#define IQ_I_U_VALUE_MINUS_1281 -7163872 // = -1281 +#define IQ_I_U_VALUE_MINUS_1280 -7158279 // = -1280 +#define IQ_I_U_VALUE_MINUS_1279 -7152687 // = -1279 +#define IQ_I_U_VALUE_MINUS_1278 -7147095 // = -1278 +#define IQ_I_U_VALUE_MINUS_1277 -7141502 // = -1277 +#define IQ_I_U_VALUE_MINUS_1276 -7135910 // = -1276 +#define IQ_I_U_VALUE_MINUS_1275 -7130317 // = -1275 +#define IQ_I_U_VALUE_MINUS_1274 -7124725 // = -1274 +#define IQ_I_U_VALUE_MINUS_1273 -7119132 // = -1273 +#define IQ_I_U_VALUE_MINUS_1272 -7113540 // = -1272 +#define IQ_I_U_VALUE_MINUS_1271 -7107948 // = -1271 +#define IQ_I_U_VALUE_MINUS_1270 -7102355 // = -1270 +#define IQ_I_U_VALUE_MINUS_1269 -7096763 // = -1269 +#define IQ_I_U_VALUE_MINUS_1268 -7091170 // = -1268 +#define IQ_I_U_VALUE_MINUS_1267 -7085578 // = -1267 +#define IQ_I_U_VALUE_MINUS_1266 -7079986 // = -1266 +#define IQ_I_U_VALUE_MINUS_1265 -7074393 // = -1265 +#define IQ_I_U_VALUE_MINUS_1264 -7068801 // = -1264 +#define IQ_I_U_VALUE_MINUS_1263 -7063208 // = -1263 +#define IQ_I_U_VALUE_MINUS_1262 -7057616 // = -1262 +#define IQ_I_U_VALUE_MINUS_1261 -7052024 // = -1261 +#define IQ_I_U_VALUE_MINUS_1260 -7046431 // = -1260 +#define IQ_I_U_VALUE_MINUS_1259 -7040839 // = -1259 +#define IQ_I_U_VALUE_MINUS_1258 -7035246 // = -1258 +#define IQ_I_U_VALUE_MINUS_1257 -7029654 // = -1257 +#define IQ_I_U_VALUE_MINUS_1256 -7024062 // = -1256 +#define IQ_I_U_VALUE_MINUS_1255 -7018469 // = -1255 +#define IQ_I_U_VALUE_MINUS_1254 -7012877 // = -1254 +#define IQ_I_U_VALUE_MINUS_1253 -7007284 // = -1253 +#define IQ_I_U_VALUE_MINUS_1252 -7001692 // = -1252 +#define IQ_I_U_VALUE_MINUS_1251 -6996100 // = -1251 +#define IQ_I_U_VALUE_MINUS_1250 -6990507 // = -1250 +#define IQ_I_U_VALUE_MINUS_1249 -6984915 // = -1249 +#define IQ_I_U_VALUE_MINUS_1248 -6979322 // = -1248 +#define IQ_I_U_VALUE_MINUS_1247 -6973730 // = -1247 +#define IQ_I_U_VALUE_MINUS_1246 -6968138 // = -1246 +#define IQ_I_U_VALUE_MINUS_1245 -6962545 // = -1245 +#define IQ_I_U_VALUE_MINUS_1244 -6956953 // = -1244 +#define IQ_I_U_VALUE_MINUS_1243 -6951360 // = -1243 +#define IQ_I_U_VALUE_MINUS_1242 -6945768 // = -1242 +#define IQ_I_U_VALUE_MINUS_1241 -6940176 // = -1241 +#define IQ_I_U_VALUE_MINUS_1240 -6934583 // = -1240 +#define IQ_I_U_VALUE_MINUS_1239 -6928991 // = -1239 +#define IQ_I_U_VALUE_MINUS_1238 -6923398 // = -1238 +#define IQ_I_U_VALUE_MINUS_1237 -6917806 // = -1237 +#define IQ_I_U_VALUE_MINUS_1236 -6912213 // = -1236 +#define IQ_I_U_VALUE_MINUS_1235 -6906621 // = -1235 +#define IQ_I_U_VALUE_MINUS_1234 -6901029 // = -1234 +#define IQ_I_U_VALUE_MINUS_1233 -6895436 // = -1233 +#define IQ_I_U_VALUE_MINUS_1232 -6889844 // = -1232 +#define IQ_I_U_VALUE_MINUS_1231 -6884251 // = -1231 +#define IQ_I_U_VALUE_MINUS_1230 -6878659 // = -1230 +#define IQ_I_U_VALUE_MINUS_1229 -6873067 // = -1229 +#define IQ_I_U_VALUE_MINUS_1228 -6867474 // = -1228 +#define IQ_I_U_VALUE_MINUS_1227 -6861882 // = -1227 +#define IQ_I_U_VALUE_MINUS_1226 -6856289 // = -1226 +#define IQ_I_U_VALUE_MINUS_1225 -6850697 // = -1225 +#define IQ_I_U_VALUE_MINUS_1224 -6845105 // = -1224 +#define IQ_I_U_VALUE_MINUS_1223 -6839512 // = -1223 +#define IQ_I_U_VALUE_MINUS_1222 -6833920 // = -1222 +#define IQ_I_U_VALUE_MINUS_1221 -6828327 // = -1221 +#define IQ_I_U_VALUE_MINUS_1220 -6822735 // = -1220 +#define IQ_I_U_VALUE_MINUS_1219 -6817143 // = -1219 +#define IQ_I_U_VALUE_MINUS_1218 -6811550 // = -1218 +#define IQ_I_U_VALUE_MINUS_1217 -6805958 // = -1217 +#define IQ_I_U_VALUE_MINUS_1216 -6800365 // = -1216 +#define IQ_I_U_VALUE_MINUS_1215 -6794773 // = -1215 +#define IQ_I_U_VALUE_MINUS_1214 -6789181 // = -1214 +#define IQ_I_U_VALUE_MINUS_1213 -6783588 // = -1213 +#define IQ_I_U_VALUE_MINUS_1212 -6777996 // = -1212 +#define IQ_I_U_VALUE_MINUS_1211 -6772403 // = -1211 +#define IQ_I_U_VALUE_MINUS_1210 -6766811 // = -1210 +#define IQ_I_U_VALUE_MINUS_1209 -6761219 // = -1209 +#define IQ_I_U_VALUE_MINUS_1208 -6755626 // = -1208 +#define IQ_I_U_VALUE_MINUS_1207 -6750034 // = -1207 +#define IQ_I_U_VALUE_MINUS_1206 -6744441 // = -1206 +#define IQ_I_U_VALUE_MINUS_1205 -6738849 // = -1205 +#define IQ_I_U_VALUE_MINUS_1204 -6733257 // = -1204 +#define IQ_I_U_VALUE_MINUS_1203 -6727664 // = -1203 +#define IQ_I_U_VALUE_MINUS_1202 -6722072 // = -1202 +#define IQ_I_U_VALUE_MINUS_1201 -6716479 // = -1201 +#define IQ_I_U_VALUE_MINUS_1200 -6710887 // = -1200 +#define IQ_I_U_VALUE_MINUS_1199 -6705294 // = -1199 +#define IQ_I_U_VALUE_MINUS_1198 -6699702 // = -1198 +#define IQ_I_U_VALUE_MINUS_1197 -6694110 // = -1197 +#define IQ_I_U_VALUE_MINUS_1196 -6688517 // = -1196 +#define IQ_I_U_VALUE_MINUS_1195 -6682925 // = -1195 +#define IQ_I_U_VALUE_MINUS_1194 -6677332 // = -1194 +#define IQ_I_U_VALUE_MINUS_1193 -6671740 // = -1193 +#define IQ_I_U_VALUE_MINUS_1192 -6666148 // = -1192 +#define IQ_I_U_VALUE_MINUS_1191 -6660555 // = -1191 +#define IQ_I_U_VALUE_MINUS_1190 -6654963 // = -1190 +#define IQ_I_U_VALUE_MINUS_1189 -6649370 // = -1189 +#define IQ_I_U_VALUE_MINUS_1188 -6643778 // = -1188 +#define IQ_I_U_VALUE_MINUS_1187 -6638186 // = -1187 +#define IQ_I_U_VALUE_MINUS_1186 -6632593 // = -1186 +#define IQ_I_U_VALUE_MINUS_1185 -6627001 // = -1185 +#define IQ_I_U_VALUE_MINUS_1184 -6621408 // = -1184 +#define IQ_I_U_VALUE_MINUS_1183 -6615816 // = -1183 +#define IQ_I_U_VALUE_MINUS_1182 -6610224 // = -1182 +#define IQ_I_U_VALUE_MINUS_1181 -6604631 // = -1181 +#define IQ_I_U_VALUE_MINUS_1180 -6599039 // = -1180 +#define IQ_I_U_VALUE_MINUS_1179 -6593446 // = -1179 +#define IQ_I_U_VALUE_MINUS_1178 -6587854 // = -1178 +#define IQ_I_U_VALUE_MINUS_1177 -6582262 // = -1177 +#define IQ_I_U_VALUE_MINUS_1176 -6576669 // = -1176 +#define IQ_I_U_VALUE_MINUS_1175 -6571077 // = -1175 +#define IQ_I_U_VALUE_MINUS_1174 -6565484 // = -1174 +#define IQ_I_U_VALUE_MINUS_1173 -6559892 // = -1173 +#define IQ_I_U_VALUE_MINUS_1172 -6554300 // = -1172 +#define IQ_I_U_VALUE_MINUS_1171 -6548707 // = -1171 +#define IQ_I_U_VALUE_MINUS_1170 -6543115 // = -1170 +#define IQ_I_U_VALUE_MINUS_1169 -6537522 // = -1169 +#define IQ_I_U_VALUE_MINUS_1168 -6531930 // = -1168 +#define IQ_I_U_VALUE_MINUS_1167 -6526338 // = -1167 +#define IQ_I_U_VALUE_MINUS_1166 -6520745 // = -1166 +#define IQ_I_U_VALUE_MINUS_1165 -6515153 // = -1165 +#define IQ_I_U_VALUE_MINUS_1164 -6509560 // = -1164 +#define IQ_I_U_VALUE_MINUS_1163 -6503968 // = -1163 +#define IQ_I_U_VALUE_MINUS_1162 -6498375 // = -1162 +#define IQ_I_U_VALUE_MINUS_1161 -6492783 // = -1161 +#define IQ_I_U_VALUE_MINUS_1160 -6487191 // = -1160 +#define IQ_I_U_VALUE_MINUS_1159 -6481598 // = -1159 +#define IQ_I_U_VALUE_MINUS_1158 -6476006 // = -1158 +#define IQ_I_U_VALUE_MINUS_1157 -6470413 // = -1157 +#define IQ_I_U_VALUE_MINUS_1156 -6464821 // = -1156 +#define IQ_I_U_VALUE_MINUS_1155 -6459229 // = -1155 +#define IQ_I_U_VALUE_MINUS_1154 -6453636 // = -1154 +#define IQ_I_U_VALUE_MINUS_1153 -6448044 // = -1153 +#define IQ_I_U_VALUE_MINUS_1152 -6442451 // = -1152 +#define IQ_I_U_VALUE_MINUS_1151 -6436859 // = -1151 +#define IQ_I_U_VALUE_MINUS_1150 -6431267 // = -1150 +#define IQ_I_U_VALUE_MINUS_1149 -6425674 // = -1149 +#define IQ_I_U_VALUE_MINUS_1148 -6420082 // = -1148 +#define IQ_I_U_VALUE_MINUS_1147 -6414489 // = -1147 +#define IQ_I_U_VALUE_MINUS_1146 -6408897 // = -1146 +#define IQ_I_U_VALUE_MINUS_1145 -6403305 // = -1145 +#define IQ_I_U_VALUE_MINUS_1144 -6397712 // = -1144 +#define IQ_I_U_VALUE_MINUS_1143 -6392120 // = -1143 +#define IQ_I_U_VALUE_MINUS_1142 -6386527 // = -1142 +#define IQ_I_U_VALUE_MINUS_1141 -6380935 // = -1141 +#define IQ_I_U_VALUE_MINUS_1140 -6375343 // = -1140 +#define IQ_I_U_VALUE_MINUS_1139 -6369750 // = -1139 +#define IQ_I_U_VALUE_MINUS_1138 -6364158 // = -1138 +#define IQ_I_U_VALUE_MINUS_1137 -6358565 // = -1137 +#define IQ_I_U_VALUE_MINUS_1136 -6352973 // = -1136 +#define IQ_I_U_VALUE_MINUS_1135 -6347381 // = -1135 +#define IQ_I_U_VALUE_MINUS_1134 -6341788 // = -1134 +#define IQ_I_U_VALUE_MINUS_1133 -6336196 // = -1133 +#define IQ_I_U_VALUE_MINUS_1132 -6330603 // = -1132 +#define IQ_I_U_VALUE_MINUS_1131 -6325011 // = -1131 +#define IQ_I_U_VALUE_MINUS_1130 -6319419 // = -1130 +#define IQ_I_U_VALUE_MINUS_1129 -6313826 // = -1129 +#define IQ_I_U_VALUE_MINUS_1128 -6308234 // = -1128 +#define IQ_I_U_VALUE_MINUS_1127 -6302641 // = -1127 +#define IQ_I_U_VALUE_MINUS_1126 -6297049 // = -1126 +#define IQ_I_U_VALUE_MINUS_1125 -6291456 // = -1125 +#define IQ_I_U_VALUE_MINUS_1124 -6285864 // = -1124 +#define IQ_I_U_VALUE_MINUS_1123 -6280272 // = -1123 +#define IQ_I_U_VALUE_MINUS_1122 -6274679 // = -1122 +#define IQ_I_U_VALUE_MINUS_1121 -6269087 // = -1121 +#define IQ_I_U_VALUE_MINUS_1120 -6263494 // = -1120 +#define IQ_I_U_VALUE_MINUS_1119 -6257902 // = -1119 +#define IQ_I_U_VALUE_MINUS_1118 -6252310 // = -1118 +#define IQ_I_U_VALUE_MINUS_1117 -6246717 // = -1117 +#define IQ_I_U_VALUE_MINUS_1116 -6241125 // = -1116 +#define IQ_I_U_VALUE_MINUS_1115 -6235532 // = -1115 +#define IQ_I_U_VALUE_MINUS_1114 -6229940 // = -1114 +#define IQ_I_U_VALUE_MINUS_1113 -6224348 // = -1113 +#define IQ_I_U_VALUE_MINUS_1112 -6218755 // = -1112 +#define IQ_I_U_VALUE_MINUS_1111 -6213163 // = -1111 +#define IQ_I_U_VALUE_MINUS_1110 -6207570 // = -1110 +#define IQ_I_U_VALUE_MINUS_1109 -6201978 // = -1109 +#define IQ_I_U_VALUE_MINUS_1108 -6196386 // = -1108 +#define IQ_I_U_VALUE_MINUS_1107 -6190793 // = -1107 +#define IQ_I_U_VALUE_MINUS_1106 -6185201 // = -1106 +#define IQ_I_U_VALUE_MINUS_1105 -6179608 // = -1105 +#define IQ_I_U_VALUE_MINUS_1104 -6174016 // = -1104 +#define IQ_I_U_VALUE_MINUS_1103 -6168424 // = -1103 +#define IQ_I_U_VALUE_MINUS_1102 -6162831 // = -1102 +#define IQ_I_U_VALUE_MINUS_1101 -6157239 // = -1101 +#define IQ_I_U_VALUE_MINUS_1100 -6151646 // = -1100 +#define IQ_I_U_VALUE_MINUS_1099 -6146054 // = -1099 +#define IQ_I_U_VALUE_MINUS_1098 -6140462 // = -1098 +#define IQ_I_U_VALUE_MINUS_1097 -6134869 // = -1097 +#define IQ_I_U_VALUE_MINUS_1096 -6129277 // = -1096 +#define IQ_I_U_VALUE_MINUS_1095 -6123684 // = -1095 +#define IQ_I_U_VALUE_MINUS_1094 -6118092 // = -1094 +#define IQ_I_U_VALUE_MINUS_1093 -6112500 // = -1093 +#define IQ_I_U_VALUE_MINUS_1092 -6106907 // = -1092 +#define IQ_I_U_VALUE_MINUS_1091 -6101315 // = -1091 +#define IQ_I_U_VALUE_MINUS_1090 -6095722 // = -1090 +#define IQ_I_U_VALUE_MINUS_1089 -6090130 // = -1089 +#define IQ_I_U_VALUE_MINUS_1088 -6084538 // = -1088 +#define IQ_I_U_VALUE_MINUS_1087 -6078945 // = -1087 +#define IQ_I_U_VALUE_MINUS_1086 -6073353 // = -1086 +#define IQ_I_U_VALUE_MINUS_1085 -6067760 // = -1085 +#define IQ_I_U_VALUE_MINUS_1084 -6062168 // = -1084 +#define IQ_I_U_VALUE_MINUS_1083 -6056575 // = -1083 +#define IQ_I_U_VALUE_MINUS_1082 -6050983 // = -1082 +#define IQ_I_U_VALUE_MINUS_1081 -6045391 // = -1081 +#define IQ_I_U_VALUE_MINUS_1080 -6039798 // = -1080 +#define IQ_I_U_VALUE_MINUS_1079 -6034206 // = -1079 +#define IQ_I_U_VALUE_MINUS_1078 -6028613 // = -1078 +#define IQ_I_U_VALUE_MINUS_1077 -6023021 // = -1077 +#define IQ_I_U_VALUE_MINUS_1076 -6017429 // = -1076 +#define IQ_I_U_VALUE_MINUS_1075 -6011836 // = -1075 +#define IQ_I_U_VALUE_MINUS_1074 -6006244 // = -1074 +#define IQ_I_U_VALUE_MINUS_1073 -6000651 // = -1073 +#define IQ_I_U_VALUE_MINUS_1072 -5995059 // = -1072 +#define IQ_I_U_VALUE_MINUS_1071 -5989467 // = -1071 +#define IQ_I_U_VALUE_MINUS_1070 -5983874 // = -1070 +#define IQ_I_U_VALUE_MINUS_1069 -5978282 // = -1069 +#define IQ_I_U_VALUE_MINUS_1068 -5972689 // = -1068 +#define IQ_I_U_VALUE_MINUS_1067 -5967097 // = -1067 +#define IQ_I_U_VALUE_MINUS_1066 -5961505 // = -1066 +#define IQ_I_U_VALUE_MINUS_1065 -5955912 // = -1065 +#define IQ_I_U_VALUE_MINUS_1064 -5950320 // = -1064 +#define IQ_I_U_VALUE_MINUS_1063 -5944727 // = -1063 +#define IQ_I_U_VALUE_MINUS_1062 -5939135 // = -1062 +#define IQ_I_U_VALUE_MINUS_1061 -5933543 // = -1061 +#define IQ_I_U_VALUE_MINUS_1060 -5927950 // = -1060 +#define IQ_I_U_VALUE_MINUS_1059 -5922358 // = -1059 +#define IQ_I_U_VALUE_MINUS_1058 -5916765 // = -1058 +#define IQ_I_U_VALUE_MINUS_1057 -5911173 // = -1057 +#define IQ_I_U_VALUE_MINUS_1056 -5905581 // = -1056 +#define IQ_I_U_VALUE_MINUS_1055 -5899988 // = -1055 +#define IQ_I_U_VALUE_MINUS_1054 -5894396 // = -1054 +#define IQ_I_U_VALUE_MINUS_1053 -5888803 // = -1053 +#define IQ_I_U_VALUE_MINUS_1052 -5883211 // = -1052 +#define IQ_I_U_VALUE_MINUS_1051 -5877619 // = -1051 +#define IQ_I_U_VALUE_MINUS_1050 -5872026 // = -1050 +#define IQ_I_U_VALUE_MINUS_1049 -5866434 // = -1049 +#define IQ_I_U_VALUE_MINUS_1048 -5860841 // = -1048 +#define IQ_I_U_VALUE_MINUS_1047 -5855249 // = -1047 +#define IQ_I_U_VALUE_MINUS_1046 -5849656 // = -1046 +#define IQ_I_U_VALUE_MINUS_1045 -5844064 // = -1045 +#define IQ_I_U_VALUE_MINUS_1044 -5838472 // = -1044 +#define IQ_I_U_VALUE_MINUS_1043 -5832879 // = -1043 +#define IQ_I_U_VALUE_MINUS_1042 -5827287 // = -1042 +#define IQ_I_U_VALUE_MINUS_1041 -5821694 // = -1041 +#define IQ_I_U_VALUE_MINUS_1040 -5816102 // = -1040 +#define IQ_I_U_VALUE_MINUS_1039 -5810510 // = -1039 +#define IQ_I_U_VALUE_MINUS_1038 -5804917 // = -1038 +#define IQ_I_U_VALUE_MINUS_1037 -5799325 // = -1037 +#define IQ_I_U_VALUE_MINUS_1036 -5793732 // = -1036 +#define IQ_I_U_VALUE_MINUS_1035 -5788140 // = -1035 +#define IQ_I_U_VALUE_MINUS_1034 -5782548 // = -1034 +#define IQ_I_U_VALUE_MINUS_1033 -5776955 // = -1033 +#define IQ_I_U_VALUE_MINUS_1032 -5771363 // = -1032 +#define IQ_I_U_VALUE_MINUS_1031 -5765770 // = -1031 +#define IQ_I_U_VALUE_MINUS_1030 -5760178 // = -1030 +#define IQ_I_U_VALUE_MINUS_1029 -5754586 // = -1029 +#define IQ_I_U_VALUE_MINUS_1028 -5748993 // = -1028 +#define IQ_I_U_VALUE_MINUS_1027 -5743401 // = -1027 +#define IQ_I_U_VALUE_MINUS_1026 -5737808 // = -1026 +#define IQ_I_U_VALUE_MINUS_1025 -5732216 // = -1025 +#define IQ_I_U_VALUE_MINUS_1024 -5726624 // = -1024 +#define IQ_I_U_VALUE_MINUS_1023 -5721031 // = -1023 +#define IQ_I_U_VALUE_MINUS_1022 -5715439 // = -1022 +#define IQ_I_U_VALUE_MINUS_1021 -5709846 // = -1021 +#define IQ_I_U_VALUE_MINUS_1020 -5704254 // = -1020 +#define IQ_I_U_VALUE_MINUS_1019 -5698662 // = -1019 +#define IQ_I_U_VALUE_MINUS_1018 -5693069 // = -1018 +#define IQ_I_U_VALUE_MINUS_1017 -5687477 // = -1017 +#define IQ_I_U_VALUE_MINUS_1016 -5681884 // = -1016 +#define IQ_I_U_VALUE_MINUS_1015 -5676292 // = -1015 +#define IQ_I_U_VALUE_MINUS_1014 -5670700 // = -1014 +#define IQ_I_U_VALUE_MINUS_1013 -5665107 // = -1013 +#define IQ_I_U_VALUE_MINUS_1012 -5659515 // = -1012 +#define IQ_I_U_VALUE_MINUS_1011 -5653922 // = -1011 +#define IQ_I_U_VALUE_MINUS_1010 -5648330 // = -1010 +#define IQ_I_U_VALUE_MINUS_1009 -5642737 // = -1009 +#define IQ_I_U_VALUE_MINUS_1008 -5637145 // = -1008 +#define IQ_I_U_VALUE_MINUS_1007 -5631553 // = -1007 +#define IQ_I_U_VALUE_MINUS_1006 -5625960 // = -1006 +#define IQ_I_U_VALUE_MINUS_1005 -5620368 // = -1005 +#define IQ_I_U_VALUE_MINUS_1004 -5614775 // = -1004 +#define IQ_I_U_VALUE_MINUS_1003 -5609183 // = -1003 +#define IQ_I_U_VALUE_MINUS_1002 -5603591 // = -1002 +#define IQ_I_U_VALUE_MINUS_1001 -5597998 // = -1001 +#define IQ_I_U_VALUE_MINUS_1000 -5592406 // = -1000 +#define IQ_I_U_VALUE_MINUS_999 -5586813 // = -999 +#define IQ_I_U_VALUE_MINUS_998 -5581221 // = -998 +#define IQ_I_U_VALUE_MINUS_997 -5575629 // = -997 +#define IQ_I_U_VALUE_MINUS_996 -5570036 // = -996 +#define IQ_I_U_VALUE_MINUS_995 -5564444 // = -995 +#define IQ_I_U_VALUE_MINUS_994 -5558851 // = -994 +#define IQ_I_U_VALUE_MINUS_993 -5553259 // = -993 +#define IQ_I_U_VALUE_MINUS_992 -5547667 // = -992 +#define IQ_I_U_VALUE_MINUS_991 -5542074 // = -991 +#define IQ_I_U_VALUE_MINUS_990 -5536482 // = -990 +#define IQ_I_U_VALUE_MINUS_989 -5530889 // = -989 +#define IQ_I_U_VALUE_MINUS_988 -5525297 // = -988 +#define IQ_I_U_VALUE_MINUS_987 -5519705 // = -987 +#define IQ_I_U_VALUE_MINUS_986 -5514112 // = -986 +#define IQ_I_U_VALUE_MINUS_985 -5508520 // = -985 +#define IQ_I_U_VALUE_MINUS_984 -5502927 // = -984 +#define IQ_I_U_VALUE_MINUS_983 -5497335 // = -983 +#define IQ_I_U_VALUE_MINUS_982 -5491743 // = -982 +#define IQ_I_U_VALUE_MINUS_981 -5486150 // = -981 +#define IQ_I_U_VALUE_MINUS_980 -5480558 // = -980 +#define IQ_I_U_VALUE_MINUS_979 -5474965 // = -979 +#define IQ_I_U_VALUE_MINUS_978 -5469373 // = -978 +#define IQ_I_U_VALUE_MINUS_977 -5463781 // = -977 +#define IQ_I_U_VALUE_MINUS_976 -5458188 // = -976 +#define IQ_I_U_VALUE_MINUS_975 -5452596 // = -975 +#define IQ_I_U_VALUE_MINUS_974 -5447003 // = -974 +#define IQ_I_U_VALUE_MINUS_973 -5441411 // = -973 +#define IQ_I_U_VALUE_MINUS_972 -5435818 // = -972 +#define IQ_I_U_VALUE_MINUS_971 -5430226 // = -971 +#define IQ_I_U_VALUE_MINUS_970 -5424634 // = -970 +#define IQ_I_U_VALUE_MINUS_969 -5419041 // = -969 +#define IQ_I_U_VALUE_MINUS_968 -5413449 // = -968 +#define IQ_I_U_VALUE_MINUS_967 -5407856 // = -967 +#define IQ_I_U_VALUE_MINUS_966 -5402264 // = -966 +#define IQ_I_U_VALUE_MINUS_965 -5396672 // = -965 +#define IQ_I_U_VALUE_MINUS_964 -5391079 // = -964 +#define IQ_I_U_VALUE_MINUS_963 -5385487 // = -963 +#define IQ_I_U_VALUE_MINUS_962 -5379894 // = -962 +#define IQ_I_U_VALUE_MINUS_961 -5374302 // = -961 +#define IQ_I_U_VALUE_MINUS_960 -5368710 // = -960 +#define IQ_I_U_VALUE_MINUS_959 -5363117 // = -959 +#define IQ_I_U_VALUE_MINUS_958 -5357525 // = -958 +#define IQ_I_U_VALUE_MINUS_957 -5351932 // = -957 +#define IQ_I_U_VALUE_MINUS_956 -5346340 // = -956 +#define IQ_I_U_VALUE_MINUS_955 -5340748 // = -955 +#define IQ_I_U_VALUE_MINUS_954 -5335155 // = -954 +#define IQ_I_U_VALUE_MINUS_953 -5329563 // = -953 +#define IQ_I_U_VALUE_MINUS_952 -5323970 // = -952 +#define IQ_I_U_VALUE_MINUS_951 -5318378 // = -951 +#define IQ_I_U_VALUE_MINUS_950 -5312786 // = -950 +#define IQ_I_U_VALUE_MINUS_949 -5307193 // = -949 +#define IQ_I_U_VALUE_MINUS_948 -5301601 // = -948 +#define IQ_I_U_VALUE_MINUS_947 -5296008 // = -947 +#define IQ_I_U_VALUE_MINUS_946 -5290416 // = -946 +#define IQ_I_U_VALUE_MINUS_945 -5284824 // = -945 +#define IQ_I_U_VALUE_MINUS_944 -5279231 // = -944 +#define IQ_I_U_VALUE_MINUS_943 -5273639 // = -943 +#define IQ_I_U_VALUE_MINUS_942 -5268046 // = -942 +#define IQ_I_U_VALUE_MINUS_941 -5262454 // = -941 +#define IQ_I_U_VALUE_MINUS_940 -5256862 // = -940 +#define IQ_I_U_VALUE_MINUS_939 -5251269 // = -939 +#define IQ_I_U_VALUE_MINUS_938 -5245677 // = -938 +#define IQ_I_U_VALUE_MINUS_937 -5240084 // = -937 +#define IQ_I_U_VALUE_MINUS_936 -5234492 // = -936 +#define IQ_I_U_VALUE_MINUS_935 -5228899 // = -935 +#define IQ_I_U_VALUE_MINUS_934 -5223307 // = -934 +#define IQ_I_U_VALUE_MINUS_933 -5217715 // = -933 +#define IQ_I_U_VALUE_MINUS_932 -5212122 // = -932 +#define IQ_I_U_VALUE_MINUS_931 -5206530 // = -931 +#define IQ_I_U_VALUE_MINUS_930 -5200937 // = -930 +#define IQ_I_U_VALUE_MINUS_929 -5195345 // = -929 +#define IQ_I_U_VALUE_MINUS_928 -5189753 // = -928 +#define IQ_I_U_VALUE_MINUS_927 -5184160 // = -927 +#define IQ_I_U_VALUE_MINUS_926 -5178568 // = -926 +#define IQ_I_U_VALUE_MINUS_925 -5172975 // = -925 +#define IQ_I_U_VALUE_MINUS_924 -5167383 // = -924 +#define IQ_I_U_VALUE_MINUS_923 -5161791 // = -923 +#define IQ_I_U_VALUE_MINUS_922 -5156198 // = -922 +#define IQ_I_U_VALUE_MINUS_921 -5150606 // = -921 +#define IQ_I_U_VALUE_MINUS_920 -5145013 // = -920 +#define IQ_I_U_VALUE_MINUS_919 -5139421 // = -919 +#define IQ_I_U_VALUE_MINUS_918 -5133829 // = -918 +#define IQ_I_U_VALUE_MINUS_917 -5128236 // = -917 +#define IQ_I_U_VALUE_MINUS_916 -5122644 // = -916 +#define IQ_I_U_VALUE_MINUS_915 -5117051 // = -915 +#define IQ_I_U_VALUE_MINUS_914 -5111459 // = -914 +#define IQ_I_U_VALUE_MINUS_913 -5105867 // = -913 +#define IQ_I_U_VALUE_MINUS_912 -5100274 // = -912 +#define IQ_I_U_VALUE_MINUS_911 -5094682 // = -911 +#define IQ_I_U_VALUE_MINUS_910 -5089089 // = -910 +#define IQ_I_U_VALUE_MINUS_909 -5083497 // = -909 +#define IQ_I_U_VALUE_MINUS_908 -5077905 // = -908 +#define IQ_I_U_VALUE_MINUS_907 -5072312 // = -907 +#define IQ_I_U_VALUE_MINUS_906 -5066720 // = -906 +#define IQ_I_U_VALUE_MINUS_905 -5061127 // = -905 +#define IQ_I_U_VALUE_MINUS_904 -5055535 // = -904 +#define IQ_I_U_VALUE_MINUS_903 -5049943 // = -903 +#define IQ_I_U_VALUE_MINUS_902 -5044350 // = -902 +#define IQ_I_U_VALUE_MINUS_901 -5038758 // = -901 +#define IQ_I_U_VALUE_MINUS_900 -5033165 // = -900 +#define IQ_I_U_VALUE_MINUS_899 -5027573 // = -899 +#define IQ_I_U_VALUE_MINUS_898 -5021980 // = -898 +#define IQ_I_U_VALUE_MINUS_897 -5016388 // = -897 +#define IQ_I_U_VALUE_MINUS_896 -5010796 // = -896 +#define IQ_I_U_VALUE_MINUS_895 -5005203 // = -895 +#define IQ_I_U_VALUE_MINUS_894 -4999611 // = -894 +#define IQ_I_U_VALUE_MINUS_893 -4994018 // = -893 +#define IQ_I_U_VALUE_MINUS_892 -4988426 // = -892 +#define IQ_I_U_VALUE_MINUS_891 -4982834 // = -891 +#define IQ_I_U_VALUE_MINUS_890 -4977241 // = -890 +#define IQ_I_U_VALUE_MINUS_889 -4971649 // = -889 +#define IQ_I_U_VALUE_MINUS_888 -4966056 // = -888 +#define IQ_I_U_VALUE_MINUS_887 -4960464 // = -887 +#define IQ_I_U_VALUE_MINUS_886 -4954872 // = -886 +#define IQ_I_U_VALUE_MINUS_885 -4949279 // = -885 +#define IQ_I_U_VALUE_MINUS_884 -4943687 // = -884 +#define IQ_I_U_VALUE_MINUS_883 -4938094 // = -883 +#define IQ_I_U_VALUE_MINUS_882 -4932502 // = -882 +#define IQ_I_U_VALUE_MINUS_881 -4926910 // = -881 +#define IQ_I_U_VALUE_MINUS_880 -4921317 // = -880 +#define IQ_I_U_VALUE_MINUS_879 -4915725 // = -879 +#define IQ_I_U_VALUE_MINUS_878 -4910132 // = -878 +#define IQ_I_U_VALUE_MINUS_877 -4904540 // = -877 +#define IQ_I_U_VALUE_MINUS_876 -4898948 // = -876 +#define IQ_I_U_VALUE_MINUS_875 -4893355 // = -875 +#define IQ_I_U_VALUE_MINUS_874 -4887763 // = -874 +#define IQ_I_U_VALUE_MINUS_873 -4882170 // = -873 +#define IQ_I_U_VALUE_MINUS_872 -4876578 // = -872 +#define IQ_I_U_VALUE_MINUS_871 -4870986 // = -871 +#define IQ_I_U_VALUE_MINUS_870 -4865393 // = -870 +#define IQ_I_U_VALUE_MINUS_869 -4859801 // = -869 +#define IQ_I_U_VALUE_MINUS_868 -4854208 // = -868 +#define IQ_I_U_VALUE_MINUS_867 -4848616 // = -867 +#define IQ_I_U_VALUE_MINUS_866 -4843024 // = -866 +#define IQ_I_U_VALUE_MINUS_865 -4837431 // = -865 +#define IQ_I_U_VALUE_MINUS_864 -4831839 // = -864 +#define IQ_I_U_VALUE_MINUS_863 -4826246 // = -863 +#define IQ_I_U_VALUE_MINUS_862 -4820654 // = -862 +#define IQ_I_U_VALUE_MINUS_861 -4815061 // = -861 +#define IQ_I_U_VALUE_MINUS_860 -4809469 // = -860 +#define IQ_I_U_VALUE_MINUS_859 -4803877 // = -859 +#define IQ_I_U_VALUE_MINUS_858 -4798284 // = -858 +#define IQ_I_U_VALUE_MINUS_857 -4792692 // = -857 +#define IQ_I_U_VALUE_MINUS_856 -4787099 // = -856 +#define IQ_I_U_VALUE_MINUS_855 -4781507 // = -855 +#define IQ_I_U_VALUE_MINUS_854 -4775915 // = -854 +#define IQ_I_U_VALUE_MINUS_853 -4770322 // = -853 +#define IQ_I_U_VALUE_MINUS_852 -4764730 // = -852 +#define IQ_I_U_VALUE_MINUS_851 -4759137 // = -851 +#define IQ_I_U_VALUE_MINUS_850 -4753545 // = -850 +#define IQ_I_U_VALUE_MINUS_849 -4747953 // = -849 +#define IQ_I_U_VALUE_MINUS_848 -4742360 // = -848 +#define IQ_I_U_VALUE_MINUS_847 -4736768 // = -847 +#define IQ_I_U_VALUE_MINUS_846 -4731175 // = -846 +#define IQ_I_U_VALUE_MINUS_845 -4725583 // = -845 +#define IQ_I_U_VALUE_MINUS_844 -4719991 // = -844 +#define IQ_I_U_VALUE_MINUS_843 -4714398 // = -843 +#define IQ_I_U_VALUE_MINUS_842 -4708806 // = -842 +#define IQ_I_U_VALUE_MINUS_841 -4703213 // = -841 +#define IQ_I_U_VALUE_MINUS_840 -4697621 // = -840 +#define IQ_I_U_VALUE_MINUS_839 -4692029 // = -839 +#define IQ_I_U_VALUE_MINUS_838 -4686436 // = -838 +#define IQ_I_U_VALUE_MINUS_837 -4680844 // = -837 +#define IQ_I_U_VALUE_MINUS_836 -4675251 // = -836 +#define IQ_I_U_VALUE_MINUS_835 -4669659 // = -835 +#define IQ_I_U_VALUE_MINUS_834 -4664067 // = -834 +#define IQ_I_U_VALUE_MINUS_833 -4658474 // = -833 +#define IQ_I_U_VALUE_MINUS_832 -4652882 // = -832 +#define IQ_I_U_VALUE_MINUS_831 -4647289 // = -831 +#define IQ_I_U_VALUE_MINUS_830 -4641697 // = -830 +#define IQ_I_U_VALUE_MINUS_829 -4636105 // = -829 +#define IQ_I_U_VALUE_MINUS_828 -4630512 // = -828 +#define IQ_I_U_VALUE_MINUS_827 -4624920 // = -827 +#define IQ_I_U_VALUE_MINUS_826 -4619327 // = -826 +#define IQ_I_U_VALUE_MINUS_825 -4613735 // = -825 +#define IQ_I_U_VALUE_MINUS_824 -4608142 // = -824 +#define IQ_I_U_VALUE_MINUS_823 -4602550 // = -823 +#define IQ_I_U_VALUE_MINUS_822 -4596958 // = -822 +#define IQ_I_U_VALUE_MINUS_821 -4591365 // = -821 +#define IQ_I_U_VALUE_MINUS_820 -4585773 // = -820 +#define IQ_I_U_VALUE_MINUS_819 -4580180 // = -819 +#define IQ_I_U_VALUE_MINUS_818 -4574588 // = -818 +#define IQ_I_U_VALUE_MINUS_817 -4568996 // = -817 +#define IQ_I_U_VALUE_MINUS_816 -4563403 // = -816 +#define IQ_I_U_VALUE_MINUS_815 -4557811 // = -815 +#define IQ_I_U_VALUE_MINUS_814 -4552218 // = -814 +#define IQ_I_U_VALUE_MINUS_813 -4546626 // = -813 +#define IQ_I_U_VALUE_MINUS_812 -4541034 // = -812 +#define IQ_I_U_VALUE_MINUS_811 -4535441 // = -811 +#define IQ_I_U_VALUE_MINUS_810 -4529849 // = -810 +#define IQ_I_U_VALUE_MINUS_809 -4524256 // = -809 +#define IQ_I_U_VALUE_MINUS_808 -4518664 // = -808 +#define IQ_I_U_VALUE_MINUS_807 -4513072 // = -807 +#define IQ_I_U_VALUE_MINUS_806 -4507479 // = -806 +#define IQ_I_U_VALUE_MINUS_805 -4501887 // = -805 +#define IQ_I_U_VALUE_MINUS_804 -4496294 // = -804 +#define IQ_I_U_VALUE_MINUS_803 -4490702 // = -803 +#define IQ_I_U_VALUE_MINUS_802 -4485110 // = -802 +#define IQ_I_U_VALUE_MINUS_801 -4479517 // = -801 +#define IQ_I_U_VALUE_MINUS_800 -4473925 // = -800 +#define IQ_I_U_VALUE_MINUS_799 -4468332 // = -799 +#define IQ_I_U_VALUE_MINUS_798 -4462740 // = -798 +#define IQ_I_U_VALUE_MINUS_797 -4457148 // = -797 +#define IQ_I_U_VALUE_MINUS_796 -4451555 // = -796 +#define IQ_I_U_VALUE_MINUS_795 -4445963 // = -795 +#define IQ_I_U_VALUE_MINUS_794 -4440370 // = -794 +#define IQ_I_U_VALUE_MINUS_793 -4434778 // = -793 +#define IQ_I_U_VALUE_MINUS_792 -4429186 // = -792 +#define IQ_I_U_VALUE_MINUS_791 -4423593 // = -791 +#define IQ_I_U_VALUE_MINUS_790 -4418001 // = -790 +#define IQ_I_U_VALUE_MINUS_789 -4412408 // = -789 +#define IQ_I_U_VALUE_MINUS_788 -4406816 // = -788 +#define IQ_I_U_VALUE_MINUS_787 -4401223 // = -787 +#define IQ_I_U_VALUE_MINUS_786 -4395631 // = -786 +#define IQ_I_U_VALUE_MINUS_785 -4390039 // = -785 +#define IQ_I_U_VALUE_MINUS_784 -4384446 // = -784 +#define IQ_I_U_VALUE_MINUS_783 -4378854 // = -783 +#define IQ_I_U_VALUE_MINUS_782 -4373261 // = -782 +#define IQ_I_U_VALUE_MINUS_781 -4367669 // = -781 +#define IQ_I_U_VALUE_MINUS_780 -4362077 // = -780 +#define IQ_I_U_VALUE_MINUS_779 -4356484 // = -779 +#define IQ_I_U_VALUE_MINUS_778 -4350892 // = -778 +#define IQ_I_U_VALUE_MINUS_777 -4345299 // = -777 +#define IQ_I_U_VALUE_MINUS_776 -4339707 // = -776 +#define IQ_I_U_VALUE_MINUS_775 -4334115 // = -775 +#define IQ_I_U_VALUE_MINUS_774 -4328522 // = -774 +#define IQ_I_U_VALUE_MINUS_773 -4322930 // = -773 +#define IQ_I_U_VALUE_MINUS_772 -4317337 // = -772 +#define IQ_I_U_VALUE_MINUS_771 -4311745 // = -771 +#define IQ_I_U_VALUE_MINUS_770 -4306153 // = -770 +#define IQ_I_U_VALUE_MINUS_769 -4300560 // = -769 +#define IQ_I_U_VALUE_MINUS_768 -4294968 // = -768 +#define IQ_I_U_VALUE_MINUS_767 -4289375 // = -767 +#define IQ_I_U_VALUE_MINUS_766 -4283783 // = -766 +#define IQ_I_U_VALUE_MINUS_765 -4278191 // = -765 +#define IQ_I_U_VALUE_MINUS_764 -4272598 // = -764 +#define IQ_I_U_VALUE_MINUS_763 -4267006 // = -763 +#define IQ_I_U_VALUE_MINUS_762 -4261413 // = -762 +#define IQ_I_U_VALUE_MINUS_761 -4255821 // = -761 +#define IQ_I_U_VALUE_MINUS_760 -4250229 // = -760 +#define IQ_I_U_VALUE_MINUS_759 -4244636 // = -759 +#define IQ_I_U_VALUE_MINUS_758 -4239044 // = -758 +#define IQ_I_U_VALUE_MINUS_757 -4233451 // = -757 +#define IQ_I_U_VALUE_MINUS_756 -4227859 // = -756 +#define IQ_I_U_VALUE_MINUS_755 -4222267 // = -755 +#define IQ_I_U_VALUE_MINUS_754 -4216674 // = -754 +#define IQ_I_U_VALUE_MINUS_753 -4211082 // = -753 +#define IQ_I_U_VALUE_MINUS_752 -4205489 // = -752 +#define IQ_I_U_VALUE_MINUS_751 -4199897 // = -751 +#define IQ_I_U_VALUE_MINUS_750 -4194304 // = -750 +#define IQ_I_U_VALUE_MINUS_749 -4188712 // = -749 +#define IQ_I_U_VALUE_MINUS_748 -4183120 // = -748 +#define IQ_I_U_VALUE_MINUS_747 -4177527 // = -747 +#define IQ_I_U_VALUE_MINUS_746 -4171935 // = -746 +#define IQ_I_U_VALUE_MINUS_745 -4166342 // = -745 +#define IQ_I_U_VALUE_MINUS_744 -4160750 // = -744 +#define IQ_I_U_VALUE_MINUS_743 -4155158 // = -743 +#define IQ_I_U_VALUE_MINUS_742 -4149565 // = -742 +#define IQ_I_U_VALUE_MINUS_741 -4143973 // = -741 +#define IQ_I_U_VALUE_MINUS_740 -4138380 // = -740 +#define IQ_I_U_VALUE_MINUS_739 -4132788 // = -739 +#define IQ_I_U_VALUE_MINUS_738 -4127196 // = -738 +#define IQ_I_U_VALUE_MINUS_737 -4121603 // = -737 +#define IQ_I_U_VALUE_MINUS_736 -4116011 // = -736 +#define IQ_I_U_VALUE_MINUS_735 -4110418 // = -735 +#define IQ_I_U_VALUE_MINUS_734 -4104826 // = -734 +#define IQ_I_U_VALUE_MINUS_733 -4099234 // = -733 +#define IQ_I_U_VALUE_MINUS_732 -4093641 // = -732 +#define IQ_I_U_VALUE_MINUS_731 -4088049 // = -731 +#define IQ_I_U_VALUE_MINUS_730 -4082456 // = -730 +#define IQ_I_U_VALUE_MINUS_729 -4076864 // = -729 +#define IQ_I_U_VALUE_MINUS_728 -4071272 // = -728 +#define IQ_I_U_VALUE_MINUS_727 -4065679 // = -727 +#define IQ_I_U_VALUE_MINUS_726 -4060087 // = -726 +#define IQ_I_U_VALUE_MINUS_725 -4054494 // = -725 +#define IQ_I_U_VALUE_MINUS_724 -4048902 // = -724 +#define IQ_I_U_VALUE_MINUS_723 -4043310 // = -723 +#define IQ_I_U_VALUE_MINUS_722 -4037717 // = -722 +#define IQ_I_U_VALUE_MINUS_721 -4032125 // = -721 +#define IQ_I_U_VALUE_MINUS_720 -4026532 // = -720 +#define IQ_I_U_VALUE_MINUS_719 -4020940 // = -719 +#define IQ_I_U_VALUE_MINUS_718 -4015348 // = -718 +#define IQ_I_U_VALUE_MINUS_717 -4009755 // = -717 +#define IQ_I_U_VALUE_MINUS_716 -4004163 // = -716 +#define IQ_I_U_VALUE_MINUS_715 -3998570 // = -715 +#define IQ_I_U_VALUE_MINUS_714 -3992978 // = -714 +#define IQ_I_U_VALUE_MINUS_713 -3987386 // = -713 +#define IQ_I_U_VALUE_MINUS_712 -3981793 // = -712 +#define IQ_I_U_VALUE_MINUS_711 -3976201 // = -711 +#define IQ_I_U_VALUE_MINUS_710 -3970608 // = -710 +#define IQ_I_U_VALUE_MINUS_709 -3965016 // = -709 +#define IQ_I_U_VALUE_MINUS_708 -3959423 // = -708 +#define IQ_I_U_VALUE_MINUS_707 -3953831 // = -707 +#define IQ_I_U_VALUE_MINUS_706 -3948239 // = -706 +#define IQ_I_U_VALUE_MINUS_705 -3942646 // = -705 +#define IQ_I_U_VALUE_MINUS_704 -3937054 // = -704 +#define IQ_I_U_VALUE_MINUS_703 -3931461 // = -703 +#define IQ_I_U_VALUE_MINUS_702 -3925869 // = -702 +#define IQ_I_U_VALUE_MINUS_701 -3920277 // = -701 +#define IQ_I_U_VALUE_MINUS_700 -3914684 // = -700 +#define IQ_I_U_VALUE_MINUS_699 -3909092 // = -699 +#define IQ_I_U_VALUE_MINUS_698 -3903499 // = -698 +#define IQ_I_U_VALUE_MINUS_697 -3897907 // = -697 +#define IQ_I_U_VALUE_MINUS_696 -3892315 // = -696 +#define IQ_I_U_VALUE_MINUS_695 -3886722 // = -695 +#define IQ_I_U_VALUE_MINUS_694 -3881130 // = -694 +#define IQ_I_U_VALUE_MINUS_693 -3875537 // = -693 +#define IQ_I_U_VALUE_MINUS_692 -3869945 // = -692 +#define IQ_I_U_VALUE_MINUS_691 -3864353 // = -691 +#define IQ_I_U_VALUE_MINUS_690 -3858760 // = -690 +#define IQ_I_U_VALUE_MINUS_689 -3853168 // = -689 +#define IQ_I_U_VALUE_MINUS_688 -3847575 // = -688 +#define IQ_I_U_VALUE_MINUS_687 -3841983 // = -687 +#define IQ_I_U_VALUE_MINUS_686 -3836391 // = -686 +#define IQ_I_U_VALUE_MINUS_685 -3830798 // = -685 +#define IQ_I_U_VALUE_MINUS_684 -3825206 // = -684 +#define IQ_I_U_VALUE_MINUS_683 -3819613 // = -683 +#define IQ_I_U_VALUE_MINUS_682 -3814021 // = -682 +#define IQ_I_U_VALUE_MINUS_681 -3808429 // = -681 +#define IQ_I_U_VALUE_MINUS_680 -3802836 // = -680 +#define IQ_I_U_VALUE_MINUS_679 -3797244 // = -679 +#define IQ_I_U_VALUE_MINUS_678 -3791651 // = -678 +#define IQ_I_U_VALUE_MINUS_677 -3786059 // = -677 +#define IQ_I_U_VALUE_MINUS_676 -3780467 // = -676 +#define IQ_I_U_VALUE_MINUS_675 -3774874 // = -675 +#define IQ_I_U_VALUE_MINUS_674 -3769282 // = -674 +#define IQ_I_U_VALUE_MINUS_673 -3763689 // = -673 +#define IQ_I_U_VALUE_MINUS_672 -3758097 // = -672 +#define IQ_I_U_VALUE_MINUS_671 -3752504 // = -671 +#define IQ_I_U_VALUE_MINUS_670 -3746912 // = -670 +#define IQ_I_U_VALUE_MINUS_669 -3741320 // = -669 +#define IQ_I_U_VALUE_MINUS_668 -3735727 // = -668 +#define IQ_I_U_VALUE_MINUS_667 -3730135 // = -667 +#define IQ_I_U_VALUE_MINUS_666 -3724542 // = -666 +#define IQ_I_U_VALUE_MINUS_665 -3718950 // = -665 +#define IQ_I_U_VALUE_MINUS_664 -3713358 // = -664 +#define IQ_I_U_VALUE_MINUS_663 -3707765 // = -663 +#define IQ_I_U_VALUE_MINUS_662 -3702173 // = -662 +#define IQ_I_U_VALUE_MINUS_661 -3696580 // = -661 +#define IQ_I_U_VALUE_MINUS_660 -3690988 // = -660 +#define IQ_I_U_VALUE_MINUS_659 -3685396 // = -659 +#define IQ_I_U_VALUE_MINUS_658 -3679803 // = -658 +#define IQ_I_U_VALUE_MINUS_657 -3674211 // = -657 +#define IQ_I_U_VALUE_MINUS_656 -3668618 // = -656 +#define IQ_I_U_VALUE_MINUS_655 -3663026 // = -655 +#define IQ_I_U_VALUE_MINUS_654 -3657434 // = -654 +#define IQ_I_U_VALUE_MINUS_653 -3651841 // = -653 +#define IQ_I_U_VALUE_MINUS_652 -3646249 // = -652 +#define IQ_I_U_VALUE_MINUS_651 -3640656 // = -651 +#define IQ_I_U_VALUE_MINUS_650 -3635064 // = -650 +#define IQ_I_U_VALUE_MINUS_649 -3629472 // = -649 +#define IQ_I_U_VALUE_MINUS_648 -3623879 // = -648 +#define IQ_I_U_VALUE_MINUS_647 -3618287 // = -647 +#define IQ_I_U_VALUE_MINUS_646 -3612694 // = -646 +#define IQ_I_U_VALUE_MINUS_645 -3607102 // = -645 +#define IQ_I_U_VALUE_MINUS_644 -3601510 // = -644 +#define IQ_I_U_VALUE_MINUS_643 -3595917 // = -643 +#define IQ_I_U_VALUE_MINUS_642 -3590325 // = -642 +#define IQ_I_U_VALUE_MINUS_641 -3584732 // = -641 +#define IQ_I_U_VALUE_MINUS_640 -3579140 // = -640 +#define IQ_I_U_VALUE_MINUS_639 -3573548 // = -639 +#define IQ_I_U_VALUE_MINUS_638 -3567955 // = -638 +#define IQ_I_U_VALUE_MINUS_637 -3562363 // = -637 +#define IQ_I_U_VALUE_MINUS_636 -3556770 // = -636 +#define IQ_I_U_VALUE_MINUS_635 -3551178 // = -635 +#define IQ_I_U_VALUE_MINUS_634 -3545585 // = -634 +#define IQ_I_U_VALUE_MINUS_633 -3539993 // = -633 +#define IQ_I_U_VALUE_MINUS_632 -3534401 // = -632 +#define IQ_I_U_VALUE_MINUS_631 -3528808 // = -631 +#define IQ_I_U_VALUE_MINUS_630 -3523216 // = -630 +#define IQ_I_U_VALUE_MINUS_629 -3517623 // = -629 +#define IQ_I_U_VALUE_MINUS_628 -3512031 // = -628 +#define IQ_I_U_VALUE_MINUS_627 -3506439 // = -627 +#define IQ_I_U_VALUE_MINUS_626 -3500846 // = -626 +#define IQ_I_U_VALUE_MINUS_625 -3495254 // = -625 +#define IQ_I_U_VALUE_MINUS_624 -3489661 // = -624 +#define IQ_I_U_VALUE_MINUS_623 -3484069 // = -623 +#define IQ_I_U_VALUE_MINUS_622 -3478477 // = -622 +#define IQ_I_U_VALUE_MINUS_621 -3472884 // = -621 +#define IQ_I_U_VALUE_MINUS_620 -3467292 // = -620 +#define IQ_I_U_VALUE_MINUS_619 -3461699 // = -619 +#define IQ_I_U_VALUE_MINUS_618 -3456107 // = -618 +#define IQ_I_U_VALUE_MINUS_617 -3450515 // = -617 +#define IQ_I_U_VALUE_MINUS_616 -3444922 // = -616 +#define IQ_I_U_VALUE_MINUS_615 -3439330 // = -615 +#define IQ_I_U_VALUE_MINUS_614 -3433737 // = -614 +#define IQ_I_U_VALUE_MINUS_613 -3428145 // = -613 +#define IQ_I_U_VALUE_MINUS_612 -3422553 // = -612 +#define IQ_I_U_VALUE_MINUS_611 -3416960 // = -611 +#define IQ_I_U_VALUE_MINUS_610 -3411368 // = -610 +#define IQ_I_U_VALUE_MINUS_609 -3405775 // = -609 +#define IQ_I_U_VALUE_MINUS_608 -3400183 // = -608 +#define IQ_I_U_VALUE_MINUS_607 -3394591 // = -607 +#define IQ_I_U_VALUE_MINUS_606 -3388998 // = -606 +#define IQ_I_U_VALUE_MINUS_605 -3383406 // = -605 +#define IQ_I_U_VALUE_MINUS_604 -3377813 // = -604 +#define IQ_I_U_VALUE_MINUS_603 -3372221 // = -603 +#define IQ_I_U_VALUE_MINUS_602 -3366629 // = -602 +#define IQ_I_U_VALUE_MINUS_601 -3361036 // = -601 +#define IQ_I_U_VALUE_MINUS_600 -3355444 // = -600 +#define IQ_I_U_VALUE_MINUS_599 -3349851 // = -599 +#define IQ_I_U_VALUE_MINUS_598 -3344259 // = -598 +#define IQ_I_U_VALUE_MINUS_597 -3338666 // = -597 +#define IQ_I_U_VALUE_MINUS_596 -3333074 // = -596 +#define IQ_I_U_VALUE_MINUS_595 -3327482 // = -595 +#define IQ_I_U_VALUE_MINUS_594 -3321889 // = -594 +#define IQ_I_U_VALUE_MINUS_593 -3316297 // = -593 +#define IQ_I_U_VALUE_MINUS_592 -3310704 // = -592 +#define IQ_I_U_VALUE_MINUS_591 -3305112 // = -591 +#define IQ_I_U_VALUE_MINUS_590 -3299520 // = -590 +#define IQ_I_U_VALUE_MINUS_589 -3293927 // = -589 +#define IQ_I_U_VALUE_MINUS_588 -3288335 // = -588 +#define IQ_I_U_VALUE_MINUS_587 -3282742 // = -587 +#define IQ_I_U_VALUE_MINUS_586 -3277150 // = -586 +#define IQ_I_U_VALUE_MINUS_585 -3271558 // = -585 +#define IQ_I_U_VALUE_MINUS_584 -3265965 // = -584 +#define IQ_I_U_VALUE_MINUS_583 -3260373 // = -583 +#define IQ_I_U_VALUE_MINUS_582 -3254780 // = -582 +#define IQ_I_U_VALUE_MINUS_581 -3249188 // = -581 +#define IQ_I_U_VALUE_MINUS_580 -3243596 // = -580 +#define IQ_I_U_VALUE_MINUS_579 -3238003 // = -579 +#define IQ_I_U_VALUE_MINUS_578 -3232411 // = -578 +#define IQ_I_U_VALUE_MINUS_577 -3226818 // = -577 +#define IQ_I_U_VALUE_MINUS_576 -3221226 // = -576 +#define IQ_I_U_VALUE_MINUS_575 -3215634 // = -575 +#define IQ_I_U_VALUE_MINUS_574 -3210041 // = -574 +#define IQ_I_U_VALUE_MINUS_573 -3204449 // = -573 +#define IQ_I_U_VALUE_MINUS_572 -3198856 // = -572 +#define IQ_I_U_VALUE_MINUS_571 -3193264 // = -571 +#define IQ_I_U_VALUE_MINUS_570 -3187672 // = -570 +#define IQ_I_U_VALUE_MINUS_569 -3182079 // = -569 +#define IQ_I_U_VALUE_MINUS_568 -3176487 // = -568 +#define IQ_I_U_VALUE_MINUS_567 -3170894 // = -567 +#define IQ_I_U_VALUE_MINUS_566 -3165302 // = -566 +#define IQ_I_U_VALUE_MINUS_565 -3159710 // = -565 +#define IQ_I_U_VALUE_MINUS_564 -3154117 // = -564 +#define IQ_I_U_VALUE_MINUS_563 -3148525 // = -563 +#define IQ_I_U_VALUE_MINUS_562 -3142932 // = -562 +#define IQ_I_U_VALUE_MINUS_561 -3137340 // = -561 +#define IQ_I_U_VALUE_MINUS_560 -3131747 // = -560 +#define IQ_I_U_VALUE_MINUS_559 -3126155 // = -559 +#define IQ_I_U_VALUE_MINUS_558 -3120563 // = -558 +#define IQ_I_U_VALUE_MINUS_557 -3114970 // = -557 +#define IQ_I_U_VALUE_MINUS_556 -3109378 // = -556 +#define IQ_I_U_VALUE_MINUS_555 -3103785 // = -555 +#define IQ_I_U_VALUE_MINUS_554 -3098193 // = -554 +#define IQ_I_U_VALUE_MINUS_553 -3092601 // = -553 +#define IQ_I_U_VALUE_MINUS_552 -3087008 // = -552 +#define IQ_I_U_VALUE_MINUS_551 -3081416 // = -551 +#define IQ_I_U_VALUE_MINUS_550 -3075823 // = -550 +#define IQ_I_U_VALUE_MINUS_549 -3070231 // = -549 +#define IQ_I_U_VALUE_MINUS_548 -3064639 // = -548 +#define IQ_I_U_VALUE_MINUS_547 -3059046 // = -547 +#define IQ_I_U_VALUE_MINUS_546 -3053454 // = -546 +#define IQ_I_U_VALUE_MINUS_545 -3047861 // = -545 +#define IQ_I_U_VALUE_MINUS_544 -3042269 // = -544 +#define IQ_I_U_VALUE_MINUS_543 -3036677 // = -543 +#define IQ_I_U_VALUE_MINUS_542 -3031084 // = -542 +#define IQ_I_U_VALUE_MINUS_541 -3025492 // = -541 +#define IQ_I_U_VALUE_MINUS_540 -3019899 // = -540 +#define IQ_I_U_VALUE_MINUS_539 -3014307 // = -539 +#define IQ_I_U_VALUE_MINUS_538 -3008715 // = -538 +#define IQ_I_U_VALUE_MINUS_537 -3003122 // = -537 +#define IQ_I_U_VALUE_MINUS_536 -2997530 // = -536 +#define IQ_I_U_VALUE_MINUS_535 -2991937 // = -535 +#define IQ_I_U_VALUE_MINUS_534 -2986345 // = -534 +#define IQ_I_U_VALUE_MINUS_533 -2980753 // = -533 +#define IQ_I_U_VALUE_MINUS_532 -2975160 // = -532 +#define IQ_I_U_VALUE_MINUS_531 -2969568 // = -531 +#define IQ_I_U_VALUE_MINUS_530 -2963975 // = -530 +#define IQ_I_U_VALUE_MINUS_529 -2958383 // = -529 +#define IQ_I_U_VALUE_MINUS_528 -2952791 // = -528 +#define IQ_I_U_VALUE_MINUS_527 -2947198 // = -527 +#define IQ_I_U_VALUE_MINUS_526 -2941606 // = -526 +#define IQ_I_U_VALUE_MINUS_525 -2936013 // = -525 +#define IQ_I_U_VALUE_MINUS_524 -2930421 // = -524 +#define IQ_I_U_VALUE_MINUS_523 -2924828 // = -523 +#define IQ_I_U_VALUE_MINUS_522 -2919236 // = -522 +#define IQ_I_U_VALUE_MINUS_521 -2913644 // = -521 +#define IQ_I_U_VALUE_MINUS_520 -2908051 // = -520 +#define IQ_I_U_VALUE_MINUS_519 -2902459 // = -519 +#define IQ_I_U_VALUE_MINUS_518 -2896866 // = -518 +#define IQ_I_U_VALUE_MINUS_517 -2891274 // = -517 +#define IQ_I_U_VALUE_MINUS_516 -2885682 // = -516 +#define IQ_I_U_VALUE_MINUS_515 -2880089 // = -515 +#define IQ_I_U_VALUE_MINUS_514 -2874497 // = -514 +#define IQ_I_U_VALUE_MINUS_513 -2868904 // = -513 +#define IQ_I_U_VALUE_MINUS_512 -2863312 // = -512 +#define IQ_I_U_VALUE_MINUS_511 -2857720 // = -511 +#define IQ_I_U_VALUE_MINUS_510 -2852127 // = -510 +#define IQ_I_U_VALUE_MINUS_509 -2846535 // = -509 +#define IQ_I_U_VALUE_MINUS_508 -2840942 // = -508 +#define IQ_I_U_VALUE_MINUS_507 -2835350 // = -507 +#define IQ_I_U_VALUE_MINUS_506 -2829758 // = -506 +#define IQ_I_U_VALUE_MINUS_505 -2824165 // = -505 +#define IQ_I_U_VALUE_MINUS_504 -2818573 // = -504 +#define IQ_I_U_VALUE_MINUS_503 -2812980 // = -503 +#define IQ_I_U_VALUE_MINUS_502 -2807388 // = -502 +#define IQ_I_U_VALUE_MINUS_501 -2801796 // = -501 +#define IQ_I_U_VALUE_MINUS_500 -2796203 // = -500 +#define IQ_I_U_VALUE_MINUS_499 -2790611 // = -499 +#define IQ_I_U_VALUE_MINUS_498 -2785018 // = -498 +#define IQ_I_U_VALUE_MINUS_497 -2779426 // = -497 +#define IQ_I_U_VALUE_MINUS_496 -2773834 // = -496 +#define IQ_I_U_VALUE_MINUS_495 -2768241 // = -495 +#define IQ_I_U_VALUE_MINUS_494 -2762649 // = -494 +#define IQ_I_U_VALUE_MINUS_493 -2757056 // = -493 +#define IQ_I_U_VALUE_MINUS_492 -2751464 // = -492 +#define IQ_I_U_VALUE_MINUS_491 -2745872 // = -491 +#define IQ_I_U_VALUE_MINUS_490 -2740279 // = -490 +#define IQ_I_U_VALUE_MINUS_489 -2734687 // = -489 +#define IQ_I_U_VALUE_MINUS_488 -2729094 // = -488 +#define IQ_I_U_VALUE_MINUS_487 -2723502 // = -487 +#define IQ_I_U_VALUE_MINUS_486 -2717909 // = -486 +#define IQ_I_U_VALUE_MINUS_485 -2712317 // = -485 +#define IQ_I_U_VALUE_MINUS_484 -2706725 // = -484 +#define IQ_I_U_VALUE_MINUS_483 -2701132 // = -483 +#define IQ_I_U_VALUE_MINUS_482 -2695540 // = -482 +#define IQ_I_U_VALUE_MINUS_481 -2689947 // = -481 +#define IQ_I_U_VALUE_MINUS_480 -2684355 // = -480 +#define IQ_I_U_VALUE_MINUS_479 -2678763 // = -479 +#define IQ_I_U_VALUE_MINUS_478 -2673170 // = -478 +#define IQ_I_U_VALUE_MINUS_477 -2667578 // = -477 +#define IQ_I_U_VALUE_MINUS_476 -2661985 // = -476 +#define IQ_I_U_VALUE_MINUS_475 -2656393 // = -475 +#define IQ_I_U_VALUE_MINUS_474 -2650801 // = -474 +#define IQ_I_U_VALUE_MINUS_473 -2645208 // = -473 +#define IQ_I_U_VALUE_MINUS_472 -2639616 // = -472 +#define IQ_I_U_VALUE_MINUS_471 -2634023 // = -471 +#define IQ_I_U_VALUE_MINUS_470 -2628431 // = -470 +#define IQ_I_U_VALUE_MINUS_469 -2622839 // = -469 +#define IQ_I_U_VALUE_MINUS_468 -2617246 // = -468 +#define IQ_I_U_VALUE_MINUS_467 -2611654 // = -467 +#define IQ_I_U_VALUE_MINUS_466 -2606061 // = -466 +#define IQ_I_U_VALUE_MINUS_465 -2600469 // = -465 +#define IQ_I_U_VALUE_MINUS_464 -2594877 // = -464 +#define IQ_I_U_VALUE_MINUS_463 -2589284 // = -463 +#define IQ_I_U_VALUE_MINUS_462 -2583692 // = -462 +#define IQ_I_U_VALUE_MINUS_461 -2578099 // = -461 +#define IQ_I_U_VALUE_MINUS_460 -2572507 // = -460 +#define IQ_I_U_VALUE_MINUS_459 -2566915 // = -459 +#define IQ_I_U_VALUE_MINUS_458 -2561322 // = -458 +#define IQ_I_U_VALUE_MINUS_457 -2555730 // = -457 +#define IQ_I_U_VALUE_MINUS_456 -2550137 // = -456 +#define IQ_I_U_VALUE_MINUS_455 -2544545 // = -455 +#define IQ_I_U_VALUE_MINUS_454 -2538953 // = -454 +#define IQ_I_U_VALUE_MINUS_453 -2533360 // = -453 +#define IQ_I_U_VALUE_MINUS_452 -2527768 // = -452 +#define IQ_I_U_VALUE_MINUS_451 -2522175 // = -451 +#define IQ_I_U_VALUE_MINUS_450 -2516583 // = -450 +#define IQ_I_U_VALUE_MINUS_449 -2510990 // = -449 +#define IQ_I_U_VALUE_MINUS_448 -2505398 // = -448 +#define IQ_I_U_VALUE_MINUS_447 -2499806 // = -447 +#define IQ_I_U_VALUE_MINUS_446 -2494213 // = -446 +#define IQ_I_U_VALUE_MINUS_445 -2488621 // = -445 +#define IQ_I_U_VALUE_MINUS_444 -2483028 // = -444 +#define IQ_I_U_VALUE_MINUS_443 -2477436 // = -443 +#define IQ_I_U_VALUE_MINUS_442 -2471844 // = -442 +#define IQ_I_U_VALUE_MINUS_441 -2466251 // = -441 +#define IQ_I_U_VALUE_MINUS_440 -2460659 // = -440 +#define IQ_I_U_VALUE_MINUS_439 -2455066 // = -439 +#define IQ_I_U_VALUE_MINUS_438 -2449474 // = -438 +#define IQ_I_U_VALUE_MINUS_437 -2443882 // = -437 +#define IQ_I_U_VALUE_MINUS_436 -2438289 // = -436 +#define IQ_I_U_VALUE_MINUS_435 -2432697 // = -435 +#define IQ_I_U_VALUE_MINUS_434 -2427104 // = -434 +#define IQ_I_U_VALUE_MINUS_433 -2421512 // = -433 +#define IQ_I_U_VALUE_MINUS_432 -2415920 // = -432 +#define IQ_I_U_VALUE_MINUS_431 -2410327 // = -431 +#define IQ_I_U_VALUE_MINUS_430 -2404735 // = -430 +#define IQ_I_U_VALUE_MINUS_429 -2399142 // = -429 +#define IQ_I_U_VALUE_MINUS_428 -2393550 // = -428 +#define IQ_I_U_VALUE_MINUS_427 -2387958 // = -427 +#define IQ_I_U_VALUE_MINUS_426 -2382365 // = -426 +#define IQ_I_U_VALUE_MINUS_425 -2376773 // = -425 +#define IQ_I_U_VALUE_MINUS_424 -2371180 // = -424 +#define IQ_I_U_VALUE_MINUS_423 -2365588 // = -423 +#define IQ_I_U_VALUE_MINUS_422 -2359996 // = -422 +#define IQ_I_U_VALUE_MINUS_421 -2354403 // = -421 +#define IQ_I_U_VALUE_MINUS_420 -2348811 // = -420 +#define IQ_I_U_VALUE_MINUS_419 -2343218 // = -419 +#define IQ_I_U_VALUE_MINUS_418 -2337626 // = -418 +#define IQ_I_U_VALUE_MINUS_417 -2332034 // = -417 +#define IQ_I_U_VALUE_MINUS_416 -2326441 // = -416 +#define IQ_I_U_VALUE_MINUS_415 -2320849 // = -415 +#define IQ_I_U_VALUE_MINUS_414 -2315256 // = -414 +#define IQ_I_U_VALUE_MINUS_413 -2309664 // = -413 +#define IQ_I_U_VALUE_MINUS_412 -2304071 // = -412 +#define IQ_I_U_VALUE_MINUS_411 -2298479 // = -411 +#define IQ_I_U_VALUE_MINUS_410 -2292887 // = -410 +#define IQ_I_U_VALUE_MINUS_409 -2287294 // = -409 +#define IQ_I_U_VALUE_MINUS_408 -2281702 // = -408 +#define IQ_I_U_VALUE_MINUS_407 -2276109 // = -407 +#define IQ_I_U_VALUE_MINUS_406 -2270517 // = -406 +#define IQ_I_U_VALUE_MINUS_405 -2264925 // = -405 +#define IQ_I_U_VALUE_MINUS_404 -2259332 // = -404 +#define IQ_I_U_VALUE_MINUS_403 -2253740 // = -403 +#define IQ_I_U_VALUE_MINUS_402 -2248147 // = -402 +#define IQ_I_U_VALUE_MINUS_401 -2242555 // = -401 +#define IQ_I_U_VALUE_MINUS_400 -2236963 // = -400 +#define IQ_I_U_VALUE_MINUS_399 -2231370 // = -399 +#define IQ_I_U_VALUE_MINUS_398 -2225778 // = -398 +#define IQ_I_U_VALUE_MINUS_397 -2220185 // = -397 +#define IQ_I_U_VALUE_MINUS_396 -2214593 // = -396 +#define IQ_I_U_VALUE_MINUS_395 -2209001 // = -395 +#define IQ_I_U_VALUE_MINUS_394 -2203408 // = -394 +#define IQ_I_U_VALUE_MINUS_393 -2197816 // = -393 +#define IQ_I_U_VALUE_MINUS_392 -2192223 // = -392 +#define IQ_I_U_VALUE_MINUS_391 -2186631 // = -391 +#define IQ_I_U_VALUE_MINUS_390 -2181039 // = -390 +#define IQ_I_U_VALUE_MINUS_389 -2175446 // = -389 +#define IQ_I_U_VALUE_MINUS_388 -2169854 // = -388 +#define IQ_I_U_VALUE_MINUS_387 -2164261 // = -387 +#define IQ_I_U_VALUE_MINUS_386 -2158669 // = -386 +#define IQ_I_U_VALUE_MINUS_385 -2153077 // = -385 +#define IQ_I_U_VALUE_MINUS_384 -2147484 // = -384 +#define IQ_I_U_VALUE_MINUS_383 -2141892 // = -383 +#define IQ_I_U_VALUE_MINUS_382 -2136299 // = -382 +#define IQ_I_U_VALUE_MINUS_381 -2130707 // = -381 +#define IQ_I_U_VALUE_MINUS_380 -2125115 // = -380 +#define IQ_I_U_VALUE_MINUS_379 -2119522 // = -379 +#define IQ_I_U_VALUE_MINUS_378 -2113930 // = -378 +#define IQ_I_U_VALUE_MINUS_377 -2108337 // = -377 +#define IQ_I_U_VALUE_MINUS_376 -2102745 // = -376 +#define IQ_I_U_VALUE_MINUS_375 -2097152 // = -375 +#define IQ_I_U_VALUE_MINUS_374 -2091560 // = -374 +#define IQ_I_U_VALUE_MINUS_373 -2085968 // = -373 +#define IQ_I_U_VALUE_MINUS_372 -2080375 // = -372 +#define IQ_I_U_VALUE_MINUS_371 -2074783 // = -371 +#define IQ_I_U_VALUE_MINUS_370 -2069190 // = -370 +#define IQ_I_U_VALUE_MINUS_369 -2063598 // = -369 +#define IQ_I_U_VALUE_MINUS_368 -2058006 // = -368 +#define IQ_I_U_VALUE_MINUS_367 -2052413 // = -367 +#define IQ_I_U_VALUE_MINUS_366 -2046821 // = -366 +#define IQ_I_U_VALUE_MINUS_365 -2041228 // = -365 +#define IQ_I_U_VALUE_MINUS_364 -2035636 // = -364 +#define IQ_I_U_VALUE_MINUS_363 -2030044 // = -363 +#define IQ_I_U_VALUE_MINUS_362 -2024451 // = -362 +#define IQ_I_U_VALUE_MINUS_361 -2018859 // = -361 +#define IQ_I_U_VALUE_MINUS_360 -2013266 // = -360 +#define IQ_I_U_VALUE_MINUS_359 -2007674 // = -359 +#define IQ_I_U_VALUE_MINUS_358 -2002082 // = -358 +#define IQ_I_U_VALUE_MINUS_357 -1996489 // = -357 +#define IQ_I_U_VALUE_MINUS_356 -1990897 // = -356 +#define IQ_I_U_VALUE_MINUS_355 -1985304 // = -355 +#define IQ_I_U_VALUE_MINUS_354 -1979712 // = -354 +#define IQ_I_U_VALUE_MINUS_353 -1974120 // = -353 +#define IQ_I_U_VALUE_MINUS_352 -1968527 // = -352 +#define IQ_I_U_VALUE_MINUS_351 -1962935 // = -351 +#define IQ_I_U_VALUE_MINUS_350 -1957342 // = -350 +#define IQ_I_U_VALUE_MINUS_349 -1951750 // = -349 +#define IQ_I_U_VALUE_MINUS_348 -1946158 // = -348 +#define IQ_I_U_VALUE_MINUS_347 -1940565 // = -347 +#define IQ_I_U_VALUE_MINUS_346 -1934973 // = -346 +#define IQ_I_U_VALUE_MINUS_345 -1929380 // = -345 +#define IQ_I_U_VALUE_MINUS_344 -1923788 // = -344 +#define IQ_I_U_VALUE_MINUS_343 -1918196 // = -343 +#define IQ_I_U_VALUE_MINUS_342 -1912603 // = -342 +#define IQ_I_U_VALUE_MINUS_341 -1907011 // = -341 +#define IQ_I_U_VALUE_MINUS_340 -1901418 // = -340 +#define IQ_I_U_VALUE_MINUS_339 -1895826 // = -339 +#define IQ_I_U_VALUE_MINUS_338 -1890234 // = -338 +#define IQ_I_U_VALUE_MINUS_337 -1884641 // = -337 +#define IQ_I_U_VALUE_MINUS_336 -1879049 // = -336 +#define IQ_I_U_VALUE_MINUS_335 -1873456 // = -335 +#define IQ_I_U_VALUE_MINUS_334 -1867864 // = -334 +#define IQ_I_U_VALUE_MINUS_333 -1862271 // = -333 +#define IQ_I_U_VALUE_MINUS_332 -1856679 // = -332 +#define IQ_I_U_VALUE_MINUS_331 -1851087 // = -331 +#define IQ_I_U_VALUE_MINUS_330 -1845494 // = -330 +#define IQ_I_U_VALUE_MINUS_329 -1839902 // = -329 +#define IQ_I_U_VALUE_MINUS_328 -1834309 // = -328 +#define IQ_I_U_VALUE_MINUS_327 -1828717 // = -327 +#define IQ_I_U_VALUE_MINUS_326 -1823125 // = -326 +#define IQ_I_U_VALUE_MINUS_325 -1817532 // = -325 +#define IQ_I_U_VALUE_MINUS_324 -1811940 // = -324 +#define IQ_I_U_VALUE_MINUS_323 -1806347 // = -323 +#define IQ_I_U_VALUE_MINUS_322 -1800755 // = -322 +#define IQ_I_U_VALUE_MINUS_321 -1795163 // = -321 +#define IQ_I_U_VALUE_MINUS_320 -1789570 // = -320 +#define IQ_I_U_VALUE_MINUS_319 -1783978 // = -319 +#define IQ_I_U_VALUE_MINUS_318 -1778385 // = -318 +#define IQ_I_U_VALUE_MINUS_317 -1772793 // = -317 +#define IQ_I_U_VALUE_MINUS_316 -1767201 // = -316 +#define IQ_I_U_VALUE_MINUS_315 -1761608 // = -315 +#define IQ_I_U_VALUE_MINUS_314 -1756016 // = -314 +#define IQ_I_U_VALUE_MINUS_313 -1750423 // = -313 +#define IQ_I_U_VALUE_MINUS_312 -1744831 // = -312 +#define IQ_I_U_VALUE_MINUS_311 -1739239 // = -311 +#define IQ_I_U_VALUE_MINUS_310 -1733646 // = -310 +#define IQ_I_U_VALUE_MINUS_309 -1728054 // = -309 +#define IQ_I_U_VALUE_MINUS_308 -1722461 // = -308 +#define IQ_I_U_VALUE_MINUS_307 -1716869 // = -307 +#define IQ_I_U_VALUE_MINUS_306 -1711277 // = -306 +#define IQ_I_U_VALUE_MINUS_305 -1705684 // = -305 +#define IQ_I_U_VALUE_MINUS_304 -1700092 // = -304 +#define IQ_I_U_VALUE_MINUS_303 -1694499 // = -303 +#define IQ_I_U_VALUE_MINUS_302 -1688907 // = -302 +#define IQ_I_U_VALUE_MINUS_301 -1683315 // = -301 +#define IQ_I_U_VALUE_MINUS_300 -1677722 // = -300 +#define IQ_I_U_VALUE_MINUS_299 -1672130 // = -299 +#define IQ_I_U_VALUE_MINUS_298 -1666537 // = -298 +#define IQ_I_U_VALUE_MINUS_297 -1660945 // = -297 +#define IQ_I_U_VALUE_MINUS_296 -1655352 // = -296 +#define IQ_I_U_VALUE_MINUS_295 -1649760 // = -295 +#define IQ_I_U_VALUE_MINUS_294 -1644168 // = -294 +#define IQ_I_U_VALUE_MINUS_293 -1638575 // = -293 +#define IQ_I_U_VALUE_MINUS_292 -1632983 // = -292 +#define IQ_I_U_VALUE_MINUS_291 -1627390 // = -291 +#define IQ_I_U_VALUE_MINUS_290 -1621798 // = -290 +#define IQ_I_U_VALUE_MINUS_289 -1616206 // = -289 +#define IQ_I_U_VALUE_MINUS_288 -1610613 // = -288 +#define IQ_I_U_VALUE_MINUS_287 -1605021 // = -287 +#define IQ_I_U_VALUE_MINUS_286 -1599428 // = -286 +#define IQ_I_U_VALUE_MINUS_285 -1593836 // = -285 +#define IQ_I_U_VALUE_MINUS_284 -1588244 // = -284 +#define IQ_I_U_VALUE_MINUS_283 -1582651 // = -283 +#define IQ_I_U_VALUE_MINUS_282 -1577059 // = -282 +#define IQ_I_U_VALUE_MINUS_281 -1571466 // = -281 +#define IQ_I_U_VALUE_MINUS_280 -1565874 // = -280 +#define IQ_I_U_VALUE_MINUS_279 -1560282 // = -279 +#define IQ_I_U_VALUE_MINUS_278 -1554689 // = -278 +#define IQ_I_U_VALUE_MINUS_277 -1549097 // = -277 +#define IQ_I_U_VALUE_MINUS_276 -1543504 // = -276 +#define IQ_I_U_VALUE_MINUS_275 -1537912 // = -275 +#define IQ_I_U_VALUE_MINUS_274 -1532320 // = -274 +#define IQ_I_U_VALUE_MINUS_273 -1526727 // = -273 +#define IQ_I_U_VALUE_MINUS_272 -1521135 // = -272 +#define IQ_I_U_VALUE_MINUS_271 -1515542 // = -271 +#define IQ_I_U_VALUE_MINUS_270 -1509950 // = -270 +#define IQ_I_U_VALUE_MINUS_269 -1504358 // = -269 +#define IQ_I_U_VALUE_MINUS_268 -1498765 // = -268 +#define IQ_I_U_VALUE_MINUS_267 -1493173 // = -267 +#define IQ_I_U_VALUE_MINUS_266 -1487580 // = -266 +#define IQ_I_U_VALUE_MINUS_265 -1481988 // = -265 +#define IQ_I_U_VALUE_MINUS_264 -1476396 // = -264 +#define IQ_I_U_VALUE_MINUS_263 -1470803 // = -263 +#define IQ_I_U_VALUE_MINUS_262 -1465211 // = -262 +#define IQ_I_U_VALUE_MINUS_261 -1459618 // = -261 +#define IQ_I_U_VALUE_MINUS_260 -1454026 // = -260 +#define IQ_I_U_VALUE_MINUS_259 -1448433 // = -259 +#define IQ_I_U_VALUE_MINUS_258 -1442841 // = -258 +#define IQ_I_U_VALUE_MINUS_257 -1437249 // = -257 +#define IQ_I_U_VALUE_MINUS_256 -1431656 // = -256 +#define IQ_I_U_VALUE_MINUS_255 -1426064 // = -255 +#define IQ_I_U_VALUE_MINUS_254 -1420471 // = -254 +#define IQ_I_U_VALUE_MINUS_253 -1414879 // = -253 +#define IQ_I_U_VALUE_MINUS_252 -1409287 // = -252 +#define IQ_I_U_VALUE_MINUS_251 -1403694 // = -251 +#define IQ_I_U_VALUE_MINUS_250 -1398102 // = -250 +#define IQ_I_U_VALUE_MINUS_249 -1392509 // = -249 +#define IQ_I_U_VALUE_MINUS_248 -1386917 // = -248 +#define IQ_I_U_VALUE_MINUS_247 -1381325 // = -247 +#define IQ_I_U_VALUE_MINUS_246 -1375732 // = -246 +#define IQ_I_U_VALUE_MINUS_245 -1370140 // = -245 +#define IQ_I_U_VALUE_MINUS_244 -1364547 // = -244 +#define IQ_I_U_VALUE_MINUS_243 -1358955 // = -243 +#define IQ_I_U_VALUE_MINUS_242 -1353363 // = -242 +#define IQ_I_U_VALUE_MINUS_241 -1347770 // = -241 +#define IQ_I_U_VALUE_MINUS_240 -1342178 // = -240 +#define IQ_I_U_VALUE_MINUS_239 -1336585 // = -239 +#define IQ_I_U_VALUE_MINUS_238 -1330993 // = -238 +#define IQ_I_U_VALUE_MINUS_237 -1325401 // = -237 +#define IQ_I_U_VALUE_MINUS_236 -1319808 // = -236 +#define IQ_I_U_VALUE_MINUS_235 -1314216 // = -235 +#define IQ_I_U_VALUE_MINUS_234 -1308623 // = -234 +#define IQ_I_U_VALUE_MINUS_233 -1303031 // = -233 +#define IQ_I_U_VALUE_MINUS_232 -1297439 // = -232 +#define IQ_I_U_VALUE_MINUS_231 -1291846 // = -231 +#define IQ_I_U_VALUE_MINUS_230 -1286254 // = -230 +#define IQ_I_U_VALUE_MINUS_229 -1280661 // = -229 +#define IQ_I_U_VALUE_MINUS_228 -1275069 // = -228 +#define IQ_I_U_VALUE_MINUS_227 -1269477 // = -227 +#define IQ_I_U_VALUE_MINUS_226 -1263884 // = -226 +#define IQ_I_U_VALUE_MINUS_225 -1258292 // = -225 +#define IQ_I_U_VALUE_MINUS_224 -1252699 // = -224 +#define IQ_I_U_VALUE_MINUS_223 -1247107 // = -223 +#define IQ_I_U_VALUE_MINUS_222 -1241514 // = -222 +#define IQ_I_U_VALUE_MINUS_221 -1235922 // = -221 +#define IQ_I_U_VALUE_MINUS_220 -1230330 // = -220 +#define IQ_I_U_VALUE_MINUS_219 -1224737 // = -219 +#define IQ_I_U_VALUE_MINUS_218 -1219145 // = -218 +#define IQ_I_U_VALUE_MINUS_217 -1213552 // = -217 +#define IQ_I_U_VALUE_MINUS_216 -1207960 // = -216 +#define IQ_I_U_VALUE_MINUS_215 -1202368 // = -215 +#define IQ_I_U_VALUE_MINUS_214 -1196775 // = -214 +#define IQ_I_U_VALUE_MINUS_213 -1191183 // = -213 +#define IQ_I_U_VALUE_MINUS_212 -1185590 // = -212 +#define IQ_I_U_VALUE_MINUS_211 -1179998 // = -211 +#define IQ_I_U_VALUE_MINUS_210 -1174406 // = -210 +#define IQ_I_U_VALUE_MINUS_209 -1168813 // = -209 +#define IQ_I_U_VALUE_MINUS_208 -1163221 // = -208 +#define IQ_I_U_VALUE_MINUS_207 -1157628 // = -207 +#define IQ_I_U_VALUE_MINUS_206 -1152036 // = -206 +#define IQ_I_U_VALUE_MINUS_205 -1146444 // = -205 +#define IQ_I_U_VALUE_MINUS_204 -1140851 // = -204 +#define IQ_I_U_VALUE_MINUS_203 -1135259 // = -203 +#define IQ_I_U_VALUE_MINUS_202 -1129666 // = -202 +#define IQ_I_U_VALUE_MINUS_201 -1124074 // = -201 +#define IQ_I_U_VALUE_MINUS_200 -1118482 // = -200 +#define IQ_I_U_VALUE_MINUS_199 -1112889 // = -199 +#define IQ_I_U_VALUE_MINUS_198 -1107297 // = -198 +#define IQ_I_U_VALUE_MINUS_197 -1101704 // = -197 +#define IQ_I_U_VALUE_MINUS_196 -1096112 // = -196 +#define IQ_I_U_VALUE_MINUS_195 -1090520 // = -195 +#define IQ_I_U_VALUE_MINUS_194 -1084927 // = -194 +#define IQ_I_U_VALUE_MINUS_193 -1079335 // = -193 +#define IQ_I_U_VALUE_MINUS_192 -1073742 // = -192 +#define IQ_I_U_VALUE_MINUS_191 -1068150 // = -191 +#define IQ_I_U_VALUE_MINUS_190 -1062558 // = -190 +#define IQ_I_U_VALUE_MINUS_189 -1056965 // = -189 +#define IQ_I_U_VALUE_MINUS_188 -1051373 // = -188 +#define IQ_I_U_VALUE_MINUS_187 -1045780 // = -187 +#define IQ_I_U_VALUE_MINUS_186 -1040188 // = -186 +#define IQ_I_U_VALUE_MINUS_185 -1034595 // = -185 +#define IQ_I_U_VALUE_MINUS_184 -1029003 // = -184 +#define IQ_I_U_VALUE_MINUS_183 -1023411 // = -183 +#define IQ_I_U_VALUE_MINUS_182 -1017818 // = -182 +#define IQ_I_U_VALUE_MINUS_181 -1012226 // = -181 +#define IQ_I_U_VALUE_MINUS_180 -1006633 // = -180 +#define IQ_I_U_VALUE_MINUS_179 -1001041 // = -179 +#define IQ_I_U_VALUE_MINUS_178 -995449 // = -178 +#define IQ_I_U_VALUE_MINUS_177 -989856 // = -177 +#define IQ_I_U_VALUE_MINUS_176 -984264 // = -176 +#define IQ_I_U_VALUE_MINUS_175 -978671 // = -175 +#define IQ_I_U_VALUE_MINUS_174 -973079 // = -174 +#define IQ_I_U_VALUE_MINUS_173 -967487 // = -173 +#define IQ_I_U_VALUE_MINUS_172 -961894 // = -172 +#define IQ_I_U_VALUE_MINUS_171 -956302 // = -171 +#define IQ_I_U_VALUE_MINUS_170 -950709 // = -170 +#define IQ_I_U_VALUE_MINUS_169 -945117 // = -169 +#define IQ_I_U_VALUE_MINUS_168 -939525 // = -168 +#define IQ_I_U_VALUE_MINUS_167 -933932 // = -167 +#define IQ_I_U_VALUE_MINUS_166 -928340 // = -166 +#define IQ_I_U_VALUE_MINUS_165 -922747 // = -165 +#define IQ_I_U_VALUE_MINUS_164 -917155 // = -164 +#define IQ_I_U_VALUE_MINUS_163 -911563 // = -163 +#define IQ_I_U_VALUE_MINUS_162 -905970 // = -162 +#define IQ_I_U_VALUE_MINUS_161 -900378 // = -161 +#define IQ_I_U_VALUE_MINUS_160 -894785 // = -160 +#define IQ_I_U_VALUE_MINUS_159 -889193 // = -159 +#define IQ_I_U_VALUE_MINUS_158 -883601 // = -158 +#define IQ_I_U_VALUE_MINUS_157 -878008 // = -157 +#define IQ_I_U_VALUE_MINUS_156 -872416 // = -156 +#define IQ_I_U_VALUE_MINUS_155 -866823 // = -155 +#define IQ_I_U_VALUE_MINUS_154 -861231 // = -154 +#define IQ_I_U_VALUE_MINUS_153 -855639 // = -153 +#define IQ_I_U_VALUE_MINUS_152 -850046 // = -152 +#define IQ_I_U_VALUE_MINUS_151 -844454 // = -151 +#define IQ_I_U_VALUE_MINUS_150 -838861 // = -150 +#define IQ_I_U_VALUE_MINUS_149 -833269 // = -149 +#define IQ_I_U_VALUE_MINUS_148 -827676 // = -148 +#define IQ_I_U_VALUE_MINUS_147 -822084 // = -147 +#define IQ_I_U_VALUE_MINUS_146 -816492 // = -146 +#define IQ_I_U_VALUE_MINUS_145 -810899 // = -145 +#define IQ_I_U_VALUE_MINUS_144 -805307 // = -144 +#define IQ_I_U_VALUE_MINUS_143 -799714 // = -143 +#define IQ_I_U_VALUE_MINUS_142 -794122 // = -142 +#define IQ_I_U_VALUE_MINUS_141 -788530 // = -141 +#define IQ_I_U_VALUE_MINUS_140 -782937 // = -140 +#define IQ_I_U_VALUE_MINUS_139 -777345 // = -139 +#define IQ_I_U_VALUE_MINUS_138 -771752 // = -138 +#define IQ_I_U_VALUE_MINUS_137 -766160 // = -137 +#define IQ_I_U_VALUE_MINUS_136 -760568 // = -136 +#define IQ_I_U_VALUE_MINUS_135 -754975 // = -135 +#define IQ_I_U_VALUE_MINUS_134 -749383 // = -134 +#define IQ_I_U_VALUE_MINUS_133 -743790 // = -133 +#define IQ_I_U_VALUE_MINUS_132 -738198 // = -132 +#define IQ_I_U_VALUE_MINUS_131 -732606 // = -131 +#define IQ_I_U_VALUE_MINUS_130 -727013 // = -130 +#define IQ_I_U_VALUE_MINUS_129 -721421 // = -129 +#define IQ_I_U_VALUE_MINUS_128 -715828 // = -128 +#define IQ_I_U_VALUE_MINUS_127 -710236 // = -127 +#define IQ_I_U_VALUE_MINUS_126 -704644 // = -126 +#define IQ_I_U_VALUE_MINUS_125 -699051 // = -125 +#define IQ_I_U_VALUE_MINUS_124 -693459 // = -124 +#define IQ_I_U_VALUE_MINUS_123 -687866 // = -123 +#define IQ_I_U_VALUE_MINUS_122 -682274 // = -122 +#define IQ_I_U_VALUE_MINUS_121 -676682 // = -121 +#define IQ_I_U_VALUE_MINUS_120 -671089 // = -120 +#define IQ_I_U_VALUE_MINUS_119 -665497 // = -119 +#define IQ_I_U_VALUE_MINUS_118 -659904 // = -118 +#define IQ_I_U_VALUE_MINUS_117 -654312 // = -117 +#define IQ_I_U_VALUE_MINUS_116 -648720 // = -116 +#define IQ_I_U_VALUE_MINUS_115 -643127 // = -115 +#define IQ_I_U_VALUE_MINUS_114 -637535 // = -114 +#define IQ_I_U_VALUE_MINUS_113 -631942 // = -113 +#define IQ_I_U_VALUE_MINUS_112 -626350 // = -112 +#define IQ_I_U_VALUE_MINUS_111 -620757 // = -111 +#define IQ_I_U_VALUE_MINUS_110 -615165 // = -110 +#define IQ_I_U_VALUE_MINUS_109 -609573 // = -109 +#define IQ_I_U_VALUE_MINUS_108 -603980 // = -108 +#define IQ_I_U_VALUE_MINUS_107 -598388 // = -107 +#define IQ_I_U_VALUE_MINUS_106 -592795 // = -106 +#define IQ_I_U_VALUE_MINUS_105 -587203 // = -105 +#define IQ_I_U_VALUE_MINUS_104 -581611 // = -104 +#define IQ_I_U_VALUE_MINUS_103 -576018 // = -103 +#define IQ_I_U_VALUE_MINUS_102 -570426 // = -102 +#define IQ_I_U_VALUE_MINUS_101 -564833 // = -101 +#define IQ_I_U_VALUE_MINUS_100 -559241 // = -100 +#define IQ_I_U_VALUE_MINUS_99 -553649 // = -99 +#define IQ_I_U_VALUE_MINUS_98 -548056 // = -98 +#define IQ_I_U_VALUE_MINUS_97 -542464 // = -97 +#define IQ_I_U_VALUE_MINUS_96 -536871 // = -96 +#define IQ_I_U_VALUE_MINUS_95 -531279 // = -95 +#define IQ_I_U_VALUE_MINUS_94 -525687 // = -94 +#define IQ_I_U_VALUE_MINUS_93 -520094 // = -93 +#define IQ_I_U_VALUE_MINUS_92 -514502 // = -92 +#define IQ_I_U_VALUE_MINUS_91 -508909 // = -91 +#define IQ_I_U_VALUE_MINUS_90 -503317 // = -90 +#define IQ_I_U_VALUE_MINUS_89 -497725 // = -89 +#define IQ_I_U_VALUE_MINUS_88 -492132 // = -88 +#define IQ_I_U_VALUE_MINUS_87 -486540 // = -87 +#define IQ_I_U_VALUE_MINUS_86 -480947 // = -86 +#define IQ_I_U_VALUE_MINUS_85 -475355 // = -85 +#define IQ_I_U_VALUE_MINUS_84 -469763 // = -84 +#define IQ_I_U_VALUE_MINUS_83 -464170 // = -83 +#define IQ_I_U_VALUE_MINUS_82 -458578 // = -82 +#define IQ_I_U_VALUE_MINUS_81 -452985 // = -81 +#define IQ_I_U_VALUE_MINUS_80 -447393 // = -80 +#define IQ_I_U_VALUE_MINUS_79 -441801 // = -79 +#define IQ_I_U_VALUE_MINUS_78 -436208 // = -78 +#define IQ_I_U_VALUE_MINUS_77 -430616 // = -77 +#define IQ_I_U_VALUE_MINUS_76 -425023 // = -76 +#define IQ_I_U_VALUE_MINUS_75 -419431 // = -75 +#define IQ_I_U_VALUE_MINUS_74 -413838 // = -74 +#define IQ_I_U_VALUE_MINUS_73 -408246 // = -73 +#define IQ_I_U_VALUE_MINUS_72 -402654 // = -72 +#define IQ_I_U_VALUE_MINUS_71 -397061 // = -71 +#define IQ_I_U_VALUE_MINUS_70 -391469 // = -70 +#define IQ_I_U_VALUE_MINUS_69 -385876 // = -69 +#define IQ_I_U_VALUE_MINUS_68 -380284 // = -68 +#define IQ_I_U_VALUE_MINUS_67 -374692 // = -67 +#define IQ_I_U_VALUE_MINUS_66 -369099 // = -66 +#define IQ_I_U_VALUE_MINUS_65 -363507 // = -65 +#define IQ_I_U_VALUE_MINUS_64 -357914 // = -64 +#define IQ_I_U_VALUE_MINUS_63 -352322 // = -63 +#define IQ_I_U_VALUE_MINUS_62 -346730 // = -62 +#define IQ_I_U_VALUE_MINUS_61 -341137 // = -61 +#define IQ_I_U_VALUE_MINUS_60 -335545 // = -60 +#define IQ_I_U_VALUE_MINUS_59 -329952 // = -59 +#define IQ_I_U_VALUE_MINUS_58 -324360 // = -58 +#define IQ_I_U_VALUE_MINUS_57 -318768 // = -57 +#define IQ_I_U_VALUE_MINUS_56 -313175 // = -56 +#define IQ_I_U_VALUE_MINUS_55 -307583 // = -55 +#define IQ_I_U_VALUE_MINUS_54 -301990 // = -54 +#define IQ_I_U_VALUE_MINUS_53 -296398 // = -53 +#define IQ_I_U_VALUE_MINUS_52 -290806 // = -52 +#define IQ_I_U_VALUE_MINUS_51 -285213 // = -51 +#define IQ_I_U_VALUE_MINUS_50 -279621 // = -50 +#define IQ_I_U_VALUE_MINUS_49 -274028 // = -49 +#define IQ_I_U_VALUE_MINUS_48 -268436 // = -48 +#define IQ_I_U_VALUE_MINUS_47 -262844 // = -47 +#define IQ_I_U_VALUE_MINUS_46 -257251 // = -46 +#define IQ_I_U_VALUE_MINUS_45 -251659 // = -45 +#define IQ_I_U_VALUE_MINUS_44 -246066 // = -44 +#define IQ_I_U_VALUE_MINUS_43 -240474 // = -43 +#define IQ_I_U_VALUE_MINUS_42 -234882 // = -42 +#define IQ_I_U_VALUE_MINUS_41 -229289 // = -41 +#define IQ_I_U_VALUE_MINUS_40 -223697 // = -40 +#define IQ_I_U_VALUE_MINUS_39 -218104 // = -39 +#define IQ_I_U_VALUE_MINUS_38 -212512 // = -38 +#define IQ_I_U_VALUE_MINUS_37 -206919 // = -37 +#define IQ_I_U_VALUE_MINUS_36 -201327 // = -36 +#define IQ_I_U_VALUE_MINUS_35 -195735 // = -35 +#define IQ_I_U_VALUE_MINUS_34 -190142 // = -34 +#define IQ_I_U_VALUE_MINUS_33 -184550 // = -33 +#define IQ_I_U_VALUE_MINUS_32 -178957 // = -32 +#define IQ_I_U_VALUE_MINUS_31 -173365 // = -31 +#define IQ_I_U_VALUE_MINUS_30 -167773 // = -30 +#define IQ_I_U_VALUE_MINUS_29 -162180 // = -29 +#define IQ_I_U_VALUE_MINUS_28 -156588 // = -28 +#define IQ_I_U_VALUE_MINUS_27 -150995 // = -27 +#define IQ_I_U_VALUE_MINUS_26 -145403 // = -26 +#define IQ_I_U_VALUE_MINUS_25 -139811 // = -25 +#define IQ_I_U_VALUE_MINUS_24 -134218 // = -24 +#define IQ_I_U_VALUE_MINUS_23 -128626 // = -23 +#define IQ_I_U_VALUE_MINUS_22 -123033 // = -22 +#define IQ_I_U_VALUE_MINUS_21 -117441 // = -21 +#define IQ_I_U_VALUE_MINUS_20 -111849 // = -20 +#define IQ_I_U_VALUE_MINUS_19 -106256 // = -19 +#define IQ_I_U_VALUE_MINUS_18 -100664 // = -18 +#define IQ_I_U_VALUE_MINUS_17 -95071 // = -17 +#define IQ_I_U_VALUE_MINUS_16 -89479 // = -16 +#define IQ_I_U_VALUE_MINUS_15 -83887 // = -15 +#define IQ_I_U_VALUE_MINUS_14 -78294 // = -14 +#define IQ_I_U_VALUE_MINUS_13 -72702 // = -13 +#define IQ_I_U_VALUE_MINUS_12 -67109 // = -12 +#define IQ_I_U_VALUE_MINUS_11 -61517 // = -11 +#define IQ_I_U_VALUE_MINUS_10 -55925 // = -10 +#define IQ_I_U_VALUE_MINUS_9 -50332 // = -9 +#define IQ_I_U_VALUE_MINUS_8 -44740 // = -8 +#define IQ_I_U_VALUE_MINUS_7 -39147 // = -7 +#define IQ_I_U_VALUE_MINUS_6 -33555 // = -6 +#define IQ_I_U_VALUE_MINUS_5 -27963 // = -5 +#define IQ_I_U_VALUE_MINUS_4 -22370 // = -4 +#define IQ_I_U_VALUE_MINUS_3 -16778 // = -3 +#define IQ_I_U_VALUE_MINUS_2 -11185 // = -2 +#define IQ_I_U_VALUE_MINUS_1 -5593 // = -1 +#define IQ_I_U_VALUE_ZERO_0 0 // = 0 +#define IQ_I_U_VALUE_PLUS_1 5592 // = 1 +#define IQ_I_U_VALUE_PLUS_2 11184 // = 2 +#define IQ_I_U_VALUE_PLUS_3 16777 // = 3 +#define IQ_I_U_VALUE_PLUS_4 22369 // = 4 +#define IQ_I_U_VALUE_PLUS_5 27962 // = 5 +#define IQ_I_U_VALUE_PLUS_6 33554 // = 6 +#define IQ_I_U_VALUE_PLUS_7 39146 // = 7 +#define IQ_I_U_VALUE_PLUS_8 44739 // = 8 +#define IQ_I_U_VALUE_PLUS_9 50331 // = 9 +#define IQ_I_U_VALUE_PLUS_10 55924 // = 10 +#define IQ_I_U_VALUE_PLUS_11 61516 // = 11 +#define IQ_I_U_VALUE_PLUS_12 67108 // = 12 +#define IQ_I_U_VALUE_PLUS_13 72701 // = 13 +#define IQ_I_U_VALUE_PLUS_14 78293 // = 14 +#define IQ_I_U_VALUE_PLUS_15 83886 // = 15 +#define IQ_I_U_VALUE_PLUS_16 89478 // = 16 +#define IQ_I_U_VALUE_PLUS_17 95070 // = 17 +#define IQ_I_U_VALUE_PLUS_18 100663 // = 18 +#define IQ_I_U_VALUE_PLUS_19 106255 // = 19 +#define IQ_I_U_VALUE_PLUS_20 111848 // = 20 +#define IQ_I_U_VALUE_PLUS_21 117440 // = 21 +#define IQ_I_U_VALUE_PLUS_22 123032 // = 22 +#define IQ_I_U_VALUE_PLUS_23 128625 // = 23 +#define IQ_I_U_VALUE_PLUS_24 134217 // = 24 +#define IQ_I_U_VALUE_PLUS_25 139810 // = 25 +#define IQ_I_U_VALUE_PLUS_26 145402 // = 26 +#define IQ_I_U_VALUE_PLUS_27 150994 // = 27 +#define IQ_I_U_VALUE_PLUS_28 156587 // = 28 +#define IQ_I_U_VALUE_PLUS_29 162179 // = 29 +#define IQ_I_U_VALUE_PLUS_30 167772 // = 30 +#define IQ_I_U_VALUE_PLUS_31 173364 // = 31 +#define IQ_I_U_VALUE_PLUS_32 178956 // = 32 +#define IQ_I_U_VALUE_PLUS_33 184549 // = 33 +#define IQ_I_U_VALUE_PLUS_34 190141 // = 34 +#define IQ_I_U_VALUE_PLUS_35 195734 // = 35 +#define IQ_I_U_VALUE_PLUS_36 201326 // = 36 +#define IQ_I_U_VALUE_PLUS_37 206918 // = 37 +#define IQ_I_U_VALUE_PLUS_38 212511 // = 38 +#define IQ_I_U_VALUE_PLUS_39 218103 // = 39 +#define IQ_I_U_VALUE_PLUS_40 223696 // = 40 +#define IQ_I_U_VALUE_PLUS_41 229288 // = 41 +#define IQ_I_U_VALUE_PLUS_42 234881 // = 42 +#define IQ_I_U_VALUE_PLUS_43 240473 // = 43 +#define IQ_I_U_VALUE_PLUS_44 246065 // = 44 +#define IQ_I_U_VALUE_PLUS_45 251658 // = 45 +#define IQ_I_U_VALUE_PLUS_46 257250 // = 46 +#define IQ_I_U_VALUE_PLUS_47 262843 // = 47 +#define IQ_I_U_VALUE_PLUS_48 268435 // = 48 +#define IQ_I_U_VALUE_PLUS_49 274027 // = 49 +#define IQ_I_U_VALUE_PLUS_50 279620 // = 50 +#define IQ_I_U_VALUE_PLUS_51 285212 // = 51 +#define IQ_I_U_VALUE_PLUS_52 290805 // = 52 +#define IQ_I_U_VALUE_PLUS_53 296397 // = 53 +#define IQ_I_U_VALUE_PLUS_54 301989 // = 54 +#define IQ_I_U_VALUE_PLUS_55 307582 // = 55 +#define IQ_I_U_VALUE_PLUS_56 313174 // = 56 +#define IQ_I_U_VALUE_PLUS_57 318767 // = 57 +#define IQ_I_U_VALUE_PLUS_58 324359 // = 58 +#define IQ_I_U_VALUE_PLUS_59 329951 // = 59 +#define IQ_I_U_VALUE_PLUS_60 335544 // = 60 +#define IQ_I_U_VALUE_PLUS_61 341136 // = 61 +#define IQ_I_U_VALUE_PLUS_62 346729 // = 62 +#define IQ_I_U_VALUE_PLUS_63 352321 // = 63 +#define IQ_I_U_VALUE_PLUS_64 357913 // = 64 +#define IQ_I_U_VALUE_PLUS_65 363506 // = 65 +#define IQ_I_U_VALUE_PLUS_66 369098 // = 66 +#define IQ_I_U_VALUE_PLUS_67 374691 // = 67 +#define IQ_I_U_VALUE_PLUS_68 380283 // = 68 +#define IQ_I_U_VALUE_PLUS_69 385875 // = 69 +#define IQ_I_U_VALUE_PLUS_70 391468 // = 70 +#define IQ_I_U_VALUE_PLUS_71 397060 // = 71 +#define IQ_I_U_VALUE_PLUS_72 402653 // = 72 +#define IQ_I_U_VALUE_PLUS_73 408245 // = 73 +#define IQ_I_U_VALUE_PLUS_74 413837 // = 74 +#define IQ_I_U_VALUE_PLUS_75 419430 // = 75 +#define IQ_I_U_VALUE_PLUS_76 425022 // = 76 +#define IQ_I_U_VALUE_PLUS_77 430615 // = 77 +#define IQ_I_U_VALUE_PLUS_78 436207 // = 78 +#define IQ_I_U_VALUE_PLUS_79 441800 // = 79 +#define IQ_I_U_VALUE_PLUS_80 447392 // = 80 +#define IQ_I_U_VALUE_PLUS_81 452984 // = 81 +#define IQ_I_U_VALUE_PLUS_82 458577 // = 82 +#define IQ_I_U_VALUE_PLUS_83 464169 // = 83 +#define IQ_I_U_VALUE_PLUS_84 469762 // = 84 +#define IQ_I_U_VALUE_PLUS_85 475354 // = 85 +#define IQ_I_U_VALUE_PLUS_86 480946 // = 86 +#define IQ_I_U_VALUE_PLUS_87 486539 // = 87 +#define IQ_I_U_VALUE_PLUS_88 492131 // = 88 +#define IQ_I_U_VALUE_PLUS_89 497724 // = 89 +#define IQ_I_U_VALUE_PLUS_90 503316 // = 90 +#define IQ_I_U_VALUE_PLUS_91 508908 // = 91 +#define IQ_I_U_VALUE_PLUS_92 514501 // = 92 +#define IQ_I_U_VALUE_PLUS_93 520093 // = 93 +#define IQ_I_U_VALUE_PLUS_94 525686 // = 94 +#define IQ_I_U_VALUE_PLUS_95 531278 // = 95 +#define IQ_I_U_VALUE_PLUS_96 536870 // = 96 +#define IQ_I_U_VALUE_PLUS_97 542463 // = 97 +#define IQ_I_U_VALUE_PLUS_98 548055 // = 98 +#define IQ_I_U_VALUE_PLUS_99 553648 // = 99 +#define IQ_I_U_VALUE_PLUS_100 559240 // = 100 +#define IQ_I_U_VALUE_PLUS_101 564832 // = 101 +#define IQ_I_U_VALUE_PLUS_102 570425 // = 102 +#define IQ_I_U_VALUE_PLUS_103 576017 // = 103 +#define IQ_I_U_VALUE_PLUS_104 581610 // = 104 +#define IQ_I_U_VALUE_PLUS_105 587202 // = 105 +#define IQ_I_U_VALUE_PLUS_106 592794 // = 106 +#define IQ_I_U_VALUE_PLUS_107 598387 // = 107 +#define IQ_I_U_VALUE_PLUS_108 603979 // = 108 +#define IQ_I_U_VALUE_PLUS_109 609572 // = 109 +#define IQ_I_U_VALUE_PLUS_110 615164 // = 110 +#define IQ_I_U_VALUE_PLUS_111 620756 // = 111 +#define IQ_I_U_VALUE_PLUS_112 626349 // = 112 +#define IQ_I_U_VALUE_PLUS_113 631941 // = 113 +#define IQ_I_U_VALUE_PLUS_114 637534 // = 114 +#define IQ_I_U_VALUE_PLUS_115 643126 // = 115 +#define IQ_I_U_VALUE_PLUS_116 648719 // = 116 +#define IQ_I_U_VALUE_PLUS_117 654311 // = 117 +#define IQ_I_U_VALUE_PLUS_118 659903 // = 118 +#define IQ_I_U_VALUE_PLUS_119 665496 // = 119 +#define IQ_I_U_VALUE_PLUS_120 671088 // = 120 +#define IQ_I_U_VALUE_PLUS_121 676681 // = 121 +#define IQ_I_U_VALUE_PLUS_122 682273 // = 122 +#define IQ_I_U_VALUE_PLUS_123 687865 // = 123 +#define IQ_I_U_VALUE_PLUS_124 693458 // = 124 +#define IQ_I_U_VALUE_PLUS_125 699050 // = 125 +#define IQ_I_U_VALUE_PLUS_126 704643 // = 126 +#define IQ_I_U_VALUE_PLUS_127 710235 // = 127 +#define IQ_I_U_VALUE_PLUS_128 715827 // = 128 +#define IQ_I_U_VALUE_PLUS_129 721420 // = 129 +#define IQ_I_U_VALUE_PLUS_130 727012 // = 130 +#define IQ_I_U_VALUE_PLUS_131 732605 // = 131 +#define IQ_I_U_VALUE_PLUS_132 738197 // = 132 +#define IQ_I_U_VALUE_PLUS_133 743789 // = 133 +#define IQ_I_U_VALUE_PLUS_134 749382 // = 134 +#define IQ_I_U_VALUE_PLUS_135 754974 // = 135 +#define IQ_I_U_VALUE_PLUS_136 760567 // = 136 +#define IQ_I_U_VALUE_PLUS_137 766159 // = 137 +#define IQ_I_U_VALUE_PLUS_138 771751 // = 138 +#define IQ_I_U_VALUE_PLUS_139 777344 // = 139 +#define IQ_I_U_VALUE_PLUS_140 782936 // = 140 +#define IQ_I_U_VALUE_PLUS_141 788529 // = 141 +#define IQ_I_U_VALUE_PLUS_142 794121 // = 142 +#define IQ_I_U_VALUE_PLUS_143 799713 // = 143 +#define IQ_I_U_VALUE_PLUS_144 805306 // = 144 +#define IQ_I_U_VALUE_PLUS_145 810898 // = 145 +#define IQ_I_U_VALUE_PLUS_146 816491 // = 146 +#define IQ_I_U_VALUE_PLUS_147 822083 // = 147 +#define IQ_I_U_VALUE_PLUS_148 827675 // = 148 +#define IQ_I_U_VALUE_PLUS_149 833268 // = 149 +#define IQ_I_U_VALUE_PLUS_150 838860 // = 150 +#define IQ_I_U_VALUE_PLUS_151 844453 // = 151 +#define IQ_I_U_VALUE_PLUS_152 850045 // = 152 +#define IQ_I_U_VALUE_PLUS_153 855638 // = 153 +#define IQ_I_U_VALUE_PLUS_154 861230 // = 154 +#define IQ_I_U_VALUE_PLUS_155 866822 // = 155 +#define IQ_I_U_VALUE_PLUS_156 872415 // = 156 +#define IQ_I_U_VALUE_PLUS_157 878007 // = 157 +#define IQ_I_U_VALUE_PLUS_158 883600 // = 158 +#define IQ_I_U_VALUE_PLUS_159 889192 // = 159 +#define IQ_I_U_VALUE_PLUS_160 894784 // = 160 +#define IQ_I_U_VALUE_PLUS_161 900377 // = 161 +#define IQ_I_U_VALUE_PLUS_162 905969 // = 162 +#define IQ_I_U_VALUE_PLUS_163 911562 // = 163 +#define IQ_I_U_VALUE_PLUS_164 917154 // = 164 +#define IQ_I_U_VALUE_PLUS_165 922746 // = 165 +#define IQ_I_U_VALUE_PLUS_166 928339 // = 166 +#define IQ_I_U_VALUE_PLUS_167 933931 // = 167 +#define IQ_I_U_VALUE_PLUS_168 939524 // = 168 +#define IQ_I_U_VALUE_PLUS_169 945116 // = 169 +#define IQ_I_U_VALUE_PLUS_170 950708 // = 170 +#define IQ_I_U_VALUE_PLUS_171 956301 // = 171 +#define IQ_I_U_VALUE_PLUS_172 961893 // = 172 +#define IQ_I_U_VALUE_PLUS_173 967486 // = 173 +#define IQ_I_U_VALUE_PLUS_174 973078 // = 174 +#define IQ_I_U_VALUE_PLUS_175 978670 // = 175 +#define IQ_I_U_VALUE_PLUS_176 984263 // = 176 +#define IQ_I_U_VALUE_PLUS_177 989855 // = 177 +#define IQ_I_U_VALUE_PLUS_178 995448 // = 178 +#define IQ_I_U_VALUE_PLUS_179 1001040 // = 179 +#define IQ_I_U_VALUE_PLUS_180 1006632 // = 180 +#define IQ_I_U_VALUE_PLUS_181 1012225 // = 181 +#define IQ_I_U_VALUE_PLUS_182 1017817 // = 182 +#define IQ_I_U_VALUE_PLUS_183 1023410 // = 183 +#define IQ_I_U_VALUE_PLUS_184 1029002 // = 184 +#define IQ_I_U_VALUE_PLUS_185 1034594 // = 185 +#define IQ_I_U_VALUE_PLUS_186 1040187 // = 186 +#define IQ_I_U_VALUE_PLUS_187 1045779 // = 187 +#define IQ_I_U_VALUE_PLUS_188 1051372 // = 188 +#define IQ_I_U_VALUE_PLUS_189 1056964 // = 189 +#define IQ_I_U_VALUE_PLUS_190 1062557 // = 190 +#define IQ_I_U_VALUE_PLUS_191 1068149 // = 191 +#define IQ_I_U_VALUE_PLUS_192 1073741 // = 192 +#define IQ_I_U_VALUE_PLUS_193 1079334 // = 193 +#define IQ_I_U_VALUE_PLUS_194 1084926 // = 194 +#define IQ_I_U_VALUE_PLUS_195 1090519 // = 195 +#define IQ_I_U_VALUE_PLUS_196 1096111 // = 196 +#define IQ_I_U_VALUE_PLUS_197 1101703 // = 197 +#define IQ_I_U_VALUE_PLUS_198 1107296 // = 198 +#define IQ_I_U_VALUE_PLUS_199 1112888 // = 199 +#define IQ_I_U_VALUE_PLUS_200 1118481 // = 200 +#define IQ_I_U_VALUE_PLUS_201 1124073 // = 201 +#define IQ_I_U_VALUE_PLUS_202 1129665 // = 202 +#define IQ_I_U_VALUE_PLUS_203 1135258 // = 203 +#define IQ_I_U_VALUE_PLUS_204 1140850 // = 204 +#define IQ_I_U_VALUE_PLUS_205 1146443 // = 205 +#define IQ_I_U_VALUE_PLUS_206 1152035 // = 206 +#define IQ_I_U_VALUE_PLUS_207 1157627 // = 207 +#define IQ_I_U_VALUE_PLUS_208 1163220 // = 208 +#define IQ_I_U_VALUE_PLUS_209 1168812 // = 209 +#define IQ_I_U_VALUE_PLUS_210 1174405 // = 210 +#define IQ_I_U_VALUE_PLUS_211 1179997 // = 211 +#define IQ_I_U_VALUE_PLUS_212 1185589 // = 212 +#define IQ_I_U_VALUE_PLUS_213 1191182 // = 213 +#define IQ_I_U_VALUE_PLUS_214 1196774 // = 214 +#define IQ_I_U_VALUE_PLUS_215 1202367 // = 215 +#define IQ_I_U_VALUE_PLUS_216 1207959 // = 216 +#define IQ_I_U_VALUE_PLUS_217 1213551 // = 217 +#define IQ_I_U_VALUE_PLUS_218 1219144 // = 218 +#define IQ_I_U_VALUE_PLUS_219 1224736 // = 219 +#define IQ_I_U_VALUE_PLUS_220 1230329 // = 220 +#define IQ_I_U_VALUE_PLUS_221 1235921 // = 221 +#define IQ_I_U_VALUE_PLUS_222 1241513 // = 222 +#define IQ_I_U_VALUE_PLUS_223 1247106 // = 223 +#define IQ_I_U_VALUE_PLUS_224 1252698 // = 224 +#define IQ_I_U_VALUE_PLUS_225 1258291 // = 225 +#define IQ_I_U_VALUE_PLUS_226 1263883 // = 226 +#define IQ_I_U_VALUE_PLUS_227 1269476 // = 227 +#define IQ_I_U_VALUE_PLUS_228 1275068 // = 228 +#define IQ_I_U_VALUE_PLUS_229 1280660 // = 229 +#define IQ_I_U_VALUE_PLUS_230 1286253 // = 230 +#define IQ_I_U_VALUE_PLUS_231 1291845 // = 231 +#define IQ_I_U_VALUE_PLUS_232 1297438 // = 232 +#define IQ_I_U_VALUE_PLUS_233 1303030 // = 233 +#define IQ_I_U_VALUE_PLUS_234 1308622 // = 234 +#define IQ_I_U_VALUE_PLUS_235 1314215 // = 235 +#define IQ_I_U_VALUE_PLUS_236 1319807 // = 236 +#define IQ_I_U_VALUE_PLUS_237 1325400 // = 237 +#define IQ_I_U_VALUE_PLUS_238 1330992 // = 238 +#define IQ_I_U_VALUE_PLUS_239 1336584 // = 239 +#define IQ_I_U_VALUE_PLUS_240 1342177 // = 240 +#define IQ_I_U_VALUE_PLUS_241 1347769 // = 241 +#define IQ_I_U_VALUE_PLUS_242 1353362 // = 242 +#define IQ_I_U_VALUE_PLUS_243 1358954 // = 243 +#define IQ_I_U_VALUE_PLUS_244 1364546 // = 244 +#define IQ_I_U_VALUE_PLUS_245 1370139 // = 245 +#define IQ_I_U_VALUE_PLUS_246 1375731 // = 246 +#define IQ_I_U_VALUE_PLUS_247 1381324 // = 247 +#define IQ_I_U_VALUE_PLUS_248 1386916 // = 248 +#define IQ_I_U_VALUE_PLUS_249 1392508 // = 249 +#define IQ_I_U_VALUE_PLUS_250 1398101 // = 250 +#define IQ_I_U_VALUE_PLUS_251 1403693 // = 251 +#define IQ_I_U_VALUE_PLUS_252 1409286 // = 252 +#define IQ_I_U_VALUE_PLUS_253 1414878 // = 253 +#define IQ_I_U_VALUE_PLUS_254 1420470 // = 254 +#define IQ_I_U_VALUE_PLUS_255 1426063 // = 255 +#define IQ_I_U_VALUE_PLUS_256 1431655 // = 256 +#define IQ_I_U_VALUE_PLUS_257 1437248 // = 257 +#define IQ_I_U_VALUE_PLUS_258 1442840 // = 258 +#define IQ_I_U_VALUE_PLUS_259 1448432 // = 259 +#define IQ_I_U_VALUE_PLUS_260 1454025 // = 260 +#define IQ_I_U_VALUE_PLUS_261 1459617 // = 261 +#define IQ_I_U_VALUE_PLUS_262 1465210 // = 262 +#define IQ_I_U_VALUE_PLUS_263 1470802 // = 263 +#define IQ_I_U_VALUE_PLUS_264 1476395 // = 264 +#define IQ_I_U_VALUE_PLUS_265 1481987 // = 265 +#define IQ_I_U_VALUE_PLUS_266 1487579 // = 266 +#define IQ_I_U_VALUE_PLUS_267 1493172 // = 267 +#define IQ_I_U_VALUE_PLUS_268 1498764 // = 268 +#define IQ_I_U_VALUE_PLUS_269 1504357 // = 269 +#define IQ_I_U_VALUE_PLUS_270 1509949 // = 270 +#define IQ_I_U_VALUE_PLUS_271 1515541 // = 271 +#define IQ_I_U_VALUE_PLUS_272 1521134 // = 272 +#define IQ_I_U_VALUE_PLUS_273 1526726 // = 273 +#define IQ_I_U_VALUE_PLUS_274 1532319 // = 274 +#define IQ_I_U_VALUE_PLUS_275 1537911 // = 275 +#define IQ_I_U_VALUE_PLUS_276 1543503 // = 276 +#define IQ_I_U_VALUE_PLUS_277 1549096 // = 277 +#define IQ_I_U_VALUE_PLUS_278 1554688 // = 278 +#define IQ_I_U_VALUE_PLUS_279 1560281 // = 279 +#define IQ_I_U_VALUE_PLUS_280 1565873 // = 280 +#define IQ_I_U_VALUE_PLUS_281 1571465 // = 281 +#define IQ_I_U_VALUE_PLUS_282 1577058 // = 282 +#define IQ_I_U_VALUE_PLUS_283 1582650 // = 283 +#define IQ_I_U_VALUE_PLUS_284 1588243 // = 284 +#define IQ_I_U_VALUE_PLUS_285 1593835 // = 285 +#define IQ_I_U_VALUE_PLUS_286 1599427 // = 286 +#define IQ_I_U_VALUE_PLUS_287 1605020 // = 287 +#define IQ_I_U_VALUE_PLUS_288 1610612 // = 288 +#define IQ_I_U_VALUE_PLUS_289 1616205 // = 289 +#define IQ_I_U_VALUE_PLUS_290 1621797 // = 290 +#define IQ_I_U_VALUE_PLUS_291 1627389 // = 291 +#define IQ_I_U_VALUE_PLUS_292 1632982 // = 292 +#define IQ_I_U_VALUE_PLUS_293 1638574 // = 293 +#define IQ_I_U_VALUE_PLUS_294 1644167 // = 294 +#define IQ_I_U_VALUE_PLUS_295 1649759 // = 295 +#define IQ_I_U_VALUE_PLUS_296 1655351 // = 296 +#define IQ_I_U_VALUE_PLUS_297 1660944 // = 297 +#define IQ_I_U_VALUE_PLUS_298 1666536 // = 298 +#define IQ_I_U_VALUE_PLUS_299 1672129 // = 299 +#define IQ_I_U_VALUE_PLUS_300 1677721 // = 300 +#define IQ_I_U_VALUE_PLUS_301 1683314 // = 301 +#define IQ_I_U_VALUE_PLUS_302 1688906 // = 302 +#define IQ_I_U_VALUE_PLUS_303 1694498 // = 303 +#define IQ_I_U_VALUE_PLUS_304 1700091 // = 304 +#define IQ_I_U_VALUE_PLUS_305 1705683 // = 305 +#define IQ_I_U_VALUE_PLUS_306 1711276 // = 306 +#define IQ_I_U_VALUE_PLUS_307 1716868 // = 307 +#define IQ_I_U_VALUE_PLUS_308 1722460 // = 308 +#define IQ_I_U_VALUE_PLUS_309 1728053 // = 309 +#define IQ_I_U_VALUE_PLUS_310 1733645 // = 310 +#define IQ_I_U_VALUE_PLUS_311 1739238 // = 311 +#define IQ_I_U_VALUE_PLUS_312 1744830 // = 312 +#define IQ_I_U_VALUE_PLUS_313 1750422 // = 313 +#define IQ_I_U_VALUE_PLUS_314 1756015 // = 314 +#define IQ_I_U_VALUE_PLUS_315 1761607 // = 315 +#define IQ_I_U_VALUE_PLUS_316 1767200 // = 316 +#define IQ_I_U_VALUE_PLUS_317 1772792 // = 317 +#define IQ_I_U_VALUE_PLUS_318 1778384 // = 318 +#define IQ_I_U_VALUE_PLUS_319 1783977 // = 319 +#define IQ_I_U_VALUE_PLUS_320 1789569 // = 320 +#define IQ_I_U_VALUE_PLUS_321 1795162 // = 321 +#define IQ_I_U_VALUE_PLUS_322 1800754 // = 322 +#define IQ_I_U_VALUE_PLUS_323 1806346 // = 323 +#define IQ_I_U_VALUE_PLUS_324 1811939 // = 324 +#define IQ_I_U_VALUE_PLUS_325 1817531 // = 325 +#define IQ_I_U_VALUE_PLUS_326 1823124 // = 326 +#define IQ_I_U_VALUE_PLUS_327 1828716 // = 327 +#define IQ_I_U_VALUE_PLUS_328 1834308 // = 328 +#define IQ_I_U_VALUE_PLUS_329 1839901 // = 329 +#define IQ_I_U_VALUE_PLUS_330 1845493 // = 330 +#define IQ_I_U_VALUE_PLUS_331 1851086 // = 331 +#define IQ_I_U_VALUE_PLUS_332 1856678 // = 332 +#define IQ_I_U_VALUE_PLUS_333 1862270 // = 333 +#define IQ_I_U_VALUE_PLUS_334 1867863 // = 334 +#define IQ_I_U_VALUE_PLUS_335 1873455 // = 335 +#define IQ_I_U_VALUE_PLUS_336 1879048 // = 336 +#define IQ_I_U_VALUE_PLUS_337 1884640 // = 337 +#define IQ_I_U_VALUE_PLUS_338 1890233 // = 338 +#define IQ_I_U_VALUE_PLUS_339 1895825 // = 339 +#define IQ_I_U_VALUE_PLUS_340 1901417 // = 340 +#define IQ_I_U_VALUE_PLUS_341 1907010 // = 341 +#define IQ_I_U_VALUE_PLUS_342 1912602 // = 342 +#define IQ_I_U_VALUE_PLUS_343 1918195 // = 343 +#define IQ_I_U_VALUE_PLUS_344 1923787 // = 344 +#define IQ_I_U_VALUE_PLUS_345 1929379 // = 345 +#define IQ_I_U_VALUE_PLUS_346 1934972 // = 346 +#define IQ_I_U_VALUE_PLUS_347 1940564 // = 347 +#define IQ_I_U_VALUE_PLUS_348 1946157 // = 348 +#define IQ_I_U_VALUE_PLUS_349 1951749 // = 349 +#define IQ_I_U_VALUE_PLUS_350 1957341 // = 350 +#define IQ_I_U_VALUE_PLUS_351 1962934 // = 351 +#define IQ_I_U_VALUE_PLUS_352 1968526 // = 352 +#define IQ_I_U_VALUE_PLUS_353 1974119 // = 353 +#define IQ_I_U_VALUE_PLUS_354 1979711 // = 354 +#define IQ_I_U_VALUE_PLUS_355 1985303 // = 355 +#define IQ_I_U_VALUE_PLUS_356 1990896 // = 356 +#define IQ_I_U_VALUE_PLUS_357 1996488 // = 357 +#define IQ_I_U_VALUE_PLUS_358 2002081 // = 358 +#define IQ_I_U_VALUE_PLUS_359 2007673 // = 359 +#define IQ_I_U_VALUE_PLUS_360 2013265 // = 360 +#define IQ_I_U_VALUE_PLUS_361 2018858 // = 361 +#define IQ_I_U_VALUE_PLUS_362 2024450 // = 362 +#define IQ_I_U_VALUE_PLUS_363 2030043 // = 363 +#define IQ_I_U_VALUE_PLUS_364 2035635 // = 364 +#define IQ_I_U_VALUE_PLUS_365 2041227 // = 365 +#define IQ_I_U_VALUE_PLUS_366 2046820 // = 366 +#define IQ_I_U_VALUE_PLUS_367 2052412 // = 367 +#define IQ_I_U_VALUE_PLUS_368 2058005 // = 368 +#define IQ_I_U_VALUE_PLUS_369 2063597 // = 369 +#define IQ_I_U_VALUE_PLUS_370 2069189 // = 370 +#define IQ_I_U_VALUE_PLUS_371 2074782 // = 371 +#define IQ_I_U_VALUE_PLUS_372 2080374 // = 372 +#define IQ_I_U_VALUE_PLUS_373 2085967 // = 373 +#define IQ_I_U_VALUE_PLUS_374 2091559 // = 374 +#define IQ_I_U_VALUE_PLUS_375 2097152 // = 375 +#define IQ_I_U_VALUE_PLUS_376 2102744 // = 376 +#define IQ_I_U_VALUE_PLUS_377 2108336 // = 377 +#define IQ_I_U_VALUE_PLUS_378 2113929 // = 378 +#define IQ_I_U_VALUE_PLUS_379 2119521 // = 379 +#define IQ_I_U_VALUE_PLUS_380 2125114 // = 380 +#define IQ_I_U_VALUE_PLUS_381 2130706 // = 381 +#define IQ_I_U_VALUE_PLUS_382 2136298 // = 382 +#define IQ_I_U_VALUE_PLUS_383 2141891 // = 383 +#define IQ_I_U_VALUE_PLUS_384 2147483 // = 384 +#define IQ_I_U_VALUE_PLUS_385 2153076 // = 385 +#define IQ_I_U_VALUE_PLUS_386 2158668 // = 386 +#define IQ_I_U_VALUE_PLUS_387 2164260 // = 387 +#define IQ_I_U_VALUE_PLUS_388 2169853 // = 388 +#define IQ_I_U_VALUE_PLUS_389 2175445 // = 389 +#define IQ_I_U_VALUE_PLUS_390 2181038 // = 390 +#define IQ_I_U_VALUE_PLUS_391 2186630 // = 391 +#define IQ_I_U_VALUE_PLUS_392 2192222 // = 392 +#define IQ_I_U_VALUE_PLUS_393 2197815 // = 393 +#define IQ_I_U_VALUE_PLUS_394 2203407 // = 394 +#define IQ_I_U_VALUE_PLUS_395 2209000 // = 395 +#define IQ_I_U_VALUE_PLUS_396 2214592 // = 396 +#define IQ_I_U_VALUE_PLUS_397 2220184 // = 397 +#define IQ_I_U_VALUE_PLUS_398 2225777 // = 398 +#define IQ_I_U_VALUE_PLUS_399 2231369 // = 399 +#define IQ_I_U_VALUE_PLUS_400 2236962 // = 400 +#define IQ_I_U_VALUE_PLUS_401 2242554 // = 401 +#define IQ_I_U_VALUE_PLUS_402 2248146 // = 402 +#define IQ_I_U_VALUE_PLUS_403 2253739 // = 403 +#define IQ_I_U_VALUE_PLUS_404 2259331 // = 404 +#define IQ_I_U_VALUE_PLUS_405 2264924 // = 405 +#define IQ_I_U_VALUE_PLUS_406 2270516 // = 406 +#define IQ_I_U_VALUE_PLUS_407 2276108 // = 407 +#define IQ_I_U_VALUE_PLUS_408 2281701 // = 408 +#define IQ_I_U_VALUE_PLUS_409 2287293 // = 409 +#define IQ_I_U_VALUE_PLUS_410 2292886 // = 410 +#define IQ_I_U_VALUE_PLUS_411 2298478 // = 411 +#define IQ_I_U_VALUE_PLUS_412 2304070 // = 412 +#define IQ_I_U_VALUE_PLUS_413 2309663 // = 413 +#define IQ_I_U_VALUE_PLUS_414 2315255 // = 414 +#define IQ_I_U_VALUE_PLUS_415 2320848 // = 415 +#define IQ_I_U_VALUE_PLUS_416 2326440 // = 416 +#define IQ_I_U_VALUE_PLUS_417 2332033 // = 417 +#define IQ_I_U_VALUE_PLUS_418 2337625 // = 418 +#define IQ_I_U_VALUE_PLUS_419 2343217 // = 419 +#define IQ_I_U_VALUE_PLUS_420 2348810 // = 420 +#define IQ_I_U_VALUE_PLUS_421 2354402 // = 421 +#define IQ_I_U_VALUE_PLUS_422 2359995 // = 422 +#define IQ_I_U_VALUE_PLUS_423 2365587 // = 423 +#define IQ_I_U_VALUE_PLUS_424 2371179 // = 424 +#define IQ_I_U_VALUE_PLUS_425 2376772 // = 425 +#define IQ_I_U_VALUE_PLUS_426 2382364 // = 426 +#define IQ_I_U_VALUE_PLUS_427 2387957 // = 427 +#define IQ_I_U_VALUE_PLUS_428 2393549 // = 428 +#define IQ_I_U_VALUE_PLUS_429 2399141 // = 429 +#define IQ_I_U_VALUE_PLUS_430 2404734 // = 430 +#define IQ_I_U_VALUE_PLUS_431 2410326 // = 431 +#define IQ_I_U_VALUE_PLUS_432 2415919 // = 432 +#define IQ_I_U_VALUE_PLUS_433 2421511 // = 433 +#define IQ_I_U_VALUE_PLUS_434 2427103 // = 434 +#define IQ_I_U_VALUE_PLUS_435 2432696 // = 435 +#define IQ_I_U_VALUE_PLUS_436 2438288 // = 436 +#define IQ_I_U_VALUE_PLUS_437 2443881 // = 437 +#define IQ_I_U_VALUE_PLUS_438 2449473 // = 438 +#define IQ_I_U_VALUE_PLUS_439 2455065 // = 439 +#define IQ_I_U_VALUE_PLUS_440 2460658 // = 440 +#define IQ_I_U_VALUE_PLUS_441 2466250 // = 441 +#define IQ_I_U_VALUE_PLUS_442 2471843 // = 442 +#define IQ_I_U_VALUE_PLUS_443 2477435 // = 443 +#define IQ_I_U_VALUE_PLUS_444 2483027 // = 444 +#define IQ_I_U_VALUE_PLUS_445 2488620 // = 445 +#define IQ_I_U_VALUE_PLUS_446 2494212 // = 446 +#define IQ_I_U_VALUE_PLUS_447 2499805 // = 447 +#define IQ_I_U_VALUE_PLUS_448 2505397 // = 448 +#define IQ_I_U_VALUE_PLUS_449 2510989 // = 449 +#define IQ_I_U_VALUE_PLUS_450 2516582 // = 450 +#define IQ_I_U_VALUE_PLUS_451 2522174 // = 451 +#define IQ_I_U_VALUE_PLUS_452 2527767 // = 452 +#define IQ_I_U_VALUE_PLUS_453 2533359 // = 453 +#define IQ_I_U_VALUE_PLUS_454 2538952 // = 454 +#define IQ_I_U_VALUE_PLUS_455 2544544 // = 455 +#define IQ_I_U_VALUE_PLUS_456 2550136 // = 456 +#define IQ_I_U_VALUE_PLUS_457 2555729 // = 457 +#define IQ_I_U_VALUE_PLUS_458 2561321 // = 458 +#define IQ_I_U_VALUE_PLUS_459 2566914 // = 459 +#define IQ_I_U_VALUE_PLUS_460 2572506 // = 460 +#define IQ_I_U_VALUE_PLUS_461 2578098 // = 461 +#define IQ_I_U_VALUE_PLUS_462 2583691 // = 462 +#define IQ_I_U_VALUE_PLUS_463 2589283 // = 463 +#define IQ_I_U_VALUE_PLUS_464 2594876 // = 464 +#define IQ_I_U_VALUE_PLUS_465 2600468 // = 465 +#define IQ_I_U_VALUE_PLUS_466 2606060 // = 466 +#define IQ_I_U_VALUE_PLUS_467 2611653 // = 467 +#define IQ_I_U_VALUE_PLUS_468 2617245 // = 468 +#define IQ_I_U_VALUE_PLUS_469 2622838 // = 469 +#define IQ_I_U_VALUE_PLUS_470 2628430 // = 470 +#define IQ_I_U_VALUE_PLUS_471 2634022 // = 471 +#define IQ_I_U_VALUE_PLUS_472 2639615 // = 472 +#define IQ_I_U_VALUE_PLUS_473 2645207 // = 473 +#define IQ_I_U_VALUE_PLUS_474 2650800 // = 474 +#define IQ_I_U_VALUE_PLUS_475 2656392 // = 475 +#define IQ_I_U_VALUE_PLUS_476 2661984 // = 476 +#define IQ_I_U_VALUE_PLUS_477 2667577 // = 477 +#define IQ_I_U_VALUE_PLUS_478 2673169 // = 478 +#define IQ_I_U_VALUE_PLUS_479 2678762 // = 479 +#define IQ_I_U_VALUE_PLUS_480 2684354 // = 480 +#define IQ_I_U_VALUE_PLUS_481 2689946 // = 481 +#define IQ_I_U_VALUE_PLUS_482 2695539 // = 482 +#define IQ_I_U_VALUE_PLUS_483 2701131 // = 483 +#define IQ_I_U_VALUE_PLUS_484 2706724 // = 484 +#define IQ_I_U_VALUE_PLUS_485 2712316 // = 485 +#define IQ_I_U_VALUE_PLUS_486 2717908 // = 486 +#define IQ_I_U_VALUE_PLUS_487 2723501 // = 487 +#define IQ_I_U_VALUE_PLUS_488 2729093 // = 488 +#define IQ_I_U_VALUE_PLUS_489 2734686 // = 489 +#define IQ_I_U_VALUE_PLUS_490 2740278 // = 490 +#define IQ_I_U_VALUE_PLUS_491 2745871 // = 491 +#define IQ_I_U_VALUE_PLUS_492 2751463 // = 492 +#define IQ_I_U_VALUE_PLUS_493 2757055 // = 493 +#define IQ_I_U_VALUE_PLUS_494 2762648 // = 494 +#define IQ_I_U_VALUE_PLUS_495 2768240 // = 495 +#define IQ_I_U_VALUE_PLUS_496 2773833 // = 496 +#define IQ_I_U_VALUE_PLUS_497 2779425 // = 497 +#define IQ_I_U_VALUE_PLUS_498 2785017 // = 498 +#define IQ_I_U_VALUE_PLUS_499 2790610 // = 499 +#define IQ_I_U_VALUE_PLUS_500 2796202 // = 500 +#define IQ_I_U_VALUE_PLUS_501 2801795 // = 501 +#define IQ_I_U_VALUE_PLUS_502 2807387 // = 502 +#define IQ_I_U_VALUE_PLUS_503 2812979 // = 503 +#define IQ_I_U_VALUE_PLUS_504 2818572 // = 504 +#define IQ_I_U_VALUE_PLUS_505 2824164 // = 505 +#define IQ_I_U_VALUE_PLUS_506 2829757 // = 506 +#define IQ_I_U_VALUE_PLUS_507 2835349 // = 507 +#define IQ_I_U_VALUE_PLUS_508 2840941 // = 508 +#define IQ_I_U_VALUE_PLUS_509 2846534 // = 509 +#define IQ_I_U_VALUE_PLUS_510 2852126 // = 510 +#define IQ_I_U_VALUE_PLUS_511 2857719 // = 511 +#define IQ_I_U_VALUE_PLUS_512 2863311 // = 512 +#define IQ_I_U_VALUE_PLUS_513 2868903 // = 513 +#define IQ_I_U_VALUE_PLUS_514 2874496 // = 514 +#define IQ_I_U_VALUE_PLUS_515 2880088 // = 515 +#define IQ_I_U_VALUE_PLUS_516 2885681 // = 516 +#define IQ_I_U_VALUE_PLUS_517 2891273 // = 517 +#define IQ_I_U_VALUE_PLUS_518 2896865 // = 518 +#define IQ_I_U_VALUE_PLUS_519 2902458 // = 519 +#define IQ_I_U_VALUE_PLUS_520 2908050 // = 520 +#define IQ_I_U_VALUE_PLUS_521 2913643 // = 521 +#define IQ_I_U_VALUE_PLUS_522 2919235 // = 522 +#define IQ_I_U_VALUE_PLUS_523 2924827 // = 523 +#define IQ_I_U_VALUE_PLUS_524 2930420 // = 524 +#define IQ_I_U_VALUE_PLUS_525 2936012 // = 525 +#define IQ_I_U_VALUE_PLUS_526 2941605 // = 526 +#define IQ_I_U_VALUE_PLUS_527 2947197 // = 527 +#define IQ_I_U_VALUE_PLUS_528 2952790 // = 528 +#define IQ_I_U_VALUE_PLUS_529 2958382 // = 529 +#define IQ_I_U_VALUE_PLUS_530 2963974 // = 530 +#define IQ_I_U_VALUE_PLUS_531 2969567 // = 531 +#define IQ_I_U_VALUE_PLUS_532 2975159 // = 532 +#define IQ_I_U_VALUE_PLUS_533 2980752 // = 533 +#define IQ_I_U_VALUE_PLUS_534 2986344 // = 534 +#define IQ_I_U_VALUE_PLUS_535 2991936 // = 535 +#define IQ_I_U_VALUE_PLUS_536 2997529 // = 536 +#define IQ_I_U_VALUE_PLUS_537 3003121 // = 537 +#define IQ_I_U_VALUE_PLUS_538 3008714 // = 538 +#define IQ_I_U_VALUE_PLUS_539 3014306 // = 539 +#define IQ_I_U_VALUE_PLUS_540 3019898 // = 540 +#define IQ_I_U_VALUE_PLUS_541 3025491 // = 541 +#define IQ_I_U_VALUE_PLUS_542 3031083 // = 542 +#define IQ_I_U_VALUE_PLUS_543 3036676 // = 543 +#define IQ_I_U_VALUE_PLUS_544 3042268 // = 544 +#define IQ_I_U_VALUE_PLUS_545 3047860 // = 545 +#define IQ_I_U_VALUE_PLUS_546 3053453 // = 546 +#define IQ_I_U_VALUE_PLUS_547 3059045 // = 547 +#define IQ_I_U_VALUE_PLUS_548 3064638 // = 548 +#define IQ_I_U_VALUE_PLUS_549 3070230 // = 549 +#define IQ_I_U_VALUE_PLUS_550 3075822 // = 550 +#define IQ_I_U_VALUE_PLUS_551 3081415 // = 551 +#define IQ_I_U_VALUE_PLUS_552 3087007 // = 552 +#define IQ_I_U_VALUE_PLUS_553 3092600 // = 553 +#define IQ_I_U_VALUE_PLUS_554 3098192 // = 554 +#define IQ_I_U_VALUE_PLUS_555 3103784 // = 555 +#define IQ_I_U_VALUE_PLUS_556 3109377 // = 556 +#define IQ_I_U_VALUE_PLUS_557 3114969 // = 557 +#define IQ_I_U_VALUE_PLUS_558 3120562 // = 558 +#define IQ_I_U_VALUE_PLUS_559 3126154 // = 559 +#define IQ_I_U_VALUE_PLUS_560 3131746 // = 560 +#define IQ_I_U_VALUE_PLUS_561 3137339 // = 561 +#define IQ_I_U_VALUE_PLUS_562 3142931 // = 562 +#define IQ_I_U_VALUE_PLUS_563 3148524 // = 563 +#define IQ_I_U_VALUE_PLUS_564 3154116 // = 564 +#define IQ_I_U_VALUE_PLUS_565 3159709 // = 565 +#define IQ_I_U_VALUE_PLUS_566 3165301 // = 566 +#define IQ_I_U_VALUE_PLUS_567 3170893 // = 567 +#define IQ_I_U_VALUE_PLUS_568 3176486 // = 568 +#define IQ_I_U_VALUE_PLUS_569 3182078 // = 569 +#define IQ_I_U_VALUE_PLUS_570 3187671 // = 570 +#define IQ_I_U_VALUE_PLUS_571 3193263 // = 571 +#define IQ_I_U_VALUE_PLUS_572 3198855 // = 572 +#define IQ_I_U_VALUE_PLUS_573 3204448 // = 573 +#define IQ_I_U_VALUE_PLUS_574 3210040 // = 574 +#define IQ_I_U_VALUE_PLUS_575 3215633 // = 575 +#define IQ_I_U_VALUE_PLUS_576 3221225 // = 576 +#define IQ_I_U_VALUE_PLUS_577 3226817 // = 577 +#define IQ_I_U_VALUE_PLUS_578 3232410 // = 578 +#define IQ_I_U_VALUE_PLUS_579 3238002 // = 579 +#define IQ_I_U_VALUE_PLUS_580 3243595 // = 580 +#define IQ_I_U_VALUE_PLUS_581 3249187 // = 581 +#define IQ_I_U_VALUE_PLUS_582 3254779 // = 582 +#define IQ_I_U_VALUE_PLUS_583 3260372 // = 583 +#define IQ_I_U_VALUE_PLUS_584 3265964 // = 584 +#define IQ_I_U_VALUE_PLUS_585 3271557 // = 585 +#define IQ_I_U_VALUE_PLUS_586 3277149 // = 586 +#define IQ_I_U_VALUE_PLUS_587 3282741 // = 587 +#define IQ_I_U_VALUE_PLUS_588 3288334 // = 588 +#define IQ_I_U_VALUE_PLUS_589 3293926 // = 589 +#define IQ_I_U_VALUE_PLUS_590 3299519 // = 590 +#define IQ_I_U_VALUE_PLUS_591 3305111 // = 591 +#define IQ_I_U_VALUE_PLUS_592 3310703 // = 592 +#define IQ_I_U_VALUE_PLUS_593 3316296 // = 593 +#define IQ_I_U_VALUE_PLUS_594 3321888 // = 594 +#define IQ_I_U_VALUE_PLUS_595 3327481 // = 595 +#define IQ_I_U_VALUE_PLUS_596 3333073 // = 596 +#define IQ_I_U_VALUE_PLUS_597 3338665 // = 597 +#define IQ_I_U_VALUE_PLUS_598 3344258 // = 598 +#define IQ_I_U_VALUE_PLUS_599 3349850 // = 599 +#define IQ_I_U_VALUE_PLUS_600 3355443 // = 600 +#define IQ_I_U_VALUE_PLUS_601 3361035 // = 601 +#define IQ_I_U_VALUE_PLUS_602 3366628 // = 602 +#define IQ_I_U_VALUE_PLUS_603 3372220 // = 603 +#define IQ_I_U_VALUE_PLUS_604 3377812 // = 604 +#define IQ_I_U_VALUE_PLUS_605 3383405 // = 605 +#define IQ_I_U_VALUE_PLUS_606 3388997 // = 606 +#define IQ_I_U_VALUE_PLUS_607 3394590 // = 607 +#define IQ_I_U_VALUE_PLUS_608 3400182 // = 608 +#define IQ_I_U_VALUE_PLUS_609 3405774 // = 609 +#define IQ_I_U_VALUE_PLUS_610 3411367 // = 610 +#define IQ_I_U_VALUE_PLUS_611 3416959 // = 611 +#define IQ_I_U_VALUE_PLUS_612 3422552 // = 612 +#define IQ_I_U_VALUE_PLUS_613 3428144 // = 613 +#define IQ_I_U_VALUE_PLUS_614 3433736 // = 614 +#define IQ_I_U_VALUE_PLUS_615 3439329 // = 615 +#define IQ_I_U_VALUE_PLUS_616 3444921 // = 616 +#define IQ_I_U_VALUE_PLUS_617 3450514 // = 617 +#define IQ_I_U_VALUE_PLUS_618 3456106 // = 618 +#define IQ_I_U_VALUE_PLUS_619 3461698 // = 619 +#define IQ_I_U_VALUE_PLUS_620 3467291 // = 620 +#define IQ_I_U_VALUE_PLUS_621 3472883 // = 621 +#define IQ_I_U_VALUE_PLUS_622 3478476 // = 622 +#define IQ_I_U_VALUE_PLUS_623 3484068 // = 623 +#define IQ_I_U_VALUE_PLUS_624 3489660 // = 624 +#define IQ_I_U_VALUE_PLUS_625 3495253 // = 625 +#define IQ_I_U_VALUE_PLUS_626 3500845 // = 626 +#define IQ_I_U_VALUE_PLUS_627 3506438 // = 627 +#define IQ_I_U_VALUE_PLUS_628 3512030 // = 628 +#define IQ_I_U_VALUE_PLUS_629 3517622 // = 629 +#define IQ_I_U_VALUE_PLUS_630 3523215 // = 630 +#define IQ_I_U_VALUE_PLUS_631 3528807 // = 631 +#define IQ_I_U_VALUE_PLUS_632 3534400 // = 632 +#define IQ_I_U_VALUE_PLUS_633 3539992 // = 633 +#define IQ_I_U_VALUE_PLUS_634 3545584 // = 634 +#define IQ_I_U_VALUE_PLUS_635 3551177 // = 635 +#define IQ_I_U_VALUE_PLUS_636 3556769 // = 636 +#define IQ_I_U_VALUE_PLUS_637 3562362 // = 637 +#define IQ_I_U_VALUE_PLUS_638 3567954 // = 638 +#define IQ_I_U_VALUE_PLUS_639 3573547 // = 639 +#define IQ_I_U_VALUE_PLUS_640 3579139 // = 640 +#define IQ_I_U_VALUE_PLUS_641 3584731 // = 641 +#define IQ_I_U_VALUE_PLUS_642 3590324 // = 642 +#define IQ_I_U_VALUE_PLUS_643 3595916 // = 643 +#define IQ_I_U_VALUE_PLUS_644 3601509 // = 644 +#define IQ_I_U_VALUE_PLUS_645 3607101 // = 645 +#define IQ_I_U_VALUE_PLUS_646 3612693 // = 646 +#define IQ_I_U_VALUE_PLUS_647 3618286 // = 647 +#define IQ_I_U_VALUE_PLUS_648 3623878 // = 648 +#define IQ_I_U_VALUE_PLUS_649 3629471 // = 649 +#define IQ_I_U_VALUE_PLUS_650 3635063 // = 650 +#define IQ_I_U_VALUE_PLUS_651 3640655 // = 651 +#define IQ_I_U_VALUE_PLUS_652 3646248 // = 652 +#define IQ_I_U_VALUE_PLUS_653 3651840 // = 653 +#define IQ_I_U_VALUE_PLUS_654 3657433 // = 654 +#define IQ_I_U_VALUE_PLUS_655 3663025 // = 655 +#define IQ_I_U_VALUE_PLUS_656 3668617 // = 656 +#define IQ_I_U_VALUE_PLUS_657 3674210 // = 657 +#define IQ_I_U_VALUE_PLUS_658 3679802 // = 658 +#define IQ_I_U_VALUE_PLUS_659 3685395 // = 659 +#define IQ_I_U_VALUE_PLUS_660 3690987 // = 660 +#define IQ_I_U_VALUE_PLUS_661 3696579 // = 661 +#define IQ_I_U_VALUE_PLUS_662 3702172 // = 662 +#define IQ_I_U_VALUE_PLUS_663 3707764 // = 663 +#define IQ_I_U_VALUE_PLUS_664 3713357 // = 664 +#define IQ_I_U_VALUE_PLUS_665 3718949 // = 665 +#define IQ_I_U_VALUE_PLUS_666 3724541 // = 666 +#define IQ_I_U_VALUE_PLUS_667 3730134 // = 667 +#define IQ_I_U_VALUE_PLUS_668 3735726 // = 668 +#define IQ_I_U_VALUE_PLUS_669 3741319 // = 669 +#define IQ_I_U_VALUE_PLUS_670 3746911 // = 670 +#define IQ_I_U_VALUE_PLUS_671 3752503 // = 671 +#define IQ_I_U_VALUE_PLUS_672 3758096 // = 672 +#define IQ_I_U_VALUE_PLUS_673 3763688 // = 673 +#define IQ_I_U_VALUE_PLUS_674 3769281 // = 674 +#define IQ_I_U_VALUE_PLUS_675 3774873 // = 675 +#define IQ_I_U_VALUE_PLUS_676 3780466 // = 676 +#define IQ_I_U_VALUE_PLUS_677 3786058 // = 677 +#define IQ_I_U_VALUE_PLUS_678 3791650 // = 678 +#define IQ_I_U_VALUE_PLUS_679 3797243 // = 679 +#define IQ_I_U_VALUE_PLUS_680 3802835 // = 680 +#define IQ_I_U_VALUE_PLUS_681 3808428 // = 681 +#define IQ_I_U_VALUE_PLUS_682 3814020 // = 682 +#define IQ_I_U_VALUE_PLUS_683 3819612 // = 683 +#define IQ_I_U_VALUE_PLUS_684 3825205 // = 684 +#define IQ_I_U_VALUE_PLUS_685 3830797 // = 685 +#define IQ_I_U_VALUE_PLUS_686 3836390 // = 686 +#define IQ_I_U_VALUE_PLUS_687 3841982 // = 687 +#define IQ_I_U_VALUE_PLUS_688 3847574 // = 688 +#define IQ_I_U_VALUE_PLUS_689 3853167 // = 689 +#define IQ_I_U_VALUE_PLUS_690 3858759 // = 690 +#define IQ_I_U_VALUE_PLUS_691 3864352 // = 691 +#define IQ_I_U_VALUE_PLUS_692 3869944 // = 692 +#define IQ_I_U_VALUE_PLUS_693 3875536 // = 693 +#define IQ_I_U_VALUE_PLUS_694 3881129 // = 694 +#define IQ_I_U_VALUE_PLUS_695 3886721 // = 695 +#define IQ_I_U_VALUE_PLUS_696 3892314 // = 696 +#define IQ_I_U_VALUE_PLUS_697 3897906 // = 697 +#define IQ_I_U_VALUE_PLUS_698 3903498 // = 698 +#define IQ_I_U_VALUE_PLUS_699 3909091 // = 699 +#define IQ_I_U_VALUE_PLUS_700 3914683 // = 700 +#define IQ_I_U_VALUE_PLUS_701 3920276 // = 701 +#define IQ_I_U_VALUE_PLUS_702 3925868 // = 702 +#define IQ_I_U_VALUE_PLUS_703 3931460 // = 703 +#define IQ_I_U_VALUE_PLUS_704 3937053 // = 704 +#define IQ_I_U_VALUE_PLUS_705 3942645 // = 705 +#define IQ_I_U_VALUE_PLUS_706 3948238 // = 706 +#define IQ_I_U_VALUE_PLUS_707 3953830 // = 707 +#define IQ_I_U_VALUE_PLUS_708 3959422 // = 708 +#define IQ_I_U_VALUE_PLUS_709 3965015 // = 709 +#define IQ_I_U_VALUE_PLUS_710 3970607 // = 710 +#define IQ_I_U_VALUE_PLUS_711 3976200 // = 711 +#define IQ_I_U_VALUE_PLUS_712 3981792 // = 712 +#define IQ_I_U_VALUE_PLUS_713 3987385 // = 713 +#define IQ_I_U_VALUE_PLUS_714 3992977 // = 714 +#define IQ_I_U_VALUE_PLUS_715 3998569 // = 715 +#define IQ_I_U_VALUE_PLUS_716 4004162 // = 716 +#define IQ_I_U_VALUE_PLUS_717 4009754 // = 717 +#define IQ_I_U_VALUE_PLUS_718 4015347 // = 718 +#define IQ_I_U_VALUE_PLUS_719 4020939 // = 719 +#define IQ_I_U_VALUE_PLUS_720 4026531 // = 720 +#define IQ_I_U_VALUE_PLUS_721 4032124 // = 721 +#define IQ_I_U_VALUE_PLUS_722 4037716 // = 722 +#define IQ_I_U_VALUE_PLUS_723 4043309 // = 723 +#define IQ_I_U_VALUE_PLUS_724 4048901 // = 724 +#define IQ_I_U_VALUE_PLUS_725 4054493 // = 725 +#define IQ_I_U_VALUE_PLUS_726 4060086 // = 726 +#define IQ_I_U_VALUE_PLUS_727 4065678 // = 727 +#define IQ_I_U_VALUE_PLUS_728 4071271 // = 728 +#define IQ_I_U_VALUE_PLUS_729 4076863 // = 729 +#define IQ_I_U_VALUE_PLUS_730 4082455 // = 730 +#define IQ_I_U_VALUE_PLUS_731 4088048 // = 731 +#define IQ_I_U_VALUE_PLUS_732 4093640 // = 732 +#define IQ_I_U_VALUE_PLUS_733 4099233 // = 733 +#define IQ_I_U_VALUE_PLUS_734 4104825 // = 734 +#define IQ_I_U_VALUE_PLUS_735 4110417 // = 735 +#define IQ_I_U_VALUE_PLUS_736 4116010 // = 736 +#define IQ_I_U_VALUE_PLUS_737 4121602 // = 737 +#define IQ_I_U_VALUE_PLUS_738 4127195 // = 738 +#define IQ_I_U_VALUE_PLUS_739 4132787 // = 739 +#define IQ_I_U_VALUE_PLUS_740 4138379 // = 740 +#define IQ_I_U_VALUE_PLUS_741 4143972 // = 741 +#define IQ_I_U_VALUE_PLUS_742 4149564 // = 742 +#define IQ_I_U_VALUE_PLUS_743 4155157 // = 743 +#define IQ_I_U_VALUE_PLUS_744 4160749 // = 744 +#define IQ_I_U_VALUE_PLUS_745 4166341 // = 745 +#define IQ_I_U_VALUE_PLUS_746 4171934 // = 746 +#define IQ_I_U_VALUE_PLUS_747 4177526 // = 747 +#define IQ_I_U_VALUE_PLUS_748 4183119 // = 748 +#define IQ_I_U_VALUE_PLUS_749 4188711 // = 749 +#define IQ_I_U_VALUE_PLUS_750 4194304 // = 750 +#define IQ_I_U_VALUE_PLUS_751 4199896 // = 751 +#define IQ_I_U_VALUE_PLUS_752 4205488 // = 752 +#define IQ_I_U_VALUE_PLUS_753 4211081 // = 753 +#define IQ_I_U_VALUE_PLUS_754 4216673 // = 754 +#define IQ_I_U_VALUE_PLUS_755 4222266 // = 755 +#define IQ_I_U_VALUE_PLUS_756 4227858 // = 756 +#define IQ_I_U_VALUE_PLUS_757 4233450 // = 757 +#define IQ_I_U_VALUE_PLUS_758 4239043 // = 758 +#define IQ_I_U_VALUE_PLUS_759 4244635 // = 759 +#define IQ_I_U_VALUE_PLUS_760 4250228 // = 760 +#define IQ_I_U_VALUE_PLUS_761 4255820 // = 761 +#define IQ_I_U_VALUE_PLUS_762 4261412 // = 762 +#define IQ_I_U_VALUE_PLUS_763 4267005 // = 763 +#define IQ_I_U_VALUE_PLUS_764 4272597 // = 764 +#define IQ_I_U_VALUE_PLUS_765 4278190 // = 765 +#define IQ_I_U_VALUE_PLUS_766 4283782 // = 766 +#define IQ_I_U_VALUE_PLUS_767 4289374 // = 767 +#define IQ_I_U_VALUE_PLUS_768 4294967 // = 768 +#define IQ_I_U_VALUE_PLUS_769 4300559 // = 769 +#define IQ_I_U_VALUE_PLUS_770 4306152 // = 770 +#define IQ_I_U_VALUE_PLUS_771 4311744 // = 771 +#define IQ_I_U_VALUE_PLUS_772 4317336 // = 772 +#define IQ_I_U_VALUE_PLUS_773 4322929 // = 773 +#define IQ_I_U_VALUE_PLUS_774 4328521 // = 774 +#define IQ_I_U_VALUE_PLUS_775 4334114 // = 775 +#define IQ_I_U_VALUE_PLUS_776 4339706 // = 776 +#define IQ_I_U_VALUE_PLUS_777 4345298 // = 777 +#define IQ_I_U_VALUE_PLUS_778 4350891 // = 778 +#define IQ_I_U_VALUE_PLUS_779 4356483 // = 779 +#define IQ_I_U_VALUE_PLUS_780 4362076 // = 780 +#define IQ_I_U_VALUE_PLUS_781 4367668 // = 781 +#define IQ_I_U_VALUE_PLUS_782 4373260 // = 782 +#define IQ_I_U_VALUE_PLUS_783 4378853 // = 783 +#define IQ_I_U_VALUE_PLUS_784 4384445 // = 784 +#define IQ_I_U_VALUE_PLUS_785 4390038 // = 785 +#define IQ_I_U_VALUE_PLUS_786 4395630 // = 786 +#define IQ_I_U_VALUE_PLUS_787 4401222 // = 787 +#define IQ_I_U_VALUE_PLUS_788 4406815 // = 788 +#define IQ_I_U_VALUE_PLUS_789 4412407 // = 789 +#define IQ_I_U_VALUE_PLUS_790 4418000 // = 790 +#define IQ_I_U_VALUE_PLUS_791 4423592 // = 791 +#define IQ_I_U_VALUE_PLUS_792 4429185 // = 792 +#define IQ_I_U_VALUE_PLUS_793 4434777 // = 793 +#define IQ_I_U_VALUE_PLUS_794 4440369 // = 794 +#define IQ_I_U_VALUE_PLUS_795 4445962 // = 795 +#define IQ_I_U_VALUE_PLUS_796 4451554 // = 796 +#define IQ_I_U_VALUE_PLUS_797 4457147 // = 797 +#define IQ_I_U_VALUE_PLUS_798 4462739 // = 798 +#define IQ_I_U_VALUE_PLUS_799 4468331 // = 799 +#define IQ_I_U_VALUE_PLUS_800 4473924 // = 800 +#define IQ_I_U_VALUE_PLUS_801 4479516 // = 801 +#define IQ_I_U_VALUE_PLUS_802 4485109 // = 802 +#define IQ_I_U_VALUE_PLUS_803 4490701 // = 803 +#define IQ_I_U_VALUE_PLUS_804 4496293 // = 804 +#define IQ_I_U_VALUE_PLUS_805 4501886 // = 805 +#define IQ_I_U_VALUE_PLUS_806 4507478 // = 806 +#define IQ_I_U_VALUE_PLUS_807 4513071 // = 807 +#define IQ_I_U_VALUE_PLUS_808 4518663 // = 808 +#define IQ_I_U_VALUE_PLUS_809 4524255 // = 809 +#define IQ_I_U_VALUE_PLUS_810 4529848 // = 810 +#define IQ_I_U_VALUE_PLUS_811 4535440 // = 811 +#define IQ_I_U_VALUE_PLUS_812 4541033 // = 812 +#define IQ_I_U_VALUE_PLUS_813 4546625 // = 813 +#define IQ_I_U_VALUE_PLUS_814 4552217 // = 814 +#define IQ_I_U_VALUE_PLUS_815 4557810 // = 815 +#define IQ_I_U_VALUE_PLUS_816 4563402 // = 816 +#define IQ_I_U_VALUE_PLUS_817 4568995 // = 817 +#define IQ_I_U_VALUE_PLUS_818 4574587 // = 818 +#define IQ_I_U_VALUE_PLUS_819 4580179 // = 819 +#define IQ_I_U_VALUE_PLUS_820 4585772 // = 820 +#define IQ_I_U_VALUE_PLUS_821 4591364 // = 821 +#define IQ_I_U_VALUE_PLUS_822 4596957 // = 822 +#define IQ_I_U_VALUE_PLUS_823 4602549 // = 823 +#define IQ_I_U_VALUE_PLUS_824 4608141 // = 824 +#define IQ_I_U_VALUE_PLUS_825 4613734 // = 825 +#define IQ_I_U_VALUE_PLUS_826 4619326 // = 826 +#define IQ_I_U_VALUE_PLUS_827 4624919 // = 827 +#define IQ_I_U_VALUE_PLUS_828 4630511 // = 828 +#define IQ_I_U_VALUE_PLUS_829 4636104 // = 829 +#define IQ_I_U_VALUE_PLUS_830 4641696 // = 830 +#define IQ_I_U_VALUE_PLUS_831 4647288 // = 831 +#define IQ_I_U_VALUE_PLUS_832 4652881 // = 832 +#define IQ_I_U_VALUE_PLUS_833 4658473 // = 833 +#define IQ_I_U_VALUE_PLUS_834 4664066 // = 834 +#define IQ_I_U_VALUE_PLUS_835 4669658 // = 835 +#define IQ_I_U_VALUE_PLUS_836 4675250 // = 836 +#define IQ_I_U_VALUE_PLUS_837 4680843 // = 837 +#define IQ_I_U_VALUE_PLUS_838 4686435 // = 838 +#define IQ_I_U_VALUE_PLUS_839 4692028 // = 839 +#define IQ_I_U_VALUE_PLUS_840 4697620 // = 840 +#define IQ_I_U_VALUE_PLUS_841 4703212 // = 841 +#define IQ_I_U_VALUE_PLUS_842 4708805 // = 842 +#define IQ_I_U_VALUE_PLUS_843 4714397 // = 843 +#define IQ_I_U_VALUE_PLUS_844 4719990 // = 844 +#define IQ_I_U_VALUE_PLUS_845 4725582 // = 845 +#define IQ_I_U_VALUE_PLUS_846 4731174 // = 846 +#define IQ_I_U_VALUE_PLUS_847 4736767 // = 847 +#define IQ_I_U_VALUE_PLUS_848 4742359 // = 848 +#define IQ_I_U_VALUE_PLUS_849 4747952 // = 849 +#define IQ_I_U_VALUE_PLUS_850 4753544 // = 850 +#define IQ_I_U_VALUE_PLUS_851 4759136 // = 851 +#define IQ_I_U_VALUE_PLUS_852 4764729 // = 852 +#define IQ_I_U_VALUE_PLUS_853 4770321 // = 853 +#define IQ_I_U_VALUE_PLUS_854 4775914 // = 854 +#define IQ_I_U_VALUE_PLUS_855 4781506 // = 855 +#define IQ_I_U_VALUE_PLUS_856 4787098 // = 856 +#define IQ_I_U_VALUE_PLUS_857 4792691 // = 857 +#define IQ_I_U_VALUE_PLUS_858 4798283 // = 858 +#define IQ_I_U_VALUE_PLUS_859 4803876 // = 859 +#define IQ_I_U_VALUE_PLUS_860 4809468 // = 860 +#define IQ_I_U_VALUE_PLUS_861 4815060 // = 861 +#define IQ_I_U_VALUE_PLUS_862 4820653 // = 862 +#define IQ_I_U_VALUE_PLUS_863 4826245 // = 863 +#define IQ_I_U_VALUE_PLUS_864 4831838 // = 864 +#define IQ_I_U_VALUE_PLUS_865 4837430 // = 865 +#define IQ_I_U_VALUE_PLUS_866 4843023 // = 866 +#define IQ_I_U_VALUE_PLUS_867 4848615 // = 867 +#define IQ_I_U_VALUE_PLUS_868 4854207 // = 868 +#define IQ_I_U_VALUE_PLUS_869 4859800 // = 869 +#define IQ_I_U_VALUE_PLUS_870 4865392 // = 870 +#define IQ_I_U_VALUE_PLUS_871 4870985 // = 871 +#define IQ_I_U_VALUE_PLUS_872 4876577 // = 872 +#define IQ_I_U_VALUE_PLUS_873 4882169 // = 873 +#define IQ_I_U_VALUE_PLUS_874 4887762 // = 874 +#define IQ_I_U_VALUE_PLUS_875 4893354 // = 875 +#define IQ_I_U_VALUE_PLUS_876 4898947 // = 876 +#define IQ_I_U_VALUE_PLUS_877 4904539 // = 877 +#define IQ_I_U_VALUE_PLUS_878 4910131 // = 878 +#define IQ_I_U_VALUE_PLUS_879 4915724 // = 879 +#define IQ_I_U_VALUE_PLUS_880 4921316 // = 880 +#define IQ_I_U_VALUE_PLUS_881 4926909 // = 881 +#define IQ_I_U_VALUE_PLUS_882 4932501 // = 882 +#define IQ_I_U_VALUE_PLUS_883 4938093 // = 883 +#define IQ_I_U_VALUE_PLUS_884 4943686 // = 884 +#define IQ_I_U_VALUE_PLUS_885 4949278 // = 885 +#define IQ_I_U_VALUE_PLUS_886 4954871 // = 886 +#define IQ_I_U_VALUE_PLUS_887 4960463 // = 887 +#define IQ_I_U_VALUE_PLUS_888 4966055 // = 888 +#define IQ_I_U_VALUE_PLUS_889 4971648 // = 889 +#define IQ_I_U_VALUE_PLUS_890 4977240 // = 890 +#define IQ_I_U_VALUE_PLUS_891 4982833 // = 891 +#define IQ_I_U_VALUE_PLUS_892 4988425 // = 892 +#define IQ_I_U_VALUE_PLUS_893 4994017 // = 893 +#define IQ_I_U_VALUE_PLUS_894 4999610 // = 894 +#define IQ_I_U_VALUE_PLUS_895 5005202 // = 895 +#define IQ_I_U_VALUE_PLUS_896 5010795 // = 896 +#define IQ_I_U_VALUE_PLUS_897 5016387 // = 897 +#define IQ_I_U_VALUE_PLUS_898 5021979 // = 898 +#define IQ_I_U_VALUE_PLUS_899 5027572 // = 899 +#define IQ_I_U_VALUE_PLUS_900 5033164 // = 900 +#define IQ_I_U_VALUE_PLUS_901 5038757 // = 901 +#define IQ_I_U_VALUE_PLUS_902 5044349 // = 902 +#define IQ_I_U_VALUE_PLUS_903 5049942 // = 903 +#define IQ_I_U_VALUE_PLUS_904 5055534 // = 904 +#define IQ_I_U_VALUE_PLUS_905 5061126 // = 905 +#define IQ_I_U_VALUE_PLUS_906 5066719 // = 906 +#define IQ_I_U_VALUE_PLUS_907 5072311 // = 907 +#define IQ_I_U_VALUE_PLUS_908 5077904 // = 908 +#define IQ_I_U_VALUE_PLUS_909 5083496 // = 909 +#define IQ_I_U_VALUE_PLUS_910 5089088 // = 910 +#define IQ_I_U_VALUE_PLUS_911 5094681 // = 911 +#define IQ_I_U_VALUE_PLUS_912 5100273 // = 912 +#define IQ_I_U_VALUE_PLUS_913 5105866 // = 913 +#define IQ_I_U_VALUE_PLUS_914 5111458 // = 914 +#define IQ_I_U_VALUE_PLUS_915 5117050 // = 915 +#define IQ_I_U_VALUE_PLUS_916 5122643 // = 916 +#define IQ_I_U_VALUE_PLUS_917 5128235 // = 917 +#define IQ_I_U_VALUE_PLUS_918 5133828 // = 918 +#define IQ_I_U_VALUE_PLUS_919 5139420 // = 919 +#define IQ_I_U_VALUE_PLUS_920 5145012 // = 920 +#define IQ_I_U_VALUE_PLUS_921 5150605 // = 921 +#define IQ_I_U_VALUE_PLUS_922 5156197 // = 922 +#define IQ_I_U_VALUE_PLUS_923 5161790 // = 923 +#define IQ_I_U_VALUE_PLUS_924 5167382 // = 924 +#define IQ_I_U_VALUE_PLUS_925 5172974 // = 925 +#define IQ_I_U_VALUE_PLUS_926 5178567 // = 926 +#define IQ_I_U_VALUE_PLUS_927 5184159 // = 927 +#define IQ_I_U_VALUE_PLUS_928 5189752 // = 928 +#define IQ_I_U_VALUE_PLUS_929 5195344 // = 929 +#define IQ_I_U_VALUE_PLUS_930 5200936 // = 930 +#define IQ_I_U_VALUE_PLUS_931 5206529 // = 931 +#define IQ_I_U_VALUE_PLUS_932 5212121 // = 932 +#define IQ_I_U_VALUE_PLUS_933 5217714 // = 933 +#define IQ_I_U_VALUE_PLUS_934 5223306 // = 934 +#define IQ_I_U_VALUE_PLUS_935 5228898 // = 935 +#define IQ_I_U_VALUE_PLUS_936 5234491 // = 936 +#define IQ_I_U_VALUE_PLUS_937 5240083 // = 937 +#define IQ_I_U_VALUE_PLUS_938 5245676 // = 938 +#define IQ_I_U_VALUE_PLUS_939 5251268 // = 939 +#define IQ_I_U_VALUE_PLUS_940 5256861 // = 940 +#define IQ_I_U_VALUE_PLUS_941 5262453 // = 941 +#define IQ_I_U_VALUE_PLUS_942 5268045 // = 942 +#define IQ_I_U_VALUE_PLUS_943 5273638 // = 943 +#define IQ_I_U_VALUE_PLUS_944 5279230 // = 944 +#define IQ_I_U_VALUE_PLUS_945 5284823 // = 945 +#define IQ_I_U_VALUE_PLUS_946 5290415 // = 946 +#define IQ_I_U_VALUE_PLUS_947 5296007 // = 947 +#define IQ_I_U_VALUE_PLUS_948 5301600 // = 948 +#define IQ_I_U_VALUE_PLUS_949 5307192 // = 949 +#define IQ_I_U_VALUE_PLUS_950 5312785 // = 950 +#define IQ_I_U_VALUE_PLUS_951 5318377 // = 951 +#define IQ_I_U_VALUE_PLUS_952 5323969 // = 952 +#define IQ_I_U_VALUE_PLUS_953 5329562 // = 953 +#define IQ_I_U_VALUE_PLUS_954 5335154 // = 954 +#define IQ_I_U_VALUE_PLUS_955 5340747 // = 955 +#define IQ_I_U_VALUE_PLUS_956 5346339 // = 956 +#define IQ_I_U_VALUE_PLUS_957 5351931 // = 957 +#define IQ_I_U_VALUE_PLUS_958 5357524 // = 958 +#define IQ_I_U_VALUE_PLUS_959 5363116 // = 959 +#define IQ_I_U_VALUE_PLUS_960 5368709 // = 960 +#define IQ_I_U_VALUE_PLUS_961 5374301 // = 961 +#define IQ_I_U_VALUE_PLUS_962 5379893 // = 962 +#define IQ_I_U_VALUE_PLUS_963 5385486 // = 963 +#define IQ_I_U_VALUE_PLUS_964 5391078 // = 964 +#define IQ_I_U_VALUE_PLUS_965 5396671 // = 965 +#define IQ_I_U_VALUE_PLUS_966 5402263 // = 966 +#define IQ_I_U_VALUE_PLUS_967 5407855 // = 967 +#define IQ_I_U_VALUE_PLUS_968 5413448 // = 968 +#define IQ_I_U_VALUE_PLUS_969 5419040 // = 969 +#define IQ_I_U_VALUE_PLUS_970 5424633 // = 970 +#define IQ_I_U_VALUE_PLUS_971 5430225 // = 971 +#define IQ_I_U_VALUE_PLUS_972 5435817 // = 972 +#define IQ_I_U_VALUE_PLUS_973 5441410 // = 973 +#define IQ_I_U_VALUE_PLUS_974 5447002 // = 974 +#define IQ_I_U_VALUE_PLUS_975 5452595 // = 975 +#define IQ_I_U_VALUE_PLUS_976 5458187 // = 976 +#define IQ_I_U_VALUE_PLUS_977 5463780 // = 977 +#define IQ_I_U_VALUE_PLUS_978 5469372 // = 978 +#define IQ_I_U_VALUE_PLUS_979 5474964 // = 979 +#define IQ_I_U_VALUE_PLUS_980 5480557 // = 980 +#define IQ_I_U_VALUE_PLUS_981 5486149 // = 981 +#define IQ_I_U_VALUE_PLUS_982 5491742 // = 982 +#define IQ_I_U_VALUE_PLUS_983 5497334 // = 983 +#define IQ_I_U_VALUE_PLUS_984 5502926 // = 984 +#define IQ_I_U_VALUE_PLUS_985 5508519 // = 985 +#define IQ_I_U_VALUE_PLUS_986 5514111 // = 986 +#define IQ_I_U_VALUE_PLUS_987 5519704 // = 987 +#define IQ_I_U_VALUE_PLUS_988 5525296 // = 988 +#define IQ_I_U_VALUE_PLUS_989 5530888 // = 989 +#define IQ_I_U_VALUE_PLUS_990 5536481 // = 990 +#define IQ_I_U_VALUE_PLUS_991 5542073 // = 991 +#define IQ_I_U_VALUE_PLUS_992 5547666 // = 992 +#define IQ_I_U_VALUE_PLUS_993 5553258 // = 993 +#define IQ_I_U_VALUE_PLUS_994 5558850 // = 994 +#define IQ_I_U_VALUE_PLUS_995 5564443 // = 995 +#define IQ_I_U_VALUE_PLUS_996 5570035 // = 996 +#define IQ_I_U_VALUE_PLUS_997 5575628 // = 997 +#define IQ_I_U_VALUE_PLUS_998 5581220 // = 998 +#define IQ_I_U_VALUE_PLUS_999 5586812 // = 999 +#define IQ_I_U_VALUE_PLUS_1000 5592405 // = 1000 +#define IQ_I_U_VALUE_PLUS_1001 5597997 // = 1001 +#define IQ_I_U_VALUE_PLUS_1002 5603590 // = 1002 +#define IQ_I_U_VALUE_PLUS_1003 5609182 // = 1003 +#define IQ_I_U_VALUE_PLUS_1004 5614774 // = 1004 +#define IQ_I_U_VALUE_PLUS_1005 5620367 // = 1005 +#define IQ_I_U_VALUE_PLUS_1006 5625959 // = 1006 +#define IQ_I_U_VALUE_PLUS_1007 5631552 // = 1007 +#define IQ_I_U_VALUE_PLUS_1008 5637144 // = 1008 +#define IQ_I_U_VALUE_PLUS_1009 5642736 // = 1009 +#define IQ_I_U_VALUE_PLUS_1010 5648329 // = 1010 +#define IQ_I_U_VALUE_PLUS_1011 5653921 // = 1011 +#define IQ_I_U_VALUE_PLUS_1012 5659514 // = 1012 +#define IQ_I_U_VALUE_PLUS_1013 5665106 // = 1013 +#define IQ_I_U_VALUE_PLUS_1014 5670699 // = 1014 +#define IQ_I_U_VALUE_PLUS_1015 5676291 // = 1015 +#define IQ_I_U_VALUE_PLUS_1016 5681883 // = 1016 +#define IQ_I_U_VALUE_PLUS_1017 5687476 // = 1017 +#define IQ_I_U_VALUE_PLUS_1018 5693068 // = 1018 +#define IQ_I_U_VALUE_PLUS_1019 5698661 // = 1019 +#define IQ_I_U_VALUE_PLUS_1020 5704253 // = 1020 +#define IQ_I_U_VALUE_PLUS_1021 5709845 // = 1021 +#define IQ_I_U_VALUE_PLUS_1022 5715438 // = 1022 +#define IQ_I_U_VALUE_PLUS_1023 5721030 // = 1023 +#define IQ_I_U_VALUE_PLUS_1024 5726623 // = 1024 +#define IQ_I_U_VALUE_PLUS_1025 5732215 // = 1025 +#define IQ_I_U_VALUE_PLUS_1026 5737807 // = 1026 +#define IQ_I_U_VALUE_PLUS_1027 5743400 // = 1027 +#define IQ_I_U_VALUE_PLUS_1028 5748992 // = 1028 +#define IQ_I_U_VALUE_PLUS_1029 5754585 // = 1029 +#define IQ_I_U_VALUE_PLUS_1030 5760177 // = 1030 +#define IQ_I_U_VALUE_PLUS_1031 5765769 // = 1031 +#define IQ_I_U_VALUE_PLUS_1032 5771362 // = 1032 +#define IQ_I_U_VALUE_PLUS_1033 5776954 // = 1033 +#define IQ_I_U_VALUE_PLUS_1034 5782547 // = 1034 +#define IQ_I_U_VALUE_PLUS_1035 5788139 // = 1035 +#define IQ_I_U_VALUE_PLUS_1036 5793731 // = 1036 +#define IQ_I_U_VALUE_PLUS_1037 5799324 // = 1037 +#define IQ_I_U_VALUE_PLUS_1038 5804916 // = 1038 +#define IQ_I_U_VALUE_PLUS_1039 5810509 // = 1039 +#define IQ_I_U_VALUE_PLUS_1040 5816101 // = 1040 +#define IQ_I_U_VALUE_PLUS_1041 5821693 // = 1041 +#define IQ_I_U_VALUE_PLUS_1042 5827286 // = 1042 +#define IQ_I_U_VALUE_PLUS_1043 5832878 // = 1043 +#define IQ_I_U_VALUE_PLUS_1044 5838471 // = 1044 +#define IQ_I_U_VALUE_PLUS_1045 5844063 // = 1045 +#define IQ_I_U_VALUE_PLUS_1046 5849655 // = 1046 +#define IQ_I_U_VALUE_PLUS_1047 5855248 // = 1047 +#define IQ_I_U_VALUE_PLUS_1048 5860840 // = 1048 +#define IQ_I_U_VALUE_PLUS_1049 5866433 // = 1049 +#define IQ_I_U_VALUE_PLUS_1050 5872025 // = 1050 +#define IQ_I_U_VALUE_PLUS_1051 5877618 // = 1051 +#define IQ_I_U_VALUE_PLUS_1052 5883210 // = 1052 +#define IQ_I_U_VALUE_PLUS_1053 5888802 // = 1053 +#define IQ_I_U_VALUE_PLUS_1054 5894395 // = 1054 +#define IQ_I_U_VALUE_PLUS_1055 5899987 // = 1055 +#define IQ_I_U_VALUE_PLUS_1056 5905580 // = 1056 +#define IQ_I_U_VALUE_PLUS_1057 5911172 // = 1057 +#define IQ_I_U_VALUE_PLUS_1058 5916764 // = 1058 +#define IQ_I_U_VALUE_PLUS_1059 5922357 // = 1059 +#define IQ_I_U_VALUE_PLUS_1060 5927949 // = 1060 +#define IQ_I_U_VALUE_PLUS_1061 5933542 // = 1061 +#define IQ_I_U_VALUE_PLUS_1062 5939134 // = 1062 +#define IQ_I_U_VALUE_PLUS_1063 5944726 // = 1063 +#define IQ_I_U_VALUE_PLUS_1064 5950319 // = 1064 +#define IQ_I_U_VALUE_PLUS_1065 5955911 // = 1065 +#define IQ_I_U_VALUE_PLUS_1066 5961504 // = 1066 +#define IQ_I_U_VALUE_PLUS_1067 5967096 // = 1067 +#define IQ_I_U_VALUE_PLUS_1068 5972688 // = 1068 +#define IQ_I_U_VALUE_PLUS_1069 5978281 // = 1069 +#define IQ_I_U_VALUE_PLUS_1070 5983873 // = 1070 +#define IQ_I_U_VALUE_PLUS_1071 5989466 // = 1071 +#define IQ_I_U_VALUE_PLUS_1072 5995058 // = 1072 +#define IQ_I_U_VALUE_PLUS_1073 6000650 // = 1073 +#define IQ_I_U_VALUE_PLUS_1074 6006243 // = 1074 +#define IQ_I_U_VALUE_PLUS_1075 6011835 // = 1075 +#define IQ_I_U_VALUE_PLUS_1076 6017428 // = 1076 +#define IQ_I_U_VALUE_PLUS_1077 6023020 // = 1077 +#define IQ_I_U_VALUE_PLUS_1078 6028612 // = 1078 +#define IQ_I_U_VALUE_PLUS_1079 6034205 // = 1079 +#define IQ_I_U_VALUE_PLUS_1080 6039797 // = 1080 +#define IQ_I_U_VALUE_PLUS_1081 6045390 // = 1081 +#define IQ_I_U_VALUE_PLUS_1082 6050982 // = 1082 +#define IQ_I_U_VALUE_PLUS_1083 6056574 // = 1083 +#define IQ_I_U_VALUE_PLUS_1084 6062167 // = 1084 +#define IQ_I_U_VALUE_PLUS_1085 6067759 // = 1085 +#define IQ_I_U_VALUE_PLUS_1086 6073352 // = 1086 +#define IQ_I_U_VALUE_PLUS_1087 6078944 // = 1087 +#define IQ_I_U_VALUE_PLUS_1088 6084537 // = 1088 +#define IQ_I_U_VALUE_PLUS_1089 6090129 // = 1089 +#define IQ_I_U_VALUE_PLUS_1090 6095721 // = 1090 +#define IQ_I_U_VALUE_PLUS_1091 6101314 // = 1091 +#define IQ_I_U_VALUE_PLUS_1092 6106906 // = 1092 +#define IQ_I_U_VALUE_PLUS_1093 6112499 // = 1093 +#define IQ_I_U_VALUE_PLUS_1094 6118091 // = 1094 +#define IQ_I_U_VALUE_PLUS_1095 6123683 // = 1095 +#define IQ_I_U_VALUE_PLUS_1096 6129276 // = 1096 +#define IQ_I_U_VALUE_PLUS_1097 6134868 // = 1097 +#define IQ_I_U_VALUE_PLUS_1098 6140461 // = 1098 +#define IQ_I_U_VALUE_PLUS_1099 6146053 // = 1099 +#define IQ_I_U_VALUE_PLUS_1100 6151645 // = 1100 +#define IQ_I_U_VALUE_PLUS_1101 6157238 // = 1101 +#define IQ_I_U_VALUE_PLUS_1102 6162830 // = 1102 +#define IQ_I_U_VALUE_PLUS_1103 6168423 // = 1103 +#define IQ_I_U_VALUE_PLUS_1104 6174015 // = 1104 +#define IQ_I_U_VALUE_PLUS_1105 6179607 // = 1105 +#define IQ_I_U_VALUE_PLUS_1106 6185200 // = 1106 +#define IQ_I_U_VALUE_PLUS_1107 6190792 // = 1107 +#define IQ_I_U_VALUE_PLUS_1108 6196385 // = 1108 +#define IQ_I_U_VALUE_PLUS_1109 6201977 // = 1109 +#define IQ_I_U_VALUE_PLUS_1110 6207569 // = 1110 +#define IQ_I_U_VALUE_PLUS_1111 6213162 // = 1111 +#define IQ_I_U_VALUE_PLUS_1112 6218754 // = 1112 +#define IQ_I_U_VALUE_PLUS_1113 6224347 // = 1113 +#define IQ_I_U_VALUE_PLUS_1114 6229939 // = 1114 +#define IQ_I_U_VALUE_PLUS_1115 6235531 // = 1115 +#define IQ_I_U_VALUE_PLUS_1116 6241124 // = 1116 +#define IQ_I_U_VALUE_PLUS_1117 6246716 // = 1117 +#define IQ_I_U_VALUE_PLUS_1118 6252309 // = 1118 +#define IQ_I_U_VALUE_PLUS_1119 6257901 // = 1119 +#define IQ_I_U_VALUE_PLUS_1120 6263493 // = 1120 +#define IQ_I_U_VALUE_PLUS_1121 6269086 // = 1121 +#define IQ_I_U_VALUE_PLUS_1122 6274678 // = 1122 +#define IQ_I_U_VALUE_PLUS_1123 6280271 // = 1123 +#define IQ_I_U_VALUE_PLUS_1124 6285863 // = 1124 +#define IQ_I_U_VALUE_PLUS_1125 6291456 // = 1125 +#define IQ_I_U_VALUE_PLUS_1126 6297048 // = 1126 +#define IQ_I_U_VALUE_PLUS_1127 6302640 // = 1127 +#define IQ_I_U_VALUE_PLUS_1128 6308233 // = 1128 +#define IQ_I_U_VALUE_PLUS_1129 6313825 // = 1129 +#define IQ_I_U_VALUE_PLUS_1130 6319418 // = 1130 +#define IQ_I_U_VALUE_PLUS_1131 6325010 // = 1131 +#define IQ_I_U_VALUE_PLUS_1132 6330602 // = 1132 +#define IQ_I_U_VALUE_PLUS_1133 6336195 // = 1133 +#define IQ_I_U_VALUE_PLUS_1134 6341787 // = 1134 +#define IQ_I_U_VALUE_PLUS_1135 6347380 // = 1135 +#define IQ_I_U_VALUE_PLUS_1136 6352972 // = 1136 +#define IQ_I_U_VALUE_PLUS_1137 6358564 // = 1137 +#define IQ_I_U_VALUE_PLUS_1138 6364157 // = 1138 +#define IQ_I_U_VALUE_PLUS_1139 6369749 // = 1139 +#define IQ_I_U_VALUE_PLUS_1140 6375342 // = 1140 +#define IQ_I_U_VALUE_PLUS_1141 6380934 // = 1141 +#define IQ_I_U_VALUE_PLUS_1142 6386526 // = 1142 +#define IQ_I_U_VALUE_PLUS_1143 6392119 // = 1143 +#define IQ_I_U_VALUE_PLUS_1144 6397711 // = 1144 +#define IQ_I_U_VALUE_PLUS_1145 6403304 // = 1145 +#define IQ_I_U_VALUE_PLUS_1146 6408896 // = 1146 +#define IQ_I_U_VALUE_PLUS_1147 6414488 // = 1147 +#define IQ_I_U_VALUE_PLUS_1148 6420081 // = 1148 +#define IQ_I_U_VALUE_PLUS_1149 6425673 // = 1149 +#define IQ_I_U_VALUE_PLUS_1150 6431266 // = 1150 +#define IQ_I_U_VALUE_PLUS_1151 6436858 // = 1151 +#define IQ_I_U_VALUE_PLUS_1152 6442450 // = 1152 +#define IQ_I_U_VALUE_PLUS_1153 6448043 // = 1153 +#define IQ_I_U_VALUE_PLUS_1154 6453635 // = 1154 +#define IQ_I_U_VALUE_PLUS_1155 6459228 // = 1155 +#define IQ_I_U_VALUE_PLUS_1156 6464820 // = 1156 +#define IQ_I_U_VALUE_PLUS_1157 6470412 // = 1157 +#define IQ_I_U_VALUE_PLUS_1158 6476005 // = 1158 +#define IQ_I_U_VALUE_PLUS_1159 6481597 // = 1159 +#define IQ_I_U_VALUE_PLUS_1160 6487190 // = 1160 +#define IQ_I_U_VALUE_PLUS_1161 6492782 // = 1161 +#define IQ_I_U_VALUE_PLUS_1162 6498374 // = 1162 +#define IQ_I_U_VALUE_PLUS_1163 6503967 // = 1163 +#define IQ_I_U_VALUE_PLUS_1164 6509559 // = 1164 +#define IQ_I_U_VALUE_PLUS_1165 6515152 // = 1165 +#define IQ_I_U_VALUE_PLUS_1166 6520744 // = 1166 +#define IQ_I_U_VALUE_PLUS_1167 6526337 // = 1167 +#define IQ_I_U_VALUE_PLUS_1168 6531929 // = 1168 +#define IQ_I_U_VALUE_PLUS_1169 6537521 // = 1169 +#define IQ_I_U_VALUE_PLUS_1170 6543114 // = 1170 +#define IQ_I_U_VALUE_PLUS_1171 6548706 // = 1171 +#define IQ_I_U_VALUE_PLUS_1172 6554299 // = 1172 +#define IQ_I_U_VALUE_PLUS_1173 6559891 // = 1173 +#define IQ_I_U_VALUE_PLUS_1174 6565483 // = 1174 +#define IQ_I_U_VALUE_PLUS_1175 6571076 // = 1175 +#define IQ_I_U_VALUE_PLUS_1176 6576668 // = 1176 +#define IQ_I_U_VALUE_PLUS_1177 6582261 // = 1177 +#define IQ_I_U_VALUE_PLUS_1178 6587853 // = 1178 +#define IQ_I_U_VALUE_PLUS_1179 6593445 // = 1179 +#define IQ_I_U_VALUE_PLUS_1180 6599038 // = 1180 +#define IQ_I_U_VALUE_PLUS_1181 6604630 // = 1181 +#define IQ_I_U_VALUE_PLUS_1182 6610223 // = 1182 +#define IQ_I_U_VALUE_PLUS_1183 6615815 // = 1183 +#define IQ_I_U_VALUE_PLUS_1184 6621407 // = 1184 +#define IQ_I_U_VALUE_PLUS_1185 6627000 // = 1185 +#define IQ_I_U_VALUE_PLUS_1186 6632592 // = 1186 +#define IQ_I_U_VALUE_PLUS_1187 6638185 // = 1187 +#define IQ_I_U_VALUE_PLUS_1188 6643777 // = 1188 +#define IQ_I_U_VALUE_PLUS_1189 6649369 // = 1189 +#define IQ_I_U_VALUE_PLUS_1190 6654962 // = 1190 +#define IQ_I_U_VALUE_PLUS_1191 6660554 // = 1191 +#define IQ_I_U_VALUE_PLUS_1192 6666147 // = 1192 +#define IQ_I_U_VALUE_PLUS_1193 6671739 // = 1193 +#define IQ_I_U_VALUE_PLUS_1194 6677331 // = 1194 +#define IQ_I_U_VALUE_PLUS_1195 6682924 // = 1195 +#define IQ_I_U_VALUE_PLUS_1196 6688516 // = 1196 +#define IQ_I_U_VALUE_PLUS_1197 6694109 // = 1197 +#define IQ_I_U_VALUE_PLUS_1198 6699701 // = 1198 +#define IQ_I_U_VALUE_PLUS_1199 6705293 // = 1199 +#define IQ_I_U_VALUE_PLUS_1200 6710886 // = 1200 +#define IQ_I_U_VALUE_PLUS_1201 6716478 // = 1201 +#define IQ_I_U_VALUE_PLUS_1202 6722071 // = 1202 +#define IQ_I_U_VALUE_PLUS_1203 6727663 // = 1203 +#define IQ_I_U_VALUE_PLUS_1204 6733256 // = 1204 +#define IQ_I_U_VALUE_PLUS_1205 6738848 // = 1205 +#define IQ_I_U_VALUE_PLUS_1206 6744440 // = 1206 +#define IQ_I_U_VALUE_PLUS_1207 6750033 // = 1207 +#define IQ_I_U_VALUE_PLUS_1208 6755625 // = 1208 +#define IQ_I_U_VALUE_PLUS_1209 6761218 // = 1209 +#define IQ_I_U_VALUE_PLUS_1210 6766810 // = 1210 +#define IQ_I_U_VALUE_PLUS_1211 6772402 // = 1211 +#define IQ_I_U_VALUE_PLUS_1212 6777995 // = 1212 +#define IQ_I_U_VALUE_PLUS_1213 6783587 // = 1213 +#define IQ_I_U_VALUE_PLUS_1214 6789180 // = 1214 +#define IQ_I_U_VALUE_PLUS_1215 6794772 // = 1215 +#define IQ_I_U_VALUE_PLUS_1216 6800364 // = 1216 +#define IQ_I_U_VALUE_PLUS_1217 6805957 // = 1217 +#define IQ_I_U_VALUE_PLUS_1218 6811549 // = 1218 +#define IQ_I_U_VALUE_PLUS_1219 6817142 // = 1219 +#define IQ_I_U_VALUE_PLUS_1220 6822734 // = 1220 +#define IQ_I_U_VALUE_PLUS_1221 6828326 // = 1221 +#define IQ_I_U_VALUE_PLUS_1222 6833919 // = 1222 +#define IQ_I_U_VALUE_PLUS_1223 6839511 // = 1223 +#define IQ_I_U_VALUE_PLUS_1224 6845104 // = 1224 +#define IQ_I_U_VALUE_PLUS_1225 6850696 // = 1225 +#define IQ_I_U_VALUE_PLUS_1226 6856288 // = 1226 +#define IQ_I_U_VALUE_PLUS_1227 6861881 // = 1227 +#define IQ_I_U_VALUE_PLUS_1228 6867473 // = 1228 +#define IQ_I_U_VALUE_PLUS_1229 6873066 // = 1229 +#define IQ_I_U_VALUE_PLUS_1230 6878658 // = 1230 +#define IQ_I_U_VALUE_PLUS_1231 6884250 // = 1231 +#define IQ_I_U_VALUE_PLUS_1232 6889843 // = 1232 +#define IQ_I_U_VALUE_PLUS_1233 6895435 // = 1233 +#define IQ_I_U_VALUE_PLUS_1234 6901028 // = 1234 +#define IQ_I_U_VALUE_PLUS_1235 6906620 // = 1235 +#define IQ_I_U_VALUE_PLUS_1236 6912212 // = 1236 +#define IQ_I_U_VALUE_PLUS_1237 6917805 // = 1237 +#define IQ_I_U_VALUE_PLUS_1238 6923397 // = 1238 +#define IQ_I_U_VALUE_PLUS_1239 6928990 // = 1239 +#define IQ_I_U_VALUE_PLUS_1240 6934582 // = 1240 +#define IQ_I_U_VALUE_PLUS_1241 6940175 // = 1241 +#define IQ_I_U_VALUE_PLUS_1242 6945767 // = 1242 +#define IQ_I_U_VALUE_PLUS_1243 6951359 // = 1243 +#define IQ_I_U_VALUE_PLUS_1244 6956952 // = 1244 +#define IQ_I_U_VALUE_PLUS_1245 6962544 // = 1245 +#define IQ_I_U_VALUE_PLUS_1246 6968137 // = 1246 +#define IQ_I_U_VALUE_PLUS_1247 6973729 // = 1247 +#define IQ_I_U_VALUE_PLUS_1248 6979321 // = 1248 +#define IQ_I_U_VALUE_PLUS_1249 6984914 // = 1249 +#define IQ_I_U_VALUE_PLUS_1250 6990506 // = 1250 +#define IQ_I_U_VALUE_PLUS_1251 6996099 // = 1251 +#define IQ_I_U_VALUE_PLUS_1252 7001691 // = 1252 +#define IQ_I_U_VALUE_PLUS_1253 7007283 // = 1253 +#define IQ_I_U_VALUE_PLUS_1254 7012876 // = 1254 +#define IQ_I_U_VALUE_PLUS_1255 7018468 // = 1255 +#define IQ_I_U_VALUE_PLUS_1256 7024061 // = 1256 +#define IQ_I_U_VALUE_PLUS_1257 7029653 // = 1257 +#define IQ_I_U_VALUE_PLUS_1258 7035245 // = 1258 +#define IQ_I_U_VALUE_PLUS_1259 7040838 // = 1259 +#define IQ_I_U_VALUE_PLUS_1260 7046430 // = 1260 +#define IQ_I_U_VALUE_PLUS_1261 7052023 // = 1261 +#define IQ_I_U_VALUE_PLUS_1262 7057615 // = 1262 +#define IQ_I_U_VALUE_PLUS_1263 7063207 // = 1263 +#define IQ_I_U_VALUE_PLUS_1264 7068800 // = 1264 +#define IQ_I_U_VALUE_PLUS_1265 7074392 // = 1265 +#define IQ_I_U_VALUE_PLUS_1266 7079985 // = 1266 +#define IQ_I_U_VALUE_PLUS_1267 7085577 // = 1267 +#define IQ_I_U_VALUE_PLUS_1268 7091169 // = 1268 +#define IQ_I_U_VALUE_PLUS_1269 7096762 // = 1269 +#define IQ_I_U_VALUE_PLUS_1270 7102354 // = 1270 +#define IQ_I_U_VALUE_PLUS_1271 7107947 // = 1271 +#define IQ_I_U_VALUE_PLUS_1272 7113539 // = 1272 +#define IQ_I_U_VALUE_PLUS_1273 7119131 // = 1273 +#define IQ_I_U_VALUE_PLUS_1274 7124724 // = 1274 +#define IQ_I_U_VALUE_PLUS_1275 7130316 // = 1275 +#define IQ_I_U_VALUE_PLUS_1276 7135909 // = 1276 +#define IQ_I_U_VALUE_PLUS_1277 7141501 // = 1277 +#define IQ_I_U_VALUE_PLUS_1278 7147094 // = 1278 +#define IQ_I_U_VALUE_PLUS_1279 7152686 // = 1279 +#define IQ_I_U_VALUE_PLUS_1280 7158278 // = 1280 +#define IQ_I_U_VALUE_PLUS_1281 7163871 // = 1281 +#define IQ_I_U_VALUE_PLUS_1282 7169463 // = 1282 +#define IQ_I_U_VALUE_PLUS_1283 7175056 // = 1283 +#define IQ_I_U_VALUE_PLUS_1284 7180648 // = 1284 +#define IQ_I_U_VALUE_PLUS_1285 7186240 // = 1285 +#define IQ_I_U_VALUE_PLUS_1286 7191833 // = 1286 +#define IQ_I_U_VALUE_PLUS_1287 7197425 // = 1287 +#define IQ_I_U_VALUE_PLUS_1288 7203018 // = 1288 +#define IQ_I_U_VALUE_PLUS_1289 7208610 // = 1289 +#define IQ_I_U_VALUE_PLUS_1290 7214202 // = 1290 +#define IQ_I_U_VALUE_PLUS_1291 7219795 // = 1291 +#define IQ_I_U_VALUE_PLUS_1292 7225387 // = 1292 +#define IQ_I_U_VALUE_PLUS_1293 7230980 // = 1293 +#define IQ_I_U_VALUE_PLUS_1294 7236572 // = 1294 +#define IQ_I_U_VALUE_PLUS_1295 7242164 // = 1295 +#define IQ_I_U_VALUE_PLUS_1296 7247757 // = 1296 +#define IQ_I_U_VALUE_PLUS_1297 7253349 // = 1297 +#define IQ_I_U_VALUE_PLUS_1298 7258942 // = 1298 +#define IQ_I_U_VALUE_PLUS_1299 7264534 // = 1299 +#define IQ_I_U_VALUE_PLUS_1300 7270126 // = 1300 +#define IQ_I_U_VALUE_PLUS_1301 7275719 // = 1301 +#define IQ_I_U_VALUE_PLUS_1302 7281311 // = 1302 +#define IQ_I_U_VALUE_PLUS_1303 7286904 // = 1303 +#define IQ_I_U_VALUE_PLUS_1304 7292496 // = 1304 +#define IQ_I_U_VALUE_PLUS_1305 7298088 // = 1305 +#define IQ_I_U_VALUE_PLUS_1306 7303681 // = 1306 +#define IQ_I_U_VALUE_PLUS_1307 7309273 // = 1307 +#define IQ_I_U_VALUE_PLUS_1308 7314866 // = 1308 +#define IQ_I_U_VALUE_PLUS_1309 7320458 // = 1309 +#define IQ_I_U_VALUE_PLUS_1310 7326050 // = 1310 +#define IQ_I_U_VALUE_PLUS_1311 7331643 // = 1311 +#define IQ_I_U_VALUE_PLUS_1312 7337235 // = 1312 +#define IQ_I_U_VALUE_PLUS_1313 7342828 // = 1313 +#define IQ_I_U_VALUE_PLUS_1314 7348420 // = 1314 +#define IQ_I_U_VALUE_PLUS_1315 7354013 // = 1315 +#define IQ_I_U_VALUE_PLUS_1316 7359605 // = 1316 +#define IQ_I_U_VALUE_PLUS_1317 7365197 // = 1317 +#define IQ_I_U_VALUE_PLUS_1318 7370790 // = 1318 +#define IQ_I_U_VALUE_PLUS_1319 7376382 // = 1319 +#define IQ_I_U_VALUE_PLUS_1320 7381975 // = 1320 +#define IQ_I_U_VALUE_PLUS_1321 7387567 // = 1321 +#define IQ_I_U_VALUE_PLUS_1322 7393159 // = 1322 +#define IQ_I_U_VALUE_PLUS_1323 7398752 // = 1323 +#define IQ_I_U_VALUE_PLUS_1324 7404344 // = 1324 +#define IQ_I_U_VALUE_PLUS_1325 7409937 // = 1325 +#define IQ_I_U_VALUE_PLUS_1326 7415529 // = 1326 +#define IQ_I_U_VALUE_PLUS_1327 7421121 // = 1327 +#define IQ_I_U_VALUE_PLUS_1328 7426714 // = 1328 +#define IQ_I_U_VALUE_PLUS_1329 7432306 // = 1329 +#define IQ_I_U_VALUE_PLUS_1330 7437899 // = 1330 +#define IQ_I_U_VALUE_PLUS_1331 7443491 // = 1331 +#define IQ_I_U_VALUE_PLUS_1332 7449083 // = 1332 +#define IQ_I_U_VALUE_PLUS_1333 7454676 // = 1333 +#define IQ_I_U_VALUE_PLUS_1334 7460268 // = 1334 +#define IQ_I_U_VALUE_PLUS_1335 7465861 // = 1335 +#define IQ_I_U_VALUE_PLUS_1336 7471453 // = 1336 +#define IQ_I_U_VALUE_PLUS_1337 7477045 // = 1337 +#define IQ_I_U_VALUE_PLUS_1338 7482638 // = 1338 +#define IQ_I_U_VALUE_PLUS_1339 7488230 // = 1339 +#define IQ_I_U_VALUE_PLUS_1340 7493823 // = 1340 +#define IQ_I_U_VALUE_PLUS_1341 7499415 // = 1341 +#define IQ_I_U_VALUE_PLUS_1342 7505007 // = 1342 +#define IQ_I_U_VALUE_PLUS_1343 7510600 // = 1343 +#define IQ_I_U_VALUE_PLUS_1344 7516192 // = 1344 +#define IQ_I_U_VALUE_PLUS_1345 7521785 // = 1345 +#define IQ_I_U_VALUE_PLUS_1346 7527377 // = 1346 +#define IQ_I_U_VALUE_PLUS_1347 7532969 // = 1347 +#define IQ_I_U_VALUE_PLUS_1348 7538562 // = 1348 +#define IQ_I_U_VALUE_PLUS_1349 7544154 // = 1349 +#define IQ_I_U_VALUE_PLUS_1350 7549747 // = 1350 +#define IQ_I_U_VALUE_PLUS_1351 7555339 // = 1351 +#define IQ_I_U_VALUE_PLUS_1352 7560932 // = 1352 +#define IQ_I_U_VALUE_PLUS_1353 7566524 // = 1353 +#define IQ_I_U_VALUE_PLUS_1354 7572116 // = 1354 +#define IQ_I_U_VALUE_PLUS_1355 7577709 // = 1355 +#define IQ_I_U_VALUE_PLUS_1356 7583301 // = 1356 +#define IQ_I_U_VALUE_PLUS_1357 7588894 // = 1357 +#define IQ_I_U_VALUE_PLUS_1358 7594486 // = 1358 +#define IQ_I_U_VALUE_PLUS_1359 7600078 // = 1359 +#define IQ_I_U_VALUE_PLUS_1360 7605671 // = 1360 +#define IQ_I_U_VALUE_PLUS_1361 7611263 // = 1361 +#define IQ_I_U_VALUE_PLUS_1362 7616856 // = 1362 +#define IQ_I_U_VALUE_PLUS_1363 7622448 // = 1363 +#define IQ_I_U_VALUE_PLUS_1364 7628040 // = 1364 +#define IQ_I_U_VALUE_PLUS_1365 7633633 // = 1365 +#define IQ_I_U_VALUE_PLUS_1366 7639225 // = 1366 +#define IQ_I_U_VALUE_PLUS_1367 7644818 // = 1367 +#define IQ_I_U_VALUE_PLUS_1368 7650410 // = 1368 +#define IQ_I_U_VALUE_PLUS_1369 7656002 // = 1369 +#define IQ_I_U_VALUE_PLUS_1370 7661595 // = 1370 +#define IQ_I_U_VALUE_PLUS_1371 7667187 // = 1371 +#define IQ_I_U_VALUE_PLUS_1372 7672780 // = 1372 +#define IQ_I_U_VALUE_PLUS_1373 7678372 // = 1373 +#define IQ_I_U_VALUE_PLUS_1374 7683964 // = 1374 +#define IQ_I_U_VALUE_PLUS_1375 7689557 // = 1375 +#define IQ_I_U_VALUE_PLUS_1376 7695149 // = 1376 +#define IQ_I_U_VALUE_PLUS_1377 7700742 // = 1377 +#define IQ_I_U_VALUE_PLUS_1378 7706334 // = 1378 +#define IQ_I_U_VALUE_PLUS_1379 7711926 // = 1379 +#define IQ_I_U_VALUE_PLUS_1380 7717519 // = 1380 +#define IQ_I_U_VALUE_PLUS_1381 7723111 // = 1381 +#define IQ_I_U_VALUE_PLUS_1382 7728704 // = 1382 +#define IQ_I_U_VALUE_PLUS_1383 7734296 // = 1383 +#define IQ_I_U_VALUE_PLUS_1384 7739888 // = 1384 +#define IQ_I_U_VALUE_PLUS_1385 7745481 // = 1385 +#define IQ_I_U_VALUE_PLUS_1386 7751073 // = 1386 +#define IQ_I_U_VALUE_PLUS_1387 7756666 // = 1387 +#define IQ_I_U_VALUE_PLUS_1388 7762258 // = 1388 +#define IQ_I_U_VALUE_PLUS_1389 7767851 // = 1389 +#define IQ_I_U_VALUE_PLUS_1390 7773443 // = 1390 +#define IQ_I_U_VALUE_PLUS_1391 7779035 // = 1391 +#define IQ_I_U_VALUE_PLUS_1392 7784628 // = 1392 +#define IQ_I_U_VALUE_PLUS_1393 7790220 // = 1393 +#define IQ_I_U_VALUE_PLUS_1394 7795813 // = 1394 +#define IQ_I_U_VALUE_PLUS_1395 7801405 // = 1395 +#define IQ_I_U_VALUE_PLUS_1396 7806997 // = 1396 +#define IQ_I_U_VALUE_PLUS_1397 7812590 // = 1397 +#define IQ_I_U_VALUE_PLUS_1398 7818182 // = 1398 +#define IQ_I_U_VALUE_PLUS_1399 7823775 // = 1399 +#define IQ_I_U_VALUE_PLUS_1400 7829367 // = 1400 +#define IQ_I_U_VALUE_PLUS_1401 7834959 // = 1401 +#define IQ_I_U_VALUE_PLUS_1402 7840552 // = 1402 +#define IQ_I_U_VALUE_PLUS_1403 7846144 // = 1403 +#define IQ_I_U_VALUE_PLUS_1404 7851737 // = 1404 +#define IQ_I_U_VALUE_PLUS_1405 7857329 // = 1405 +#define IQ_I_U_VALUE_PLUS_1406 7862921 // = 1406 +#define IQ_I_U_VALUE_PLUS_1407 7868514 // = 1407 +#define IQ_I_U_VALUE_PLUS_1408 7874106 // = 1408 +#define IQ_I_U_VALUE_PLUS_1409 7879699 // = 1409 +#define IQ_I_U_VALUE_PLUS_1410 7885291 // = 1410 +#define IQ_I_U_VALUE_PLUS_1411 7890883 // = 1411 +#define IQ_I_U_VALUE_PLUS_1412 7896476 // = 1412 +#define IQ_I_U_VALUE_PLUS_1413 7902068 // = 1413 +#define IQ_I_U_VALUE_PLUS_1414 7907661 // = 1414 +#define IQ_I_U_VALUE_PLUS_1415 7913253 // = 1415 +#define IQ_I_U_VALUE_PLUS_1416 7918845 // = 1416 +#define IQ_I_U_VALUE_PLUS_1417 7924438 // = 1417 +#define IQ_I_U_VALUE_PLUS_1418 7930030 // = 1418 +#define IQ_I_U_VALUE_PLUS_1419 7935623 // = 1419 +#define IQ_I_U_VALUE_PLUS_1420 7941215 // = 1420 +#define IQ_I_U_VALUE_PLUS_1421 7946807 // = 1421 +#define IQ_I_U_VALUE_PLUS_1422 7952400 // = 1422 +#define IQ_I_U_VALUE_PLUS_1423 7957992 // = 1423 +#define IQ_I_U_VALUE_PLUS_1424 7963585 // = 1424 +#define IQ_I_U_VALUE_PLUS_1425 7969177 // = 1425 +#define IQ_I_U_VALUE_PLUS_1426 7974770 // = 1426 +#define IQ_I_U_VALUE_PLUS_1427 7980362 // = 1427 +#define IQ_I_U_VALUE_PLUS_1428 7985954 // = 1428 +#define IQ_I_U_VALUE_PLUS_1429 7991547 // = 1429 +#define IQ_I_U_VALUE_PLUS_1430 7997139 // = 1430 +#define IQ_I_U_VALUE_PLUS_1431 8002732 // = 1431 +#define IQ_I_U_VALUE_PLUS_1432 8008324 // = 1432 +#define IQ_I_U_VALUE_PLUS_1433 8013916 // = 1433 +#define IQ_I_U_VALUE_PLUS_1434 8019509 // = 1434 +#define IQ_I_U_VALUE_PLUS_1435 8025101 // = 1435 +#define IQ_I_U_VALUE_PLUS_1436 8030694 // = 1436 +#define IQ_I_U_VALUE_PLUS_1437 8036286 // = 1437 +#define IQ_I_U_VALUE_PLUS_1438 8041878 // = 1438 +#define IQ_I_U_VALUE_PLUS_1439 8047471 // = 1439 +#define IQ_I_U_VALUE_PLUS_1440 8053063 // = 1440 +#define IQ_I_U_VALUE_PLUS_1441 8058656 // = 1441 +#define IQ_I_U_VALUE_PLUS_1442 8064248 // = 1442 +#define IQ_I_U_VALUE_PLUS_1443 8069840 // = 1443 +#define IQ_I_U_VALUE_PLUS_1444 8075433 // = 1444 +#define IQ_I_U_VALUE_PLUS_1445 8081025 // = 1445 +#define IQ_I_U_VALUE_PLUS_1446 8086618 // = 1446 +#define IQ_I_U_VALUE_PLUS_1447 8092210 // = 1447 +#define IQ_I_U_VALUE_PLUS_1448 8097802 // = 1448 +#define IQ_I_U_VALUE_PLUS_1449 8103395 // = 1449 +#define IQ_I_U_VALUE_PLUS_1450 8108987 // = 1450 +#define IQ_I_U_VALUE_PLUS_1451 8114580 // = 1451 +#define IQ_I_U_VALUE_PLUS_1452 8120172 // = 1452 +#define IQ_I_U_VALUE_PLUS_1453 8125764 // = 1453 +#define IQ_I_U_VALUE_PLUS_1454 8131357 // = 1454 +#define IQ_I_U_VALUE_PLUS_1455 8136949 // = 1455 +#define IQ_I_U_VALUE_PLUS_1456 8142542 // = 1456 +#define IQ_I_U_VALUE_PLUS_1457 8148134 // = 1457 +#define IQ_I_U_VALUE_PLUS_1458 8153726 // = 1458 +#define IQ_I_U_VALUE_PLUS_1459 8159319 // = 1459 +#define IQ_I_U_VALUE_PLUS_1460 8164911 // = 1460 +#define IQ_I_U_VALUE_PLUS_1461 8170504 // = 1461 +#define IQ_I_U_VALUE_PLUS_1462 8176096 // = 1462 +#define IQ_I_U_VALUE_PLUS_1463 8181689 // = 1463 +#define IQ_I_U_VALUE_PLUS_1464 8187281 // = 1464 +#define IQ_I_U_VALUE_PLUS_1465 8192873 // = 1465 +#define IQ_I_U_VALUE_PLUS_1466 8198466 // = 1466 +#define IQ_I_U_VALUE_PLUS_1467 8204058 // = 1467 +#define IQ_I_U_VALUE_PLUS_1468 8209651 // = 1468 +#define IQ_I_U_VALUE_PLUS_1469 8215243 // = 1469 +#define IQ_I_U_VALUE_PLUS_1470 8220835 // = 1470 +#define IQ_I_U_VALUE_PLUS_1471 8226428 // = 1471 +#define IQ_I_U_VALUE_PLUS_1472 8232020 // = 1472 +#define IQ_I_U_VALUE_PLUS_1473 8237613 // = 1473 +#define IQ_I_U_VALUE_PLUS_1474 8243205 // = 1474 +#define IQ_I_U_VALUE_PLUS_1475 8248797 // = 1475 +#define IQ_I_U_VALUE_PLUS_1476 8254390 // = 1476 +#define IQ_I_U_VALUE_PLUS_1477 8259982 // = 1477 +#define IQ_I_U_VALUE_PLUS_1478 8265575 // = 1478 +#define IQ_I_U_VALUE_PLUS_1479 8271167 // = 1479 +#define IQ_I_U_VALUE_PLUS_1480 8276759 // = 1480 +#define IQ_I_U_VALUE_PLUS_1481 8282352 // = 1481 +#define IQ_I_U_VALUE_PLUS_1482 8287944 // = 1482 +#define IQ_I_U_VALUE_PLUS_1483 8293537 // = 1483 +#define IQ_I_U_VALUE_PLUS_1484 8299129 // = 1484 +#define IQ_I_U_VALUE_PLUS_1485 8304721 // = 1485 +#define IQ_I_U_VALUE_PLUS_1486 8310314 // = 1486 +#define IQ_I_U_VALUE_PLUS_1487 8315906 // = 1487 +#define IQ_I_U_VALUE_PLUS_1488 8321499 // = 1488 +#define IQ_I_U_VALUE_PLUS_1489 8327091 // = 1489 +#define IQ_I_U_VALUE_PLUS_1490 8332683 // = 1490 +#define IQ_I_U_VALUE_PLUS_1491 8338276 // = 1491 +#define IQ_I_U_VALUE_PLUS_1492 8343868 // = 1492 +#define IQ_I_U_VALUE_PLUS_1493 8349461 // = 1493 +#define IQ_I_U_VALUE_PLUS_1494 8355053 // = 1494 +#define IQ_I_U_VALUE_PLUS_1495 8360645 // = 1495 +#define IQ_I_U_VALUE_PLUS_1496 8366238 // = 1496 +#define IQ_I_U_VALUE_PLUS_1497 8371830 // = 1497 +#define IQ_I_U_VALUE_PLUS_1498 8377423 // = 1498 +#define IQ_I_U_VALUE_PLUS_1499 8383015 // = 1499 +#define IQ_I_U_VALUE_PLUS_1500 8388608 // = 1500 +#define IQ_I_U_VALUE_PLUS_1501 8394200 // = 1501 +#define IQ_I_U_VALUE_PLUS_1502 8399792 // = 1502 +#define IQ_I_U_VALUE_PLUS_1503 8405385 // = 1503 +#define IQ_I_U_VALUE_PLUS_1504 8410977 // = 1504 +#define IQ_I_U_VALUE_PLUS_1505 8416570 // = 1505 +#define IQ_I_U_VALUE_PLUS_1506 8422162 // = 1506 +#define IQ_I_U_VALUE_PLUS_1507 8427754 // = 1507 +#define IQ_I_U_VALUE_PLUS_1508 8433347 // = 1508 +#define IQ_I_U_VALUE_PLUS_1509 8438939 // = 1509 +#define IQ_I_U_VALUE_PLUS_1510 8444532 // = 1510 +#define IQ_I_U_VALUE_PLUS_1511 8450124 // = 1511 +#define IQ_I_U_VALUE_PLUS_1512 8455716 // = 1512 +#define IQ_I_U_VALUE_PLUS_1513 8461309 // = 1513 +#define IQ_I_U_VALUE_PLUS_1514 8466901 // = 1514 +#define IQ_I_U_VALUE_PLUS_1515 8472494 // = 1515 +#define IQ_I_U_VALUE_PLUS_1516 8478086 // = 1516 +#define IQ_I_U_VALUE_PLUS_1517 8483678 // = 1517 +#define IQ_I_U_VALUE_PLUS_1518 8489271 // = 1518 +#define IQ_I_U_VALUE_PLUS_1519 8494863 // = 1519 +#define IQ_I_U_VALUE_PLUS_1520 8500456 // = 1520 +#define IQ_I_U_VALUE_PLUS_1521 8506048 // = 1521 +#define IQ_I_U_VALUE_PLUS_1522 8511640 // = 1522 +#define IQ_I_U_VALUE_PLUS_1523 8517233 // = 1523 +#define IQ_I_U_VALUE_PLUS_1524 8522825 // = 1524 +#define IQ_I_U_VALUE_PLUS_1525 8528418 // = 1525 +#define IQ_I_U_VALUE_PLUS_1526 8534010 // = 1526 +#define IQ_I_U_VALUE_PLUS_1527 8539602 // = 1527 +#define IQ_I_U_VALUE_PLUS_1528 8545195 // = 1528 +#define IQ_I_U_VALUE_PLUS_1529 8550787 // = 1529 +#define IQ_I_U_VALUE_PLUS_1530 8556380 // = 1530 +#define IQ_I_U_VALUE_PLUS_1531 8561972 // = 1531 +#define IQ_I_U_VALUE_PLUS_1532 8567564 // = 1532 +#define IQ_I_U_VALUE_PLUS_1533 8573157 // = 1533 +#define IQ_I_U_VALUE_PLUS_1534 8578749 // = 1534 +#define IQ_I_U_VALUE_PLUS_1535 8584342 // = 1535 +#define IQ_I_U_VALUE_PLUS_1536 8589934 // = 1536 +#define IQ_I_U_VALUE_PLUS_1537 8595526 // = 1537 +#define IQ_I_U_VALUE_PLUS_1538 8601119 // = 1538 +#define IQ_I_U_VALUE_PLUS_1539 8606711 // = 1539 +#define IQ_I_U_VALUE_PLUS_1540 8612304 // = 1540 +#define IQ_I_U_VALUE_PLUS_1541 8617896 // = 1541 +#define IQ_I_U_VALUE_PLUS_1542 8623489 // = 1542 +#define IQ_I_U_VALUE_PLUS_1543 8629081 // = 1543 +#define IQ_I_U_VALUE_PLUS_1544 8634673 // = 1544 +#define IQ_I_U_VALUE_PLUS_1545 8640266 // = 1545 +#define IQ_I_U_VALUE_PLUS_1546 8645858 // = 1546 +#define IQ_I_U_VALUE_PLUS_1547 8651451 // = 1547 +#define IQ_I_U_VALUE_PLUS_1548 8657043 // = 1548 +#define IQ_I_U_VALUE_PLUS_1549 8662635 // = 1549 +#define IQ_I_U_VALUE_PLUS_1550 8668228 // = 1550 +#define IQ_I_U_VALUE_PLUS_1551 8673820 // = 1551 +#define IQ_I_U_VALUE_PLUS_1552 8679413 // = 1552 +#define IQ_I_U_VALUE_PLUS_1553 8685005 // = 1553 +#define IQ_I_U_VALUE_PLUS_1554 8690597 // = 1554 +#define IQ_I_U_VALUE_PLUS_1555 8696190 // = 1555 +#define IQ_I_U_VALUE_PLUS_1556 8701782 // = 1556 +#define IQ_I_U_VALUE_PLUS_1557 8707375 // = 1557 +#define IQ_I_U_VALUE_PLUS_1558 8712967 // = 1558 +#define IQ_I_U_VALUE_PLUS_1559 8718559 // = 1559 +#define IQ_I_U_VALUE_PLUS_1560 8724152 // = 1560 +#define IQ_I_U_VALUE_PLUS_1561 8729744 // = 1561 +#define IQ_I_U_VALUE_PLUS_1562 8735337 // = 1562 +#define IQ_I_U_VALUE_PLUS_1563 8740929 // = 1563 +#define IQ_I_U_VALUE_PLUS_1564 8746521 // = 1564 +#define IQ_I_U_VALUE_PLUS_1565 8752114 // = 1565 +#define IQ_I_U_VALUE_PLUS_1566 8757706 // = 1566 +#define IQ_I_U_VALUE_PLUS_1567 8763299 // = 1567 +#define IQ_I_U_VALUE_PLUS_1568 8768891 // = 1568 +#define IQ_I_U_VALUE_PLUS_1569 8774483 // = 1569 +#define IQ_I_U_VALUE_PLUS_1570 8780076 // = 1570 +#define IQ_I_U_VALUE_PLUS_1571 8785668 // = 1571 +#define IQ_I_U_VALUE_PLUS_1572 8791261 // = 1572 +#define IQ_I_U_VALUE_PLUS_1573 8796853 // = 1573 +#define IQ_I_U_VALUE_PLUS_1574 8802445 // = 1574 +#define IQ_I_U_VALUE_PLUS_1575 8808038 // = 1575 +#define IQ_I_U_VALUE_PLUS_1576 8813630 // = 1576 +#define IQ_I_U_VALUE_PLUS_1577 8819223 // = 1577 +#define IQ_I_U_VALUE_PLUS_1578 8824815 // = 1578 +#define IQ_I_U_VALUE_PLUS_1579 8830408 // = 1579 +#define IQ_I_U_VALUE_PLUS_1580 8836000 // = 1580 +#define IQ_I_U_VALUE_PLUS_1581 8841592 // = 1581 +#define IQ_I_U_VALUE_PLUS_1582 8847185 // = 1582 +#define IQ_I_U_VALUE_PLUS_1583 8852777 // = 1583 +#define IQ_I_U_VALUE_PLUS_1584 8858370 // = 1584 +#define IQ_I_U_VALUE_PLUS_1585 8863962 // = 1585 +#define IQ_I_U_VALUE_PLUS_1586 8869554 // = 1586 +#define IQ_I_U_VALUE_PLUS_1587 8875147 // = 1587 +#define IQ_I_U_VALUE_PLUS_1588 8880739 // = 1588 +#define IQ_I_U_VALUE_PLUS_1589 8886332 // = 1589 +#define IQ_I_U_VALUE_PLUS_1590 8891924 // = 1590 +#define IQ_I_U_VALUE_PLUS_1591 8897516 // = 1591 +#define IQ_I_U_VALUE_PLUS_1592 8903109 // = 1592 +#define IQ_I_U_VALUE_PLUS_1593 8908701 // = 1593 +#define IQ_I_U_VALUE_PLUS_1594 8914294 // = 1594 +#define IQ_I_U_VALUE_PLUS_1595 8919886 // = 1595 +#define IQ_I_U_VALUE_PLUS_1596 8925478 // = 1596 +#define IQ_I_U_VALUE_PLUS_1597 8931071 // = 1597 +#define IQ_I_U_VALUE_PLUS_1598 8936663 // = 1598 +#define IQ_I_U_VALUE_PLUS_1599 8942256 // = 1599 +#define IQ_I_U_VALUE_PLUS_1600 8947848 // = 1600 +#define IQ_I_U_VALUE_PLUS_1601 8953440 // = 1601 +#define IQ_I_U_VALUE_PLUS_1602 8959033 // = 1602 +#define IQ_I_U_VALUE_PLUS_1603 8964625 // = 1603 +#define IQ_I_U_VALUE_PLUS_1604 8970218 // = 1604 +#define IQ_I_U_VALUE_PLUS_1605 8975810 // = 1605 +#define IQ_I_U_VALUE_PLUS_1606 8981402 // = 1606 +#define IQ_I_U_VALUE_PLUS_1607 8986995 // = 1607 +#define IQ_I_U_VALUE_PLUS_1608 8992587 // = 1608 +#define IQ_I_U_VALUE_PLUS_1609 8998180 // = 1609 +#define IQ_I_U_VALUE_PLUS_1610 9003772 // = 1610 +#define IQ_I_U_VALUE_PLUS_1611 9009364 // = 1611 +#define IQ_I_U_VALUE_PLUS_1612 9014957 // = 1612 +#define IQ_I_U_VALUE_PLUS_1613 9020549 // = 1613 +#define IQ_I_U_VALUE_PLUS_1614 9026142 // = 1614 +#define IQ_I_U_VALUE_PLUS_1615 9031734 // = 1615 +#define IQ_I_U_VALUE_PLUS_1616 9037327 // = 1616 +#define IQ_I_U_VALUE_PLUS_1617 9042919 // = 1617 +#define IQ_I_U_VALUE_PLUS_1618 9048511 // = 1618 +#define IQ_I_U_VALUE_PLUS_1619 9054104 // = 1619 +#define IQ_I_U_VALUE_PLUS_1620 9059696 // = 1620 +#define IQ_I_U_VALUE_PLUS_1621 9065289 // = 1621 +#define IQ_I_U_VALUE_PLUS_1622 9070881 // = 1622 +#define IQ_I_U_VALUE_PLUS_1623 9076473 // = 1623 +#define IQ_I_U_VALUE_PLUS_1624 9082066 // = 1624 +#define IQ_I_U_VALUE_PLUS_1625 9087658 // = 1625 +#define IQ_I_U_VALUE_PLUS_1626 9093251 // = 1626 +#define IQ_I_U_VALUE_PLUS_1627 9098843 // = 1627 +#define IQ_I_U_VALUE_PLUS_1628 9104435 // = 1628 +#define IQ_I_U_VALUE_PLUS_1629 9110028 // = 1629 +#define IQ_I_U_VALUE_PLUS_1630 9115620 // = 1630 +#define IQ_I_U_VALUE_PLUS_1631 9121213 // = 1631 +#define IQ_I_U_VALUE_PLUS_1632 9126805 // = 1632 +#define IQ_I_U_VALUE_PLUS_1633 9132397 // = 1633 +#define IQ_I_U_VALUE_PLUS_1634 9137990 // = 1634 +#define IQ_I_U_VALUE_PLUS_1635 9143582 // = 1635 +#define IQ_I_U_VALUE_PLUS_1636 9149175 // = 1636 +#define IQ_I_U_VALUE_PLUS_1637 9154767 // = 1637 +#define IQ_I_U_VALUE_PLUS_1638 9160359 // = 1638 +#define IQ_I_U_VALUE_PLUS_1639 9165952 // = 1639 +#define IQ_I_U_VALUE_PLUS_1640 9171544 // = 1640 +#define IQ_I_U_VALUE_PLUS_1641 9177137 // = 1641 +#define IQ_I_U_VALUE_PLUS_1642 9182729 // = 1642 +#define IQ_I_U_VALUE_PLUS_1643 9188321 // = 1643 +#define IQ_I_U_VALUE_PLUS_1644 9193914 // = 1644 +#define IQ_I_U_VALUE_PLUS_1645 9199506 // = 1645 +#define IQ_I_U_VALUE_PLUS_1646 9205099 // = 1646 +#define IQ_I_U_VALUE_PLUS_1647 9210691 // = 1647 +#define IQ_I_U_VALUE_PLUS_1648 9216283 // = 1648 +#define IQ_I_U_VALUE_PLUS_1649 9221876 // = 1649 +#define IQ_I_U_VALUE_PLUS_1650 9227468 // = 1650 +#define IQ_I_U_VALUE_PLUS_1651 9233061 // = 1651 +#define IQ_I_U_VALUE_PLUS_1652 9238653 // = 1652 +#define IQ_I_U_VALUE_PLUS_1653 9244246 // = 1653 +#define IQ_I_U_VALUE_PLUS_1654 9249838 // = 1654 +#define IQ_I_U_VALUE_PLUS_1655 9255430 // = 1655 +#define IQ_I_U_VALUE_PLUS_1656 9261023 // = 1656 +#define IQ_I_U_VALUE_PLUS_1657 9266615 // = 1657 +#define IQ_I_U_VALUE_PLUS_1658 9272208 // = 1658 +#define IQ_I_U_VALUE_PLUS_1659 9277800 // = 1659 +#define IQ_I_U_VALUE_PLUS_1660 9283392 // = 1660 +#define IQ_I_U_VALUE_PLUS_1661 9288985 // = 1661 +#define IQ_I_U_VALUE_PLUS_1662 9294577 // = 1662 +#define IQ_I_U_VALUE_PLUS_1663 9300170 // = 1663 +#define IQ_I_U_VALUE_PLUS_1664 9305762 // = 1664 +#define IQ_I_U_VALUE_PLUS_1665 9311354 // = 1665 +#define IQ_I_U_VALUE_PLUS_1666 9316947 // = 1666 +#define IQ_I_U_VALUE_PLUS_1667 9322539 // = 1667 +#define IQ_I_U_VALUE_PLUS_1668 9328132 // = 1668 +#define IQ_I_U_VALUE_PLUS_1669 9333724 // = 1669 +#define IQ_I_U_VALUE_PLUS_1670 9339316 // = 1670 +#define IQ_I_U_VALUE_PLUS_1671 9344909 // = 1671 +#define IQ_I_U_VALUE_PLUS_1672 9350501 // = 1672 +#define IQ_I_U_VALUE_PLUS_1673 9356094 // = 1673 +#define IQ_I_U_VALUE_PLUS_1674 9361686 // = 1674 +#define IQ_I_U_VALUE_PLUS_1675 9367278 // = 1675 +#define IQ_I_U_VALUE_PLUS_1676 9372871 // = 1676 +#define IQ_I_U_VALUE_PLUS_1677 9378463 // = 1677 +#define IQ_I_U_VALUE_PLUS_1678 9384056 // = 1678 +#define IQ_I_U_VALUE_PLUS_1679 9389648 // = 1679 +#define IQ_I_U_VALUE_PLUS_1680 9395240 // = 1680 +#define IQ_I_U_VALUE_PLUS_1681 9400833 // = 1681 +#define IQ_I_U_VALUE_PLUS_1682 9406425 // = 1682 +#define IQ_I_U_VALUE_PLUS_1683 9412018 // = 1683 +#define IQ_I_U_VALUE_PLUS_1684 9417610 // = 1684 +#define IQ_I_U_VALUE_PLUS_1685 9423202 // = 1685 +#define IQ_I_U_VALUE_PLUS_1686 9428795 // = 1686 +#define IQ_I_U_VALUE_PLUS_1687 9434387 // = 1687 +#define IQ_I_U_VALUE_PLUS_1688 9439980 // = 1688 +#define IQ_I_U_VALUE_PLUS_1689 9445572 // = 1689 +#define IQ_I_U_VALUE_PLUS_1690 9451165 // = 1690 +#define IQ_I_U_VALUE_PLUS_1691 9456757 // = 1691 +#define IQ_I_U_VALUE_PLUS_1692 9462349 // = 1692 +#define IQ_I_U_VALUE_PLUS_1693 9467942 // = 1693 +#define IQ_I_U_VALUE_PLUS_1694 9473534 // = 1694 +#define IQ_I_U_VALUE_PLUS_1695 9479127 // = 1695 +#define IQ_I_U_VALUE_PLUS_1696 9484719 // = 1696 +#define IQ_I_U_VALUE_PLUS_1697 9490311 // = 1697 +#define IQ_I_U_VALUE_PLUS_1698 9495904 // = 1698 +#define IQ_I_U_VALUE_PLUS_1699 9501496 // = 1699 +#define IQ_I_U_VALUE_PLUS_1700 9507089 // = 1700 +#define IQ_I_U_VALUE_PLUS_1701 9512681 // = 1701 +#define IQ_I_U_VALUE_PLUS_1702 9518273 // = 1702 +#define IQ_I_U_VALUE_PLUS_1703 9523866 // = 1703 +#define IQ_I_U_VALUE_PLUS_1704 9529458 // = 1704 +#define IQ_I_U_VALUE_PLUS_1705 9535051 // = 1705 +#define IQ_I_U_VALUE_PLUS_1706 9540643 // = 1706 +#define IQ_I_U_VALUE_PLUS_1707 9546235 // = 1707 +#define IQ_I_U_VALUE_PLUS_1708 9551828 // = 1708 +#define IQ_I_U_VALUE_PLUS_1709 9557420 // = 1709 +#define IQ_I_U_VALUE_PLUS_1710 9563013 // = 1710 +#define IQ_I_U_VALUE_PLUS_1711 9568605 // = 1711 +#define IQ_I_U_VALUE_PLUS_1712 9574197 // = 1712 +#define IQ_I_U_VALUE_PLUS_1713 9579790 // = 1713 +#define IQ_I_U_VALUE_PLUS_1714 9585382 // = 1714 +#define IQ_I_U_VALUE_PLUS_1715 9590975 // = 1715 +#define IQ_I_U_VALUE_PLUS_1716 9596567 // = 1716 +#define IQ_I_U_VALUE_PLUS_1717 9602159 // = 1717 +#define IQ_I_U_VALUE_PLUS_1718 9607752 // = 1718 +#define IQ_I_U_VALUE_PLUS_1719 9613344 // = 1719 +#define IQ_I_U_VALUE_PLUS_1720 9618937 // = 1720 +#define IQ_I_U_VALUE_PLUS_1721 9624529 // = 1721 +#define IQ_I_U_VALUE_PLUS_1722 9630121 // = 1722 +#define IQ_I_U_VALUE_PLUS_1723 9635714 // = 1723 +#define IQ_I_U_VALUE_PLUS_1724 9641306 // = 1724 +#define IQ_I_U_VALUE_PLUS_1725 9646899 // = 1725 +#define IQ_I_U_VALUE_PLUS_1726 9652491 // = 1726 +#define IQ_I_U_VALUE_PLUS_1727 9658084 // = 1727 +#define IQ_I_U_VALUE_PLUS_1728 9663676 // = 1728 +#define IQ_I_U_VALUE_PLUS_1729 9669268 // = 1729 +#define IQ_I_U_VALUE_PLUS_1730 9674861 // = 1730 +#define IQ_I_U_VALUE_PLUS_1731 9680453 // = 1731 +#define IQ_I_U_VALUE_PLUS_1732 9686046 // = 1732 +#define IQ_I_U_VALUE_PLUS_1733 9691638 // = 1733 +#define IQ_I_U_VALUE_PLUS_1734 9697230 // = 1734 +#define IQ_I_U_VALUE_PLUS_1735 9702823 // = 1735 +#define IQ_I_U_VALUE_PLUS_1736 9708415 // = 1736 +#define IQ_I_U_VALUE_PLUS_1737 9714008 // = 1737 +#define IQ_I_U_VALUE_PLUS_1738 9719600 // = 1738 +#define IQ_I_U_VALUE_PLUS_1739 9725192 // = 1739 +#define IQ_I_U_VALUE_PLUS_1740 9730785 // = 1740 +#define IQ_I_U_VALUE_PLUS_1741 9736377 // = 1741 +#define IQ_I_U_VALUE_PLUS_1742 9741970 // = 1742 +#define IQ_I_U_VALUE_PLUS_1743 9747562 // = 1743 +#define IQ_I_U_VALUE_PLUS_1744 9753154 // = 1744 +#define IQ_I_U_VALUE_PLUS_1745 9758747 // = 1745 +#define IQ_I_U_VALUE_PLUS_1746 9764339 // = 1746 +#define IQ_I_U_VALUE_PLUS_1747 9769932 // = 1747 +#define IQ_I_U_VALUE_PLUS_1748 9775524 // = 1748 +#define IQ_I_U_VALUE_PLUS_1749 9781116 // = 1749 +#define IQ_I_U_VALUE_PLUS_1750 9786709 // = 1750 +#define IQ_I_U_VALUE_PLUS_1751 9792301 // = 1751 +#define IQ_I_U_VALUE_PLUS_1752 9797894 // = 1752 +#define IQ_I_U_VALUE_PLUS_1753 9803486 // = 1753 +#define IQ_I_U_VALUE_PLUS_1754 9809078 // = 1754 +#define IQ_I_U_VALUE_PLUS_1755 9814671 // = 1755 +#define IQ_I_U_VALUE_PLUS_1756 9820263 // = 1756 +#define IQ_I_U_VALUE_PLUS_1757 9825856 // = 1757 +#define IQ_I_U_VALUE_PLUS_1758 9831448 // = 1758 +#define IQ_I_U_VALUE_PLUS_1759 9837040 // = 1759 +#define IQ_I_U_VALUE_PLUS_1760 9842633 // = 1760 +#define IQ_I_U_VALUE_PLUS_1761 9848225 // = 1761 +#define IQ_I_U_VALUE_PLUS_1762 9853818 // = 1762 +#define IQ_I_U_VALUE_PLUS_1763 9859410 // = 1763 +#define IQ_I_U_VALUE_PLUS_1764 9865003 // = 1764 +#define IQ_I_U_VALUE_PLUS_1765 9870595 // = 1765 +#define IQ_I_U_VALUE_PLUS_1766 9876187 // = 1766 +#define IQ_I_U_VALUE_PLUS_1767 9881780 // = 1767 +#define IQ_I_U_VALUE_PLUS_1768 9887372 // = 1768 +#define IQ_I_U_VALUE_PLUS_1769 9892965 // = 1769 +#define IQ_I_U_VALUE_PLUS_1770 9898557 // = 1770 +#define IQ_I_U_VALUE_PLUS_1771 9904149 // = 1771 +#define IQ_I_U_VALUE_PLUS_1772 9909742 // = 1772 +#define IQ_I_U_VALUE_PLUS_1773 9915334 // = 1773 +#define IQ_I_U_VALUE_PLUS_1774 9920927 // = 1774 +#define IQ_I_U_VALUE_PLUS_1775 9926519 // = 1775 +#define IQ_I_U_VALUE_PLUS_1776 9932111 // = 1776 +#define IQ_I_U_VALUE_PLUS_1777 9937704 // = 1777 +#define IQ_I_U_VALUE_PLUS_1778 9943296 // = 1778 +#define IQ_I_U_VALUE_PLUS_1779 9948889 // = 1779 +#define IQ_I_U_VALUE_PLUS_1780 9954481 // = 1780 +#define IQ_I_U_VALUE_PLUS_1781 9960073 // = 1781 +#define IQ_I_U_VALUE_PLUS_1782 9965666 // = 1782 +#define IQ_I_U_VALUE_PLUS_1783 9971258 // = 1783 +#define IQ_I_U_VALUE_PLUS_1784 9976851 // = 1784 +#define IQ_I_U_VALUE_PLUS_1785 9982443 // = 1785 +#define IQ_I_U_VALUE_PLUS_1786 9988035 // = 1786 +#define IQ_I_U_VALUE_PLUS_1787 9993628 // = 1787 +#define IQ_I_U_VALUE_PLUS_1788 9999220 // = 1788 +#define IQ_I_U_VALUE_PLUS_1789 10004813 // = 1789 +#define IQ_I_U_VALUE_PLUS_1790 10010405 // = 1790 +#define IQ_I_U_VALUE_PLUS_1791 10015997 // = 1791 +#define IQ_I_U_VALUE_PLUS_1792 10021590 // = 1792 +#define IQ_I_U_VALUE_PLUS_1793 10027182 // = 1793 +#define IQ_I_U_VALUE_PLUS_1794 10032775 // = 1794 +#define IQ_I_U_VALUE_PLUS_1795 10038367 // = 1795 +#define IQ_I_U_VALUE_PLUS_1796 10043959 // = 1796 +#define IQ_I_U_VALUE_PLUS_1797 10049552 // = 1797 +#define IQ_I_U_VALUE_PLUS_1798 10055144 // = 1798 +#define IQ_I_U_VALUE_PLUS_1799 10060737 // = 1799 +#define IQ_I_U_VALUE_PLUS_1800 10066329 // = 1800 +#define IQ_I_U_VALUE_PLUS_1801 10071922 // = 1801 +#define IQ_I_U_VALUE_PLUS_1802 10077514 // = 1802 +#define IQ_I_U_VALUE_PLUS_1803 10083106 // = 1803 +#define IQ_I_U_VALUE_PLUS_1804 10088699 // = 1804 +#define IQ_I_U_VALUE_PLUS_1805 10094291 // = 1805 +#define IQ_I_U_VALUE_PLUS_1806 10099884 // = 1806 +#define IQ_I_U_VALUE_PLUS_1807 10105476 // = 1807 +#define IQ_I_U_VALUE_PLUS_1808 10111068 // = 1808 +#define IQ_I_U_VALUE_PLUS_1809 10116661 // = 1809 +#define IQ_I_U_VALUE_PLUS_1810 10122253 // = 1810 +#define IQ_I_U_VALUE_PLUS_1811 10127846 // = 1811 +#define IQ_I_U_VALUE_PLUS_1812 10133438 // = 1812 +#define IQ_I_U_VALUE_PLUS_1813 10139030 // = 1813 +#define IQ_I_U_VALUE_PLUS_1814 10144623 // = 1814 +#define IQ_I_U_VALUE_PLUS_1815 10150215 // = 1815 +#define IQ_I_U_VALUE_PLUS_1816 10155808 // = 1816 +#define IQ_I_U_VALUE_PLUS_1817 10161400 // = 1817 +#define IQ_I_U_VALUE_PLUS_1818 10166992 // = 1818 +#define IQ_I_U_VALUE_PLUS_1819 10172585 // = 1819 +#define IQ_I_U_VALUE_PLUS_1820 10178177 // = 1820 +#define IQ_I_U_VALUE_PLUS_1821 10183770 // = 1821 +#define IQ_I_U_VALUE_PLUS_1822 10189362 // = 1822 +#define IQ_I_U_VALUE_PLUS_1823 10194954 // = 1823 +#define IQ_I_U_VALUE_PLUS_1824 10200547 // = 1824 +#define IQ_I_U_VALUE_PLUS_1825 10206139 // = 1825 +#define IQ_I_U_VALUE_PLUS_1826 10211732 // = 1826 +#define IQ_I_U_VALUE_PLUS_1827 10217324 // = 1827 +#define IQ_I_U_VALUE_PLUS_1828 10222916 // = 1828 +#define IQ_I_U_VALUE_PLUS_1829 10228509 // = 1829 +#define IQ_I_U_VALUE_PLUS_1830 10234101 // = 1830 +#define IQ_I_U_VALUE_PLUS_1831 10239694 // = 1831 +#define IQ_I_U_VALUE_PLUS_1832 10245286 // = 1832 +#define IQ_I_U_VALUE_PLUS_1833 10250878 // = 1833 +#define IQ_I_U_VALUE_PLUS_1834 10256471 // = 1834 +#define IQ_I_U_VALUE_PLUS_1835 10262063 // = 1835 +#define IQ_I_U_VALUE_PLUS_1836 10267656 // = 1836 +#define IQ_I_U_VALUE_PLUS_1837 10273248 // = 1837 +#define IQ_I_U_VALUE_PLUS_1838 10278841 // = 1838 +#define IQ_I_U_VALUE_PLUS_1839 10284433 // = 1839 +#define IQ_I_U_VALUE_PLUS_1840 10290025 // = 1840 +#define IQ_I_U_VALUE_PLUS_1841 10295618 // = 1841 +#define IQ_I_U_VALUE_PLUS_1842 10301210 // = 1842 +#define IQ_I_U_VALUE_PLUS_1843 10306803 // = 1843 +#define IQ_I_U_VALUE_PLUS_1844 10312395 // = 1844 +#define IQ_I_U_VALUE_PLUS_1845 10317987 // = 1845 +#define IQ_I_U_VALUE_PLUS_1846 10323580 // = 1846 +#define IQ_I_U_VALUE_PLUS_1847 10329172 // = 1847 +#define IQ_I_U_VALUE_PLUS_1848 10334765 // = 1848 +#define IQ_I_U_VALUE_PLUS_1849 10340357 // = 1849 +#define IQ_I_U_VALUE_PLUS_1850 10345949 // = 1850 +#define IQ_I_U_VALUE_PLUS_1851 10351542 // = 1851 +#define IQ_I_U_VALUE_PLUS_1852 10357134 // = 1852 +#define IQ_I_U_VALUE_PLUS_1853 10362727 // = 1853 +#define IQ_I_U_VALUE_PLUS_1854 10368319 // = 1854 +#define IQ_I_U_VALUE_PLUS_1855 10373911 // = 1855 +#define IQ_I_U_VALUE_PLUS_1856 10379504 // = 1856 +#define IQ_I_U_VALUE_PLUS_1857 10385096 // = 1857 +#define IQ_I_U_VALUE_PLUS_1858 10390689 // = 1858 +#define IQ_I_U_VALUE_PLUS_1859 10396281 // = 1859 +#define IQ_I_U_VALUE_PLUS_1860 10401873 // = 1860 +#define IQ_I_U_VALUE_PLUS_1861 10407466 // = 1861 +#define IQ_I_U_VALUE_PLUS_1862 10413058 // = 1862 +#define IQ_I_U_VALUE_PLUS_1863 10418651 // = 1863 +#define IQ_I_U_VALUE_PLUS_1864 10424243 // = 1864 +#define IQ_I_U_VALUE_PLUS_1865 10429835 // = 1865 +#define IQ_I_U_VALUE_PLUS_1866 10435428 // = 1866 +#define IQ_I_U_VALUE_PLUS_1867 10441020 // = 1867 +#define IQ_I_U_VALUE_PLUS_1868 10446613 // = 1868 +#define IQ_I_U_VALUE_PLUS_1869 10452205 // = 1869 +#define IQ_I_U_VALUE_PLUS_1870 10457797 // = 1870 +#define IQ_I_U_VALUE_PLUS_1871 10463390 // = 1871 +#define IQ_I_U_VALUE_PLUS_1872 10468982 // = 1872 +#define IQ_I_U_VALUE_PLUS_1873 10474575 // = 1873 +#define IQ_I_U_VALUE_PLUS_1874 10480167 // = 1874 +#define IQ_I_U_VALUE_PLUS_1875 10485760 // = 1875 +#define IQ_I_U_VALUE_PLUS_1876 10491352 // = 1876 +#define IQ_I_U_VALUE_PLUS_1877 10496944 // = 1877 +#define IQ_I_U_VALUE_PLUS_1878 10502537 // = 1878 +#define IQ_I_U_VALUE_PLUS_1879 10508129 // = 1879 +#define IQ_I_U_VALUE_PLUS_1880 10513722 // = 1880 +#define IQ_I_U_VALUE_PLUS_1881 10519314 // = 1881 +#define IQ_I_U_VALUE_PLUS_1882 10524906 // = 1882 +#define IQ_I_U_VALUE_PLUS_1883 10530499 // = 1883 +#define IQ_I_U_VALUE_PLUS_1884 10536091 // = 1884 +#define IQ_I_U_VALUE_PLUS_1885 10541684 // = 1885 +#define IQ_I_U_VALUE_PLUS_1886 10547276 // = 1886 +#define IQ_I_U_VALUE_PLUS_1887 10552868 // = 1887 +#define IQ_I_U_VALUE_PLUS_1888 10558461 // = 1888 +#define IQ_I_U_VALUE_PLUS_1889 10564053 // = 1889 +#define IQ_I_U_VALUE_PLUS_1890 10569646 // = 1890 +#define IQ_I_U_VALUE_PLUS_1891 10575238 // = 1891 +#define IQ_I_U_VALUE_PLUS_1892 10580830 // = 1892 +#define IQ_I_U_VALUE_PLUS_1893 10586423 // = 1893 +#define IQ_I_U_VALUE_PLUS_1894 10592015 // = 1894 +#define IQ_I_U_VALUE_PLUS_1895 10597608 // = 1895 +#define IQ_I_U_VALUE_PLUS_1896 10603200 // = 1896 +#define IQ_I_U_VALUE_PLUS_1897 10608792 // = 1897 +#define IQ_I_U_VALUE_PLUS_1898 10614385 // = 1898 +#define IQ_I_U_VALUE_PLUS_1899 10619977 // = 1899 +#define IQ_I_U_VALUE_PLUS_1900 10625570 // = 1900 +#define IQ_I_U_VALUE_PLUS_1901 10631162 // = 1901 +#define IQ_I_U_VALUE_PLUS_1902 10636754 // = 1902 +#define IQ_I_U_VALUE_PLUS_1903 10642347 // = 1903 +#define IQ_I_U_VALUE_PLUS_1904 10647939 // = 1904 +#define IQ_I_U_VALUE_PLUS_1905 10653532 // = 1905 +#define IQ_I_U_VALUE_PLUS_1906 10659124 // = 1906 +#define IQ_I_U_VALUE_PLUS_1907 10664716 // = 1907 +#define IQ_I_U_VALUE_PLUS_1908 10670309 // = 1908 +#define IQ_I_U_VALUE_PLUS_1909 10675901 // = 1909 +#define IQ_I_U_VALUE_PLUS_1910 10681494 // = 1910 +#define IQ_I_U_VALUE_PLUS_1911 10687086 // = 1911 +#define IQ_I_U_VALUE_PLUS_1912 10692678 // = 1912 +#define IQ_I_U_VALUE_PLUS_1913 10698271 // = 1913 +#define IQ_I_U_VALUE_PLUS_1914 10703863 // = 1914 +#define IQ_I_U_VALUE_PLUS_1915 10709456 // = 1915 +#define IQ_I_U_VALUE_PLUS_1916 10715048 // = 1916 +#define IQ_I_U_VALUE_PLUS_1917 10720641 // = 1917 +#define IQ_I_U_VALUE_PLUS_1918 10726233 // = 1918 +#define IQ_I_U_VALUE_PLUS_1919 10731825 // = 1919 +#define IQ_I_U_VALUE_PLUS_1920 10737418 // = 1920 +#define IQ_I_U_VALUE_PLUS_1921 10743010 // = 1921 +#define IQ_I_U_VALUE_PLUS_1922 10748603 // = 1922 +#define IQ_I_U_VALUE_PLUS_1923 10754195 // = 1923 +#define IQ_I_U_VALUE_PLUS_1924 10759787 // = 1924 +#define IQ_I_U_VALUE_PLUS_1925 10765380 // = 1925 +#define IQ_I_U_VALUE_PLUS_1926 10770972 // = 1926 +#define IQ_I_U_VALUE_PLUS_1927 10776565 // = 1927 +#define IQ_I_U_VALUE_PLUS_1928 10782157 // = 1928 +#define IQ_I_U_VALUE_PLUS_1929 10787749 // = 1929 +#define IQ_I_U_VALUE_PLUS_1930 10793342 // = 1930 +#define IQ_I_U_VALUE_PLUS_1931 10798934 // = 1931 +#define IQ_I_U_VALUE_PLUS_1932 10804527 // = 1932 +#define IQ_I_U_VALUE_PLUS_1933 10810119 // = 1933 +#define IQ_I_U_VALUE_PLUS_1934 10815711 // = 1934 +#define IQ_I_U_VALUE_PLUS_1935 10821304 // = 1935 +#define IQ_I_U_VALUE_PLUS_1936 10826896 // = 1936 +#define IQ_I_U_VALUE_PLUS_1937 10832489 // = 1937 +#define IQ_I_U_VALUE_PLUS_1938 10838081 // = 1938 +#define IQ_I_U_VALUE_PLUS_1939 10843673 // = 1939 +#define IQ_I_U_VALUE_PLUS_1940 10849266 // = 1940 +#define IQ_I_U_VALUE_PLUS_1941 10854858 // = 1941 +#define IQ_I_U_VALUE_PLUS_1942 10860451 // = 1942 +#define IQ_I_U_VALUE_PLUS_1943 10866043 // = 1943 +#define IQ_I_U_VALUE_PLUS_1944 10871635 // = 1944 +#define IQ_I_U_VALUE_PLUS_1945 10877228 // = 1945 +#define IQ_I_U_VALUE_PLUS_1946 10882820 // = 1946 +#define IQ_I_U_VALUE_PLUS_1947 10888413 // = 1947 +#define IQ_I_U_VALUE_PLUS_1948 10894005 // = 1948 +#define IQ_I_U_VALUE_PLUS_1949 10899597 // = 1949 +#define IQ_I_U_VALUE_PLUS_1950 10905190 // = 1950 +#define IQ_I_U_VALUE_PLUS_1951 10910782 // = 1951 +#define IQ_I_U_VALUE_PLUS_1952 10916375 // = 1952 +#define IQ_I_U_VALUE_PLUS_1953 10921967 // = 1953 +#define IQ_I_U_VALUE_PLUS_1954 10927560 // = 1954 +#define IQ_I_U_VALUE_PLUS_1955 10933152 // = 1955 +#define IQ_I_U_VALUE_PLUS_1956 10938744 // = 1956 +#define IQ_I_U_VALUE_PLUS_1957 10944337 // = 1957 +#define IQ_I_U_VALUE_PLUS_1958 10949929 // = 1958 +#define IQ_I_U_VALUE_PLUS_1959 10955522 // = 1959 +#define IQ_I_U_VALUE_PLUS_1960 10961114 // = 1960 +#define IQ_I_U_VALUE_PLUS_1961 10966706 // = 1961 +#define IQ_I_U_VALUE_PLUS_1962 10972299 // = 1962 +#define IQ_I_U_VALUE_PLUS_1963 10977891 // = 1963 +#define IQ_I_U_VALUE_PLUS_1964 10983484 // = 1964 +#define IQ_I_U_VALUE_PLUS_1965 10989076 // = 1965 +#define IQ_I_U_VALUE_PLUS_1966 10994668 // = 1966 +#define IQ_I_U_VALUE_PLUS_1967 11000261 // = 1967 +#define IQ_I_U_VALUE_PLUS_1968 11005853 // = 1968 +#define IQ_I_U_VALUE_PLUS_1969 11011446 // = 1969 +#define IQ_I_U_VALUE_PLUS_1970 11017038 // = 1970 +#define IQ_I_U_VALUE_PLUS_1971 11022630 // = 1971 +#define IQ_I_U_VALUE_PLUS_1972 11028223 // = 1972 +#define IQ_I_U_VALUE_PLUS_1973 11033815 // = 1973 +#define IQ_I_U_VALUE_PLUS_1974 11039408 // = 1974 +#define IQ_I_U_VALUE_PLUS_1975 11045000 // = 1975 +#define IQ_I_U_VALUE_PLUS_1976 11050592 // = 1976 +#define IQ_I_U_VALUE_PLUS_1977 11056185 // = 1977 +#define IQ_I_U_VALUE_PLUS_1978 11061777 // = 1978 +#define IQ_I_U_VALUE_PLUS_1979 11067370 // = 1979 +#define IQ_I_U_VALUE_PLUS_1980 11072962 // = 1980 +#define IQ_I_U_VALUE_PLUS_1981 11078554 // = 1981 +#define IQ_I_U_VALUE_PLUS_1982 11084147 // = 1982 +#define IQ_I_U_VALUE_PLUS_1983 11089739 // = 1983 +#define IQ_I_U_VALUE_PLUS_1984 11095332 // = 1984 +#define IQ_I_U_VALUE_PLUS_1985 11100924 // = 1985 +#define IQ_I_U_VALUE_PLUS_1986 11106516 // = 1986 +#define IQ_I_U_VALUE_PLUS_1987 11112109 // = 1987 +#define IQ_I_U_VALUE_PLUS_1988 11117701 // = 1988 +#define IQ_I_U_VALUE_PLUS_1989 11123294 // = 1989 +#define IQ_I_U_VALUE_PLUS_1990 11128886 // = 1990 +#define IQ_I_U_VALUE_PLUS_1991 11134479 // = 1991 +#define IQ_I_U_VALUE_PLUS_1992 11140071 // = 1992 +#define IQ_I_U_VALUE_PLUS_1993 11145663 // = 1993 +#define IQ_I_U_VALUE_PLUS_1994 11151256 // = 1994 +#define IQ_I_U_VALUE_PLUS_1995 11156848 // = 1995 +#define IQ_I_U_VALUE_PLUS_1996 11162441 // = 1996 +#define IQ_I_U_VALUE_PLUS_1997 11168033 // = 1997 +#define IQ_I_U_VALUE_PLUS_1998 11173625 // = 1998 +#define IQ_I_U_VALUE_PLUS_1999 11179218 // = 1999 +#define IQ_I_U_VALUE_PLUS_2000 11184810 // = 2000 +#define IQ_I_U_VALUE_PLUS_2001 11190403 // = 2001 +#define IQ_I_U_VALUE_PLUS_2002 11195995 // = 2002 +#define IQ_I_U_VALUE_PLUS_2003 11201587 // = 2003 +#define IQ_I_U_VALUE_PLUS_2004 11207180 // = 2004 +#define IQ_I_U_VALUE_PLUS_2005 11212772 // = 2005 +#define IQ_I_U_VALUE_PLUS_2006 11218365 // = 2006 +#define IQ_I_U_VALUE_PLUS_2007 11223957 // = 2007 +#define IQ_I_U_VALUE_PLUS_2008 11229549 // = 2008 +#define IQ_I_U_VALUE_PLUS_2009 11235142 // = 2009 +#define IQ_I_U_VALUE_PLUS_2010 11240734 // = 2010 +#define IQ_I_U_VALUE_PLUS_2011 11246327 // = 2011 +#define IQ_I_U_VALUE_PLUS_2012 11251919 // = 2012 +#define IQ_I_U_VALUE_PLUS_2013 11257511 // = 2013 +#define IQ_I_U_VALUE_PLUS_2014 11263104 // = 2014 +#define IQ_I_U_VALUE_PLUS_2015 11268696 // = 2015 +#define IQ_I_U_VALUE_PLUS_2016 11274289 // = 2016 +#define IQ_I_U_VALUE_PLUS_2017 11279881 // = 2017 +#define IQ_I_U_VALUE_PLUS_2018 11285473 // = 2018 +#define IQ_I_U_VALUE_PLUS_2019 11291066 // = 2019 +#define IQ_I_U_VALUE_PLUS_2020 11296658 // = 2020 +#define IQ_I_U_VALUE_PLUS_2021 11302251 // = 2021 +#define IQ_I_U_VALUE_PLUS_2022 11307843 // = 2022 +#define IQ_I_U_VALUE_PLUS_2023 11313435 // = 2023 +#define IQ_I_U_VALUE_PLUS_2024 11319028 // = 2024 +#define IQ_I_U_VALUE_PLUS_2025 11324620 // = 2025 +#define IQ_I_U_VALUE_PLUS_2026 11330213 // = 2026 +#define IQ_I_U_VALUE_PLUS_2027 11335805 // = 2027 +#define IQ_I_U_VALUE_PLUS_2028 11341398 // = 2028 +#define IQ_I_U_VALUE_PLUS_2029 11346990 // = 2029 +#define IQ_I_U_VALUE_PLUS_2030 11352582 // = 2030 +#define IQ_I_U_VALUE_PLUS_2031 11358175 // = 2031 +#define IQ_I_U_VALUE_PLUS_2032 11363767 // = 2032 +#define IQ_I_U_VALUE_PLUS_2033 11369360 // = 2033 +#define IQ_I_U_VALUE_PLUS_2034 11374952 // = 2034 +#define IQ_I_U_VALUE_PLUS_2035 11380544 // = 2035 +#define IQ_I_U_VALUE_PLUS_2036 11386137 // = 2036 +#define IQ_I_U_VALUE_PLUS_2037 11391729 // = 2037 +#define IQ_I_U_VALUE_PLUS_2038 11397322 // = 2038 +#define IQ_I_U_VALUE_PLUS_2039 11402914 // = 2039 +#define IQ_I_U_VALUE_PLUS_2040 11408506 // = 2040 +#define IQ_I_U_VALUE_PLUS_2041 11414099 // = 2041 +#define IQ_I_U_VALUE_PLUS_2042 11419691 // = 2042 +#define IQ_I_U_VALUE_PLUS_2043 11425284 // = 2043 +#define IQ_I_U_VALUE_PLUS_2044 11430876 // = 2044 +#define IQ_I_U_VALUE_PLUS_2045 11436468 // = 2045 +#define IQ_I_U_VALUE_PLUS_2046 11442061 // = 2046 +#define IQ_I_U_VALUE_PLUS_2047 11447653 // = 2047 +#define IQ_I_U_VALUE_PLUS_2048 11453246 // = 2048 +#define IQ_I_U_VALUE_PLUS_2049 11458838 // = 2049 +#define IQ_I_U_VALUE_PLUS_2050 11464430 // = 2050 +#define IQ_I_U_VALUE_PLUS_2051 11470023 // = 2051 +#define IQ_I_U_VALUE_PLUS_2052 11475615 // = 2052 +#define IQ_I_U_VALUE_PLUS_2053 11481208 // = 2053 +#define IQ_I_U_VALUE_PLUS_2054 11486800 // = 2054 +#define IQ_I_U_VALUE_PLUS_2055 11492392 // = 2055 +#define IQ_I_U_VALUE_PLUS_2056 11497985 // = 2056 +#define IQ_I_U_VALUE_PLUS_2057 11503577 // = 2057 +#define IQ_I_U_VALUE_PLUS_2058 11509170 // = 2058 +#define IQ_I_U_VALUE_PLUS_2059 11514762 // = 2059 +#define IQ_I_U_VALUE_PLUS_2060 11520354 // = 2060 +#define IQ_I_U_VALUE_PLUS_2061 11525947 // = 2061 +#define IQ_I_U_VALUE_PLUS_2062 11531539 // = 2062 +#define IQ_I_U_VALUE_PLUS_2063 11537132 // = 2063 +#define IQ_I_U_VALUE_PLUS_2064 11542724 // = 2064 +#define IQ_I_U_VALUE_PLUS_2065 11548317 // = 2065 +#define IQ_I_U_VALUE_PLUS_2066 11553909 // = 2066 +#define IQ_I_U_VALUE_PLUS_2067 11559501 // = 2067 +#define IQ_I_U_VALUE_PLUS_2068 11565094 // = 2068 +#define IQ_I_U_VALUE_PLUS_2069 11570686 // = 2069 +#define IQ_I_U_VALUE_PLUS_2070 11576279 // = 2070 +#define IQ_I_U_VALUE_PLUS_2071 11581871 // = 2071 +#define IQ_I_U_VALUE_PLUS_2072 11587463 // = 2072 +#define IQ_I_U_VALUE_PLUS_2073 11593056 // = 2073 +#define IQ_I_U_VALUE_PLUS_2074 11598648 // = 2074 +#define IQ_I_U_VALUE_PLUS_2075 11604241 // = 2075 +#define IQ_I_U_VALUE_PLUS_2076 11609833 // = 2076 +#define IQ_I_U_VALUE_PLUS_2077 11615425 // = 2077 +#define IQ_I_U_VALUE_PLUS_2078 11621018 // = 2078 +#define IQ_I_U_VALUE_PLUS_2079 11626610 // = 2079 +#define IQ_I_U_VALUE_PLUS_2080 11632203 // = 2080 +#define IQ_I_U_VALUE_PLUS_2081 11637795 // = 2081 +#define IQ_I_U_VALUE_PLUS_2082 11643387 // = 2082 +#define IQ_I_U_VALUE_PLUS_2083 11648980 // = 2083 +#define IQ_I_U_VALUE_PLUS_2084 11654572 // = 2084 +#define IQ_I_U_VALUE_PLUS_2085 11660165 // = 2085 +#define IQ_I_U_VALUE_PLUS_2086 11665757 // = 2086 +#define IQ_I_U_VALUE_PLUS_2087 11671349 // = 2087 +#define IQ_I_U_VALUE_PLUS_2088 11676942 // = 2088 +#define IQ_I_U_VALUE_PLUS_2089 11682534 // = 2089 +#define IQ_I_U_VALUE_PLUS_2090 11688127 // = 2090 +#define IQ_I_U_VALUE_PLUS_2091 11693719 // = 2091 +#define IQ_I_U_VALUE_PLUS_2092 11699311 // = 2092 +#define IQ_I_U_VALUE_PLUS_2093 11704904 // = 2093 +#define IQ_I_U_VALUE_PLUS_2094 11710496 // = 2094 +#define IQ_I_U_VALUE_PLUS_2095 11716089 // = 2095 +#define IQ_I_U_VALUE_PLUS_2096 11721681 // = 2096 +#define IQ_I_U_VALUE_PLUS_2097 11727273 // = 2097 +#define IQ_I_U_VALUE_PLUS_2098 11732866 // = 2098 +#define IQ_I_U_VALUE_PLUS_2099 11738458 // = 2099 +#define IQ_I_U_VALUE_PLUS_2100 11744051 // = 2100 +#define IQ_I_U_VALUE_PLUS_2101 11749643 // = 2101 +#define IQ_I_U_VALUE_PLUS_2102 11755236 // = 2102 +#define IQ_I_U_VALUE_PLUS_2103 11760828 // = 2103 +#define IQ_I_U_VALUE_PLUS_2104 11766420 // = 2104 +#define IQ_I_U_VALUE_PLUS_2105 11772013 // = 2105 +#define IQ_I_U_VALUE_PLUS_2106 11777605 // = 2106 +#define IQ_I_U_VALUE_PLUS_2107 11783198 // = 2107 +#define IQ_I_U_VALUE_PLUS_2108 11788790 // = 2108 +#define IQ_I_U_VALUE_PLUS_2109 11794382 // = 2109 +#define IQ_I_U_VALUE_PLUS_2110 11799975 // = 2110 +#define IQ_I_U_VALUE_PLUS_2111 11805567 // = 2111 +#define IQ_I_U_VALUE_PLUS_2112 11811160 // = 2112 +#define IQ_I_U_VALUE_PLUS_2113 11816752 // = 2113 +#define IQ_I_U_VALUE_PLUS_2114 11822344 // = 2114 +#define IQ_I_U_VALUE_PLUS_2115 11827937 // = 2115 +#define IQ_I_U_VALUE_PLUS_2116 11833529 // = 2116 +#define IQ_I_U_VALUE_PLUS_2117 11839122 // = 2117 +#define IQ_I_U_VALUE_PLUS_2118 11844714 // = 2118 +#define IQ_I_U_VALUE_PLUS_2119 11850306 // = 2119 +#define IQ_I_U_VALUE_PLUS_2120 11855899 // = 2120 +#define IQ_I_U_VALUE_PLUS_2121 11861491 // = 2121 +#define IQ_I_U_VALUE_PLUS_2122 11867084 // = 2122 +#define IQ_I_U_VALUE_PLUS_2123 11872676 // = 2123 +#define IQ_I_U_VALUE_PLUS_2124 11878268 // = 2124 +#define IQ_I_U_VALUE_PLUS_2125 11883861 // = 2125 +#define IQ_I_U_VALUE_PLUS_2126 11889453 // = 2126 +#define IQ_I_U_VALUE_PLUS_2127 11895046 // = 2127 +#define IQ_I_U_VALUE_PLUS_2128 11900638 // = 2128 +#define IQ_I_U_VALUE_PLUS_2129 11906230 // = 2129 +#define IQ_I_U_VALUE_PLUS_2130 11911823 // = 2130 +#define IQ_I_U_VALUE_PLUS_2131 11917415 // = 2131 +#define IQ_I_U_VALUE_PLUS_2132 11923008 // = 2132 +#define IQ_I_U_VALUE_PLUS_2133 11928600 // = 2133 +#define IQ_I_U_VALUE_PLUS_2134 11934192 // = 2134 +#define IQ_I_U_VALUE_PLUS_2135 11939785 // = 2135 +#define IQ_I_U_VALUE_PLUS_2136 11945377 // = 2136 +#define IQ_I_U_VALUE_PLUS_2137 11950970 // = 2137 +#define IQ_I_U_VALUE_PLUS_2138 11956562 // = 2138 +#define IQ_I_U_VALUE_PLUS_2139 11962155 // = 2139 +#define IQ_I_U_VALUE_PLUS_2140 11967747 // = 2140 +#define IQ_I_U_VALUE_PLUS_2141 11973339 // = 2141 +#define IQ_I_U_VALUE_PLUS_2142 11978932 // = 2142 +#define IQ_I_U_VALUE_PLUS_2143 11984524 // = 2143 +#define IQ_I_U_VALUE_PLUS_2144 11990117 // = 2144 +#define IQ_I_U_VALUE_PLUS_2145 11995709 // = 2145 +#define IQ_I_U_VALUE_PLUS_2146 12001301 // = 2146 +#define IQ_I_U_VALUE_PLUS_2147 12006894 // = 2147 +#define IQ_I_U_VALUE_PLUS_2148 12012486 // = 2148 +#define IQ_I_U_VALUE_PLUS_2149 12018079 // = 2149 +#define IQ_I_U_VALUE_PLUS_2150 12023671 // = 2150 +#define IQ_I_U_VALUE_PLUS_2151 12029263 // = 2151 +#define IQ_I_U_VALUE_PLUS_2152 12034856 // = 2152 +#define IQ_I_U_VALUE_PLUS_2153 12040448 // = 2153 +#define IQ_I_U_VALUE_PLUS_2154 12046041 // = 2154 +#define IQ_I_U_VALUE_PLUS_2155 12051633 // = 2155 +#define IQ_I_U_VALUE_PLUS_2156 12057225 // = 2156 +#define IQ_I_U_VALUE_PLUS_2157 12062818 // = 2157 +#define IQ_I_U_VALUE_PLUS_2158 12068410 // = 2158 +#define IQ_I_U_VALUE_PLUS_2159 12074003 // = 2159 +#define IQ_I_U_VALUE_PLUS_2160 12079595 // = 2160 +#define IQ_I_U_VALUE_PLUS_2161 12085187 // = 2161 +#define IQ_I_U_VALUE_PLUS_2162 12090780 // = 2162 +#define IQ_I_U_VALUE_PLUS_2163 12096372 // = 2163 +#define IQ_I_U_VALUE_PLUS_2164 12101965 // = 2164 +#define IQ_I_U_VALUE_PLUS_2165 12107557 // = 2165 +#define IQ_I_U_VALUE_PLUS_2166 12113149 // = 2166 +#define IQ_I_U_VALUE_PLUS_2167 12118742 // = 2167 +#define IQ_I_U_VALUE_PLUS_2168 12124334 // = 2168 +#define IQ_I_U_VALUE_PLUS_2169 12129927 // = 2169 +#define IQ_I_U_VALUE_PLUS_2170 12135519 // = 2170 +#define IQ_I_U_VALUE_PLUS_2171 12141111 // = 2171 +#define IQ_I_U_VALUE_PLUS_2172 12146704 // = 2172 +#define IQ_I_U_VALUE_PLUS_2173 12152296 // = 2173 +#define IQ_I_U_VALUE_PLUS_2174 12157889 // = 2174 +#define IQ_I_U_VALUE_PLUS_2175 12163481 // = 2175 +#define IQ_I_U_VALUE_PLUS_2176 12169074 // = 2176 +#define IQ_I_U_VALUE_PLUS_2177 12174666 // = 2177 +#define IQ_I_U_VALUE_PLUS_2178 12180258 // = 2178 +#define IQ_I_U_VALUE_PLUS_2179 12185851 // = 2179 +#define IQ_I_U_VALUE_PLUS_2180 12191443 // = 2180 +#define IQ_I_U_VALUE_PLUS_2181 12197036 // = 2181 +#define IQ_I_U_VALUE_PLUS_2182 12202628 // = 2182 +#define IQ_I_U_VALUE_PLUS_2183 12208220 // = 2183 +#define IQ_I_U_VALUE_PLUS_2184 12213813 // = 2184 +#define IQ_I_U_VALUE_PLUS_2185 12219405 // = 2185 +#define IQ_I_U_VALUE_PLUS_2186 12224998 // = 2186 +#define IQ_I_U_VALUE_PLUS_2187 12230590 // = 2187 +#define IQ_I_U_VALUE_PLUS_2188 12236182 // = 2188 +#define IQ_I_U_VALUE_PLUS_2189 12241775 // = 2189 +#define IQ_I_U_VALUE_PLUS_2190 12247367 // = 2190 +#define IQ_I_U_VALUE_PLUS_2191 12252960 // = 2191 +#define IQ_I_U_VALUE_PLUS_2192 12258552 // = 2192 +#define IQ_I_U_VALUE_PLUS_2193 12264144 // = 2193 +#define IQ_I_U_VALUE_PLUS_2194 12269737 // = 2194 +#define IQ_I_U_VALUE_PLUS_2195 12275329 // = 2195 +#define IQ_I_U_VALUE_PLUS_2196 12280922 // = 2196 +#define IQ_I_U_VALUE_PLUS_2197 12286514 // = 2197 +#define IQ_I_U_VALUE_PLUS_2198 12292106 // = 2198 +#define IQ_I_U_VALUE_PLUS_2199 12297699 // = 2199 +#define IQ_I_U_VALUE_PLUS_2200 12303291 // = 2200 +#define IQ_I_U_VALUE_PLUS_2201 12308884 // = 2201 +#define IQ_I_U_VALUE_PLUS_2202 12314476 // = 2202 +#define IQ_I_U_VALUE_PLUS_2203 12320068 // = 2203 +#define IQ_I_U_VALUE_PLUS_2204 12325661 // = 2204 +#define IQ_I_U_VALUE_PLUS_2205 12331253 // = 2205 +#define IQ_I_U_VALUE_PLUS_2206 12336846 // = 2206 +#define IQ_I_U_VALUE_PLUS_2207 12342438 // = 2207 +#define IQ_I_U_VALUE_PLUS_2208 12348030 // = 2208 +#define IQ_I_U_VALUE_PLUS_2209 12353623 // = 2209 +#define IQ_I_U_VALUE_PLUS_2210 12359215 // = 2210 +#define IQ_I_U_VALUE_PLUS_2211 12364808 // = 2211 +#define IQ_I_U_VALUE_PLUS_2212 12370400 // = 2212 +#define IQ_I_U_VALUE_PLUS_2213 12375993 // = 2213 +#define IQ_I_U_VALUE_PLUS_2214 12381585 // = 2214 +#define IQ_I_U_VALUE_PLUS_2215 12387177 // = 2215 +#define IQ_I_U_VALUE_PLUS_2216 12392770 // = 2216 +#define IQ_I_U_VALUE_PLUS_2217 12398362 // = 2217 +#define IQ_I_U_VALUE_PLUS_2218 12403955 // = 2218 +#define IQ_I_U_VALUE_PLUS_2219 12409547 // = 2219 +#define IQ_I_U_VALUE_PLUS_2220 12415139 // = 2220 +#define IQ_I_U_VALUE_PLUS_2221 12420732 // = 2221 +#define IQ_I_U_VALUE_PLUS_2222 12426324 // = 2222 +#define IQ_I_U_VALUE_PLUS_2223 12431917 // = 2223 +#define IQ_I_U_VALUE_PLUS_2224 12437509 // = 2224 +#define IQ_I_U_VALUE_PLUS_2225 12443101 // = 2225 +#define IQ_I_U_VALUE_PLUS_2226 12448694 // = 2226 +#define IQ_I_U_VALUE_PLUS_2227 12454286 // = 2227 +#define IQ_I_U_VALUE_PLUS_2228 12459879 // = 2228 +#define IQ_I_U_VALUE_PLUS_2229 12465471 // = 2229 +#define IQ_I_U_VALUE_PLUS_2230 12471063 // = 2230 +#define IQ_I_U_VALUE_PLUS_2231 12476656 // = 2231 +#define IQ_I_U_VALUE_PLUS_2232 12482248 // = 2232 +#define IQ_I_U_VALUE_PLUS_2233 12487841 // = 2233 +#define IQ_I_U_VALUE_PLUS_2234 12493433 // = 2234 +#define IQ_I_U_VALUE_PLUS_2235 12499025 // = 2235 +#define IQ_I_U_VALUE_PLUS_2236 12504618 // = 2236 +#define IQ_I_U_VALUE_PLUS_2237 12510210 // = 2237 +#define IQ_I_U_VALUE_PLUS_2238 12515803 // = 2238 +#define IQ_I_U_VALUE_PLUS_2239 12521395 // = 2239 +#define IQ_I_U_VALUE_PLUS_2240 12526987 // = 2240 +#define IQ_I_U_VALUE_PLUS_2241 12532580 // = 2241 +#define IQ_I_U_VALUE_PLUS_2242 12538172 // = 2242 +#define IQ_I_U_VALUE_PLUS_2243 12543765 // = 2243 +#define IQ_I_U_VALUE_PLUS_2244 12549357 // = 2244 +#define IQ_I_U_VALUE_PLUS_2245 12554949 // = 2245 +#define IQ_I_U_VALUE_PLUS_2246 12560542 // = 2246 +#define IQ_I_U_VALUE_PLUS_2247 12566134 // = 2247 +#define IQ_I_U_VALUE_PLUS_2248 12571727 // = 2248 +#define IQ_I_U_VALUE_PLUS_2249 12577319 // = 2249 +#define IQ_I_U_VALUE_PLUS_2250 12582912 // = 2250 +#define IQ_I_U_VALUE_PLUS_2251 12588504 // = 2251 +#define IQ_I_U_VALUE_PLUS_2252 12594096 // = 2252 +#define IQ_I_U_VALUE_PLUS_2253 12599689 // = 2253 +#define IQ_I_U_VALUE_PLUS_2254 12605281 // = 2254 +#define IQ_I_U_VALUE_PLUS_2255 12610874 // = 2255 +#define IQ_I_U_VALUE_PLUS_2256 12616466 // = 2256 +#define IQ_I_U_VALUE_PLUS_2257 12622058 // = 2257 +#define IQ_I_U_VALUE_PLUS_2258 12627651 // = 2258 +#define IQ_I_U_VALUE_PLUS_2259 12633243 // = 2259 +#define IQ_I_U_VALUE_PLUS_2260 12638836 // = 2260 +#define IQ_I_U_VALUE_PLUS_2261 12644428 // = 2261 +#define IQ_I_U_VALUE_PLUS_2262 12650020 // = 2262 +#define IQ_I_U_VALUE_PLUS_2263 12655613 // = 2263 +#define IQ_I_U_VALUE_PLUS_2264 12661205 // = 2264 +#define IQ_I_U_VALUE_PLUS_2265 12666798 // = 2265 +#define IQ_I_U_VALUE_PLUS_2266 12672390 // = 2266 +#define IQ_I_U_VALUE_PLUS_2267 12677982 // = 2267 +#define IQ_I_U_VALUE_PLUS_2268 12683575 // = 2268 +#define IQ_I_U_VALUE_PLUS_2269 12689167 // = 2269 +#define IQ_I_U_VALUE_PLUS_2270 12694760 // = 2270 +#define IQ_I_U_VALUE_PLUS_2271 12700352 // = 2271 +#define IQ_I_U_VALUE_PLUS_2272 12705944 // = 2272 +#define IQ_I_U_VALUE_PLUS_2273 12711537 // = 2273 +#define IQ_I_U_VALUE_PLUS_2274 12717129 // = 2274 +#define IQ_I_U_VALUE_PLUS_2275 12722722 // = 2275 +#define IQ_I_U_VALUE_PLUS_2276 12728314 // = 2276 +#define IQ_I_U_VALUE_PLUS_2277 12733906 // = 2277 +#define IQ_I_U_VALUE_PLUS_2278 12739499 // = 2278 +#define IQ_I_U_VALUE_PLUS_2279 12745091 // = 2279 +#define IQ_I_U_VALUE_PLUS_2280 12750684 // = 2280 +#define IQ_I_U_VALUE_PLUS_2281 12756276 // = 2281 +#define IQ_I_U_VALUE_PLUS_2282 12761868 // = 2282 +#define IQ_I_U_VALUE_PLUS_2283 12767461 // = 2283 +#define IQ_I_U_VALUE_PLUS_2284 12773053 // = 2284 +#define IQ_I_U_VALUE_PLUS_2285 12778646 // = 2285 +#define IQ_I_U_VALUE_PLUS_2286 12784238 // = 2286 +#define IQ_I_U_VALUE_PLUS_2287 12789830 // = 2287 +#define IQ_I_U_VALUE_PLUS_2288 12795423 // = 2288 +#define IQ_I_U_VALUE_PLUS_2289 12801015 // = 2289 +#define IQ_I_U_VALUE_PLUS_2290 12806608 // = 2290 +#define IQ_I_U_VALUE_PLUS_2291 12812200 // = 2291 +#define IQ_I_U_VALUE_PLUS_2292 12817793 // = 2292 +#define IQ_I_U_VALUE_PLUS_2293 12823385 // = 2293 +#define IQ_I_U_VALUE_PLUS_2294 12828977 // = 2294 +#define IQ_I_U_VALUE_PLUS_2295 12834570 // = 2295 +#define IQ_I_U_VALUE_PLUS_2296 12840162 // = 2296 +#define IQ_I_U_VALUE_PLUS_2297 12845755 // = 2297 +#define IQ_I_U_VALUE_PLUS_2298 12851347 // = 2298 +#define IQ_I_U_VALUE_PLUS_2299 12856939 // = 2299 +#define IQ_I_U_VALUE_PLUS_2300 12862532 // = 2300 +#define IQ_I_U_VALUE_PLUS_2301 12868124 // = 2301 +#define IQ_I_U_VALUE_PLUS_2302 12873717 // = 2302 +#define IQ_I_U_VALUE_PLUS_2303 12879309 // = 2303 +#define IQ_I_U_VALUE_PLUS_2304 12884901 // = 2304 +#define IQ_I_U_VALUE_PLUS_2305 12890494 // = 2305 +#define IQ_I_U_VALUE_PLUS_2306 12896086 // = 2306 +#define IQ_I_U_VALUE_PLUS_2307 12901679 // = 2307 +#define IQ_I_U_VALUE_PLUS_2308 12907271 // = 2308 +#define IQ_I_U_VALUE_PLUS_2309 12912863 // = 2309 +#define IQ_I_U_VALUE_PLUS_2310 12918456 // = 2310 +#define IQ_I_U_VALUE_PLUS_2311 12924048 // = 2311 +#define IQ_I_U_VALUE_PLUS_2312 12929641 // = 2312 +#define IQ_I_U_VALUE_PLUS_2313 12935233 // = 2313 +#define IQ_I_U_VALUE_PLUS_2314 12940825 // = 2314 +#define IQ_I_U_VALUE_PLUS_2315 12946418 // = 2315 +#define IQ_I_U_VALUE_PLUS_2316 12952010 // = 2316 +#define IQ_I_U_VALUE_PLUS_2317 12957603 // = 2317 +#define IQ_I_U_VALUE_PLUS_2318 12963195 // = 2318 +#define IQ_I_U_VALUE_PLUS_2319 12968787 // = 2319 +#define IQ_I_U_VALUE_PLUS_2320 12974380 // = 2320 +#define IQ_I_U_VALUE_PLUS_2321 12979972 // = 2321 +#define IQ_I_U_VALUE_PLUS_2322 12985565 // = 2322 +#define IQ_I_U_VALUE_PLUS_2323 12991157 // = 2323 +#define IQ_I_U_VALUE_PLUS_2324 12996749 // = 2324 +#define IQ_I_U_VALUE_PLUS_2325 13002342 // = 2325 +#define IQ_I_U_VALUE_PLUS_2326 13007934 // = 2326 +#define IQ_I_U_VALUE_PLUS_2327 13013527 // = 2327 +#define IQ_I_U_VALUE_PLUS_2328 13019119 // = 2328 +#define IQ_I_U_VALUE_PLUS_2329 13024712 // = 2329 +#define IQ_I_U_VALUE_PLUS_2330 13030304 // = 2330 +#define IQ_I_U_VALUE_PLUS_2331 13035896 // = 2331 +#define IQ_I_U_VALUE_PLUS_2332 13041489 // = 2332 +#define IQ_I_U_VALUE_PLUS_2333 13047081 // = 2333 +#define IQ_I_U_VALUE_PLUS_2334 13052674 // = 2334 +#define IQ_I_U_VALUE_PLUS_2335 13058266 // = 2335 +#define IQ_I_U_VALUE_PLUS_2336 13063858 // = 2336 +#define IQ_I_U_VALUE_PLUS_2337 13069451 // = 2337 +#define IQ_I_U_VALUE_PLUS_2338 13075043 // = 2338 +#define IQ_I_U_VALUE_PLUS_2339 13080636 // = 2339 +#define IQ_I_U_VALUE_PLUS_2340 13086228 // = 2340 +#define IQ_I_U_VALUE_PLUS_2341 13091820 // = 2341 +#define IQ_I_U_VALUE_PLUS_2342 13097413 // = 2342 +#define IQ_I_U_VALUE_PLUS_2343 13103005 // = 2343 +#define IQ_I_U_VALUE_PLUS_2344 13108598 // = 2344 +#define IQ_I_U_VALUE_PLUS_2345 13114190 // = 2345 +#define IQ_I_U_VALUE_PLUS_2346 13119782 // = 2346 +#define IQ_I_U_VALUE_PLUS_2347 13125375 // = 2347 +#define IQ_I_U_VALUE_PLUS_2348 13130967 // = 2348 +#define IQ_I_U_VALUE_PLUS_2349 13136560 // = 2349 +#define IQ_I_U_VALUE_PLUS_2350 13142152 // = 2350 +#define IQ_I_U_VALUE_PLUS_2351 13147744 // = 2351 +#define IQ_I_U_VALUE_PLUS_2352 13153337 // = 2352 +#define IQ_I_U_VALUE_PLUS_2353 13158929 // = 2353 +#define IQ_I_U_VALUE_PLUS_2354 13164522 // = 2354 +#define IQ_I_U_VALUE_PLUS_2355 13170114 // = 2355 +#define IQ_I_U_VALUE_PLUS_2356 13175706 // = 2356 +#define IQ_I_U_VALUE_PLUS_2357 13181299 // = 2357 +#define IQ_I_U_VALUE_PLUS_2358 13186891 // = 2358 +#define IQ_I_U_VALUE_PLUS_2359 13192484 // = 2359 +#define IQ_I_U_VALUE_PLUS_2360 13198076 // = 2360 +#define IQ_I_U_VALUE_PLUS_2361 13203668 // = 2361 +#define IQ_I_U_VALUE_PLUS_2362 13209261 // = 2362 +#define IQ_I_U_VALUE_PLUS_2363 13214853 // = 2363 +#define IQ_I_U_VALUE_PLUS_2364 13220446 // = 2364 +#define IQ_I_U_VALUE_PLUS_2365 13226038 // = 2365 +#define IQ_I_U_VALUE_PLUS_2366 13231631 // = 2366 +#define IQ_I_U_VALUE_PLUS_2367 13237223 // = 2367 +#define IQ_I_U_VALUE_PLUS_2368 13242815 // = 2368 +#define IQ_I_U_VALUE_PLUS_2369 13248408 // = 2369 +#define IQ_I_U_VALUE_PLUS_2370 13254000 // = 2370 +#define IQ_I_U_VALUE_PLUS_2371 13259593 // = 2371 +#define IQ_I_U_VALUE_PLUS_2372 13265185 // = 2372 +#define IQ_I_U_VALUE_PLUS_2373 13270777 // = 2373 +#define IQ_I_U_VALUE_PLUS_2374 13276370 // = 2374 +#define IQ_I_U_VALUE_PLUS_2375 13281962 // = 2375 +#define IQ_I_U_VALUE_PLUS_2376 13287555 // = 2376 +#define IQ_I_U_VALUE_PLUS_2377 13293147 // = 2377 +#define IQ_I_U_VALUE_PLUS_2378 13298739 // = 2378 +#define IQ_I_U_VALUE_PLUS_2379 13304332 // = 2379 +#define IQ_I_U_VALUE_PLUS_2380 13309924 // = 2380 +#define IQ_I_U_VALUE_PLUS_2381 13315517 // = 2381 +#define IQ_I_U_VALUE_PLUS_2382 13321109 // = 2382 +#define IQ_I_U_VALUE_PLUS_2383 13326701 // = 2383 +#define IQ_I_U_VALUE_PLUS_2384 13332294 // = 2384 +#define IQ_I_U_VALUE_PLUS_2385 13337886 // = 2385 +#define IQ_I_U_VALUE_PLUS_2386 13343479 // = 2386 +#define IQ_I_U_VALUE_PLUS_2387 13349071 // = 2387 +#define IQ_I_U_VALUE_PLUS_2388 13354663 // = 2388 +#define IQ_I_U_VALUE_PLUS_2389 13360256 // = 2389 +#define IQ_I_U_VALUE_PLUS_2390 13365848 // = 2390 +#define IQ_I_U_VALUE_PLUS_2391 13371441 // = 2391 +#define IQ_I_U_VALUE_PLUS_2392 13377033 // = 2392 +#define IQ_I_U_VALUE_PLUS_2393 13382625 // = 2393 +#define IQ_I_U_VALUE_PLUS_2394 13388218 // = 2394 +#define IQ_I_U_VALUE_PLUS_2395 13393810 // = 2395 +#define IQ_I_U_VALUE_PLUS_2396 13399403 // = 2396 +#define IQ_I_U_VALUE_PLUS_2397 13404995 // = 2397 +#define IQ_I_U_VALUE_PLUS_2398 13410587 // = 2398 +#define IQ_I_U_VALUE_PLUS_2399 13416180 // = 2399 +#define IQ_I_U_VALUE_PLUS_2400 13421772 // = 2400 +#define IQ_I_U_VALUE_PLUS_2401 13427365 // = 2401 +#define IQ_I_U_VALUE_PLUS_2402 13432957 // = 2402 +#define IQ_I_U_VALUE_PLUS_2403 13438550 // = 2403 +#define IQ_I_U_VALUE_PLUS_2404 13444142 // = 2404 +#define IQ_I_U_VALUE_PLUS_2405 13449734 // = 2405 +#define IQ_I_U_VALUE_PLUS_2406 13455327 // = 2406 +#define IQ_I_U_VALUE_PLUS_2407 13460919 // = 2407 +#define IQ_I_U_VALUE_PLUS_2408 13466512 // = 2408 +#define IQ_I_U_VALUE_PLUS_2409 13472104 // = 2409 +#define IQ_I_U_VALUE_PLUS_2410 13477696 // = 2410 +#define IQ_I_U_VALUE_PLUS_2411 13483289 // = 2411 +#define IQ_I_U_VALUE_PLUS_2412 13488881 // = 2412 +#define IQ_I_U_VALUE_PLUS_2413 13494474 // = 2413 +#define IQ_I_U_VALUE_PLUS_2414 13500066 // = 2414 +#define IQ_I_U_VALUE_PLUS_2415 13505658 // = 2415 +#define IQ_I_U_VALUE_PLUS_2416 13511251 // = 2416 +#define IQ_I_U_VALUE_PLUS_2417 13516843 // = 2417 +#define IQ_I_U_VALUE_PLUS_2418 13522436 // = 2418 +#define IQ_I_U_VALUE_PLUS_2419 13528028 // = 2419 +#define IQ_I_U_VALUE_PLUS_2420 13533620 // = 2420 +#define IQ_I_U_VALUE_PLUS_2421 13539213 // = 2421 +#define IQ_I_U_VALUE_PLUS_2422 13544805 // = 2422 +#define IQ_I_U_VALUE_PLUS_2423 13550398 // = 2423 +#define IQ_I_U_VALUE_PLUS_2424 13555990 // = 2424 +#define IQ_I_U_VALUE_PLUS_2425 13561582 // = 2425 +#define IQ_I_U_VALUE_PLUS_2426 13567175 // = 2426 +#define IQ_I_U_VALUE_PLUS_2427 13572767 // = 2427 +#define IQ_I_U_VALUE_PLUS_2428 13578360 // = 2428 +#define IQ_I_U_VALUE_PLUS_2429 13583952 // = 2429 +#define IQ_I_U_VALUE_PLUS_2430 13589544 // = 2430 +#define IQ_I_U_VALUE_PLUS_2431 13595137 // = 2431 +#define IQ_I_U_VALUE_PLUS_2432 13600729 // = 2432 +#define IQ_I_U_VALUE_PLUS_2433 13606322 // = 2433 +#define IQ_I_U_VALUE_PLUS_2434 13611914 // = 2434 +#define IQ_I_U_VALUE_PLUS_2435 13617506 // = 2435 +#define IQ_I_U_VALUE_PLUS_2436 13623099 // = 2436 +#define IQ_I_U_VALUE_PLUS_2437 13628691 // = 2437 +#define IQ_I_U_VALUE_PLUS_2438 13634284 // = 2438 +#define IQ_I_U_VALUE_PLUS_2439 13639876 // = 2439 +#define IQ_I_U_VALUE_PLUS_2440 13645469 // = 2440 +#define IQ_I_U_VALUE_PLUS_2441 13651061 // = 2441 +#define IQ_I_U_VALUE_PLUS_2442 13656653 // = 2442 +#define IQ_I_U_VALUE_PLUS_2443 13662246 // = 2443 +#define IQ_I_U_VALUE_PLUS_2444 13667838 // = 2444 +#define IQ_I_U_VALUE_PLUS_2445 13673431 // = 2445 +#define IQ_I_U_VALUE_PLUS_2446 13679023 // = 2446 +#define IQ_I_U_VALUE_PLUS_2447 13684615 // = 2447 +#define IQ_I_U_VALUE_PLUS_2448 13690208 // = 2448 +#define IQ_I_U_VALUE_PLUS_2449 13695800 // = 2449 +#define IQ_I_U_VALUE_PLUS_2450 13701393 // = 2450 +#define IQ_I_U_VALUE_PLUS_2451 13706985 // = 2451 +#define IQ_I_U_VALUE_PLUS_2452 13712577 // = 2452 +#define IQ_I_U_VALUE_PLUS_2453 13718170 // = 2453 +#define IQ_I_U_VALUE_PLUS_2454 13723762 // = 2454 +#define IQ_I_U_VALUE_PLUS_2455 13729355 // = 2455 +#define IQ_I_U_VALUE_PLUS_2456 13734947 // = 2456 +#define IQ_I_U_VALUE_PLUS_2457 13740539 // = 2457 +#define IQ_I_U_VALUE_PLUS_2458 13746132 // = 2458 +#define IQ_I_U_VALUE_PLUS_2459 13751724 // = 2459 +#define IQ_I_U_VALUE_PLUS_2460 13757317 // = 2460 +#define IQ_I_U_VALUE_PLUS_2461 13762909 // = 2461 +#define IQ_I_U_VALUE_PLUS_2462 13768501 // = 2462 +#define IQ_I_U_VALUE_PLUS_2463 13774094 // = 2463 +#define IQ_I_U_VALUE_PLUS_2464 13779686 // = 2464 +#define IQ_I_U_VALUE_PLUS_2465 13785279 // = 2465 +#define IQ_I_U_VALUE_PLUS_2466 13790871 // = 2466 +#define IQ_I_U_VALUE_PLUS_2467 13796463 // = 2467 +#define IQ_I_U_VALUE_PLUS_2468 13802056 // = 2468 +#define IQ_I_U_VALUE_PLUS_2469 13807648 // = 2469 +#define IQ_I_U_VALUE_PLUS_2470 13813241 // = 2470 +#define IQ_I_U_VALUE_PLUS_2471 13818833 // = 2471 +#define IQ_I_U_VALUE_PLUS_2472 13824425 // = 2472 +#define IQ_I_U_VALUE_PLUS_2473 13830018 // = 2473 +#define IQ_I_U_VALUE_PLUS_2474 13835610 // = 2474 +#define IQ_I_U_VALUE_PLUS_2475 13841203 // = 2475 +#define IQ_I_U_VALUE_PLUS_2476 13846795 // = 2476 +#define IQ_I_U_VALUE_PLUS_2477 13852388 // = 2477 +#define IQ_I_U_VALUE_PLUS_2478 13857980 // = 2478 +#define IQ_I_U_VALUE_PLUS_2479 13863572 // = 2479 +#define IQ_I_U_VALUE_PLUS_2480 13869165 // = 2480 +#define IQ_I_U_VALUE_PLUS_2481 13874757 // = 2481 +#define IQ_I_U_VALUE_PLUS_2482 13880350 // = 2482 +#define IQ_I_U_VALUE_PLUS_2483 13885942 // = 2483 +#define IQ_I_U_VALUE_PLUS_2484 13891534 // = 2484 +#define IQ_I_U_VALUE_PLUS_2485 13897127 // = 2485 +#define IQ_I_U_VALUE_PLUS_2486 13902719 // = 2486 +#define IQ_I_U_VALUE_PLUS_2487 13908312 // = 2487 +#define IQ_I_U_VALUE_PLUS_2488 13913904 // = 2488 +#define IQ_I_U_VALUE_PLUS_2489 13919496 // = 2489 +#define IQ_I_U_VALUE_PLUS_2490 13925089 // = 2490 +#define IQ_I_U_VALUE_PLUS_2491 13930681 // = 2491 +#define IQ_I_U_VALUE_PLUS_2492 13936274 // = 2492 +#define IQ_I_U_VALUE_PLUS_2493 13941866 // = 2493 +#define IQ_I_U_VALUE_PLUS_2494 13947458 // = 2494 +#define IQ_I_U_VALUE_PLUS_2495 13953051 // = 2495 +#define IQ_I_U_VALUE_PLUS_2496 13958643 // = 2496 +#define IQ_I_U_VALUE_PLUS_2497 13964236 // = 2497 +#define IQ_I_U_VALUE_PLUS_2498 13969828 // = 2498 +#define IQ_I_U_VALUE_PLUS_2499 13975420 // = 2499 +#define IQ_I_U_VALUE_PLUS_2500 13981013 // = 2500 +#define IQ_I_U_VALUE_PLUS_2501 13986605 // = 2501 +#define IQ_I_U_VALUE_PLUS_2502 13992198 // = 2502 +#define IQ_I_U_VALUE_PLUS_2503 13997790 // = 2503 +#define IQ_I_U_VALUE_PLUS_2504 14003382 // = 2504 +#define IQ_I_U_VALUE_PLUS_2505 14008975 // = 2505 +#define IQ_I_U_VALUE_PLUS_2506 14014567 // = 2506 +#define IQ_I_U_VALUE_PLUS_2507 14020160 // = 2507 +#define IQ_I_U_VALUE_PLUS_2508 14025752 // = 2508 +#define IQ_I_U_VALUE_PLUS_2509 14031344 // = 2509 +#define IQ_I_U_VALUE_PLUS_2510 14036937 // = 2510 +#define IQ_I_U_VALUE_PLUS_2511 14042529 // = 2511 +#define IQ_I_U_VALUE_PLUS_2512 14048122 // = 2512 +#define IQ_I_U_VALUE_PLUS_2513 14053714 // = 2513 +#define IQ_I_U_VALUE_PLUS_2514 14059307 // = 2514 +#define IQ_I_U_VALUE_PLUS_2515 14064899 // = 2515 +#define IQ_I_U_VALUE_PLUS_2516 14070491 // = 2516 +#define IQ_I_U_VALUE_PLUS_2517 14076084 // = 2517 +#define IQ_I_U_VALUE_PLUS_2518 14081676 // = 2518 +#define IQ_I_U_VALUE_PLUS_2519 14087269 // = 2519 +#define IQ_I_U_VALUE_PLUS_2520 14092861 // = 2520 +#define IQ_I_U_VALUE_PLUS_2521 14098453 // = 2521 +#define IQ_I_U_VALUE_PLUS_2522 14104046 // = 2522 +#define IQ_I_U_VALUE_PLUS_2523 14109638 // = 2523 +#define IQ_I_U_VALUE_PLUS_2524 14115231 // = 2524 +#define IQ_I_U_VALUE_PLUS_2525 14120823 // = 2525 +#define IQ_I_U_VALUE_PLUS_2526 14126415 // = 2526 +#define IQ_I_U_VALUE_PLUS_2527 14132008 // = 2527 +#define IQ_I_U_VALUE_PLUS_2528 14137600 // = 2528 +#define IQ_I_U_VALUE_PLUS_2529 14143193 // = 2529 +#define IQ_I_U_VALUE_PLUS_2530 14148785 // = 2530 +#define IQ_I_U_VALUE_PLUS_2531 14154377 // = 2531 +#define IQ_I_U_VALUE_PLUS_2532 14159970 // = 2532 +#define IQ_I_U_VALUE_PLUS_2533 14165562 // = 2533 +#define IQ_I_U_VALUE_PLUS_2534 14171155 // = 2534 +#define IQ_I_U_VALUE_PLUS_2535 14176747 // = 2535 +#define IQ_I_U_VALUE_PLUS_2536 14182339 // = 2536 +#define IQ_I_U_VALUE_PLUS_2537 14187932 // = 2537 +#define IQ_I_U_VALUE_PLUS_2538 14193524 // = 2538 +#define IQ_I_U_VALUE_PLUS_2539 14199117 // = 2539 +#define IQ_I_U_VALUE_PLUS_2540 14204709 // = 2540 +#define IQ_I_U_VALUE_PLUS_2541 14210301 // = 2541 +#define IQ_I_U_VALUE_PLUS_2542 14215894 // = 2542 +#define IQ_I_U_VALUE_PLUS_2543 14221486 // = 2543 +#define IQ_I_U_VALUE_PLUS_2544 14227079 // = 2544 +#define IQ_I_U_VALUE_PLUS_2545 14232671 // = 2545 +#define IQ_I_U_VALUE_PLUS_2546 14238263 // = 2546 +#define IQ_I_U_VALUE_PLUS_2547 14243856 // = 2547 +#define IQ_I_U_VALUE_PLUS_2548 14249448 // = 2548 +#define IQ_I_U_VALUE_PLUS_2549 14255041 // = 2549 +#define IQ_I_U_VALUE_PLUS_2550 14260633 // = 2550 +#define IQ_I_U_VALUE_PLUS_2551 14266226 // = 2551 +#define IQ_I_U_VALUE_PLUS_2552 14271818 // = 2552 +#define IQ_I_U_VALUE_PLUS_2553 14277410 // = 2553 +#define IQ_I_U_VALUE_PLUS_2554 14283003 // = 2554 +#define IQ_I_U_VALUE_PLUS_2555 14288595 // = 2555 +#define IQ_I_U_VALUE_PLUS_2556 14294188 // = 2556 +#define IQ_I_U_VALUE_PLUS_2557 14299780 // = 2557 +#define IQ_I_U_VALUE_PLUS_2558 14305372 // = 2558 +#define IQ_I_U_VALUE_PLUS_2559 14310965 // = 2559 +#define IQ_I_U_VALUE_PLUS_2560 14316557 // = 2560 +#define IQ_I_U_VALUE_PLUS_2561 14322150 // = 2561 +#define IQ_I_U_VALUE_PLUS_2562 14327742 // = 2562 +#define IQ_I_U_VALUE_PLUS_2563 14333334 // = 2563 +#define IQ_I_U_VALUE_PLUS_2564 14338927 // = 2564 +#define IQ_I_U_VALUE_PLUS_2565 14344519 // = 2565 +#define IQ_I_U_VALUE_PLUS_2566 14350112 // = 2566 +#define IQ_I_U_VALUE_PLUS_2567 14355704 // = 2567 +#define IQ_I_U_VALUE_PLUS_2568 14361296 // = 2568 +#define IQ_I_U_VALUE_PLUS_2569 14366889 // = 2569 +#define IQ_I_U_VALUE_PLUS_2570 14372481 // = 2570 +#define IQ_I_U_VALUE_PLUS_2571 14378074 // = 2571 +#define IQ_I_U_VALUE_PLUS_2572 14383666 // = 2572 +#define IQ_I_U_VALUE_PLUS_2573 14389258 // = 2573 +#define IQ_I_U_VALUE_PLUS_2574 14394851 // = 2574 +#define IQ_I_U_VALUE_PLUS_2575 14400443 // = 2575 +#define IQ_I_U_VALUE_PLUS_2576 14406036 // = 2576 +#define IQ_I_U_VALUE_PLUS_2577 14411628 // = 2577 +#define IQ_I_U_VALUE_PLUS_2578 14417220 // = 2578 +#define IQ_I_U_VALUE_PLUS_2579 14422813 // = 2579 +#define IQ_I_U_VALUE_PLUS_2580 14428405 // = 2580 +#define IQ_I_U_VALUE_PLUS_2581 14433998 // = 2581 +#define IQ_I_U_VALUE_PLUS_2582 14439590 // = 2582 +#define IQ_I_U_VALUE_PLUS_2583 14445182 // = 2583 +#define IQ_I_U_VALUE_PLUS_2584 14450775 // = 2584 +#define IQ_I_U_VALUE_PLUS_2585 14456367 // = 2585 +#define IQ_I_U_VALUE_PLUS_2586 14461960 // = 2586 +#define IQ_I_U_VALUE_PLUS_2587 14467552 // = 2587 +#define IQ_I_U_VALUE_PLUS_2588 14473145 // = 2588 +#define IQ_I_U_VALUE_PLUS_2589 14478737 // = 2589 +#define IQ_I_U_VALUE_PLUS_2590 14484329 // = 2590 +#define IQ_I_U_VALUE_PLUS_2591 14489922 // = 2591 +#define IQ_I_U_VALUE_PLUS_2592 14495514 // = 2592 +#define IQ_I_U_VALUE_PLUS_2593 14501107 // = 2593 +#define IQ_I_U_VALUE_PLUS_2594 14506699 // = 2594 +#define IQ_I_U_VALUE_PLUS_2595 14512291 // = 2595 +#define IQ_I_U_VALUE_PLUS_2596 14517884 // = 2596 +#define IQ_I_U_VALUE_PLUS_2597 14523476 // = 2597 +#define IQ_I_U_VALUE_PLUS_2598 14529069 // = 2598 +#define IQ_I_U_VALUE_PLUS_2599 14534661 // = 2599 +#define IQ_I_U_VALUE_PLUS_2600 14540253 // = 2600 +#define IQ_I_U_VALUE_PLUS_2601 14545846 // = 2601 +#define IQ_I_U_VALUE_PLUS_2602 14551438 // = 2602 +#define IQ_I_U_VALUE_PLUS_2603 14557031 // = 2603 +#define IQ_I_U_VALUE_PLUS_2604 14562623 // = 2604 +#define IQ_I_U_VALUE_PLUS_2605 14568215 // = 2605 +#define IQ_I_U_VALUE_PLUS_2606 14573808 // = 2606 +#define IQ_I_U_VALUE_PLUS_2607 14579400 // = 2607 +#define IQ_I_U_VALUE_PLUS_2608 14584993 // = 2608 +#define IQ_I_U_VALUE_PLUS_2609 14590585 // = 2609 +#define IQ_I_U_VALUE_PLUS_2610 14596177 // = 2610 +#define IQ_I_U_VALUE_PLUS_2611 14601770 // = 2611 +#define IQ_I_U_VALUE_PLUS_2612 14607362 // = 2612 +#define IQ_I_U_VALUE_PLUS_2613 14612955 // = 2613 +#define IQ_I_U_VALUE_PLUS_2614 14618547 // = 2614 +#define IQ_I_U_VALUE_PLUS_2615 14624139 // = 2615 +#define IQ_I_U_VALUE_PLUS_2616 14629732 // = 2616 +#define IQ_I_U_VALUE_PLUS_2617 14635324 // = 2617 +#define IQ_I_U_VALUE_PLUS_2618 14640917 // = 2618 +#define IQ_I_U_VALUE_PLUS_2619 14646509 // = 2619 +#define IQ_I_U_VALUE_PLUS_2620 14652101 // = 2620 +#define IQ_I_U_VALUE_PLUS_2621 14657694 // = 2621 +#define IQ_I_U_VALUE_PLUS_2622 14663286 // = 2622 +#define IQ_I_U_VALUE_PLUS_2623 14668879 // = 2623 +#define IQ_I_U_VALUE_PLUS_2624 14674471 // = 2624 +#define IQ_I_U_VALUE_PLUS_2625 14680064 // = 2625 +#define IQ_I_U_VALUE_PLUS_2626 14685656 // = 2626 +#define IQ_I_U_VALUE_PLUS_2627 14691248 // = 2627 +#define IQ_I_U_VALUE_PLUS_2628 14696841 // = 2628 +#define IQ_I_U_VALUE_PLUS_2629 14702433 // = 2629 +#define IQ_I_U_VALUE_PLUS_2630 14708026 // = 2630 +#define IQ_I_U_VALUE_PLUS_2631 14713618 // = 2631 +#define IQ_I_U_VALUE_PLUS_2632 14719210 // = 2632 +#define IQ_I_U_VALUE_PLUS_2633 14724803 // = 2633 +#define IQ_I_U_VALUE_PLUS_2634 14730395 // = 2634 +#define IQ_I_U_VALUE_PLUS_2635 14735988 // = 2635 +#define IQ_I_U_VALUE_PLUS_2636 14741580 // = 2636 +#define IQ_I_U_VALUE_PLUS_2637 14747172 // = 2637 +#define IQ_I_U_VALUE_PLUS_2638 14752765 // = 2638 +#define IQ_I_U_VALUE_PLUS_2639 14758357 // = 2639 +#define IQ_I_U_VALUE_PLUS_2640 14763950 // = 2640 +#define IQ_I_U_VALUE_PLUS_2641 14769542 // = 2641 +#define IQ_I_U_VALUE_PLUS_2642 14775134 // = 2642 +#define IQ_I_U_VALUE_PLUS_2643 14780727 // = 2643 +#define IQ_I_U_VALUE_PLUS_2644 14786319 // = 2644 +#define IQ_I_U_VALUE_PLUS_2645 14791912 // = 2645 +#define IQ_I_U_VALUE_PLUS_2646 14797504 // = 2646 +#define IQ_I_U_VALUE_PLUS_2647 14803096 // = 2647 +#define IQ_I_U_VALUE_PLUS_2648 14808689 // = 2648 +#define IQ_I_U_VALUE_PLUS_2649 14814281 // = 2649 +#define IQ_I_U_VALUE_PLUS_2650 14819874 // = 2650 +#define IQ_I_U_VALUE_PLUS_2651 14825466 // = 2651 +#define IQ_I_U_VALUE_PLUS_2652 14831058 // = 2652 +#define IQ_I_U_VALUE_PLUS_2653 14836651 // = 2653 +#define IQ_I_U_VALUE_PLUS_2654 14842243 // = 2654 +#define IQ_I_U_VALUE_PLUS_2655 14847836 // = 2655 +#define IQ_I_U_VALUE_PLUS_2656 14853428 // = 2656 +#define IQ_I_U_VALUE_PLUS_2657 14859020 // = 2657 +#define IQ_I_U_VALUE_PLUS_2658 14864613 // = 2658 +#define IQ_I_U_VALUE_PLUS_2659 14870205 // = 2659 +#define IQ_I_U_VALUE_PLUS_2660 14875798 // = 2660 +#define IQ_I_U_VALUE_PLUS_2661 14881390 // = 2661 +#define IQ_I_U_VALUE_PLUS_2662 14886982 // = 2662 +#define IQ_I_U_VALUE_PLUS_2663 14892575 // = 2663 +#define IQ_I_U_VALUE_PLUS_2664 14898167 // = 2664 +#define IQ_I_U_VALUE_PLUS_2665 14903760 // = 2665 +#define IQ_I_U_VALUE_PLUS_2666 14909352 // = 2666 +#define IQ_I_U_VALUE_PLUS_2667 14914945 // = 2667 +#define IQ_I_U_VALUE_PLUS_2668 14920537 // = 2668 +#define IQ_I_U_VALUE_PLUS_2669 14926129 // = 2669 +#define IQ_I_U_VALUE_PLUS_2670 14931722 // = 2670 +#define IQ_I_U_VALUE_PLUS_2671 14937314 // = 2671 +#define IQ_I_U_VALUE_PLUS_2672 14942907 // = 2672 +#define IQ_I_U_VALUE_PLUS_2673 14948499 // = 2673 +#define IQ_I_U_VALUE_PLUS_2674 14954091 // = 2674 +#define IQ_I_U_VALUE_PLUS_2675 14959684 // = 2675 +#define IQ_I_U_VALUE_PLUS_2676 14965276 // = 2676 +#define IQ_I_U_VALUE_PLUS_2677 14970869 // = 2677 +#define IQ_I_U_VALUE_PLUS_2678 14976461 // = 2678 +#define IQ_I_U_VALUE_PLUS_2679 14982053 // = 2679 +#define IQ_I_U_VALUE_PLUS_2680 14987646 // = 2680 +#define IQ_I_U_VALUE_PLUS_2681 14993238 // = 2681 +#define IQ_I_U_VALUE_PLUS_2682 14998831 // = 2682 +#define IQ_I_U_VALUE_PLUS_2683 15004423 // = 2683 +#define IQ_I_U_VALUE_PLUS_2684 15010015 // = 2684 +#define IQ_I_U_VALUE_PLUS_2685 15015608 // = 2685 +#define IQ_I_U_VALUE_PLUS_2686 15021200 // = 2686 +#define IQ_I_U_VALUE_PLUS_2687 15026793 // = 2687 +#define IQ_I_U_VALUE_PLUS_2688 15032385 // = 2688 +#define IQ_I_U_VALUE_PLUS_2689 15037977 // = 2689 +#define IQ_I_U_VALUE_PLUS_2690 15043570 // = 2690 +#define IQ_I_U_VALUE_PLUS_2691 15049162 // = 2691 +#define IQ_I_U_VALUE_PLUS_2692 15054755 // = 2692 +#define IQ_I_U_VALUE_PLUS_2693 15060347 // = 2693 +#define IQ_I_U_VALUE_PLUS_2694 15065939 // = 2694 +#define IQ_I_U_VALUE_PLUS_2695 15071532 // = 2695 +#define IQ_I_U_VALUE_PLUS_2696 15077124 // = 2696 +#define IQ_I_U_VALUE_PLUS_2697 15082717 // = 2697 +#define IQ_I_U_VALUE_PLUS_2698 15088309 // = 2698 +#define IQ_I_U_VALUE_PLUS_2699 15093901 // = 2699 +#define IQ_I_U_VALUE_PLUS_2700 15099494 // = 2700 +#define IQ_I_U_VALUE_PLUS_2701 15105086 // = 2701 +#define IQ_I_U_VALUE_PLUS_2702 15110679 // = 2702 +#define IQ_I_U_VALUE_PLUS_2703 15116271 // = 2703 +#define IQ_I_U_VALUE_PLUS_2704 15121864 // = 2704 +#define IQ_I_U_VALUE_PLUS_2705 15127456 // = 2705 +#define IQ_I_U_VALUE_PLUS_2706 15133048 // = 2706 +#define IQ_I_U_VALUE_PLUS_2707 15138641 // = 2707 +#define IQ_I_U_VALUE_PLUS_2708 15144233 // = 2708 +#define IQ_I_U_VALUE_PLUS_2709 15149826 // = 2709 +#define IQ_I_U_VALUE_PLUS_2710 15155418 // = 2710 +#define IQ_I_U_VALUE_PLUS_2711 15161010 // = 2711 +#define IQ_I_U_VALUE_PLUS_2712 15166603 // = 2712 +#define IQ_I_U_VALUE_PLUS_2713 15172195 // = 2713 +#define IQ_I_U_VALUE_PLUS_2714 15177788 // = 2714 +#define IQ_I_U_VALUE_PLUS_2715 15183380 // = 2715 +#define IQ_I_U_VALUE_PLUS_2716 15188972 // = 2716 +#define IQ_I_U_VALUE_PLUS_2717 15194565 // = 2717 +#define IQ_I_U_VALUE_PLUS_2718 15200157 // = 2718 +#define IQ_I_U_VALUE_PLUS_2719 15205750 // = 2719 +#define IQ_I_U_VALUE_PLUS_2720 15211342 // = 2720 +#define IQ_I_U_VALUE_PLUS_2721 15216934 // = 2721 +#define IQ_I_U_VALUE_PLUS_2722 15222527 // = 2722 +#define IQ_I_U_VALUE_PLUS_2723 15228119 // = 2723 +#define IQ_I_U_VALUE_PLUS_2724 15233712 // = 2724 +#define IQ_I_U_VALUE_PLUS_2725 15239304 // = 2725 +#define IQ_I_U_VALUE_PLUS_2726 15244896 // = 2726 +#define IQ_I_U_VALUE_PLUS_2727 15250489 // = 2727 +#define IQ_I_U_VALUE_PLUS_2728 15256081 // = 2728 +#define IQ_I_U_VALUE_PLUS_2729 15261674 // = 2729 +#define IQ_I_U_VALUE_PLUS_2730 15267266 // = 2730 +#define IQ_I_U_VALUE_PLUS_2731 15272858 // = 2731 +#define IQ_I_U_VALUE_PLUS_2732 15278451 // = 2732 +#define IQ_I_U_VALUE_PLUS_2733 15284043 // = 2733 +#define IQ_I_U_VALUE_PLUS_2734 15289636 // = 2734 +#define IQ_I_U_VALUE_PLUS_2735 15295228 // = 2735 +#define IQ_I_U_VALUE_PLUS_2736 15300820 // = 2736 +#define IQ_I_U_VALUE_PLUS_2737 15306413 // = 2737 +#define IQ_I_U_VALUE_PLUS_2738 15312005 // = 2738 +#define IQ_I_U_VALUE_PLUS_2739 15317598 // = 2739 +#define IQ_I_U_VALUE_PLUS_2740 15323190 // = 2740 +#define IQ_I_U_VALUE_PLUS_2741 15328783 // = 2741 +#define IQ_I_U_VALUE_PLUS_2742 15334375 // = 2742 +#define IQ_I_U_VALUE_PLUS_2743 15339967 // = 2743 +#define IQ_I_U_VALUE_PLUS_2744 15345560 // = 2744 +#define IQ_I_U_VALUE_PLUS_2745 15351152 // = 2745 +#define IQ_I_U_VALUE_PLUS_2746 15356745 // = 2746 +#define IQ_I_U_VALUE_PLUS_2747 15362337 // = 2747 +#define IQ_I_U_VALUE_PLUS_2748 15367929 // = 2748 +#define IQ_I_U_VALUE_PLUS_2749 15373522 // = 2749 +#define IQ_I_U_VALUE_PLUS_2750 15379114 // = 2750 +#define IQ_I_U_VALUE_PLUS_2751 15384707 // = 2751 +#define IQ_I_U_VALUE_PLUS_2752 15390299 // = 2752 +#define IQ_I_U_VALUE_PLUS_2753 15395891 // = 2753 +#define IQ_I_U_VALUE_PLUS_2754 15401484 // = 2754 +#define IQ_I_U_VALUE_PLUS_2755 15407076 // = 2755 +#define IQ_I_U_VALUE_PLUS_2756 15412669 // = 2756 +#define IQ_I_U_VALUE_PLUS_2757 15418261 // = 2757 +#define IQ_I_U_VALUE_PLUS_2758 15423853 // = 2758 +#define IQ_I_U_VALUE_PLUS_2759 15429446 // = 2759 +#define IQ_I_U_VALUE_PLUS_2760 15435038 // = 2760 +#define IQ_I_U_VALUE_PLUS_2761 15440631 // = 2761 +#define IQ_I_U_VALUE_PLUS_2762 15446223 // = 2762 +#define IQ_I_U_VALUE_PLUS_2763 15451815 // = 2763 +#define IQ_I_U_VALUE_PLUS_2764 15457408 // = 2764 +#define IQ_I_U_VALUE_PLUS_2765 15463000 // = 2765 +#define IQ_I_U_VALUE_PLUS_2766 15468593 // = 2766 +#define IQ_I_U_VALUE_PLUS_2767 15474185 // = 2767 +#define IQ_I_U_VALUE_PLUS_2768 15479777 // = 2768 +#define IQ_I_U_VALUE_PLUS_2769 15485370 // = 2769 +#define IQ_I_U_VALUE_PLUS_2770 15490962 // = 2770 +#define IQ_I_U_VALUE_PLUS_2771 15496555 // = 2771 +#define IQ_I_U_VALUE_PLUS_2772 15502147 // = 2772 +#define IQ_I_U_VALUE_PLUS_2773 15507739 // = 2773 +#define IQ_I_U_VALUE_PLUS_2774 15513332 // = 2774 +#define IQ_I_U_VALUE_PLUS_2775 15518924 // = 2775 +#define IQ_I_U_VALUE_PLUS_2776 15524517 // = 2776 +#define IQ_I_U_VALUE_PLUS_2777 15530109 // = 2777 +#define IQ_I_U_VALUE_PLUS_2778 15535702 // = 2778 +#define IQ_I_U_VALUE_PLUS_2779 15541294 // = 2779 +#define IQ_I_U_VALUE_PLUS_2780 15546886 // = 2780 +#define IQ_I_U_VALUE_PLUS_2781 15552479 // = 2781 +#define IQ_I_U_VALUE_PLUS_2782 15558071 // = 2782 +#define IQ_I_U_VALUE_PLUS_2783 15563664 // = 2783 +#define IQ_I_U_VALUE_PLUS_2784 15569256 // = 2784 +#define IQ_I_U_VALUE_PLUS_2785 15574848 // = 2785 +#define IQ_I_U_VALUE_PLUS_2786 15580441 // = 2786 +#define IQ_I_U_VALUE_PLUS_2787 15586033 // = 2787 +#define IQ_I_U_VALUE_PLUS_2788 15591626 // = 2788 +#define IQ_I_U_VALUE_PLUS_2789 15597218 // = 2789 +#define IQ_I_U_VALUE_PLUS_2790 15602810 // = 2790 +#define IQ_I_U_VALUE_PLUS_2791 15608403 // = 2791 +#define IQ_I_U_VALUE_PLUS_2792 15613995 // = 2792 +#define IQ_I_U_VALUE_PLUS_2793 15619588 // = 2793 +#define IQ_I_U_VALUE_PLUS_2794 15625180 // = 2794 +#define IQ_I_U_VALUE_PLUS_2795 15630772 // = 2795 +#define IQ_I_U_VALUE_PLUS_2796 15636365 // = 2796 +#define IQ_I_U_VALUE_PLUS_2797 15641957 // = 2797 +#define IQ_I_U_VALUE_PLUS_2798 15647550 // = 2798 +#define IQ_I_U_VALUE_PLUS_2799 15653142 // = 2799 +#define IQ_I_U_VALUE_PLUS_2800 15658734 // = 2800 +#define IQ_I_U_VALUE_PLUS_2801 15664327 // = 2801 +#define IQ_I_U_VALUE_PLUS_2802 15669919 // = 2802 +#define IQ_I_U_VALUE_PLUS_2803 15675512 // = 2803 +#define IQ_I_U_VALUE_PLUS_2804 15681104 // = 2804 +#define IQ_I_U_VALUE_PLUS_2805 15686696 // = 2805 +#define IQ_I_U_VALUE_PLUS_2806 15692289 // = 2806 +#define IQ_I_U_VALUE_PLUS_2807 15697881 // = 2807 +#define IQ_I_U_VALUE_PLUS_2808 15703474 // = 2808 +#define IQ_I_U_VALUE_PLUS_2809 15709066 // = 2809 +#define IQ_I_U_VALUE_PLUS_2810 15714658 // = 2810 +#define IQ_I_U_VALUE_PLUS_2811 15720251 // = 2811 +#define IQ_I_U_VALUE_PLUS_2812 15725843 // = 2812 +#define IQ_I_U_VALUE_PLUS_2813 15731436 // = 2813 +#define IQ_I_U_VALUE_PLUS_2814 15737028 // = 2814 +#define IQ_I_U_VALUE_PLUS_2815 15742621 // = 2815 +#define IQ_I_U_VALUE_PLUS_2816 15748213 // = 2816 +#define IQ_I_U_VALUE_PLUS_2817 15753805 // = 2817 +#define IQ_I_U_VALUE_PLUS_2818 15759398 // = 2818 +#define IQ_I_U_VALUE_PLUS_2819 15764990 // = 2819 +#define IQ_I_U_VALUE_PLUS_2820 15770583 // = 2820 +#define IQ_I_U_VALUE_PLUS_2821 15776175 // = 2821 +#define IQ_I_U_VALUE_PLUS_2822 15781767 // = 2822 +#define IQ_I_U_VALUE_PLUS_2823 15787360 // = 2823 +#define IQ_I_U_VALUE_PLUS_2824 15792952 // = 2824 +#define IQ_I_U_VALUE_PLUS_2825 15798545 // = 2825 +#define IQ_I_U_VALUE_PLUS_2826 15804137 // = 2826 +#define IQ_I_U_VALUE_PLUS_2827 15809729 // = 2827 +#define IQ_I_U_VALUE_PLUS_2828 15815322 // = 2828 +#define IQ_I_U_VALUE_PLUS_2829 15820914 // = 2829 +#define IQ_I_U_VALUE_PLUS_2830 15826507 // = 2830 +#define IQ_I_U_VALUE_PLUS_2831 15832099 // = 2831 +#define IQ_I_U_VALUE_PLUS_2832 15837691 // = 2832 +#define IQ_I_U_VALUE_PLUS_2833 15843284 // = 2833 +#define IQ_I_U_VALUE_PLUS_2834 15848876 // = 2834 +#define IQ_I_U_VALUE_PLUS_2835 15854469 // = 2835 +#define IQ_I_U_VALUE_PLUS_2836 15860061 // = 2836 +#define IQ_I_U_VALUE_PLUS_2837 15865653 // = 2837 +#define IQ_I_U_VALUE_PLUS_2838 15871246 // = 2838 +#define IQ_I_U_VALUE_PLUS_2839 15876838 // = 2839 +#define IQ_I_U_VALUE_PLUS_2840 15882431 // = 2840 +#define IQ_I_U_VALUE_PLUS_2841 15888023 // = 2841 +#define IQ_I_U_VALUE_PLUS_2842 15893615 // = 2842 +#define IQ_I_U_VALUE_PLUS_2843 15899208 // = 2843 +#define IQ_I_U_VALUE_PLUS_2844 15904800 // = 2844 +#define IQ_I_U_VALUE_PLUS_2845 15910393 // = 2845 +#define IQ_I_U_VALUE_PLUS_2846 15915985 // = 2846 +#define IQ_I_U_VALUE_PLUS_2847 15921577 // = 2847 +#define IQ_I_U_VALUE_PLUS_2848 15927170 // = 2848 +#define IQ_I_U_VALUE_PLUS_2849 15932762 // = 2849 +#define IQ_I_U_VALUE_PLUS_2850 15938355 // = 2850 +#define IQ_I_U_VALUE_PLUS_2851 15943947 // = 2851 +#define IQ_I_U_VALUE_PLUS_2852 15949540 // = 2852 +#define IQ_I_U_VALUE_PLUS_2853 15955132 // = 2853 +#define IQ_I_U_VALUE_PLUS_2854 15960724 // = 2854 +#define IQ_I_U_VALUE_PLUS_2855 15966317 // = 2855 +#define IQ_I_U_VALUE_PLUS_2856 15971909 // = 2856 +#define IQ_I_U_VALUE_PLUS_2857 15977502 // = 2857 +#define IQ_I_U_VALUE_PLUS_2858 15983094 // = 2858 +#define IQ_I_U_VALUE_PLUS_2859 15988686 // = 2859 +#define IQ_I_U_VALUE_PLUS_2860 15994279 // = 2860 +#define IQ_I_U_VALUE_PLUS_2861 15999871 // = 2861 +#define IQ_I_U_VALUE_PLUS_2862 16005464 // = 2862 +#define IQ_I_U_VALUE_PLUS_2863 16011056 // = 2863 +#define IQ_I_U_VALUE_PLUS_2864 16016648 // = 2864 +#define IQ_I_U_VALUE_PLUS_2865 16022241 // = 2865 +#define IQ_I_U_VALUE_PLUS_2866 16027833 // = 2866 +#define IQ_I_U_VALUE_PLUS_2867 16033426 // = 2867 +#define IQ_I_U_VALUE_PLUS_2868 16039018 // = 2868 +#define IQ_I_U_VALUE_PLUS_2869 16044610 // = 2869 +#define IQ_I_U_VALUE_PLUS_2870 16050203 // = 2870 +#define IQ_I_U_VALUE_PLUS_2871 16055795 // = 2871 +#define IQ_I_U_VALUE_PLUS_2872 16061388 // = 2872 +#define IQ_I_U_VALUE_PLUS_2873 16066980 // = 2873 +#define IQ_I_U_VALUE_PLUS_2874 16072572 // = 2874 +#define IQ_I_U_VALUE_PLUS_2875 16078165 // = 2875 +#define IQ_I_U_VALUE_PLUS_2876 16083757 // = 2876 +#define IQ_I_U_VALUE_PLUS_2877 16089350 // = 2877 +#define IQ_I_U_VALUE_PLUS_2878 16094942 // = 2878 +#define IQ_I_U_VALUE_PLUS_2879 16100534 // = 2879 +#define IQ_I_U_VALUE_PLUS_2880 16106127 // = 2880 +#define IQ_I_U_VALUE_PLUS_2881 16111719 // = 2881 +#define IQ_I_U_VALUE_PLUS_2882 16117312 // = 2882 +#define IQ_I_U_VALUE_PLUS_2883 16122904 // = 2883 +#define IQ_I_U_VALUE_PLUS_2884 16128496 // = 2884 +#define IQ_I_U_VALUE_PLUS_2885 16134089 // = 2885 +#define IQ_I_U_VALUE_PLUS_2886 16139681 // = 2886 +#define IQ_I_U_VALUE_PLUS_2887 16145274 // = 2887 +#define IQ_I_U_VALUE_PLUS_2888 16150866 // = 2888 +#define IQ_I_U_VALUE_PLUS_2889 16156459 // = 2889 +#define IQ_I_U_VALUE_PLUS_2890 16162051 // = 2890 +#define IQ_I_U_VALUE_PLUS_2891 16167643 // = 2891 +#define IQ_I_U_VALUE_PLUS_2892 16173236 // = 2892 +#define IQ_I_U_VALUE_PLUS_2893 16178828 // = 2893 +#define IQ_I_U_VALUE_PLUS_2894 16184421 // = 2894 +#define IQ_I_U_VALUE_PLUS_2895 16190013 // = 2895 +#define IQ_I_U_VALUE_PLUS_2896 16195605 // = 2896 +#define IQ_I_U_VALUE_PLUS_2897 16201198 // = 2897 +#define IQ_I_U_VALUE_PLUS_2898 16206790 // = 2898 +#define IQ_I_U_VALUE_PLUS_2899 16212383 // = 2899 +#define IQ_I_U_VALUE_PLUS_2900 16217975 // = 2900 +#define IQ_I_U_VALUE_PLUS_2901 16223567 // = 2901 +#define IQ_I_U_VALUE_PLUS_2902 16229160 // = 2902 +#define IQ_I_U_VALUE_PLUS_2903 16234752 // = 2903 +#define IQ_I_U_VALUE_PLUS_2904 16240345 // = 2904 +#define IQ_I_U_VALUE_PLUS_2905 16245937 // = 2905 +#define IQ_I_U_VALUE_PLUS_2906 16251529 // = 2906 +#define IQ_I_U_VALUE_PLUS_2907 16257122 // = 2907 +#define IQ_I_U_VALUE_PLUS_2908 16262714 // = 2908 +#define IQ_I_U_VALUE_PLUS_2909 16268307 // = 2909 +#define IQ_I_U_VALUE_PLUS_2910 16273899 // = 2910 +#define IQ_I_U_VALUE_PLUS_2911 16279491 // = 2911 +#define IQ_I_U_VALUE_PLUS_2912 16285084 // = 2912 +#define IQ_I_U_VALUE_PLUS_2913 16290676 // = 2913 +#define IQ_I_U_VALUE_PLUS_2914 16296269 // = 2914 +#define IQ_I_U_VALUE_PLUS_2915 16301861 // = 2915 +#define IQ_I_U_VALUE_PLUS_2916 16307453 // = 2916 +#define IQ_I_U_VALUE_PLUS_2917 16313046 // = 2917 +#define IQ_I_U_VALUE_PLUS_2918 16318638 // = 2918 +#define IQ_I_U_VALUE_PLUS_2919 16324231 // = 2919 +#define IQ_I_U_VALUE_PLUS_2920 16329823 // = 2920 +#define IQ_I_U_VALUE_PLUS_2921 16335415 // = 2921 +#define IQ_I_U_VALUE_PLUS_2922 16341008 // = 2922 +#define IQ_I_U_VALUE_PLUS_2923 16346600 // = 2923 +#define IQ_I_U_VALUE_PLUS_2924 16352193 // = 2924 +#define IQ_I_U_VALUE_PLUS_2925 16357785 // = 2925 +#define IQ_I_U_VALUE_PLUS_2926 16363378 // = 2926 +#define IQ_I_U_VALUE_PLUS_2927 16368970 // = 2927 +#define IQ_I_U_VALUE_PLUS_2928 16374562 // = 2928 +#define IQ_I_U_VALUE_PLUS_2929 16380155 // = 2929 +#define IQ_I_U_VALUE_PLUS_2930 16385747 // = 2930 +#define IQ_I_U_VALUE_PLUS_2931 16391340 // = 2931 +#define IQ_I_U_VALUE_PLUS_2932 16396932 // = 2932 +#define IQ_I_U_VALUE_PLUS_2933 16402524 // = 2933 +#define IQ_I_U_VALUE_PLUS_2934 16408117 // = 2934 +#define IQ_I_U_VALUE_PLUS_2935 16413709 // = 2935 +#define IQ_I_U_VALUE_PLUS_2936 16419302 // = 2936 +#define IQ_I_U_VALUE_PLUS_2937 16424894 // = 2937 +#define IQ_I_U_VALUE_PLUS_2938 16430486 // = 2938 +#define IQ_I_U_VALUE_PLUS_2939 16436079 // = 2939 +#define IQ_I_U_VALUE_PLUS_2940 16441671 // = 2940 +#define IQ_I_U_VALUE_PLUS_2941 16447264 // = 2941 +#define IQ_I_U_VALUE_PLUS_2942 16452856 // = 2942 +#define IQ_I_U_VALUE_PLUS_2943 16458448 // = 2943 +#define IQ_I_U_VALUE_PLUS_2944 16464041 // = 2944 +#define IQ_I_U_VALUE_PLUS_2945 16469633 // = 2945 +#define IQ_I_U_VALUE_PLUS_2946 16475226 // = 2946 +#define IQ_I_U_VALUE_PLUS_2947 16480818 // = 2947 +#define IQ_I_U_VALUE_PLUS_2948 16486410 // = 2948 +#define IQ_I_U_VALUE_PLUS_2949 16492003 // = 2949 +#define IQ_I_U_VALUE_PLUS_2950 16497595 // = 2950 +#define IQ_I_U_VALUE_PLUS_2951 16503188 // = 2951 +#define IQ_I_U_VALUE_PLUS_2952 16508780 // = 2952 +#define IQ_I_U_VALUE_PLUS_2953 16514372 // = 2953 +#define IQ_I_U_VALUE_PLUS_2954 16519965 // = 2954 +#define IQ_I_U_VALUE_PLUS_2955 16525557 // = 2955 +#define IQ_I_U_VALUE_PLUS_2956 16531150 // = 2956 +#define IQ_I_U_VALUE_PLUS_2957 16536742 // = 2957 +#define IQ_I_U_VALUE_PLUS_2958 16542334 // = 2958 +#define IQ_I_U_VALUE_PLUS_2959 16547927 // = 2959 +#define IQ_I_U_VALUE_PLUS_2960 16553519 // = 2960 +#define IQ_I_U_VALUE_PLUS_2961 16559112 // = 2961 +#define IQ_I_U_VALUE_PLUS_2962 16564704 // = 2962 +#define IQ_I_U_VALUE_PLUS_2963 16570297 // = 2963 +#define IQ_I_U_VALUE_PLUS_2964 16575889 // = 2964 +#define IQ_I_U_VALUE_PLUS_2965 16581481 // = 2965 +#define IQ_I_U_VALUE_PLUS_2966 16587074 // = 2966 +#define IQ_I_U_VALUE_PLUS_2967 16592666 // = 2967 +#define IQ_I_U_VALUE_PLUS_2968 16598259 // = 2968 +#define IQ_I_U_VALUE_PLUS_2969 16603851 // = 2969 +#define IQ_I_U_VALUE_PLUS_2970 16609443 // = 2970 +#define IQ_I_U_VALUE_PLUS_2971 16615036 // = 2971 +#define IQ_I_U_VALUE_PLUS_2972 16620628 // = 2972 +#define IQ_I_U_VALUE_PLUS_2973 16626221 // = 2973 +#define IQ_I_U_VALUE_PLUS_2974 16631813 // = 2974 +#define IQ_I_U_VALUE_PLUS_2975 16637405 // = 2975 +#define IQ_I_U_VALUE_PLUS_2976 16642998 // = 2976 +#define IQ_I_U_VALUE_PLUS_2977 16648590 // = 2977 +#define IQ_I_U_VALUE_PLUS_2978 16654183 // = 2978 +#define IQ_I_U_VALUE_PLUS_2979 16659775 // = 2979 +#define IQ_I_U_VALUE_PLUS_2980 16665367 // = 2980 +#define IQ_I_U_VALUE_PLUS_2981 16670960 // = 2981 +#define IQ_I_U_VALUE_PLUS_2982 16676552 // = 2982 +#define IQ_I_U_VALUE_PLUS_2983 16682145 // = 2983 +#define IQ_I_U_VALUE_PLUS_2984 16687737 // = 2984 +#define IQ_I_U_VALUE_PLUS_2985 16693329 // = 2985 +#define IQ_I_U_VALUE_PLUS_2986 16698922 // = 2986 +#define IQ_I_U_VALUE_PLUS_2987 16704514 // = 2987 +#define IQ_I_U_VALUE_PLUS_2988 16710107 // = 2988 +#define IQ_I_U_VALUE_PLUS_2989 16715699 // = 2989 +#define IQ_I_U_VALUE_PLUS_2990 16721291 // = 2990 +#define IQ_I_U_VALUE_PLUS_2991 16726884 // = 2991 +#define IQ_I_U_VALUE_PLUS_2992 16732476 // = 2992 +#define IQ_I_U_VALUE_PLUS_2993 16738069 // = 2993 +#define IQ_I_U_VALUE_PLUS_2994 16743661 // = 2994 +#define IQ_I_U_VALUE_PLUS_2995 16749253 // = 2995 +#define IQ_I_U_VALUE_PLUS_2996 16754846 // = 2996 +#define IQ_I_U_VALUE_PLUS_2997 16760438 // = 2997 +#define IQ_I_U_VALUE_PLUS_2998 16766031 // = 2998 +#define IQ_I_U_VALUE_PLUS_2999 16771623 // = 2999 +#define IQ_I_U_VALUE_PLUS_3000 16777216 // = 3000 +#define IQ_I_U_VALUE_PLUS_3001 16782808 // = 3001 +#define IQ_I_U_VALUE_PLUS_3002 16788400 // = 3002 +#define IQ_I_U_VALUE_PLUS_3003 16793993 // = 3003 +#define IQ_I_U_VALUE_PLUS_3004 16799585 // = 3004 +#define IQ_I_U_VALUE_PLUS_3005 16805178 // = 3005 +#define IQ_I_U_VALUE_PLUS_3006 16810770 // = 3006 +#define IQ_I_U_VALUE_PLUS_3007 16816362 // = 3007 +#define IQ_I_U_VALUE_PLUS_3008 16821955 // = 3008 +#define IQ_I_U_VALUE_PLUS_3009 16827547 // = 3009 +#define IQ_I_U_VALUE_PLUS_3010 16833140 // = 3010 +#define IQ_I_U_VALUE_PLUS_3011 16838732 // = 3011 +#define IQ_I_U_VALUE_PLUS_3012 16844324 // = 3012 +#define IQ_I_U_VALUE_PLUS_3013 16849917 // = 3013 +#define IQ_I_U_VALUE_PLUS_3014 16855509 // = 3014 +#define IQ_I_U_VALUE_PLUS_3015 16861102 // = 3015 +#define IQ_I_U_VALUE_PLUS_3016 16866694 // = 3016 +#define IQ_I_U_VALUE_PLUS_3017 16872286 // = 3017 +#define IQ_I_U_VALUE_PLUS_3018 16877879 // = 3018 +#define IQ_I_U_VALUE_PLUS_3019 16883471 // = 3019 +#define IQ_I_U_VALUE_PLUS_3020 16889064 // = 3020 +#define IQ_I_U_VALUE_PLUS_3021 16894656 // = 3021 +#define IQ_I_U_VALUE_PLUS_3022 16900248 // = 3022 +#define IQ_I_U_VALUE_PLUS_3023 16905841 // = 3023 +#define IQ_I_U_VALUE_PLUS_3024 16911433 // = 3024 +#define IQ_I_U_VALUE_PLUS_3025 16917026 // = 3025 +#define IQ_I_U_VALUE_PLUS_3026 16922618 // = 3026 +#define IQ_I_U_VALUE_PLUS_3027 16928210 // = 3027 +#define IQ_I_U_VALUE_PLUS_3028 16933803 // = 3028 +#define IQ_I_U_VALUE_PLUS_3029 16939395 // = 3029 +#define IQ_I_U_VALUE_PLUS_3030 16944988 // = 3030 +#define IQ_I_U_VALUE_PLUS_3031 16950580 // = 3031 +#define IQ_I_U_VALUE_PLUS_3032 16956172 // = 3032 +#define IQ_I_U_VALUE_PLUS_3033 16961765 // = 3033 +#define IQ_I_U_VALUE_PLUS_3034 16967357 // = 3034 +#define IQ_I_U_VALUE_PLUS_3035 16972950 // = 3035 +#define IQ_I_U_VALUE_PLUS_3036 16978542 // = 3036 +#define IQ_I_U_VALUE_PLUS_3037 16984134 // = 3037 +#define IQ_I_U_VALUE_PLUS_3038 16989727 // = 3038 +#define IQ_I_U_VALUE_PLUS_3039 16995319 // = 3039 +#define IQ_I_U_VALUE_PLUS_3040 17000912 // = 3040 +#define IQ_I_U_VALUE_PLUS_3041 17006504 // = 3041 +#define IQ_I_U_VALUE_PLUS_3042 17012097 // = 3042 +#define IQ_I_U_VALUE_PLUS_3043 17017689 // = 3043 +#define IQ_I_U_VALUE_PLUS_3044 17023281 // = 3044 +#define IQ_I_U_VALUE_PLUS_3045 17028874 // = 3045 +#define IQ_I_U_VALUE_PLUS_3046 17034466 // = 3046 +#define IQ_I_U_VALUE_PLUS_3047 17040059 // = 3047 +#define IQ_I_U_VALUE_PLUS_3048 17045651 // = 3048 +#define IQ_I_U_VALUE_PLUS_3049 17051243 // = 3049 +#define IQ_I_U_VALUE_PLUS_3050 17056836 // = 3050 +#define IQ_I_U_VALUE_PLUS_3051 17062428 // = 3051 +#define IQ_I_U_VALUE_PLUS_3052 17068021 // = 3052 +#define IQ_I_U_VALUE_PLUS_3053 17073613 // = 3053 +#define IQ_I_U_VALUE_PLUS_3054 17079205 // = 3054 +#define IQ_I_U_VALUE_PLUS_3055 17084798 // = 3055 +#define IQ_I_U_VALUE_PLUS_3056 17090390 // = 3056 +#define IQ_I_U_VALUE_PLUS_3057 17095983 // = 3057 +#define IQ_I_U_VALUE_PLUS_3058 17101575 // = 3058 +#define IQ_I_U_VALUE_PLUS_3059 17107167 // = 3059 +#define IQ_I_U_VALUE_PLUS_3060 17112760 // = 3060 +#define IQ_I_U_VALUE_PLUS_3061 17118352 // = 3061 +#define IQ_I_U_VALUE_PLUS_3062 17123945 // = 3062 +#define IQ_I_U_VALUE_PLUS_3063 17129537 // = 3063 +#define IQ_I_U_VALUE_PLUS_3064 17135129 // = 3064 +#define IQ_I_U_VALUE_PLUS_3065 17140722 // = 3065 +#define IQ_I_U_VALUE_PLUS_3066 17146314 // = 3066 +#define IQ_I_U_VALUE_PLUS_3067 17151907 // = 3067 +#define IQ_I_U_VALUE_PLUS_3068 17157499 // = 3068 +#define IQ_I_U_VALUE_PLUS_3069 17163091 // = 3069 +#define IQ_I_U_VALUE_PLUS_3070 17168684 // = 3070 +#define IQ_I_U_VALUE_PLUS_3071 17174276 // = 3071 +#define IQ_I_U_VALUE_PLUS_3072 17179869 // = 3072 +#define IQ_I_U_VALUE_PLUS_3073 17185461 // = 3073 +#define IQ_I_U_VALUE_PLUS_3074 17191053 // = 3074 +#define IQ_I_U_VALUE_PLUS_3075 17196646 // = 3075 +#define IQ_I_U_VALUE_PLUS_3076 17202238 // = 3076 +#define IQ_I_U_VALUE_PLUS_3077 17207831 // = 3077 +#define IQ_I_U_VALUE_PLUS_3078 17213423 // = 3078 +#define IQ_I_U_VALUE_PLUS_3079 17219016 // = 3079 +#define IQ_I_U_VALUE_PLUS_3080 17224608 // = 3080 +#define IQ_I_U_VALUE_PLUS_3081 17230200 // = 3081 +#define IQ_I_U_VALUE_PLUS_3082 17235793 // = 3082 +#define IQ_I_U_VALUE_PLUS_3083 17241385 // = 3083 +#define IQ_I_U_VALUE_PLUS_3084 17246978 // = 3084 +#define IQ_I_U_VALUE_PLUS_3085 17252570 // = 3085 +#define IQ_I_U_VALUE_PLUS_3086 17258162 // = 3086 +#define IQ_I_U_VALUE_PLUS_3087 17263755 // = 3087 +#define IQ_I_U_VALUE_PLUS_3088 17269347 // = 3088 +#define IQ_I_U_VALUE_PLUS_3089 17274940 // = 3089 +#define IQ_I_U_VALUE_PLUS_3090 17280532 // = 3090 +#define IQ_I_U_VALUE_PLUS_3091 17286124 // = 3091 +#define IQ_I_U_VALUE_PLUS_3092 17291717 // = 3092 +#define IQ_I_U_VALUE_PLUS_3093 17297309 // = 3093 +#define IQ_I_U_VALUE_PLUS_3094 17302902 // = 3094 +#define IQ_I_U_VALUE_PLUS_3095 17308494 // = 3095 +#define IQ_I_U_VALUE_PLUS_3096 17314086 // = 3096 +#define IQ_I_U_VALUE_PLUS_3097 17319679 // = 3097 +#define IQ_I_U_VALUE_PLUS_3098 17325271 // = 3098 +#define IQ_I_U_VALUE_PLUS_3099 17330864 // = 3099 +#define IQ_I_U_VALUE_PLUS_3100 17336456 // = 3100 +#define IQ_I_U_VALUE_PLUS_3101 17342048 // = 3101 +#define IQ_I_U_VALUE_PLUS_3102 17347641 // = 3102 +#define IQ_I_U_VALUE_PLUS_3103 17353233 // = 3103 +#define IQ_I_U_VALUE_PLUS_3104 17358826 // = 3104 +#define IQ_I_U_VALUE_PLUS_3105 17364418 // = 3105 +#define IQ_I_U_VALUE_PLUS_3106 17370010 // = 3106 +#define IQ_I_U_VALUE_PLUS_3107 17375603 // = 3107 +#define IQ_I_U_VALUE_PLUS_3108 17381195 // = 3108 +#define IQ_I_U_VALUE_PLUS_3109 17386788 // = 3109 +#define IQ_I_U_VALUE_PLUS_3110 17392380 // = 3110 +#define IQ_I_U_VALUE_PLUS_3111 17397972 // = 3111 +#define IQ_I_U_VALUE_PLUS_3112 17403565 // = 3112 +#define IQ_I_U_VALUE_PLUS_3113 17409157 // = 3113 +#define IQ_I_U_VALUE_PLUS_3114 17414750 // = 3114 +#define IQ_I_U_VALUE_PLUS_3115 17420342 // = 3115 +#define IQ_I_U_VALUE_PLUS_3116 17425935 // = 3116 +#define IQ_I_U_VALUE_PLUS_3117 17431527 // = 3117 +#define IQ_I_U_VALUE_PLUS_3118 17437119 // = 3118 +#define IQ_I_U_VALUE_PLUS_3119 17442712 // = 3119 +#define IQ_I_U_VALUE_PLUS_3120 17448304 // = 3120 +#define IQ_I_U_VALUE_PLUS_3121 17453897 // = 3121 +#define IQ_I_U_VALUE_PLUS_3122 17459489 // = 3122 +#define IQ_I_U_VALUE_PLUS_3123 17465081 // = 3123 +#define IQ_I_U_VALUE_PLUS_3124 17470674 // = 3124 +#define IQ_I_U_VALUE_PLUS_3125 17476266 // = 3125 +#define IQ_I_U_VALUE_PLUS_3126 17481859 // = 3126 +#define IQ_I_U_VALUE_PLUS_3127 17487451 // = 3127 +#define IQ_I_U_VALUE_PLUS_3128 17493043 // = 3128 +#define IQ_I_U_VALUE_PLUS_3129 17498636 // = 3129 +#define IQ_I_U_VALUE_PLUS_3130 17504228 // = 3130 +#define IQ_I_U_VALUE_PLUS_3131 17509821 // = 3131 +#define IQ_I_U_VALUE_PLUS_3132 17515413 // = 3132 +#define IQ_I_U_VALUE_PLUS_3133 17521005 // = 3133 +#define IQ_I_U_VALUE_PLUS_3134 17526598 // = 3134 +#define IQ_I_U_VALUE_PLUS_3135 17532190 // = 3135 +#define IQ_I_U_VALUE_PLUS_3136 17537783 // = 3136 +#define IQ_I_U_VALUE_PLUS_3137 17543375 // = 3137 +#define IQ_I_U_VALUE_PLUS_3138 17548967 // = 3138 +#define IQ_I_U_VALUE_PLUS_3139 17554560 // = 3139 +#define IQ_I_U_VALUE_PLUS_3140 17560152 // = 3140 +#define IQ_I_U_VALUE_PLUS_3141 17565745 // = 3141 +#define IQ_I_U_VALUE_PLUS_3142 17571337 // = 3142 +#define IQ_I_U_VALUE_PLUS_3143 17576929 // = 3143 +#define IQ_I_U_VALUE_PLUS_3144 17582522 // = 3144 +#define IQ_I_U_VALUE_PLUS_3145 17588114 // = 3145 +#define IQ_I_U_VALUE_PLUS_3146 17593707 // = 3146 +#define IQ_I_U_VALUE_PLUS_3147 17599299 // = 3147 +#define IQ_I_U_VALUE_PLUS_3148 17604891 // = 3148 +#define IQ_I_U_VALUE_PLUS_3149 17610484 // = 3149 +#define IQ_I_U_VALUE_PLUS_3150 17616076 // = 3150 +#define IQ_I_U_VALUE_PLUS_3151 17621669 // = 3151 +#define IQ_I_U_VALUE_PLUS_3152 17627261 // = 3152 +#define IQ_I_U_VALUE_PLUS_3153 17632854 // = 3153 +#define IQ_I_U_VALUE_PLUS_3154 17638446 // = 3154 +#define IQ_I_U_VALUE_PLUS_3155 17644038 // = 3155 +#define IQ_I_U_VALUE_PLUS_3156 17649631 // = 3156 +#define IQ_I_U_VALUE_PLUS_3157 17655223 // = 3157 +#define IQ_I_U_VALUE_PLUS_3158 17660816 // = 3158 +#define IQ_I_U_VALUE_PLUS_3159 17666408 // = 3159 +#define IQ_I_U_VALUE_PLUS_3160 17672000 // = 3160 +#define IQ_I_U_VALUE_PLUS_3161 17677593 // = 3161 +#define IQ_I_U_VALUE_PLUS_3162 17683185 // = 3162 +#define IQ_I_U_VALUE_PLUS_3163 17688778 // = 3163 +#define IQ_I_U_VALUE_PLUS_3164 17694370 // = 3164 +#define IQ_I_U_VALUE_PLUS_3165 17699962 // = 3165 +#define IQ_I_U_VALUE_PLUS_3166 17705555 // = 3166 +#define IQ_I_U_VALUE_PLUS_3167 17711147 // = 3167 +#define IQ_I_U_VALUE_PLUS_3168 17716740 // = 3168 +#define IQ_I_U_VALUE_PLUS_3169 17722332 // = 3169 +#define IQ_I_U_VALUE_PLUS_3170 17727924 // = 3170 +#define IQ_I_U_VALUE_PLUS_3171 17733517 // = 3171 +#define IQ_I_U_VALUE_PLUS_3172 17739109 // = 3172 +#define IQ_I_U_VALUE_PLUS_3173 17744702 // = 3173 +#define IQ_I_U_VALUE_PLUS_3174 17750294 // = 3174 +#define IQ_I_U_VALUE_PLUS_3175 17755886 // = 3175 +#define IQ_I_U_VALUE_PLUS_3176 17761479 // = 3176 +#define IQ_I_U_VALUE_PLUS_3177 17767071 // = 3177 +#define IQ_I_U_VALUE_PLUS_3178 17772664 // = 3178 +#define IQ_I_U_VALUE_PLUS_3179 17778256 // = 3179 +#define IQ_I_U_VALUE_PLUS_3180 17783848 // = 3180 +#define IQ_I_U_VALUE_PLUS_3181 17789441 // = 3181 +#define IQ_I_U_VALUE_PLUS_3182 17795033 // = 3182 +#define IQ_I_U_VALUE_PLUS_3183 17800626 // = 3183 +#define IQ_I_U_VALUE_PLUS_3184 17806218 // = 3184 +#define IQ_I_U_VALUE_PLUS_3185 17811810 // = 3185 +#define IQ_I_U_VALUE_PLUS_3186 17817403 // = 3186 +#define IQ_I_U_VALUE_PLUS_3187 17822995 // = 3187 +#define IQ_I_U_VALUE_PLUS_3188 17828588 // = 3188 +#define IQ_I_U_VALUE_PLUS_3189 17834180 // = 3189 +#define IQ_I_U_VALUE_PLUS_3190 17839773 // = 3190 +#define IQ_I_U_VALUE_PLUS_3191 17845365 // = 3191 +#define IQ_I_U_VALUE_PLUS_3192 17850957 // = 3192 +#define IQ_I_U_VALUE_PLUS_3193 17856550 // = 3193 +#define IQ_I_U_VALUE_PLUS_3194 17862142 // = 3194 +#define IQ_I_U_VALUE_PLUS_3195 17867735 // = 3195 +#define IQ_I_U_VALUE_PLUS_3196 17873327 // = 3196 +#define IQ_I_U_VALUE_PLUS_3197 17878919 // = 3197 +#define IQ_I_U_VALUE_PLUS_3198 17884512 // = 3198 +#define IQ_I_U_VALUE_PLUS_3199 17890104 // = 3199 +#define IQ_I_U_VALUE_PLUS_3200 17895697 // = 3200 +#define IQ_I_U_VALUE_PLUS_3201 17901289 // = 3201 +#define IQ_I_U_VALUE_PLUS_3202 17906881 // = 3202 +#define IQ_I_U_VALUE_PLUS_3203 17912474 // = 3203 +#define IQ_I_U_VALUE_PLUS_3204 17918066 // = 3204 +#define IQ_I_U_VALUE_PLUS_3205 17923659 // = 3205 +#define IQ_I_U_VALUE_PLUS_3206 17929251 // = 3206 +#define IQ_I_U_VALUE_PLUS_3207 17934843 // = 3207 +#define IQ_I_U_VALUE_PLUS_3208 17940436 // = 3208 +#define IQ_I_U_VALUE_PLUS_3209 17946028 // = 3209 +#define IQ_I_U_VALUE_PLUS_3210 17951621 // = 3210 +#define IQ_I_U_VALUE_PLUS_3211 17957213 // = 3211 +#define IQ_I_U_VALUE_PLUS_3212 17962805 // = 3212 +#define IQ_I_U_VALUE_PLUS_3213 17968398 // = 3213 +#define IQ_I_U_VALUE_PLUS_3214 17973990 // = 3214 +#define IQ_I_U_VALUE_PLUS_3215 17979583 // = 3215 +#define IQ_I_U_VALUE_PLUS_3216 17985175 // = 3216 +#define IQ_I_U_VALUE_PLUS_3217 17990767 // = 3217 +#define IQ_I_U_VALUE_PLUS_3218 17996360 // = 3218 +#define IQ_I_U_VALUE_PLUS_3219 18001952 // = 3219 +#define IQ_I_U_VALUE_PLUS_3220 18007545 // = 3220 +#define IQ_I_U_VALUE_PLUS_3221 18013137 // = 3221 +#define IQ_I_U_VALUE_PLUS_3222 18018729 // = 3222 +#define IQ_I_U_VALUE_PLUS_3223 18024322 // = 3223 +#define IQ_I_U_VALUE_PLUS_3224 18029914 // = 3224 +#define IQ_I_U_VALUE_PLUS_3225 18035507 // = 3225 +#define IQ_I_U_VALUE_PLUS_3226 18041099 // = 3226 +#define IQ_I_U_VALUE_PLUS_3227 18046692 // = 3227 +#define IQ_I_U_VALUE_PLUS_3228 18052284 // = 3228 +#define IQ_I_U_VALUE_PLUS_3229 18057876 // = 3229 +#define IQ_I_U_VALUE_PLUS_3230 18063469 // = 3230 +#define IQ_I_U_VALUE_PLUS_3231 18069061 // = 3231 +#define IQ_I_U_VALUE_PLUS_3232 18074654 // = 3232 +#define IQ_I_U_VALUE_PLUS_3233 18080246 // = 3233 +#define IQ_I_U_VALUE_PLUS_3234 18085838 // = 3234 +#define IQ_I_U_VALUE_PLUS_3235 18091431 // = 3235 +#define IQ_I_U_VALUE_PLUS_3236 18097023 // = 3236 +#define IQ_I_U_VALUE_PLUS_3237 18102616 // = 3237 +#define IQ_I_U_VALUE_PLUS_3238 18108208 // = 3238 +#define IQ_I_U_VALUE_PLUS_3239 18113800 // = 3239 +#define IQ_I_U_VALUE_PLUS_3240 18119393 // = 3240 +#define IQ_I_U_VALUE_PLUS_3241 18124985 // = 3241 +#define IQ_I_U_VALUE_PLUS_3242 18130578 // = 3242 +#define IQ_I_U_VALUE_PLUS_3243 18136170 // = 3243 +#define IQ_I_U_VALUE_PLUS_3244 18141762 // = 3244 +#define IQ_I_U_VALUE_PLUS_3245 18147355 // = 3245 +#define IQ_I_U_VALUE_PLUS_3246 18152947 // = 3246 +#define IQ_I_U_VALUE_PLUS_3247 18158540 // = 3247 +#define IQ_I_U_VALUE_PLUS_3248 18164132 // = 3248 +#define IQ_I_U_VALUE_PLUS_3249 18169724 // = 3249 +#define IQ_I_U_VALUE_PLUS_3250 18175317 // = 3250 +#define IQ_I_U_VALUE_PLUS_3251 18180909 // = 3251 +#define IQ_I_U_VALUE_PLUS_3252 18186502 // = 3252 +#define IQ_I_U_VALUE_PLUS_3253 18192094 // = 3253 +#define IQ_I_U_VALUE_PLUS_3254 18197686 // = 3254 +#define IQ_I_U_VALUE_PLUS_3255 18203279 // = 3255 +#define IQ_I_U_VALUE_PLUS_3256 18208871 // = 3256 +#define IQ_I_U_VALUE_PLUS_3257 18214464 // = 3257 +#define IQ_I_U_VALUE_PLUS_3258 18220056 // = 3258 +#define IQ_I_U_VALUE_PLUS_3259 18225648 // = 3259 +#define IQ_I_U_VALUE_PLUS_3260 18231241 // = 3260 +#define IQ_I_U_VALUE_PLUS_3261 18236833 // = 3261 +#define IQ_I_U_VALUE_PLUS_3262 18242426 // = 3262 +#define IQ_I_U_VALUE_PLUS_3263 18248018 // = 3263 +#define IQ_I_U_VALUE_PLUS_3264 18253611 // = 3264 +#define IQ_I_U_VALUE_PLUS_3265 18259203 // = 3265 +#define IQ_I_U_VALUE_PLUS_3266 18264795 // = 3266 +#define IQ_I_U_VALUE_PLUS_3267 18270388 // = 3267 +#define IQ_I_U_VALUE_PLUS_3268 18275980 // = 3268 +#define IQ_I_U_VALUE_PLUS_3269 18281573 // = 3269 +#define IQ_I_U_VALUE_PLUS_3270 18287165 // = 3270 +#define IQ_I_U_VALUE_PLUS_3271 18292757 // = 3271 +#define IQ_I_U_VALUE_PLUS_3272 18298350 // = 3272 +#define IQ_I_U_VALUE_PLUS_3273 18303942 // = 3273 +#define IQ_I_U_VALUE_PLUS_3274 18309535 // = 3274 +#define IQ_I_U_VALUE_PLUS_3275 18315127 // = 3275 +#define IQ_I_U_VALUE_PLUS_3276 18320719 // = 3276 +#define IQ_I_U_VALUE_PLUS_3277 18326312 // = 3277 +#define IQ_I_U_VALUE_PLUS_3278 18331904 // = 3278 +#define IQ_I_U_VALUE_PLUS_3279 18337497 // = 3279 +#define IQ_I_U_VALUE_PLUS_3280 18343089 // = 3280 +#define IQ_I_U_VALUE_PLUS_3281 18348681 // = 3281 +#define IQ_I_U_VALUE_PLUS_3282 18354274 // = 3282 +#define IQ_I_U_VALUE_PLUS_3283 18359866 // = 3283 +#define IQ_I_U_VALUE_PLUS_3284 18365459 // = 3284 +#define IQ_I_U_VALUE_PLUS_3285 18371051 // = 3285 +#define IQ_I_U_VALUE_PLUS_3286 18376643 // = 3286 +#define IQ_I_U_VALUE_PLUS_3287 18382236 // = 3287 +#define IQ_I_U_VALUE_PLUS_3288 18387828 // = 3288 +#define IQ_I_U_VALUE_PLUS_3289 18393421 // = 3289 +#define IQ_I_U_VALUE_PLUS_3290 18399013 // = 3290 +#define IQ_I_U_VALUE_PLUS_3291 18404605 // = 3291 +#define IQ_I_U_VALUE_PLUS_3292 18410198 // = 3292 +#define IQ_I_U_VALUE_PLUS_3293 18415790 // = 3293 +#define IQ_I_U_VALUE_PLUS_3294 18421383 // = 3294 +#define IQ_I_U_VALUE_PLUS_3295 18426975 // = 3295 +#define IQ_I_U_VALUE_PLUS_3296 18432567 // = 3296 +#define IQ_I_U_VALUE_PLUS_3297 18438160 // = 3297 +#define IQ_I_U_VALUE_PLUS_3298 18443752 // = 3298 +#define IQ_I_U_VALUE_PLUS_3299 18449345 // = 3299 +#define IQ_I_U_VALUE_PLUS_3300 18454937 // = 3300 +#define IQ_I_U_VALUE_PLUS_3301 18460530 // = 3301 +#define IQ_I_U_VALUE_PLUS_3302 18466122 // = 3302 +#define IQ_I_U_VALUE_PLUS_3303 18471714 // = 3303 +#define IQ_I_U_VALUE_PLUS_3304 18477307 // = 3304 +#define IQ_I_U_VALUE_PLUS_3305 18482899 // = 3305 +#define IQ_I_U_VALUE_PLUS_3306 18488492 // = 3306 +#define IQ_I_U_VALUE_PLUS_3307 18494084 // = 3307 +#define IQ_I_U_VALUE_PLUS_3308 18499676 // = 3308 +#define IQ_I_U_VALUE_PLUS_3309 18505269 // = 3309 +#define IQ_I_U_VALUE_PLUS_3310 18510861 // = 3310 +#define IQ_I_U_VALUE_PLUS_3311 18516454 // = 3311 +#define IQ_I_U_VALUE_PLUS_3312 18522046 // = 3312 +#define IQ_I_U_VALUE_PLUS_3313 18527638 // = 3313 +#define IQ_I_U_VALUE_PLUS_3314 18533231 // = 3314 +#define IQ_I_U_VALUE_PLUS_3315 18538823 // = 3315 +#define IQ_I_U_VALUE_PLUS_3316 18544416 // = 3316 +#define IQ_I_U_VALUE_PLUS_3317 18550008 // = 3317 +#define IQ_I_U_VALUE_PLUS_3318 18555600 // = 3318 +#define IQ_I_U_VALUE_PLUS_3319 18561193 // = 3319 +#define IQ_I_U_VALUE_PLUS_3320 18566785 // = 3320 +#define IQ_I_U_VALUE_PLUS_3321 18572378 // = 3321 +#define IQ_I_U_VALUE_PLUS_3322 18577970 // = 3322 +#define IQ_I_U_VALUE_PLUS_3323 18583562 // = 3323 +#define IQ_I_U_VALUE_PLUS_3324 18589155 // = 3324 +#define IQ_I_U_VALUE_PLUS_3325 18594747 // = 3325 +#define IQ_I_U_VALUE_PLUS_3326 18600340 // = 3326 +#define IQ_I_U_VALUE_PLUS_3327 18605932 // = 3327 +#define IQ_I_U_VALUE_PLUS_3328 18611524 // = 3328 +#define IQ_I_U_VALUE_PLUS_3329 18617117 // = 3329 +#define IQ_I_U_VALUE_PLUS_3330 18622709 // = 3330 +#define IQ_I_U_VALUE_PLUS_3331 18628302 // = 3331 +#define IQ_I_U_VALUE_PLUS_3332 18633894 // = 3332 +#define IQ_I_U_VALUE_PLUS_3333 18639486 // = 3333 +#define IQ_I_U_VALUE_PLUS_3334 18645079 // = 3334 +#define IQ_I_U_VALUE_PLUS_3335 18650671 // = 3335 +#define IQ_I_U_VALUE_PLUS_3336 18656264 // = 3336 +#define IQ_I_U_VALUE_PLUS_3337 18661856 // = 3337 +#define IQ_I_U_VALUE_PLUS_3338 18667449 // = 3338 +#define IQ_I_U_VALUE_PLUS_3339 18673041 // = 3339 +#define IQ_I_U_VALUE_PLUS_3340 18678633 // = 3340 +#define IQ_I_U_VALUE_PLUS_3341 18684226 // = 3341 +#define IQ_I_U_VALUE_PLUS_3342 18689818 // = 3342 +#define IQ_I_U_VALUE_PLUS_3343 18695411 // = 3343 +#define IQ_I_U_VALUE_PLUS_3344 18701003 // = 3344 +#define IQ_I_U_VALUE_PLUS_3345 18706595 // = 3345 +#define IQ_I_U_VALUE_PLUS_3346 18712188 // = 3346 +#define IQ_I_U_VALUE_PLUS_3347 18717780 // = 3347 +#define IQ_I_U_VALUE_PLUS_3348 18723373 // = 3348 +#define IQ_I_U_VALUE_PLUS_3349 18728965 // = 3349 +#define IQ_I_U_VALUE_PLUS_3350 18734557 // = 3350 +#define IQ_I_U_VALUE_PLUS_3351 18740150 // = 3351 +#define IQ_I_U_VALUE_PLUS_3352 18745742 // = 3352 +#define IQ_I_U_VALUE_PLUS_3353 18751335 // = 3353 +#define IQ_I_U_VALUE_PLUS_3354 18756927 // = 3354 +#define IQ_I_U_VALUE_PLUS_3355 18762519 // = 3355 +#define IQ_I_U_VALUE_PLUS_3356 18768112 // = 3356 +#define IQ_I_U_VALUE_PLUS_3357 18773704 // = 3357 +#define IQ_I_U_VALUE_PLUS_3358 18779297 // = 3358 +#define IQ_I_U_VALUE_PLUS_3359 18784889 // = 3359 +#define IQ_I_U_VALUE_PLUS_3360 18790481 // = 3360 +#define IQ_I_U_VALUE_PLUS_3361 18796074 // = 3361 +#define IQ_I_U_VALUE_PLUS_3362 18801666 // = 3362 +#define IQ_I_U_VALUE_PLUS_3363 18807259 // = 3363 +#define IQ_I_U_VALUE_PLUS_3364 18812851 // = 3364 +#define IQ_I_U_VALUE_PLUS_3365 18818443 // = 3365 +#define IQ_I_U_VALUE_PLUS_3366 18824036 // = 3366 +#define IQ_I_U_VALUE_PLUS_3367 18829628 // = 3367 +#define IQ_I_U_VALUE_PLUS_3368 18835221 // = 3368 +#define IQ_I_U_VALUE_PLUS_3369 18840813 // = 3369 +#define IQ_I_U_VALUE_PLUS_3370 18846405 // = 3370 +#define IQ_I_U_VALUE_PLUS_3371 18851998 // = 3371 +#define IQ_I_U_VALUE_PLUS_3372 18857590 // = 3372 +#define IQ_I_U_VALUE_PLUS_3373 18863183 // = 3373 +#define IQ_I_U_VALUE_PLUS_3374 18868775 // = 3374 +#define IQ_I_U_VALUE_PLUS_3375 18874368 // = 3375 +#define IQ_I_U_VALUE_PLUS_3376 18879960 // = 3376 +#define IQ_I_U_VALUE_PLUS_3377 18885552 // = 3377 +#define IQ_I_U_VALUE_PLUS_3378 18891145 // = 3378 +#define IQ_I_U_VALUE_PLUS_3379 18896737 // = 3379 +#define IQ_I_U_VALUE_PLUS_3380 18902330 // = 3380 +#define IQ_I_U_VALUE_PLUS_3381 18907922 // = 3381 +#define IQ_I_U_VALUE_PLUS_3382 18913514 // = 3382 +#define IQ_I_U_VALUE_PLUS_3383 18919107 // = 3383 +#define IQ_I_U_VALUE_PLUS_3384 18924699 // = 3384 +#define IQ_I_U_VALUE_PLUS_3385 18930292 // = 3385 +#define IQ_I_U_VALUE_PLUS_3386 18935884 // = 3386 +#define IQ_I_U_VALUE_PLUS_3387 18941476 // = 3387 +#define IQ_I_U_VALUE_PLUS_3388 18947069 // = 3388 +#define IQ_I_U_VALUE_PLUS_3389 18952661 // = 3389 +#define IQ_I_U_VALUE_PLUS_3390 18958254 // = 3390 +#define IQ_I_U_VALUE_PLUS_3391 18963846 // = 3391 +#define IQ_I_U_VALUE_PLUS_3392 18969438 // = 3392 +#define IQ_I_U_VALUE_PLUS_3393 18975031 // = 3393 +#define IQ_I_U_VALUE_PLUS_3394 18980623 // = 3394 +#define IQ_I_U_VALUE_PLUS_3395 18986216 // = 3395 +#define IQ_I_U_VALUE_PLUS_3396 18991808 // = 3396 +#define IQ_I_U_VALUE_PLUS_3397 18997400 // = 3397 +#define IQ_I_U_VALUE_PLUS_3398 19002993 // = 3398 +#define IQ_I_U_VALUE_PLUS_3399 19008585 // = 3399 +#define IQ_I_U_VALUE_PLUS_3400 19014178 // = 3400 +#define IQ_I_U_VALUE_PLUS_3401 19019770 // = 3401 +#define IQ_I_U_VALUE_PLUS_3402 19025362 // = 3402 +#define IQ_I_U_VALUE_PLUS_3403 19030955 // = 3403 +#define IQ_I_U_VALUE_PLUS_3404 19036547 // = 3404 +#define IQ_I_U_VALUE_PLUS_3405 19042140 // = 3405 +#define IQ_I_U_VALUE_PLUS_3406 19047732 // = 3406 +#define IQ_I_U_VALUE_PLUS_3407 19053324 // = 3407 +#define IQ_I_U_VALUE_PLUS_3408 19058917 // = 3408 +#define IQ_I_U_VALUE_PLUS_3409 19064509 // = 3409 +#define IQ_I_U_VALUE_PLUS_3410 19070102 // = 3410 +#define IQ_I_U_VALUE_PLUS_3411 19075694 // = 3411 +#define IQ_I_U_VALUE_PLUS_3412 19081286 // = 3412 +#define IQ_I_U_VALUE_PLUS_3413 19086879 // = 3413 +#define IQ_I_U_VALUE_PLUS_3414 19092471 // = 3414 +#define IQ_I_U_VALUE_PLUS_3415 19098064 // = 3415 +#define IQ_I_U_VALUE_PLUS_3416 19103656 // = 3416 +#define IQ_I_U_VALUE_PLUS_3417 19109249 // = 3417 +#define IQ_I_U_VALUE_PLUS_3418 19114841 // = 3418 +#define IQ_I_U_VALUE_PLUS_3419 19120433 // = 3419 +#define IQ_I_U_VALUE_PLUS_3420 19126026 // = 3420 +#define IQ_I_U_VALUE_PLUS_3421 19131618 // = 3421 +#define IQ_I_U_VALUE_PLUS_3422 19137211 // = 3422 +#define IQ_I_U_VALUE_PLUS_3423 19142803 // = 3423 +#define IQ_I_U_VALUE_PLUS_3424 19148395 // = 3424 +#define IQ_I_U_VALUE_PLUS_3425 19153988 // = 3425 +#define IQ_I_U_VALUE_PLUS_3426 19159580 // = 3426 +#define IQ_I_U_VALUE_PLUS_3427 19165173 // = 3427 +#define IQ_I_U_VALUE_PLUS_3428 19170765 // = 3428 +#define IQ_I_U_VALUE_PLUS_3429 19176357 // = 3429 +#define IQ_I_U_VALUE_PLUS_3430 19181950 // = 3430 +#define IQ_I_U_VALUE_PLUS_3431 19187542 // = 3431 +#define IQ_I_U_VALUE_PLUS_3432 19193135 // = 3432 +#define IQ_I_U_VALUE_PLUS_3433 19198727 // = 3433 +#define IQ_I_U_VALUE_PLUS_3434 19204319 // = 3434 +#define IQ_I_U_VALUE_PLUS_3435 19209912 // = 3435 +#define IQ_I_U_VALUE_PLUS_3436 19215504 // = 3436 +#define IQ_I_U_VALUE_PLUS_3437 19221097 // = 3437 +#define IQ_I_U_VALUE_PLUS_3438 19226689 // = 3438 +#define IQ_I_U_VALUE_PLUS_3439 19232281 // = 3439 +#define IQ_I_U_VALUE_PLUS_3440 19237874 // = 3440 +#define IQ_I_U_VALUE_PLUS_3441 19243466 // = 3441 +#define IQ_I_U_VALUE_PLUS_3442 19249059 // = 3442 +#define IQ_I_U_VALUE_PLUS_3443 19254651 // = 3443 +#define IQ_I_U_VALUE_PLUS_3444 19260243 // = 3444 +#define IQ_I_U_VALUE_PLUS_3445 19265836 // = 3445 +#define IQ_I_U_VALUE_PLUS_3446 19271428 // = 3446 +#define IQ_I_U_VALUE_PLUS_3447 19277021 // = 3447 +#define IQ_I_U_VALUE_PLUS_3448 19282613 // = 3448 +#define IQ_I_U_VALUE_PLUS_3449 19288205 // = 3449 +#define IQ_I_U_VALUE_PLUS_3450 19293798 // = 3450 +#define IQ_I_U_VALUE_PLUS_3451 19299390 // = 3451 +#define IQ_I_U_VALUE_PLUS_3452 19304983 // = 3452 +#define IQ_I_U_VALUE_PLUS_3453 19310575 // = 3453 +#define IQ_I_U_VALUE_PLUS_3454 19316168 // = 3454 +#define IQ_I_U_VALUE_PLUS_3455 19321760 // = 3455 +#define IQ_I_U_VALUE_PLUS_3456 19327352 // = 3456 +#define IQ_I_U_VALUE_PLUS_3457 19332945 // = 3457 +#define IQ_I_U_VALUE_PLUS_3458 19338537 // = 3458 +#define IQ_I_U_VALUE_PLUS_3459 19344130 // = 3459 +#define IQ_I_U_VALUE_PLUS_3460 19349722 // = 3460 +#define IQ_I_U_VALUE_PLUS_3461 19355314 // = 3461 +#define IQ_I_U_VALUE_PLUS_3462 19360907 // = 3462 +#define IQ_I_U_VALUE_PLUS_3463 19366499 // = 3463 +#define IQ_I_U_VALUE_PLUS_3464 19372092 // = 3464 +#define IQ_I_U_VALUE_PLUS_3465 19377684 // = 3465 +#define IQ_I_U_VALUE_PLUS_3466 19383276 // = 3466 +#define IQ_I_U_VALUE_PLUS_3467 19388869 // = 3467 +#define IQ_I_U_VALUE_PLUS_3468 19394461 // = 3468 +#define IQ_I_U_VALUE_PLUS_3469 19400054 // = 3469 +#define IQ_I_U_VALUE_PLUS_3470 19405646 // = 3470 +#define IQ_I_U_VALUE_PLUS_3471 19411238 // = 3471 +#define IQ_I_U_VALUE_PLUS_3472 19416831 // = 3472 +#define IQ_I_U_VALUE_PLUS_3473 19422423 // = 3473 +#define IQ_I_U_VALUE_PLUS_3474 19428016 // = 3474 +#define IQ_I_U_VALUE_PLUS_3475 19433608 // = 3475 +#define IQ_I_U_VALUE_PLUS_3476 19439200 // = 3476 +#define IQ_I_U_VALUE_PLUS_3477 19444793 // = 3477 +#define IQ_I_U_VALUE_PLUS_3478 19450385 // = 3478 +#define IQ_I_U_VALUE_PLUS_3479 19455978 // = 3479 +#define IQ_I_U_VALUE_PLUS_3480 19461570 // = 3480 +#define IQ_I_U_VALUE_PLUS_3481 19467162 // = 3481 +#define IQ_I_U_VALUE_PLUS_3482 19472755 // = 3482 +#define IQ_I_U_VALUE_PLUS_3483 19478347 // = 3483 +#define IQ_I_U_VALUE_PLUS_3484 19483940 // = 3484 +#define IQ_I_U_VALUE_PLUS_3485 19489532 // = 3485 +#define IQ_I_U_VALUE_PLUS_3486 19495124 // = 3486 +#define IQ_I_U_VALUE_PLUS_3487 19500717 // = 3487 +#define IQ_I_U_VALUE_PLUS_3488 19506309 // = 3488 +#define IQ_I_U_VALUE_PLUS_3489 19511902 // = 3489 +#define IQ_I_U_VALUE_PLUS_3490 19517494 // = 3490 +#define IQ_I_U_VALUE_PLUS_3491 19523087 // = 3491 +#define IQ_I_U_VALUE_PLUS_3492 19528679 // = 3492 +#define IQ_I_U_VALUE_PLUS_3493 19534271 // = 3493 +#define IQ_I_U_VALUE_PLUS_3494 19539864 // = 3494 +#define IQ_I_U_VALUE_PLUS_3495 19545456 // = 3495 +#define IQ_I_U_VALUE_PLUS_3496 19551049 // = 3496 +#define IQ_I_U_VALUE_PLUS_3497 19556641 // = 3497 +#define IQ_I_U_VALUE_PLUS_3498 19562233 // = 3498 +#define IQ_I_U_VALUE_PLUS_3499 19567826 // = 3499 +#define IQ_I_U_VALUE_PLUS_3500 19573418 // = 3500 + + +#endif + + + + + +#endif /* _IQ_VALUES_NORMA_F_H_ */ diff --git a/Inu/Src/N12_Libs/iq_values_norma_oborot.h b/Inu/Src/N12_Libs/iq_values_norma_oborot.h new file mode 100644 index 0000000..6c626b9 --- /dev/null +++ b/Inu/Src/N12_Libs/iq_values_norma_oborot.h @@ -0,0 +1,22 @@ +/* + * iq_values_norma.h + * + * Created on: 9 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef _IQ_VALUES_N_H_ +#define _IQ_VALUES_N_H_ + +#include "params_norma.h" + + +#if (NORMA_MZZ_INT==3000) + +#endif + + + + + +#endif /* _IQ_VALUES_NORMA_N_H_ */ diff --git a/Inu/Src/N12_Libs/log_params.c b/Inu/Src/N12_Libs/log_params.c new file mode 100644 index 0000000..6438cd3 --- /dev/null +++ b/Inu/Src/N12_Libs/log_params.c @@ -0,0 +1,149 @@ +#include "log_params.h" +#include "log_to_memory.h" +#include "MemoryFunctions.h" + +//#pragma DATA_SECTION(log_params, ".fast_vars"); +TYPE_LOG_PARAMS log_params = TYPE_LOG_PARAMS_DEFAULT; + +void defineVarsErrSlowLogs(void) +{ + //volatile static + unsigned long l1; + + //fastlog + log_params.volume_of_fast_log = VOLUME_OF_FAST_LOG; + log_params.start_address_log = START_ADDRESS_LOG; + l1 = (unsigned long)(log_params.BlockSizeErr*VOLUME_OF_FAST_LOG); +// l1 = (unsigned long)(VOLUME_OF_FAST_LOG) * l1; + log_params.end_address_log = (unsigned long)log_params.start_address_log + (unsigned long)l1 - 1; + // + while (log_params.end_address_log >= START_ADDRESS_LOG_SLOW) + { + log_params.end_address_log -= log_params.BlockSizeErr; + log_params.volume_of_fast_log--; + } + + l1 = (unsigned long)(log_params.volume_of_fast_log/3); + l1 = (unsigned long)(log_params.BlockSizeErr*l1); + log_params.end_address_log_level_1 = (unsigned long)log_params.start_address_log + (unsigned long)l1 - 1; + log_params.end_address_log_level_2 = log_params.end_address_log_level_1 + (unsigned long)l1 - 1; + + + //slow log + log_params.volume_of_slow_log = VOLUME_OF_SLOW_LOG; + log_params.start_address_log_slow = ((unsigned long)log_params.end_address_log + 0x1); + l1 = (unsigned long)VOLUME_OF_SLOW_LOG * (unsigned long)log_params.BlockSizeSlow; + log_params.end_address_log_slow = ((unsigned long)log_params.start_address_log_slow + l1 - 1); + // + while (log_params.end_address_log_slow >= END_ADDRESS_LOGS) + { + log_params.end_address_log_slow -= log_params.BlockSizeSlow; + log_params.volume_of_slow_log--; + } + l1 = (unsigned long)(log_params.volume_of_slow_log/3); + l1 = (unsigned long)(log_params.BlockSizeSlow*l1); + log_params.end_address_log_slow_level_1 = (unsigned long)log_params.start_address_log_slow + (unsigned long)l1 - 1; + log_params.end_address_log_slow_level_2 = log_params.end_address_log_slow_level_1 + (unsigned long)l1 - 1; + +// log_params.start_address_save_log_memory = START_ADDRESS_SAVE_ON_ALARM; +// log_params.end_address_save_log_memory = END_ADDRESS_LOGS; + +// log_params.end_address_log_slow_level_2 = log_params.end_address_save_log_memory - 0x2000; +// log_params.end_address_log_slow_level_3 = log_params.end_address_save_log_memory - 0x4000; + + + // + log_params.addres_mem = log_params.start_address_log; + log_params.addres_mem_slow = log_params.start_address_log_slow; + +} + +void initLogSize(unsigned int c_fast, unsigned int c_slow) +{ + log_params.size_slow_done = 0; + log_params.size_fast_done = 0; + log_params.init = 0; + + if (c_fast>SIZE_LOGS_ARRAY) + c_fast = SIZE_LOGS_ARRAY; + + if (c_slow>SIZE_LOGS_ARRAY) + c_slow = SIZE_LOGS_ARRAY; + + logsdata.block_size_fast = c_fast; + logsdata.block_size_slow = c_slow; + + getFastLogs(1); + getSlowLogs(1); + +// log_params.BlockSizeErr = logpar.block_size_counter_fast;//block_size_counter_fast; +// log_params.BlockSizeSlow = logpar.block_size_counter_slow; + + defineVarsErrSlowLogs(); + + log_params.init = 1; + + clear_mem_all(); + + +// clear_mem(FAST_LOG); +// clear_mem(SLOW_LOG); + + // set_start_mem(FAST_LOG); + // getFastLogs(); + // log_params.BlockSizeErr = block_size_counter_fast; + // set_start_mem(SLOW_LOG); + // getLogs(); + // log_params.BlockSizeSlow = block_size_counter_slow; +} + +//void initErrLog() +//{ +// +// static unsigned long SizeLogErr = 0; +// static unsigned long SizeLogSlow = 0; +// unsigned int sizeHiword = 0; +// unsigned int sizeLoword = 0; +// unsigned int addrHiword = 0; +// unsigned int addrLoword = 0; +// +// set_start_mem(FAST_LOG); +//// set_start_mem(ALARM_SAVE_MEMORY); +// set_start_mem(INIT_LOG); +//// set_start_mem(ERR_LOG); +// +// clear_mem(INIT_LOG); +// clear_mem(FAST_LOG); +//// clear_mem(ALARM_SAVE_MEMORY); +//// clear_mem(ERR_LOG); +// +//// SizeLog = log_params.end_address_log - log_params.start_address_log; // END_ADDRESS_LOG - START_ADDRESS_LOG; //ERR_BLOCK_SIZE*600; +// SizeLogErr = log_params.end_address_err_log - log_params.start_address_err_log; // END_ADDRESS_ERR_LOG - START_ADDRESS_ERR_LOG;//(long)ERR_BLOCK_SIZE*(long)3000; +// SizeLogSlow = log_params.end_address_save_log_memory - log_params.start_address_save_log_memory; // END_ADDRESS_LOG_SLOW - START_ADDRESS_LOG_SLOW; +// +// sizeHiword = SizeLogErr >> 16; +// sizeLoword = SizeLogErr; +// +// WriteMemory(ADDR_SIZE_ERR_LOW, sizeLoword); +// WriteMemory(ADDR_SIZE_ERR_HIGH, sizeHiword); +// +// sizeHiword = SizeLogSlow >> 16; +// sizeLoword = SizeLogSlow; +// WriteMemory(ADDR_SIZE_SLOW_LOW, sizeLoword); +// WriteMemory(ADDR_SIZE_SLOW_HIGH, sizeHiword); //!!! +// +// WriteMemory(ADDR_ERR_BLOCK_SIZE, log_params.BlockSizeErr); +// WriteMemory(ADDR_SLOW_BLOCK_SIZE, log_params.BlockSizeSlow); +// +// addrHiword = log_params.start_address_err_log >> 16; +// addrLoword = log_params.start_address_err_log; +// WriteMemory(ADDR_START_ADDR_ERR_LOG_LOW, addrLoword); +// WriteMemory(ADDR_START_ADDR_ERR_LOG_HIGH, addrHiword); +// +// addrHiword = log_params.start_address_save_log_memory >> 16; +// addrLoword = log_params.start_address_save_log_memory; +// WriteMemory(ADDR_START_ADDR_SLOW_LOG_LOW, addrLoword); +// WriteMemory(ADDR_START_ADDR_SLOW_LOG_HIGH, addrHiword); +//} + + diff --git a/Inu/Src/N12_Libs/log_params.h b/Inu/Src/N12_Libs/log_params.h new file mode 100644 index 0000000..f555df3 --- /dev/null +++ b/Inu/Src/N12_Libs/log_params.h @@ -0,0 +1,109 @@ + +#ifndef _LOG_PARAMS +#define _LOG_PARAMS + +#define PERIOD_LOGS 3 + + +#define START_ADDRESS_LOG 0xA0000 //0xa0000 +#define START_ADDRESS_LOG_SLOW 0xC0000 //0xa0000 +#define END_ADDRESS_LOGS 0x0dffff //0x0ef000 +#define END_ADDRESS_LOGS_FINAL 0x0efff0 //0x0ef000 + +//#define COUNTER_ERR_WRITES 1 +#define VOLUME_OF_FAST_LOG 2000L //0x800L // 0x1000 //0x3500 +#define VOLUME_OF_SLOW_LOG 2000L //0x800L // 0x800 // 0x1000 //0x3500 + + +//#define MAX_SUZE_LOG 0x20000 +//#define END_ADDRESS_LOD_TEMP 0xC0000 +//#define START_ADDRESS_SAVE_ON_ALARM 0xC0000 + +//#define LENGTH_HAZARD 100 +#define COUNT_SAVE_LOG_OFF 50 //500 + + + +#define ADDR_SIZE_ERR_LOW 0xa0000 +#define ADDR_SIZE_ERR_HIGH 0xa0001 +#define ADDR_SIZE_SLOW_LOW 0xa0002 +#define ADDR_SIZE_SLOW_HIGH 0xa0003 +#define ADDR_ERR_BLOCK_SIZE 0xa0004 +#define ADDR_SLOW_BLOCK_SIZE 0xa0005 +#define ADDR_START_ADDR_ERR_LOG_LOW 0xa0006 +#define ADDR_START_ADDR_ERR_LOG_HIGH 0xa0007 +#define ADDR_START_ADDR_SLOW_LOG_LOW 0xa0008 +#define ADDR_START_ADDR_SLOW_LOG_HIGH 0xa0009 + + +#define START_ADDR_TIME_ERR_WRITE 0xa000a +#define END_ADDR_TIME_ERR_WRITE 0xa000e +#define LAST_WRITTEN_BLOCK 0xa000f + + + +typedef struct +{ + int stop_log_level_1; + int stop_log_level_2; + + int stop_log_slow_level_1; + int stop_log_slow_level_2; + + + unsigned int init; + unsigned int BlockSizeErr; + unsigned int BlockSizeSlow; + + + unsigned long start_address_log;//START_ADDRESS_LOG + unsigned long end_address_log;//END_ADDRESS_LOG + unsigned long end_address_log_level_1;//END_ADDRESS_LOG_LEVEL_2 + unsigned long end_address_log_level_2; + + // unsigned long addr_size_err_low;//ADDR_SIZE_ERR_LOW + + unsigned long start_address_log_slow;//START_ADDRESS_LOG_SLOW + unsigned long end_address_log_slow; +// unsigned long start_address_save_log_memory; +// unsigned long end_address_save_log_memory; + + unsigned long end_address_log_slow_level_1; + unsigned long end_address_log_slow_level_2; +// unsigned long end_address_log_slow_level_3; +// unsigned long start_address_err_log;//START_ADDRESS_ERR_LOG +// unsigned long end_address_err_log;//END_ADDRESS_ERR_LOG + + unsigned long addres_mem;//START_ADDRESS_LOG + unsigned long addres_mem_slow;//START_ADDRESS_LOG + unsigned int log_cycle_done; + unsigned int log_cycle_done_slow; + + int no_write_slow; + int no_write_fast; + int size_slow_done; + int size_fast_done; + + int stop_log_fast; + int stop_log_slow; + int log_saved_to_const_mem; + int copy_log_to_const_memory; + + unsigned int volume_of_fast_log; + unsigned int volume_of_slow_log; + + unsigned int cur_volume_of_fast_log; + unsigned int cur_volume_of_slow_log; + + + +} TYPE_LOG_PARAMS; + +#define TYPE_LOG_PARAMS_DEFAULT {0,0,0,0, 0,0,0,0, 0,0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0, 0,0, 0,0} + +extern TYPE_LOG_PARAMS log_params; + +void initErrLog(void); +void initLogSize(unsigned int c_fast, unsigned int c_slow); + +#endif //_LOG_PARAMS diff --git a/Inu/Src/N12_Libs/log_to_memory.c b/Inu/Src/N12_Libs/log_to_memory.c new file mode 100644 index 0000000..510d698 --- /dev/null +++ b/Inu/Src/N12_Libs/log_to_memory.c @@ -0,0 +1,484 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2001. */ +/****************************************************************/ +/* log_to_mem.c + **************************************************************** + * y * + ****************************************************************/ + +#include "log_to_memory.h" +#include "MemoryFunctions.h" +#include "log_params.h" + +#include "global_time.h" + +// +// / logs_data(), write_to_mem clear_mem +// y y (. / write_to_mem) + +//#pragma DATA_SECTION(count_mem, ".fast_vars1"); +//static unsigned long count_mem = START_ADDRESS_LOG; //static +//#pragma DATA_SECTION(count_mem_slow, ".fast_vars1"); +//static unsigned long count_mem_slow; // = START_ADDRESS_LOG_SLOW;//START_ADDRESS_LOG_SLOW; //static +//#pragma DATA_SECTION(count_mem_err, ".fast_vars1"); +//static unsigned long count_mem_err; // = START_ADDRESS_ERR_LOG;//START_ADDRESS_ERR_LOG; //static +//#pragma DATA_SECTION(count_mem_init, ".fast_vars1"); +//static unsigned long count_mem_init = ADDR_SIZE_ERR_LOW; + +// y y +// y +int hb_logs_data = 0; +//int stop_log = 0; +//int stop_log_slow = 0; +//int block_size_counter_slow = 0; + +//int block_size_counter_fast = 0; + +//#pragma DATA_SECTION(LOAG, ".fast_vars1"); +//int LOAG[12]; + +#pragma DATA_SECTION(logsdata, ".fast_vars1"); +LOGSDATA logsdata = LOGSDATA_DEFAULT; + +//int no_write = 0; // , ( ) +//int no_write_slow = 0; // , ( ) + +//int size_fast_done = 0; +//int size_slow_done = 0; + + +//#pragma CODE_SECTION(clear_logpar,".fast_run"); +void clear_logpar(void) +{ + int i; + for(i=0;i= log_params.end_address_log) + log_params.addres_mem = log_params.end_address_log; + + WriteMemory(log_params.addres_mem, DataM); + // Fast_log_written = 1; + // if (one_block) block_size_counter++; + // *(int *)count_mem = ((DataM & 0xFFFF) ); + log_params.addres_mem++; + + return; + } + + if (tlog == SLOW_LOG) + { + if (!log_params.size_slow_done) + { + log_params.BlockSizeSlow++; + return; + } + + if (log_params.no_write_slow) + return; +// if (logpar.stop_log_level_1) +// return; + if (log_params.addres_mem_slow >= log_params.end_address_log_slow) + log_params.addres_mem_slow = log_params.end_address_log_slow; + + WriteMemory(log_params.addres_mem_slow, DataM); + // Fast_log_written = 1; + // if (one_block) block_size_counter++; + // *(int *)count_mem = ((DataM & 0xFFFF) ); + log_params.addres_mem_slow++; + return; + } + +// if (tlog == ALARM_SAVE_MEMORY) +// { +// +// if (!size_slow_done) +// { +// block_size_counter_slow++; +// return; +// } +// +// if (no_write_slow) +// return; +// +// if (logpar.stop_log_slow_level_1) +// return; +// +// if (count_mem_slow >= log_params.end_address_save_log_memory) +// count_mem_slow = log_params.end_address_save_log_memory; +// +// WriteMemory(count_mem_slow, DataM); +// count_mem_slow++; +// +// return; +// } + + /* if (tlog==ERR_LOG) + { + if (count_mem_err >= END_ADDRESS_ERR_LOG) count_mem_err = END_ADDRESS_ERR_LOG; + WriteMemory(count_mem_err,DataM); + count_mem_err++; + } +*/ +} + +#pragma CODE_SECTION(test_mem_limit, ".fast_run"); +void test_mem_limit(int tlog, int ciclelog) +{ + + if (tlog == FAST_LOG) + { + // block_size_counter = 0; + if (log_params.addres_mem >= log_params.end_address_log) + { + log_params.log_cycle_done = 1; + if (ciclelog == 1) + { + log_params.stop_log_fast = 0; +// log_params.stop_log_level_1 = 0; + log_params.addres_mem = log_params.start_address_log; + } + else + { + log_params.stop_log_fast = 1; +// log_params.stop_log_level_1 = 1; + } + } + + if (log_params.addres_mem >= (log_params.end_address_log_level_1)) + { + log_params.stop_log_level_1 = 1; + } + else + { + log_params.stop_log_level_1 = 0; + } + + if (log_params.addres_mem >= (log_params.end_address_log_level_2)) + { + log_params.stop_log_level_2 = 1; + } + else + { + log_params.stop_log_level_2 = 0; + } + return; + } + + if (tlog == SLOW_LOG) + { + // block_size_counter = 0; + if (log_params.addres_mem_slow >= log_params.end_address_log_slow) + { + log_params.log_cycle_done_slow = 1; + if (ciclelog == 1) + { + log_params.stop_log_slow = 0; + /// logpar.stop_log_level_1 = 0; + log_params.addres_mem_slow= log_params.start_address_log_slow; + } + else + { + log_params.stop_log_slow = 1; + // logpar.stop_log_level_1 = 1; + } + + if (log_params.addres_mem_slow >= (log_params.end_address_log_slow_level_1)) + { + log_params.stop_log_slow_level_1= 1; + } + else + { + log_params.stop_log_slow_level_1 = 0; + } + + if (log_params.addres_mem_slow >= (log_params.end_address_log_slow_level_2)) + { + log_params.stop_log_slow_level_2 = 1; + } + else + { + log_params.stop_log_slow_level_2 = 0; + } + } + + return; + } +// if (tlog == ALARM_SAVE_MEMORY) +// { +// if (ciclelog == 1) +// { +// logpar.stop_log_slow_level_1 = 0; +// } +// +// if (count_mem_slow >= (log_params.end_address_save_log_memory - LENGTH_HAZARD)) +// { +// if (ciclelog == 1) +// { +// stop_log_slow = 0; +// logpar.stop_log_slow_level_1 = 0; +// count_mem_slow = log_params.start_address_save_log_memory; +// } +// else +// { +// stop_log_slow = 1; +// logpar.stop_log_slow_level_1 = 1; +// } +// } +// +// if (count_mem_slow >= (log_params.end_address_log_slow_level_2)) +// { +// logpar.stop_log_slow_level_2 = 1; +// } +// else +// { +// logpar.stop_log_slow_level_2 = 0; +// } +// +// if (count_mem_slow >= (log_params.end_address_log_slow_level_3)) +// { +// logpar.stop_log_slow_level_3 = 1; +// } +// else +// { +// logpar.stop_log_slow_level_3 = 0; +// } +// +// return; +// } +} + +// y, +void clear_mem(int tlog) +{ + + + if (tlog == FAST_LOG) + { + + for (log_params.addres_mem = log_params.start_address_log; log_params.addres_mem < log_params.end_address_log; log_params.addres_mem++) + WriteMemory(log_params.addres_mem, 0x0); + + log_params.addres_mem = log_params.start_address_log; + hb_logs_data = 0; + log_params.stop_log_fast = 0; + + log_params.stop_log_level_1 = 0; + log_params.stop_log_level_2 = 0; + + return; + } + + if (tlog == SLOW_LOG) + { + + for (log_params.addres_mem_slow = log_params.start_address_log_slow; log_params.addres_mem_slow < log_params.end_address_log_slow; log_params.addres_mem_slow++) + WriteMemory(log_params.addres_mem_slow, 0x0); + + log_params.addres_mem_slow = log_params.start_address_log_slow; + hb_logs_data = 0; + log_params.stop_log_slow = 0; + log_params.stop_log_slow_level_1 = 0; + log_params.stop_log_slow_level_2 = 0; + + + + return; + } +// if (tlog == ALARM_SAVE_MEMORY) +// { +// +// for (count_mem_slow = log_params.start_address_save_log_memory; count_mem_slow < log_params.end_address_save_log_memory; count_mem_slow++) +// WriteMemory(count_mem_slow, 0x0); +// +// count_mem_slow = log_params.start_address_save_log_memory; +// hb_logs_data = 0; +// stop_log_slow = 0; +// +// logpar.stop_log_slow_level_1 = 0; +// logpar.stop_log_slow_level_2 = 0; +// logpar.stop_log_slow_level_3 = 0; +// +// return; +// } + +// if (tlog == ERR_LOG) +// { +// +// for (count_mem_err = log_params.start_address_err_log; count_mem_err < log_params.end_address_err_log; count_mem_err++) +// WriteMemory(count_mem_err, 0x0); +// +// count_mem_err = log_params.start_address_err_log; +// return; +// } + +// if (tlog == INIT_LOG) +// { +// for (count_mem_init = ADDR_SIZE_ERR_LOW; count_mem_init <= END_ADDR_TIME_ERR_WRITE; count_mem_init++) +// WriteMemory(count_mem_init, 0x0); +// +// count_mem_init = ADDR_SIZE_ERR_LOW; +// return; +// } +} + +// +void clear_mem_all() { + for (log_params.addres_mem = START_ADDRESS_LOG; log_params.addres_mem < END_ADDRESS_LOGS; log_params.addres_mem++) { + WriteMemory(log_params.addres_mem, 0x0); + } + + log_params.addres_mem = log_params.start_address_log; + log_params.stop_log_fast = 0; + log_params.stop_log_level_1 = 0; + log_params.stop_log_level_2 = 0; + log_params.log_cycle_done = 0; + + hb_logs_data = 0; + log_params.addres_mem_slow = log_params.start_address_log_slow; + log_params.stop_log_slow = 0; + log_params.stop_log_slow_level_1 = 0; + log_params.stop_log_slow_level_2 = 0; + +} + +// +void set_start_mem(int tlog) +{ + + if (tlog == FAST_LOG) + { + + log_params.addres_mem = log_params.start_address_log; + log_params.log_cycle_done = 0; + hb_logs_data = 0; + log_params.stop_log_fast = 0; + + log_params.stop_log_level_1 = 0; + log_params.stop_log_level_2 = 0; + } + + if (tlog == SLOW_LOG) + { + + log_params.addres_mem_slow = log_params.start_address_log_slow; + log_params.log_cycle_done = 0; + hb_logs_data = 0; + log_params.stop_log_slow = 0; + + log_params.stop_log_slow_level_1 = 0; + log_params.stop_log_slow_level_2 = 0; + } + +// if (tlog == ALARM_SAVE_MEMORY) +// { +// +// count_mem_slow = log_params.start_address_save_log_memory; +// hb_logs_data = 0; +// stop_log_slow = 0; +// +// logpar.stop_log_slow_level_1 = 0; +// logpar.stop_log_slow_level_2 = 0; +// logpar.stop_log_slow_level_3 = 0; +// } + +// if (tlog == ERR_LOG) +// { +// +// count_mem_err = log_params.start_address_err_log; +// hb_logs_data = 0; +// stop_log_slow = 0; +// +// logpar.stop_log_slow_level_1 = 0; +// logpar.stop_log_slow_level_2 = 0; +// logpar.stop_log_slow_level_3 = 0; +// } +// if (tlog == INIT_LOG) +// { +// count_mem_init = ADDR_SIZE_ERR_LOW; +// } +} + + +#pragma CODE_SECTION(getFastLogs, ".fast_run2"); +void getFastLogs(int cicleLog) +{ + int i_log; + + if (log_params.size_fast_done) + test_mem_limit(FAST_LOG, cicleLog); + + for (i_log=0;i_log0) + log_params.cur_volume_of_slow_log--; + else + log_params.cur_volume_of_slow_log = log_params.volume_of_slow_log; + + log_params.size_slow_done = 1; +} + + +//void copyLogsToSaveArea() +//{ +// unsigned long from = START_ADDRESS_LOG; +// unsigned long to = START_ADDRESS_SAVE_ON_ALARM; +// +// for (;from <= log_params.end_address_log && to < END_ADDRESS_LOGS ;++from, ++to) { +// WriteMemory(to, ReadMemory(from)); +// } +//} + +//void copyLogsToSaveAreaUnrolled() +//{ +// unsigned long from = log_params.log_cycle_done ? log_params.addres_mem : log_params.start_address_log; +// unsigned long to = START_ADDRESS_SAVE_ON_ALARM; +// unsigned long count = log_params.end_address_log - log_params.start_address_log; +// +// for (;count-- > 0 && to < END_ADDRESS_LOGS ;++from, ++to) { +// if (from >= log_params.end_address_log) { +// from = log_params.start_address_log; +// } +// WriteMemory(to, ReadMemory(from)); +// } +//} + diff --git a/Inu/Src/N12_Libs/log_to_memory.h b/Inu/Src/N12_Libs/log_to_memory.h new file mode 100644 index 0000000..7f1d691 --- /dev/null +++ b/Inu/Src/N12_Libs/log_to_memory.h @@ -0,0 +1,96 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2001. */ +/****************************************************************/ +/* log_to_mem.h + **************************************************************** + * y * + ****************************************************************/ + +#ifndef _LOG_TO_MEM +#define _LOG_TO_MEM + + + + +#ifdef __cplusplus + extern "C" { +#endif + +#define SIZE_LOGS_ARRAY 92 + +#define INIT_LOG 3 +//#define ERR_LOG 2 +//#define ALARM_SAVE_MEMORY 1 +#define FAST_LOG 0 +#define SLOW_LOG 4 +#define ALL_LOG 5 + + +typedef struct +{ +// int copy_log_to_const_memory; +// +//// int start_write_fast_log; // , count_log_params_fast_log +//// int count_log_params_fast_log; // +// +// int block_size_counter_fast; +// int block_size_counter_slow; +// + int block_size_fast; + int block_size_slow; + + int logs[SIZE_LOGS_ARRAY]; + +} LOGSDATA; + +//extern int LOAG[]; + +#define LOGSDATA_DEFAULT {0,0, {0} } + + +/* */ +#define NO_ROTATE_LOG 0 + +//extern int no_write; // , ( ) +//extern int stop_log; // +//extern int Fast_log_written; //FAST LOG +//extern int block_size_counter_slow; +//extern int block_size_counter_fast; + +//extern int block_size_counter;// +//extern int size_fast_done; +//extern int size_slow_done; + + +/* y, */ +void write_to_mem(int tlog,int DataM); +void write_to_mem_a(int DataM); + + +/* y y */ +void test_mem_limit(int tlog,int ciclelog); +void set_start_mem(int tlog); + +/* y () */ +void clear_mem(int tlog); +void clear_mem_all(void); + +void getFastLogs(int cicleLog); +void getSlowLogs(int cicleLog); + +// +void copyLogsToSaveArea(void); +// . +// . +void copyLogsToSaveAreaUnrolled(void); +void clear_logpar(void); + +extern LOGSDATA logsdata; + +#ifdef __cplusplus + } +#endif + +#endif /* _LOG_TO_MEM */ diff --git a/Inu/Src/N12_Libs/math_pi.h b/Inu/Src/N12_Libs/math_pi.h new file mode 100644 index 0000000..a12ecd2 --- /dev/null +++ b/Inu/Src/N12_Libs/math_pi.h @@ -0,0 +1,50 @@ +/* + * math_pi.h + * + * Created on: 6 . 2020 . + * Author: stud + */ + +#ifndef SRC_LIBS_NIO12_MATH_PI_H_ +#define SRC_LIBS_NIO12_MATH_PI_H_ + + +#define CONST_SQRT3 29058990 //1.7320508075688772935274463415059 = sqrt(3) +#define CONST_SQRT3_2 14529495 //1.7320508075688772935274463415059/2=0.8660254 = sqrt(3)/2 +#define CONST_IQ_1 16777216 //1 + + +#define CONST_IQ_2 33554432 //2 + + + +#define CONST_IQ_01 1677721 //0.1 +#define CONST_IQ_02 3355442 //0.2 +#define CONST_IQ_03 5033163 //0.3 +#define CONST_IQ_04 6710884 //0.4 +#define CONST_IQ_05 8388608 //0.5 + +#define CONST_IQ_06 10066329 //0.6 +#define CONST_IQ_07 11744051 //0.7 +#define CONST_IQ_08 13421772 //0.8 +#define CONST_IQ_09 15099494 //0.9 + + +#define CONST_IQ_PI6 8784530 //30 +#define CONST_IQ_PI3 17569060 // 60 +#define CONST_IQ_PI05 26353589 // 90 +#define CONST_IQ_PI 52707178 // 180 +//#define CONST_IQ_OUR1 35664138 // +#define CONST_IQ_2PI 105414357 // 360 +#define CONST_IQ_120G 35138119 // 120 grad +#define CONST_IQ_3 50331648 // 3 + +//#define IQ_ALFA_SATURATION1 15099494//16441671//15099494 +//#define IQ_ALFA_SATURATION2 1677721//16441671//15099494 + + +#define PI 3.1415926535897932384626433832795 + + + +#endif /* SRC_LIBS_NIO12_MATH_PI_H_ */ diff --git a/Inu/Src/N12_Libs/mathlib.c b/Inu/Src/N12_Libs/mathlib.c new file mode 100644 index 0000000..b8d401c --- /dev/null +++ b/Inu/Src/N12_Libs/mathlib.c @@ -0,0 +1,437 @@ +/* + + () 2002 . + + Processor: TMS320C32 + + Filename: vector_troll.h + + y + + Edit date: 04-12-02 + + Function: + + Revisions: +*/ +#include "IQmathLib.h" + +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include +#include "mathlib.h" + +#include "params_norma.h" +#include "math_pi.h" +#include "params_pwm24.h" +#include +#include "params_norma.h" + +_iq SQRT_32 = _IQ(0.8660254037844); +_iq CONST_23 = _IQ(2.0/3.0); +_iq CONST_15 = _IQ(1.5); + + + + +#define real float + +float my_satur_float(float Input, float Positive, float Negative, float DeadZone) +{ + if (fabs(DeadZone)>0.000001 && Input>-DeadZone && Input=Positive) Input=Positive; + else + if (Input<=Negative) Input=Negative; + + return Input; +} + +int my_satur_int(int Input, int Positive, int Negative, int DeadZone) +{ + if (DeadZone!=0 && Input>-DeadZone && Input=Positive) Input=Positive; + else + if (Input<=Negative) Input=Negative; + + return Input; +} + +long my_satur_long(long Input, long Positive, long Negative, long DeadZone) +{ + + if (DeadZone!=0 && Input>-DeadZone && Input=Positive) Input=Positive; + else + if (Input<=Negative) Input=Negative; + + return Input; +} +/* + + +real pid_regul(real Kp_regul, real Tperiod_regul, real Minimum, real Maximum, + real yk, real *uk1, real *yk1, real *yzad, real *ek, real *ek1, real *ek2, + real d0, real d1, real d2) +{ + real uk; + + + *ek = - yk + *yzad; + uk = *uk1 + Kp_regul * ( d0 * *ek + d1 * *ek1 + d2 * *ek2 ); + + if (uk>Maximum) uk=Maximum; + if (ukMaximum) uk=Maximum; + if (ukMaximum) *VarIntegral=Maximum; + if (*VarIntegralMaximum) VarOut=Maximum; + if (VarOutStepP) || (deltaVar<-StepN)) + { + if (deltaVar>0) InpVarCurr += StepP; + else InpVarCurr -= StepN; + } + else + InpVarCurr=InpVarInstant; + + + VarOut = InpVarCurr; + return VarOut; +} + +#pragma CODE_SECTION(zad_intensiv_q,".fast_run"); +_iq zad_intensiv_q(_iq StepP, _iq StepN, _iq InpVarCurr, _iq InpVarInstant) +{ + _iq deltaVar, VarOut; + + deltaVar = InpVarInstant-InpVarCurr; + + if ((deltaVar>StepP) || (deltaVar<-StepN)) + { + if (deltaVar>0) InpVarCurr += StepP; + else InpVarCurr -= StepN; + } + else + InpVarCurr=InpVarInstant; + + + VarOut = InpVarCurr; + return VarOut; + + +} + + + + + + +real pi_regul3(real Kp_regul, real ki_regul, real Tperiod_regul, real Minimum, real Maximum, + real InpVar, real *InpVarPrev, real *OutVarPrev) +{ + real VarOut; + + + VarOut = Kp_regul*(ki_regul/Kp_regul*Tperiod_regul/2.0+1)*InpVar + Kp_regul*(ki_regul/Kp_regul*Tperiod_regul/2.0-1) * (*InpVarPrev) + *OutVarPrev; + + if (VarOut>Maximum) VarOut=Maximum; + if (VarOutMaximum) VarOut=Maximum; + if (VarOutdata_array == 0) return 0; + for (i = 0; i < v->size_array; ++i) { + summ_squares += _IQmpy(v->data_array[i], v->data_array[i]); + } + return _IQsqrt(summ_squares / v->size_array); +} + +//_iq calc_rms_array_var_period(RMS_CALC_ARRAY_THINNING *v) { +// _iq summ_squares = 0; +// int i = 0; +// int count_elem = 0; +// if (v->signal_period > v->size_array) { +// v->signal_period = v->size_array; +// } +// count_elem = v->signal_period; +// i = v->last_elem_position; +// while (count_elem > 0) { +// summ_squares += _IQmpy(v->data_array[i], v->data_array[i]); +// i -= 1; +// if (i < 0) { i = v->size_array - 1; } +// count_elem -= 1; +// +// } +// v->Out_rms = _IQsqrt(summ_squares / v->signal_period); +// return v->Out_rms; +//} + +_iq calc_rms_array_var_period_IQ15(RMS_CALC_ARRAY_THINNING *v) { + _iq16 summ_squares = 0; + int i = 0; + int count_elem = 0; + if (v->data_array == 0) { + return 0; + } + if (v->signal_period > v->size_array) { + v->signal_period = v->size_array; + } + count_elem = v->signal_period; + i = v->last_elem_position; + while (count_elem > 0) { + summ_squares += 0;//_IQ15mpy(v->data_array[i], v->data_array[i]); + i -= 1; + if (i < 0) { i = v->size_array - 1; } + count_elem -= 1; + + } + v->Out_rms =_IQ15toIQ(_IQ15sqrt(summ_squares / v->signal_period)); + return v->Out_rms; +} + +float fast_round(float x) +{ + float d; + long i; + + + i = (long)x; + + if (x<0) + { + d = i - x; + if (d>=0.5) + i = i - 1; + } + else + { + d = x - i; + if (d>=0.5) + i = i + 1; + } + return (float)i; + +} + +float fast_round_with_delta(float prev, float x, float delta) +{ + float d; + long i; + + + i = (long)x; + + if (x<0) + { + d = i - x; + if (d>=0.5) + i = i - 1; + } + else + { + d = x - i; + if (d>=0.5) + i = i + 1; + } + + if (fabs(prev-x)>=delta) + return (float)i; + else + return (float)prev; + +} + + +float fast_round_with_limiter(float x, float lim) +{ + float d; + long i; + + + if (fabs(x)<=lim) + return 0; + + i = (long)x; + + if (x<0) + { + d = i - x; + if (d>=0.5) + i = i - 1; + } + else + { + d = x - i; + if (d>=0.5) + i = i + 1; + } + return (float)i; + +} + + +#pragma CODE_SECTION(calc_rms,".fast_run"); +_iq calc_rms(_iq input, _iq input_prev, _iq freq_signal) +{ + static _iq pi_pwm = _IQ(PI*NORMA_FROTOR/(FREQ_PWM/5.0)); + + _iq cosw, sinw, wdt, y2, z1, z2, z3, y; + + wdt = _IQmpy(pi_pwm,freq_signal); + sinw = _IQsinPU(wdt); + cosw = _IQcosPU(wdt); + + if (cosw==0) + return 0; + + z1 = input_prev - _IQmpy(input,cosw); +// z2 = sinw; + z3 = _IQdiv(z1,sinw); + + y2 = _IQmpy(input,input)+_IQmpy(z3,z3); + +// cosw = _IQsin(); + + y = _IQsqrt(y2); + return y; +} + + + diff --git a/Inu/Src/N12_Libs/mathlib.h b/Inu/Src/N12_Libs/mathlib.h new file mode 100644 index 0000000..2910690 --- /dev/null +++ b/Inu/Src/N12_Libs/mathlib.h @@ -0,0 +1,81 @@ + +#ifndef _MATHLIB +#define _MATHLIB + +#include "IQmathLib.h" + + +/* + +real pi_regul(real Kp_regul, real Tintegral_regul, real Tperiod_regul, + real Minimum, real Maximum, real InpVar, real *VarIntegral); + +real exp_regul(real Tperiod_regul, real Texp_regul, real InpVarCurr, real InpVarInstant); + + + +real pid_regul2(real Kp_regul, real Tperiod_regul, real Minimum, real Maximum, + real yk, real *uk1, real *yk1, real *yk2, real *yzad, + real d0, real d1, real d2); + +real pid_regul(real Kp_regul, real Tperiod_regul, real Minimum, real Maximum, + real yk, real *uk1, real *yk1, real *yzad, real *ek, real *ek1, real *ek2, + real d0, real d1, real d2); + +real pi_regul3(real Kp_regul, real ki_regul, real Tperiod_regul, real Minimum, real Maximum, + real InpVar, real *InpVarPrev, real *OutVarPrev); + +real pi_regul4(real Kp_regul, real ki_regul, real Tperiod_regul, real Minimum, real Maximum, + real InpVar, real *InpVarPrev, real *OutVarPrev); + +*/ +float zad_intensiv(float StepP, float StepN, float InpVarCurr, float InpVarInstant); + +_iq zad_intensiv_q(_iq StepP, _iq StepN, _iq InpVarCurr, _iq InpVarInstant); +_iq im_calc( _iq ia, _iq ib, _iq ic); + +float exp_regul(float Tperiod_regul, float Texp_regul, float InpVarCurr, float InpVarInstant); + + + +float my_satur_float(float Input, float Positive, float Negative, float DeadZone); + +int my_satur_int(int Input, int Positive, int Negative, int DeadZone); +long my_satur_long(long Input, long Positive, long Negative, long DeadZone); + + + + +#define exp_regul_fast(Tperiod_regul,Texp_regul,InpVarCurr,InpVarInstant) (InpVarCurr + Tperiod_regul*(InpVarInstant-InpVarCurr)/Texp_regul) + +typedef struct { + _iq *data_array; + int size_array; + _iq (*calc)(); +} RMS_CALC_ARRAY; + +#define RMS_CALC_DEFAULTS { 0,0, calc_rms_array_simple} + +_iq calc_rms_array_simple(RMS_CALC_ARRAY *v); + +typedef struct { + _iq16 *data_array; + int size_array; + int last_elem_position; + int signal_period; + _iq Out_rms; + _iq (*calc)(); +} RMS_CALC_ARRAY_THINNING; + +#define RMS_CALC_THINNING_DEFAULTS { 0,0,0,0,0, calc_rms_array_var_period_IQ15} + +_iq calc_rms_array_var_period(RMS_CALC_ARRAY_THINNING *v); +_iq calc_rms_array_var_period_IQ15(RMS_CALC_ARRAY_THINNING *v); +float fast_round(float x); +float fast_round_with_limiter(float x, float lim); +float fast_round_with_delta(float prev, float x, float delta); + +_iq calc_rms(_iq input, _iq input_prev, _iq freq_signal); + +#endif + diff --git a/Inu/Src/N12_Libs/modbus_table_v2.c b/Inu/Src/N12_Libs/modbus_table_v2.c new file mode 100644 index 0000000..0ccb1ef --- /dev/null +++ b/Inu/Src/N12_Libs/modbus_table_v2.c @@ -0,0 +1,89 @@ +#include "modbus_table_v2.h" + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "RS_Functions.h" +#include "xp_project.h" +//#include "modbus_fill_table.h" +//#include "adc_tools.h" +//#include "can_setup.h" +//#include "isolation.h" +//#include "rotation_speed.h" + +// #include "IQmathLib.h" +//#include "errors.h" +//#include "params.h" +//#include "can_watercool.h" +// #include "doors_control.h" + +#pragma DATA_SECTION(modbus_table_rs_in,".logs"); +MODBUS_REG_STRUCT modbus_table_rs_in[SIZE_MODBUS_TABLE]; + + +#pragma DATA_SECTION(modbus_table_rs_out,".logs"); +MODBUS_REG_STRUCT modbus_table_rs_out[SIZE_MODBUS_TABLE]; + + +#pragma DATA_SECTION(modbus_table_can_in,".logs"); +MODBUS_REG_STRUCT modbus_table_can_in[SIZE_MODBUS_TABLE]; + + +#pragma DATA_SECTION(modbus_table_can_out,".logs"); +MODBUS_REG_STRUCT modbus_table_can_out[SIZE_MODBUS_TABLE]; + +#pragma DATA_SECTION(modbus_table_can_out_temp,".logs"); +MODBUS_REG_STRUCT modbus_table_can_out_temp[SIZE_MODBUS_TABLE]; + + + +void clear_modbus_table_in() +{ +int i; + + for (i=0;i +#include +#endif +#include + +//--------------------------------------------------------------------------- +// Various Usefull Constant Definitions: +// +#define QG GLOBAL_Q +#define Q30 30 +#define Q29 29 +#define Q28 28 +#define Q27 27 +#define Q26 26 +#define Q25 25 +#define Q24 24 +#define Q23 23 +#define Q22 22 +#define Q21 21 +#define Q20 20 +#define Q19 19 +#define Q18 18 +#define Q17 17 +#define Q16 16 +#define Q15 15 +#define Q14 14 +#define Q13 13 +#define Q12 12 +#define Q11 11 +#define Q10 10 +#define Q9 9 +#define Q8 8 +#define Q7 7 +#define Q6 6 +#define Q5 5 +#define Q4 4 +#define Q3 3 +#define Q2 2 +#define Q1 1 + +#define MAX_IQ_POS LONG_MAX +#define MAX_IQ_NEG LONG_MIN +#define MIN_IQ_POS 1 +#define MIN_IQ_NEG -1 + +//########################################################################### +#if MATH_TYPE == IQ_MATH +//########################################################################### +// If IQ_MATH is used, the following IQmath library function definitions +// are used: +//=========================================================================== +typedef long _iq; +typedef long _iq30; +typedef long _iq29; +typedef long _iq28; +typedef long _iq27; +typedef long _iq26; +typedef long _iq25; +typedef long _iq24; +typedef long _iq23; +typedef long _iq22; +typedef long _iq21; +typedef long _iq20; +typedef long _iq19; +typedef long _iq18; +typedef long _iq17; +typedef long _iq16; +typedef long _iq15; +typedef long _iq14; +typedef long _iq13; +typedef long _iq12; +typedef long _iq11; +typedef long _iq10; +typedef long _iq9; +typedef long _iq8; +typedef long _iq7; +typedef long _iq6; +typedef long _iq5; +typedef long _iq4; +typedef long _iq3; +typedef long _iq2; +typedef long _iq1; +//--------------------------------------------------------------------------- +#define _IQmpy2(A) ((A)<<1) +#define _IQmpy4(A) ((A)<<2) +#define _IQmpy8(A) ((A)<<3) +#define _IQmpy16(A) ((A)<<4) +#define _IQmpy32(A) ((A)<<5) +#define _IQmpy64(A) ((A)<<6) + +#define _IQdiv2(A) ((A)>>1) +#define _IQdiv4(A) ((A)>>2) +#define _IQdiv8(A) ((A)>>3) +#define _IQdiv16(A) ((A)>>4) +#define _IQdiv32(A) ((A)>>5) +#define _IQdiv64(A) ((A)>>6) +//--------------------------------------------------------------------------- +#define _IQ30(A) (long) ((A) * 1073741824.0L) +#define _IQ29(A) (long) ((A) * 536870912.0L) +#define _IQ28(A) (long) ((A) * 268435456.0L) +#define _IQ27(A) (long) ((A) * 134217728.0L) +#define _IQ26(A) (long) ((A) * 67108864.0L) +#define _IQ25(A) (long) ((A) * 33554432.0L) +#define _IQ24(A) (long) ((A) * 16777216.0L) +#define _IQ23(A) (long) ((A) * 8388608.0L) +#define _IQ22(A) (long) ((A) * 4194304.0L) +#define _IQ21(A) (long) ((A) * 2097152.0L) +#define _IQ20(A) (long) ((A) * 1048576.0L) +#define _IQ19(A) (long) ((A) * 524288.0L) +#define _IQ18(A) (long) ((A) * 262144.0L) +#define _IQ17(A) (long) ((A) * 131072.0L) +#define _IQ16(A) (long) ((A) * 65536.0L) +#define _IQ15(A) (long) ((A) * 32768.0L) +#define _IQ14(A) (long) ((A) * 16384.0L) +#define _IQ13(A) (long) ((A) * 8192.0L) +#define _IQ12(A) (long) ((A) * 4096.0L) +#define _IQ11(A) (long) ((A) * 2048.0L) +#define _IQ10(A) (long) ((A) * 1024.0L) +#define _IQ9(A) (long) ((A) * 512.0L) +#define _IQ8(A) (long) ((A) * 256.0L) +#define _IQ7(A) (long) ((A) * 128.0L) +#define _IQ6(A) (long) ((A) * 64.0L) +#define _IQ5(A) (long) ((A) * 32.0L) +#define _IQ4(A) (long) ((A) * 16.0L) +#define _IQ3(A) (long) ((A) * 8.0L) +#define _IQ2(A) (long) ((A) * 4.0L) +#define _IQ1(A) (long) ((A) * 2.0L) + +#if GLOBAL_Q == 30 +#define _IQ(A) _IQ30(A) +#endif +#if GLOBAL_Q == 29 +#define _IQ(A) _IQ29(A) +#endif +#if GLOBAL_Q == 28 +#define _IQ(A) _IQ28(A) +#endif +#if GLOBAL_Q == 27 +#define _IQ(A) _IQ27(A) +#endif +#if GLOBAL_Q == 26 +#define _IQ(A) _IQ26(A) +#endif +#if GLOBAL_Q == 25 +#define _IQ(A) _IQ25(A) +#endif +#if GLOBAL_Q == 24 +#define _IQ(A) _IQ24(A) +#endif +#if GLOBAL_Q == 23 +#define _IQ(A) _IQ23(A) +#endif +#if GLOBAL_Q == 22 +#define _IQ(A) _IQ22(A) +#endif +#if GLOBAL_Q == 21 +#define _IQ(A) _IQ21(A) +#endif +#if GLOBAL_Q == 20 +#define _IQ(A) _IQ20(A) +#endif +#if GLOBAL_Q == 19 +#define _IQ(A) _IQ19(A) +#endif +#if GLOBAL_Q == 18 +#define _IQ(A) _IQ18(A) +#endif +#if GLOBAL_Q == 17 +#define _IQ(A) _IQ17(A) +#endif +#if GLOBAL_Q == 16 +#define _IQ(A) _IQ16(A) +#endif +#if GLOBAL_Q == 15 +#define _IQ(A) _IQ15(A) +#endif +#if GLOBAL_Q == 14 +#define _IQ(A) _IQ14(A) +#endif +#if GLOBAL_Q == 13 +#define _IQ(A) _IQ13(A) +#endif +#if GLOBAL_Q == 12 +#define _IQ(A) _IQ12(A) +#endif +#if GLOBAL_Q == 11 +#define _IQ(A) _IQ11(A) +#endif +#if GLOBAL_Q == 10 +#define _IQ(A) _IQ10(A) +#endif +#if GLOBAL_Q == 9 +#define _IQ(A) _IQ9(A) +#endif +#if GLOBAL_Q == 8 +#define _IQ(A) _IQ8(A) +#endif +#if GLOBAL_Q == 7 +#define _IQ(A) _IQ7(A) +#endif +#if GLOBAL_Q == 6 +#define _IQ(A) _IQ6(A) +#endif +#if GLOBAL_Q == 5 +#define _IQ(A) _IQ5(A) +#endif +#if GLOBAL_Q == 4 +#define _IQ(A) _IQ4(A) +#endif +#if GLOBAL_Q == 3 +#define _IQ(A) _IQ3(A) +#endif +#if GLOBAL_Q == 2 +#define _IQ(A) _IQ2(A) +#endif +#if GLOBAL_Q == 1 +#define _IQ(A) _IQ1(A) +#endif +//--------------------------------------------------------------------------- +extern float _IQ30toF(long A); +extern float _IQ29toF(long A); +extern float _IQ28toF(long A); +extern float _IQ27toF(long A); +extern float _IQ26toF(long A); +extern float _IQ25toF(long A); +extern float _IQ24toF(long A); +extern float _IQ23toF(long A); +extern float _IQ22toF(long A); +extern float _IQ21toF(long A); +extern float _IQ20toF(long A); +extern float _IQ19toF(long A); +extern float _IQ18toF(long A); +extern float _IQ17toF(long A); +extern float _IQ16toF(long A); +extern float _IQ15toF(long A); +extern float _IQ14toF(long A); +extern float _IQ13toF(long A); +extern float _IQ12toF(long A); +extern float _IQ11toF(long A); +extern float _IQ10toF(long A); +extern float _IQ9toF(long A); +extern float _IQ8toF(long A); +extern float _IQ7toF(long A); +extern float _IQ6toF(long A); +extern float _IQ5toF(long A); +extern float _IQ4toF(long A); +extern float _IQ3toF(long A); +extern float _IQ2toF(long A); +extern float _IQ1toF(long A); + +#if GLOBAL_Q == 30 +#define _IQtoF(A) _IQ30toF(A) +#endif +#if GLOBAL_Q == 29 +#define _IQtoF(A) _IQ29toF(A) +#endif +#if GLOBAL_Q == 28 +#define _IQtoF(A) _IQ28toF(A) +#endif +#if GLOBAL_Q == 27 +#define _IQtoF(A) _IQ27toF(A) +#endif +#if GLOBAL_Q == 26 +#define _IQtoF(A) _IQ26toF(A) +#endif +#if GLOBAL_Q == 25 +#define _IQtoF(A) _IQ25toF(A) +#endif +#if GLOBAL_Q == 24 +#define _IQtoF(A) _IQ24toF(A) +#endif +#if GLOBAL_Q == 23 +#define _IQtoF(A) _IQ23toF(A) +#endif +#if GLOBAL_Q == 22 +#define _IQtoF(A) _IQ22toF(A) +#endif +#if GLOBAL_Q == 21 +#define _IQtoF(A) _IQ21toF(A) +#endif +#if GLOBAL_Q == 20 +#define _IQtoF(A) _IQ20toF(A) +#endif +#if GLOBAL_Q == 19 +#define _IQtoF(A) _IQ19toF(A) +#endif +#if GLOBAL_Q == 18 +#define _IQtoF(A) _IQ18toF(A) +#endif +#if GLOBAL_Q == 17 +#define _IQtoF(A) _IQ17toF(A) +#endif +#if GLOBAL_Q == 16 +#define _IQtoF(A) _IQ16toF(A) +#endif +#if GLOBAL_Q == 15 +#define _IQtoF(A) _IQ15toF(A) +#endif +#if GLOBAL_Q == 14 +#define _IQtoF(A) _IQ14toF(A) +#endif +#if GLOBAL_Q == 13 +#define _IQtoF(A) _IQ13toF(A) +#endif +#if GLOBAL_Q == 12 +#define _IQtoF(A) _IQ12toF(A) +#endif +#if GLOBAL_Q == 11 +#define _IQtoF(A) _IQ11toF(A) +#endif +#if GLOBAL_Q == 10 +#define _IQtoF(A) _IQ10toF(A) +#endif +#if GLOBAL_Q == 9 +#define _IQtoF(A) _IQ9toF(A) +#endif +#if GLOBAL_Q == 8 +#define _IQtoF(A) _IQ8toF(A) +#endif +#if GLOBAL_Q == 7 +#define _IQtoF(A) _IQ7toF(A) +#endif +#if GLOBAL_Q == 6 +#define _IQtoF(A) _IQ6toF(A) +#endif +#if GLOBAL_Q == 5 +#define _IQtoF(A) _IQ5toF(A) +#endif +#if GLOBAL_Q == 4 +#define _IQtoF(A) _IQ4toF(A) +#endif +#if GLOBAL_Q == 3 +#define _IQtoF(A) _IQ3toF(A) +#endif +#if GLOBAL_Q == 2 +#define _IQtoF(A) _IQ2toF(A) +#endif +#if GLOBAL_Q == 1 +#define _IQtoF(A) _IQ1toF(A) +#endif +//--------------------------------------------------------------------------- +#define _IQsat(A, Pos, Neg) __IQsat(A, Pos, Neg) +//--------------------------------------------------------------------------- +#define _IQtoIQ30(A) ((long) (A) << (30 - GLOBAL_Q)) +#define _IQ30toIQ(A) ((long) (A) >> (30 - GLOBAL_Q)) + +#if (GLOBAL_Q >= 29) +#define _IQtoIQ29(A) ((long) (A) >> (GLOBAL_Q - 29)) +#define _IQ29toIQ(A) ((long) (A) << (GLOBAL_Q - 29)) +#else +#define _IQtoIQ29(A) ((long) (A) << (29 - GLOBAL_Q)) +#define _IQ29toIQ(A) ((long) (A) >> (29 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 28) +#define _IQtoIQ28(A) ((long) (A) >> (GLOBAL_Q - 28)) +#define _IQ28toIQ(A) ((long) (A) << (GLOBAL_Q - 28)) +#else +#define _IQtoIQ28(A) ((long) (A) << (28 - GLOBAL_Q)) +#define _IQ28toIQ(A) ((long) (A) >> (28 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 27) +#define _IQtoIQ27(A) ((long) (A) >> (GLOBAL_Q - 27)) +#define _IQ27toIQ(A) ((long) (A) << (GLOBAL_Q - 27)) +#else +#define _IQtoIQ27(A) ((long) (A) << (27 - GLOBAL_Q)) +#define _IQ27toIQ(A) ((long) (A) >> (27 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 26) +#define _IQtoIQ26(A) ((long) (A) >> (GLOBAL_Q - 26)) +#define _IQ26toIQ(A) ((long) (A) << (GLOBAL_Q - 26)) +#else +#define _IQtoIQ26(A) ((long) (A) << (26 - GLOBAL_Q)) +#define _IQ26toIQ(A) ((long) (A) >> (26 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 25) +#define _IQtoIQ25(A) ((long) (A) >> (GLOBAL_Q - 25)) +#define _IQ25toIQ(A) ((long) (A) << (GLOBAL_Q - 25)) +#else +#define _IQtoIQ25(A) ((long) (A) << (25 - GLOBAL_Q)) +#define _IQ25toIQ(A) ((long) (A) >> (25 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 24) +#define _IQtoIQ24(A) ((long) (A) >> (GLOBAL_Q - 24)) +#define _IQ24toIQ(A) ((long) (A) << (GLOBAL_Q - 24)) +#else +#define _IQtoIQ24(A) ((long) (A) << (24 - GLOBAL_Q)) +#define _IQ24toIQ(A) ((long) (A) >> (24 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 23) +#define _IQtoIQ23(A) ((long) (A) >> (GLOBAL_Q - 23)) +#define _IQ23toIQ(A) ((long) (A) << (GLOBAL_Q - 23)) +#else +#define _IQtoIQ23(A) ((long) (A) << (23 - GLOBAL_Q)) +#define _IQ23toIQ(A) ((long) (A) >> (23 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 22) +#define _IQtoIQ22(A) ((long) (A) >> (GLOBAL_Q - 22)) +#define _IQ22toIQ(A) ((long) (A) << (GLOBAL_Q - 22)) +#else +#define _IQtoIQ22(A) ((long) (A) << (22 - GLOBAL_Q)) +#define _IQ22toIQ(A) ((long) (A) >> (22 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 21) +#define _IQtoIQ21(A) ((long) (A) >> (GLOBAL_Q - 21)) +#define _IQ21toIQ(A) ((long) (A) << (GLOBAL_Q - 21)) +#else +#define _IQtoIQ21(A) ((long) (A) << (21 - GLOBAL_Q)) +#define _IQ21toIQ(A) ((long) (A) >> (21 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 20) +#define _IQtoIQ20(A) ((long) (A) >> (GLOBAL_Q - 20)) +#define _IQ20toIQ(A) ((long) (A) << (GLOBAL_Q - 20)) +#else +#define _IQtoIQ20(A) ((long) (A) << (20 - GLOBAL_Q)) +#define _IQ20toIQ(A) ((long) (A) >> (20 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 19) +#define _IQtoIQ19(A) ((long) (A) >> (GLOBAL_Q - 19)) +#define _IQ19toIQ(A) ((long) (A) << (GLOBAL_Q - 19)) +#else +#define _IQtoIQ19(A) ((long) (A) << (19 - GLOBAL_Q)) +#define _IQ19toIQ(A) ((long) (A) >> (19 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 18) +#define _IQtoIQ18(A) ((long) (A) >> (GLOBAL_Q - 18)) +#define _IQ18toIQ(A) ((long) (A) << (GLOBAL_Q - 18)) +#else +#define _IQtoIQ18(A) ((long) (A) << (18 - GLOBAL_Q)) +#define _IQ18toIQ(A) ((long) (A) >> (18 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 17) +#define _IQtoIQ17(A) ((long) (A) >> (GLOBAL_Q - 17)) +#define _IQ17toIQ(A) ((long) (A) << (GLOBAL_Q - 17)) +#else +#define _IQtoIQ17(A) ((long) (A) << (17 - GLOBAL_Q)) +#define _IQ17toIQ(A) ((long) (A) >> (17 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 16) +#define _IQtoIQ16(A) ((long) (A) >> (GLOBAL_Q - 16)) +#define _IQ16toIQ(A) ((long) (A) << (GLOBAL_Q - 16)) +#else +#define _IQtoIQ16(A) ((long) (A) << (16 - GLOBAL_Q)) +#define _IQ16toIQ(A) ((long) (A) >> (16 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 15) +#define _IQtoIQ15(A) ((long) (A) >> (GLOBAL_Q - 15)) +#define _IQ15toIQ(A) ((long) (A) << (GLOBAL_Q - 15)) +#define _IQtoQ15(A) ((long) (A) >> (GLOBAL_Q - 15)) +#define _Q15toIQ(A) ((long) (A) << (GLOBAL_Q - 15)) +#else +#define _IQtoIQ15(A) ((long) (A) << (15 - GLOBAL_Q)) +#define _IQ15toIQ(A) ((long) (A) >> (15 - GLOBAL_Q)) +#define _IQtoQ15(A) ((long) (A) << (15 - GLOBAL_Q)) +#define _Q15toIQ(A) ((long) (A) >> (15 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 14) +#define _IQtoIQ14(A) ((long) (A) >> (GLOBAL_Q - 14)) +#define _IQ14toIQ(A) ((long) (A) << (GLOBAL_Q - 14)) +#define _IQtoQ14(A) ((long) (A) >> (GLOBAL_Q - 14)) +#define _Q14toIQ(A) ((long) (A) << (GLOBAL_Q - 14)) +#else +#define _IQtoIQ14(A) ((long) (A) << (14 - GLOBAL_Q)) +#define _IQ14toIQ(A) ((long) (A) >> (14 - GLOBAL_Q)) +#define _IQtoQ14(A) ((long) (A) << (14 - GLOBAL_Q)) +#define _Q14toIQ(A) ((long) (A) >> (14 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 13) +#define _IQtoIQ13(A) ((long) (A) >> (GLOBAL_Q - 13)) +#define _IQ13toIQ(A) ((long) (A) << (GLOBAL_Q - 13)) +#define _IQtoQ13(A) ((long) (A) >> (GLOBAL_Q - 13)) +#define _Q13toIQ(A) ((long) (A) << (GLOBAL_Q - 13)) +#else +#define _IQtoIQ13(A) ((long) (A) << (13 - GLOBAL_Q)) +#define _IQ13toIQ(A) ((long) (A) >> (13 - GLOBAL_Q)) +#define _IQtoQ13(A) ((long) (A) << (13 - GLOBAL_Q)) +#define _Q13toIQ(A) ((long) (A) >> (13 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 12) +#define _IQtoIQ12(A) ((long) (A) >> (GLOBAL_Q - 12)) +#define _IQ12toIQ(A) ((long) (A) << (GLOBAL_Q - 12)) +#define _IQtoQ12(A) ((long) (A) >> (GLOBAL_Q - 12)) +#define _Q12toIQ(A) ((long) (A) << (GLOBAL_Q - 12)) +#else +#define _IQtoIQ12(A) ((long) (A) << (12 - GLOBAL_Q)) +#define _IQ12toIQ(A) ((long) (A) >> (12 - GLOBAL_Q)) +#define _IQtoQ12(A) ((long) (A) << (12 - GLOBAL_Q)) +#define _Q12toIQ(A) ((long) (A) >> (12 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 11) +#define _IQtoIQ11(A) ((long) (A) >> (GLOBAL_Q - 11)) +#define _IQ11toIQ(A) ((long) (A) << (GLOBAL_Q - 11)) +#define _IQtoQ11(A) ((long) (A) >> (GLOBAL_Q - 11)) +#define _Q11toIQ(A) ((long) (A) << (GLOBAL_Q - 11)) +#else +#define _IQtoIQ11(A) ((long) (A) << (11 - GLOBAL_Q)) +#define _IQ11toIQ(A) ((long) (A) >> (11 - GLOBAL_Q)) +#define _IQtoQ11(A) ((long) (A) << (11 - GLOBAL_Q)) +#define _Q11toIQ(A) ((long) (A) >> (11 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 10) +#define _IQtoIQ10(A) ((long) (A) >> (GLOBAL_Q - 10)) +#define _IQ10toIQ(A) ((long) (A) << (GLOBAL_Q - 10)) +#define _IQtoQ10(A) ((long) (A) >> (GLOBAL_Q - 10)) +#define _Q10toIQ(A) ((long) (A) << (GLOBAL_Q - 10)) +#else +#define _IQtoIQ10(A) ((long) (A) << (10 - GLOBAL_Q)) +#define _IQ10toIQ(A) ((long) (A) >> (10 - GLOBAL_Q)) +#define _IQtoQ10(A) ((long) (A) << (10 - GLOBAL_Q)) +#define _Q10toIQ(A) ((long) (A) >> (10 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 9) +#define _IQtoIQ9(A) ((long) (A) >> (GLOBAL_Q - 9)) +#define _IQ9toIQ(A) ((long) (A) << (GLOBAL_Q - 9)) +#define _IQtoQ9(A) ((long) (A) >> (GLOBAL_Q - 9)) +#define _Q9toIQ(A) ((long) (A) << (GLOBAL_Q - 9)) +#else +#define _IQtoIQ9(A) ((long) (A) << (9 - GLOBAL_Q)) +#define _IQ9toIQ(A) ((long) (A) >> (9 - GLOBAL_Q)) +#define _IQtoQ9(A) ((long) (A) << (9 - GLOBAL_Q)) +#define _Q9toIQ(A) ((long) (A) >> (9 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 8) +#define _IQtoIQ8(A) ((long) (A) >> (GLOBAL_Q - 8)) +#define _IQ8toIQ(A) ((long) (A) << (GLOBAL_Q - 8)) +#define _IQtoQ8(A) ((long) (A) >> (GLOBAL_Q - 8)) +#define _Q8toIQ(A) ((long) (A) << (GLOBAL_Q - 8)) +#else +#define _IQtoIQ8(A) ((long) (A) << (8 - GLOBAL_Q)) +#define _IQ8toIQ(A) ((long) (A) >> (8 - GLOBAL_Q)) +#define _IQtoQ8(A) ((long) (A) << (8 - GLOBAL_Q)) +#define _Q8toIQ(A) ((long) (A) >> (8 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 7) +#define _IQtoIQ7(A) ((long) (A) >> (GLOBAL_Q - 7)) +#define _IQ7toIQ(A) ((long) (A) << (GLOBAL_Q - 7)) +#define _IQtoQ7(A) ((long) (A) >> (GLOBAL_Q - 7)) +#define _Q7toIQ(A) ((long) (A) << (GLOBAL_Q - 7)) +#else +#define _IQtoIQ7(A) ((long) (A) << (7 - GLOBAL_Q)) +#define _IQ7toIQ(A) ((long) (A) >> (7 - GLOBAL_Q)) +#define _IQtoQ7(A) ((long) (A) << (7 - GLOBAL_Q)) +#define _Q7toIQ(A) ((long) (A) >> (7 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 6) +#define _IQtoIQ6(A) ((long) (A) >> (GLOBAL_Q - 6)) +#define _IQ6toIQ(A) ((long) (A) << (GLOBAL_Q - 6)) +#define _IQtoQ6(A) ((long) (A) >> (GLOBAL_Q - 6)) +#define _Q6toIQ(A) ((long) (A) << (GLOBAL_Q - 6)) +#else +#define _IQtoIQ6(A) ((long) (A) << (6 - GLOBAL_Q)) +#define _IQ6toIQ(A) ((long) (A) >> (6 - GLOBAL_Q)) +#define _IQtoQ6(A) ((long) (A) << (6 - GLOBAL_Q)) +#define _Q6toIQ(A) ((long) (A) >> (6 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 5) +#define _IQtoIQ5(A) ((long) (A) >> (GLOBAL_Q - 5)) +#define _IQ5toIQ(A) ((long) (A) << (GLOBAL_Q - 5)) +#define _IQtoQ5(A) ((long) (A) >> (GLOBAL_Q - 5)) +#define _Q5toIQ(A) ((long) (A) << (GLOBAL_Q - 5)) +#else +#define _IQtoIQ5(A) ((long) (A) << (5 - GLOBAL_Q)) +#define _IQ5toIQ(A) ((long) (A) >> (5 - GLOBAL_Q)) +#define _IQtoQ5(A) ((long) (A) << (5 - GLOBAL_Q)) +#define _Q5toIQ(A) ((long) (A) >> (5 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 4) +#define _IQtoIQ4(A) ((long) (A) >> (GLOBAL_Q - 4)) +#define _IQ4toIQ(A) ((long) (A) << (GLOBAL_Q - 4)) +#define _IQtoQ4(A) ((long) (A) >> (GLOBAL_Q - 4)) +#define _Q4toIQ(A) ((long) (A) << (GLOBAL_Q - 4)) +#else +#define _IQtoIQ4(A) ((long) (A) << (4 - GLOBAL_Q)) +#define _IQ4toIQ(A) ((long) (A) >> (4 - GLOBAL_Q)) +#define _IQtoQ4(A) ((long) (A) << (4 - GLOBAL_Q)) +#define _Q4toIQ(A) ((long) (A) >> (4 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 3) +#define _IQtoIQ3(A) ((long) (A) >> (GLOBAL_Q - 3)) +#define _IQ3toIQ(A) ((long) (A) << (GLOBAL_Q - 3)) +#define _IQtoQ3(A) ((long) (A) >> (GLOBAL_Q - 3)) +#define _Q3toIQ(A) ((long) (A) << (GLOBAL_Q - 3)) +#else +#define _IQtoIQ3(A) ((long) (A) << (3 - GLOBAL_Q)) +#define _IQ3toIQ(A) ((long) (A) >> (3 - GLOBAL_Q)) +#define _IQtoQ3(A) ((long) (A) << (3 - GLOBAL_Q)) +#define _Q3toIQ(A) ((long) (A) >> (3 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 2) +#define _IQtoIQ2(A) ((long) (A) >> (GLOBAL_Q - 2)) +#define _IQ2toIQ(A) ((long) (A) << (GLOBAL_Q - 2)) +#define _IQtoQ2(A) ((long) (A) >> (GLOBAL_Q - 2)) +#define _Q2toIQ(A) ((long) (A) << (GLOBAL_Q - 2)) +#else +#define _IQtoIQ2(A) ((long) (A) << (2 - GLOBAL_Q)) +#define _IQ2toIQ(A) ((long) (A) >> (2 - GLOBAL_Q)) +#define _IQtoQ2(A) ((long) (A) << (2 - GLOBAL_Q)) +#define _Q2toIQ(A) ((long) (A) >> (2 - GLOBAL_Q)) +#endif + +#if (GLOBAL_Q >= 1) +#define _IQtoQ1(A) ((long) (A) >> (GLOBAL_Q - 1)) +#define _Q1toIQ(A) ((long) (A) << (GLOBAL_Q - 1)) +#else +#define _IQtoQ1(A) ((long) (A) << (1 - GLOBAL_Q)) +#define _Q1toIQ(A) ((long) (A) >> (1 - GLOBAL_Q)) +#endif + +#define _IQtoIQ1(A) ((long) (A) >> (GLOBAL_Q - 1)) +#define _IQ1toIQ(A) ((long) (A) << (GLOBAL_Q - 1)) +//--------------------------------------------------------------------------- +#define _IQmpy(A,B) __IQmpy(A,B,GLOBAL_Q) +#define _IQ30mpy(A,B) __IQmpy(A,B,30) +#define _IQ29mpy(A,B) __IQmpy(A,B,29) +#define _IQ28mpy(A,B) __IQmpy(A,B,28) +#define _IQ27mpy(A,B) __IQmpy(A,B,27) +#define _IQ26mpy(A,B) __IQmpy(A,B,26) +#define _IQ25mpy(A,B) __IQmpy(A,B,25) +#define _IQ24mpy(A,B) __IQmpy(A,B,24) +#define _IQ23mpy(A,B) __IQmpy(A,B,23) +#define _IQ22mpy(A,B) __IQmpy(A,B,22) +#define _IQ21mpy(A,B) __IQmpy(A,B,21) +#define _IQ20mpy(A,B) __IQmpy(A,B,20) +#define _IQ19mpy(A,B) __IQmpy(A,B,19) +#define _IQ18mpy(A,B) __IQmpy(A,B,18) +#define _IQ17mpy(A,B) __IQmpy(A,B,17) +#define _IQ16mpy(A,B) __IQmpy(A,B,16) +#define _IQ15mpy(A,B) __IQmpy(A,B,15) +#define _IQ14mpy(A,B) __IQmpy(A,B,14) +#define _IQ13mpy(A,B) __IQmpy(A,B,13) +#define _IQ12mpy(A,B) __IQmpy(A,B,12) +#define _IQ11mpy(A,B) __IQmpy(A,B,11) +#define _IQ10mpy(A,B) __IQmpy(A,B,10) +#define _IQ9mpy(A,B) __IQmpy(A,B,9) +#define _IQ8mpy(A,B) __IQmpy(A,B,8) +#define _IQ7mpy(A,B) __IQmpy(A,B,7) +#define _IQ6mpy(A,B) __IQmpy(A,B,6) +#define _IQ5mpy(A,B) __IQmpy(A,B,5) +#define _IQ4mpy(A,B) __IQmpy(A,B,4) +#define _IQ3mpy(A,B) __IQmpy(A,B,3) +#define _IQ2mpy(A,B) __IQmpy(A,B,2) +#define _IQ1mpy(A,B) __IQmpy(A,B,1) +//--------------------------------------------------------------------------- +extern long _IQ30rmpy(long A, long B); +extern long _IQ29rmpy(long A, long B); +extern long _IQ28rmpy(long A, long B); +extern long _IQ27rmpy(long A, long B); +extern long _IQ26rmpy(long A, long B); +extern long _IQ25rmpy(long A, long B); +extern long _IQ24rmpy(long A, long B); +extern long _IQ23rmpy(long A, long B); +extern long _IQ22rmpy(long A, long B); +extern long _IQ21rmpy(long A, long B); +extern long _IQ20rmpy(long A, long B); +extern long _IQ19rmpy(long A, long B); +extern long _IQ18rmpy(long A, long B); +extern long _IQ17rmpy(long A, long B); +extern long _IQ16rmpy(long A, long B); +extern long _IQ15rmpy(long A, long B); +extern long _IQ14rmpy(long A, long B); +extern long _IQ13rmpy(long A, long B); +extern long _IQ12rmpy(long A, long B); +extern long _IQ11rmpy(long A, long B); +extern long _IQ10rmpy(long A, long B); +extern long _IQ9rmpy(long A, long B); +extern long _IQ8rmpy(long A, long B); +extern long _IQ7rmpy(long A, long B); +extern long _IQ6rmpy(long A, long B); +extern long _IQ5rmpy(long A, long B); +extern long _IQ4rmpy(long A, long B); +extern long _IQ3rmpy(long A, long B); +extern long _IQ2rmpy(long A, long B); +extern long _IQ1rmpy(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQrmpy(A,B) _IQ30rmpy(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQrmpy(A,B) _IQ29rmpy(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQrmpy(A,B) _IQ28rmpy(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQrmpy(A,B) _IQ27rmpy(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQrmpy(A,B) _IQ26rmpy(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQrmpy(A,B) _IQ25rmpy(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQrmpy(A,B) _IQ24rmpy(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQrmpy(A,B) _IQ23rmpy(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQrmpy(A,B) _IQ22rmpy(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQrmpy(A,B) _IQ21rmpy(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQrmpy(A,B) _IQ20rmpy(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQrmpy(A,B) _IQ19rmpy(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQrmpy(A,B) _IQ18rmpy(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQrmpy(A,B) _IQ17rmpy(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQrmpy(A,B) _IQ16rmpy(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQrmpy(A,B) _IQ15rmpy(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQrmpy(A,B) _IQ14rmpy(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQrmpy(A,B) _IQ13rmpy(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQrmpy(A,B) _IQ12rmpy(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQrmpy(A,B) _IQ11rmpy(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQrmpy(A,B) _IQ10rmpy(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQrmpy(A,B) _IQ9rmpy(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQrmpy(A,B) _IQ8rmpy(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQrmpy(A,B) _IQ7rmpy(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQrmpy(A,B) _IQ6rmpy(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQrmpy(A,B) _IQ5rmpy(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQrmpy(A,B) _IQ4rmpy(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQrmpy(A,B) _IQ3rmpy(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQrmpy(A,B) _IQ2rmpy(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQrmpy(A,B) _IQ1rmpy(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30rsmpy(long A, long B); +extern long _IQ29rsmpy(long A, long B); +extern long _IQ28rsmpy(long A, long B); +extern long _IQ27rsmpy(long A, long B); +extern long _IQ26rsmpy(long A, long B); +extern long _IQ25rsmpy(long A, long B); +extern long _IQ24rsmpy(long A, long B); +extern long _IQ23rsmpy(long A, long B); +extern long _IQ22rsmpy(long A, long B); +extern long _IQ21rsmpy(long A, long B); +extern long _IQ20rsmpy(long A, long B); +extern long _IQ19rsmpy(long A, long B); +extern long _IQ18rsmpy(long A, long B); +extern long _IQ17rsmpy(long A, long B); +extern long _IQ16rsmpy(long A, long B); +extern long _IQ15rsmpy(long A, long B); +extern long _IQ14rsmpy(long A, long B); +extern long _IQ13rsmpy(long A, long B); +extern long _IQ12rsmpy(long A, long B); +extern long _IQ11rsmpy(long A, long B); +extern long _IQ10rsmpy(long A, long B); +extern long _IQ9rsmpy(long A, long B); +extern long _IQ8rsmpy(long A, long B); +extern long _IQ7rsmpy(long A, long B); +extern long _IQ6rsmpy(long A, long B); +extern long _IQ5rsmpy(long A, long B); +extern long _IQ4rsmpy(long A, long B); +extern long _IQ3rsmpy(long A, long B); +extern long _IQ2rsmpy(long A, long B); +extern long _IQ1rsmpy(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQrsmpy(A,B) _IQ30rsmpy(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQrsmpy(A,B) _IQ29rsmpy(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQrsmpy(A,B) _IQ28rsmpy(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQrsmpy(A,B) _IQ27rsmpy(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQrsmpy(A,B) _IQ26rsmpy(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQrsmpy(A,B) _IQ25rsmpy(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQrsmpy(A,B) _IQ24rsmpy(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQrsmpy(A,B) _IQ23rsmpy(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQrsmpy(A,B) _IQ22rsmpy(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQrsmpy(A,B) _IQ21rsmpy(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQrsmpy(A,B) _IQ20rsmpy(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQrsmpy(A,B) _IQ19rsmpy(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQrsmpy(A,B) _IQ18rsmpy(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQrsmpy(A,B) _IQ17rsmpy(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQrsmpy(A,B) _IQ16rsmpy(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQrsmpy(A,B) _IQ15rsmpy(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQrsmpy(A,B) _IQ14rsmpy(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQrsmpy(A,B) _IQ13rsmpy(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQrsmpy(A,B) _IQ12rsmpy(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQrsmpy(A,B) _IQ11rsmpy(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQrsmpy(A,B) _IQ10rsmpy(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQrsmpy(A,B) _IQ9rsmpy(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQrsmpy(A,B) _IQ8rsmpy(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQrsmpy(A,B) _IQ7rsmpy(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQrsmpy(A,B) _IQ6rsmpy(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQrsmpy(A,B) _IQ5rsmpy(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQrsmpy(A,B) _IQ4rsmpy(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQrsmpy(A,B) _IQ3rsmpy(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQrsmpy(A,B) _IQ2rsmpy(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQrsmpy(A,B) _IQ1rsmpy(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30div(long A, long B); +extern long _IQ29div(long A, long B); +extern long _IQ28div(long A, long B); +extern long _IQ27div(long A, long B); +extern long _IQ26div(long A, long B); +extern long _IQ25div(long A, long B); +extern long _IQ24div(long A, long B); +extern long _IQ23div(long A, long B); +extern long _IQ22div(long A, long B); +extern long _IQ21div(long A, long B); +extern long _IQ20div(long A, long B); +extern long _IQ19div(long A, long B); +extern long _IQ18div(long A, long B); +extern long _IQ17div(long A, long B); +extern long _IQ16div(long A, long B); +extern long _IQ15div(long A, long B); +extern long _IQ14div(long A, long B); +extern long _IQ13div(long A, long B); +extern long _IQ12div(long A, long B); +extern long _IQ11div(long A, long B); +extern long _IQ10div(long A, long B); +extern long _IQ9div(long A, long B); +extern long _IQ8div(long A, long B); +extern long _IQ7div(long A, long B); +extern long _IQ6div(long A, long B); +extern long _IQ5div(long A, long B); +extern long _IQ4div(long A, long B); +extern long _IQ3div(long A, long B); +extern long _IQ2div(long A, long B); +extern long _IQ1div(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQdiv(A,B) _IQ30div(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQdiv(A,B) _IQ29div(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQdiv(A,B) _IQ28div(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQdiv(A,B) _IQ27div(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQdiv(A,B) _IQ26div(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQdiv(A,B) _IQ25div(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQdiv(A,B) _IQ24div(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQdiv(A,B) _IQ23div(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQdiv(A,B) _IQ22div(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQdiv(A,B) _IQ21div(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQdiv(A,B) _IQ20div(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQdiv(A,B) _IQ19div(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQdiv(A,B) _IQ18div(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQdiv(A,B) _IQ17div(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQdiv(A,B) _IQ16div(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQdiv(A,B) _IQ15div(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQdiv(A,B) _IQ14div(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQdiv(A,B) _IQ13div(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQdiv(A,B) _IQ12div(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQdiv(A,B) _IQ11div(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQdiv(A,B) _IQ10div(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQdiv(A,B) _IQ9div(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQdiv(A,B) _IQ8div(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQdiv(A,B) _IQ7div(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQdiv(A,B) _IQ6div(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQdiv(A,B) _IQ5div(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQdiv(A,B) _IQ4div(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQdiv(A,B) _IQ3div(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQdiv(A,B) _IQ2div(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQdiv(A,B) _IQ1div(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30sin(long A); +extern long _IQ29sin(long A); +extern long _IQ28sin(long A); +extern long _IQ27sin(long A); +extern long _IQ26sin(long A); +extern long _IQ25sin(long A); +extern long _IQ24sin(long A); +extern long _IQ23sin(long A); +extern long _IQ22sin(long A); +extern long _IQ21sin(long A); +extern long _IQ20sin(long A); +extern long _IQ19sin(long A); +extern long _IQ18sin(long A); +extern long _IQ17sin(long A); +extern long _IQ16sin(long A); +extern long _IQ15sin(long A); +extern long _IQ14sin(long A); +extern long _IQ13sin(long A); +extern long _IQ12sin(long A); +extern long _IQ11sin(long A); +extern long _IQ10sin(long A); +extern long _IQ9sin(long A); +extern long _IQ8sin(long A); +extern long _IQ7sin(long A); +extern long _IQ6sin(long A); +extern long _IQ5sin(long A); +extern long _IQ4sin(long A); +extern long _IQ3sin(long A); +extern long _IQ2sin(long A); +extern long _IQ1sin(long A); + +#if GLOBAL_Q == 30 +#define _IQsin(A) _IQ30sin(A) +#endif +#if GLOBAL_Q == 29 +#define _IQsin(A) _IQ29sin(A) +#endif +#if GLOBAL_Q == 28 +#define _IQsin(A) _IQ28sin(A) +#endif +#if GLOBAL_Q == 27 +#define _IQsin(A) _IQ27sin(A) +#endif +#if GLOBAL_Q == 26 +#define _IQsin(A) _IQ26sin(A) +#endif +#if GLOBAL_Q == 25 +#define _IQsin(A) _IQ25sin(A) +#endif +#if GLOBAL_Q == 24 +#define _IQsin(A) _IQ24sin(A) +#endif +#if GLOBAL_Q == 23 +#define _IQsin(A) _IQ23sin(A) +#endif +#if GLOBAL_Q == 22 +#define _IQsin(A) _IQ22sin(A) +#endif +#if GLOBAL_Q == 21 +#define _IQsin(A) _IQ21sin(A) +#endif +#if GLOBAL_Q == 20 +#define _IQsin(A) _IQ20sin(A) +#endif +#if GLOBAL_Q == 19 +#define _IQsin(A) _IQ19sin(A) +#endif +#if GLOBAL_Q == 18 +#define _IQsin(A) _IQ18sin(A) +#endif +#if GLOBAL_Q == 17 +#define _IQsin(A) _IQ17sin(A) +#endif +#if GLOBAL_Q == 16 +#define _IQsin(A) _IQ16sin(A) +#endif +#if GLOBAL_Q == 15 +#define _IQsin(A) _IQ15sin(A) +#endif +#if GLOBAL_Q == 14 +#define _IQsin(A) _IQ14sin(A) +#endif +#if GLOBAL_Q == 13 +#define _IQsin(A) _IQ13sin(A) +#endif +#if GLOBAL_Q == 12 +#define _IQsin(A) _IQ12sin(A) +#endif +#if GLOBAL_Q == 11 +#define _IQsin(A) _IQ11sin(A) +#endif +#if GLOBAL_Q == 10 +#define _IQsin(A) _IQ10sin(A) +#endif +#if GLOBAL_Q == 9 +#define _IQsin(A) _IQ9sin(A) +#endif +#if GLOBAL_Q == 8 +#define _IQsin(A) _IQ8sin(A) +#endif +#if GLOBAL_Q == 7 +#define _IQsin(A) _IQ7sin(A) +#endif +#if GLOBAL_Q == 6 +#define _IQsin(A) _IQ6sin(A) +#endif +#if GLOBAL_Q == 5 +#define _IQsin(A) _IQ5sin(A) +#endif +#if GLOBAL_Q == 4 +#define _IQsin(A) _IQ4sin(A) +#endif +#if GLOBAL_Q == 3 +#define _IQsin(A) _IQ3sin(A) +#endif +#if GLOBAL_Q == 2 +#define _IQsin(A) _IQ2sin(A) +#endif +#if GLOBAL_Q == 1 +#define _IQsin(A) _IQ1sin(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30sinPU(long A); +extern long _IQ29sinPU(long A); +extern long _IQ28sinPU(long A); +extern long _IQ27sinPU(long A); +extern long _IQ26sinPU(long A); +extern long _IQ25sinPU(long A); +extern long _IQ24sinPU(long A); +extern long _IQ23sinPU(long A); +extern long _IQ22sinPU(long A); +extern long _IQ21sinPU(long A); +extern long _IQ20sinPU(long A); +extern long _IQ19sinPU(long A); +extern long _IQ18sinPU(long A); +extern long _IQ17sinPU(long A); +extern long _IQ16sinPU(long A); +extern long _IQ15sinPU(long A); +extern long _IQ14sinPU(long A); +extern long _IQ13sinPU(long A); +extern long _IQ12sinPU(long A); +extern long _IQ11sinPU(long A); +extern long _IQ10sinPU(long A); +extern long _IQ9sinPU(long A); +extern long _IQ8sinPU(long A); +extern long _IQ7sinPU(long A); +extern long _IQ6sinPU(long A); +extern long _IQ5sinPU(long A); +extern long _IQ4sinPU(long A); +extern long _IQ3sinPU(long A); +extern long _IQ2sinPU(long A); +extern long _IQ1sinPU(long A); + +#if GLOBAL_Q == 30 +#define _IQsinPU(A) _IQ30sinPU(A) +#endif +#if GLOBAL_Q == 29 +#define _IQsinPU(A) _IQ29sinPU(A) +#endif +#if GLOBAL_Q == 28 +#define _IQsinPU(A) _IQ28sinPU(A) +#endif +#if GLOBAL_Q == 27 +#define _IQsinPU(A) _IQ27sinPU(A) +#endif +#if GLOBAL_Q == 26 +#define _IQsinPU(A) _IQ26sinPU(A) +#endif +#if GLOBAL_Q == 25 +#define _IQsinPU(A) _IQ25sinPU(A) +#endif +#if GLOBAL_Q == 24 +#define _IQsinPU(A) _IQ24sinPU(A) +#endif +#if GLOBAL_Q == 23 +#define _IQsinPU(A) _IQ23sinPU(A) +#endif +#if GLOBAL_Q == 22 +#define _IQsinPU(A) _IQ22sinPU(A) +#endif +#if GLOBAL_Q == 21 +#define _IQsinPU(A) _IQ21sinPU(A) +#endif +#if GLOBAL_Q == 20 +#define _IQsinPU(A) _IQ20sinPU(A) +#endif +#if GLOBAL_Q == 19 +#define _IQsinPU(A) _IQ19sinPU(A) +#endif +#if GLOBAL_Q == 18 +#define _IQsinPU(A) _IQ18sinPU(A) +#endif +#if GLOBAL_Q == 17 +#define _IQsinPU(A) _IQ17sinPU(A) +#endif +#if GLOBAL_Q == 16 +#define _IQsinPU(A) _IQ16sinPU(A) +#endif +#if GLOBAL_Q == 15 +#define _IQsinPU(A) _IQ15sinPU(A) +#endif +#if GLOBAL_Q == 14 +#define _IQsinPU(A) _IQ14sinPU(A) +#endif +#if GLOBAL_Q == 13 +#define _IQsinPU(A) _IQ13sinPU(A) +#endif +#if GLOBAL_Q == 12 +#define _IQsinPU(A) _IQ12sinPU(A) +#endif +#if GLOBAL_Q == 11 +#define _IQsinPU(A) _IQ11sinPU(A) +#endif +#if GLOBAL_Q == 10 +#define _IQsinPU(A) _IQ10sinPU(A) +#endif +#if GLOBAL_Q == 9 +#define _IQsinPU(A) _IQ9sinPU(A) +#endif +#if GLOBAL_Q == 8 +#define _IQsinPU(A) _IQ8sinPU(A) +#endif +#if GLOBAL_Q == 7 +#define _IQsinPU(A) _IQ7sinPU(A) +#endif +#if GLOBAL_Q == 6 +#define _IQsinPU(A) _IQ6sinPU(A) +#endif +#if GLOBAL_Q == 5 +#define _IQsinPU(A) _IQ5sinPU(A) +#endif +#if GLOBAL_Q == 4 +#define _IQsinPU(A) _IQ4sinPU(A) +#endif +#if GLOBAL_Q == 3 +#define _IQsinPU(A) _IQ3sinPU(A) +#endif +#if GLOBAL_Q == 2 +#define _IQsinPU(A) _IQ2sinPU(A) +#endif +#if GLOBAL_Q == 1 +#define _IQsinPU(A) _IQ1sinPU(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30asin(long A); +extern long _IQ29asin(long A); +extern long _IQ28asin(long A); +extern long _IQ27asin(long A); +extern long _IQ26asin(long A); +extern long _IQ25asin(long A); +extern long _IQ24asin(long A); +extern long _IQ23asin(long A); +extern long _IQ22asin(long A); +extern long _IQ21asin(long A); +extern long _IQ20asin(long A); +extern long _IQ19asin(long A); +extern long _IQ18asin(long A); +extern long _IQ17asin(long A); +extern long _IQ16asin(long A); +extern long _IQ15asin(long A); +extern long _IQ14asin(long A); +extern long _IQ13asin(long A); +extern long _IQ12asin(long A); +extern long _IQ11asin(long A); +extern long _IQ10asin(long A); +extern long _IQ9asin(long A); +extern long _IQ8asin(long A); +extern long _IQ7asin(long A); +extern long _IQ6asin(long A); +extern long _IQ5asin(long A); +extern long _IQ4asin(long A); +extern long _IQ3asin(long A); +extern long _IQ2asin(long A); +extern long _IQ1asin(long A); + +#if GLOBAL_Q == 30 +#define _IQasin(A) _IQ30asin(A) +#endif +#if GLOBAL_Q == 29 +#define _IQasin(A) _IQ29asin(A) +#endif +#if GLOBAL_Q == 28 +#define _IQasin(A) _IQ28asin(A) +#endif +#if GLOBAL_Q == 27 +#define _IQasin(A) _IQ27asin(A) +#endif +#if GLOBAL_Q == 26 +#define _IQasin(A) _IQ26asin(A) +#endif +#if GLOBAL_Q == 25 +#define _IQasin(A) _IQ25asin(A) +#endif +#if GLOBAL_Q == 24 +#define _IQasin(A) _IQ24asin(A) +#endif +#if GLOBAL_Q == 23 +#define _IQasin(A) _IQ23asin(A) +#endif +#if GLOBAL_Q == 22 +#define _IQasin(A) _IQ22asin(A) +#endif +#if GLOBAL_Q == 21 +#define _IQasin(A) _IQ21asin(A) +#endif +#if GLOBAL_Q == 20 +#define _IQasin(A) _IQ20asin(A) +#endif +#if GLOBAL_Q == 19 +#define _IQasin(A) _IQ19asin(A) +#endif +#if GLOBAL_Q == 18 +#define _IQasin(A) _IQ18asin(A) +#endif +#if GLOBAL_Q == 17 +#define _IQasin(A) _IQ17asin(A) +#endif +#if GLOBAL_Q == 16 +#define _IQasin(A) _IQ16asin(A) +#endif +#if GLOBAL_Q == 15 +#define _IQasin(A) _IQ15asin(A) +#endif +#if GLOBAL_Q == 14 +#define _IQasin(A) _IQ14asin(A) +#endif +#if GLOBAL_Q == 13 +#define _IQasin(A) _IQ13asin(A) +#endif +#if GLOBAL_Q == 12 +#define _IQasin(A) _IQ12asin(A) +#endif +#if GLOBAL_Q == 11 +#define _IQasin(A) _IQ11asin(A) +#endif +#if GLOBAL_Q == 10 +#define _IQasin(A) _IQ10asin(A) +#endif +#if GLOBAL_Q == 9 +#define _IQasin(A) _IQ9asin(A) +#endif +#if GLOBAL_Q == 8 +#define _IQasin(A) _IQ8asin(A) +#endif +#if GLOBAL_Q == 7 +#define _IQasin(A) _IQ7asin(A) +#endif +#if GLOBAL_Q == 6 +#define _IQasin(A) _IQ6asin(A) +#endif +#if GLOBAL_Q == 5 +#define _IQasin(A) _IQ5asin(A) +#endif +#if GLOBAL_Q == 4 +#define _IQasin(A) _IQ4asin(A) +#endif +#if GLOBAL_Q == 3 +#define _IQasin(A) _IQ3asin(A) +#endif +#if GLOBAL_Q == 2 +#define _IQasin(A) _IQ2asin(A) +#endif +#if GLOBAL_Q == 1 +#define _IQasin(A) _IQ1asin(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30cos(long A); +extern long _IQ29cos(long A); +extern long _IQ28cos(long A); +extern long _IQ27cos(long A); +extern long _IQ26cos(long A); +extern long _IQ25cos(long A); +extern long _IQ24cos(long A); +extern long _IQ23cos(long A); +extern long _IQ22cos(long A); +extern long _IQ21cos(long A); +extern long _IQ20cos(long A); +extern long _IQ19cos(long A); +extern long _IQ18cos(long A); +extern long _IQ17cos(long A); +extern long _IQ16cos(long A); +extern long _IQ15cos(long A); +extern long _IQ14cos(long A); +extern long _IQ13cos(long A); +extern long _IQ12cos(long A); +extern long _IQ11cos(long A); +extern long _IQ10cos(long A); +extern long _IQ9cos(long A); +extern long _IQ8cos(long A); +extern long _IQ7cos(long A); +extern long _IQ6cos(long A); +extern long _IQ5cos(long A); +extern long _IQ4cos(long A); +extern long _IQ3cos(long A); +extern long _IQ2cos(long A); +extern long _IQ1cos(long A); + +#if GLOBAL_Q == 30 +#define _IQcos(A) _IQ30cos(A) +#endif +#if GLOBAL_Q == 29 +#define _IQcos(A) _IQ29cos(A) +#endif +#if GLOBAL_Q == 28 +#define _IQcos(A) _IQ28cos(A) +#endif +#if GLOBAL_Q == 27 +#define _IQcos(A) _IQ27cos(A) +#endif +#if GLOBAL_Q == 26 +#define _IQcos(A) _IQ26cos(A) +#endif +#if GLOBAL_Q == 25 +#define _IQcos(A) _IQ25cos(A) +#endif +#if GLOBAL_Q == 24 +#define _IQcos(A) _IQ24cos(A) +#endif +#if GLOBAL_Q == 23 +#define _IQcos(A) _IQ23cos(A) +#endif +#if GLOBAL_Q == 22 +#define _IQcos(A) _IQ22cos(A) +#endif +#if GLOBAL_Q == 21 +#define _IQcos(A) _IQ21cos(A) +#endif +#if GLOBAL_Q == 20 +#define _IQcos(A) _IQ20cos(A) +#endif +#if GLOBAL_Q == 19 +#define _IQcos(A) _IQ19cos(A) +#endif +#if GLOBAL_Q == 18 +#define _IQcos(A) _IQ18cos(A) +#endif +#if GLOBAL_Q == 17 +#define _IQcos(A) _IQ17cos(A) +#endif +#if GLOBAL_Q == 16 +#define _IQcos(A) _IQ16cos(A) +#endif +#if GLOBAL_Q == 15 +#define _IQcos(A) _IQ15cos(A) +#endif +#if GLOBAL_Q == 14 +#define _IQcos(A) _IQ14cos(A) +#endif +#if GLOBAL_Q == 13 +#define _IQcos(A) _IQ13cos(A) +#endif +#if GLOBAL_Q == 12 +#define _IQcos(A) _IQ12cos(A) +#endif +#if GLOBAL_Q == 11 +#define _IQcos(A) _IQ11cos(A) +#endif +#if GLOBAL_Q == 10 +#define _IQcos(A) _IQ10cos(A) +#endif +#if GLOBAL_Q == 9 +#define _IQcos(A) _IQ9cos(A) +#endif +#if GLOBAL_Q == 8 +#define _IQcos(A) _IQ8cos(A) +#endif +#if GLOBAL_Q == 7 +#define _IQcos(A) _IQ7cos(A) +#endif +#if GLOBAL_Q == 6 +#define _IQcos(A) _IQ6cos(A) +#endif +#if GLOBAL_Q == 5 +#define _IQcos(A) _IQ5cos(A) +#endif +#if GLOBAL_Q == 4 +#define _IQcos(A) _IQ4cos(A) +#endif +#if GLOBAL_Q == 3 +#define _IQcos(A) _IQ3cos(A) +#endif +#if GLOBAL_Q == 2 +#define _IQcos(A) _IQ2cos(A) +#endif +#if GLOBAL_Q == 1 +#define _IQcos(A) _IQ1cos(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30cosPU(long A); +extern long _IQ29cosPU(long A); +extern long _IQ28cosPU(long A); +extern long _IQ27cosPU(long A); +extern long _IQ26cosPU(long A); +extern long _IQ25cosPU(long A); +extern long _IQ24cosPU(long A); +extern long _IQ23cosPU(long A); +extern long _IQ22cosPU(long A); +extern long _IQ21cosPU(long A); +extern long _IQ20cosPU(long A); +extern long _IQ19cosPU(long A); +extern long _IQ18cosPU(long A); +extern long _IQ17cosPU(long A); +extern long _IQ16cosPU(long A); +extern long _IQ15cosPU(long A); +extern long _IQ14cosPU(long A); +extern long _IQ13cosPU(long A); +extern long _IQ12cosPU(long A); +extern long _IQ11cosPU(long A); +extern long _IQ10cosPU(long A); +extern long _IQ9cosPU(long A); +extern long _IQ8cosPU(long A); +extern long _IQ7cosPU(long A); +extern long _IQ6cosPU(long A); +extern long _IQ5cosPU(long A); +extern long _IQ4cosPU(long A); +extern long _IQ3cosPU(long A); +extern long _IQ2cosPU(long A); +extern long _IQ1cosPU(long A); + +#if GLOBAL_Q == 30 +#define _IQcosPU(A) _IQ30cosPU(A) +#endif +#if GLOBAL_Q == 29 +#define _IQcosPU(A) _IQ29cosPU(A) +#endif +#if GLOBAL_Q == 28 +#define _IQcosPU(A) _IQ28cosPU(A) +#endif +#if GLOBAL_Q == 27 +#define _IQcosPU(A) _IQ27cosPU(A) +#endif +#if GLOBAL_Q == 26 +#define _IQcosPU(A) _IQ26cosPU(A) +#endif +#if GLOBAL_Q == 25 +#define _IQcosPU(A) _IQ25cosPU(A) +#endif +#if GLOBAL_Q == 24 +#define _IQcosPU(A) _IQ24cosPU(A) +#endif +#if GLOBAL_Q == 23 +#define _IQcosPU(A) _IQ23cosPU(A) +#endif +#if GLOBAL_Q == 22 +#define _IQcosPU(A) _IQ22cosPU(A) +#endif +#if GLOBAL_Q == 21 +#define _IQcosPU(A) _IQ21cosPU(A) +#endif +#if GLOBAL_Q == 20 +#define _IQcosPU(A) _IQ20cosPU(A) +#endif +#if GLOBAL_Q == 19 +#define _IQcosPU(A) _IQ19cosPU(A) +#endif +#if GLOBAL_Q == 18 +#define _IQcosPU(A) _IQ18cosPU(A) +#endif +#if GLOBAL_Q == 17 +#define _IQcosPU(A) _IQ17cosPU(A) +#endif +#if GLOBAL_Q == 16 +#define _IQcosPU(A) _IQ16cosPU(A) +#endif +#if GLOBAL_Q == 15 +#define _IQcosPU(A) _IQ15cosPU(A) +#endif +#if GLOBAL_Q == 14 +#define _IQcosPU(A) _IQ14cosPU(A) +#endif +#if GLOBAL_Q == 13 +#define _IQcosPU(A) _IQ13cosPU(A) +#endif +#if GLOBAL_Q == 12 +#define _IQcosPU(A) _IQ12cosPU(A) +#endif +#if GLOBAL_Q == 11 +#define _IQcosPU(A) _IQ11cosPU(A) +#endif +#if GLOBAL_Q == 10 +#define _IQcosPU(A) _IQ10cosPU(A) +#endif +#if GLOBAL_Q == 9 +#define _IQcosPU(A) _IQ9cosPU(A) +#endif +#if GLOBAL_Q == 8 +#define _IQcosPU(A) _IQ8cosPU(A) +#endif +#if GLOBAL_Q == 7 +#define _IQcosPU(A) _IQ7cosPU(A) +#endif +#if GLOBAL_Q == 6 +#define _IQcosPU(A) _IQ6cosPU(A) +#endif +#if GLOBAL_Q == 5 +#define _IQcosPU(A) _IQ5cosPU(A) +#endif +#if GLOBAL_Q == 4 +#define _IQcosPU(A) _IQ4cosPU(A) +#endif +#if GLOBAL_Q == 3 +#define _IQcosPU(A) _IQ3cosPU(A) +#endif +#if GLOBAL_Q == 2 +#define _IQcosPU(A) _IQ2cosPU(A) +#endif +#if GLOBAL_Q == 1 +#define _IQcosPU(A) _IQ1cosPU(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30acos(long A); +extern long _IQ29acos(long A); +extern long _IQ28acos(long A); +extern long _IQ27acos(long A); +extern long _IQ26acos(long A); +extern long _IQ25acos(long A); +extern long _IQ24acos(long A); +extern long _IQ23acos(long A); +extern long _IQ22acos(long A); +extern long _IQ21acos(long A); +extern long _IQ20acos(long A); +extern long _IQ19acos(long A); +extern long _IQ18acos(long A); +extern long _IQ17acos(long A); +extern long _IQ16acos(long A); +extern long _IQ15acos(long A); +extern long _IQ14acos(long A); +extern long _IQ13acos(long A); +extern long _IQ12acos(long A); +extern long _IQ11acos(long A); +extern long _IQ10acos(long A); +extern long _IQ9acos(long A); +extern long _IQ8acos(long A); +extern long _IQ7acos(long A); +extern long _IQ6acos(long A); +extern long _IQ5acos(long A); +extern long _IQ4acos(long A); +extern long _IQ3acos(long A); +extern long _IQ2acos(long A); +extern long _IQ1acos(long A); + +#if GLOBAL_Q == 30 +#define _IQacos(A) _IQ30acos(A) +#endif +#if GLOBAL_Q == 29 +#define _IQacos(A) _IQ29acos(A) +#endif +#if GLOBAL_Q == 28 +#define _IQacos(A) _IQ28acos(A) +#endif +#if GLOBAL_Q == 27 +#define _IQacos(A) _IQ27acos(A) +#endif +#if GLOBAL_Q == 26 +#define _IQacos(A) _IQ26acos(A) +#endif +#if GLOBAL_Q == 25 +#define _IQacos(A) _IQ25acos(A) +#endif +#if GLOBAL_Q == 24 +#define _IQacos(A) _IQ24acos(A) +#endif +#if GLOBAL_Q == 23 +#define _IQacos(A) _IQ23acos(A) +#endif +#if GLOBAL_Q == 22 +#define _IQacos(A) _IQ22acos(A) +#endif +#if GLOBAL_Q == 21 +#define _IQacos(A) _IQ21acos(A) +#endif +#if GLOBAL_Q == 20 +#define _IQacos(A) _IQ20acos(A) +#endif +#if GLOBAL_Q == 19 +#define _IQacos(A) _IQ19acos(A) +#endif +#if GLOBAL_Q == 18 +#define _IQacos(A) _IQ18acos(A) +#endif +#if GLOBAL_Q == 17 +#define _IQacos(A) _IQ17acos(A) +#endif +#if GLOBAL_Q == 16 +#define _IQacos(A) _IQ16acos(A) +#endif +#if GLOBAL_Q == 15 +#define _IQacos(A) _IQ15acos(A) +#endif +#if GLOBAL_Q == 14 +#define _IQacos(A) _IQ14acos(A) +#endif +#if GLOBAL_Q == 13 +#define _IQacos(A) _IQ13acos(A) +#endif +#if GLOBAL_Q == 12 +#define _IQacos(A) _IQ12acos(A) +#endif +#if GLOBAL_Q == 11 +#define _IQacos(A) _IQ11acos(A) +#endif +#if GLOBAL_Q == 10 +#define _IQacos(A) _IQ10acos(A) +#endif +#if GLOBAL_Q == 9 +#define _IQacos(A) _IQ9acos(A) +#endif +#if GLOBAL_Q == 8 +#define _IQacos(A) _IQ8acos(A) +#endif +#if GLOBAL_Q == 7 +#define _IQacos(A) _IQ7acos(A) +#endif +#if GLOBAL_Q == 6 +#define _IQacos(A) _IQ6acos(A) +#endif +#if GLOBAL_Q == 5 +#define _IQacos(A) _IQ5acos(A) +#endif +#if GLOBAL_Q == 4 +#define _IQacos(A) _IQ4acos(A) +#endif +#if GLOBAL_Q == 3 +#define _IQacos(A) _IQ3acos(A) +#endif +#if GLOBAL_Q == 2 +#define _IQacos(A) _IQ2acos(A) +#endif +#if GLOBAL_Q == 1 +#define _IQacos(A) _IQ1acos(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30atan2(long A, long B); +extern long _IQ29atan2(long A, long B); +extern long _IQ28atan2(long A, long B); +extern long _IQ27atan2(long A, long B); +extern long _IQ26atan2(long A, long B); +extern long _IQ25atan2(long A, long B); +extern long _IQ24atan2(long A, long B); +extern long _IQ23atan2(long A, long B); +extern long _IQ22atan2(long A, long B); +extern long _IQ21atan2(long A, long B); +extern long _IQ20atan2(long A, long B); +extern long _IQ19atan2(long A, long B); +extern long _IQ18atan2(long A, long B); +extern long _IQ17atan2(long A, long B); +extern long _IQ16atan2(long A, long B); +extern long _IQ15atan2(long A, long B); +extern long _IQ14atan2(long A, long B); +extern long _IQ13atan2(long A, long B); +extern long _IQ12atan2(long A, long B); +extern long _IQ11atan2(long A, long B); +extern long _IQ10atan2(long A, long B); +extern long _IQ9atan2(long A, long B); +extern long _IQ8atan2(long A, long B); +extern long _IQ7atan2(long A, long B); +extern long _IQ6atan2(long A, long B); +extern long _IQ5atan2(long A, long B); +extern long _IQ4atan2(long A, long B); +extern long _IQ3atan2(long A, long B); +extern long _IQ2atan2(long A, long B); +extern long _IQ1atan2(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQatan2(A,B) _IQ30atan2(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQatan2(A,B) _IQ29atan2(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQatan2(A,B) _IQ28atan2(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQatan2(A,B) _IQ27atan2(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQatan2(A,B) _IQ26atan2(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQatan2(A,B) _IQ25atan2(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQatan2(A,B) _IQ24atan2(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQatan2(A,B) _IQ23atan2(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQatan2(A,B) _IQ22atan2(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQatan2(A,B) _IQ21atan2(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQatan2(A,B) _IQ20atan2(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQatan2(A,B) _IQ19atan2(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQatan2(A,B) _IQ18atan2(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQatan2(A,B) _IQ17atan2(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQatan2(A,B) _IQ16atan2(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQatan2(A,B) _IQ15atan2(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQatan2(A,B) _IQ14atan2(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQatan2(A,B) _IQ13atan2(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQatan2(A,B) _IQ12atan2(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQatan2(A,B) _IQ11atan2(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQatan2(A,B) _IQ10atan2(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQatan2(A,B) _IQ9atan2(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQatan2(A,B) _IQ8atan2(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQatan2(A,B) _IQ7atan2(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQatan2(A,B) _IQ6atan2(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQatan2(A,B) _IQ5atan2(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQatan2(A,B) _IQ4atan2(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQatan2(A,B) _IQ3atan2(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQatan2(A,B) _IQ2atan2(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQatan2(A,B) _IQ1atan2(A,B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30atan2PU(long A, long B); +extern long _IQ29atan2PU(long A, long B); +extern long _IQ28atan2PU(long A, long B); +extern long _IQ27atan2PU(long A, long B); +extern long _IQ26atan2PU(long A, long B); +extern long _IQ25atan2PU(long A, long B); +extern long _IQ24atan2PU(long A, long B); +extern long _IQ23atan2PU(long A, long B); +extern long _IQ22atan2PU(long A, long B); +extern long _IQ21atan2PU(long A, long B); +extern long _IQ20atan2PU(long A, long B); +extern long _IQ19atan2PU(long A, long B); +extern long _IQ18atan2PU(long A, long B); +extern long _IQ17atan2PU(long A, long B); +extern long _IQ16atan2PU(long A, long B); +extern long _IQ15atan2PU(long A, long B); +extern long _IQ14atan2PU(long A, long B); +extern long _IQ13atan2PU(long A, long B); +extern long _IQ12atan2PU(long A, long B); +extern long _IQ11atan2PU(long A, long B); +extern long _IQ10atan2PU(long A, long B); +extern long _IQ9atan2PU(long A, long B); +extern long _IQ8atan2PU(long A, long B); +extern long _IQ7atan2PU(long A, long B); +extern long _IQ6atan2PU(long A, long B); +extern long _IQ5atan2PU(long A, long B); +extern long _IQ4atan2PU(long A, long B); +extern long _IQ3atan2PU(long A, long B); +extern long _IQ2atan2PU(long A, long B); +extern long _IQ1atan2PU(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQatan2PU(A,B) _IQ30atan2PU(A,B) +#endif +#if GLOBAL_Q == 29 +#define _IQatan2PU(A,B) _IQ29atan2PU(A,B) +#endif +#if GLOBAL_Q == 28 +#define _IQatan2PU(A,B) _IQ28atan2PU(A,B) +#endif +#if GLOBAL_Q == 27 +#define _IQatan2PU(A,B) _IQ27atan2PU(A,B) +#endif +#if GLOBAL_Q == 26 +#define _IQatan2PU(A,B) _IQ26atan2PU(A,B) +#endif +#if GLOBAL_Q == 25 +#define _IQatan2PU(A,B) _IQ25atan2PU(A,B) +#endif +#if GLOBAL_Q == 24 +#define _IQatan2PU(A,B) _IQ24atan2PU(A,B) +#endif +#if GLOBAL_Q == 23 +#define _IQatan2PU(A,B) _IQ23atan2PU(A,B) +#endif +#if GLOBAL_Q == 22 +#define _IQatan2PU(A,B) _IQ22atan2PU(A,B) +#endif +#if GLOBAL_Q == 21 +#define _IQatan2PU(A,B) _IQ21atan2PU(A,B) +#endif +#if GLOBAL_Q == 20 +#define _IQatan2PU(A,B) _IQ20atan2PU(A,B) +#endif +#if GLOBAL_Q == 19 +#define _IQatan2PU(A,B) _IQ19atan2PU(A,B) +#endif +#if GLOBAL_Q == 18 +#define _IQatan2PU(A,B) _IQ18atan2PU(A,B) +#endif +#if GLOBAL_Q == 17 +#define _IQatan2PU(A,B) _IQ17atan2PU(A,B) +#endif +#if GLOBAL_Q == 16 +#define _IQatan2PU(A,B) _IQ16atan2PU(A,B) +#endif +#if GLOBAL_Q == 15 +#define _IQatan2PU(A,B) _IQ15atan2PU(A,B) +#endif +#if GLOBAL_Q == 14 +#define _IQatan2PU(A,B) _IQ14atan2PU(A,B) +#endif +#if GLOBAL_Q == 13 +#define _IQatan2PU(A,B) _IQ13atan2PU(A,B) +#endif +#if GLOBAL_Q == 12 +#define _IQatan2PU(A,B) _IQ12atan2PU(A,B) +#endif +#if GLOBAL_Q == 11 +#define _IQatan2PU(A,B) _IQ11atan2PU(A,B) +#endif +#if GLOBAL_Q == 10 +#define _IQatan2PU(A,B) _IQ10atan2PU(A,B) +#endif +#if GLOBAL_Q == 9 +#define _IQatan2PU(A,B) _IQ9atan2PU(A,B) +#endif +#if GLOBAL_Q == 8 +#define _IQatan2PU(A,B) _IQ8atan2PU(A,B) +#endif +#if GLOBAL_Q == 7 +#define _IQatan2PU(A,B) _IQ7atan2PU(A,B) +#endif +#if GLOBAL_Q == 6 +#define _IQatan2PU(A,B) _IQ6atan2PU(A,B) +#endif +#if GLOBAL_Q == 5 +#define _IQatan2PU(A,B) _IQ5atan2PU(A,B) +#endif +#if GLOBAL_Q == 4 +#define _IQatan2PU(A,B) _IQ4atan2PU(A,B) +#endif +#if GLOBAL_Q == 3 +#define _IQatan2PU(A,B) _IQ3atan2PU(A,B) +#endif +#if GLOBAL_Q == 2 +#define _IQatan2PU(A,B) _IQ2atan2PU(A,B) +#endif +#if GLOBAL_Q == 1 +#define _IQatan2PU(A,B) _IQ1atan2PU(A,B) +#endif +//--------------------------------------------------------------------------- +#define _IQ30atan(A) _IQ30atan2(A,_IQ30(1.0)) +#define _IQ29atan(A) _IQ29atan2(A,_IQ29(1.0)) +#define _IQ28atan(A) _IQ28atan2(A,_IQ28(1.0)) +#define _IQ27atan(A) _IQ27atan2(A,_IQ27(1.0)) +#define _IQ26atan(A) _IQ26atan2(A,_IQ26(1.0)) +#define _IQ25atan(A) _IQ25atan2(A,_IQ25(1.0)) +#define _IQ24atan(A) _IQ24atan2(A,_IQ24(1.0)) +#define _IQ23atan(A) _IQ23atan2(A,_IQ23(1.0)) +#define _IQ22atan(A) _IQ22atan2(A,_IQ22(1.0)) +#define _IQ21atan(A) _IQ21atan2(A,_IQ21(1.0)) +#define _IQ20atan(A) _IQ20atan2(A,_IQ20(1.0)) +#define _IQ19atan(A) _IQ19atan2(A,_IQ19(1.0)) +#define _IQ18atan(A) _IQ18atan2(A,_IQ18(1.0)) +#define _IQ17atan(A) _IQ17atan2(A,_IQ17(1.0)) +#define _IQ16atan(A) _IQ16atan2(A,_IQ16(1.0)) +#define _IQ15atan(A) _IQ15atan2(A,_IQ15(1.0)) +#define _IQ14atan(A) _IQ14atan2(A,_IQ14(1.0)) +#define _IQ13atan(A) _IQ13atan2(A,_IQ13(1.0)) +#define _IQ12atan(A) _IQ12atan2(A,_IQ12(1.0)) +#define _IQ11atan(A) _IQ11atan2(A,_IQ11(1.0)) +#define _IQ10atan(A) _IQ10atan2(A,_IQ10(1.0)) +#define _IQ9atan(A) _IQ9atan2(A,_IQ9(1.0)) +#define _IQ8atan(A) _IQ8atan2(A,_IQ8(1.0)) +#define _IQ7atan(A) _IQ7atan2(A,_IQ7(1.0)) +#define _IQ6atan(A) _IQ6atan2(A,_IQ6(1.0)) +#define _IQ5atan(A) _IQ5atan2(A,_IQ5(1.0)) +#define _IQ4atan(A) _IQ4atan2(A,_IQ4(1.0)) +#define _IQ3atan(A) _IQ3atan2(A,_IQ3(1.0)) +#define _IQ2atan(A) _IQ2atan2(A,_IQ2(1.0)) +#define _IQ1atan(A) _IQ1atan2(A,_IQ1(1.0)) +#if GLOBAL_Q == 30 +#define _IQatan(A) _IQ30atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 29 +#define _IQatan(A) _IQ29atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 28 +#define _IQatan(A) _IQ28atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 27 +#define _IQatan(A) _IQ27atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 26 +#define _IQatan(A) _IQ26atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 25 +#define _IQatan(A) _IQ25atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 24 +#define _IQatan(A) _IQ24atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 23 +#define _IQatan(A) _IQ23atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 22 +#define _IQatan(A) _IQ22atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 21 +#define _IQatan(A) _IQ21atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 20 +#define _IQatan(A) _IQ20atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 19 +#define _IQatan(A) _IQ19atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 18 +#define _IQatan(A) _IQ18atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 17 +#define _IQatan(A) _IQ17atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 16 +#define _IQatan(A) _IQ16atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 15 +#define _IQatan(A) _IQ15atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 14 +#define _IQatan(A) _IQ14atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 13 +#define _IQatan(A) _IQ13atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 12 +#define _IQatan(A) _IQ12atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 11 +#define _IQatan(A) _IQ11atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 10 +#define _IQatan(A) _IQ10atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 9 +#define _IQatan(A) _IQ9atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 8 +#define _IQatan(A) _IQ8atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 7 +#define _IQatan(A) _IQ7atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 6 +#define _IQatan(A) _IQ6atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 5 +#define _IQatan(A) _IQ5atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 4 +#define _IQatan(A) _IQ4atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 3 +#define _IQatan(A) _IQ3atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 2 +#define _IQatan(A) _IQ2atan2(A,_IQ(1.0)) +#endif +#if GLOBAL_Q == 1 +#define _IQatan(A) _IQ1atan2(A,_IQ(1.0)) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30sqrt(long A); +extern long _IQ29sqrt(long A); +extern long _IQ28sqrt(long A); +extern long _IQ27sqrt(long A); +extern long _IQ26sqrt(long A); +extern long _IQ25sqrt(long A); +extern long _IQ24sqrt(long A); +extern long _IQ23sqrt(long A); +extern long _IQ22sqrt(long A); +extern long _IQ21sqrt(long A); +extern long _IQ20sqrt(long A); +extern long _IQ19sqrt(long A); +extern long _IQ18sqrt(long A); +extern long _IQ17sqrt(long A); +extern long _IQ16sqrt(long A); +extern long _IQ15sqrt(long A); +extern long _IQ14sqrt(long A); +extern long _IQ13sqrt(long A); +extern long _IQ12sqrt(long A); +extern long _IQ11sqrt(long A); +extern long _IQ10sqrt(long A); +extern long _IQ9sqrt(long A); +extern long _IQ8sqrt(long A); +extern long _IQ7sqrt(long A); +extern long _IQ6sqrt(long A); +extern long _IQ5sqrt(long A); +extern long _IQ4sqrt(long A); +extern long _IQ3sqrt(long A); +extern long _IQ2sqrt(long A); +extern long _IQ1sqrt(long A); + +#if GLOBAL_Q == 30 +#define _IQsqrt(A) _IQ30sqrt(A) +#endif +#if GLOBAL_Q == 29 +#define _IQsqrt(A) _IQ29sqrt(A) +#endif +#if GLOBAL_Q == 28 +#define _IQsqrt(A) _IQ28sqrt(A) +#endif +#if GLOBAL_Q == 27 +#define _IQsqrt(A) _IQ27sqrt(A) +#endif +#if GLOBAL_Q == 26 +#define _IQsqrt(A) _IQ26sqrt(A) +#endif +#if GLOBAL_Q == 25 +#define _IQsqrt(A) _IQ25sqrt(A) +#endif +#if GLOBAL_Q == 24 +#define _IQsqrt(A) _IQ24sqrt(A) +#endif +#if GLOBAL_Q == 23 +#define _IQsqrt(A) _IQ23sqrt(A) +#endif +#if GLOBAL_Q == 22 +#define _IQsqrt(A) _IQ22sqrt(A) +#endif +#if GLOBAL_Q == 21 +#define _IQsqrt(A) _IQ21sqrt(A) +#endif +#if GLOBAL_Q == 20 +#define _IQsqrt(A) _IQ20sqrt(A) +#endif +#if GLOBAL_Q == 19 +#define _IQsqrt(A) _IQ19sqrt(A) +#endif +#if GLOBAL_Q == 18 +#define _IQsqrt(A) _IQ18sqrt(A) +#endif +#if GLOBAL_Q == 17 +#define _IQsqrt(A) _IQ17sqrt(A) +#endif +#if GLOBAL_Q == 16 +#define _IQsqrt(A) _IQ16sqrt(A) +#endif +#if GLOBAL_Q == 15 +#define _IQsqrt(A) _IQ15sqrt(A) +#endif +#if GLOBAL_Q == 14 +#define _IQsqrt(A) _IQ14sqrt(A) +#endif +#if GLOBAL_Q == 13 +#define _IQsqrt(A) _IQ13sqrt(A) +#endif +#if GLOBAL_Q == 12 +#define _IQsqrt(A) _IQ12sqrt(A) +#endif +#if GLOBAL_Q == 11 +#define _IQsqrt(A) _IQ11sqrt(A) +#endif +#if GLOBAL_Q == 10 +#define _IQsqrt(A) _IQ10sqrt(A) +#endif +#if GLOBAL_Q == 9 +#define _IQsqrt(A) _IQ9sqrt(A) +#endif +#if GLOBAL_Q == 8 +#define _IQsqrt(A) _IQ8sqrt(A) +#endif +#if GLOBAL_Q == 7 +#define _IQsqrt(A) _IQ7sqrt(A) +#endif +#if GLOBAL_Q == 6 +#define _IQsqrt(A) _IQ6sqrt(A) +#endif +#if GLOBAL_Q == 5 +#define _IQsqrt(A) _IQ5sqrt(A) +#endif +#if GLOBAL_Q == 4 +#define _IQsqrt(A) _IQ4sqrt(A) +#endif +#if GLOBAL_Q == 3 +#define _IQsqrt(A) _IQ3sqrt(A) +#endif +#if GLOBAL_Q == 2 +#define _IQsqrt(A) _IQ2sqrt(A) +#endif +#if GLOBAL_Q == 1 +#define _IQsqrt(A) _IQ1sqrt(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30isqrt(long A); +extern long _IQ29isqrt(long A); +extern long _IQ28isqrt(long A); +extern long _IQ27isqrt(long A); +extern long _IQ26isqrt(long A); +extern long _IQ25isqrt(long A); +extern long _IQ24isqrt(long A); +extern long _IQ23isqrt(long A); +extern long _IQ22isqrt(long A); +extern long _IQ21isqrt(long A); +extern long _IQ20isqrt(long A); +extern long _IQ19isqrt(long A); +extern long _IQ18isqrt(long A); +extern long _IQ17isqrt(long A); +extern long _IQ16isqrt(long A); +extern long _IQ15isqrt(long A); +extern long _IQ14isqrt(long A); +extern long _IQ13isqrt(long A); +extern long _IQ12isqrt(long A); +extern long _IQ11isqrt(long A); +extern long _IQ10isqrt(long A); +extern long _IQ9isqrt(long A); +extern long _IQ8isqrt(long A); +extern long _IQ7isqrt(long A); +extern long _IQ6isqrt(long A); +extern long _IQ5isqrt(long A); +extern long _IQ4isqrt(long A); +extern long _IQ3isqrt(long A); +extern long _IQ2isqrt(long A); +extern long _IQ1isqrt(long A); + +#if GLOBAL_Q == 30 +#define _IQisqrt(A) _IQ30isqrt(A) +#endif +#if GLOBAL_Q == 29 +#define _IQisqrt(A) _IQ29isqrt(A) +#endif +#if GLOBAL_Q == 28 +#define _IQisqrt(A) _IQ28isqrt(A) +#endif +#if GLOBAL_Q == 27 +#define _IQisqrt(A) _IQ27isqrt(A) +#endif +#if GLOBAL_Q == 26 +#define _IQisqrt(A) _IQ26isqrt(A) +#endif +#if GLOBAL_Q == 25 +#define _IQisqrt(A) _IQ25isqrt(A) +#endif +#if GLOBAL_Q == 24 +#define _IQisqrt(A) _IQ24isqrt(A) +#endif +#if GLOBAL_Q == 23 +#define _IQisqrt(A) _IQ23isqrt(A) +#endif +#if GLOBAL_Q == 22 +#define _IQisqrt(A) _IQ22isqrt(A) +#endif +#if GLOBAL_Q == 21 +#define _IQisqrt(A) _IQ21isqrt(A) +#endif +#if GLOBAL_Q == 20 +#define _IQisqrt(A) _IQ20isqrt(A) +#endif +#if GLOBAL_Q == 19 +#define _IQisqrt(A) _IQ19isqrt(A) +#endif +#if GLOBAL_Q == 18 +#define _IQisqrt(A) _IQ18isqrt(A) +#endif +#if GLOBAL_Q == 17 +#define _IQisqrt(A) _IQ17isqrt(A) +#endif +#if GLOBAL_Q == 16 +#define _IQisqrt(A) _IQ16isqrt(A) +#endif +#if GLOBAL_Q == 15 +#define _IQisqrt(A) _IQ15isqrt(A) +#endif +#if GLOBAL_Q == 14 +#define _IQisqrt(A) _IQ14isqrt(A) +#endif +#if GLOBAL_Q == 13 +#define _IQisqrt(A) _IQ13isqrt(A) +#endif +#if GLOBAL_Q == 12 +#define _IQisqrt(A) _IQ12isqrt(A) +#endif +#if GLOBAL_Q == 11 +#define _IQisqrt(A) _IQ11isqrt(A) +#endif +#if GLOBAL_Q == 10 +#define _IQisqrt(A) _IQ10isqrt(A) +#endif +#if GLOBAL_Q == 9 +#define _IQisqrt(A) _IQ9isqrt(A) +#endif +#if GLOBAL_Q == 8 +#define _IQisqrt(A) _IQ8isqrt(A) +#endif +#if GLOBAL_Q == 7 +#define _IQisqrt(A) _IQ7isqrt(A) +#endif +#if GLOBAL_Q == 6 +#define _IQisqrt(A) _IQ6isqrt(A) +#endif +#if GLOBAL_Q == 5 +#define _IQisqrt(A) _IQ5isqrt(A) +#endif +#if GLOBAL_Q == 4 +#define _IQisqrt(A) _IQ4isqrt(A) +#endif +#if GLOBAL_Q == 3 +#define _IQisqrt(A) _IQ3isqrt(A) +#endif +#if GLOBAL_Q == 2 +#define _IQisqrt(A) _IQ2isqrt(A) +#endif +#if GLOBAL_Q == 1 +#define _IQisqrt(A) _IQ1isqrt(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30exp(long A); +extern long _IQ29exp(long A); +extern long _IQ28exp(long A); +extern long _IQ27exp(long A); +extern long _IQ26exp(long A); +extern long _IQ25exp(long A); +extern long _IQ24exp(long A); +extern long _IQ23exp(long A); +extern long _IQ22exp(long A); +extern long _IQ21exp(long A); +extern long _IQ20exp(long A); +extern long _IQ19exp(long A); +extern long _IQ18exp(long A); +extern long _IQ17exp(long A); +extern long _IQ16exp(long A); +extern long _IQ15exp(long A); +extern long _IQ14exp(long A); +extern long _IQ13exp(long A); +extern long _IQ12exp(long A); +extern long _IQ11exp(long A); +extern long _IQ10exp(long A); +extern long _IQ9exp(long A); +extern long _IQ8exp(long A); +extern long _IQ7exp(long A); +extern long _IQ6exp(long A); +extern long _IQ5exp(long A); +extern long _IQ4exp(long A); +extern long _IQ3exp(long A); +extern long _IQ2exp(long A); +extern long _IQ1exp(long A); + +#if GLOBAL_Q == 30 +#define _IQexp(A) _IQ30exp(A) +#endif +#if GLOBAL_Q == 29 +#define _IQexp(A) _IQ29exp(A) +#endif +#if GLOBAL_Q == 28 +#define _IQexp(A) _IQ28exp(A) +#endif +#if GLOBAL_Q == 27 +#define _IQexp(A) _IQ27exp(A) +#endif +#if GLOBAL_Q == 26 +#define _IQexp(A) _IQ26exp(A) +#endif +#if GLOBAL_Q == 25 +#define _IQexp(A) _IQ25exp(A) +#endif +#if GLOBAL_Q == 24 +#define _IQexp(A) _IQ24exp(A) +#endif +#if GLOBAL_Q == 23 +#define _IQexp(A) _IQ23exp(A) +#endif +#if GLOBAL_Q == 22 +#define _IQexp(A) _IQ22exp(A) +#endif +#if GLOBAL_Q == 21 +#define _IQexp(A) _IQ21exp(A) +#endif +#if GLOBAL_Q == 20 +#define _IQexp(A) _IQ20exp(A) +#endif +#if GLOBAL_Q == 19 +#define _IQexp(A) _IQ19exp(A) +#endif +#if GLOBAL_Q == 18 +#define _IQexp(A) _IQ18exp(A) +#endif +#if GLOBAL_Q == 17 +#define _IQexp(A) _IQ17exp(A) +#endif +#if GLOBAL_Q == 16 +#define _IQexp(A) _IQ16exp(A) +#endif +#if GLOBAL_Q == 15 +#define _IQexp(A) _IQ15exp(A) +#endif +#if GLOBAL_Q == 14 +#define _IQexp(A) _IQ14exp(A) +#endif +#if GLOBAL_Q == 13 +#define _IQexp(A) _IQ13exp(A) +#endif +#if GLOBAL_Q == 12 +#define _IQexp(A) _IQ12exp(A) +#endif +#if GLOBAL_Q == 11 +#define _IQexp(A) _IQ11exp(A) +#endif +#if GLOBAL_Q == 10 +#define _IQexp(A) _IQ10exp(A) +#endif +#if GLOBAL_Q == 9 +#define _IQexp(A) _IQ9exp(A) +#endif +#if GLOBAL_Q == 8 +#define _IQexp(A) _IQ8exp(A) +#endif +#if GLOBAL_Q == 7 +#define _IQexp(A) _IQ7exp(A) +#endif +#if GLOBAL_Q == 6 +#define _IQexp(A) _IQ6exp(A) +#endif +#if GLOBAL_Q == 5 +#define _IQexp(A) _IQ5exp(A) +#endif +#if GLOBAL_Q == 4 +#define _IQexp(A) _IQ4exp(A) +#endif +#if GLOBAL_Q == 3 +#define _IQexp(A) _IQ3exp(A) +#endif +#if GLOBAL_Q == 2 +#define _IQexp(A) _IQ2exp(A) +#endif +#if GLOBAL_Q == 1 +#define _IQexp(A) _IQ1exp(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30int(long A); +extern long _IQ29int(long A); +extern long _IQ28int(long A); +extern long _IQ27int(long A); +extern long _IQ26int(long A); +extern long _IQ25int(long A); +extern long _IQ24int(long A); +extern long _IQ23int(long A); +extern long _IQ22int(long A); +extern long _IQ21int(long A); +extern long _IQ20int(long A); +extern long _IQ19int(long A); +extern long _IQ18int(long A); +extern long _IQ17int(long A); +extern long _IQ16int(long A); +extern long _IQ15int(long A); +extern long _IQ14int(long A); +extern long _IQ13int(long A); +extern long _IQ12int(long A); +extern long _IQ11int(long A); +extern long _IQ10int(long A); +extern long _IQ9int(long A); +extern long _IQ8int(long A); +extern long _IQ7int(long A); +extern long _IQ6int(long A); +extern long _IQ5int(long A); +extern long _IQ4int(long A); +extern long _IQ3int(long A); +extern long _IQ2int(long A); +extern long _IQ1int(long A); + +#if GLOBAL_Q == 30 +#define _IQint(A) _IQ30int(A) +#endif +#if GLOBAL_Q == 29 +#define _IQint(A) _IQ29int(A) +#endif +#if GLOBAL_Q == 28 +#define _IQint(A) _IQ28int(A) +#endif +#if GLOBAL_Q == 27 +#define _IQint(A) _IQ27int(A) +#endif +#if GLOBAL_Q == 26 +#define _IQint(A) _IQ26int(A) +#endif +#if GLOBAL_Q == 25 +#define _IQint(A) _IQ25int(A) +#endif +#if GLOBAL_Q == 24 +#define _IQint(A) _IQ24int(A) +#endif +#if GLOBAL_Q == 23 +#define _IQint(A) _IQ23int(A) +#endif +#if GLOBAL_Q == 22 +#define _IQint(A) _IQ22int(A) +#endif +#if GLOBAL_Q == 21 +#define _IQint(A) _IQ21int(A) +#endif +#if GLOBAL_Q == 20 +#define _IQint(A) _IQ20int(A) +#endif +#if GLOBAL_Q == 19 +#define _IQint(A) _IQ19int(A) +#endif +#if GLOBAL_Q == 18 +#define _IQint(A) _IQ18int(A) +#endif +#if GLOBAL_Q == 17 +#define _IQint(A) _IQ17int(A) +#endif +#if GLOBAL_Q == 16 +#define _IQint(A) _IQ16int(A) +#endif +#if GLOBAL_Q == 15 +#define _IQint(A) _IQ15int(A) +#endif +#if GLOBAL_Q == 14 +#define _IQint(A) _IQ14int(A) +#endif +#if GLOBAL_Q == 13 +#define _IQint(A) _IQ13int(A) +#endif +#if GLOBAL_Q == 12 +#define _IQint(A) _IQ12int(A) +#endif +#if GLOBAL_Q == 11 +#define _IQint(A) _IQ11int(A) +#endif +#if GLOBAL_Q == 10 +#define _IQint(A) _IQ10int(A) +#endif +#if GLOBAL_Q == 9 +#define _IQint(A) _IQ9int(A) +#endif +#if GLOBAL_Q == 8 +#define _IQint(A) _IQ8int(A) +#endif +#if GLOBAL_Q == 7 +#define _IQint(A) _IQ7int(A) +#endif +#if GLOBAL_Q == 6 +#define _IQint(A) _IQ6int(A) +#endif +#if GLOBAL_Q == 5 +#define _IQint(A) _IQ5int(A) +#endif +#if GLOBAL_Q == 4 +#define _IQint(A) _IQ4int(A) +#endif +#if GLOBAL_Q == 3 +#define _IQint(A) _IQ3int(A) +#endif +#if GLOBAL_Q == 2 +#define _IQint(A) _IQ2int(A) +#endif +#if GLOBAL_Q == 1 +#define _IQint(A) _IQ1int(A) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30frac(long A); +extern long _IQ29frac(long A); +extern long _IQ28frac(long A); +extern long _IQ27frac(long A); +extern long _IQ26frac(long A); +extern long _IQ25frac(long A); +extern long _IQ24frac(long A); +extern long _IQ23frac(long A); +extern long _IQ22frac(long A); +extern long _IQ21frac(long A); +extern long _IQ20frac(long A); +extern long _IQ19frac(long A); +extern long _IQ18frac(long A); +extern long _IQ17frac(long A); +extern long _IQ16frac(long A); +extern long _IQ15frac(long A); +extern long _IQ14frac(long A); +extern long _IQ13frac(long A); +extern long _IQ12frac(long A); +extern long _IQ11frac(long A); +extern long _IQ10frac(long A); +extern long _IQ9frac(long A); +extern long _IQ8frac(long A); +extern long _IQ7frac(long A); +extern long _IQ6frac(long A); +extern long _IQ5frac(long A); +extern long _IQ4frac(long A); +extern long _IQ3frac(long A); +extern long _IQ2frac(long A); +extern long _IQ1frac(long A); + +#if GLOBAL_Q == 30 +#define _IQfrac(A) _IQ30frac(A) +#endif +#if GLOBAL_Q == 29 +#define _IQfrac(A) _IQ29frac(A) +#endif +#if GLOBAL_Q == 28 +#define _IQfrac(A) _IQ28frac(A) +#endif +#if GLOBAL_Q == 27 +#define _IQfrac(A) _IQ27frac(A) +#endif +#if GLOBAL_Q == 26 +#define _IQfrac(A) _IQ26frac(A) +#endif +#if GLOBAL_Q == 25 +#define _IQfrac(A) _IQ25frac(A) +#endif +#if GLOBAL_Q == 24 +#define _IQfrac(A) _IQ24frac(A) +#endif +#if GLOBAL_Q == 23 +#define _IQfrac(A) _IQ23frac(A) +#endif +#if GLOBAL_Q == 22 +#define _IQfrac(A) _IQ22frac(A) +#endif +#if GLOBAL_Q == 21 +#define _IQfrac(A) _IQ21frac(A) +#endif +#if GLOBAL_Q == 20 +#define _IQfrac(A) _IQ20frac(A) +#endif +#if GLOBAL_Q == 19 +#define _IQfrac(A) _IQ19frac(A) +#endif +#if GLOBAL_Q == 18 +#define _IQfrac(A) _IQ18frac(A) +#endif +#if GLOBAL_Q == 17 +#define _IQfrac(A) _IQ17frac(A) +#endif +#if GLOBAL_Q == 16 +#define _IQfrac(A) _IQ16frac(A) +#endif +#if GLOBAL_Q == 15 +#define _IQfrac(A) _IQ15frac(A) +#endif +#if GLOBAL_Q == 14 +#define _IQfrac(A) _IQ14frac(A) +#endif +#if GLOBAL_Q == 13 +#define _IQfrac(A) _IQ13frac(A) +#endif +#if GLOBAL_Q == 12 +#define _IQfrac(A) _IQ12frac(A) +#endif +#if GLOBAL_Q == 11 +#define _IQfrac(A) _IQ11frac(A) +#endif +#if GLOBAL_Q == 10 +#define _IQfrac(A) _IQ10frac(A) +#endif +#if GLOBAL_Q == 9 +#define _IQfrac(A) _IQ9frac(A) +#endif +#if GLOBAL_Q == 8 +#define _IQfrac(A) _IQ8frac(A) +#endif +#if GLOBAL_Q == 7 +#define _IQfrac(A) _IQ7frac(A) +#endif +#if GLOBAL_Q == 6 +#define _IQfrac(A) _IQ6frac(A) +#endif +#if GLOBAL_Q == 5 +#define _IQfrac(A) _IQ5frac(A) +#endif +#if GLOBAL_Q == 4 +#define _IQfrac(A) _IQ4frac(A) +#endif +#if GLOBAL_Q == 3 +#define _IQfrac(A) _IQ3frac(A) +#endif +#if GLOBAL_Q == 2 +#define _IQfrac(A) _IQ2frac(A) +#endif +#if GLOBAL_Q == 1 +#define _IQfrac(A) _IQ1frac(A) +#endif +//--------------------------------------------------------------------------- +#define _IQmpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (GLOBAL_Q + 32 - IQA - IQB)) +#define _IQ30mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (30 + 32 - IQA - IQB)) +#define _IQ29mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (29 + 32 - IQA - IQB)) +#define _IQ28mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (28 + 32 - IQA - IQB)) +#define _IQ27mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (27 + 32 - IQA - IQB)) +#define _IQ26mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (26 + 32 - IQA - IQB)) +#define _IQ25mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (25 + 32 - IQA - IQB)) +#define _IQ24mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (24 + 32 - IQA - IQB)) +#define _IQ23mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (23 + 32 - IQA - IQB)) +#define _IQ22mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (22 + 32 - IQA - IQB)) +#define _IQ21mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (21 + 32 - IQA - IQB)) +#define _IQ20mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (20 + 32 - IQA - IQB)) +#define _IQ19mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (19 + 32 - IQA - IQB)) +#define _IQ18mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (18 + 32 - IQA - IQB)) +#define _IQ17mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (17 + 32 - IQA - IQB)) +#define _IQ16mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (16 + 32 - IQA - IQB)) +#define _IQ15mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (15 + 32 - IQA - IQB)) +#define _IQ14mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (14 + 32 - IQA - IQB)) +#define _IQ13mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (13 + 32 - IQA - IQB)) +#define _IQ12mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (12 + 32 - IQA - IQB)) +#define _IQ11mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (11 + 32 - IQA - IQB)) +#define _IQ10mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (10 + 32 - IQA - IQB)) +#define _IQ9mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (9 + 32 - IQA - IQB)) +#define _IQ8mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (8 + 32 - IQA - IQB)) +#define _IQ7mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (7 + 32 - IQA - IQB)) +#define _IQ6mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (6 + 32 - IQA - IQB)) +#define _IQ5mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (5 + 32 - IQA - IQB)) +#define _IQ4mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (4 + 32 - IQA - IQB)) +#define _IQ3mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (3 + 32 - IQA - IQB)) +#define _IQ2mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (2 + 32 - IQA - IQB)) +#define _IQ1mpyIQX(A, IQA, B, IQB) __IQxmpy(A, B, (1 + 32 - IQA - IQB)) +//--------------------------------------------------------------------------- +#define _IQmpyI32(A,B) ((A)*(B)) +#define _IQ30mpyI32(A,B) ((A)*(B)) +#define _IQ29mpyI32(A,B) ((A)*(B)) +#define _IQ28mpyI32(A,B) ((A)*(B)) +#define _IQ27mpyI32(A,B) ((A)*(B)) +#define _IQ26mpyI32(A,B) ((A)*(B)) +#define _IQ25mpyI32(A,B) ((A)*(B)) +#define _IQ24mpyI32(A,B) ((A)*(B)) +#define _IQ23mpyI32(A,B) ((A)*(B)) +#define _IQ22mpyI32(A,B) ((A)*(B)) +#define _IQ21mpyI32(A,B) ((A)*(B)) +#define _IQ20mpyI32(A,B) ((A)*(B)) +#define _IQ19mpyI32(A,B) ((A)*(B)) +#define _IQ18mpyI32(A,B) ((A)*(B)) +#define _IQ17mpyI32(A,B) ((A)*(B)) +#define _IQ16mpyI32(A,B) ((A)*(B)) +#define _IQ15mpyI32(A,B) ((A)*(B)) +#define _IQ14mpyI32(A,B) ((A)*(B)) +#define _IQ13mpyI32(A,B) ((A)*(B)) +#define _IQ12mpyI32(A,B) ((A)*(B)) +#define _IQ11mpyI32(A,B) ((A)*(B)) +#define _IQ10mpyI32(A,B) ((A)*(B)) +#define _IQ9mpyI32(A,B) ((A)*(B)) +#define _IQ8mpyI32(A,B) ((A)*(B)) +#define _IQ7mpyI32(A,B) ((A)*(B)) +#define _IQ6mpyI32(A,B) ((A)*(B)) +#define _IQ5mpyI32(A,B) ((A)*(B)) +#define _IQ4mpyI32(A,B) ((A)*(B)) +#define _IQ3mpyI32(A,B) ((A)*(B)) +#define _IQ2mpyI32(A,B) ((A)*(B)) +#define _IQ1mpyI32(A,B) ((A)*(B)) +//--------------------------------------------------------------------------- +extern long _IQ30mpyI32int(long A, long B); +extern long _IQ29mpyI32int(long A, long B); +extern long _IQ28mpyI32int(long A, long B); +extern long _IQ27mpyI32int(long A, long B); +extern long _IQ26mpyI32int(long A, long B); +extern long _IQ25mpyI32int(long A, long B); +extern long _IQ24mpyI32int(long A, long B); +extern long _IQ23mpyI32int(long A, long B); +extern long _IQ22mpyI32int(long A, long B); +extern long _IQ21mpyI32int(long A, long B); +extern long _IQ20mpyI32int(long A, long B); +extern long _IQ19mpyI32int(long A, long B); +extern long _IQ18mpyI32int(long A, long B); +extern long _IQ17mpyI32int(long A, long B); +extern long _IQ16mpyI32int(long A, long B); +extern long _IQ15mpyI32int(long A, long B); +extern long _IQ14mpyI32int(long A, long B); +extern long _IQ13mpyI32int(long A, long B); +extern long _IQ12mpyI32int(long A, long B); +extern long _IQ11mpyI32int(long A, long B); +extern long _IQ10mpyI32int(long A, long B); +extern long _IQ9mpyI32int(long A, long B); +extern long _IQ8mpyI32int(long A, long B); +extern long _IQ7mpyI32int(long A, long B); +extern long _IQ6mpyI32int(long A, long B); +extern long _IQ5mpyI32int(long A, long B); +extern long _IQ4mpyI32int(long A, long B); +extern long _IQ3mpyI32int(long A, long B); +extern long _IQ2mpyI32int(long A, long B); +extern long _IQ1mpyI32int(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQmpyI32int(A, B) _IQ30mpyI32int(A, B) +#endif +#if GLOBAL_Q == 29 +#define _IQmpyI32int(A, B) _IQ29mpyI32int(A, B) +#endif +#if GLOBAL_Q == 28 +#define _IQmpyI32int(A, B) _IQ28mpyI32int(A, B) +#endif +#if GLOBAL_Q == 27 +#define _IQmpyI32int(A, B) _IQ27mpyI32int(A, B) +#endif +#if GLOBAL_Q == 26 +#define _IQmpyI32int(A, B) _IQ26mpyI32int(A, B) +#endif +#if GLOBAL_Q == 25 +#define _IQmpyI32int(A, B) _IQ25mpyI32int(A, B) +#endif +#if GLOBAL_Q == 24 +#define _IQmpyI32int(A, B) _IQ24mpyI32int(A, B) +#endif +#if GLOBAL_Q == 23 +#define _IQmpyI32int(A, B) _IQ23mpyI32int(A, B) +#endif +#if GLOBAL_Q == 22 +#define _IQmpyI32int(A, B) _IQ22mpyI32int(A, B) +#endif +#if GLOBAL_Q == 21 +#define _IQmpyI32int(A, B) _IQ21mpyI32int(A, B) +#endif +#if GLOBAL_Q == 20 +#define _IQmpyI32int(A, B) _IQ20mpyI32int(A, B) +#endif +#if GLOBAL_Q == 19 +#define _IQmpyI32int(A, B) _IQ19mpyI32int(A, B) +#endif +#if GLOBAL_Q == 18 +#define _IQmpyI32int(A, B) _IQ18mpyI32int(A, B) +#endif +#if GLOBAL_Q == 17 +#define _IQmpyI32int(A, B) _IQ17mpyI32int(A, B) +#endif +#if GLOBAL_Q == 16 +#define _IQmpyI32int(A, B) _IQ16mpyI32int(A, B) +#endif +#if GLOBAL_Q == 15 +#define _IQmpyI32int(A, B) _IQ15mpyI32int(A, B) +#endif +#if GLOBAL_Q == 14 +#define _IQmpyI32int(A, B) _IQ14mpyI32int(A, B) +#endif +#if GLOBAL_Q == 13 +#define _IQmpyI32int(A, B) _IQ13mpyI32int(A, B) +#endif +#if GLOBAL_Q == 12 +#define _IQmpyI32int(A, B) _IQ12mpyI32int(A, B) +#endif +#if GLOBAL_Q == 11 +#define _IQmpyI32int(A, B) _IQ11mpyI32int(A, B) +#endif +#if GLOBAL_Q == 10 +#define _IQmpyI32int(A, B) _IQ10mpyI32int(A, B) +#endif +#if GLOBAL_Q == 9 +#define _IQmpyI32int(A, B) _IQ9mpyI32int(A, B) +#endif +#if GLOBAL_Q == 8 +#define _IQmpyI32int(A, B) _IQ8mpyI32int(A, B) +#endif +#if GLOBAL_Q == 7 +#define _IQmpyI32int(A, B) _IQ7mpyI32int(A, B) +#endif +#if GLOBAL_Q == 6 +#define _IQmpyI32int(A, B) _IQ6mpyI32int(A, B) +#endif +#if GLOBAL_Q == 5 +#define _IQmpyI32int(A, B) _IQ5mpyI32int(A, B) +#endif +#if GLOBAL_Q == 4 +#define _IQmpyI32int(A, B) _IQ4mpyI32int(A, B) +#endif +#if GLOBAL_Q == 3 +#define _IQmpyI32int(A, B) _IQ3mpyI32int(A, B) +#endif +#if GLOBAL_Q == 2 +#define _IQmpyI32int(A, B) _IQ2mpyI32int(A, B) +#endif +#if GLOBAL_Q == 1 +#define _IQmpyI32int(A, B) _IQ1mpyI32int(A, B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30mpyI32frac(long A, long B); +extern long _IQ29mpyI32frac(long A, long B); +extern long _IQ28mpyI32frac(long A, long B); +extern long _IQ27mpyI32frac(long A, long B); +extern long _IQ26mpyI32frac(long A, long B); +extern long _IQ25mpyI32frac(long A, long B); +extern long _IQ24mpyI32frac(long A, long B); +extern long _IQ23mpyI32frac(long A, long B); +extern long _IQ22mpyI32frac(long A, long B); +extern long _IQ21mpyI32frac(long A, long B); +extern long _IQ20mpyI32frac(long A, long B); +extern long _IQ19mpyI32frac(long A, long B); +extern long _IQ18mpyI32frac(long A, long B); +extern long _IQ17mpyI32frac(long A, long B); +extern long _IQ16mpyI32frac(long A, long B); +extern long _IQ15mpyI32frac(long A, long B); +extern long _IQ14mpyI32frac(long A, long B); +extern long _IQ13mpyI32frac(long A, long B); +extern long _IQ12mpyI32frac(long A, long B); +extern long _IQ11mpyI32frac(long A, long B); +extern long _IQ10mpyI32frac(long A, long B); +extern long _IQ9mpyI32frac(long A, long B); +extern long _IQ8mpyI32frac(long A, long B); +extern long _IQ7mpyI32frac(long A, long B); +extern long _IQ6mpyI32frac(long A, long B); +extern long _IQ5mpyI32frac(long A, long B); +extern long _IQ4mpyI32frac(long A, long B); +extern long _IQ3mpyI32frac(long A, long B); +extern long _IQ2mpyI32frac(long A, long B); +extern long _IQ1mpyI32frac(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQmpyI32frac(A, B) _IQ30mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 29 +#define _IQmpyI32frac(A, B) _IQ29mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 28 +#define _IQmpyI32frac(A, B) _IQ28mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 27 +#define _IQmpyI32frac(A, B) _IQ27mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 26 +#define _IQmpyI32frac(A, B) _IQ26mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 25 +#define _IQmpyI32frac(A, B) _IQ25mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 24 +#define _IQmpyI32frac(A, B) _IQ24mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 23 +#define _IQmpyI32frac(A, B) _IQ23mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 22 +#define _IQmpyI32frac(A, B) _IQ22mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 21 +#define _IQmpyI32frac(A, B) _IQ21mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 20 +#define _IQmpyI32frac(A, B) _IQ20mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 19 +#define _IQmpyI32frac(A, B) _IQ19mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 18 +#define _IQmpyI32frac(A, B) _IQ18mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 17 +#define _IQmpyI32frac(A, B) _IQ17mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 16 +#define _IQmpyI32frac(A, B) _IQ16mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 15 +#define _IQmpyI32frac(A, B) _IQ15mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 14 +#define _IQmpyI32frac(A, B) _IQ14mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 13 +#define _IQmpyI32frac(A, B) _IQ13mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 12 +#define _IQmpyI32frac(A, B) _IQ12mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 11 +#define _IQmpyI32frac(A, B) _IQ11mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 10 +#define _IQmpyI32frac(A, B) _IQ10mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 9 +#define _IQmpyI32frac(A, B) _IQ9mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 8 +#define _IQmpyI32frac(A, B) _IQ8mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 7 +#define _IQmpyI32frac(A, B) _IQ7mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 6 +#define _IQmpyI32frac(A, B) _IQ6mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 5 +#define _IQmpyI32frac(A, B) _IQ5mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 4 +#define _IQmpyI32frac(A, B) _IQ4mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 3 +#define _IQmpyI32frac(A, B) _IQ3mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 2 +#define _IQmpyI32frac(A, B) _IQ2mpyI32frac(A, B) +#endif +#if GLOBAL_Q == 1 +#define _IQmpyI32frac(A, B) _IQ1mpyI32frac(A, B) +#endif +//--------------------------------------------------------------------------- +extern long _IQ30mag(long A, long B); +extern long _IQ29mag(long A, long B); +extern long _IQ28mag(long A, long B); +extern long _IQ27mag(long A, long B); +extern long _IQ26mag(long A, long B); +extern long _IQ25mag(long A, long B); +extern long _IQ24mag(long A, long B); +extern long _IQ23mag(long A, long B); +extern long _IQ22mag(long A, long B); +extern long _IQ21mag(long A, long B); +extern long _IQ20mag(long A, long B); +extern long _IQ19mag(long A, long B); +extern long _IQ18mag(long A, long B); +extern long _IQ17mag(long A, long B); +extern long _IQ16mag(long A, long B); +extern long _IQ15mag(long A, long B); +extern long _IQ14mag(long A, long B); +extern long _IQ13mag(long A, long B); +extern long _IQ12mag(long A, long B); +extern long _IQ11mag(long A, long B); +extern long _IQ10mag(long A, long B); +extern long _IQ9mag(long A, long B); +extern long _IQ8mag(long A, long B); +extern long _IQ7mag(long A, long B); +extern long _IQ6mag(long A, long B); +extern long _IQ5mag(long A, long B); +extern long _IQ4mag(long A, long B); +extern long _IQ3mag(long A, long B); +extern long _IQ2mag(long A, long B); +extern long _IQ1mag(long A, long B); + +#if GLOBAL_Q == 30 +#define _IQmag(A, B) _IQ30mag(A, B) +#endif +#if GLOBAL_Q == 29 +#define _IQmag(A, B) _IQ29mag(A, B) +#endif +#if GLOBAL_Q == 28 +#define _IQmag(A, B) _IQ28mag(A, B) +#endif +#if GLOBAL_Q == 27 +#define _IQmag(A, B) _IQ27mag(A, B) +#endif +#if GLOBAL_Q == 26 +#define _IQmag(A, B) _IQ26mag(A, B) +#endif +#if GLOBAL_Q == 25 +#define _IQmag(A, B) _IQ25mag(A, B) +#endif +#if GLOBAL_Q == 24 +#define _IQmag(A, B) _IQ24mag(A, B) +#endif +#if GLOBAL_Q == 23 +#define _IQmag(A, B) _IQ23mag(A, B) +#endif +#if GLOBAL_Q == 22 +#define _IQmag(A, B) _IQ22mag(A, B) +#endif +#if GLOBAL_Q == 21 +#define _IQmag(A, B) _IQ21mag(A, B) +#endif +#if GLOBAL_Q == 20 +#define _IQmag(A, B) _IQ20mag(A, B) +#endif +#if GLOBAL_Q == 19 +#define _IQmag(A, B) _IQ19mag(A, B) +#endif +#if GLOBAL_Q == 18 +#define _IQmag(A, B) _IQ18mag(A, B) +#endif +#if GLOBAL_Q == 17 +#define _IQmag(A, B) _IQ17mag(A, B) +#endif +#if GLOBAL_Q == 16 +#define _IQmag(A, B) _IQ16mag(A, B) +#endif +#if GLOBAL_Q == 15 +#define _IQmag(A, B) _IQ15mag(A, B) +#endif +#if GLOBAL_Q == 14 +#define _IQmag(A, B) _IQ14mag(A, B) +#endif +#if GLOBAL_Q == 13 +#define _IQmag(A, B) _IQ13mag(A, B) +#endif +#if GLOBAL_Q == 12 +#define _IQmag(A, B) _IQ12mag(A, B) +#endif +#if GLOBAL_Q == 11 +#define _IQmag(A, B) _IQ11mag(A, B) +#endif +#if GLOBAL_Q == 10 +#define _IQmag(A, B) _IQ10mag(A, B) +#endif +#if GLOBAL_Q == 9 +#define _IQmag(A, B) _IQ9mag(A, B) +#endif +#if GLOBAL_Q == 8 +#define _IQmag(A, B) _IQ8mag(A, B) +#endif +#if GLOBAL_Q == 7 +#define _IQmag(A, B) _IQ7mag(A, B) +#endif +#if GLOBAL_Q == 6 +#define _IQmag(A, B) _IQ6mag(A, B) +#endif +#if GLOBAL_Q == 5 +#define _IQmag(A, B) _IQ5mag(A, B) +#endif +#if GLOBAL_Q == 4 +#define _IQmag(A, B) _IQ4mag(A, B) +#endif +#if GLOBAL_Q == 3 +#define _IQmag(A, B) _IQ3mag(A, B) +#endif +#if GLOBAL_Q == 2 +#define _IQmag(A, B) _IQ2mag(A, B) +#endif +#if GLOBAL_Q == 1 +#define _IQmag(A, B) _IQ1mag(A, B) +#endif +//--------------------------------------------------------------------------- +extern long _atoIQN(const char *A, long q_value); +#define _atoIQ(A) _atoIQN(A, GLOBAL_Q) +#define _atoIQ30(A) _atoIQN(A, 30) +#define _atoIQ29(A) _atoIQN(A, 29) +#define _atoIQ28(A) _atoIQN(A, 28) +#define _atoIQ27(A) _atoIQN(A, 27) +#define _atoIQ26(A) _atoIQN(A, 26) +#define _atoIQ25(A) _atoIQN(A, 25) +#define _atoIQ24(A) _atoIQN(A, 24) +#define _atoIQ23(A) _atoIQN(A, 23) +#define _atoIQ22(A) _atoIQN(A, 22) +#define _atoIQ21(A) _atoIQN(A, 21) +#define _atoIQ20(A) _atoIQN(A, 20) +#define _atoIQ19(A) _atoIQN(A, 19) +#define _atoIQ18(A) _atoIQN(A, 18) +#define _atoIQ17(A) _atoIQN(A, 17) +#define _atoIQ16(A) _atoIQN(A, 16) +#define _atoIQ15(A) _atoIQN(A, 15) +#define _atoIQ14(A) _atoIQN(A, 14) +#define _atoIQ13(A) _atoIQN(A, 13) +#define _atoIQ12(A) _atoIQN(A, 12) +#define _atoIQ11(A) _atoIQN(A, 11) +#define _atoIQ10(A) _atoIQN(A, 10) +#define _atoIQ9(A) _atoIQN(A, 9) +#define _atoIQ8(A) _atoIQN(A, 8) +#define _atoIQ7(A) _atoIQN(A, 7) +#define _atoIQ6(A) _atoIQN(A, 6) +#define _atoIQ5(A) _atoIQN(A, 5) +#define _atoIQ4(A) _atoIQN(A, 4) +#define _atoIQ3(A) _atoIQN(A, 3) +#define _atoIQ2(A) _atoIQN(A, 2) +#define _atoIQ1(A) _atoIQN(A, 1) +//--------------------------------------------------------------------------- +extern int __IQNtoa(char *A, const char *B, long C, int D); +extern int _IQ30toa(char *A, const char *B, long C); +extern int _IQ29toa(char *A, const char *B, long C); +extern int _IQ28toa(char *A, const char *B, long C); +extern int _IQ27toa(char *A, const char *B, long C); +extern int _IQ26toa(char *A, const char *B, long C); +extern int _IQ25toa(char *A, const char *B, long C); +extern int _IQ24toa(char *A, const char *B, long C); +extern int _IQ23toa(char *A, const char *B, long C); +extern int _IQ22toa(char *A, const char *B, long C); +extern int _IQ21toa(char *A, const char *B, long C); +extern int _IQ20toa(char *A, const char *B, long C); +extern int _IQ19toa(char *A, const char *B, long C); +extern int _IQ18toa(char *A, const char *B, long C); +extern int _IQ17toa(char *A, const char *B, long C); +extern int _IQ16toa(char *A, const char *B, long C); +extern int _IQ15toa(char *A, const char *B, long C); +extern int _IQ14toa(char *A, const char *B, long C); +extern int _IQ13toa(char *A, const char *B, long C); +extern int _IQ12toa(char *A, const char *B, long C); +extern int _IQ11toa(char *A, const char *B, long C); +extern int _IQ10toa(char *A, const char *B, long C); +extern int _IQ9toa(char *A, const char *B, long C); +extern int _IQ8toa(char *A, const char *B, long C); +extern int _IQ7toa(char *A, const char *B, long C); +extern int _IQ6toa(char *A, const char *B, long C); +extern int _IQ5toa(char *A, const char *B, long C); +extern int _IQ4toa(char *A, const char *B, long C); +extern int _IQ3toa(char *A, const char *B, long C); +extern int _IQ2toa(char *A, const char *B, long C); +extern int _IQ1toa(char *A, const char *B, long C); + + +#define _IQ30toa(A, B, C) __IQNtoa(A, B, C, 30); +#define _IQ29toa(A, B, C) __IQNtoa(A, B, C, 29); +#define _IQ28toa(A, B, C) __IQNtoa(A, B, C, 28); +#define _IQ27toa(A, B, C) __IQNtoa(A, B, C, 27); +#define _IQ26toa(A, B, C) __IQNtoa(A, B, C, 26); +#define _IQ25toa(A, B, C) __IQNtoa(A, B, C, 25); +#define _IQ24toa(A, B, C) __IQNtoa(A, B, C, 24); +#define _IQ23toa(A, B, C) __IQNtoa(A, B, C, 23); +#define _IQ21toa(A, B, C) __IQNtoa(A, B, C, 21); +#define _IQ22toa(A, B, C) __IQNtoa(A, B, C, 22); +#define _IQ20toa(A, B, C) __IQNtoa(A, B, C, 20); +#define _IQ19toa(A, B, C) __IQNtoa(A, B, C, 19); +#define _IQ18toa(A, B, C) __IQNtoa(A, B, C, 18); +#define _IQ17toa(A, B, C) __IQNtoa(A, B, C, 17); +#define _IQ16toa(A, B, C) __IQNtoa(A, B, C, 16); +#define _IQ15toa(A, B, C) __IQNtoa(A, B, C, 15); +#define _IQ14toa(A, B, C) __IQNtoa(A, B, C, 14); +#define _IQ13toa(A, B, C) __IQNtoa(A, B, C, 13); +#define _IQ12toa(A, B, C) __IQNtoa(A, B, C, 12); +#define _IQ11toa(A, B, C) __IQNtoa(A, B, C, 11); +#define _IQ10toa(A, B, C) __IQNtoa(A, B, C, 10); +#define _IQ9toa(A, B, C) __IQNtoa(A, B, C, 9); +#define _IQ8toa(A, B, C) __IQNtoa(A, B, C, 8); +#define _IQ7toa(A, B, C) __IQNtoa(A, B, C, 7); +#define _IQ6toa(A, B, C) __IQNtoa(A, B, C, 6); +#define _IQ5toa(A, B, C) __IQNtoa(A, B, C, 5); +#define _IQ4toa(A, B, C) __IQNtoa(A, B, C, 4); +#define _IQ3toa(A, B, C) __IQNtoa(A, B, C, 3); +#define _IQ2toa(A, B, C) __IQNtoa(A, B, C, 2); +#define _IQ1toa(A, B, C) __IQNtoa(A, B, C, 1); + + +#if GLOBAL_Q == 30 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 30) +#endif +#if GLOBAL_Q == 29 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 29) +#endif +#if GLOBAL_Q == 28 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 28) +#endif +#if GLOBAL_Q == 27 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 27) +#endif +#if GLOBAL_Q == 26 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 26) +#endif +#if GLOBAL_Q == 25 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 25) +#endif +#if GLOBAL_Q == 24 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 24) +#endif +#if GLOBAL_Q == 23 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 23) +#endif +#if GLOBAL_Q == 22 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 22) +#endif +#if GLOBAL_Q == 21 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 21) +#endif +#if GLOBAL_Q == 20 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 20) +#endif +#if GLOBAL_Q == 19 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 19) +#endif +#if GLOBAL_Q == 18 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 18) +#endif +#if GLOBAL_Q == 17 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 17) +#endif +#if GLOBAL_Q == 16 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 16) +#endif +#if GLOBAL_Q == 15 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 15) +#endif +#if GLOBAL_Q == 14 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 14) +#endif +#if GLOBAL_Q == 13 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 13) +#endif +#if GLOBAL_Q == 12 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 12) +#endif +#if GLOBAL_Q == 11 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 11) +#endif +#if GLOBAL_Q == 10 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 10) +#endif +#if GLOBAL_Q == 9 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 9) +#endif +#if GLOBAL_Q == 8 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 8) +#endif +#if GLOBAL_Q == 7 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 7) +#endif +#if GLOBAL_Q == 6 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 6) +#endif +#if GLOBAL_Q == 5 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 5) +#endif +#if GLOBAL_Q == 4 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 4) +#endif +#if GLOBAL_Q == 3 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 3) +#endif +#if GLOBAL_Q == 2 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 2) +#endif +#if GLOBAL_Q == 1 +#define _IQtoa(A, B, C) __IQNtoa(A, B, C, 1) +#endif +//--------------------------------------------------------------------------- +#define _IQabs(A) labs(A) +#define _IQ30abs(A) labs(A) +#define _IQ29abs(A) labs(A) +#define _IQ28abs(A) labs(A) +#define _IQ27abs(A) labs(A) +#define _IQ26abs(A) labs(A) +#define _IQ25abs(A) labs(A) +#define _IQ24abs(A) labs(A) +#define _IQ23abs(A) labs(A) +#define _IQ22abs(A) labs(A) +#define _IQ21abs(A) labs(A) +#define _IQ20abs(A) labs(A) +#define _IQ19abs(A) labs(A) +#define _IQ18abs(A) labs(A) +#define _IQ17abs(A) labs(A) +#define _IQ16abs(A) labs(A) +#define _IQ15abs(A) labs(A) +#define _IQ14abs(A) labs(A) +#define _IQ13abs(A) labs(A) +#define _IQ12abs(A) labs(A) +#define _IQ11abs(A) labs(A) +#define _IQ10abs(A) labs(A) +#define _IQ9abs(A) labs(A) +#define _IQ8abs(A) labs(A) +#define _IQ7abs(A) labs(A) +#define _IQ6abs(A) labs(A) +#define _IQ5abs(A) labs(A) +#define _IQ4abs(A) labs(A) +#define _IQ3abs(A) labs(A) +#define _IQ2abs(A) labs(A) +#define _IQ1abs(A) labs(A) +//--------------------------------------------------------------------------- +extern long _IQ30log(long A); +extern long _IQ29log(long A); +extern long _IQ28log(long A); +extern long _IQ27log(long A); +extern long _IQ26log(long A); +extern long _IQ25log(long A); +extern long _IQ24log(long A); +extern long _IQ23log(long A); +extern long _IQ22log(long A); +extern long _IQ21log(long A); +extern long _IQ20log(long A); +extern long _IQ19log(long A); +extern long _IQ18log(long A); +extern long _IQ17log(long A); +extern long _IQ16log(long A); +extern long _IQ15log(long A); +extern long _IQ14log(long A); +extern long _IQ13log(long A); +extern long _IQ12log(long A); +extern long _IQ11log(long A); +extern long _IQ10log(long A); +extern long _IQ9log(long A); +extern long _IQ8log(long A); +extern long _IQ7log(long A); +extern long _IQ6log(long A); +extern long _IQ5log(long A); +extern long _IQ4log(long A); +extern long _IQ3log(long A); +extern long _IQ2log(long A); +extern long _IQ1log(long A); + +#if GLOBAL_Q == 30 +#define _IQlog(A) _IQ30log(A) +#endif +#if GLOBAL_Q == 29 +#define _IQlog(A) _IQ29log(A) +#endif +#if GLOBAL_Q == 28 +#define _IQlog(A) _IQ28log(A) +#endif +#if GLOBAL_Q == 27 +#define _IQlog(A) _IQ27log(A) +#endif +#if GLOBAL_Q == 26 +#define _IQlog(A) _IQ26log(A) +#endif +#if GLOBAL_Q == 25 +#define _IQlog(A) _IQ25log(A) +#endif +#if GLOBAL_Q == 24 +#define _IQlog(A) _IQ24log(A) +#endif +#if GLOBAL_Q == 23 +#define _IQlog(A) _IQ23log(A) +#endif +#if GLOBAL_Q == 22 +#define _IQlog(A) _IQ22log(A) +#endif +#if GLOBAL_Q == 21 +#define _IQlog(A) _IQ21log(A) +#endif +#if GLOBAL_Q == 20 +#define _IQlog(A) _IQ20log(A) +#endif +#if GLOBAL_Q == 19 +#define _IQlog(A) _IQ19log(A) +#endif +#if GLOBAL_Q == 18 +#define _IQlog(A) _IQ18log(A) +#endif +#if GLOBAL_Q == 17 +#define _IQlog(A) _IQ17log(A) +#endif +#if GLOBAL_Q == 16 +#define _IQlog(A) _IQ16log(A) +#endif +#if GLOBAL_Q == 15 +#define _IQlog(A) _IQ15log(A) +#endif +#if GLOBAL_Q == 14 +#define _IQlog(A) _IQ14log(A) +#endif +#if GLOBAL_Q == 13 +#define _IQlog(A) _IQ13log(A) +#endif +#if GLOBAL_Q == 12 +#define _IQlog(A) _IQ12log(A) +#endif +#if GLOBAL_Q == 11 +#define _IQlog(A) _IQ11log(A) +#endif +#if GLOBAL_Q == 10 +#define _IQlog(A) _IQ10log(A) +#endif +#if GLOBAL_Q == 9 +#define _IQlog(A) _IQ9log(A) +#endif +#if GLOBAL_Q == 8 +#define _IQlog(A) _IQ8log(A) +#endif +#if GLOBAL_Q == 7 +#define _IQlog(A) _IQ7log(A) +#endif +#if GLOBAL_Q == 6 +#define _IQlog(A) _IQ6log(A) +#endif +#if GLOBAL_Q == 5 +#define _IQlog(A) _IQ5log(A) +#endif +#if GLOBAL_Q == 4 +#define _IQlog(A) _IQ4log(A) +#endif +#if GLOBAL_Q == 3 +#define _IQlog(A) _IQ3log(A) +#endif +#if GLOBAL_Q == 2 +#define _IQlog(A) _IQ2log(A) +#endif +#if GLOBAL_Q == 1 +#define _IQlog(A) _IQ1log(A) +#endif +//########################################################################### +#else // MATH_TYPE == FLOAT_MATH +//########################################################################### +// If FLOAT_MATH is used, the IQmath library function are replaced by +// equivalent floating point operations: +//=========================================================================== +typedef float _iq; +typedef float _iq30; +typedef float _iq29; +typedef float _iq28; +typedef float _iq27; +typedef float _iq26; +typedef float _iq25; +typedef float _iq24; +typedef float _iq23; +typedef float _iq22; +typedef float _iq21; +typedef float _iq20; +typedef float _iq19; +typedef float _iq18; +typedef float _iq17; +typedef float _iq16; +typedef float _iq15; +typedef float _iq14; +typedef float _iq13; +typedef float _iq12; +typedef float _iq11; +typedef float _iq10; +typedef float _iq9; +typedef float _iq8; +typedef float _iq7; +typedef float _iq6; +typedef float _iq5; +typedef float _iq4; +typedef float _iq3; +typedef float _iq2; +typedef float _iq1; + +//--------------------------------------------------------------------------- +#define _IQmpy2(A) ((A)*2.0) +#define _IQmpy4(A) ((A)*4.0) +#define _IQmpy8(A) ((A)*8.0) +#define _IQmpy16(A) ((A)*16.0) +#define _IQmpy32(A) ((A)*32.0) +#define _IQmpy64(A) ((A)*64.0) + +#define _IQdiv2(A) ((A)*0.5) +#define _IQdiv4(A) ((A)*0.25) +#define _IQdiv8(A) ((A)*0.125) +#define _IQdiv16(A) ((A)*0.0625) +#define _IQdiv32(A) ((A)*0.03125) +#define _IQdiv64(A) ((A)*0.015625) +//--------------------------------------------------------------------------- +#define _IQ(A) (A) +#define _IQ30(A) (A) +#define _IQ29(A) (A) +#define _IQ28(A) (A) +#define _IQ27(A) (A) +#define _IQ26(A) (A) +#define _IQ25(A) (A) +#define _IQ24(A) (A) +#define _IQ23(A) (A) +#define _IQ22(A) (A) +#define _IQ21(A) (A) +#define _IQ20(A) (A) +#define _IQ19(A) (A) +#define _IQ18(A) (A) +#define _IQ17(A) (A) +#define _IQ16(A) (A) +#define _IQ15(A) (A) +#define _IQ14(A) (A) +#define _IQ13(A) (A) +#define _IQ12(A) (A) +#define _IQ10(A) (A) +#define _IQ9(A) (A) +#define _IQ8(A) (A) +#define _IQ7(A) (A) +#define _IQ6(A) (A) +#define _IQ5(A) (A) +#define _IQ4(A) (A) +#define _IQ3(A) (A) +#define _IQ2(A) (A) +#define _IQ1(A) (A) +//--------------------------------------------------------------------------- +#define _IQtoF(A) (A) +#define _IQ30toF(A) (A) +#define _IQ29toF(A) (A) +#define _IQ28toF(A) (A) +#define _IQ27toF(A) (A) +#define _IQ26toF(A) (A) +#define _IQ25toF(A) (A) +#define _IQ24toF(A) (A) +#define _IQ23toF(A) (A) +#define _IQ22toF(A) (A) +#define _IQ21toF(A) (A) +#define _IQ20toF(A) (A) +#define _IQ19toF(A) (A) +#define _IQ18toF(A) (A) +#define _IQ17toF(A) (A) +#define _IQ16toF(A) (A) +#define _IQ15toF(A) (A) +#define _IQ14toF(A) (A) +#define _IQ13toF(A) (A) +#define _IQ12toF(A) (A) +#define _IQ11toF(A) (A) +#define _IQ10toF(A) (A) +#define _IQ9toF(A) (A) +#define _IQ8toF(A) (A) +#define _IQ7toF(A) (A) +#define _IQ6toF(A) (A) +#define _IQ5toF(A) (A) +#define _IQ4toF(A) (A) +#define _IQ3toF(A) (A) +#define _IQ2toF(A) (A) +#define _IQ1toF(A) (A) +//--------------------------------------------------------------------------- +//extern float _satf(float A, float Pos, float Neg); +//#define _IQsat(A, Pos, Neg) _satf(A, Pos, Neg) +// +// The following define requires codegen tools V5.2.2 or later +// +#define _IQsat(A, Pos, Neg) (__fmax(((__fmin((A),(Pos)))),(Neg))) +//--------------------------------------------------------------------------- +#define _IQtoIQ30(A) (A) +#define _IQtoIQ29(A) (A) +#define _IQtoIQ28(A) (A) +#define _IQtoIQ27(A) (A) +#define _IQtoIQ26(A) (A) +#define _IQtoIQ25(A) (A) +#define _IQtoIQ24(A) (A) +#define _IQtoIQ23(A) (A) +#define _IQtoIQ22(A) (A) +#define _IQtoIQ21(A) (A) +#define _IQtoIQ20(A) (A) +#define _IQtoIQ19(A) (A) +#define _IQtoIQ18(A) (A) +#define _IQtoIQ17(A) (A) +#define _IQtoIQ16(A) (A) +#define _IQtoIQ15(A) (A) +#define _IQtoIQ14(A) (A) +#define _IQtoIQ13(A) (A) +#define _IQtoIQ12(A) (A) +#define _IQtoIQ11(A) (A) +#define _IQtoIQ10(A) (A) +#define _IQtoIQ9(A) (A) +#define _IQtoIQ8(A) (A) +#define _IQtoIQ7(A) (A) +#define _IQtoIQ6(A) (A) +#define _IQtoIQ5(A) (A) +#define _IQtoIQ4(A) (A) +#define _IQtoIQ3(A) (A) +#define _IQtoIQ2(A) (A) +#define _IQtoIQ1(A) (A) +//--------------------------------------------------------------------------- +#define _IQ30toIQ(A) (A) +#define _IQ29toIQ(A) (A) +#define _IQ28toIQ(A) (A) +#define _IQ27toIQ(A) (A) +#define _IQ26toIQ(A) (A) +#define _IQ25toIQ(A) (A) +#define _IQ24toIQ(A) (A) +#define _IQ23toIQ(A) (A) +#define _IQ22toIQ(A) (A) +#define _IQ21toIQ(A) (A) +#define _IQ20toIQ(A) (A) +#define _IQ19toIQ(A) (A) +#define _IQ18toIQ(A) (A) +#define _IQ17toIQ(A) (A) +#define _IQ16toIQ(A) (A) +#define _IQ15toIQ(A) (A) +#define _IQ14toIQ(A) (A) +#define _IQ13toIQ(A) (A) +#define _IQ12toIQ(A) (A) +#define _IQ11toIQ(A) (A) +#define _IQ10toIQ(A) (A) +#define _IQ9toIQ(A) (A) +#define _IQ8toIQ(A) (A) +#define _IQ7toIQ(A) (A) +#define _IQ6toIQ(A) (A) +#define _IQ5toIQ(A) (A) +#define _IQ4toIQ(A) (A) +#define _IQ3toIQ(A) (A) +#define _IQ2toIQ(A) (A) +#define _IQ1toIQ(A) (A) +//--------------------------------------------------------------------------- +#define _IQtoQ15(A) (int) ((A) * 32768.0) +#define _IQtoQ14(A) (int) ((A) * 16384.0) +#define _IQtoQ13(A) (int) ((A) * 8192.0) +#define _IQtoQ12(A) (int) ((A) * 4096.0) +#define _IQtoQ11(A) (int) ((A) * 2048.0) +#define _IQtoQ10(A) (int) ((A) * 1024.0) +#define _IQtoQ9(A) (int) ((A) * 512.0) +#define _IQtoQ8(A) (int) ((A) * 256.0) +#define _IQtoQ7(A) (int) ((A) * 128.0) +#define _IQtoQ6(A) (int) ((A) * 64.0) +#define _IQtoQ5(A) (int) ((A) * 32.0) +#define _IQtoQ4(A) (int) ((A) * 16.0) +#define _IQtoQ3(A) (int) ((A) * 8.0) +#define _IQtoQ2(A) (int) ((A) * 4.0) +#define _IQtoQ1(A) (int) ((A) * 2.0) + +//--------------------------------------------------------------------------- +#define _Q15toIQ(A) (((float) (A)) * 0.000030518) +#define _Q14toIQ(A) (((float) (A)) * 0.000061035) +#define _Q13toIQ(A) (((float) (A)) * 0.000122070) +#define _Q12toIQ(A) (((float) (A)) * 0.000244141) +#define _Q11toIQ(A) (((float) (A)) * 0.000488281) +#define _Q10toIQ(A) (((float) (A)) * 0.000976563) +#define _Q9toIQ(A) (((float) (A)) * 0.001953125) +#define _Q8toIQ(A) (((float) (A)) * 0.003906250) +#define _Q7toIQ(A) (((float) (A)) * 0.007812500) +#define _Q6toIQ(A) (((float) (A)) * 0.015625000) +#define _Q5toIQ(A) (((float) (A)) * 0.031250000) +#define _Q4toIQ(A) (((float) (A)) * 0.062500000) +#define _Q3toIQ(A) (((float) (A)) * 0.125000000) +#define _Q2toIQ(A) (((float) (A)) * 0.250000000) +#define _Q1toIQ(A) (((float) (A)) * 0.500000000) +//--------------------------------------------------------------------------- +#define _IQmpy(A,B) ((A) * (B)) +#define _IQ30mpy(A,B) ((A) * (B)) +#define _IQ29mpy(A,B) ((A) * (B)) +#define _IQ28mpy(A,B) ((A) * (B)) +#define _IQ27mpy(A,B) ((A) * (B)) +#define _IQ26mpy(A,B) ((A) * (B)) +#define _IQ25mpy(A,B) ((A) * (B)) +#define _IQ24mpy(A,B) ((A) * (B)) +#define _IQ23mpy(A,B) ((A) * (B)) +#define _IQ22mpy(A,B) ((A) * (B)) +#define _IQ21mpy(A,B) ((A) * (B)) +#define _IQ20mpy(A,B) ((A) * (B)) +#define _IQ19mpy(A,B) ((A) * (B)) +#define _IQ18mpy(A,B) ((A) * (B)) +#define _IQ17mpy(A,B) ((A) * (B)) +#define _IQ16mpy(A,B) ((A) * (B)) +#define _IQ15mpy(A,B) ((A) * (B)) +#define _IQ14mpy(A,B) ((A) * (B)) +#define _IQ13mpy(A,B) ((A) * (B)) +#define _IQ12mpy(A,B) ((A) * (B)) +#define _IQ11mpy(A,B) ((A) * (B)) +#define _IQ10mpy(A,B) ((A) * (B)) +#define _IQ9mpy(A,B) ((A) * (B)) +#define _IQ8mpy(A,B) ((A) * (B)) +#define _IQ7mpy(A,B) ((A) * (B)) +#define _IQ6mpy(A,B) ((A) * (B)) +#define _IQ5mpy(A,B) ((A) * (B)) +#define _IQ4mpy(A,B) ((A) * (B)) +#define _IQ3mpy(A,B) ((A) * (B)) +#define _IQ2mpy(A,B) ((A) * (B)) +#define _IQ1mpy(A,B) ((A) * (B)) +//--------------------------------------------------------------------------- +#define _IQrmpy(A,B) ((A) * (B)) +#define _IQ30rmpy(A,B) ((A) * (B)) +#define _IQ29rmpy(A,B) ((A) * (B)) +#define _IQ28rmpy(A,B) ((A) * (B)) +#define _IQ27rmpy(A,B) ((A) * (B)) +#define _IQ26rmpy(A,B) ((A) * (B)) +#define _IQ25rmpy(A,B) ((A) * (B)) +#define _IQ24rmpy(A,B) ((A) * (B)) +#define _IQ23rmpy(A,B) ((A) * (B)) +#define _IQ22rmpy(A,B) ((A) * (B)) +#define _IQ21rmpy(A,B) ((A) * (B)) +#define _IQ20rmpy(A,B) ((A) * (B)) +#define _IQ19rmpy(A,B) ((A) * (B)) +#define _IQ18rmpy(A,B) ((A) * (B)) +#define _IQ17rmpy(A,B) ((A) * (B)) +#define _IQ16rmpy(A,B) ((A) * (B)) +#define _IQ15rmpy(A,B) ((A) * (B)) +#define _IQ14rmpy(A,B) ((A) * (B)) +#define _IQ13rmpy(A,B) ((A) * (B)) +#define _IQ12rmpy(A,B) ((A) * (B)) +#define _IQ11rmpy(A,B) ((A) * (B)) +#define _IQ10rmpy(A,B) ((A) * (B)) +#define _IQ9rmpy(A,B) ((A) * (B)) +#define _IQ8rmpy(A,B) ((A) * (B)) +#define _IQ7rmpy(A,B) ((A) * (B)) +#define _IQ6rmpy(A,B) ((A) * (B)) +#define _IQ5rmpy(A,B) ((A) * (B)) +#define _IQ4rmpy(A,B) ((A) * (B)) +#define _IQ3rmpy(A,B) ((A) * (B)) +#define _IQ2rmpy(A,B) ((A) * (B)) +#define _IQ1rmpy(A,B) ((A) * (B)) +//--------------------------------------------------------------------------- +#define _IQrsmpy(A,B) ((A) * (B)) +#define _IQ30rsmpy(A,B) ((A) * (B)) +#define _IQ29rsmpy(A,B) ((A) * (B)) +#define _IQ28rsmpy(A,B) ((A) * (B)) +#define _IQ27rsmpy(A,B) ((A) * (B)) +#define _IQ26rsmpy(A,B) ((A) * (B)) +#define _IQ25rsmpy(A,B) ((A) * (B)) +#define _IQ24rsmpy(A,B) ((A) * (B)) +#define _IQ23rsmpy(A,B) ((A) * (B)) +#define _IQ22rsmpy(A,B) ((A) * (B)) +#define _IQ21rsmpy(A,B) ((A) * (B)) +#define _IQ20rsmpy(A,B) ((A) * (B)) +#define _IQ19rsmpy(A,B) ((A) * (B)) +#define _IQ18rsmpy(A,B) ((A) * (B)) +#define _IQ17rsmpy(A,B) ((A) * (B)) +#define _IQ16rsmpy(A,B) ((A) * (B)) +#define _IQ15rsmpy(A,B) ((A) * (B)) +#define _IQ14rsmpy(A,B) ((A) * (B)) +#define _IQ13rsmpy(A,B) ((A) * (B)) +#define _IQ12rsmpy(A,B) ((A) * (B)) +#define _IQ11rsmpy(A,B) ((A) * (B)) +#define _IQ10rsmpy(A,B) ((A) * (B)) +#define _IQ9rsmpy(A,B) ((A) * (B)) +#define _IQ8rsmpy(A,B) ((A) * (B)) +#define _IQ7rsmpy(A,B) ((A) * (B)) +#define _IQ6rsmpy(A,B) ((A) * (B)) +#define _IQ5rsmpy(A,B) ((A) * (B)) +#define _IQ4rsmpy(A,B) ((A) * (B)) +#define _IQ3rsmpy(A,B) ((A) * (B)) +#define _IQ2rsmpy(A,B) ((A) * (B)) +#define _IQ1rsmpy(A,B) ((A) * (B)) +//--------------------------------------------------------------------------- +#define _IQdiv(A,B) ((float)(A) / (float)(B)) +#define _IQ30div(A,B) ((float)(A) / (float)(B)) +#define _IQ29div(A,B) ((float)(A) / (float)(B)) +#define _IQ28div(A,B) ((float)(A) / (float)(B)) +#define _IQ27div(A,B) ((float)(A) / (float)(B)) +#define _IQ26div(A,B) ((float)(A) / (float)(B)) +#define _IQ25div(A,B) ((float)(A) / (float)(B)) +#define _IQ24div(A,B) ((float)(A) / (float)(B)) +#define _IQ23div(A,B) ((float)(A) / (float)(B)) +#define _IQ22div(A,B) ((float)(A) / (float)(B)) +#define _IQ21div(A,B) ((float)(A) / (float)(B)) +#define _IQ20div(A,B) ((float)(A) / (float)(B)) +#define _IQ19div(A,B) ((float)(A) / (float)(B)) +#define _IQ18div(A,B) ((float)(A) / (float)(B)) +#define _IQ17div(A,B) ((float)(A) / (float)(B)) +#define _IQ16div(A,B) ((float)(A) / (float)(B)) +#define _IQ15div(A,B) ((float)(A) / (float)(B)) +#define _IQ14div(A,B) ((float)(A) / (float)(B)) +#define _IQ13div(A,B) ((float)(A) / (float)(B)) +#define _IQ12div(A,B) ((float)(A) / (float)(B)) +#define _IQ11div(A,B) ((float)(A) / (float)(B)) +#define _IQ10div(A,B) ((float)(A) / (float)(B)) +#define _IQ9div(A,B) ((float)(A) / (float)(B)) +#define _IQ8div(A,B) ((float)(A) / (float)(B)) +#define _IQ7div(A,B) ((float)(A) / (float)(B)) +#define _IQ6div(A,B) ((float)(A) / (float)(B)) +#define _IQ5div(A,B) ((float)(A) / (float)(B)) +#define _IQ4div(A,B) ((float)(A) / (float)(B)) +#define _IQ3div(A,B) ((float)(A) / (float)(B)) +#define _IQ2div(A,B) ((float)(A) / (float)(B)) +#define _IQ1div(A,B) ((float)(A) / (float)(B)) +//--------------------------------------------------------------------------- +#define _IQsin(A) sin(A) +#define _IQ30sin(A) sin(A) +#define _IQ29sin(A) sin(A) +#define _IQ28sin(A) sin(A) +#define _IQ27sin(A) sin(A) +#define _IQ26sin(A) sin(A) +#define _IQ25sin(A) sin(A) +#define _IQ24sin(A) sin(A) +#define _IQ23sin(A) sin(A) +#define _IQ22sin(A) sin(A) +#define _IQ21sin(A) sin(A) +#define _IQ20sin(A) sin(A) +#define _IQ19sin(A) sin(A) +#define _IQ18sin(A) sin(A) +#define _IQ17sin(A) sin(A) +#define _IQ16sin(A) sin(A) +#define _IQ15sin(A) sin(A) +#define _IQ14sin(A) sin(A) +#define _IQ13sin(A) sin(A) +#define _IQ12sin(A) sin(A) +#define _IQ11sin(A) sin(A) +#define _IQ10sin(A) sin(A) +#define _IQ9sin(A) sin(A) +#define _IQ8sin(A) sin(A) +#define _IQ7sin(A) sin(A) +#define _IQ6sin(A) sin(A) +#define _IQ5sin(A) sin(A) +#define _IQ4sin(A) sin(A) +#define _IQ3sin(A) sin(A) +#define _IQ2sin(A) sin(A) +#define _IQ1sin(A) sin(A) +//--------------------------------------------------------------------------- +#define _IQsinPU(A) sin((A)*6.283185307) +#define _IQ30sinPU(A) sin((A)*6.283185307) +#define _IQ29sinPU(A) sin((A)*6.283185307) +#define _IQ28sinPU(A) sin((A)*6.283185307) +#define _IQ27sinPU(A) sin((A)*6.283185307) +#define _IQ26sinPU(A) sin((A)*6.283185307) +#define _IQ25sinPU(A) sin((A)*6.283185307) +#define _IQ24sinPU(A) sin((A)*6.283185307) +#define _IQ23sinPU(A) sin((A)*6.283185307) +#define _IQ22sinPU(A) sin((A)*6.283185307) +#define _IQ21sinPU(A) sin((A)*6.283185307) +#define _IQ20sinPU(A) sin((A)*6.283185307) +#define _IQ19sinPU(A) sin((A)*6.283185307) +#define _IQ18sinPU(A) sin((A)*6.283185307) +#define _IQ17sinPU(A) sin((A)*6.283185307) +#define _IQ16sinPU(A) sin((A)*6.283185307) +#define _IQ15sinPU(A) sin((A)*6.283185307) +#define _IQ14sinPU(A) sin((A)*6.283185307) +#define _IQ13sinPU(A) sin((A)*6.283185307) +#define _IQ12sinPU(A) sin((A)*6.283185307) +#define _IQ11sinPU(A) sin((A)*6.283185307) +#define _IQ10sinPU(A) sin((A)*6.283185307) +#define _IQ9sinPU(A) sin((A)*6.283185307) +#define _IQ8sinPU(A) sin((A)*6.283185307) +#define _IQ7sinPU(A) sin((A)*6.283185307) +#define _IQ6sinPU(A) sin((A)*6.283185307) +#define _IQ5sinPU(A) sin((A)*6.283185307) +#define _IQ4sinPU(A) sin((A)*6.283185307) +#define _IQ3sinPU(A) sin((A)*6.283185307) +#define _IQ2sinPU(A) sin((A)*6.283185307) +#define _IQ1sinPU(A) sin((A)*6.283185307) +//--------------------------------------------------------------------------- +#define _IQasin(A) asin(A) +#define _IQ29asin(A) asin(A) +#define _IQ28asin(A) asin(A) +#define _IQ27asin(A) asin(A) +#define _IQ26asin(A) asin(A) +#define _IQ25asin(A) asin(A) +#define _IQ24asin(A) asin(A) +#define _IQ23asin(A) asin(A) +#define _IQ22asin(A) asin(A) +#define _IQ21asin(A) asin(A) +#define _IQ20asin(A) asin(A) +#define _IQ19asin(A) asin(A) +#define _IQ18asin(A) asin(A) +#define _IQ17asin(A) asin(A) +#define _IQ16asin(A) asin(A) +#define _IQ15asin(A) asin(A) +#define _IQ14asin(A) asin(A) +#define _IQ13asin(A) asin(A) +#define _IQ12asin(A) asin(A) +#define _IQ11asin(A) asin(A) +#define _IQ10asin(A) asin(A) +#define _IQ9asin(A) asin(A) +#define _IQ8asin(A) asin(A) +#define _IQ7asin(A) asin(A) +#define _IQ6asin(A) asin(A) +#define _IQ5asin(A) asin(A) +#define _IQ4asin(A) asin(A) +#define _IQ3asin(A) asin(A) +#define _IQ2asin(A) asin(A) +#define _IQ1asin(A) asin(A) +//--------------------------------------------------------------------------- +#define _IQcos(A) cos(A) +#define _IQ30cos(A) cos(A) +#define _IQ29cos(A) cos(A) +#define _IQ28cos(A) cos(A) +#define _IQ27cos(A) cos(A) +#define _IQ26cos(A) cos(A) +#define _IQ25cos(A) cos(A) +#define _IQ24cos(A) cos(A) +#define _IQ23cos(A) cos(A) +#define _IQ22cos(A) cos(A) +#define _IQ21cos(A) cos(A) +#define _IQ20cos(A) cos(A) +#define _IQ19cos(A) cos(A) +#define _IQ18cos(A) cos(A) +#define _IQ17cos(A) cos(A) +#define _IQ16cos(A) cos(A) +#define _IQ15cos(A) cos(A) +#define _IQ14cos(A) cos(A) +#define _IQ13cos(A) cos(A) +#define _IQ12cos(A) cos(A) +#define _IQ11cos(A) cos(A) +#define _IQ10cos(A) cos(A) +#define _IQ9cos(A) cos(A) +#define _IQ8cos(A) cos(A) +#define _IQ7cos(A) cos(A) +#define _IQ6cos(A) cos(A) +#define _IQ5cos(A) cos(A) +#define _IQ4cos(A) cos(A) +#define _IQ3cos(A) cos(A) +#define _IQ2cos(A) cos(A) +#define _IQ1cos(A) cos(A) +//--------------------------------------------------------------------------- +#define _IQcosPU(A) cos((A)*6.283185307) +#define _IQ30cosPU(A) cos((A)*6.283185307) +#define _IQ29cosPU(A) cos((A)*6.283185307) +#define _IQ28cosPU(A) cos((A)*6.283185307) +#define _IQ27cosPU(A) cos((A)*6.283185307) +#define _IQ26cosPU(A) cos((A)*6.283185307) +#define _IQ25cosPU(A) cos((A)*6.283185307) +#define _IQ24cosPU(A) cos((A)*6.283185307) +#define _IQ23cosPU(A) cos((A)*6.283185307) +#define _IQ22cosPU(A) cos((A)*6.283185307) +#define _IQ21cosPU(A) cos((A)*6.283185307) +#define _IQ20cosPU(A) cos((A)*6.283185307) +#define _IQ19cosPU(A) cos((A)*6.283185307) +#define _IQ18cosPU(A) cos((A)*6.283185307) +#define _IQ17cosPU(A) cos((A)*6.283185307) +#define _IQ16cosPU(A) cos((A)*6.283185307) +#define _IQ15cosPU(A) cos((A)*6.283185307) +#define _IQ14cosPU(A) cos((A)*6.283185307) +#define _IQ13cosPU(A) cos((A)*6.283185307) +#define _IQ12cosPU(A) cos((A)*6.283185307) +#define _IQ11cosPU(A) cos((A)*6.283185307) +#define _IQ10cosPU(A) cos((A)*6.283185307) +#define _IQ9cosPU(A) cos((A)*6.283185307) +#define _IQ8cosPU(A) cos((A)*6.283185307) +#define _IQ7cosPU(A) cos((A)*6.283185307) +#define _IQ6cosPU(A) cos((A)*6.283185307) +#define _IQ5cosPU(A) cos((A)*6.283185307) +#define _IQ4cosPU(A) cos((A)*6.283185307) +#define _IQ3cosPU(A) cos((A)*6.283185307) +#define _IQ2cosPU(A) cos((A)*6.283185307) +#define _IQ1cosPU(A) cos((A)*6.283185307) +//--------------------------------------------------------------------------- +#define _IQacos(A) acos(A) +#define _IQ29acos(A) acos(A) +#define _IQ28acos(A) acos(A) +#define _IQ27acos(A) acos(A) +#define _IQ26acos(A) acos(A) +#define _IQ25acos(A) acos(A) +#define _IQ24acos(A) acos(A) +#define _IQ23acos(A) acos(A) +#define _IQ22acos(A) acos(A) +#define _IQ21acos(A) acos(A) +#define _IQ20acos(A) acos(A) +#define _IQ19acos(A) acos(A) +#define _IQ18acos(A) acos(A) +#define _IQ17acos(A) acos(A) +#define _IQ16acos(A) acos(A) +#define _IQ15acos(A) acos(A) +#define _IQ14acos(A) acos(A) +#define _IQ13acos(A) acos(A) +#define _IQ12acos(A) acos(A) +#define _IQ11acos(A) acos(A) +#define _IQ10acos(A) acos(A) +#define _IQ9acos(A) acos(A) +#define _IQ8acos(A) acos(A) +#define _IQ7acos(A) acos(A) +#define _IQ6acos(A) acos(A) +#define _IQ5acos(A) acos(A) +#define _IQ4acos(A) acos(A) +#define _IQ3acos(A) acos(A) +#define _IQ2acos(A) acos(A) +#define _IQ1acos(A) acos(A) +//--------------------------------------------------------------------------- +#define _IQatan(A) atan(A) +#define _IQ30atan(A) atan(A) +#define _IQ29atan(A) atan(A) +#define _IQ28atan(A) atan(A) +#define _IQ27atan(A) atan(A) +#define _IQ26atan(A) atan(A) +#define _IQ25atan(A) atan(A) +#define _IQ24atan(A) atan(A) +#define _IQ23atan(A) atan(A) +#define _IQ22atan(A) atan(A) +#define _IQ21atan(A) atan(A) +#define _IQ20atan(A) atan(A) +#define _IQ19atan(A) atan(A) +#define _IQ18atan(A) atan(A) +#define _IQ17atan(A) atan(A) +#define _IQ16atan(A) atan(A) +#define _IQ15atan(A) atan(A) +#define _IQ14atan(A) atan(A) +#define _IQ13atan(A) atan(A) +#define _IQ12atan(A) atan(A) +#define _IQ11atan(A) atan(A) +#define _IQ10atan(A) atan(A) +#define _IQ9atan(A) atan(A) +#define _IQ8atan(A) atan(A) +#define _IQ7atan(A) atan(A) +#define _IQ6atan(A) atan(A) +#define _IQ5atan(A) atan(A) +#define _IQ4atan(A) atan(A) +#define _IQ3atan(A) atan(A) +#define _IQ2atan(A) atan(A) +#define _IQ1atan(A) atan(A) +//--------------------------------------------------------------------------- +#define _IQatan2(A,B) atan2(A,B) +#define _IQ30atan2(A,B) atan2(A,B) +#define _IQ29atan2(A,B) atan2(A,B) +#define _IQ28atan2(A,B) atan2(A,B) +#define _IQ27atan2(A,B) atan2(A,B) +#define _IQ26atan2(A,B) atan2(A,B) +#define _IQ25atan2(A,B) atan2(A,B) +#define _IQ24atan2(A,B) atan2(A,B) +#define _IQ23atan2(A,B) atan2(A,B) +#define _IQ22atan2(A,B) atan2(A,B) +#define _IQ21atan2(A,B) atan2(A,B) +#define _IQ20atan2(A,B) atan2(A,B) +#define _IQ19atan2(A,B) atan2(A,B) +#define _IQ18atan2(A,B) atan2(A,B) +#define _IQ17atan2(A,B) atan2(A,B) +#define _IQ16atan2(A,B) atan2(A,B) +#define _IQ15atan2(A,B) atan2(A,B) +#define _IQ14atan2(A,B) atan2(A,B) +#define _IQ13atan2(A,B) atan2(A,B) +#define _IQ12atan2(A,B) atan2(A,B) +#define _IQ11atan2(A,B) atan2(A,B) +#define _IQ10atan2(A,B) atan2(A,B) +#define _IQ9atan2(A,B) atan2(A,B) +#define _IQ8atan2(A,B) atan2(A,B) +#define _IQ7atan2(A,B) atan2(A,B) +#define _IQ6atan2(A,B) atan2(A,B) +#define _IQ5atan2(A,B) atan2(A,B) +#define _IQ4atan2(A,B) atan2(A,B) +#define _IQ3atan2(A,B) atan2(A,B) +#define _IQ2atan2(A,B) atan2(A,B) +#define _IQ1atan2(A,B) atan2(A,B) +//--------------------------------------------------------------------------- +#define _IQatan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ30atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ29atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ28atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ27atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ26atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ25atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ24atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ23atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ22atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ21atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ20atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ19atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ18atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ17atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ16atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ15atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ14atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ13atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ12atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ11atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ10atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ9atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ8atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ7atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ6atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ5atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ4atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ3atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ2atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +#define _IQ1atan2PU(A,B) ((atan2(A,B)*(1.0/6.283185307)) >= 0.0 ? (atan2(A,B)*(1.0/6.283185307)):1.0 + (atan2(A,B)*(1.0/6.283185307))) +//--------------------------------------------------------------------------- +#define _IQsqrt(A) sqrt(A) +#define _IQ30sqrt(A) sqrt(A) +#define _IQ29sqrt(A) sqrt(A) +#define _IQ28sqrt(A) sqrt(A) +#define _IQ27sqrt(A) sqrt(A) +#define _IQ26sqrt(A) sqrt(A) +#define _IQ25sqrt(A) sqrt(A) +#define _IQ24sqrt(A) sqrt(A) +#define _IQ23sqrt(A) sqrt(A) +#define _IQ22sqrt(A) sqrt(A) +#define _IQ21sqrt(A) sqrt(A) +#define _IQ20sqrt(A) sqrt(A) +#define _IQ19sqrt(A) sqrt(A) +#define _IQ18sqrt(A) sqrt(A) +#define _IQ17sqrt(A) sqrt(A) +#define _IQ16sqrt(A) sqrt(A) +#define _IQ15sqrt(A) sqrt(A) +#define _IQ14sqrt(A) sqrt(A) +#define _IQ13sqrt(A) sqrt(A) +#define _IQ12sqrt(A) sqrt(A) +#define _IQ11sqrt(A) sqrt(A) +#define _IQ10sqrt(A) sqrt(A) +#define _IQ9sqrt(A) sqrt(A) +#define _IQ8sqrt(A) sqrt(A) +#define _IQ7sqrt(A) sqrt(A) +#define _IQ6sqrt(A) sqrt(A) +#define _IQ5sqrt(A) sqrt(A) +#define _IQ4sqrt(A) sqrt(A) +#define _IQ3sqrt(A) sqrt(A) +#define _IQ2sqrt(A) sqrt(A) +#define _IQ1sqrt(A) sqrt(A) +//--------------------------------------------------------------------------- +#define _IQisqrt(A) (1.0/sqrt(A)) +#define _IQ30isqrt(A) (1.0/sqrt(A)) +#define _IQ29isqrt(A) (1.0/sqrt(A)) +#define _IQ28isqrt(A) (1.0/sqrt(A)) +#define _IQ27isqrt(A) (1.0/sqrt(A)) +#define _IQ26isqrt(A) (1.0/sqrt(A)) +#define _IQ25isqrt(A) (1.0/sqrt(A)) +#define _IQ24isqrt(A) (1.0/sqrt(A)) +#define _IQ23isqrt(A) (1.0/sqrt(A)) +#define _IQ22isqrt(A) (1.0/sqrt(A)) +#define _IQ21isqrt(A) (1.0/sqrt(A)) +#define _IQ20isqrt(A) (1.0/sqrt(A)) +#define _IQ19isqrt(A) (1.0/sqrt(A)) +#define _IQ18isqrt(A) (1.0/sqrt(A)) +#define _IQ17isqrt(A) (1.0/sqrt(A)) +#define _IQ16isqrt(A) (1.0/sqrt(A)) +#define _IQ15isqrt(A) (1.0/sqrt(A)) +#define _IQ14isqrt(A) (1.0/sqrt(A)) +#define _IQ13isqrt(A) (1.0/sqrt(A)) +#define _IQ12isqrt(A) (1.0/sqrt(A)) +#define _IQ11isqrt(A) (1.0/sqrt(A)) +#define _IQ10isqrt(A) (1.0/sqrt(A)) +#define _IQ9isqrt(A) (1.0/sqrt(A)) +#define _IQ8isqrt(A) (1.0/sqrt(A)) +#define _IQ7isqrt(A) (1.0/sqrt(A)) +#define _IQ6isqrt(A) (1.0/sqrt(A)) +#define _IQ5isqrt(A) (1.0/sqrt(A)) +#define _IQ4isqrt(A) (1.0/sqrt(A)) +#define _IQ3isqrt(A) (1.0/sqrt(A)) +#define _IQ2isqrt(A) (1.0/sqrt(A)) +#define _IQ1isqrt(A) (1.0/sqrt(A)) +//--------------------------------------------------------------------------- +#define _IQexp(A) exp(A) +#define _IQ30exp(A) exp(A) +#define _IQ29exp(A) exp(A) +#define _IQ28exp(A) exp(A) +#define _IQ27exp(A) exp(A) +#define _IQ26exp(A) exp(A) +#define _IQ25exp(A) exp(A) +#define _IQ24exp(A) exp(A) +#define _IQ23exp(A) exp(A) +#define _IQ22exp(A) exp(A) +#define _IQ21exp(A) exp(A) +#define _IQ20exp(A) exp(A) +#define _IQ19exp(A) exp(A) +#define _IQ18exp(A) exp(A) +#define _IQ17exp(A) exp(A) +#define _IQ16exp(A) exp(A) +#define _IQ15exp(A) exp(A) +#define _IQ14exp(A) exp(A) +#define _IQ13exp(A) exp(A) +#define _IQ12exp(A) exp(A) +#define _IQ11exp(A) exp(A) +#define _IQ10exp(A) exp(A) +#define _IQ9exp(A) exp(A) +#define _IQ8exp(A) exp(A) +#define _IQ7exp(A) exp(A) +#define _IQ6exp(A) exp(A) +#define _IQ5exp(A) exp(A) +#define _IQ4exp(A) exp(A) +#define _IQ3exp(A) exp(A) +#define _IQ2exp(A) exp(A) +#define _IQ1exp(A) exp(A) +//--------------------------------------------------------------------------- +#define _IQint(A) ((long) (A)) +#define _IQ30int(A) ((long) (A)) +#define _IQ29int(A) ((long) (A)) +#define _IQ28int(A) ((long) (A)) +#define _IQ27int(A) ((long) (A)) +#define _IQ26int(A) ((long) (A)) +#define _IQ25int(A) ((long) (A)) +#define _IQ24int(A) ((long) (A)) +#define _IQ23int(A) ((long) (A)) +#define _IQ22int(A) ((long) (A)) +#define _IQ21int(A) ((long) (A)) +#define _IQ20int(A) ((long) (A)) +#define _IQ19int(A) ((long) (A)) +#define _IQ18int(A) ((long) (A)) +#define _IQ17int(A) ((long) (A)) +#define _IQ16int(A) ((long) (A)) +#define _IQ15int(A) ((long) (A)) +#define _IQ14int(A) ((long) (A)) +#define _IQ13int(A) ((long) (A)) +#define _IQ12int(A) ((long) (A)) +#define _IQ11int(A) ((long) (A)) +#define _IQ10int(A) ((long) (A)) +#define _IQ9int(A) ((long) (A)) +#define _IQ8int(A) ((long) (A)) +#define _IQ7int(A) ((long) (A)) +#define _IQ6int(A) ((long) (A)) +#define _IQ5int(A) ((long) (A)) +#define _IQ4int(A) ((long) (A)) +#define _IQ3int(A) ((long) (A)) +#define _IQ2int(A) ((long) (A)) +#define _IQ1int(A) ((long) (A)) +//--------------------------------------------------------------------------- +#define _IQfrac(A) ((A) - (float)((long) (A))) +#define _IQ30frac(A) ((A) - (float)((long) (A))) +#define _IQ29frac(A) ((A) - (float)((long) (A))) +#define _IQ28frac(A) ((A) - (float)((long) (A))) +#define _IQ27frac(A) ((A) - (float)((long) (A))) +#define _IQ26frac(A) ((A) - (float)((long) (A))) +#define _IQ25frac(A) ((A) - (float)((long) (A))) +#define _IQ24frac(A) ((A) - (float)((long) (A))) +#define _IQ23frac(A) ((A) - (float)((long) (A))) +#define _IQ22frac(A) ((A) - (float)((long) (A))) +#define _IQ21frac(A) ((A) - (float)((long) (A))) +#define _IQ20frac(A) ((A) - (float)((long) (A))) +#define _IQ19frac(A) ((A) - (float)((long) (A))) +#define _IQ18frac(A) ((A) - (float)((long) (A))) +#define _IQ17frac(A) ((A) - (float)((long) (A))) +#define _IQ16frac(A) ((A) - (float)((long) (A))) +#define _IQ15frac(A) ((A) - (float)((long) (A))) +#define _IQ14frac(A) ((A) - (float)((long) (A))) +#define _IQ13frac(A) ((A) - (float)((long) (A))) +#define _IQ12frac(A) ((A) - (float)((long) (A))) +#define _IQ11frac(A) ((A) - (float)((long) (A))) +#define _IQ10frac(A) ((A) - (float)((long) (A))) +#define _IQ9frac(A) ((A) - (float)((long) (A))) +#define _IQ8frac(A) ((A) - (float)((long) (A))) +#define _IQ7frac(A) ((A) - (float)((long) (A))) +#define _IQ6frac(A) ((A) - (float)((long) (A))) +#define _IQ5frac(A) ((A) - (float)((long) (A))) +#define _IQ4frac(A) ((A) - (float)((long) (A))) +#define _IQ3frac(A) ((A) - (float)((long) (A))) +#define _IQ2frac(A) ((A) - (float)((long) (A))) +#define _IQ1frac(A) ((A) - (float)((long) (A))) +//--------------------------------------------------------------------------- +#define _IQmpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ30mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ29mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ28mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ27mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ26mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ25mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ24mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ23mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ22mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ21mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ20mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ19mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ18mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ17mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ16mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ15mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ14mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ13mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ12mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ11mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ10mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ9mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ8mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ7mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ6mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ5mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ4mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ3mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ2mpyIQX(A, IQA, B, IQB) ((A)*(B)) +#define _IQ1mpyIQX(A, IQA, B, IQB) ((A)*(B)) +//--------------------------------------------------------------------------- +#define _IQmpyI32(A,B) ((A) * (float) (B)) +#define _IQ30mpyI32(A,B) ((A) * (float) (B)) +#define _IQ29mpyI32(A,B) ((A) * (float) (B)) +#define _IQ28mpyI32(A,B) ((A) * (float) (B)) +#define _IQ27mpyI32(A,B) ((A) * (float) (B)) +#define _IQ26mpyI32(A,B) ((A) * (float) (B)) +#define _IQ25mpyI32(A,B) ((A) * (float) (B)) +#define _IQ24mpyI32(A,B) ((A) * (float) (B)) +#define _IQ23mpyI32(A,B) ((A) * (float) (B)) +#define _IQ22mpyI32(A,B) ((A) * (float) (B)) +#define _IQ21mpyI32(A,B) ((A) * (float) (B)) +#define _IQ20mpyI32(A,B) ((A) * (float) (B)) +#define _IQ19mpyI32(A,B) ((A) * (float) (B)) +#define _IQ18mpyI32(A,B) ((A) * (float) (B)) +#define _IQ17mpyI32(A,B) ((A) * (float) (B)) +#define _IQ16mpyI32(A,B) ((A) * (float) (B)) +#define _IQ15mpyI32(A,B) ((A) * (float) (B)) +#define _IQ14mpyI32(A,B) ((A) * (float) (B)) +#define _IQ13mpyI32(A,B) ((A) * (float) (B)) +#define _IQ12mpyI32(A,B) ((A) * (float) (B)) +#define _IQ11mpyI32(A,B) ((A) * (float) (B)) +#define _IQ10mpyI32(A,B) ((A) * (float) (B)) +#define _IQ9mpyI32(A,B) ((A) * (float) (B)) +#define _IQ8mpyI32(A,B) ((A) * (float) (B)) +#define _IQ7mpyI32(A,B) ((A) * (float) (B)) +#define _IQ6mpyI32(A,B) ((A) * (float) (B)) +#define _IQ5mpyI32(A,B) ((A) * (float) (B)) +#define _IQ4mpyI32(A,B) ((A) * (float) (B)) +#define _IQ3mpyI32(A,B) ((A) * (float) (B)) +#define _IQ2mpyI32(A,B) ((A) * (float) (B)) +#define _IQ1mpyI32(A,B) ((A) * (float) (B)) +//--------------------------------------------------------------------------- +#define _IQmpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ30mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ29mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ28mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ27mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ26mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ25mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ24mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ23mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ22mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ21mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ20mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ19mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ18mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ17mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ16mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ15mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ14mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ13mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ12mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ11mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ10mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ9mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ8mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ7mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ6mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ5mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ4mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ3mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ2mpyI32int(A,B) ((long) ((A) * (float) (B))) +#define _IQ1mpyI32int(A,B) ((long) ((A) * (float) (B))) +//--------------------------------------------------------------------------- +#define _IQmpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ30mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ29mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ28mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ27mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ26mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ25mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ24mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ23mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ22mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ21mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ20mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ19mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ18mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ17mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ16mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ15mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ14mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ13mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ12mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ11mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ10mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ9mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ8mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ7mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ6mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ5mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ4mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ3mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ2mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +#define _IQ1mpyI32frac(A,B) ((A) - (float)((long) ((A) * (float) (B)))) +//--------------------------------------------------------------------------- +#define _IQmag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ30mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ29mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ28mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ27mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ26mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ25mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ24mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ23mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ22mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ21mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ20mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ19mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ18mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ17mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ16mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ15mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ14mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ13mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ12mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ11mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ10mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ9mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ8mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ7mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ6mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ5mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ4mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ3mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ2mag(A,B) sqrt((A)*(A) + (B)*(B)) +#define _IQ1mag(A,B) sqrt((A)*(A) + (B)*(B)) +//--------------------------------------------------------------------------- +#define _atoIQ(A) atof(A) +#define _atoIQ30(A) atof(A) +#define _atoIQ29(A) atof(A) +#define _atoIQ28(A) atof(A) +#define _atoIQ27(A) atof(A) +#define _atoIQ26(A) atof(A) +#define _atoIQ25(A) atof(A) +#define _atoIQ24(A) atof(A) +#define _atoIQ23(A) atof(A) +#define _atoIQ22(A) atof(A) +#define _atoIQ21(A) atof(A) +#define _atoIQ20(A) atof(A) +#define _atoIQ19(A) atof(A) +#define _atoIQ18(A) atof(A) +#define _atoIQ17(A) atof(A) +#define _atoIQ16(A) atof(A) +#define _atoIQ15(A) atof(A) +#define _atoIQ14(A) atof(A) +#define _atoIQ13(A) atof(A) +#define _atoIQ12(A) atof(A) +#define _atoIQ11(A) atof(A) +#define _atoIQ10(A) atof(A) +#define _atoIQ9(A) atof(A) +#define _atoIQ8(A) atof(A) +#define _atoIQ7(A) atof(A) +#define _atoIQ6(A) atof(A) +#define _atoIQ5(A) atof(A) +#define _atoIQ4(A) atof(A) +#define _atoIQ3(A) atof(A) +#define _atoIQ2(A) atof(A) +#define _atoIQ1(A) atof(A) +//--------------------------------------------------------------------------- +#define _IQtoa(A, B, C) sprintf(A, B, C) +#define _IQ30toa(A, B, C) sprintf(A, B, C) +#define _IQ29toa(A, B, C) sprintf(A, B, C) +#define _IQ28toa(A, B, C) sprintf(A, B, C) +#define _IQ27toa(A, B, C) sprintf(A, B, C) +#define _IQ26toa(A, B, C) sprintf(A, B, C) +#define _IQ25toa(A, B, C) sprintf(A, B, C) +#define _IQ24toa(A, B, C) sprintf(A, B, C) +#define _IQ23toa(A, B, C) sprintf(A, B, C) +#define _IQ22toa(A, B, C) sprintf(A, B, C) +#define _IQ21toa(A, B, C) sprintf(A, B, C) +#define _IQ20toa(A, B, C) sprintf(A, B, C) +#define _IQ19toa(A, B, C) sprintf(A, B, C) +#define _IQ18toa(A, B, C) sprintf(A, B, C) +#define _IQ17toa(A, B, C) sprintf(A, B, C) +#define _IQ16toa(A, B, C) sprintf(A, B, C) +#define _IQ15toa(A, B, C) sprintf(A, B, C) +#define _IQ14toa(A, B, C) sprintf(A, B, C) +#define _IQ13toa(A, B, C) sprintf(A, B, C) +#define _IQ12toa(A, B, C) sprintf(A, B, C) +#define _IQ11toa(A, B, C) sprintf(A, B, C) +#define _IQ10toa(A, B, C) sprintf(A, B, C) +#define _IQ9toa(A, B, C) sprintf(A, B, C) +#define _IQ8toa(A, B, C) sprintf(A, B, C) +#define _IQ7toa(A, B, C) sprintf(A, B, C) +#define _IQ6toa(A, B, C) sprintf(A, B, C) +#define _IQ5toa(A, B, C) sprintf(A, B, C) +#define _IQ4toa(A, B, C) sprintf(A, B, C) +#define _IQ3toa(A, B, C) sprintf(A, B, C) +#define _IQ2toa(A, B, C) sprintf(A, B, C) +#define _IQ1toa(A, B, C) sprintf(A, B, C) +//--------------------------------------------------------------------------- +#define _IQabs(A) fabs(A) +#define _IQ30abs(A) fabs(A) +#define _IQ29abs(A) fabs(A) +#define _IQ28abs(A) fabs(A) +#define _IQ27abs(A) fabs(A) +#define _IQ26abs(A) fabs(A) +#define _IQ25abs(A) fabs(A) +#define _IQ24abs(A) fabs(A) +#define _IQ23abs(A) fabs(A) +#define _IQ22abs(A) fabs(A) +#define _IQ21abs(A) fabs(A) +#define _IQ20abs(A) fabs(A) +#define _IQ19abs(A) fabs(A) +#define _IQ18abs(A) fabs(A) +#define _IQ17abs(A) fabs(A) +#define _IQ16abs(A) fabs(A) +#define _IQ15abs(A) fabs(A) +#define _IQ14abs(A) fabs(A) +#define _IQ13abs(A) fabs(A) +#define _IQ12abs(A) fabs(A) +#define _IQ11abs(A) fabs(A) +#define _IQ10abs(A) fabs(A) +#define _IQ9abs(A) fabs(A) +#define _IQ8abs(A) fabs(A) +#define _IQ7abs(A) fabs(A) +#define _IQ6abs(A) fabs(A) +#define _IQ5abs(A) fabs(A) +#define _IQ4abs(A) fabs(A) +#define _IQ3abs(A) fabs(A) +#define _IQ2abs(A) fabs(A) +#define _IQ1abs(A) fabs(A) +//--------------------------------------------------------------------------- +#define _IQlog(A) log(A) +#define _IQ30log(A) log(A) +#define _IQ29log(A) log(A) +#define _IQ28log(A) log(A) +#define _IQ27log(A) log(A) +#define _IQ26log(A) log(A) +#define _IQ25log(A) log(A) +#define _IQ24log(A) log(A) +#define _IQ23log(A) log(A) +#define _IQ22log(A) log(A) +#define _IQ21log(A) log(A) +#define _IQ20log(A) log(A) +#define _IQ19log(A) log(A) +#define _IQ18log(A) log(A) +#define _IQ17log(A) log(A) +#define _IQ16log(A) log(A) +#define _IQ15log(A) log(A) +#define _IQ14log(A) log(A) +#define _IQ13log(A) log(A) +#define _IQ12log(A) log(A) +#define _IQ11log(A) log(A) +#define _IQ10log(A) log(A) +#define _IQ9log(A) log(A) +#define _IQ8log(A) log(A) +#define _IQ7log(A) log(A) +#define _IQ6log(A) log(A) +#define _IQ5log(A) log(A) +#define _IQ4log(A) log(A) +#define _IQ3log(A) log(A) +#define _IQ2log(A) log(A) +#define _IQ1log(A) log(A) +//########################################################################### +#endif // No more. +//########################################################################### + +#endif /* __IQMATHLIB_H_INCLUDED__ */ diff --git a/Inu/Src/N12_Libs/not_use/adaptive_filters.c b/Inu/Src/N12_Libs/not_use/adaptive_filters.c new file mode 100644 index 0000000..43111c7 --- /dev/null +++ b/Inu/Src/N12_Libs/not_use/adaptive_filters.c @@ -0,0 +1,626 @@ +/* + * adaptive_filters.c + * + * Created on: 24 . 2023 . + * Author: user + */ + +/* +Determining the appropriate values for the adaptive coefficients Ka and Kb in an adaptive PI +regulator requires a thorough understanding of your specific control system and motor dynamics. +The values of Ka and Kb are typically determined through a tuning process, which involves +experimentation and iteration to achieve the desired control performance. + +Here's a general approach to tuning the adaptive coefficients Ka and Kb: + +Start with small initial values: Begin with small values for Ka and Kb, such as 0.01 or 0.001. + +Observe the system behavior: Run the control system with these initial values and observe the +response of the motor. Pay attention to the speed control performance, such as overshoot, settling +time, and steady-state error. + +Adjust Ka and Kb based on the response: Increase or decrease the values of Ka and Kb based on +the observed system behavior. If the system response is slow or exhibits large overshoot, +consider increasing the values. If the system response is too aggressive or unstable, +consider decreasing the values. + +Iterate the tuning process: Repeat steps 2 and 3, adjusting Ka and Kb iteratively until you +achieve the desired control performance. It may require several iterations to find suitable +values. + +It's important to note that the tuning process is highly dependent on the specific motor +characteristics, the requirements of the control system, and the desired performance. +Therefore, it's recommended to consult motor control experts, refer to motor datasheets, or consider model-based control techniques for a more accurate tuning process. + +Additionally, advanced control techniques such as adaptive control algorithms +(e.g., Model Reference Adaptive Control or Self-Tuning Regulators) can be explored for more +advanced and precise adaptation of control parameters. + +Remember to thoroughly test and validate the tuned parameters under various operating +conditions to ensure stability and robust performance of the motor control system. + */ + +// Constants for the PI regulator +#define Kp 0.5 +#define Ki 0.2 + +// Constants for the adaptive part +#define Ka 0.05 +#define Kb 0.02 + +// Function to calculate the adaptive PI control output +float adaptivePI(float setpoint, float measured_speed, float integral_error) +{ + static float prev_error = 0.0; + static float prev_output = 0.0; + + // Calculate the error + float error = setpoint - measured_speed; + + // Calculate the integral error + integral_error += error; + + // Calculate the adaptive part + float adaptive = Ka * error + Kb * (error - prev_error); + + // Calculate the PI control output + float output = Kp * error + Ki * integral_error + adaptive; + + // Store the current error and output for the next iteration + prev_error = error; + prev_output = output; + + return output; +} + +int main1() +{ + float setpoint = 100.0; // Desired speed setpoint + float measured_speed = 85.0; // Measured speed of the motor + float integral_error = 0.0; // Integral error for the PI regulator + + // Calculate the control output using the adaptive PI regulator + float control_output = adaptivePI(setpoint, measured_speed, integral_error); + + printf("Control Output: %f\n", control_output); + + return 0; +} + + + +//////////////////////////// +/* +In this simplified example, the mracControl function implements the MRAC algorithm for motor speed control. +The function takes the desired speed reference (reference_speed), the measured speed of the motor (measured_speed), +and the adaptation parameter (adaptation_param) as inputs. It returns the control output. + +The MRAC algorithm calculates the error between the reference speed and the measured speed. It then multiplies +the error by the adaptation parameter, controller gain (Kc), and applies it as the control output. +The adaptation parameter is updated based on the derivative of the error and the adaptation rate (Lambda). + +The main function demonstrates how to use the mracControl function by providing sample values for the reference + speed, measured speed, and adaptation parameter. It calculates the control output and prints it to the console. + +Please note that this is a simplified example, and in a real-world scenario, you would need to consider +the specific motor dynamics, tuning of parameters, and implementation details based on the control +requirements of your motor system. + */ + + +// Constants for the MRAC algorithm +#define Kc 0.5 // Controller gain +#define Lambda 0.1 // Adaptation rate + +// Reference model parameters +#define Km 0.5 // Model gain +#define Tm 1.0 // Model time constant + +// Function to calculate the MRAC control output +float mracControl(float reference_speed, float measured_speed, float adaptation_param) +{ + static float control_output = 0.0; + static float prev_error = 0.0; + + // Calculate the error + float error = reference_speed - measured_speed; + + // Calculate the control output + control_output = Kc * adaptation_param * error; + + // Update the adaptation parameter + float derivative_error = (error - prev_error) / Tm; + adaptation_param += Lambda * derivative_error; + + // Store the current error for the next iteration + prev_error = error; + + return control_output; +} + +int main2() +{ + float reference_speed = 100.0; // Desired speed reference + float measured_speed = 85.0; // Measured speed of the motor + float adaptation_param = 1.0; // Initial value for the adaptation parameter + + // Calculate the MRAC control output + float control_output = mracControl(reference_speed, measured_speed, adaptation_param); + + printf("Control Output: %f\n", control_output); + + return 0; +} + + +////////////////////////////////////// + +/* + In this simplified example, the strControl function implements the STR algorithm for motor speed control. + It takes the desired speed reference (reference_speed), the measured speed of the motor (measured_speed), + and the adaptation parameter (adaptation_param) as inputs. It returns the control output. + +The STR algorithm calculates the error between the reference speed and the measured speed. +It then multiplies the error by the adaptation parameter, controller gain (Kc), and applies it as the control output. + +The updateAdaptationParam function updates the adaptation parameter based on the derivative of the error and the control output. +It calculates the derivative error by comparing the current control output and the previous control output, divided by +the difference in measured speed. The adaptation parameter is updated by adding the product of the derivative error and the adaptation rate (Lambda). + +The main function demonstrates how to use the strControl function and the updateAdaptationParam function +by providing sample values for the reference speed, measured speed, and adaptation parameter. +It calculates the control output, updates the adaptation parameter, and prints the control output to the console. + +Please note that this is a simplified example, and in a real-world scenario, you would need to consider the specific motor dynamics, +tuning of parameters, and implementation details based on the control requirements of your motor system. + + */ + + +#include + +// Constants for the STR algorithm +#define Kc 0.5 // Initial controller gain +#define Lambda 0.1 // Adaptation rate + +// Function to calculate the STR control output +float strControl(float reference_speed, float measured_speed, float adaptation_param) +{ + static float control_output = 0.0; + + // Calculate the error + float error = reference_speed - measured_speed; + + // Calculate the control output + control_output = Kc * adaptation_param * error; + + return control_output; +} + +// Function to update the adaptation parameter +float updateAdaptationParam(float adaptation_param, float measured_speed, float control_output) +{ + static float prev_error = 0.0; + static float prev_control_output = 0.0; + + // Calculate the error derivative + float derivative_error = (control_output - prev_control_output) / (measured_speed - prev_error); + + // Update the adaptation parameter + adaptation_param += Lambda * derivative_error; + + // Store the current error and control output for the next iteration + prev_error = measured_speed; + prev_control_output = control_output; + + return adaptation_param; +} + +int main3() +{ + float reference_speed = 100.0; // Desired speed reference + float measured_speed = 85.0; // Measured speed of the motor + float adaptation_param = 1.0; // Initial value for the adaptation parameter + + // Calculate the STR control output + float control_output = strControl(reference_speed, measured_speed, adaptation_param); + + // Update the adaptation parameter + adaptation_param = updateAdaptationParam(adaptation_param, measured_speed, control_output); + + printf("Control Output: %f\n", control_output); + + return 0; +} +/////////////////////// +/* +In this example, the adaptivePIControl function calculates the adaptive PI control +output based on the reference speed, measured speed, and the current values of the + proportional gain (Kp) and integral gain (Ki). The function also updates the integral term. + +The gradientDescentAdaptation function performs the gradient descent adaptation to + adjust the gains (Kp and Ki) based on the error between the reference speed and the + measured speed. It iteratively updates the gains using the gradients of the error + with respect to the gains. + +The main function demonstrates the usage of the adaptive PI control and the gradient +descent adaptation. It initializes the gains, performs the adaptation, and calculates + the control output. The control output is then printed to the console. + +Please note that this is a simplified example, and in a real-world scenario, you would + need to consider the specific motor dynamics, tuning of parameters, and implementation + details based on the control requirements of your motor system. Additionally, gradient + descent may not always be the most suitable adaptation algorithm for every situation, + and other algorithms may be more appropriate depending on the system characteristics + and control objectives. + */ + + +// Constants for the adaptive PI control +#define Kp_initial 1.0 // Initial proportional gain +#define Ki_initial 0.5 // Initial integral gain +#define Learning_rate 0.01 // Learning rate for adaptation +#define Max_iterations 1000 // Maximum number of iterations for adaptation + +// Function to calculate the adaptive PI control output +float adaptivePIControl(float reference_speed, float measured_speed, float *Kp, float *Ki) +{ + static float integral_term = 0.0; + float error = reference_speed - measured_speed; + + // Update the integral term + integral_term += error; + + // Calculate the control output + float control_output = (*Kp) * error + (*Ki) * integral_term; + + return control_output; +} + +// Function to perform gradient descent adaptation +void gradientDescentAdaptation(float reference_speed, float measured_speed, float *Kp, float *Ki) +{ + int iteration; + float error; + float Kp_gradient, Ki_gradient; + + for (iteration = 0; iteration < Max_iterations; iteration++) + { + // Calculate the error + error = reference_speed - measured_speed; + + // Calculate the gradients + Kp_gradient = error; + Ki_gradient = error; + + // Update the gains using gradient descent + *Kp += Learning_rate * Kp_gradient; + *Ki += Learning_rate * Ki_gradient; + } +} + +int main4() +{ + float reference_speed = 100.0; // Desired speed reference + float measured_speed = 85.0; // Measured speed of the motor + + // Initialize the gains + float Kp = Kp_initial; + float Ki = Ki_initial; + + // Perform gradient descent adaptation + gradientDescentAdaptation(reference_speed, measured_speed, &Kp, &Ki); + + // Calculate the adaptive PI control output + float control_output = adaptivePIControl(reference_speed, measured_speed, &Kp, &Ki); + + printf("Control Output: %f\n", control_output); + + return 0; +} + + + +///////////////////////////////////////////////////// +/* +In this example, the adaptivePIControl function calculates the adaptive PI control + output based on the reference speed, measured speed, and the current values of the + proportional gain (Kp) and integral gain (Ki). The function also updates the integral term. + +The rlsAdaptation function performs the Recursive Least Squares (RLS) adaptation to + adjust the gains (Kp and Ki) based on the error between the reference speed and the + measured speed. It iteratively updates the estimates of the gains and the covariance + matrix using the RLS algorithm. + +The main function demonstrates the usage of the adaptive PI control and the RLS adaptation. + It initializes the gains and covariance matrix, performs the adaptation, and calculates + the control output. The control output is then printed to the console. + +Please note that this is a simplified example, and in a real-world scenario, you would +need to consider the specific motor dynamics, tuning of parameters, and implementation +details based on the control requirements of your motor system. Additionally, the RLS +algorithm may require additional considerations such as regularization techniques to + handle numerical stability and noise in the measurements. + */ + +#include +#include + +// Constants for the adaptive PI control and RLS algorithm +#define Lambda 0.9 // Forgetting factor +#define Initial_estimate 1.0 // Initial estimate for covariance matrix +#define Max_iterations 1000 // Maximum number of iterations for adaptation + +// Function to calculate the adaptive PI control output +float adaptivePIControl(float reference_speed, float measured_speed, float Kp, float Ki) +{ + static float integral_term = 0.0; + float error = reference_speed - measured_speed; + + // Update the integral term + integral_term += error; + + // Calculate the control output + float control_output = Kp * error + Ki * integral_term; + + return control_output; +} + +// Function to perform Recursive Least Squares (RLS) adaptation +void rlsAdaptation(float reference_speed, float measured_speed, float *Kp, float *Ki, float *P) +{ + int iteration; + float error; + float integral_term = 0.0; + float Kp_estimate = *Kp; + float Ki_estimate = *Ki; + float P_estimate = *P; + + for (iteration = 0; iteration < Max_iterations; iteration++) + { + // Calculate the error + error = reference_speed - measured_speed; + + // Update the integral term + integral_term += error; + + // Calculate the gain vector + float K_vector = P_estimate * integral_term / (Lambda + integral_term * P_estimate * integral_term); + + // Update the estimates + Kp_estimate += K_vector * error; + Ki_estimate += K_vector * integral_term; + P_estimate = P_estimate / (Lambda + integral_term * P_estimate * integral_term); + + // Update the gains + *Kp = Kp_estimate; + *Ki = Ki_estimate; + *P = P_estimate; + } +} + +int main() +{ + float reference_speed = 100.0; // Desired speed reference + float measured_speed = 85.0; // Measured speed of the motor + + // Initialize the gains and covariance matrix + float Kp = 1.0; + float Ki = 0.5; + float P = Initial_estimate; + + // Perform RLS adaptation + rlsAdaptation(reference_speed, measured_speed, &Kp, &Ki, &P); + + // Calculate the adaptive PI control output + float control_output = adaptivePIControl(reference_speed, measured_speed, Kp, Ki); + + printf("Control Output: %f\n", control_output); + + return 0; +} +///////////////////////////////////////////////////// +/* +In this example, the adaptivePIControl function calculates the adaptive PI +control output based on the reference speed, measured speed, and the current +values of the proportional gain (Kp) and integral gain (Ki). The function also + updates the integral term. + +The lmsAdaptation function performs the Least Mean Squares (LMS) adaptation to +adjust the gains (Kp and Ki) based on the error between the reference speed and +the measured speed. It iteratively updates the estimates of the gains using the +LMS algorithm. + +The main function demonstrates the usage of the adaptive PI control and the + LMS adaptation. It initializes the gains, performs the adaptation, and calculates + the control output. The control output is then printed to the console. + +Please note that this is a simplified example, and in a real-world scenario, you + would need to consider the specific motor dynamics, tuning of parameters, and + implementation details based on the control requirements of your motor system. + Additionally, the LMS algorithm may require additional considerations such as + step-size adaptation techniques or regularization to improve convergence and handle + noise in the measurements. + */ + +// Constants for the adaptive PI control and LMS algorithm +#define Step_size 0.01 // Step size for adaptation +#define Max_iterations 1000 // Maximum number of iterations for adaptation + +// Function to calculate the adaptive PI control output +float adaptivePIControl(float reference_speed, float measured_speed, float Kp, float Ki) +{ + static float integral_term = 0.0; + float error = reference_speed - measured_speed; + + // Update the integral term + integral_term += error; + + // Calculate the control output + float control_output = Kp * error + Ki * integral_term; + + return control_output; +} + +// Function to perform Least Mean Squares (LMS) adaptation +void lmsAdaptation(float reference_speed, float measured_speed, float *Kp, float *Ki) +{ + int iteration; + float error; + float integral_term = 0.0; + float Kp_estimate = *Kp; + float Ki_estimate = *Ki; + + for (iteration = 0; iteration < Max_iterations; iteration++) + { + // Calculate the error + error = reference_speed - measured_speed; + + // Update the integral term + integral_term += error; + + // Update the estimates + Kp_estimate += Step_size * error; + Ki_estimate += Step_size * integral_term; + + // Update the gains + *Kp = Kp_estimate; + *Ki = Ki_estimate; + } +} + +int main() +{ + float reference_speed = 100.0; // Desired speed reference + float measured_speed = 85.0; // Measured speed of the motor + + // Initialize the gains + float Kp = 1.0; + float Ki = 0.5; + + // Perform LMS adaptation + lmsAdaptation(reference_speed, measured_speed, &Kp, &Ki); + + // Calculate the adaptive PI control output + float control_output = adaptivePIControl(reference_speed, measured_speed, Kp, Ki); + + printf("Control Output: %f\n", control_output); + + return 0; +} + +////////////////////////////////////////////// + + +/* +In this example, the adaptiveControl function calculates the adaptive control + output based on the reference input and the measured output of the plant. + It also updates the state variable and adapts the plant parameters using the + MRAC algorithm. + +The state variable represents the internal state of the plant model and is + updated using the plant gain and the difference between the reference input + and the current state variable multiplied by the adaptation rate. + +The control output is calculated using the updated state variable. + +The plant parameters, including the gain and time constant, are adapted using +the error between the measured output and the reference input, the state +variable, and the adaptation rate. + +The main function demonstrates the usage of the adaptive control and the MRAC +algorithm. It initializes the plant parameters, performs the adaptation, and +calculates the control output. The control output is then printed to the console. + +Please note that this is a simplified example, and in a real-world scenario, +you would need to consider the specific plant dynamics, tuning of parameters, +and implementation details based on the control requirements of your system. +Additionally, the MRAC algorithm may require additional considerations such as +stability analysis, anti-windup techniques, and robustness enhancements to handle + modeling uncertainties and external disturbances. + */ + +// Constants for the model reference adaptive control (MRAC) +#define Adaptation_rate 0.01 // Adaptation rate for parameter updates +#define Reference_model_gain 1.0 // Gain of the reference model +#define Reference_model_time_constant 1.0 // Time constant of the reference model + +// Function to calculate the adaptive control output +float adaptiveControl(float reference_input, float measured_output, float *plant_gain, float *plant_time_constant) +{ + static float state_variable = 0.0; + float control_output; + + // Update the state variable using the plant model + state_variable += (*plant_gain) * (reference_input - state_variable) * Adaptation_rate; + + // Calculate the control output using the updated state variable + control_output = state_variable; + + // Adapt the plant parameters using the error between the measured output and the reference input + float error = reference_input - measured_output; + *plant_gain += error * state_variable * Adaptation_rate; + *plant_time_constant += error * state_variable * state_variable * Adaptation_rate; + + return control_output; +} + +int main() +{ + float reference_input = 1.0; // Desired reference input + float measured_output = 0.0; // Measured output of the plant + + // Initialize the plant parameters + float plant_gain = 0.5; + float plant_time_constant = 0.75; + + // Calculate the adaptive control output + float control_output = adaptiveControl(reference_input, measured_output, &plant_gain, &plant_time_constant); + + printf("Control Output: %f\n", control_output); + + return 0; +} +//////////////////////////////////////////// + +#include + +// Constants for the PID control +#define Kp 1.0 // Proportional gain +#define Ki 0.5 // Integral gain +#define Kd 0.2 // Derivative gain + +// Function to calculate the PID control output +float PIDControl(float reference_value, float measured_value, float *previous_error, float *integral) +{ + float error = reference_value - measured_value; + float derivative = error - (*previous_error); + + // Update the integral term + *integral += error; + + // Calculate the control output + float control_output = Kp * error + Ki * (*integral) + Kd * derivative; + + // Update the previous error + *previous_error = error; + + return control_output; +} + +int main() +{ + float reference_value = 10.0; // Desired reference value + float measured_value = 8.0; // Measured value + + // Initialize variables for PID control + float previous_error = 0.0; + float integral = 0.0; + + // Calculate the PID control output + float control_output = PIDControl(reference_value, measured_value, &previous_error, &integral); + + printf("Control Output: %f\n", control_output); + + return 0; +} diff --git a/Inu/Src/N12_Libs/not_use/pi_adaptive.c b/Inu/Src/N12_Libs/not_use/pi_adaptive.c new file mode 100644 index 0000000..afcf23d --- /dev/null +++ b/Inu/Src/N12_Libs/not_use/pi_adaptive.c @@ -0,0 +1,40 @@ +#include + +// +double kp = 0.5; // +double ki = 0.2; // +double e_prev = 0; // +double i_term = 0; // + +// , +double calculate_control_action(double setpoint, double process_variable) +{ + double error = setpoint - process_variable; // + + // + i_term += ki * error; + + // + double adaptive_kp = kp / (1 + (i_term * i_term)); + + // + double control_action = adaptive_kp * error + i_term; + + // + e_prev = error; + + return control_action; +} + +int main() +{ + double setpoint = 25.0; // + double process_variable = 20.0; // + + // + printf("Control action: %f\n", calculate_control_action(setpoint, process_variable)); + + return 0; +} + + diff --git a/Inu/Src/N12_Libs/options_table.c b/Inu/Src/N12_Libs/options_table.c new file mode 100644 index 0000000..e3b8e2c --- /dev/null +++ b/Inu/Src/N12_Libs/options_table.c @@ -0,0 +1,37 @@ +//#include "RS_Functions_modbus.h" +#include "options_table.h" + +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" + + + +#pragma DATA_SECTION(options_controller, ".slow_vars") +MODBUS_REG_STRUCT options_controller[SIZE_OPTIONS_TABLE]; + + + +int store_data_flash(MODBUS_REG_STRUCT *modbus_t, unsigned int size) +{ + volatile unsigned long Address1, Address2; + volatile unsigned long Length, LengthW; + unsigned int cerr, repl, count_ok; + + Address1 = (unsigned long)modbus_t; + Address2 = ADR_STORE_OPTION_TO_FLASH; + + LengthW = size; + + if( (Address2 < 0x100000) || (Address2 > 0x180000) || ((Address2+LengthW) > 0x180000) ) + { + return 1; + } + + RunFlashData(Address1,Address2,LengthW, &cerr, &repl, &count_ok ); + + + return 0; + +} + + diff --git a/Inu/Src/N12_Libs/options_table.h b/Inu/Src/N12_Libs/options_table.h new file mode 100644 index 0000000..8447a55 --- /dev/null +++ b/Inu/Src/N12_Libs/options_table.h @@ -0,0 +1,17 @@ +#ifndef _OPTIONS_TABLE_H +#define _OPTIONS_TABLE_H + +#include "modbus_struct.h" + +#define ADR_STORE_OPTION_TO_FLASH 0x16000 + + +#define SIZE_OPTIONS_TABLE 200 + + +extern MODBUS_REG_STRUCT options_controller[SIZE_OPTIONS_TABLE]; + +int store_data_flash(MODBUS_REG_STRUCT *modbus_t, unsigned int size); + + +#endif // end _OPTIONS_TABLE_H diff --git a/Inu/Src/N12_Libs/oscil_can.c b/Inu/Src/N12_Libs/oscil_can.c new file mode 100644 index 0000000..47bcb39 --- /dev/null +++ b/Inu/Src/N12_Libs/oscil_can.c @@ -0,0 +1,293 @@ +/* + * oscil_can.c + * + * Created on: 24 2020 . + * Author: yura + */ + +#include "oscil_can.h" + +#include "CAN_Setup.h" +#include "global_time.h" + + + +#pragma DATA_SECTION(oscil_can, ".slow_vars") +OSCIL_CAN oscil_can = OSCIL_CAN_DEFAULTS; + + + +//int oscil_buffer[OSCIL_CAN_NUMBER_CHANNEL][OSCIL_CAN_NUMBER_POINTS]; + + + +void oscil_clear_buffer(OSCIL_CAN_handle oc) +{ + unsigned int i,k; + + for (i=0;ioscil_buffer[i][k] = 0; + + for (i=0;itemp_oscil_buffer[i][k] = 0; + + + oc->current_position = 0; + // oc->enable_rewrite = 1; + +} + + +void oscil_send_buffer(OSCIL_CAN_handle oc) +{ + static unsigned int old_time = 0; + static int prev_send_to_can = 0; + unsigned long old_t; + unsigned int i; + int real_mbox; + static int flag_send_buf = 0; + + +// if (flag_send_buf) +// { +// +// +// +// return; +// } + + + + oc->global_enable = TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x1; + oc->send_after_cmd = (TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x2) >> 1; + oc->cmd_send = (TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x4) >> 2; + oc->stop_update_on_error = (TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x8) >> 3; + oc->stop_update_on_stop_pwm = (TerminalUnites[oc->number_can_box_terminal_oscil][0] & 0x10) >> 4; + + TerminalUnites[oc->number_can_box_terminal_oscil][0] &= ~0x4; // clear cmd_send + + oc->number_ch = TerminalUnites[oc->number_can_box_terminal_oscil][1]; + oc->number_points = TerminalUnites[oc->number_can_box_terminal_oscil][2]; + oc->step = TerminalUnites[oc->number_can_box_terminal_oscil][3]; + + + if (oc->global_enable==0) + return; + + real_mbox = get_real_out_mbox(TERMINAL_TYPE_BOX, oc->number_can_box_terminal_oscil); + + // , , + // .. OSCIL_TIME_WAIT . + if (prev_send_to_can && CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_OFF)==0) + { + old_time = (unsigned int)global_time.miliseconds; + return; + } + prev_send_to_can = 0; + + if (oc->send_after_cmd==0) + { + if (!detect_pause_milisec(OSCIL_TIME_WAIT,&old_time)) + return; + } + + + if ( (oc->send_after_cmd==0 || (oc->send_after_cmd==1 && oc->cmd_send==1 ) ) ) + { + + oc->cmd_send = 0; // clear cmd + + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_ON)) + { + + // oc->enable_rewrite = 0; + + + old_t = oc->current_position;// +// old_t = global_time.microseconds; + + oc->prepare_data_can(oc); + +// oc->timer_send = (global_time.microseconds - old_t); + oc->timer_send = (oc->current_position - old_t); + + flag_send_buf = 1; + + CAN_cycle_send( + TERMINAL_TYPE_BOX, + oc->number_can_box_terminal_oscil, + 0, + &(oc->temp_oscil_buffer[0][0]), (oc->number_ch * oc->number_points) , CAN_BOX_EXTENDED_ADR, CAN_BOX_PRIORITY_LOW ); + + prev_send_to_can = 1; + // while (CAN_cycle_free(real_mbox)==0); + +// oc->timer_send = (global_time.microseconds - old_t)/100; + + + oc->enable_rewrite = 1; + + +// if (cur_position_buf_modbus16_can >= SIZE_MODBUS_TABLE) +// { +// cur_position_buf_modbus16_can = 0; +//// modbus_table_can_out[ADR_CAN_TEST_PLUS_ONE].all++; +// } +// +// if ((cur_position_buf_modbus16_can + SIZE_BUF_WRITE_TO_MODBUS16_CAN) >= SIZE_MODBUS_TABLE) +// count_write_to_modbus_can = SIZE_MODBUS_TABLE - cur_position_buf_modbus16_can; +// else +// count_write_to_modbus_can = SIZE_BUF_WRITE_TO_MODBUS16_CAN; +// +// if (CAN_cycle_free(real_mbox)) +// { +// CAN_cycle_send( +// MPU_TYPE_BOX, +// edrk.flag_second_PCH, +// cur_position_buf_modbus16_can + 1, +// &modbus_table_can_out[cur_position_buf_modbus16_can].all, +// count_write_to_modbus_can, 0); +// +// cur_position_buf_modbus16_can = cur_position_buf_modbus16_can + SIZE_BUF_WRITE_TO_MODBUS16_CAN; +// } +// +// + + + + + + } + } + + +} + + +//#pragma CODE_SECTION(oscil_next_position,".fast_run"); +void oscil_next_position(OSCIL_CAN_handle oc) +{ + static int prev_status_pwm = 0; + static int prev_status_error = 0; + static int cmd_stop_after_stop_pwm = 0; + static int cmd_stop_after_stop_error = 0; + + static int count_write_after_stop = 0; + + static int prev_stop_update_on_stop_pwm = 0; + static int prev_stop_update_on_stop_error = 0; + +////////// + if (oc->stop_update_on_error) + { + if (oc->status_error && prev_status_error==0) + { + // + count_write_after_stop = OSCIL_CAN_NUMBER_POINTS_AFTER_STOP; + cmd_stop_after_stop_error = 1; + } + + if (oc->status_error==0 && prev_status_error) + { + // . + cmd_stop_after_stop_error = 0; + } + + } + else + cmd_stop_after_stop_error = 0; + +//////////// + + if (oc->stop_update_on_stop_pwm==1 && prev_stop_update_on_stop_pwm==0) + { + // onPWM . + cmd_stop_after_stop_pwm = 1; + } + + if (oc->stop_update_on_stop_pwm) + { + if (oc->status_pwm==0 && prev_status_pwm) + { + // PWM . + count_write_after_stop = OSCIL_CAN_NUMBER_POINTS_AFTER_STOP; + cmd_stop_after_stop_pwm = 1; + } + + if (oc->status_pwm && prev_status_pwm==0) + { + // PWM . + cmd_stop_after_stop_pwm = 0; + } + } + else + cmd_stop_after_stop_pwm = 0; + + prev_stop_update_on_stop_pwm = oc->stop_update_on_stop_pwm; + prev_stop_update_on_stop_error = oc->stop_update_on_error; + prev_status_error = oc->status_error; + prev_status_pwm = oc->status_pwm; +//////////// + + + + oc->current_step++; + if (oc->current_step>=oc->step) + { + oc->current_step = 0; + + if (cmd_stop_after_stop_error || cmd_stop_after_stop_pwm) + { + if (count_write_after_stop) + { + count_write_after_stop--; + oc->current_position++; + oc->code_status_log = OSCIL_CODE_STATUS_LOG_RUN_TO_STOP; + } + else + oc->code_status_log = OSCIL_CODE_STATUS_LOG_STOP; + } + else + { + oc->current_position++; + oc->code_status_log = OSCIL_CODE_STATUS_LOG_RUN; + } + + if (oc->current_position==(OSCIL_CAN_NUMBER_POINTS+OSCIL_CAN_NUMBER_POINTS_ADD)) + oc->current_position = 0; + } + + +} + + +#pragma CODE_SECTION(oscil_prepare_data_can,".fast_run"); +void oscil_prepare_data_can(OSCIL_CAN_handle oc) +{ + unsigned int old_position, t_position; + int i, k; + + + old_position = oc->current_position; + + for (i=0;i=0;k--) + { + if (t_position==0) + { + t_position = (OSCIL_CAN_NUMBER_POINTS+OSCIL_CAN_NUMBER_POINTS_ADD)-1; + } + else + t_position = t_position - 1; + + oc->temp_oscil_buffer[i][k] = oc->oscil_buffer[i][t_position]; + + } + + } + +} diff --git a/Inu/Src/N12_Libs/oscil_can.h b/Inu/Src/N12_Libs/oscil_can.h new file mode 100644 index 0000000..bb55f46 --- /dev/null +++ b/Inu/Src/N12_Libs/oscil_can.h @@ -0,0 +1,103 @@ +/* + * oscil_can.h + * + * Created on: 24 2020 . + * Author: yura + */ + +#ifndef SRC_LIBS_NIO12_OSCIL_CAN_H_ +#define SRC_LIBS_NIO12_OSCIL_CAN_H_ + + +#define OSCIL_CODE_STATUS_LOG_STOP 1 // +#define OSCIL_CODE_STATUS_LOG_RUN 2 // ... +#define OSCIL_CODE_STATUS_LOG_RUN_TO_STOP 3 // , , . + + + +#define OSCIL_CAN_NUMBER_CHANNEL 32 // - +#define OSCIL_CAN_NUMBER_POINTS 500 // - ( ) +#define OSCIL_TIME_WAIT 5000 // CAN () +#define OSCIL_CAN_NUMBER_POINTS_ADD 100 // . oscil_buffer->temp_oscil_buffer + +#define OSCIL_CAN_NUMBER_POINTS_AFTER_STOP 100 // + + + +typedef struct { + int oscil_buffer[OSCIL_CAN_NUMBER_CHANNEL][OSCIL_CAN_NUMBER_POINTS+OSCIL_CAN_NUMBER_POINTS_ADD]; + int temp_oscil_buffer[OSCIL_CAN_NUMBER_CHANNEL][OSCIL_CAN_NUMBER_POINTS]; + unsigned int global_enable; + unsigned int number_ch; + unsigned int number_points; + unsigned int step; + unsigned int send_after_cmd; + unsigned int cmd_send; + unsigned int current_step; + unsigned int enable_rewrite; + unsigned int current_position; + unsigned int timer_send; + unsigned int code_status_log; + + unsigned int status_error; // 0- /1- + unsigned int status_pwm; // 0- /1- + + unsigned int stop_update_on_error; // + unsigned int stop_update_on_stop_pwm; // + + + int number_can_box_terminal_oscil; + int number_can_box_terminal_cmd; + unsigned int pause_can; // CAN + + + void (*clear)(); // Clear buffers + void (*send)(); // Send buffers + void (*set_next_position)(); // Set next position in buffers + void (*prepare_data_can)(); // Set next position in buffers + +} OSCIL_CAN; + +typedef OSCIL_CAN *OSCIL_CAN_handle; + + + +#define OSCIL_CAN_DEFAULTS { {0},{0}, \ + 0, \ + OSCIL_CAN_NUMBER_CHANNEL, \ + OSCIL_CAN_NUMBER_POINTS, \ + 1, \ + 0, \ + 0, \ + 0, \ + 1, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 1, \ + 1, \ + 0,0, \ + OSCIL_TIME_WAIT, \ + oscil_clear_buffer, \ + oscil_send_buffer, \ + oscil_next_position, \ + oscil_prepare_data_can \ +} + + + + +void oscil_clear_buffer(OSCIL_CAN_handle); +void oscil_send_buffer(OSCIL_CAN_handle); +void oscil_next_position(OSCIL_CAN_handle); +void oscil_prepare_data_can(OSCIL_CAN_handle); + + + +extern OSCIL_CAN oscil_can; + +#endif /* SRC_LIBS_NIO12_OSCIL_CAN_H_ */ + + diff --git a/Inu/Src/N12_Libs/params_protect.h b/Inu/Src/N12_Libs/params_protect.h new file mode 100644 index 0000000..d85c625 --- /dev/null +++ b/Inu/Src/N12_Libs/params_protect.h @@ -0,0 +1,63 @@ +#ifndef PARAMS_H +#define PARAMS_H + +//////////////////////////////////////////////////////////////// +// Loaded capasitors level +#define V_CAPASITORS_LOADED_IQ 11184810 //13421772 ~ 2400V // 11184810 ~ 2000V +#define V_NOMINAL 15099494 //15099494 ~ 2700V + +// Level of nominal current and maximum current +#define I_OUT_NOMINAL_IQ 9777761 //6431266 ~ 1150A //2796202 ~ 500A //By TU 1240A RMS - 1748A ~ 9777761 IQ +#define I_OUT_LIMIT_IQ 8388608 //8388608 ~ 1500A //5592405 ~ 1000A // 4473924 ~ 800A //1.5*In - 2622A ~ 14666642 IQ + //11184811 ~ 2000A // 12482249 ~ 2232A // 6710886 ~ 1200A + +// Input voltage levels for protection +#define V_IN_PLUS_20 (2340) +#define V_IN_PLUS_25 2650 //2450 +#define V_IN_MINUS_20 (1560) +#define V_IN_MINUS_25 1462 + + +//ACP program errors level +#define ERR_LEVEL_ADC_PLUS 3950 //+1270A //2950 // +650A //3467 // 3367 //3367 //3267 // 0xfff-0x29c +#define ERR_LEVEL_ADC_MINUS 150 //-1270A //1150 //-650A // 267 //367 +#define ERR_LEVEL_ADC_PLUS_6 650 //875 ~ 2500V //650 ~ 3000B // 740 ~ 2800B // +#define ERR_LEVEL_ADC_MINUS_6 1205 //1775V ~ 1205 +#define ERR_LEVEL_I_FAZA_PLUS 594 //1760A ~ 1058 //2000A ~ 924 //843 ~ 2100A // 594 ~ 2500A +#define ERR_LEVEL_I_FAZA_MINUS 3496 //1760A ~ 3031 //2000A ~ 3166 //3226 ~2100A // 3496 ~ 2500A +#define ERR_LEVEL_I_ZPT_PLUS 520 //520 ~ 1500A +#define ERR_LEVEL_BREAK_REZ 858 //858 ~ 800A +#define MIN_DETECT_UD_ZERO 2300 + +#define ERR_LEVEL_ADC_PLUS_6_ON_GO_IQ 16777216 //3000V // 16217975 //2900V +#define ERR_LEVEL_ADC_PLUS_6_IQ 16777216 //3000V //15658734 //2800V + +// Temperature protection levels +#define TEMPERATURE_LIMIT 600 //Area temperature +#define TEMPERATURE_WARNING 500 +#define TEMPERATURE_WATER_LIMIT 500 //Water temeperature +#define TEMPERATURE_WATER_WARNING 450 +#define TEMPERATURE_WATER_FAZA_LIMIT 500 //Water temperature on phase output +#define TEMPERATURE_WATER_FAZA_WARNING 450 +#define TEMPERATURE_WATER_SNABBER_RESISTORS_LIMIT 500 +#define TEMPERATURE_WATER_SNABBER_RESISTORS_WARNING 450 +#define TEMPERATURE_WATER_DROSSEL_LIMIT 600 //Output drossel water limits +#define TEMPERATURE_WATER_DROSSEL_WARNING 500 +#define TEMPERATURE_WATER_DIODS_LIMIT 500 //water temperature at rectifier outlet +#define TEMPERATURE_WATER_DIODS_WARNING 450 +#define TEMPERATURE_WATER_CHOPPER_LIMIT 500 +#define TEMPERATURE_WATER_CHOPPER_WARNING 450 +#define TEMPERATURE_REZISTORS_LIMIT_BV 600 //temperature on coolers of input filter resistors +#define TEMPERATURE_REZISTORS_WARNING_BV 500 +#define TEMPERATURE_REZISTORS_LIMIT_BI 500 //temperature on the coolers of the output filter resistors +#define TEMPERATURE_REZISTORS_WARNING_BI 450 +#define TEMPERATURE_INPUT_BSO_DN20 500 +#define TEMPERATURE_INPUT_BSO_DN100 500 +#define TEMPERATURE_OUTPUT_BSO_DN20 400 +#define TEMPERATURE_OUTPUT_BSO_DN100 400 +//////////////////////////////////// +#define TEMPERATURE_AREA_DATCHIK_ERROR -100 + + + +#endif //PARAMS_H \ No newline at end of file diff --git a/Inu/Src/N12_Libs/pid_reg3.c b/Inu/Src/N12_Libs/pid_reg3.c new file mode 100644 index 0000000..39502f5 --- /dev/null +++ b/Inu/Src/N12_Libs/pid_reg3.c @@ -0,0 +1,64 @@ +/*===================================================================================== + File name: PID_REG3.C (IQ version) + + Originator: Digital Control Systems Group + Texas Instruments + + Description: The PID controller with anti-windup + +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +-------------------------------------------------------------------------------------*/ + +#include "pid_reg3.h" + +#include "IQmathLib.h" // Include header for IQmath library + +#define IQ_100 1677721600 + +#pragma CODE_SECTION(pid_reg3_calc,".fast_run"); +void pid_reg3_calc(PIDREG3 *v) +{ +_iq Ud2; + // Compute the error + v->Err = v->Ref - v->Fdb; + + // Compute the proportional output + v->Up = _IQmpy(v->Kp,v->Err); + + // Compute the integral output + v->Ui = v->Ui + _IQmpy(v->Ki,v->Up) + _IQmpy(v->Kc,v->SatErr); +/* + // Saturate the integral output + if (v->Ui > v->OutMax) + v->Ui = v->OutMax; + else if (v->Ui < v->OutMin) + v->Ui = v->OutMin; +*/ + // Compute the derivative output + Ud2 = v->Up - v->Up1;// _IQmpy(IQ_100,(v->Up - v->Up1)); + v->Ud = _IQmpy(v->Kd,Ud2); + + + // Compute the pre-saturated output + v->OutPreSat = v->Up + v->Ui + v->Ud; + + // Saturate the output + if (v->OutPreSat > v->OutMax) + v->Out = v->OutMax; + else if (v->OutPreSat < v->OutMin) + v->Out = v->OutMin; + else + v->Out = v->OutPreSat; + + // Compute the saturate difference + v->SatErr = v->Out - v->OutPreSat; + + // Update the previous proportional output + v->Up1 = v->Up; + + +} + diff --git a/Inu/Src/N12_Libs/pid_reg3.h b/Inu/Src/N12_Libs/pid_reg3.h new file mode 100644 index 0000000..d7b882c --- /dev/null +++ b/Inu/Src/N12_Libs/pid_reg3.h @@ -0,0 +1,98 @@ +/* ================================================================================= +File name: PID_REG3.H (IQ version) + +Originator: Digital Control Systems Group + Texas Instruments + +Description: +Header file containing constants, data type definitions, and +function prototypes for the PIDREG3. +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +------------------------------------------------------------------------------*/ +#ifndef __PIDREG3_H__ +#define __PIDREG3_H__ + +#include "IQmathLib.h" +//#include "dmctype.h" + +typedef struct { _iq Ref; // Input: Reference input + _iq Fdb; // Input: Feedback input + _iq Err; // Variable: Error + _iq Kp; // Parameter: Proportional gain + _iq Up; // Variable: Proportional output + _iq Ui; // Variable: Integral output + _iq Ud; // Variable: Derivative output + _iq OutPreSat; // Variable: Pre-saturated output + _iq OutMax; // Parameter: Maximum output + _iq OutMin; // Parameter: Minimum output + _iq Out; // Output: PID output + _iq SatErr; // Variable: Saturated difference + _iq Ki; // Parameter: Integral gain + _iq Kc; // Parameter: Integral correction gain + _iq Kd; // Parameter: Derivative gain + _iq Up1; // History: Previous proportional output + void (*calc)(); // Pointer to calculation function + } PIDREG3; + +typedef PIDREG3 *PIDREG3_handle; +/*----------------------------------------------------------------------------- +Default initalizer for the PIDREG3 object. +-----------------------------------------------------------------------------*/ +#define PIDREG3_DEFAULTS { 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + (void (*)(PIDREG3_handle))pid_reg3_calc } + +/*------------------------------------------------------------------------------ +Prototypes for the functions in PIDREG3.C +------------------------------------------------------------------------------*/ +void pid_reg3_calc(PIDREG3_handle); + +#endif // __PIDREG3_H__ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Inu/Src/N12_Libs/rmp_cntl_v1.c b/Inu/Src/N12_Libs/rmp_cntl_v1.c new file mode 100644 index 0000000..b99ffbc --- /dev/null +++ b/Inu/Src/N12_Libs/rmp_cntl_v1.c @@ -0,0 +1,51 @@ +/*===================================================================================== + File name: RMP3CNTL.C (IQ version) + + Originator: Digital Control Systems Group + Texas Instruments + + Description: The ramp3 down control + +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +-------------------------------------------------------------------------------------*/ +#include "dmctype.h" +#include "IQmathLib.h" // Include header for IQmath library + +#include "rmp_cntl_v1.h" + + +#pragma CODE_SECTION(rmp_cntl_v1_calc,".fast_run"); +void rmp_cntl_v1_calc(RMP_V1 *v) +{ + _iq tmp; + + tmp = v->DesiredInput - v->Out; + + if (tmp > (_iq)v->RampPlus) + { + //v->RampDoneFlag = 0; + v->Out += v->RampPlus; + if (v->Out > v->RampHighLimit) + v->Out = v->RampHighLimit; + } + else + { + if (tmp < (_iq)v->RampMinus) + { + //v->RampDoneFlag = 0; + v->Out += (_iq)v->RampMinus; + if (v->Out < v->RampLowLimit) + v->Out = v->RampLowLimit; + } + else + { + v->Out = v->DesiredInput; + //v->RampDoneFlag = 0x7FFFFFFF; + } + } +} + + diff --git a/Inu/Src/N12_Libs/rmp_cntl_v1.h b/Inu/Src/N12_Libs/rmp_cntl_v1.h new file mode 100644 index 0000000..71a576c --- /dev/null +++ b/Inu/Src/N12_Libs/rmp_cntl_v1.h @@ -0,0 +1,48 @@ +/* ================================================================================= +File name: RMP3CNTL.H (IQ version) + +Originator: Digital Control Systems Group + Texas Instruments + +Description: +Header file containing constants, data type definitions, and +function prototypes for the RMP3 module. +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +------------------------------------------------------------------------------*/ +#ifndef __RMP_CNTL_V1_H__ +#define __RMP_CNTL_V1_H__ + +typedef struct { _iq DesiredInput; // Input: Desired ramp input (Q0) - independently with global Q + _iq RampPlus; // Parameter: Ramp3 delay expressed in no of sampling period (Q0) - independently with global Q + _iq RampMinus; // Variable: Counter for rmp3 delay (Q0) - independently with global Q + _iq Out; // Output: Ramp3 output (Q0) - independently with global Q + _iq RampLowLimit; // Parameter: Minimum ramp output (Q0) - independently with global Q + _iq RampHighLimit; // Parameter: Minimum ramp output (Q0) - independently with global Q + //Uint32 RampDoneFlag; // Output: Flag output (Q0) - independently with global Q + void (*calc)(); // Pointer to calculation function + } RMP_V1; + +typedef RMP_V1 *RMP_V1_handle; +/*----------------------------------------------------------------------------- +Default initalizer for the RMP3 object. +-----------------------------------------------------------------------------*/ +#define RMP_V1_DEFAULTS { 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0x00000050, \ + (void (*)())rmp_cntl_v1_calc } + +/*------------------------------------------------------------------------------ +Prototypes for the functions in RMP3CNTL.C +------------------------------------------------------------------------------*/ +void rmp_cntl_v1_calc(RMP_V1_handle); + + + +#endif // __RMP3_CNTL_H__ + diff --git a/Inu/Src/N12_Libs/rmp_cntl_v2.c b/Inu/Src/N12_Libs/rmp_cntl_v2.c new file mode 100644 index 0000000..174dffd --- /dev/null +++ b/Inu/Src/N12_Libs/rmp_cntl_v2.c @@ -0,0 +1,193 @@ +/*===================================================================================== + File name: RMP3CNTL.C (IQ version) + + Originator: Digital Control Systems Group + Texas Instruments + + Description: The ramp3 down control + +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +-------------------------------------------------------------------------------------*/ +#include "dmctype.h" +#include "IQmathLib.h" // Include header for IQmath library + +#include "rmp_cntl_v2.h" + +/* + * PosRampPlus + * PosRampMinus + * NegRampPlus + * NegRampMinus + */ + +#pragma CODE_SECTION(rmp_cntl_v2_calc,".fast_run"); +void rmp_cntl_v2_calc(RMP_V2 *v) +{ + _iq tmp; + + tmp = v->DesiredInput - v->Out; + + if (v->Out>=0) + { + // + + + if (v->Out >= v->RampHighLimit1) + { + // + if (tmp > (_iq)v->PosRampPlus2) + { + v->Out += v->PosRampPlus2; + if (v->Out > v->RampHighLimit) + v->Out = v->RampHighLimit; + } + else + { + if (tmp < (_iq)v->PosRampMinus2) + { + v->Out += (_iq)v->PosRampMinus2; + if (v->Out < v->RampLowLimit) + v->Out = v->RampLowLimit; + } + else + { + v->Out = v->DesiredInput; + } + } + + + } + else + { + // + if (tmp > (_iq)v->PosRampPlus1) + { + v->Out += v->PosRampPlus1; + if (v->Out > v->RampHighLimit) + v->Out = v->RampHighLimit; + } + else + { + if (tmp < (_iq)v->PosRampMinus1) + { + v->Out += (_iq)v->PosRampMinus1; + if (v->Out < v->RampLowLimit) + v->Out = v->RampLowLimit; + } + else + { + v->Out = v->DesiredInput; + } + } + + } + +// if (tmp > (_iq)v->PosRampPlus) +// { +// //v->RampDoneFlag = 0; +// v->Out += v->PosRampPlus; +// if (v->Out > v->RampHighLimit) +// v->Out = v->RampHighLimit; +// } +// else +// { +// if (tmp < (_iq)v->PosRampMinus) +// { +// //v->RampDoneFlag = 0; +// v->Out += (_iq)v->PosRampMinus; +// if (v->Out < v->RampLowLimit) +// v->Out = v->RampLowLimit; +// } +// else +// { +// v->Out = v->DesiredInput; +// //v->RampDoneFlag = 0x7FFFFFFF; +// } +// } + + } + else + { + // . + + + if (v->Out <= v->RampLowLimit1) + { + // + if (tmp > (_iq)v->NegRampPlus2) + { + v->Out += v->NegRampPlus2; + if (v->Out > v->RampHighLimit) + v->Out = v->RampHighLimit; + } + else + { + if (tmp < (_iq)v->NegRampMinus2) + { + v->Out += (_iq)v->NegRampMinus2; + if (v->Out < v->RampLowLimit) + v->Out = v->RampLowLimit; + } + else + { + v->Out = v->DesiredInput; + } + } + + } + else + { + // + if (tmp > (_iq)v->NegRampPlus1) + { + v->Out += v->NegRampPlus1; + if (v->Out > v->RampHighLimit) + v->Out = v->RampHighLimit; + } + else + { + if (tmp < (_iq)v->NegRampMinus1) + { + v->Out += (_iq)v->NegRampMinus1; + if (v->Out < v->RampLowLimit) + v->Out = v->RampLowLimit; + } + else + { + v->Out = v->DesiredInput; + } + } + + } + +// if (tmp > (_iq)v->NegRampPlus) +// { +// //v->RampDoneFlag = 0; +// v->Out += v->NegRampPlus; +// if (v->Out > v->RampHighLimit) +// v->Out = v->RampHighLimit; +// } +// else +// { +// if (tmp < (_iq)v->NegRampMinus) +// { +// //v->RampDoneFlag = 0; +// v->Out += (_iq)v->NegRampMinus; +// if (v->Out < v->RampLowLimit) +// v->Out = v->RampLowLimit; +// } +// else +// { +// v->Out = v->DesiredInput; +// //v->RampDoneFlag = 0x7FFFFFFF; +// } +// } + + } + +} + + diff --git a/Inu/Src/N12_Libs/rmp_cntl_v2.h b/Inu/Src/N12_Libs/rmp_cntl_v2.h new file mode 100644 index 0000000..eaa80af --- /dev/null +++ b/Inu/Src/N12_Libs/rmp_cntl_v2.h @@ -0,0 +1,69 @@ +/* ================================================================================= +File name: RMP3CNTL.H (IQ version) + +Originator: Digital Control Systems Group + Texas Instruments + +Description: +Header file containing constants, data type definitions, and +function prototypes for the RMP3 module. +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +------------------------------------------------------------------------------*/ +#ifndef __RMP_CNTL_V2_H__ +#define __RMP_CNTL_V2_H__ + +typedef struct { _iq DesiredInput; // Input: Desired ramp input (Q0) - independently with global Q + + _iq PosRampPlus1; // Parameter: Ramp3 delay expressed in no of sampling period (Q0) - independently with global Q + _iq PosRampMinus1; // Variable: Counter for rmp3 delay (Q0) - independently with global Q + _iq PosRampPlus2; // Parameter: Ramp3 delay expressed in no of sampling period (Q0) - independently with global Q + _iq PosRampMinus2; // Variable: Counter for rmp3 delay (Q0) - independently with global Q + + _iq NegRampPlus1; // Parameter: Ramp3 delay expressed in no of sampling period (Q0) - independently with global Q + _iq NegRampMinus1; // Variable: Counter for rmp3 delay (Q0) - independently with global Q + _iq NegRampPlus2; // Parameter: Ramp3 delay expressed in no of sampling period (Q0) - independently with global Q + _iq NegRampMinus2; // Variable: Counter for rmp3 delay (Q0) - independently with global Q + + _iq Out; // Output: Ramp3 output (Q0) - independently with global Q + + _iq RampLowLimit1; // Parameter: Minimum ramp output (Q0) - independently with global Q + _iq RampHighLimit1; // Parameter: Minimum ramp output (Q0) - independently with global Q + + _iq RampLowLimit; // Parameter: Minimum ramp output (Q0) - independently with global Q + _iq RampHighLimit; // Parameter: Minimum ramp output (Q0) - independently with global Q + //Uint32 RampDoneFlag; // Output: Flag output (Q0) - independently with global Q + void (*calc)(); // Pointer to calculation function + } RMP_V2; + +typedef RMP_V2 *RMP_V2_handle; +/*----------------------------------------------------------------------------- +Default initalizer for the RMP3 object. +-----------------------------------------------------------------------------*/ +#define RMP_V2_DEFAULTS { 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0x00000050, \ + (void (*)())rmp_cntl_v2_calc } + +/*------------------------------------------------------------------------------ +Prototypes for the functions in RMP3CNTL.C +------------------------------------------------------------------------------*/ +void rmp_cntl_v2_calc(RMP_V2_handle); + + + +#endif // __RMP3_CNTL_H__ + diff --git a/Inu/Src/N12_Libs/svgen_dq.h b/Inu/Src/N12_Libs/svgen_dq.h new file mode 100644 index 0000000..2949fd1 --- /dev/null +++ b/Inu/Src/N12_Libs/svgen_dq.h @@ -0,0 +1,38 @@ +/* ================================================================================= +File name: SVGEN_DQ.H (IQ version) + +Originator: Digital Control Systems Group + Texas Instruments + +Description: +Header file containing constants, data type definitions, and +function prototypes for the SVGEN_DQ. +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +------------------------------------------------------------------------------*/ +#ifndef __SVGEN_DQ_H__ +#define __SVGEN_DQ_H__ + +typedef struct { _iq Ualpha; // Input: reference alpha-axis phase voltage + _iq Ubeta; // Input: reference beta-axis phase voltage + _iq Ta; // Output: reference phase-a switching function + _iq Tb; // Output: reference phase-b switching function + _iq Tc; // Output: reference phase-c switching function + void (*calc)(); // Pointer to calculation function + } SVGENDQ; + +typedef SVGENDQ *SVGENDQ_handle; +/*----------------------------------------------------------------------------- +Default initalizer for the SVGENDQ object. +-----------------------------------------------------------------------------*/ +#define SVGENDQ_DEFAULTS { 0,0,0,0,0, \ + (void (*)(Uint32))svgendq_calc } + +/*------------------------------------------------------------------------------ +Prototypes for the functions in SVGEN_DQ.C +------------------------------------------------------------------------------*/ +void svgendq_calc(SVGENDQ_handle); + +#endif // __SVGEN_DQ_H__ diff --git a/Inu/Src/N12_Libs/svgen_dq_v2.c b/Inu/Src/N12_Libs/svgen_dq_v2.c new file mode 100644 index 0000000..6176b1c --- /dev/null +++ b/Inu/Src/N12_Libs/svgen_dq_v2.c @@ -0,0 +1,122 @@ +/*===================================================================================== + File name: SVGEN_DQ.C (IQ version) + + Originator: Digital Control Systems Group + Texas Instruments + + Description: Space-vector PWM generation based on d-q components + +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +-------------------------------------------------------------------------------------*/ + +#include "dmctype.h" +#include "IQmathLib.h" // Include header for IQmath library +#include "math_pi.h" +#include "svgen_dq.h" +_iq iq_max = _IQ(1.0)-1; + + + + +//#pragma CODE_SECTION(svgendq_calc,".fast_run2"); +void svgendq_calc(SVGENDQ *v) +{ + _iq Va,Vb,Vc,t1,t2,temp_sv1,temp_sv2; + Uint16 Sector = 0; // Sector is treated as Q0 - independently with global Q + + Sector = 0; \ + temp_sv1=_IQdiv2(v->Ubeta); /*divide by 2*/ \ + temp_sv2=_IQmpy(CONST_SQRT3_2,v->Ualpha); /* 0.8660254 = sqrt(3)/2*/ \ + +// Inverse clarke transformation + Va = v->Ubeta; \ + Vb = -temp_sv1 + temp_sv2; \ + Vc = -temp_sv1 - temp_sv2; \ + +// 60 degree Sector determination + if (Va>0) + Sector = 1; + if (Vb>0) + Sector = Sector + 2; + if (Vc>0) + Sector = Sector + 4; + +// X,Y,Z (Va,Vb,Vc) calculations X = Va, Y = Vb, Z = Vc \ Va = v.Ubeta; + Vb = temp_sv1 + temp_sv2; + Vc = temp_sv1 - temp_sv2; +// Sector 0: this is special case for (Ualpha,Ubeta) = (0,0) + + if (Sector==0) // Sector 0: this is special case for (Ualpha,Ubeta) = (0,0) + { + v->Ta = CONST_IQ_05; + v->Tb = CONST_IQ_05; + v->Tc = CONST_IQ_05; + } + if (Sector==1) // Sector 1: t1=Z and t2=Y (abc ---> Tb,Ta,Tc) + { + t1 = Vc; + t2 = Vb; + v->Tb = _IQdiv2((CONST_IQ_1-t1-t2)); // tbon = (1-t1-t2)/2 + v->Ta = v->Tb+t1; // taon = tbon+t1 + v->Tc = v->Ta+t2; // tcon = taon+t2 + } + else if (Sector==2) // Sector 2: t1=Y and t2=-X (abc ---> Ta,Tc,Tb) + { + t1 = Vb; + t2 = -Va; + v->Ta = _IQdiv2((CONST_IQ_1-t1-t2)); // taon = (1-t1-t2)/2 + v->Tc = v->Ta+t1; // tcon = taon+t1 + v->Tb = v->Tc+t2; // tbon = tcon+t2 + } + else if (Sector==3) // Sector 3: t1=-Z and t2=X (abc ---> Ta,Tb,Tc) + { + t1 = -Vc; + t2 = Va; + v->Ta = _IQdiv2((CONST_IQ_1-t1-t2)); // taon = (1-t1-t2)/2 + v->Tb = v->Ta+t1; // tbon = taon+t1 + v->Tc = v->Tb+t2; // tcon = tbon+t2 + } + else if (Sector==4) // Sector 4: t1=-X and t2=Z (abc ---> Tc,Tb,Ta) + { + t1 = -Va; + t2 = Vc; + v->Tc = _IQdiv2((CONST_IQ_1-t1-t2)); // tcon = (1-t1-t2)/2 + v->Tb = v->Tc+t1; // tbon = tcon+t1 + v->Ta = v->Tb+t2; // taon = tbon+t2 + } + else if (Sector==5) // Sector 5: t1=X and t2=-Y (abc ---> Tb,Tc,Ta) + { + t1 = Va; + t2 = -Vb; + v->Tb = _IQdiv2((CONST_IQ_1-t1-t2)); // tbon = (1-t1-t2)/2 + v->Tc = v->Tb+t1; // tcon = tbon+t1 + v->Ta = v->Tc+t2; // taon = tcon+t2 + } + else if (Sector==6) // Sector 6: t1=-Y and t2=-Z (abc ---> Tc,Ta,Tb) + { + t1 = -Vb; + t2 = -Vc; + v->Tc = _IQdiv2((CONST_IQ_1-t1-t2)); // tcon = (1-t1-t2)/2 + v->Ta = v->Tc+t1; // taon = tcon+t1 + v->Tb = v->Ta+t2; // tbon = taon+t2 + } + +// Convert the unsigned GLOBAL_Q format (ranged (0,1)) -> signed GLOBAL_Q format (ranged (-1,1)) + v->Ta = _IQmpy2(v->Ta - CONST_IQ_05); + v->Tb = _IQmpy2(v->Tb - CONST_IQ_05); + v->Tc = _IQmpy2(v->Tc - CONST_IQ_05); + + if (v->Ta > iq_max) v->Ta = iq_max; + if (v->Tb > iq_max) v->Tb = iq_max; + if (v->Tc > iq_max) v->Tc = iq_max; + + if (v->Ta < -iq_max) v->Ta = -iq_max; + if (v->Tb < -iq_max) v->Tb = -iq_max; + if (v->Tc < -iq_max) v->Tc = -iq_max; + +} + + diff --git a/Inu/Src/N12_Libs/svgen_mf.c b/Inu/Src/N12_Libs/svgen_mf.c new file mode 100644 index 0000000..3570aa9 --- /dev/null +++ b/Inu/Src/N12_Libs/svgen_mf.c @@ -0,0 +1,164 @@ +/*===================================================================================== + File name: SVGEN_MF.C (IQ version) + + Originator: Digital Control Systems Group + Texas Instruments + + Description: Space-vector PWM generation based on magnitude and frequency components + +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +-------------------------------------------------------------------------------------*/ +#include "IQmathLib.h" // Include header for IQmath library +#include "dmctype.h" + + +#include "svgen_mf.h" + +#include + + +static _iq iq1_0=_IQ(1.0); +static _iq iq6_0=_IQ(6.0); +static _iq iq0_5=_IQ(0.5); +static _iq iq2_0=_IQ(2.0); + +static _iq iq3_0=_IQ(3.0); +static _iq iq4_0=_IQ(4.0); +static _iq iq5_0=_IQ(5.0); + + +//#pragma CODE_SECTION(svgenmf_calc,".fast_run"); +void svgenmf_calc(SVGENMF *v) +{ + _iq StepAngle,EntryOld,dx,dy; + _iq T = iq1_0;//_IQ(1.0); + + // Normalise the freq input to appropriate step angle + // Here, 1 pu. = 60 degree +//#ifdef DOUBLE_UPDATE_PWM +// StepAngle = (_IQmpy(v->Freq,v->FreqMax))>>1; // decrise step /2 for double update +//#else + StepAngle = _IQmpy(v->Freq,v->FreqMax); // normal step +//#endif + + // Calculate new angle alpha + EntryOld = v->NewEntry; + + v->Full_Alpha = v->Full_Alpha + StepAngle; + + if (v->Full_Alpha < 0) + v->Full_Alpha = v->Full_Alpha+iq6_0; + + if (v->Full_Alpha >= iq6_0) + v->Full_Alpha = v->Full_Alpha-iq6_0; + + + //new sector detect + if (v->Full_Alpha >= iq5_0) + { + v->SectorPointer=5; + v->Alpha = v->Full_Alpha-iq5_0; + } + else + if (v->Full_Alpha >= iq4_0) + { + v->SectorPointer=4; + v->Alpha = v->Full_Alpha-iq4_0; + } + else + if (v->Full_Alpha >= iq3_0) + { + v->SectorPointer=3; + v->Alpha = v->Full_Alpha-iq3_0; + } + else + if (v->Full_Alpha >= iq2_0) + { + v->SectorPointer=2; + v->Alpha = v->Full_Alpha-iq2_0; + } + else + if (v->Full_Alpha >= iq1_0) + { + v->SectorPointer=1; + v->Alpha = v->Full_Alpha-iq1_0; + } + else + { + v->SectorPointer=0; + v->Alpha = v->Full_Alpha; + } + + +// v->Alpha = v->Alpha + StepAngle; +// if (v->Alpha >= iq1_0) +// v->Alpha = v->Alpha-iq1_0; + + + v->NewEntry = v->Alpha; + + dy = _IQsin(_IQmpy(v->NewEntry,PI_THIRD)); // dy = sin(NewEntry) + dx = _IQsin(PI_THIRD-_IQmpy(v->NewEntry,PI_THIRD)); // dx = sin(60-NewEntry) + + // Determine which sector +// if (v->NewEntry-EntryOld<0) +// { +// if (v->SectorPointer==5) +// v->SectorPointer = 0; +// else +// v->SectorPointer = v->SectorPointer + 1; +// } + + if (v->SectorPointer==0) // Sector 1 calculations - a,b,c --> a,b,c + { + v->Ta = _IQmpy(iq0_5,(T-dx-dy)); + v->Tb = v->Ta + dx; + v->Tc = T - v->Ta; + } + else if (v->SectorPointer==1) // Sector 2 calculations - a,b,c --> b,a,c & dx <--> dy + { + v->Tb = _IQmpy(iq0_5,(T-dx-dy)); + v->Ta = v->Tb + dy; + v->Tc = T - v->Tb; + } + else if (v->SectorPointer==2) // Sector 3 calculations - a,b,c --> b,c,a + { + v->Tb = _IQmpy(iq0_5,(T-dx-dy)); + v->Tc = v->Tb + dx; + v->Ta = T - v->Tb; + } + else if (v->SectorPointer==3) // Sector 4 calculations - a,b,c --> c,b,a & dx <--> dy + { + v->Tc = _IQmpy(iq0_5,(T-dx-dy)); + v->Tb = v->Tc + dy; + v->Ta = T - v->Tc; + } + else if (v->SectorPointer==4) // Sector 5 calculations - a,b,c --> c,a,b + { + v->Tc = _IQmpy(iq0_5,(T-dx-dy)); + v->Ta = v->Tc + dx; + v->Tb = T - v->Tc; + } + else if (v->SectorPointer==5) // Sector 6 calculations - a,b,c --> a,c,b & dx <--> dy + { + v->Ta = _IQmpy(iq0_5,(T-dx-dy)); + v->Tc = v->Ta + dy; + v->Tb = T - v->Ta; + } + +// Convert the unsigned GLOBAL_Q format (ranged (0,1)) -> signed GLOBAL_Q format (ranged (-1,1)) +// Then, multiply with a gain and add an offset. + v->Ta = _IQmpy(iq2_0,(v->Ta-iq0_5)); + v->Ta = _IQmpy(v->Gain,v->Ta) + v->Offset; + + v->Tb = _IQmpy(iq2_0,(v->Tb-iq0_5)); + v->Tb = _IQmpy(v->Gain,v->Tb) + v->Offset; + + v->Tc = _IQmpy(iq2_0,(v->Tc-iq0_5)); + v->Tc = _IQmpy(v->Gain,v->Tc) + v->Offset; + +} + diff --git a/Inu/Src/N12_Libs/svgen_mf.h b/Inu/Src/N12_Libs/svgen_mf.h new file mode 100644 index 0000000..d7188ef --- /dev/null +++ b/Inu/Src/N12_Libs/svgen_mf.h @@ -0,0 +1,46 @@ +/* ================================================================================= +File name: SVGEN_MF.H (IQ version) + +Originator: Digital Control Systems Group + Texas Instruments + +Description: +Header file containing constants, data type definitions, and +function prototypes for the SVGEN_MF. +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +------------------------------------------------------------------------------*/ +#ifndef __SVGEN_MF_H__ +#define __SVGEN_MF_H__ + +typedef struct { _iq Gain; // Input: reference gain voltage (pu) + _iq Offset; // Input: reference offset voltage (pu) + _iq Freq; // Input: reference frequency (pu) + _iq FreqMax; // Parameter: Maximum step angle = 6*base_freq*T (pu) + _iq Alpha; // History: Sector angle (pu) + _iq Full_Alpha; + _iq NewEntry; // History: Sine (angular) look-up pointer (pu) + Uint32 SectorPointer; // History: Sector number (Q0) - independently with global Q + _iq Ta; // Output: reference phase-a switching function (pu) + _iq Tb; // Output: reference phase-b switching function (pu) + _iq Tc; // Output: reference phase-c switching function (pu) + void (*calc)(); // Pointer to calculation function + } SVGENMF; + +typedef SVGENMF *SVGENMF_handle; +/*----------------------------------------------------------------------------- +Default initalizer for the SVGENMF object. +-----------------------------------------------------------------------------*/ +#define SVGENMF_DEFAULTS { 0,0,0,0,0,0,0,0,0,0,0, \ + (void (*)(Uint32))svgenmf_calc } + +#define PI_THIRD _IQ(1.04719755119660) // This is 60 degree +/*------------------------------------------------------------------------------ +Prototypes for the functions in SVGEN_MF.C +------------------------------------------------------------------------------*/ +void svgenmf_calc(SVGENMF_handle); + +#endif // __SVGEN_MF_H__ + diff --git a/Inu/Src/N12_Libs/uf_alg_ing.c b/Inu/Src/N12_Libs/uf_alg_ing.c new file mode 100644 index 0000000..378b2c2 --- /dev/null +++ b/Inu/Src/N12_Libs/uf_alg_ing.c @@ -0,0 +1,736 @@ +/* + * uf_alg_ing.c + * + * Created on: 10 . 2020 . + * Author: yura + */ + + + +#include "IQmathLib.h" +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File + + + +#include "uf_alg_ing.h" + +#include +#include +#include +#include +#include +#include + +#include "math_pi.h" +#include "svgen_dq.h" +#include "svgen_mf.h" +#include "dq_to_alphabeta_cos.h" +#include "params_norma.h" + + + +//#pragma DATA_SECTION(svgen_mf1,".fast_vars"); +SVGENMF svgen_mf1 = SVGENMF_DEFAULTS; + +//#pragma DATA_SECTION(svgen_mf2,".fast_vars"); +//SVGENMF svgen_mf2 = SVGENMF_DEFAULTS; + + +//#pragma DATA_SECTION(svgen_dq_1,".fast_vars"); +SVGENDQ svgen_dq_1 = SVGENDQ_DEFAULTS; +//#pragma DATA_SECTION(svgen_dq_2,".fast_vars"); +//SVGENDQ svgen_dq_2 = SVGENDQ_DEFAULTS; + + +UF_ALG_VALUE uf_alg = UF_ALG_VALUE_DEFAULT; + +void InitVariablesSvgen_Ing(unsigned int freq) +{ + + + + svgen_dq_1.Ualpha = 0; + svgen_dq_1.Ubeta = 0; + + // svgen_dq_2.Ualpha = 0; + // svgen_dq_2.Ubeta = 0; + + uf_alg.hz_to_angle = _IQ(2.0 * PI * NORMA_FROTOR / freq ); // +// uf_alg.hz_to_angle = _IQ(2.0 * PI * NORMA_FROTOR / freq /2.0 ); // + + + + +// Initialize the SVGEN_MF module +// svgen_mf1.FreqMax = _IQ(6*NORMA_FROTOR/freq); +// svgen_mf2.FreqMax = _IQ(6*NORMA_FROTOR/freq); +// +// +// svgen_mf2.Offset=_IQ(0); +// svgen_mf1.Offset=_IQ(0); + + init_alpha_Ing(0); + + +} + + + + + + + + +void init_alpha_Ing(unsigned int master_slave) +{ + + + uf_alg.winding_displacement_bs1 = 0; + uf_alg.winding_displacement_bs2 = 0; + + +// power_ain1.init(&power_ain1); +// power_ain2.init(&power_ain2); + +// svgen_mf1.NewEntry = 0;//_IQ(0.5); +// svgen_mf2.NewEntry = 0; + +// svgen_mf1.SectorPointer = 0; +// svgen_mf2.SectorPointer = 0; + +// 0 +// svgen_mf1.Alpha = _IQ(0); +// svgen_mf2.Alpha = _IQ(0); + +// +// +// + +#if (SETUP_SDVIG_OBMOTKI == SDVIG_OBMOTKI_30_PLUS) +// 30 . + // , 60 =1. +// svgen_mf1.Alpha = _IQ(0.5); +// svgen_mf2.Alpha = _IQ(0); +// +// svgen_mf1.Full_Alpha = svgen_mf1.Alpha; +// svgen_mf2.Full_Alpha = svgen_mf2.Alpha; + + // + uf_alg.winding_displacement_bs1 = CONST_IQ_PI6; //_IQ(0.5); + uf_alg.winding_displacement_bs2 = 0; + +#else + + +#if (SETUP_SDVIG_OBMOTKI == SDVIG_OBMOTKI_30_MINUS) +// -30 . + // , 60 =1. +// svgen_mf1.Alpha = _IQ(0); +// svgen_mf2.Alpha = _IQ(0.5); +// svgen_mf1.Full_Alpha = svgen_mf1.Alpha; +// svgen_mf2.Full_Alpha = svgen_mf2.Alpha; +// + // + uf_alg.winding_displacement_bs2 = CONST_IQ_PI6; // _IQ(0.5); + uf_alg.winding_displacement_bs1 = 0; + +#else + +#if (SETUP_SDVIG_OBMOTKI == SDVIG_OBMOTKI_ZERO) +// 0 . +// svgen_mf1.Alpha = _IQ(0); +// svgen_mf2.Alpha = _IQ(0); +// svgen_mf1.Full_Alpha = svgen_mf1.Alpha; +// svgen_mf2.Full_Alpha = svgen_mf2.Alpha; + + uf_alg.winding_displacement_bs1 = 0; + uf_alg.winding_displacement_bs2 = 0; + +#else + #error "!!!!!! SETUP_SDVIG_OBMOTKI params_motor.h!!!" + + +#endif + +#endif + +#endif + + + + +} + +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(uf_disbalance_uzpt,".fast_run"); +void uf_disbalance_uzpt(_iq Uzad_uf1, unsigned int disable_alg_u_disbalance, _iq kplus_u_disbalance, _iq k_u_disbalance, + _iq U_1, _iq U_2, + _iq Uzad_max, + _iq *Kplus_out) +{ + _iq pwm_t,delta_U,Uplus,Uminus; + volatile _iq Kplus; + static _iq u1=0,u2=0; + static _iq delta_U_minimal = _IQ (25.0/NORMA_ACP); + + volatile _iq KplusMax; + + +// change_pwm_freq(Fzad_uf); + + + Uplus = U_2;//filter.iqU_2_fast; // Uplus U2 .. "-" - + Uminus = U_1;//filter.iqU_1_fast; + + delta_U = Uplus - Uminus; + + if (_IQabs(delta_U) < delta_U_minimal) + delta_U = 0; + + if (disable_alg_u_disbalance==0) + { + if (kplus_u_disbalance!=0) // , , . + { + Kplus = kplus_u_disbalance; + } + else + { + if (delta_U != 0) + { + Kplus = _IQmpy(k_u_disbalance, _IQmpy(Uzad_uf1, (_IQdiv( (Uplus-Uminus), (Uplus+Uminus) )) ) );//CONST_1 + _IQmpy(k_u_disbalance, _IQmpy(Uzad_uf1, ( _IQdiv(_IQmpy(CONST_2,Uplus),(Uplus+Uminus)) - CONST_1 ) ) ); + } + else + { + Kplus = 0; + } + } + } + else + { +// Uplus = 0; +// Uminus = 0; +// delta_U = 0; + Kplus = 0; + } + + KplusMax = _IQmpy(Uzad_uf1,CONST_IQ_05); + + if (Kplus>=KplusMax) + { + Kplus = KplusMax; + } + + if (Kplus<=-KplusMax) + { + Kplus = -KplusMax; + } + + + *Kplus_out = Kplus; + + +} +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// + + + + +//////////////////////////////////////////////////////////////////////////// +// kplus_u_disbalance = 0, , +// enable_alg_u_disbalance - +// k_u_disbalance - . . +//////////////////////////////////////////////////////////////////////////// +//#pragma CODE_SECTION(uf_const_f_24_Ing,".fast_run"); +void uf_const_f_24_Ing(_iq Fzad_uf1,_iq Fzad_uf2,_iq Uzad_uf1, _iq Uzad_uf2, + unsigned int enable_alg_u_disbalance, _iq kplus_u_disbalance, _iq k_u_disbalance, + _iq U_1, _iq U_2, unsigned int flag_km_0, + _iq Uzad_max, + _iq *Kplus_out) +{ + + _iq pwm_t,delta_U,Uplus,Uminus; + _iq Kplus; + static _iq u1=0,u2=0; + + volatile _iq KplusMax; + + + uf_disbalance_uzpt(Uzad_uf1, enable_alg_u_disbalance, kplus_u_disbalance, k_u_disbalance, U_1, U_2, Uzad_max, &Kplus); +// change_pwm_freq(Fzad_uf); + + *Kplus_out = Kplus; + + +///////////////////////////////////////// + svgen_mf1.Gain = _IQsat(Uzad_uf1,Uzad_max,0); // Pass inputs to svgen_mf1 + svgen_mf1.Freq = Fzad_uf1; // Pass inputs to svgen_mf1 + +// svgen_mf2.Gain = _IQsat(Uzad_uf2,Uzad_max,0);; // Pass inputs to svgen_mf1 +// svgen_mf2.Freq = Fzad_uf2; // Pass inputs to svgen_mf1 + + svgen_mf1.calc(&svgen_mf1); // Call compute function for svgen_mf1 + // svgen_mf2.calc(&svgen_mf2); // Call compute function for svgen_mf2 + ///////////////////////////////////////// + + + + + + + + + /* + logpar.log1 = (int16)(_IQtoIQ15(Uzad_uf1)); + logpar.log2 = (int16)(_IQtoIQ15(Fzad_uf1)); + logpar.log3 = (int16)((svgen_pwm24_1.Ta_0)); + logpar.log4 = (int16)((svgen_pwm24_1.Ta_1)); + logpar.log5 = (int16)(_IQtoIQ15(svgen_mf1.Ta)); + logpar.log6 = (int16)(_IQtoIQ15(_IQdiv(Kplus,CONST_IQ_10))); + logpar.log7 = (int16)(_IQtoIQ15(_IQdiv(Kminus,CONST_IQ_10))); + logpar.log8 = (int16)(_IQtoIQ15(Uplus)); + logpar.log9 = (int16)(_IQtoIQ15(Uminus)); + +*/ +// 1 +// a + pwm_t = correct_balance_uzpt_pwm24 (svgen_mf1.Ta, Kplus); + recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_1, &svgen_pwm24_1.Ta_0, &svgen_pwm24_1.Ta_1, &svgen_pwm24_1.Ta_imp, pwm_t); +// b + pwm_t = correct_balance_uzpt_pwm24 (svgen_mf1.Tb, Kplus); + recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_1, &svgen_pwm24_1.Tb_0, &svgen_pwm24_1.Tb_1, &svgen_pwm24_1.Tb_imp,pwm_t); +// c + pwm_t = correct_balance_uzpt_pwm24 (svgen_mf1.Tc, Kplus); + recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_1, &svgen_pwm24_1.Tc_0, &svgen_pwm24_1.Tc_1, &svgen_pwm24_1.Tc_imp,pwm_t); + +// 2 + svgen_pwm24_2.Ta_0 = svgen_pwm24_1.Ta_0; + svgen_pwm24_2.Ta_1 = svgen_pwm24_1.Ta_1; + svgen_pwm24_2.Tb_0 = svgen_pwm24_1.Tb_0; + svgen_pwm24_2.Tb_1 = svgen_pwm24_1.Tb_1; + svgen_pwm24_2.Tc_0 = svgen_pwm24_1.Tc_0; + svgen_pwm24_2.Tc_1 = svgen_pwm24_1.Tc_1; + +// a +// pwm_t = correct_balance_uzpt_pwm24 (svgen_mf1.Ta, Kplus); +// recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_2, &svgen_pwm24_2.Ta_0, &svgen_pwm24_2.Ta_1, &svgen_pwm24_2.Ta_imp,pwm_t); +//// b +// pwm_t = correct_balance_uzpt_pwm24 (svgen_mf1.Tb, Kplus); +// recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_2, &svgen_pwm24_2.Tb_0, &svgen_pwm24_2.Tb_1, &svgen_pwm24_2.Tb_imp,pwm_t); +//// c2 +// pwm_t = correct_balance_uzpt_pwm24 (svgen_mf1.Tc, Kplus); +// recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_2, &svgen_pwm24_2.Tc_0, &svgen_pwm24_2.Tc_1, &svgen_pwm24_2.Tc_imp,pwm_t); +// + +//// + if (flag_km_0) + { + svgen_pwm24_1.prev_level = V_PWM24_PREV_PWM_WORK_KM0; + svgen_pwm24_2.prev_level = V_PWM24_PREV_PWM_WORK_KM0; + } + else + { + svgen_pwm24_1.prev_level = V_PWM24_PREV_PWM_WORK; + svgen_pwm24_2.prev_level = V_PWM24_PREV_PWM_WORK; + } + + + +///////// +///////// + +// logpar.log10 = (int16)((svgen_pwm24_1.Ta_0)); +// logpar.log11 = (int16)((svgen_pwm24_1.Ta_1)); + + + +} + + +//////////////////////////////////////////////////////////// +#pragma CODE_SECTION(test_calc_simple_dq_pwm24_Ing,".v_24pwm_run"); +void test_calc_simple_dq_pwm24_Ing(_iq Fzad_uf1, + _iq Uzad_uf1, + unsigned int disable_alg_u_disbalance, + _iq kplus_u_disbalance, + _iq k_u_disbalance, + _iq U_1, + _iq U_2, + unsigned int flag_km_0, + _iq Uzad_max, + _iq master_tetta, + _iq master_Uzad_uf1, + unsigned int master, + unsigned int n_bs, + _iq *Kplus_out, + _iq *tetta_out, + _iq *Uzad_out +) +{ +// static _iq hz_to_angle = _IQ(2.0 * PI * NORMA_FROTOR / FREQ_PWM / 2.0); +// static _iq tetta = 0; + _iq pwm_t; + _iq Kplus; + _iq Ud = 0; + _iq Uq = 0; + _iq add_tetta = 0; + + DQ_TO_ALPHABETA dq_to_ab = DQ_TO_ALPHABETA_DEFAULTS; + + //////////////////////////////////////// + + uf_disbalance_uzpt(Uzad_uf1, disable_alg_u_disbalance, kplus_u_disbalance, k_u_disbalance, + U_1, U_2, + Uzad_max, + &Kplus); + + + //////////////////////////////////////// + + + //////////////////////////////////////// + //////////////////////////////////////// + if (master==MODE_MASTER) + { + // master + add_tetta = _IQmpy(Fzad_uf1, uf_alg.hz_to_angle); + uf_alg.tetta += add_tetta; + Ud = 0; + Uq = _IQsat(Uzad_uf1,Uzad_max,0); + } + else + if (master==MODE_SLAVE) + { + // slave + add_tetta = 0; + uf_alg.tetta = master_tetta; + Ud = 0; + Uq = _IQsat(master_Uzad_uf1,Uzad_max,0); + } + else + { + // ! + Ud = 0; + Uq = 0; + add_tetta = 0; + uf_alg.tetta = 0; + } + //////////////////////////////////////// + //////////////////////////////////////// + + + + uf_alg.Ud = Ud; + uf_alg.Uq = Uq; + + if (uf_alg.tetta > CONST_IQ_2PI) + { + uf_alg.tetta -= CONST_IQ_2PI; + } + + if (uf_alg.tetta < 0) + { + uf_alg.tetta += CONST_IQ_2PI; + } + + if (n_bs==0) + uf_alg.tetta_bs = uf_alg.tetta + uf_alg.winding_displacement_bs1; + else + uf_alg.tetta_bs = uf_alg.tetta + uf_alg.winding_displacement_bs2; + + dq_to_ab.Tetta = uf_alg.tetta_bs; + //////////////////////////////////////// + //////////////////////////////////////// + + dq_to_ab.Ud = Ud; + dq_to_ab.Uq = Uq; + dq_to_ab.calc2(&dq_to_ab); + + svgen_dq_1.Ualpha = dq_to_ab.Ualpha; + svgen_dq_1.Ubeta = dq_to_ab.Ubeta; + //////////////////////////////////////// + + uf_alg.Ualpha = dq_to_ab.Ualpha; + uf_alg.Ubeta = dq_to_ab.Ubeta; + //////////////////////////////////////// + + +// svgen_dq_1.Ualpha = 0; +// svgen_dq_1.Ubeta = 0; + + svgen_dq_1.calc(&svgen_dq_1); + + uf_alg.svgen_dq_Ta = svgen_dq_1.Ta; + uf_alg.svgen_dq_Tb = svgen_dq_1.Tb; + uf_alg.svgen_dq_Tc = svgen_dq_1.Tc; + //////////////////////////////////////// + + +// dq_to_ab.Tetta = uf_alg.tetta; +// dq_to_ab.Ud = Ud; +// dq_to_ab.Uq = Uq; +// dq_to_ab.calc2(&dq_to_ab); +// +// svgen_dq_2.Ualpha = dq_to_ab.Ualpha; +// svgen_dq_2.Ubeta = dq_to_ab.Ubeta; +// +// svgen_dq_2.calc(&svgen_dq_2); + +// 1 +// a + pwm_t = correct_balance_uzpt_pwm24 (svgen_dq_1.Ta, Kplus); + recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_1, &svgen_pwm24_1.Ta_0, &svgen_pwm24_1.Ta_1, &svgen_pwm24_1.Ta_imp, pwm_t); +// b + pwm_t = correct_balance_uzpt_pwm24 (svgen_dq_1.Tb, Kplus); + recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_1, &svgen_pwm24_1.Tb_0, &svgen_pwm24_1.Tb_1, &svgen_pwm24_1.Tb_imp,pwm_t); +// c + pwm_t = correct_balance_uzpt_pwm24 (svgen_dq_1.Tc, Kplus); + recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_1, &svgen_pwm24_1.Tc_0, &svgen_pwm24_1.Tc_1, &svgen_pwm24_1.Tc_imp,pwm_t); + +// 2 1 .. . Ingeteam + svgen_pwm24_2.Ta_0 = svgen_pwm24_1.Ta_0; + svgen_pwm24_2.Ta_1 = svgen_pwm24_1.Ta_1; + svgen_pwm24_2.Tb_0 = svgen_pwm24_1.Tb_0; + svgen_pwm24_2.Tb_1 = svgen_pwm24_1.Tb_1; + svgen_pwm24_2.Tc_0 = svgen_pwm24_1.Tc_0; + svgen_pwm24_2.Tc_1 = svgen_pwm24_1.Tc_1; + +// +//// a +// pwm_t = correct_balance_uzpt_pwm24 (svgen_dq_1.Ta, Kplus); +// recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_2, &svgen_pwm24_2.Ta_0, &svgen_pwm24_2.Ta_1, &svgen_pwm24_2.Ta_imp,pwm_t); +//// b +// pwm_t = correct_balance_uzpt_pwm24 (svgen_dq_1.Tb, Kplus); +// recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_2, &svgen_pwm24_2.Tb_0, &svgen_pwm24_2.Tb_1, &svgen_pwm24_2.Tb_imp,pwm_t); +//// c2 +// pwm_t = correct_balance_uzpt_pwm24 (svgen_dq_1.Tc, Kplus); +// recalc_time_pwm_minimal_2_xilinx_pwm24 (&svgen_pwm24_2, &svgen_pwm24_2.Tc_0, &svgen_pwm24_2.Tc_1, &svgen_pwm24_2.Tc_imp,pwm_t); + + //////////////////////////////////////// + //////////////////////////////////////// + +//// + if (flag_km_0) + { + svgen_pwm24_1.prev_level = V_PWM24_PREV_PWM_WORK_KM0; + svgen_pwm24_2.prev_level = V_PWM24_PREV_PWM_WORK_KM0; + } + else + { + svgen_pwm24_1.prev_level = V_PWM24_PREV_PWM_WORK; + svgen_pwm24_2.prev_level = V_PWM24_PREV_PWM_WORK; + } + + //////////////////////////////////////// + //////////////////////////////////////// + + +// logpar.log1 = (int16)(_IQtoIQ15(uz1)); +// logpar.log2 = (int16)(_IQtoIQ15(fz1)); +// logpar.log3 = (int16)(_IQtoIQ15(Ud)); +// logpar.log4 = (int16)(_IQtoIQ15(Uq)); +// logpar.log5 = (int16)(_IQtoIQ15(svgen_dq_1.Ualpha)); +// logpar.log6 = (int16)(_IQtoIQ15(svgen_dq_1.Ubeta)); +// logpar.log7 = (int16)(_IQtoIQ15(svgen_dq_1.Ta)); +// logpar.log8 = (int16)(_IQtoIQ15(svgen_dq_1.Tb)); +// logpar.log9 = (int16)(_IQtoIQ15(svgen_dq_1.Tc)); +// logpar.log10 = (int16)(_IQtoIQ12(analog.tetta)); +// logpar.log11 = (int16)(svgen_pwm24_1.Ta_0.Ti); +// logpar.log12 = (int16)((svgen_pwm24_1.Ta_1.Ti)); +// logpar.log13 = (int16)(svgen_pwm24_1.Tb_0.Ti); +// logpar.log14 = (int16)((svgen_pwm24_1.Tb_1.Ti)); +// logpar.log15 = (int16)(svgen_pwm24_1.Tc_0.Ti); +// logpar.log16 = (int16)((svgen_pwm24_1.Tc_1.Ti)); + + +// svgen_pwm24_1.calc(&svgen_pwm24_1); +// svgen_pwm24_2.calc(&svgen_pwm24_2); + + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + +// set_predel_dshim24_simple0(&svgen_pwm24_1.Ta_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// set_predel_dshim24_simple1(&svgen_pwm24_1.Ta_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// +// set_predel_dshim24_simple0(&svgen_pwm24_1.Tb_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// set_predel_dshim24_simple1(&svgen_pwm24_1.Tb_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// +// set_predel_dshim24_simple0(&svgen_pwm24_1.Tc_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// set_predel_dshim24_simple1(&svgen_pwm24_1.Tc_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// +// set_predel_dshim24_simple0(&svgen_pwm24_2.Ta_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// set_predel_dshim24_simple1(&svgen_pwm24_2.Ta_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// +// set_predel_dshim24_simple0(&svgen_pwm24_2.Tb_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// set_predel_dshim24_simple1(&svgen_pwm24_2.Tb_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// +// set_predel_dshim24_simple0(&svgen_pwm24_2.Tc_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); +// set_predel_dshim24_simple1(&svgen_pwm24_2.Tc_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + + + *Uzad_out = Uq; + + if (master==MODE_MASTER) + *tetta_out = uf_alg.tetta + add_tetta; // , .. slave ? + else + *tetta_out = uf_alg.tetta; + + *Kplus_out = Kplus; + +} + +#pragma CODE_SECTION(test_calc_vect_dq_pwm24_Ing,".v_24pwm_run"); +void test_calc_vect_dq_pwm24_Ing(_iq Theta_zad,_iq Ud_zad, _iq Uq_zad, + unsigned int disable_alg_u_disbalance, _iq kplus_u_disbalance, _iq k_u_disbalance, + _iq U_1, _iq U_2, unsigned int flag_km_0, + _iq Uzad_max, + unsigned int master, + unsigned int n_bs, + _iq *Kplus_out, + _iq *Uzad_out ) +{ + _iq Kplus; + _iq Ud = 0; + _iq Uq = 0; + _iq Umod = 0; + _iq pwm_t; + + DQ_TO_ALPHABETA dq_to_ab = DQ_TO_ALPHABETA_DEFAULTS; + + static _iq max_Km = _IQ(MAX_ZADANIE_K_M); + static _iq max_Km_square = _IQ(MAX_ZADANIE_K_M * MAX_ZADANIE_K_M); + + //////////////////////////////////////// + Umod = _IQsqrt(_IQmpy(Ud_zad, Ud_zad) + _IQmpy(Uq_zad, Uq_zad)); + if (Umod > max_Km) { + Uq_zad = _IQsqrt(max_Km_square - _IQmpy(Ud_zad, Ud_zad)); + } + Umod = _IQsqrt(_IQmpy(Ud_zad, Ud_zad) + _IQmpy(Uq_zad, Uq_zad)); + + uf_disbalance_uzpt(Umod, disable_alg_u_disbalance, kplus_u_disbalance, + k_u_disbalance, U_1, U_2, Uzad_max, &Kplus); + *Kplus_out = Kplus; + + *Uzad_out = Umod; + //////////////////////////////////////// + //////////////////////////////////////// + if (master == MODE_MASTER) + { + // master + uf_alg.tetta = Theta_zad; + Ud = Ud_zad; + Uq = Uq_zad; //_IQsat(Uzad_uf1,Uzad_max,0); + } + else if (master == MODE_SLAVE) + { + // slave + uf_alg.tetta = Theta_zad; + Ud = Ud_zad; + Uq = Uq_zad; //_IQsat(master_Uzad_uf1,Uzad_max,0); + } + else + { + // ! + Ud = 0; + Uq = 0; + uf_alg.tetta = 0; + } + //////////////////////////////////////// + //////////////////////////////////////// + + uf_alg.Ud = Ud; + uf_alg.Uq = Uq; + + if (uf_alg.tetta > CONST_IQ_2PI) + { + uf_alg.tetta -= CONST_IQ_2PI; + } + + if (uf_alg.tetta < 0) + { + uf_alg.tetta += CONST_IQ_2PI; + } + + if (n_bs == 0) + uf_alg.tetta_bs = uf_alg.tetta + uf_alg.winding_displacement_bs1; + else + uf_alg.tetta_bs = uf_alg.tetta + uf_alg.winding_displacement_bs2; + + dq_to_ab.Tetta = uf_alg.tetta_bs; + dq_to_ab.Ud = Ud; + dq_to_ab.Uq = Uq; + dq_to_ab.calc2(&dq_to_ab); + + svgen_dq_1.Ualpha = dq_to_ab.Ualpha; + svgen_dq_1.Ubeta = dq_to_ab.Ubeta; + //////////////////////////////////////// + + uf_alg.Ualpha = dq_to_ab.Ualpha; + uf_alg.Ubeta = dq_to_ab.Ubeta; + + svgen_dq_1.calc(&svgen_dq_1); + + uf_alg.svgen_dq_Ta = svgen_dq_1.Ta; + uf_alg.svgen_dq_Tb = svgen_dq_1.Tb; + uf_alg.svgen_dq_Tc = svgen_dq_1.Tc; + +// 1 +// a + pwm_t = correct_balance_uzpt_pwm24(svgen_dq_1.Ta, Kplus); + recalc_time_pwm_minimal_2_xilinx_pwm24(&svgen_pwm24_1, &svgen_pwm24_1.Ta_0, + &svgen_pwm24_1.Ta_1, + &svgen_pwm24_1.Ta_imp, pwm_t); +// b + pwm_t = correct_balance_uzpt_pwm24(svgen_dq_1.Tb, Kplus); + recalc_time_pwm_minimal_2_xilinx_pwm24(&svgen_pwm24_1, &svgen_pwm24_1.Tb_0, + &svgen_pwm24_1.Tb_1, + &svgen_pwm24_1.Tb_imp, pwm_t); +// c + pwm_t = correct_balance_uzpt_pwm24(svgen_dq_1.Tc, Kplus); + recalc_time_pwm_minimal_2_xilinx_pwm24(&svgen_pwm24_1, &svgen_pwm24_1.Tc_0, + &svgen_pwm24_1.Tc_1, + &svgen_pwm24_1.Tc_imp, pwm_t); + +// 2 1 .. . Ingeteam + + svgen_pwm24_2.Ta_0 = svgen_pwm24_1.Ta_0; + svgen_pwm24_2.Ta_1 = svgen_pwm24_1.Ta_1; + svgen_pwm24_2.Tb_0 = svgen_pwm24_1.Tb_0; + svgen_pwm24_2.Tb_1 = svgen_pwm24_1.Tb_1; + svgen_pwm24_2.Tc_0 = svgen_pwm24_1.Tc_0; + svgen_pwm24_2.Tc_1 = svgen_pwm24_1.Tc_1; + + + +//// a +// pwm_t = correct_balance_uzpt_pwm24(svgen_dq_1.Ta, Kplus); +// recalc_time_pwm_minimal_2_xilinx_pwm24(&svgen_pwm24_2, &svgen_pwm24_2.Ta_0, +// &svgen_pwm24_2.Ta_1, +// &svgen_pwm24_2.Ta_imp, pwm_t); +//// b +// pwm_t = correct_balance_uzpt_pwm24(svgen_dq_1.Tb, Kplus); +// recalc_time_pwm_minimal_2_xilinx_pwm24(&svgen_pwm24_2, &svgen_pwm24_2.Tb_0, +// &svgen_pwm24_2.Tb_1, +// &svgen_pwm24_2.Tb_imp, pwm_t); +//// c2 +// pwm_t = correct_balance_uzpt_pwm24(svgen_dq_1.Tc, Kplus); +// recalc_time_pwm_minimal_2_xilinx_pwm24(&svgen_pwm24_2, &svgen_pwm24_2.Tc_0, +// &svgen_pwm24_2.Tc_1, +// &svgen_pwm24_2.Tc_imp, pwm_t); + + //////////////////////////////////////// + //////////////////////////////////////// + + +} + + + diff --git a/Inu/Src/N12_Libs/uf_alg_ing.h b/Inu/Src/N12_Libs/uf_alg_ing.h new file mode 100644 index 0000000..209d9ce --- /dev/null +++ b/Inu/Src/N12_Libs/uf_alg_ing.h @@ -0,0 +1,93 @@ +/* + * uf_alg.h + * + * Created on: 10 . 2020 . + * Author: yura + */ + +#ifndef _UF_ALG_ING_H_ +#define _UF_ALG_ING_H_ + +#include "svgen_mf.h" + + +#define CONST_IQ_05 8388608 //0.5 +#define CONST_IQ_1 16777216 //1.0 + + + +/* UF ALG */ +typedef struct +{ + + _iq tetta; + _iq tetta_bs; + + + _iq winding_displacement_bs1; + _iq winding_displacement_bs2; + + _iq hz_to_angle; + _iq Kplus; + + _iq Ud; + _iq Uq; + + _iq Ualpha; + _iq Ubeta; + + _iq svgen_dq_Ta; + _iq svgen_dq_Tb; + _iq svgen_dq_Tc; + + +} UF_ALG_VALUE; + + + + +#define UF_ALG_VALUE_DEFAULT {0,0,0,0,0,0,0,0,0,0,0,0,0} + + + +extern UF_ALG_VALUE uf_alg ; + +extern SVGENMF svgen_mf1; +extern SVGENMF svgen_mf2; + + +//void uf_const_f(_iq Fzad_uf1,_iq Fzad_uf2,_iq Uzad_uf1, _iq Uzad_uf2, int Revers,unsigned int enable_alg_u_disbalance); + +void uf_const_f_24_Ing(_iq Fzad_uf1,_iq Fzad_uf2,_iq Uzad_uf1, _iq Uzad_uf2, unsigned int enable_alg_u_disbalance, _iq kplus_u_disbalance, _iq k_u_disbalance, + _iq U_1, _iq U_2, unsigned int flag_km_0, + _iq Uzad_max, + _iq *Kplus_out); + +void uf_disbalance_uzpt(_iq Uzad_uf1, unsigned int disable_alg_u_disbalance, _iq kplus_u_disbalance, _iq k_u_disbalance, + _iq U_1, _iq U_2, + _iq Uzad_max, + _iq *Kplus_out); + +void init_alpha_Ing(unsigned int bs); +void InitVariablesSvgen_Ing(unsigned int freq); +void test_calc_simple_dq_pwm24_Ing(_iq Fzad_uf1,_iq Uzad_uf1, unsigned int disable_alg_u_disbalance, _iq kplus_u_disbalance, _iq k_u_disbalance, + _iq U_1, _iq U_2, unsigned int flag_km_0, + _iq Uzad_max, + _iq master_tetta, + _iq master_Uzad_uf1, + unsigned int master, + unsigned int n_bs, + _iq *Kplus_out, + _iq *tetta_out, + _iq *Uzad_out); + +void test_calc_vect_dq_pwm24_Ing(_iq Theta_zad,_iq Ud_zad, _iq Uq_zad, + unsigned int disable_alg_u_disbalance, _iq kplus_u_disbalance, _iq k_u_disbalance, + _iq U_1, _iq U_2, unsigned int flag_km_0, + _iq Uzad_max, + unsigned int master, + unsigned int n_bs, + _iq *Kplus_out, + _iq *Uzad_out); + +#endif /* _UF_ALG_H_ */ diff --git a/Inu/Src/N12_Libs/vhzprof.c b/Inu/Src/N12_Libs/vhzprof.c new file mode 100644 index 0000000..ba76a40 --- /dev/null +++ b/Inu/Src/N12_Libs/vhzprof.c @@ -0,0 +1,45 @@ +/*===================================================================================== + File name: VHZPROF.C (IQ version) + + Originator: Digital Control Systems Group + Texas Instruments + + Description: V/f Profile for Scalar Control of Induction Motor + +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +-------------------------------------------------------------------------------------*/ +#include "IQmathLib.h" // Include header for IQmath library + +#include "vhzprof.h" + +#include "math.h" // Include math libs + +#include "dmctype.h" +//#include + +void vhz_prof_calc(VHZPROF *v) +{ + _iq VfSlope, AbsFreq; + +// Take absolute frequency to allow the operation of both rotational directions + AbsFreq = labs(v->Freq); + + if (AbsFreq <= v->LowFreq) + // Compute output voltage in profile #1 + v->VoltOut = v->VoltMin; + else if ((AbsFreq > v->LowFreq)&(AbsFreq <= v->HighFreq)) + { + // Compute slope of V/f profile + VfSlope = _IQdiv((v->VoltMax - v->VoltMin),(v->HighFreq - v->LowFreq)); + // Compute output voltage in profile #2 + v->VoltOut = v->VoltMin + _IQmpy(VfSlope,(AbsFreq-v->LowFreq)); + } + else if ((AbsFreq > v->HighFreq)&(AbsFreq < v->FreqMax)) + // Compute output voltage in profile #3 + v->VoltOut = v->VoltMax; +} + + diff --git a/Inu/Src/N12_Libs/vhzprof.h b/Inu/Src/N12_Libs/vhzprof.h new file mode 100644 index 0000000..a1326df --- /dev/null +++ b/Inu/Src/N12_Libs/vhzprof.h @@ -0,0 +1,41 @@ +/* ================================================================================= +File name: VHZ_PROF.H (IQ version) + +Originator: Digital Control Systems Group + Texas Instruments + +Description: +Header file containing constants, data type definitions, and +function prototypes for the VHZPROF. +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20 +------------------------------------------------------------------------------*/ +#ifndef __VHZ_PROF_H__ +#define __VHZ_PROF_H__ + +typedef struct { _iq Freq; // Input: Input Frequency (pu) + _iq VoltOut; // Output: Output voltage (pu) + _iq LowFreq; // Parameter: Low Frequency (pu) + _iq HighFreq; // Parameter: High Frequency at rated voltage (pu) + _iq FreqMax; // Parameter: Maximum Frequency (pu) + _iq VoltMax; // Parameter: Rated voltage (pu) + _iq VoltMin; // Parameter: Voltage at low Frequency range (pu) + void (*calc)(); // Pointer to calculation function + } VHZPROF; + +typedef VHZPROF *VHZPROF_handle; +/*----------------------------------------------------------------------------- +Default initalizer for the VHZPROF object. +-----------------------------------------------------------------------------*/ +#define VHZPROF_DEFAULTS { 0,0, \ + 0,0,0,0,0, \ + (void (*)(Uint32))vhz_prof_calc } + +/*------------------------------------------------------------------------------ +Prototypes for the functions in VHZ_PROF.C +------------------------------------------------------------------------------*/ +void vhz_prof_calc(VHZPROF_handle); + +#endif // __VHZ_PROF_H__ diff --git a/Inu/Src/N12_Libs/word_structurs.h b/Inu/Src/N12_Libs/word_structurs.h new file mode 100644 index 0000000..7d67dfa --- /dev/null +++ b/Inu/Src/N12_Libs/word_structurs.h @@ -0,0 +1,64 @@ +/* + * word_structurs.h + * + * Created on: 5 . 2020 . + * Author: Yura + */ + +#ifndef SRC_LIBS_NIO12_WORD_STRUCTURS_H_ +#define SRC_LIBS_NIO12_WORD_STRUCTURS_H_ + +//////////////////////////////////////////////////////////////////////////////// +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + unsigned int bit8: 1; + unsigned int bit9: 1; + unsigned int bit10: 1; + unsigned int bit11: 1; + unsigned int bit12: 1; + unsigned int bit13: 1; + unsigned int bit14: 1; + unsigned int bit15: 1; + } bits; // + int all; // +} WORD_INT2BITS_STRUCT; // +////// +//////////////////////////////////////////////////////////////////////////////// +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + unsigned int bit8: 1; + unsigned int bit9: 1; + unsigned int bit10: 1; + unsigned int bit11: 1; + unsigned int bit12: 1; + unsigned int bit13: 1; + unsigned int bit14: 1; + unsigned int bit15: 1; + } bits; // + unsigned int all; // +} WORD_UINT2BITS_STRUCT; // +////// + + + +#endif /* SRC_LIBS_NIO12_WORD_STRUCTURS_H_ */ diff --git a/Inu/Src/VectorControl/abc_to_alphabeta.c b/Inu/Src/N12_VectorControl/abc_to_alphabeta.c similarity index 100% rename from Inu/Src/VectorControl/abc_to_alphabeta.c rename to Inu/Src/N12_VectorControl/abc_to_alphabeta.c diff --git a/Inu/Src/VectorControl/abc_to_alphabeta.h b/Inu/Src/N12_VectorControl/abc_to_alphabeta.h similarity index 100% rename from Inu/Src/VectorControl/abc_to_alphabeta.h rename to Inu/Src/N12_VectorControl/abc_to_alphabeta.h diff --git a/Inu/Src/VectorControl/abc_to_dq.c b/Inu/Src/N12_VectorControl/abc_to_dq.c similarity index 100% rename from Inu/Src/VectorControl/abc_to_dq.c rename to Inu/Src/N12_VectorControl/abc_to_dq.c diff --git a/Inu/Src/VectorControl/abc_to_dq.h b/Inu/Src/N12_VectorControl/abc_to_dq.h similarity index 100% rename from Inu/Src/VectorControl/abc_to_dq.h rename to Inu/Src/N12_VectorControl/abc_to_dq.h diff --git a/Inu/Src/VectorControl/alg_pll.c b/Inu/Src/N12_VectorControl/alg_pll.c similarity index 100% rename from Inu/Src/VectorControl/alg_pll.c rename to Inu/Src/N12_VectorControl/alg_pll.c diff --git a/Inu/Src/VectorControl/alg_pll.h b/Inu/Src/N12_VectorControl/alg_pll.h similarity index 100% rename from Inu/Src/VectorControl/alg_pll.h rename to Inu/Src/N12_VectorControl/alg_pll.h diff --git a/Inu/Src/VectorControl/alphabeta_to_dq.c b/Inu/Src/N12_VectorControl/alphabeta_to_dq.c similarity index 100% rename from Inu/Src/VectorControl/alphabeta_to_dq.c rename to Inu/Src/N12_VectorControl/alphabeta_to_dq.c diff --git a/Inu/Src/VectorControl/alphabeta_to_dq.h b/Inu/Src/N12_VectorControl/alphabeta_to_dq.h similarity index 100% rename from Inu/Src/VectorControl/alphabeta_to_dq.h rename to Inu/Src/N12_VectorControl/alphabeta_to_dq.h diff --git a/Inu/Src/VectorControl/dq_to_alphabeta_cos.c b/Inu/Src/N12_VectorControl/dq_to_alphabeta_cos.c similarity index 100% rename from Inu/Src/VectorControl/dq_to_alphabeta_cos.c rename to Inu/Src/N12_VectorControl/dq_to_alphabeta_cos.c diff --git a/Inu/Src/VectorControl/dq_to_alphabeta_cos.h b/Inu/Src/N12_VectorControl/dq_to_alphabeta_cos.h similarity index 100% rename from Inu/Src/VectorControl/dq_to_alphabeta_cos.h rename to Inu/Src/N12_VectorControl/dq_to_alphabeta_cos.h diff --git a/Inu/Src/VectorControl/params_pll.h b/Inu/Src/N12_VectorControl/params_pll.h similarity index 100% rename from Inu/Src/VectorControl/params_pll.h rename to Inu/Src/N12_VectorControl/params_pll.h diff --git a/Inu/Src/VectorControl/regul_power.c b/Inu/Src/N12_VectorControl/regul_power.c similarity index 100% rename from Inu/Src/VectorControl/regul_power.c rename to Inu/Src/N12_VectorControl/regul_power.c diff --git a/Inu/Src/VectorControl/regul_power.h b/Inu/Src/N12_VectorControl/regul_power.h similarity index 100% rename from Inu/Src/VectorControl/regul_power.h rename to Inu/Src/N12_VectorControl/regul_power.h diff --git a/Inu/Src/VectorControl/regul_turns.c b/Inu/Src/N12_VectorControl/regul_turns.c similarity index 100% rename from Inu/Src/VectorControl/regul_turns.c rename to Inu/Src/N12_VectorControl/regul_turns.c diff --git a/Inu/Src/VectorControl/regul_turns.h b/Inu/Src/N12_VectorControl/regul_turns.h similarity index 100% rename from Inu/Src/VectorControl/regul_turns.h rename to Inu/Src/N12_VectorControl/regul_turns.h diff --git a/Inu/Src/VectorControl/smooth.c b/Inu/Src/N12_VectorControl/smooth.c similarity index 100% rename from Inu/Src/VectorControl/smooth.c rename to Inu/Src/N12_VectorControl/smooth.c diff --git a/Inu/Src/VectorControl/smooth.h b/Inu/Src/N12_VectorControl/smooth.h similarity index 100% rename from Inu/Src/VectorControl/smooth.h rename to Inu/Src/N12_VectorControl/smooth.h diff --git a/Inu/Src/VectorControl/teta_calc.c b/Inu/Src/N12_VectorControl/teta_calc.c similarity index 100% rename from Inu/Src/VectorControl/teta_calc.c rename to Inu/Src/N12_VectorControl/teta_calc.c diff --git a/Inu/Src/VectorControl/teta_calc.h b/Inu/Src/N12_VectorControl/teta_calc.h similarity index 100% rename from Inu/Src/VectorControl/teta_calc.h rename to Inu/Src/N12_VectorControl/teta_calc.h diff --git a/Inu/Src/VectorControl/vector_control.c b/Inu/Src/N12_VectorControl/vector_control.c similarity index 100% rename from Inu/Src/VectorControl/vector_control.c rename to Inu/Src/N12_VectorControl/vector_control.c diff --git a/Inu/Src/VectorControl/vector_control.h b/Inu/Src/N12_VectorControl/vector_control.h similarity index 100% rename from Inu/Src/VectorControl/vector_control.h rename to Inu/Src/N12_VectorControl/vector_control.h diff --git a/Inu/Src/N12_Xilinx/CRC_Functions.c b/Inu/Src/N12_Xilinx/CRC_Functions.c new file mode 100644 index 0000000..3d75514 --- /dev/null +++ b/Inu/Src/N12_Xilinx/CRC_Functions.c @@ -0,0 +1,143 @@ +#include "CRC_Functions.h" +#pragma DATA_SECTION(crc_16_tab, ".slow_vars") +WORD crc_16_tab[] = { + 0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241, + 0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440, + 0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40, + 0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841, + 0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40, + 0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41, + 0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641, + 0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040, + 0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240, + 0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441, + 0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41, + 0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840, + 0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41, + 0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40, + 0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640, + 0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041, + 0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240, + 0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441, + 0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41, + 0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840, + 0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41, + 0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40, + 0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640, + 0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041, + 0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241, + 0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440, + 0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40, + 0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841, + 0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40, + 0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41, + 0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641, + 0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040 +}; + +unsigned char GetCRC8_Dallas1_WireReverse(unsigned char *DataArrIn, unsigned int DataLength) +{ + unsigned char i, Data = 0, CRC = 0, CheckBit; + unsigned int ByteCnt = 0; + + do + { + Data = DataArrIn[ByteCnt]; + for(i = 0; i < 8; i++) + { + CheckBit = CRC ^ Data; + CheckBit &= 1; + CRC >>= 1; + Data >>= 1; + if(CheckBit == 1) CRC ^= 0x8C; + } + ByteCnt++; + } + while(ByteCnt < DataLength); + + return CRC; +} + +unsigned char GetCRC8_Dallas1_Wire(unsigned char *DataArrIn, unsigned int DataLength) +{ + unsigned char CRC = 0x00; + unsigned int i; + + while (DataLength--) + { + CRC ^= *(DataArrIn++); + + for (i = 0; i < 8; i++) CRC = (CRC & 0x80 ? (CRC << 1) ^ 0x31 : CRC << 1) & 0x00FF; + } + + return CRC; +} + +unsigned int GetCRC16_IBM(unsigned int crc, unsigned int *buf, unsigned int size) +{ + + while(size--) + { + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ *buf++) & 0xff ]; + crc = crc & 0xffff; + } + + return (crc & 0xffff); +} + + +unsigned int GetCRC16_IBM_v2(unsigned int crc, unsigned int *buf, unsigned int size) +{ + unsigned int xor = 0; + + + while(size--) + { +// crc = (crc >> 8) ^ crc_16_tab[ (crc ^ *buf++) & 0xff ]; +// crc = crc & 0xffff; + + xor = ((*buf++) ^ crc) & 0xff; + crc >>= 8; + crc ^= crc_16_tab[xor]; + } + + return (crc & 0xffff); +} + + +unsigned int GetCRC16_B(unsigned int crc,unsigned int *buf,unsigned long size ) +{ + +unsigned int x, dword, byte; +unsigned long i; + + + + for (i = 0; i < size; i++) + { + x = i % 2; + + dword = buf[i/2]; +// dword = *buf; + + + if (x == 0) + { + byte = ((dword >> 8)&0xFF); + } + + if (x == 1) + { + byte = (dword & 0xFF); + } + + crc = (crc >> 8) ^ crc_16_tab[ (crc ^ (byte) ) & 0xff ]; + crc = crc & 0xffff; + +// crc = crc + ((byte) & 0xff); + + } + + return (crc & 0xffff); +} + diff --git a/Inu/Src/N12_Xilinx/CRC_Functions.h b/Inu/Src/N12_Xilinx/CRC_Functions.h new file mode 100644 index 0000000..be01c01 --- /dev/null +++ b/Inu/Src/N12_Xilinx/CRC_Functions.h @@ -0,0 +1,12 @@ +#ifndef _CRC_FUNCTIONS_H +#define _CRC_FUNCTIONS_H + +typedef unsigned short WORD; + +unsigned int GetCRC16_IBM(unsigned int crc, unsigned int *buf, unsigned int size); +unsigned int GetCRC16_B(unsigned int crc,unsigned int *buf,unsigned long size); +unsigned char GetCRC8_Dallas1_WireReverse(unsigned char *DataArrIn, unsigned int DataLength); +unsigned char GetCRC8_Dallas1_Wire(unsigned char *DataArrIn, unsigned int DataLength); +unsigned int GetCRC16_IBM_v2(unsigned int crc, unsigned int *buf, unsigned int size); + +#endif diff --git a/Inu/Src/N12_Xilinx/MemoryFunctions.c b/Inu/Src/N12_Xilinx/MemoryFunctions.c new file mode 100644 index 0000000..69b195c --- /dev/null +++ b/Inu/Src/N12_Xilinx/MemoryFunctions.c @@ -0,0 +1,325 @@ +#include "MemoryFunctions.h" + + +#define START_ADR_FLASH 0x100000 + +void write_xmemory(unsigned long addr, unsigned int data); +unsigned int flash_read_word(unsigned long adr); +void flash_reset(); + +unsigned char flash_toggle_bit(long adr) +{ + unsigned int dq1,dq2,tog,tim; + unsigned long cicle; + + cicle=0; + dq1 = flash_read_word(adr); + do + { + dq2= flash_read_word(adr); + tog = (dq1 & 0x40) + ( dq2 & 0x40); + if (tog!=0x40) + return 0; + dq1=dq2; + tim=dq2 & 0x20; + cicle++; + } while ((cicle!=26553500) && (tim==0)); + dq1 = flash_read_word(adr); + dq2 = flash_read_word(adr); + tog = (dq1 & 0x40) + ( dq2 & 0x40); + if (tog!=0x40) + return 0; + + flash_reset(); + return 1; + +} + +#pragma CODE_SECTION(ReadMemory,".fast_run"); +unsigned int ReadMemory(unsigned long addr) +{ + return (*(volatile int *)(addr)); +} + +#pragma CODE_SECTION(WriteMemory,".fast_run"); +void WriteMemory(unsigned long addr, unsigned int data) +{ + (*(volatile int *)( addr )) = data; +} + +unsigned char flash_erase_sector(unsigned long adr) +{ + write_xmemory(0x555,0xaa); + write_xmemory(0x2aa,0x55); + write_xmemory(0x555,0x80); + write_xmemory(0x555,0xaa); + write_xmemory(0x2aa,0x55); + write_xmemory(adr,0x30); + + return flash_toggle_bit(adr); +} + +#pragma CODE_SECTION(write_xmemory,".fast_run"); +void write_xmemory(unsigned long addr, unsigned int data) +{ + (*(volatile int *)(START_ADR_FLASH+addr)) = data; +} + +#pragma CODE_SECTION(read_xmemory,".fast_run"); +unsigned int read_xmemory(unsigned long addr) +{ + return (*(volatile int *)(START_ADR_FLASH+addr)); +} + +unsigned int flash_read_word(unsigned long adr) +{ + return read_xmemory(adr); +} + +void flash_reset() +{ + write_xmemory(0,0xf0); +} + +unsigned int flash_write_word(unsigned long adr, unsigned int dat) +{ + unsigned int dq=0xffff; + + if (dat!=dq) + { + write_xmemory(0x555,0xaa ); + write_xmemory(0x2aa,0x55 ); + write_xmemory(0x555,0xa0 ); + write_xmemory(adr,dat); + dq=flash_toggle_bit(adr); + dq=flash_read_word(adr); + } + return (dq==dat); +} + + +unsigned int RunFlashData(unsigned long AdrFrom, unsigned long AdrTo, unsigned long Length, + unsigned int *cerr_out, unsigned int *repl_out, unsigned int *count_ok_out) +{ + + + unsigned long adr_start,adr_end,f_s,f_e; + int i; + static char flash_tab[] = { + 32,32,32,32,32,32,32,32,32,32,32,32,32,32,16,4,4,8 + }; + + unsigned int d1,d2, d3, cerr=0, repl = 0, count_ok = 0; + unsigned long adr_out,adr_in, adr_out_s; + + *cerr_out = 0; + *repl_out = 0; + *count_ok_out = 0; + + + + flash_reset(); + + i=0; + adr_start=AdrTo-START_ADR_FLASH; + adr_end=adr_start+Length; + + + f_s=0; + f_e=0; + + for (i=0;i<16;i++) + { + f_s=f_e; + f_e=f_s+(unsigned long)flash_tab[i]*1024; + + if ( f_s<=adr_start && f_e>adr_start ) flash_erase_sector(f_s); + if ( f_s>adr_start && f_eadr_end ) flash_erase_sector(f_s); + } + + +// i=flash_erase_sector(0x20000); +// i=flash_erase_sector(0x28000); +// i=flash_erase_sector(0x30000); +// i=flash_erase_sector(0x38000); + + + if (i!=0) + { + // error + // delay_loop(); + } + + //check clear flash? + adr_out_s=AdrTo-START_ADR_FLASH; + cerr=0; + adr_in=AdrFrom; + for (adr_out = 0; adr_out < Length; adr_out++) + { + d1=flash_read_word(adr_out+adr_out_s); + if (d1!=0xffff) + { + cerr++; + } + } + + if (cerr) + { + *cerr_out = cerr; + *repl_out = 0; + *count_ok_out = 0; + return RETURN_FLASHED_NOT_CLEAR_1; + } + // end check clear flash + + + // flash + adr_out_s = AdrTo-START_ADR_FLASH; + cerr = 0; + adr_in = AdrFrom; + + + for (adr_out = 0; adr_out < Length; adr_out++) + { + + d1=flash_read_word(adr_out+adr_out_s); + d3=ReadMemory(adr_in); + adr_in++; + + if (d1==0xffff) // ? + { + + flash_write_word(adr_out+adr_out_s,d3); + + d2=flash_read_word(adr_out+adr_out_s); + + if (d2!=d3) + { + // + repl++; + + if (d2==0xffff) + { + flash_write_word(adr_out+adr_out_s,d3); + d2=flash_read_word(adr_out+adr_out_s); + + if (d2!=d3) + { + cerr++; + + *cerr_out = cerr; + *repl_out = repl; + *count_ok_out = count_ok; + return RETURN_FLASHED_ERROR_AFTER_REPL; + } + else + count_ok++; + } + else + { + // - , , + cerr++; + *cerr_out = cerr; + *repl_out = repl; + *count_ok_out = count_ok; + return RETURN_FLASHED_ERROR_BEFORE_REPL_NOT_CLEAR; + } + + } + else + count_ok++; + + } + else + { + // -! ! + cerr++; + *cerr_out = cerr; + *repl_out = repl; + *count_ok_out = count_ok; + return RETURN_FLASHED_NOT_CLEAR_2; + } + + } + + *cerr_out = cerr; + *repl_out = repl; + *count_ok_out = count_ok; + + + if (cerr) + return RETURN_FLASHED_ERROR; + + return RETURN_FLASHED_OK; + + + + +} + + + +unsigned int VerifyFlashData(unsigned long AdrFrom, unsigned long AdrTo, unsigned long Length, + unsigned int *cerr_out, unsigned int *repl_out, unsigned int *count_ok_out) +{ + + + unsigned long adr_start,adr_end,f_s,f_e; + int i; + + volatile unsigned int d1,d2, d3, cerr=0, repl = 0, count_ok = 0; + unsigned long adr_out,adr_in, adr_out_s; + + *cerr_out = 0; + *repl_out = 0; + *count_ok_out = 0; + + i=0; + adr_start=AdrTo-START_ADR_FLASH; + adr_end=adr_start+Length; + + + f_s=0; + f_e=0; + + + // test flash + adr_out_s = AdrTo-START_ADR_FLASH; + cerr = 0; + adr_in = AdrFrom; + + + for (adr_out = 0; adr_out < Length; adr_out++) + { + + d1=flash_read_word(adr_out+adr_out_s); + d3=ReadMemory(adr_in); + adr_in++; + + repl++; + + if (d1!=d3) + { + cerr++; + } + else + count_ok++; + + } + + + *cerr_out = cerr; + *repl_out = count_ok; + *count_ok_out = count_ok; + + + if (cerr) + return RETURN_FLASHED_ERROR; + + return RETURN_FLASHED_OK; + +} + + + diff --git a/Inu/Src/N12_Xilinx/MemoryFunctions.h b/Inu/Src/N12_Xilinx/MemoryFunctions.h new file mode 100644 index 0000000..365f2d6 --- /dev/null +++ b/Inu/Src/N12_Xilinx/MemoryFunctions.h @@ -0,0 +1,36 @@ +#ifndef _MEMORY_FUNCTIONS_H +#define _MEMORY_FUNCTIONS_H + + +enum {RETURN_FLASHED_OK=0, + RETURN_FLASHED_NOT_CLEAR_1, + RETURN_FLASHED_NOT_CLEAR_2, + RETURN_FLASHED_ERROR_AFTER_REPL, + RETURN_FLASHED_ERROR_BEFORE_REPL_NOT_CLEAR, + RETURN_FLASHED_ERROR +}; + +//#include "RS_Functions_modbus.h" + +void WriteMemory(unsigned long addr, unsigned int data); +unsigned int ReadMemory(unsigned long addr); + + +//unsigned int RunFlashData(unsigned long AdrFrom,unsigned long AdrTo, unsigned long Length); +unsigned int RunFlashData(unsigned long AdrFrom, unsigned long AdrTo, unsigned long Length, + unsigned int *cerr_out, unsigned int *repl_out, unsigned int *count_ok_out); + +unsigned int VerifyFlashData(unsigned long AdrFrom, unsigned long AdrTo, unsigned long Length, + unsigned int *cerr_out, unsigned int *repl_out, unsigned int *count_ok_out); + + + +#define i_ReadMemory(addr) ReadMemory(addr) +#define i_WriteMemory(addr,data) WriteMemory(addr,data) + + +//#define i_ReadMemory(addr) (*(volatile int *)(addr)) +//#define i_WriteMemory(addr,data) { (*(volatile int *)( addr )) = data; } + + +#endif diff --git a/Inu/Src/N12_Xilinx/RS_Function_terminal.c b/Inu/Src/N12_Xilinx/RS_Function_terminal.c new file mode 100644 index 0000000..99f38e5 --- /dev/null +++ b/Inu/Src/N12_Xilinx/RS_Function_terminal.c @@ -0,0 +1,98 @@ +/* + * RS_Function_terminal.c + * + * Created on: 12 . 2020 . + * Author: stud + */ + +#include "RS_Function_terminal.h" + +#include +#include + +#include "modbus_table_v2.h" +#include "options_table.h" +#include "DSP281x_Device.h" +#include "CRC_Functions.h" +#include "MemoryFunctions.h" +#include "RS_Functions.h" + + + + + +#pragma DATA_SECTION(reply, ".slow_vars") +TMS_TO_TERMINAL_STRUCT reply = TMS_TO_TERMINAL_STRUCT_DEFAULT; +#pragma DATA_SECTION(reply_test_all, ".slow_vars") +TMS_TO_TERMINAL_TEST_ALL_STRUCT reply_test_all = TMS_TO_TERMINAL_TEST_ALL_STRUCT_DEFAULT; + + + + +void ReceiveCommandTestAll(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned int crc; +// int Data,Data1,Data2,Data3, Data4, DataM, tk1,tk2,tk3,tk0,period = 0, periodMiddle = 0, DataAnalog1, DataAnalog2, doubleImpulse, sinusImpulse; +// static unsigned int prevImp; + // const + CMD_TO_TMS_TEST_ALL_STRUCT* pcommand = (CMD_TO_TMS_TEST_ALL_STRUCT *)(RS232_Arr->RS_Header); + + + + // +// *(TMS_TO_TERMINAL_TEST_ALL_STRUCT*)RS232_Arr->buffer = reply_test_all; /* ? y */ + + + // , + reply_test_all.head.Address = RS232_Arr->addr_recive;//CNTRL_ADDR; + reply_test_all.head.Number = CMD_RS232_TEST_ALL; + + + + func_fill_answer_to_TMS_test(&reply_test_all, pcommand); + + + *(TMS_TO_TERMINAL_TEST_ALL_STRUCT*)RS232_Arr->buffer = reply_test_all; /* */ + + crc = 0xffff; + crc = GetCRC16_IBM( crc, RS232_Arr->buffer, sizeof(TMS_TO_TERMINAL_TEST_ALL_STRUCT)-3); + + reply_test_all.crc_lo = LOBYTE(crc); + reply_test_all.crc_hi = HIBYTE(crc); + + // - y + *(TMS_TO_TERMINAL_TEST_ALL_STRUCT*)RS232_Arr->buffer = reply_test_all; // ? y + RS_Send(RS232_Arr,RS232_Arr->buffer, sizeof(TMS_TO_TERMINAL_TEST_ALL_STRUCT)+1); + + return; +} + +void ReceiveCommand(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned int crc; + + // const + // + //CMD_TO_TMS* const pcommand = (CMD_TO_TMS *)(RS232_Arr->RS_Header); + CMD_TO_TMS_STRUCT* pcommand = (CMD_TO_TMS_STRUCT *)(RS232_Arr->RS_Header); + // , + reply.head.Address = RS232_Arr->addr_recive;//CNTRL_ADDR; + reply.head.Number = CMD_RS232_STD; + +// func_fill_answer_to_TMS(&reply, pcommand); + func_unpack_answer_from_TMS_RS232(pcommand); + func_pack_answer_to_TMS(&reply); + + *(TMS_TO_TERMINAL_STRUCT*)RS232_Arr->buffer = reply; // y + + crc = 0xffff; + crc = GetCRC16_IBM( crc, RS232_Arr->buffer, sizeof(TMS_TO_TERMINAL_STRUCT)-3); + + reply.crc_lo = LOBYTE(crc); + reply.crc_hi = HIBYTE(crc); + + // y + *(TMS_TO_TERMINAL_STRUCT*)RS232_Arr->buffer = reply; // y + RS_Send(RS232_Arr,RS232_Arr->buffer, sizeof(TMS_TO_TERMINAL_STRUCT)+1); + return; +} diff --git a/Inu/Src/N12_Xilinx/RS_Function_terminal.h b/Inu/Src/N12_Xilinx/RS_Function_terminal.h new file mode 100644 index 0000000..13c9485 --- /dev/null +++ b/Inu/Src/N12_Xilinx/RS_Function_terminal.h @@ -0,0 +1,605 @@ +/* + * RS_Function_terminal.h + * + * Created on: 12 . 2020 . + * Author: stud + */ + +#ifndef SRC_XILINX_NIO12_RS_FUNCTION_TERMINAL_H_ +#define SRC_XILINX_NIO12_RS_FUNCTION_TERMINAL_H_ + +#include "RS_Functions.h" + + +typedef struct +{ + CHAR analog1_lo; // + CHAR analog1_hi; // + CHAR analog2_lo; // + CHAR analog2_hi; // + CHAR analog3_lo; // + CHAR analog3_hi; // + // + CHAR analog4_lo; // + CHAR analog4_hi; // + CHAR analog5_lo; // + CHAR analog5_hi; // + CHAR analog6_lo; // + CHAR analog6_hi; // + +// + CHAR analog7_lo; // + CHAR analog7_hi; // + CHAR analog8_lo; // + CHAR analog8_hi; // + CHAR analog9_lo; // + CHAR analog9_hi; // + CHAR analog10_lo; // + CHAR analog10_hi; // + CHAR analog11_lo; // + CHAR analog11_hi; // + CHAR analog12_lo; // + CHAR analog12_hi; // + CHAR analog13_lo; // + CHAR analog13_hi; // + CHAR analog14_lo; // + CHAR analog14_hi; // + CHAR analog15_lo; // + CHAR analog15_hi; // + + +} CMD_ANALOG_DATA_STRUCT; + +typedef union +{ + struct + { + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + } bit_data; // + CHAR byte_data; // +} CMD_DIGIT_BYTE_STRUCT; // + +typedef struct +{ + CMD_DIGIT_BYTE_STRUCT Byte01; + CMD_DIGIT_BYTE_STRUCT Byte02; + CMD_DIGIT_BYTE_STRUCT Byte03; + CMD_DIGIT_BYTE_STRUCT Byte04; + + CMD_DIGIT_BYTE_STRUCT Byte05; + CMD_DIGIT_BYTE_STRUCT Byte06; + +} CMD_DIGIT_DATA_STRUCT; + +typedef struct +{ + CHAR Address; // + CHAR Number; // +} CMD_TMS_HEAD_STRUCT; + +typedef struct +{ + // + CMD_TMS_HEAD_STRUCT head; + + // + CMD_ANALOG_DATA_STRUCT analog_data; + + // y + CMD_DIGIT_DATA_STRUCT digit_data; + + // y + CHAR crc_lo; + CHAR crc_hi; + + // + CHAR add_byte; +} CMD_TO_TMS_STRUCT; + +typedef struct +{ + CHAR Address; // + CHAR Number; // +} CMD_TMS_HEAD_TEST_ALL_STRUCT; + +typedef struct +{ + CHAR analog1_lo; // + CHAR analog1_hi; // + CHAR analog2_lo; // + CHAR analog2_hi; // + CHAR analog3_lo; // + CHAR analog3_hi; // + CHAR analog4_lo; // + CHAR analog4_hi; // + CHAR analog5_lo; // + CHAR analog5_hi; // + +} CMD_ANALOG_DATA_TEST_ALL_STRUCT; + +typedef struct +{ + CMD_DIGIT_BYTE_STRUCT byte01; + CMD_DIGIT_BYTE_STRUCT byte02; + + CMD_DIGIT_BYTE_STRUCT byte03; + CMD_DIGIT_BYTE_STRUCT byte04; + + CMD_DIGIT_BYTE_STRUCT byte05; + CMD_DIGIT_BYTE_STRUCT byte06; + + CMD_DIGIT_BYTE_STRUCT byte07; + CMD_DIGIT_BYTE_STRUCT byte08; + + CMD_DIGIT_BYTE_STRUCT byte09; + CMD_DIGIT_BYTE_STRUCT byte10; + + CMD_DIGIT_BYTE_STRUCT byte11; + CMD_DIGIT_BYTE_STRUCT byte12; +} CMD_DIGIT_DATA_TEST_ALL_STRUCT; + +typedef struct +{ + // + CMD_TMS_HEAD_TEST_ALL_STRUCT head; + + // + CMD_ANALOG_DATA_TEST_ALL_STRUCT analog_data; + + // y + CMD_DIGIT_DATA_TEST_ALL_STRUCT digit_data; + + // y + CHAR crc_lo; + CHAR crc_hi; + + // + CHAR add_byte; +} CMD_TO_TMS_TEST_ALL_STRUCT; + + +typedef struct +{ + CMD_DIGIT_BYTE_STRUCT byte01; + CMD_DIGIT_BYTE_STRUCT byte02; + CMD_DIGIT_BYTE_STRUCT byte03; + CMD_DIGIT_BYTE_STRUCT byte04; + CMD_DIGIT_BYTE_STRUCT byte05; + CMD_DIGIT_BYTE_STRUCT byte06; + CMD_DIGIT_BYTE_STRUCT byte07; + CMD_DIGIT_BYTE_STRUCT byte08; + CMD_DIGIT_BYTE_STRUCT byte09; + CMD_DIGIT_BYTE_STRUCT byte10; + CMD_DIGIT_BYTE_STRUCT byte11; + CMD_DIGIT_BYTE_STRUCT byte12; + + CMD_DIGIT_BYTE_STRUCT byte13; + CMD_DIGIT_BYTE_STRUCT byte14; + CMD_DIGIT_BYTE_STRUCT byte15; + CMD_DIGIT_BYTE_STRUCT byte16; + CMD_DIGIT_BYTE_STRUCT byte17; + CMD_DIGIT_BYTE_STRUCT byte18; + CMD_DIGIT_BYTE_STRUCT byte19; + CMD_DIGIT_BYTE_STRUCT byte20; + CMD_DIGIT_BYTE_STRUCT byte21; + CMD_DIGIT_BYTE_STRUCT byte22; + CMD_DIGIT_BYTE_STRUCT byte23; + CMD_DIGIT_BYTE_STRUCT byte24; + CMD_DIGIT_BYTE_STRUCT byte25; + CMD_DIGIT_BYTE_STRUCT byte26; + CMD_DIGIT_BYTE_STRUCT byte27; + CMD_DIGIT_BYTE_STRUCT byte28; + + CMD_DIGIT_BYTE_STRUCT byte29; + CMD_DIGIT_BYTE_STRUCT byte30; + CMD_DIGIT_BYTE_STRUCT byte31; + CMD_DIGIT_BYTE_STRUCT byte32; + CMD_DIGIT_BYTE_STRUCT byte33; + CMD_DIGIT_BYTE_STRUCT byte34; + CMD_DIGIT_BYTE_STRUCT byte35; + CMD_DIGIT_BYTE_STRUCT byte36; + CMD_DIGIT_BYTE_STRUCT byte37; + CMD_DIGIT_BYTE_STRUCT byte38; + CMD_DIGIT_BYTE_STRUCT byte39; + CMD_DIGIT_BYTE_STRUCT byte40; + CMD_DIGIT_BYTE_STRUCT byte41; + CMD_DIGIT_BYTE_STRUCT byte42; + CMD_DIGIT_BYTE_STRUCT byte43; + CMD_DIGIT_BYTE_STRUCT byte44; + + CMD_DIGIT_BYTE_STRUCT byte45; + CMD_DIGIT_BYTE_STRUCT byte46; + CMD_DIGIT_BYTE_STRUCT byte47; + CMD_DIGIT_BYTE_STRUCT byte48; + CMD_DIGIT_BYTE_STRUCT byte49; + CMD_DIGIT_BYTE_STRUCT byte50; + + CMD_DIGIT_BYTE_STRUCT byte51; + CMD_DIGIT_BYTE_STRUCT byte52; + + CMD_DIGIT_BYTE_STRUCT byte53; + CMD_DIGIT_BYTE_STRUCT byte54; + + CMD_DIGIT_BYTE_STRUCT byte55; + CMD_DIGIT_BYTE_STRUCT byte56; + + CMD_DIGIT_BYTE_STRUCT byte57; + CMD_DIGIT_BYTE_STRUCT byte58; + CMD_DIGIT_BYTE_STRUCT byte59; + CMD_DIGIT_BYTE_STRUCT byte60; + +} ANS_DIGIT_DATA_TO_TERMINAL_STRUCT; // + +typedef struct +{ + CHAR analog1_lo; + CHAR analog1_hi; + CHAR analog2_lo; + CHAR analog2_hi; + CHAR analog3_lo; + CHAR analog3_hi; + CHAR analog4_lo; + CHAR analog4_hi; + CHAR analog5_lo; + CHAR analog5_hi; + CHAR analog6_lo; + CHAR analog6_hi; + CHAR analog7_lo; + CHAR analog7_hi; + CHAR analog8_lo; + CHAR analog8_hi; + CHAR analog9_lo; + CHAR analog9_hi; + + CHAR analog10_lo; + CHAR analog10_hi; + CHAR analog11_lo; + CHAR analog11_hi; + CHAR analog12_lo; + CHAR analog12_hi; + CHAR analog13_lo; + CHAR analog13_hi; + CHAR analog14_lo; + CHAR analog14_hi; + CHAR analog15_lo; + CHAR analog15_hi; + CHAR analog16_lo; + CHAR analog16_hi; + CHAR analog17_lo; + CHAR analog17_hi; + CHAR analog18_lo; + CHAR analog18_hi; + CHAR analog19_lo; + CHAR analog19_hi; + + CHAR analog20_lo; + CHAR analog20_hi; + CHAR analog21_lo; + CHAR analog21_hi; + CHAR analog22_lo; + CHAR analog22_hi; + CHAR analog23_lo; + CHAR analog23_hi; + CHAR analog24_lo; + CHAR analog24_hi; + + + CHAR analog25_lo; + CHAR analog25_hi; + CHAR analog26_lo; + CHAR analog26_hi; + CHAR analog27_lo; + CHAR analog27_hi; + CHAR analog28_lo; + CHAR analog28_hi; + CHAR analog29_lo; + CHAR analog29_hi; + CHAR analog30_lo; + CHAR analog30_hi; + + CHAR analog31_lo; + CHAR analog31_hi; + CHAR analog32_lo; + CHAR analog32_hi; + CHAR analog33_lo; + CHAR analog33_hi; + CHAR analog34_lo; + CHAR analog34_hi; + CHAR analog35_lo; + CHAR analog35_hi; + CHAR analog36_lo; + CHAR analog36_hi; + CHAR analog37_lo; + CHAR analog37_hi; + CHAR analog38_lo; + CHAR analog38_hi; + CHAR analog39_lo; + CHAR analog39_hi; + CHAR analog40_lo; + CHAR analog40_hi; + + CHAR analog41_lo; + CHAR analog41_hi; + CHAR analog42_lo; + CHAR analog42_hi; + CHAR analog43_lo; + CHAR analog43_hi; + CHAR analog44_lo; + CHAR analog44_hi; + CHAR analog45_lo; + CHAR analog45_hi; + CHAR analog46_lo; + CHAR analog46_hi; + CHAR analog47_lo; + CHAR analog47_hi; + CHAR analog48_lo; + CHAR analog48_hi; + CHAR analog49_lo; + CHAR analog49_hi; + CHAR analog50_lo; + CHAR analog50_hi; + + CHAR analog51_lo; + CHAR analog51_hi; + CHAR analog52_lo; + CHAR analog52_hi; + CHAR analog53_lo; + CHAR analog53_hi; + CHAR analog54_lo; + CHAR analog54_hi; + CHAR analog55_lo; + CHAR analog55_hi; + CHAR analog56_lo; + CHAR analog56_hi; + CHAR analog57_lo; + CHAR analog57_hi; + CHAR analog58_lo; + CHAR analog58_hi; + CHAR analog59_lo; + CHAR analog59_hi; + CHAR analog60_lo; + CHAR analog60_hi; + + CHAR analog61_lo; + CHAR analog61_hi; + CHAR analog62_lo; + CHAR analog62_hi; + CHAR analog63_lo; + CHAR analog63_hi; + CHAR analog64_lo; + CHAR analog64_hi; + CHAR analog65_lo; + CHAR analog65_hi; + CHAR analog66_lo; + CHAR analog66_hi; + CHAR analog67_lo; + CHAR analog67_hi; + CHAR analog68_lo; + CHAR analog68_hi; + + CHAR analog69_lo; + CHAR analog69_hi; + CHAR analog70_lo; + CHAR analog70_hi; + CHAR analog71_lo; + CHAR analog71_hi; + CHAR analog72_lo; + CHAR analog72_hi; + CHAR analog73_lo; + CHAR analog73_hi; + CHAR analog74_lo; + CHAR analog74_hi; + CHAR analog75_lo; + CHAR analog75_hi; + CHAR analog76_lo; + CHAR analog76_hi; + CHAR analog77_lo; + CHAR analog77_hi; + CHAR analog78_lo; + CHAR analog78_hi; + CHAR analog79_lo; + CHAR analog79_hi; + CHAR analog80_lo; + CHAR analog80_hi; + + CHAR analog81_lo; + CHAR analog81_hi; + CHAR analog82_lo; + CHAR analog82_hi; + CHAR analog83_lo; + CHAR analog83_hi; + CHAR analog84_lo; + CHAR analog84_hi; + + CHAR analog85_lo; + CHAR analog85_hi; + CHAR analog86_lo; + CHAR analog86_hi; + CHAR analog87_lo; + CHAR analog87_hi; + CHAR analog88_lo; + CHAR analog88_hi; + CHAR analog89_lo; + CHAR analog89_hi; + + CHAR analog90_lo; + CHAR analog90_hi; + CHAR analog91_lo; + CHAR analog91_hi; + CHAR analog92_lo; + CHAR analog92_hi; + CHAR analog93_lo; + CHAR analog93_hi; + CHAR analog94_lo; + CHAR analog94_hi; + + CHAR analog95_lo; + CHAR analog95_hi; + CHAR analog96_lo; + CHAR analog96_hi; + + +} TMS_ANALOG_DATA_STRUCT; + +typedef struct +{ + // + CMD_TMS_HEAD_STRUCT head; + + // y + ANS_DIGIT_DATA_TO_TERMINAL_STRUCT digit_data; + + // + TMS_ANALOG_DATA_STRUCT analog_data; + + // y + CHAR crc_lo; + CHAR crc_hi; + + // + CHAR add_byte; + +} TMS_TO_TERMINAL_STRUCT; + +#define TMS_TO_TERMINAL_STRUCT_DEFAULT {{0}, {0}, {0}, 0, 0, 0} + +typedef struct +{ + CMD_DIGIT_BYTE_STRUCT byte01; + CMD_DIGIT_BYTE_STRUCT byte02; + CMD_DIGIT_BYTE_STRUCT byte03; + CMD_DIGIT_BYTE_STRUCT byte04; + CMD_DIGIT_BYTE_STRUCT byte05; + CMD_DIGIT_BYTE_STRUCT byte06; + CMD_DIGIT_BYTE_STRUCT byte07; + CMD_DIGIT_BYTE_STRUCT byte08; + CMD_DIGIT_BYTE_STRUCT byte09; + CMD_DIGIT_BYTE_STRUCT byte10; + CMD_DIGIT_BYTE_STRUCT byte11; + CMD_DIGIT_BYTE_STRUCT byte12; + + CMD_DIGIT_BYTE_STRUCT byte13; + CMD_DIGIT_BYTE_STRUCT byte14; + CMD_DIGIT_BYTE_STRUCT byte15; + CMD_DIGIT_BYTE_STRUCT byte16; + CMD_DIGIT_BYTE_STRUCT byte17; + CMD_DIGIT_BYTE_STRUCT byte18; + CMD_DIGIT_BYTE_STRUCT byte19; + CMD_DIGIT_BYTE_STRUCT byte20; + CMD_DIGIT_BYTE_STRUCT byte21; + CMD_DIGIT_BYTE_STRUCT byte22; + CMD_DIGIT_BYTE_STRUCT byte23; + CMD_DIGIT_BYTE_STRUCT byte24; + + CMD_DIGIT_BYTE_STRUCT byte25; + CMD_DIGIT_BYTE_STRUCT byte26; + CMD_DIGIT_BYTE_STRUCT byte27; + CMD_DIGIT_BYTE_STRUCT byte28; + CMD_DIGIT_BYTE_STRUCT byte29; + CMD_DIGIT_BYTE_STRUCT byte30; + CMD_DIGIT_BYTE_STRUCT byte31; + CMD_DIGIT_BYTE_STRUCT byte32; + CMD_DIGIT_BYTE_STRUCT byte33; + CMD_DIGIT_BYTE_STRUCT byte34; + +} ANS_DIGIT_DATA_TO_TERMINAL_TEST_ALL_STRUCT; + +typedef struct +{ + CHAR analog1_lo; + CHAR analog1_hi; + CHAR analog2_lo; + CHAR analog2_hi; + CHAR analog3_lo; + CHAR analog3_hi; + CHAR analog4_lo; + CHAR analog4_hi; + CHAR analog5_lo; + CHAR analog5_hi; + CHAR analog6_lo; + CHAR analog6_hi; + CHAR analog7_lo; + CHAR analog7_hi; + CHAR analog8_lo; + CHAR analog8_hi; + CHAR analog9_lo; + CHAR analog9_hi; + + CHAR analog10_lo; + CHAR analog10_hi; + CHAR analog11_lo; + CHAR analog11_hi; + CHAR analog12_lo; + CHAR analog12_hi; + CHAR analog13_lo; + CHAR analog13_hi; + CHAR analog14_lo; + CHAR analog14_hi; + CHAR analog15_lo; + CHAR analog15_hi; + CHAR analog16_lo; + CHAR analog16_hi; + CHAR analog17_lo; + CHAR analog17_hi; + CHAR analog18_lo; + CHAR analog18_hi; + CHAR analog19_lo; + CHAR analog19_hi; + + CHAR analog20_lo; + CHAR analog20_hi; + CHAR analog21_lo; + CHAR analog21_hi; + CHAR analog22_lo; + CHAR analog22_hi; + CHAR analog23_lo; + CHAR analog23_hi; + CHAR analog24_lo; + CHAR analog24_hi; + +} TMS_ANALOG_DATA_TEST_ALL_STRUCT; + +typedef struct +{ + // + CMD_TMS_HEAD_TEST_ALL_STRUCT head; + + // y + ANS_DIGIT_DATA_TO_TERMINAL_TEST_ALL_STRUCT digit_data; + + // + TMS_ANALOG_DATA_TEST_ALL_STRUCT analog_data; + + // y + CHAR crc_lo; + CHAR crc_hi; + + // + CHAR add_byte; + + // TMS +// unsigned int pcommand; + + // +// void (*fill_answer)(); + +} TMS_TO_TERMINAL_TEST_ALL_STRUCT; + +void ReceiveCommandTestAll(RS_DATA_STRUCT *RS232_Arr); +void ReceiveCommand(RS_DATA_STRUCT *RS232_Arr); + + +extern TMS_TO_TERMINAL_TEST_ALL_STRUCT reply_test_all; +extern TMS_TO_TERMINAL_STRUCT reply; + + + + +#endif /* SRC_XILINX_NIO12_RS_FUNCTION_TERMINAL_H_ */ diff --git a/Inu/Src/N12_Xilinx/RS_Functions.c b/Inu/Src/N12_Xilinx/RS_Functions.c new file mode 100644 index 0000000..0057622 --- /dev/null +++ b/Inu/Src/N12_Xilinx/RS_Functions.c @@ -0,0 +1,2639 @@ +#include "params.h" +#include "global_time.h" +#include "RS_Functions.h" + +#include +#if (USE_TEST_TERMINAL) +#include "RS_Function_terminal.h" +#endif + +#if (USE_MODBUS_TABLE_SVU) +#include "RS_modbus_svu.h" +#endif + +#if (USE_MODBUS_TABLE_PULT) +#include "RS_modbus_pult.h" +#endif + +#include "CRC_Functions.h" +#include "TuneUpPlane.h" // + +#include "pwm_test_lines.h" +#include "profile_interrupt.h" + + +#define _ENABLE_INTERRUPT_RS232_LED2 0//1 + + +#define _USE_RS_FIFO 1 + +#define RS232_SPEED 57600//115200 + +#define COM_1 0 //1 +#define COM_2 1 //2 +//#define SIZE_MODBUS_TABLE 334 +//#define ADR_MODBUS_TABLE 0x0001 + +#define BM_CHAR32 0 +#define TIME_WAIT_RS232_BYTE_OUT 2000 + +#define ADDR_FOR_ALL_DEF 0x4 +#define ADR_FOR_SPECIAL 0x100 +#define BM_PACKED 1 + +#define ADDR_UNIVERSAL_DEF 10 + +#define REC_BLOC_BEGIN 0xa0000 +#define REC_BLOC_END 0xeffff + +#define SelectNothing() WriteOper(1, 1, 1, 1) + +#define SCIa_TX_IntClear() SciaRegs.SCIFFTX.bit.TXINTCLR = 1 +#define SCIb_TX_IntClear() ScibRegs.SCIFFTX.bit.TXINTCLR = 1 + +#define IncCountMode28() WriteOper(1, 1, 0, 0) + + +#define SCIa_RX_IntClear() {SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;} +#define SCIb_RX_IntClear() {ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1; ScibRegs.SCIFFRX.bit.RXFFINTCLR=1;} + + +#define SCIa_SW_Reset() {SciaRegs.SCICTL1.bit.SWRESET=0; SciaRegs.SCICTL1.bit.SWRESET=1;} +#define SCIb_SW_Reset() {ScibRegs.SCICTL1.bit.SWRESET=0; ScibRegs.SCICTL1.bit.SWRESET=1;} + + +//#define SCIb_Get() ScibRegs.SCIRXBUF.bit.RXDT + +#define SelectReset28() WriteOper(1, 1, 1, 0) +#define SelectReset28_ForLoad67() WriteOper(0, 0, 1, 0) + +//#define enableUARTInt_A() SciaRegs.SCICTL2.all = 2 // recive +//#define enableUARTInt_B() ScibRegs.SCICTL2.all = 2 // recive + +//#define EnableUART_IntW_A() SciaRegs.SCICTL2.all = 1 // transmit +//#define EnableUART_IntW_B() ScibRegs.SCICTL2.all = 1 // transmit + +//#define SCIa_OK() SciaRegs.SCICTL2.bit.TXEMPTY +//#define SCIb_OK() ScibRegs.SCICTL2.bit.TXEMPTY + +//#define SCIa_Wait4OK() while(!SCIa_OK()) +#define SCIa_Send(a) SciaRegs.SCITXBUF = (unsigned char)a + +//#define SCIb_Wait4OK() while(!SCIb_OK()) +#define SCIb_Send(a) ScibRegs.SCITXBUF = (unsigned char)a + + + +#define SCIa_Get() SciaRegs.SCIRXBUF.bit.RXDT + +#define SCIa_RX_Error() SciaRegs.SCIRXST.bit.RXERROR +#define SCIb_RX_Error() SciaRegs.SCIRXST.bit.RXERROR + + +#define SetLoad28_FromResetInternalFlash() \ + SelectNothing(); \ + IncCountMode28(); + +const int CNTRL_ADDR_UNIVERSAL = ADDR_UNIVERSAL_DEF; + +//RS_DATA_STRUCT RS232_A, RS232_B; +#pragma DATA_SECTION(rs_a, ".slow_vars") +#pragma DATA_SECTION(rs_b, ".slow_vars") +RS_DATA_STRUCT rs_a = RS_DATA_STRUCT_DEFAULT, rs_b = RS_DATA_STRUCT_DEFAULT; + +#pragma DATA_SECTION(RS_Len, ".slow_vars") +unsigned int RS_Len[RS_LEN_CMD] = {0}; + + +//MODBUS_REG_STRUCT modbus_table_rs_in[SIZE_MODBUS_TABLE]; +//MODBUS_REG_STRUCT modbus_table_rs_out[SIZE_MODBUS_TABLE]; + +char size_cmd15 = 1; +char size_cmd16 = 1; + +//unsigned int enable_profile_led1_rsa = 1; +//unsigned int enable_profile_led1_rsb = 1; +//unsigned int enable_profile_led2_rsa = 0; +//unsigned int enable_profile_led2_rsb = 0; + + + +int CNTRL_ADDR = 1; + +int ADDR_FOR_ALL = ADDR_FOR_ALL_DEF; + +float KmodTerm = 0.0, freqTerm = 0.0; + +int flag_special_mode_rs = 0; +int disable_flag_special_mode_rs = 0; + + + +void RS_Wait4OK_TXRDY(char commnumber); + +void Answer(RS_DATA_STRUCT *RS232_Arr,int n); + +void EnableUART_Int_RX(char commnumber); +void EnableUART_Int_TX(char commnumber); + +void RS_LineToReceive(char commnumber); +void RS_SetLineMode(char commnumber, int bit, char parity, int stop); +void RS_SetBitMode(RS_DATA_STRUCT *RS232_Arr, int n); +void clear_timer_rs_live(RS_DATA_STRUCT *rs_arr); +void clear_timer_rs_live_mpu(RS_DATA_STRUCT *rs_arr); +void SCI_Send(char commnumber, char bs); +void RS_Wait4OK(char commnumber); +void RS_LineToSend(char commnumber); +void RS_TX_Handler(RS_DATA_STRUCT *RS232_Arr); +//int RS232_BSend(RS_DATA_STRUCT *RS232_Arr,unsigned int *pBuf, unsigned long len); + + +void EnableReceiveRS485(void) +{ +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_19_ON; +#endif + + GpioDataRegs.GPBDAT.bit.GPIOB14 = 1; +} + +void EnableSendRS485(void) +{ + +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_19_OFF; +#endif + + GpioDataRegs.GPBDAT.bit.GPIOB14 = 0; +} + + +void T_Flash(RS_DATA_STRUCT *RS232_Arr) +{ + volatile unsigned long Address1,Address2; + volatile unsigned long Length, LengthW; + unsigned int cerr, repl, count_ok, return_code; + + if(!RS232_Arr->BS_LoadOK) + { + RS_LineToReceive(RS232_Arr->commnumber); // RS485 + RS_SetBitMode(RS232_Arr,9); + return; + } + + Address1 = RS232_Arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (RS232_Arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (RS232_Arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (RS232_Arr->RS_Header[2] & 0xFF); + + Address2 = RS232_Arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (RS232_Arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (RS232_Arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (RS232_Arr->RS_Header[6] & 0xFF); + + Length = RS232_Arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (RS232_Arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (RS232_Arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (RS232_Arr->RS_Header[10] & 0xFF); + + LengthW = Length/2; + if (LengthW*2 0x180000) || ((Address2+LengthW) > 0x180000) ) + { + RS_LineToReceive(RS232_Arr->commnumber); // RS485 + RS_SetBitMode(RS232_Arr,9); + return; + } + + return_code = RunFlashData(Address1,Address2, LengthW, &cerr, &repl, &count_ok ); + if (return_code==0) + Answer(RS232_Arr,CMD_RS232_TFLASH); + else + { + RS_LineToReceive(RS232_Arr->commnumber); // RS485 + RS_SetBitMode(RS232_Arr,9); + return; + } + + + return; +} + +void Upload(RS_DATA_STRUCT *RS232_Arr) +{ + int32 Address, Length, crc; + + Address = RS232_Arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (RS232_Arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (RS232_Arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (RS232_Arr->RS_Header[2] & 0xFF); + + Length = RS232_Arr->RS_Header[9] & 0xFF; + Length = (Length<<8) | (RS232_Arr->RS_Header[8] & 0xFF); + Length = (Length<<8) | (RS232_Arr->RS_Header[7] & 0xFF); + Length = (Length<<8) | (RS232_Arr->RS_Header[6] & 0xFF); + + +// RS232_Arr->buffer[0] = RS232_Arr->addr_recive; //CNTRL_ADDR; +// RS232_Arr->buffer[1] = CMD_RS232_UPLOAD; + RS232_Arr->buffer_stage1[0] = RS232_Arr->addr_recive; //CNTRL_ADDR; + RS232_Arr->buffer_stage1[1] = CMD_RS232_UPLOAD; + + crc = 0xffff; + crc = GetCRC16_IBM( crc, RS232_Arr->buffer_stage1, 2); + crc = GetCRC16_B( crc, (unsigned int *)Address, Length); + + RS232_Arr->RS_SLength_stage1 = 2; /* */ + RS232_Arr->pRS_SendPtr_stage1 = RS232_Arr->buffer_stage1; + RS232_Arr->RS_SendBlockMode_stage1 = BM_CHAR32; + + RS232_Arr->RS_SLength_stage2 = Length; /* */ + RS232_Arr->pRS_SendPtr_stage2 = (unsigned int*)Address; + RS232_Arr->RS_SendBlockMode_stage2 = BM_PACKED; + + +// RS_Send(RS232_Arr,RS232_Arr->buffer, 2); // <=2 + +// RS232_Arr->buffer[0] = CMD_RS232_UPLOAD; +// RS_Send(RS232_Arr,RS232_Arr->buffer, 1); // <=2 +// while (RS232_Arr->RS_OnTransmitedData); + +// RS_Wait4OK(RS232_Arr->commnumber); + + +// RS232_BSend(RS232_Arr,(unsigned int*)Address, Length); +// RS_Wait4OK(RS232_Arr->commnumber); +// while (RS232_Arr->RS_OnTransmitedData); + + RS232_Arr->buffer[0] = LOBYTE(crc); + RS232_Arr->buffer[1] = HIBYTE(crc); + RS232_Arr->buffer[2] = 0; + RS232_Arr->buffer[3] = 0; + + RS232_Arr->cmd_tx_stage = 2; + RS_Send(RS232_Arr,RS232_Arr->buffer, 4); + +// RS232_Send_Staged(RS232_Arr,(unsigned int*)Address, Length); + +// RS_Send(RS232_Arr,RS232_Arr->buffer, 4+2); + +} + +void SetupArrCmdLength() +{ +int i; + + for (i=0;itime_wait_rs_out = (p)->time_wait_rs_out_mpu = (p)->time_wait_rs_lost = 0; + + +void SCI_SwReset(char commnumber) +{ + + switch (commnumber) + { + case COM_1: + SciaRegs.SCICTL1.bit.SWRESET=0; // Relinquish SCI from Reset + SciaRegs.SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset + + break; + case COM_2: + ScibRegs.SCICTL1.bit.SWRESET=0; // Relinquish SCI from Reset + ScibRegs.SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset + break; + } + + +} + +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + +//static int buf_fifo_rsa[17]={0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0}; +//static int buf_fifo_rsb[17]={0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0}; + +static int buf_fifo_rs_ab[2][17]={ {0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0}, {0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0} }; + +#pragma CODE_SECTION(my_test_rs,".fast_run2"); +int my_test_rs(int comn) +{ + int cc=0; + + cc = 0; + if (comn==COM_1) + { + while ((SciaRegs.SCIFFRX.bit.RXFIFST != 0) ) + { + buf_fifo_rs_ab[comn][cc++] = SciaRegs.SCIRXBUF.bit.RXDT; + if (cc>=17) cc = 0; + } + return cc; + } + else + { + while ((ScibRegs.SCIFFRX.bit.RXFIFST != 0) ) + { + buf_fifo_rs_ab[comn][cc++] = ScibRegs.SCIRXBUF.bit.RXDT; + if (cc>=17) cc = 0; + } + return cc; + } + +} + +/////////////// +//#pragma CODE_SECTION(RS_RXA_Handler_fast,".fast_run2"); +void RS_RXA_Handler_fast(RS_DATA_STRUCT *RS232_Arr) +{ + char Rc; + char RS232_BytePtr; + int cc1, cc2,cn; + +//i_led2_on_off(1); + + + ClearTimerRS_Live(RS232_Arr); + + cn = RS232_Arr->commnumber; + cc1 = my_test_rs(cn); + cc2 = 0; + for(;;) // 'goto' + { + if (cn==COM_1) + { + if (SciaRegs.SCIRXST.bit.RXERROR) + { +// Rc = SciaRegs.SCIRXBUF.all; + (RS232_Arr->count_recive_rxerror)++; + RS232_Arr->do_resetup_rs = 1; + } + if (SciaRegs.SCIRXST.bit.RXWAKE) + { + Rc = SciaRegs.SCIRXBUF.all; + } + } + else + { + + if (ScibRegs.SCIRXST.bit.RXERROR) + { +// Rc = SciaRegs.SCIRXBUF.all; + (RS232_Arr->count_recive_rxerror)++; + RS232_Arr->do_resetup_rs = 1; + } + if (ScibRegs.SCIRXST.bit.RXWAKE) + { + Rc = ScibRegs.SCIRXBUF.all; + } + } + + +// if (!SciaRegs.SCIRXST.bit.RXRDY) + if (cc1 == 0) +// if ((SciaRegs.SCIFFRX.bit.RXFIFST == 0) ) + { +// PieCtrlRegs.PIEACK.bit.ACK9 |= 1; +// SCI_RX_IntClear(RS232_Arr->commnumber); +// SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; +//i_led2_on_off(0); + return; // + } +//i_led2_on_off(1); + /* ? */ +// if (SciaRegs.SCIRXST.bit.RXERROR) +// { +// Rc = SciaRegs.SCIRXBUF.all;//SciaRegs.SCIRXBUF.bit.RXDT;//RS_Get(RS232_Arr->commnumber); // +// continue; +// } + cc1--; + +// if (cn==COM_1) + Rc = buf_fifo_rs_ab[cn][cc2];//SciaRegs.SCIRXBUF.all;// SciaRegs.SCIRXBUF.bit.RXDT;//RS_Get(RS232_Arr->commnumber); // +// else +// Rc = buf_fifo_rsb[cc2]; + cc2++; + + (RS232_Arr->count_recive_bytes_all)++; +//i_led2_on_off(0); + + if(RS232_Arr->RS_DataReady) + { + continue; // + } + + if (RS232_Arr->RS_Flag9bit==1) // RS485???????? + { + // + RS232_Arr->RS_FlagBegin = true; // + RS232_Arr->RS_RecvLen = 0; + RS232_Arr->RS_FlagSkiping = false; + RS232_Arr->RS_HeaderCnt = 0; + RS232_Arr->RS_Cmd = 0; + } +//i_led2_on_off(1); + if(RS232_Arr->RS_FlagSkiping) + { + (RS232_Arr->count_recive_bytes_skipped)++; + continue; // + } + + if (RS232_Arr->RS_FlagBegin) // + { + if (RS232_Arr->RS_HeaderCnt==0) // + { +//i_led2_on_off(0); + if( (Rc == CNTRL_ADDR_UNIVERSAL) || (Rc == CNTRL_ADDR && CNTRL_ADDR!=0) || ((Rc == RS232_Arr->addr_answer) && RS232_Arr->flag_LEADING) + || ((Rc == ADDR_FOR_ALL && ADDR_FOR_ALL!=0) && !RS232_Arr->flag_LEADING)) + { + RS232_Arr->addr_recive=Rc; // + RS232_Arr->RS_Header[RS232_Arr->RS_HeaderCnt++] = Rc; // +// ClearTimerRS_Live(RS232_Arr); + + RS_SetBitMode(RS232_Arr,8); // 8- + } + else + { +//i_led1_toggle(); + RS232_Arr->RS_FlagSkiping = true; // + RS232_Arr->RS_FlagBegin = false; // 9- + (RS232_Arr->count_recive_cmd_skipped)++; +//i_led1_on_off(0); + } +//i_led2_on_off(1); + } + else + { +//i_led2_on_off(0);i_led2_on_off(1); +// ClearTimerRS_Live(RS232_Arr); + + RS232_Arr->RS_Header[RS232_Arr->RS_HeaderCnt++] = Rc; // .. + + if (RS232_Arr->RS_HeaderCnt == 7 && !RS232_Arr->flag_LEADING) + { + switch (RS232_Arr->RS_Cmd) { + case CMD_RS232_MODBUS_16: + RS_Len[CMD_RS232_MODBUS_16] = (10+Rc); break; + case CMD_RS232_MODBUS_15: + RS_Len[CMD_RS232_MODBUS_15] = (10+Rc); break; + } + } + +//i_led2_on_off(0);i_led2_on_off(1); + + // - + if (RS232_Arr->RS_HeaderCnt == 2) + { + RS232_Arr->RS_Cmd = Rc; + // + // CMD_LOAD - + // CMD_STD_ANS - +// if ((RS232_Arr->RS_Cmd < 0 /*CMD_RS232_MODBUS_3*/) || (RS232_Arr->RS_Cmd > CMD_RS232_STD_ANS) || (RS_Len[RS232_Arr->RS_Cmd]<3)) + if ((RS232_Arr->RS_Cmd > CMD_RS232_STD_ANS) || (RS_Len[RS232_Arr->RS_Cmd]<3)) + { + RS_SetBitMode(RS232_Arr,9); // 9- RS485? + RS232_Arr->RS_HeaderCnt = 0; // + RS232_Arr->RS_FlagBegin = true; + RS232_Arr->RS_FlagSkiping = false; + RS232_Arr->RS_Cmd=0; + (RS232_Arr->count_recive_bad)++; + continue; + } + if(RS232_Arr->RS_Cmd == 4) { + asm(" NOP "); + } + if (RS232_Arr->RS_Cmd == CMD_RS232_LOAD) { // + RS232_Arr->RS_FlagBegin = false;// + RS232_Arr->count_recive_bytes_all = 0;// , + } + } +//i_led2_on_off(0); + if( (RS232_Arr->RS_HeaderCnt >= (int)RS_Len[RS232_Arr->RS_Cmd]) || + (RS232_Arr->RS_HeaderCnt >= (int)sizeof(RS232_Arr->RS_Header))) + { // + RS_SetBitMode(RS232_Arr,9); // 9- RS485? + RS232_Arr->RS_FlagBegin = false; + RS232_Arr->RS_FlagSkiping = true; + RS232_Arr->RS_DataReady = true; + RS232_Arr->RS_Cmd=0; + (RS232_Arr->count_recive_dirty)++; + } +//i_led2_on_off(1); + } + +//i_led2_on_off(0); + + } + else // + { + if(RS232_Arr->pRS_RecvPtr<(unsigned int *)REC_BLOC_BEGIN || RS232_Arr->pRS_RecvPtr>(unsigned int *)REC_BLOC_END) + RS232_Arr->pRS_RecvPtr = (unsigned int *)REC_BLOC_BEGIN; // , + + if(RS232_Arr->RS_PrevCmd != CMD_RS232_INITLOAD) + { + (RS232_Arr->count_recive_bad)++; + continue; // - + } + + if(RS232_Arr->RS_DataReady) // , + { // + RS232_Arr->RS_FlagSkiping = true; // + (RS232_Arr->count_recive_cmd_skipped)++; + continue; + } + + RS232_BytePtr = RS232_Arr->RS_RecvLen++ % 2; + if(RS232_BytePtr) *RS232_Arr->pRS_RecvPtr++ |= Rc; // + else *RS232_Arr->pRS_RecvPtr = Rc<<8; + + if(RS232_Arr->RS_Length <= RS232_Arr->RS_RecvLen) // + { + RS232_Arr->RS_PrevCmd = RS232_Arr->RS_Header[1] = CMD_RS232_LOAD; + RS_SetBitMode(RS232_Arr,9); // 9- RS485? + RS232_Arr->RS_FlagSkiping = true; // + RS232_Arr->RS_DataReady = true; // - + (RS232_Arr->count_recive_dirty)++; + } + } + } +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +int get_free_rs_fifo_tx(char commnumber) +{ + if(commnumber==COM_1) + { + return (16 - SciaRegs.SCIFFTX.bit.TXFFST-1); + } + else + { + return (16 - ScibRegs.SCIFFTX.bit.TXFFST-1); + } +} +/////////////////////////////////////////////////////////// +void RS_TX_Handler(RS_DATA_STRUCT *RS232_Arr) +{ + char RS232_BytePtr; + unsigned int final_flag=0, free_fifo; + unsigned int i; + + static unsigned int max_s_b = 1; // max_s_b + unsigned int final_free_fifo=0; + +// if(RS232_Arr->RS_SendBlockMode == BM_CHAR32) +// { + free_fifo = get_free_rs_fifo_tx(RS232_Arr->commnumber); + ClearTimerRS_Live(RS232_Arr); + + if (free_fifo>=max_s_b) + free_fifo=max_s_b; // max_s_b + + for (i=0;icmd_tx_stage) + { + case 2: //stage1 + if (RS232_Arr->RS_SendLen >= RS232_Arr->RS_SLength_stage1) + { + RS232_Arr->cmd_tx_stage = 1; + RS232_Arr->RS_SendLen = 0; + // break; + } + else + { + if(RS232_Arr->RS_SendBlockMode_stage1 != BM_CHAR32) + { + RS232_BytePtr = (RS232_Arr->RS_SendLen) % 2; + if(RS232_BytePtr) SCI_Send(RS232_Arr->commnumber, LOBYTE( *(RS232_Arr->pRS_SendPtr_stage1++) )); + else SCI_Send(RS232_Arr->commnumber, HIBYTE( *RS232_Arr->pRS_SendPtr_stage1 )); + } + else + SCI_Send(RS232_Arr->commnumber,*(RS232_Arr->pRS_SendPtr_stage1++)); + + (RS232_Arr->RS_SendLen)++; + break; + } + break; + + case 1: //stage2 + if (RS232_Arr->RS_SendLen >= RS232_Arr->RS_SLength_stage2) + { + RS232_Arr->cmd_tx_stage = 0; + RS232_Arr->RS_SendLen = 0; + // break; + } + else + { + if(RS232_Arr->RS_SendBlockMode_stage2 != BM_CHAR32) + { + RS232_BytePtr = (RS232_Arr->RS_SendLen) % 2; + if(RS232_BytePtr) SCI_Send(RS232_Arr->commnumber, LOBYTE( *(RS232_Arr->pRS_SendPtr_stage2++) )); + else SCI_Send(RS232_Arr->commnumber, HIBYTE( *RS232_Arr->pRS_SendPtr_stage2 )); + } + else + SCI_Send(RS232_Arr->commnumber,*(RS232_Arr->pRS_SendPtr_stage2++)); + + (RS232_Arr->RS_SendLen)++; + break; + } + break; + + + case 0: + //stage 0 + if (RS232_Arr->RS_SendLen >= RS232_Arr->RS_SLength) + { + final_flag = 1; + break; + } + else + { + if(RS232_Arr->RS_SendBlockMode != BM_CHAR32) + { + RS232_BytePtr = (RS232_Arr->RS_SendLen) % 2; + if(RS232_BytePtr) SCI_Send(RS232_Arr->commnumber, LOBYTE( *(RS232_Arr->pRS_SendPtr++) )); + else SCI_Send(RS232_Arr->commnumber, HIBYTE( *RS232_Arr->pRS_SendPtr )); + } + else + SCI_Send(RS232_Arr->commnumber,*(RS232_Arr->pRS_SendPtr++)); + + (RS232_Arr->RS_SendLen)++; + } + break; + default : + break; + } + if (final_flag) + break; + } + + if (final_flag) + { + + final_free_fifo = get_free_rs_fifo_tx(RS232_Arr->commnumber); + + if (final_free_fifo>=15) // ? ? + { + if(RS232_Arr->RS_SendBlockMode == BM_CHAR32) + { +// if (max_s_b>1) +// RS_Wait4OK(RS232_Arr->commnumber); + + RS_SetBitMode(RS232_Arr,9); /* 9- RS485?*/ + RS_LineToReceive(RS232_Arr->commnumber); /* RS485 */ + + RS232_Arr->flag_TIMEOUT_to_Send=false; /* */ + } + + if (RS232_Arr->RS_DataWillSend) + RS232_Arr->RS_DataSended = 1; + RS232_Arr->RS_DataWillSend = 0; + + EnableUART_Int_RX(RS232_Arr->commnumber); /* */ + } + } + +} +// + + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +//#pragma CODE_SECTION(RSA_TX_Handler,".fast_run2"); +interrupt void RSA_TX_Handler(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG92; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + +#if (_ENABLE_INTERRUPT_RS232_LED2) +i_led2_on_off(1); +#endif + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.rsa) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.rsa) + i_led2_on_off_special(1); +#endif + + + + EINT; + + +// i_led2_on_off(1); + + // Insert ISR Code here....... + RS_TX_Handler(&rs_a); + +// i_led2_on_off(0); + + // Next line for debug only (remove after inserting ISR Code): +// ESTOP0; + SCIa_TX_IntClear(); +// SciaRegs.SCIFFTX.bit.TXINTCLR=1; // Clear SCI Interrupt flag + PieCtrlRegs.PIEACK.all |= BIT8; // Issue PIE ACK + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.rsa) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.rsa) + i_led2_on_off_special(0); +#endif + + +#if (_ENABLE_INTERRUPT_RS232_LED2) +i_led2_on_off(0); +#endif + +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +//#pragma CODE_SECTION(RSB_TX_Handler,".fast_run2"); +interrupt void RSB_TX_Handler(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG94; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_16_ON; +#endif + +#if (_ENABLE_INTERRUPT_RS232_LED2) +i_led2_on_off(1); +#endif + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.rsb) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.rsb) + i_led2_on_off_special(1); +#endif + + EINT; + + // i_led2_on_off(1); + + // Insert ISR Code here....... + RS_TX_Handler(&rs_b); + +// i_led2_on_off(0); + + // Next line for debug only (remove after inserting ISR Code): +// ESTOP0; + SCIb_TX_IntClear(); +// SciaRegs.SCIFFTX.bit.TXINTCLR=1; // Clear SCI Interrupt flag + PieCtrlRegs.PIEACK.all |= BIT8; // Issue PIE ACK + + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.rsb) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.rsb) + i_led2_on_off_special(0); +#endif + +#if (_ENABLE_INTERRUPT_RS232_LED2) +i_led2_on_off(0); +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_16_OFF; +#endif + + +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +//#pragma CODE_SECTION(RSA_RX_Handler,".fast_run2"); +interrupt void RSA_RX_Handler(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG91; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + +#if (_ENABLE_INTERRUPT_RS232_LED2) +i_led2_on_off(1); +#endif + + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.rsa) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.rsa) + i_led2_on_off_special(1); +#endif + + EINT; + // i_led1_on_off(1); + + + // Insert ISR Code here....... + // ClearTimerRS_Live(&rs_a); + +// i_led2_on_off(0); + //RS_RX_Handler(&rs_a); + RS_RXA_Handler_fast(&rs_a); + // my_test_rs(); + + // Next line for debug only (remove after inserting ISR Code): +// ESTOP0; +// i_led2_on_off(0); + // i_led1_on_off(0); + + SCIa_RX_IntClear(); + +// SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag +// SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag + + PieCtrlRegs.PIEACK.all |= BIT8; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.rsa) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.rsa) + i_led2_on_off_special(0); +#endif + +#if (_ENABLE_INTERRUPT_RS232_LED2) +i_led2_on_off(0); +#endif + +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +//#pragma CODE_SECTION(RSB_RX_Handler,".fast_run2"); +interrupt void RSB_RX_Handler(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all; + IER |= M_INT9; + IER &= MINT9; // Set "global" priority + PieCtrlRegs.PIEIER9.all &= MG93; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_17_ON; +#endif + + +#if (_ENABLE_INTERRUPT_RS232_LED2) +i_led2_on_off(1); +#endif + + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.rsb) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.rsb) + i_led2_on_off_special(1); +#endif + + EINT; + + // i_led1_on_off(1); + // Insert ISR Code here....... + //ClearTimerRS_Live(&rs_b); + RS_RXA_Handler_fast(&rs_b); + // i_led1_on_off(0); + + // Next line for debug only (remove after inserting ISR Code): +// ESTOP0; + SCIb_RX_IntClear(); + + PieCtrlRegs.PIEACK.all |= BIT8; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER9.all = TempPIEIER; + + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.rsb) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.rsb) + i_led2_on_off_special(0); +#endif + +#if (_ENABLE_INTERRUPT_RS232_LED2) +i_led2_on_off(0); +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_17_OFF; +#endif + +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +/// +////////////////////////////////////////////////////// +void RS_LineToSend(char commnumber) +{ +/* RS485. , + RS485 B.*/ +// addr_xilinx(TR485) = 0xffffffff; + +// SCIa_RX_Int_disable(); // +// SCIa_TX_Int_enable(); // + if (commnumber==COM_1) + { +// ScibRegs.SCICTL1.bit.RXENA=0; + SciaRegs.SCICTL1.bit.RXENA=0; +// SciaRegs.SCICTL1.bit.TXENA=1; + } + else + { + EnableSendRS485(); + ScibRegs.SCICTL1.bit.RXENA=0; +// ScibRegs.SCICTL1.bit.TXENA=1; + } + +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void RS_LineToReceive(char commnumber) +{ +/* RS485. , + RS485 B.*/ +// addr_xilinx(TR485) = 0x0; + +// SCIa_RX_Int_enable(); // +// SCIa_TX_Int_disable(); // + + if (commnumber==COM_1) + { + SCIa_RX_IntClear(); + } + else + { + EnableReceiveRS485(); + +// pause_1000(100); + + SCIb_RX_IntClear(); +// SCIb_TX_IntClear(); // clear TX FIFO interrupts + +// my_test_rs(commnumber); + // SCIb_RX_IntClear(); +// SCIb_TX_IntClear(); // clear TX FIFO interrupts + + } +// pause_1000(1000); + EnableUART_Int_RX(commnumber); /* UART */ +// my_test_rs(commnumber); + + if (commnumber==COM_1) + { +// SCIa_RX_IntClear(); + SciaRegs.SCICTL1.bit.RXENA=1; + } + else + { +// SCIb_RX_IntClear(); + ScibRegs.SCICTL1.bit.RXENA=1; + } + + +} + + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +static void RS_SetLineSpeed(char commnumber,unsigned long speed) +{ +float SciBaud; + + SciBaud = ((float)LSPCLK/(speed*8.0))-1.0; + + if((SciBaud-(unsigned int)SciBaud)>0.5) SciBaud++; + + + if(commnumber==COM_1) + { + SciaRegs.SCIHBAUD = HIBYTE((int)SciBaud); + SciaRegs.SCILBAUD = LOBYTE((int)SciBaud); + } + + if(commnumber==COM_2) + { + ScibRegs.SCIHBAUD = HIBYTE((int)SciBaud); + ScibRegs.SCILBAUD = LOBYTE((int)SciBaud); + } + + +} + + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////// +/// +////////////////////////////////////////////////////// +void EnableUART_Int_RX(char commnumber) +{ +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_18_ON; +#endif + + switch (commnumber) + { + case COM_1: //SciaRegs.SCICTL2.bit.RXBKINTENA = 0;//1; //enableUARTInt_A(); + SciaRegs.SCIFFRX.bit.RXFFIENA = 1; +// SciaRegs.SCICTL2.bit.TXINTENA = 1; + SciaRegs.SCIFFTX.bit.TXFFIENA = 0; + rs_a.RS_OnTransmitedData = 0; + SciaRegs.SCICTL1.bit.RXENA = 1; + SciaRegs.SCICTL1.bit.TXENA = 0; + break; + + case COM_2: //ScibRegs.SCICTL2.bit.RXBKINTENA = 0;//1; //enableUARTInt_A(); + ScibRegs.SCIFFRX.bit.RXFFIENA = 1; +// SciaRegs.SCICTL2.bit.TXINTENA = 1; + ScibRegs.SCIFFTX.bit.TXFFIENA = 0; + rs_b.RS_OnTransmitedData = 0; + ScibRegs.SCICTL1.bit.RXENA = 1; + ScibRegs.SCICTL1.bit.TXENA = 0; + + break; + } + +} + +////////////////////////////////////////////////////// +/// +////////////////////////////////////////////////////// +void EnableUART_Int_TX(char commnumber) +{ + +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_18_OFF; +#endif + + switch (commnumber) + { + case COM_1: rs_a.RS_OnTransmitedData = 1; + //SciaRegs.SCICTL2.bit.RXBKINTENA = 0; + SciaRegs.SCIFFRX.bit.RXFFIENA = 0; +// SciaRegs.SCICTL2.bit.TXINTENA = 1; + SciaRegs.SCIFFTX.bit.TXFFIENA = 1;//EnableUART_IntW_A(); + SciaRegs.SCICTL1.bit.RXENA = 0; + SciaRegs.SCICTL1.bit.TXENA = 1; + break; + + case COM_2: rs_b.RS_OnTransmitedData = 1; + //ScibRegs.SCICTL2.bit.RXBKINTENA = 0; + ScibRegs.SCIFFRX.bit.RXFFIENA = 0; +// SciaRegs.SCICTL2.bit.TXINTENA = 1; + ScibRegs.SCIFFTX.bit.TXFFIENA = 1;//EnableUART_IntW_A(); + ScibRegs.SCICTL1.bit.RXENA = 0; + ScibRegs.SCICTL1.bit.TXENA = 1; + break; + } +} + + + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +void RS_SetAdrAnswerController(RS_DATA_STRUCT *RS232_Arr,int set_addr_answer) +{ + RS232_Arr->addr_answer = set_addr_answer; /* ( )*/ +} + +void RS_SetControllerLeading(RS_DATA_STRUCT *RS232_Arr,int bool) +{ + RS232_Arr->flag_LEADING = bool; /* ( )*/ +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void RS_SetLineMode(char commnumber, int bit, char parity, int stop) +{ +/* +SCICCR - SCI Communication Control Register +Bit Bit Name Designation Functions +20 SCI CHAR20 SCICHAR Select the character (data) length (one to eight bits). +3 ADDR/IDLE MODE ADDRIDLE_MODE The idle-line mode (0) is usually used for normal communications because the address-bit mode adds an extra bit to the frame. The idle-line mode does not add this extra bit and is compatible with RS-232 type communications. +4 LOOP BACK ENABLE LOOPBKENA This bit enables (1) the Loop Back test mode where the Tx pin is internally connected to the Rx pin. +5 PARITY ENABLE PARITYENA Enables the parity function if set to 1, or disables the parity function if cleared to 0. +6 EVEN/ODD PARITY PARITY If parity is enabled, selects odd parity if cleared to 0 or even parity if set to 1. +7 STOP BITS STOPBITS Determines the number of stop bits transmittedone stop bit if cleared to 0 or two stop bits if set to 1. +*/ + + if (commnumber==COM_1) + { + if(bit>0 && bit<9) SciaRegs.SCICCR.bit.SCICHAR = bit-1; + + switch(parity) + { + case 'N': SciaRegs.SCICCR.bit.PARITYENA = 0; + break; + case 'O': SciaRegs.SCICCR.bit.PARITYENA = 1; + SciaRegs.SCICCR.bit.PARITY = 0; + break; + case 'E': SciaRegs.SCICCR.bit.PARITYENA = 1; + SciaRegs.SCICCR.bit.PARITY = 1; + break; + } + + if (stop==1) SciaRegs.SCICCR.bit.STOPBITS = 0; + if (stop==2) SciaRegs.SCICCR.bit.STOPBITS = 1; + + SciaRegs.SCICCR.bit.LOOPBKENA = 0; //0 + SciaRegs.SCICCR.bit.ADDRIDLE_MODE = 0; + } + + if (commnumber==COM_2) + { + if(bit>0 && bit<9) ScibRegs.SCICCR.bit.SCICHAR = bit-1; + + switch(parity) + { + case 'N': ScibRegs.SCICCR.bit.PARITYENA = 0; + break; + case 'O': ScibRegs.SCICCR.bit.PARITYENA = 1; + ScibRegs.SCICCR.bit.PARITY = 0; + break; + case 'E': ScibRegs.SCICCR.bit.PARITYENA = 1; + ScibRegs.SCICCR.bit.PARITY = 1; + break; + } + + if (stop==1) ScibRegs.SCICCR.bit.STOPBITS = 0; + if (stop==2) ScibRegs.SCICCR.bit.STOPBITS = 1; + + ScibRegs.SCICCR.bit.LOOPBKENA = 0; //0 + ScibRegs.SCICCR.bit.ADDRIDLE_MODE = 0; + } + + +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void RS_SetBitMode(RS_DATA_STRUCT *RS232_Arr, int n) +{ + if(n == 8) + { + RS_SetLineMode(RS232_Arr->commnumber,8,'N',1); /* */ + RS232_Arr->RS_Flag9bit=0; + } + if(n == 9) + { + RS_SetLineMode(RS232_Arr->commnumber,8,'N',1); /* */ + RS232_Arr->RS_Flag9bit=1; + RS232_Arr->cmd_tx_stage = 0; + } + + +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void clear_timer_rs_live(RS_DATA_STRUCT *rs_arr) { + ClearTimerRS_Live(rs_arr); +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void clear_timer_rs_live_mpu(RS_DATA_STRUCT *rs_arr) { + rs_arr->time_wait_rs_out_mpu = 0; +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void resetup_rs(RS_DATA_STRUCT *rs_arr) { + + RS_LineToReceive(rs_arr->commnumber); // RS485 + RS_SetBitMode(rs_arr, 9); + RS_SetControllerLeading(rs_arr, false); + ClearTimerRS_Live(rs_arr); +// return -1; +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void resetup_mpu_rs(RS_DATA_STRUCT *rs_arr) { + + +// RS_SetControllerLeading(rs_arr,false); + +// RS_LineToReceive(commnumber); // RS485 + +// RS_SetBitMode(&rs_b,9); +// rs_b.RS_PrevCmd = 0; // + + ////// + + if (rs_arr->commnumber==COM_1) + SCIa_SW_Reset() + else + SCIb_SW_Reset(); + + + + RS_LineToReceive(rs_arr->commnumber); // RS485 + RS_SetBitMode(rs_arr, 9); + RS_SetControllerLeading(rs_arr, false); + ClearTimerRS_Live(rs_arr); + rs_arr->RS_PrevCmd = 0; // + + rs_arr->RS_DataSended = 0; + rs_arr->RS_DataWillSend = 0; + + rs_arr->RS_DataReadyAnswer = 0; + rs_arr->RS_DataReadyAnswerAnalyze = 0; + + rs_arr->RS_DataReadyRequest = 0; + rs_arr->do_resetup_rs = 0; + + +// SCIb_RX_IntClear(); +// SCIb_TX_IntClear(); // clear TX FIFO interrupts + + EnableUART_Int_RX(rs_arr->commnumber); // UART + +// return -1; + +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +/* RS */ +int test_rs_live(RS_DATA_STRUCT *rs_arr) +{ + if (rs_arr->time_wait_rs_out>(2*RS_TIME_OUT)) + return 2; /* */ + if (rs_arr->time_wait_rs_out>RS_TIME_OUT) + return 0; /* */ + if (rs_arr->time_wait_rs_out_mpu>RS_TIME_OUT_MPU) + return 4; /* */ + + if (rs_arr->time_wait_rs_out>RS_TIME_OUT_HMI) + return 5; /* */ + + else + return 1; /* */ +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void inc_RS_timeout_cicle(void) +{ + + unsigned int i, t_refresh; + static unsigned int old_time_rs = 0; + + t_refresh = get_delta_milisec(&old_time_rs, 1); + if (t_refresh>1000) + t_refresh = 1000; + if (t_refresh<1) + t_refresh = 1; + + if (rs_a.time_wait_rs_out=RS_TIME_OUT_LOST) + resetup_mpu_rs(&rs_a); + } + else + { + if (rs_b.time_wait_rs_lost>=RS_TIME_OUT_LOST) + resetup_mpu_rs(&rs_b); + } + +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void clear_buffers_rs(RS_DATA_STRUCT *rs_arr) +{ + unsigned int i; + + + for (i=0;iRS_Header[i] = 0; + + for (i=0;ibuffer[i] = 0; + +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +#ifdef _USE_RS_FIFO +void SetupUART(char commnumber, unsigned long speed_baud) +{ + // x1 Free run. Continues SCI operation regardless of suspend + // 10 Complete current receive/transmit sequence before stopping + // 00 Immediate stop on suspend + + + if(commnumber==COM_1) + { + SciaRegs.SCIPRI.bit.FREE = 1; + SciaRegs.SCIPRI.bit.SOFT = 0; + +// Initialize SCI-A: +// Note: Clocks were turned on to the SCIA peripheral +// in the InitSysCtrl() function + + EALLOW; + GpioMuxRegs.GPFMUX.bit.SCIRXDA_GPIOF5=1; + GpioMuxRegs.GPFMUX.bit.SCITXDA_GPIOF4=1; + EDIS; + + RS_SetLineMode(commnumber,8,'N',1); + +/////// + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + + SciaRegs.SCICTL1.all = 0; +// SciaRegs.SCICTL1.bit.RXENA = 1; // enable RX, +// SciaRegs.SCICTL1.bit.TXENA = 1; // enable TX + SciaRegs.SCICTL1.bit.RXENA = 0; // disable RX, + SciaRegs.SCICTL1.bit.TXENA = 0; // disable TX + SciaRegs.SCICTL1.bit.RXERRINTENA = 1; //Receive error interrupt enabled + SciaRegs.SCICTL1.bit.TXWAKE = 0; + SciaRegs.SCICTL1.bit.SLEEP = 0; + + SciaRegs.SCICTL2.bit.TXINTENA = 0;//1; + SciaRegs.SCICTL2.bit.RXBKINTENA = 0;//1; + + RS_SetLineSpeed(commnumber,speed_baud); /* */ + + SciaRegs.SCICCR.bit.LOOPBKENA = 0; // Enable loop back + +// SciaRegs.SCIFFTX.all=0xC028; +//SCIFFTX + SciaRegs.SCIFFTX.bit.SCIFFENA=1; // SCI FIFO enable + + SciaRegs.SCIFFTX.bit.TXFFILIL = 0;//1; // TXFFIL40 Transmit FIFO interrupt level bits. Transmit FIFO will generate interrupt when the FIFO + // status bits (TXFFST40) and FIFO level bits (TXFFIL40 ) match (less than or equal to). + + SciaRegs.SCIFFTX.bit.TXFIFOXRESET=0; + SciaRegs.SCIFFTX.bit.TXFFST = 0; + SciaRegs.SCIFFTX.bit.TXFFINT = 0; + SciaRegs.SCIFFTX.bit.TXINTCLR = 0; + SciaRegs.SCIFFTX.bit.TXFFIENA = 0; // Transmit FIFO interrrupt enable + + SciaRegs.SCIFFTX.bit.SCIRST = 1; + +//SCIFFRX +// SciaRegs.SCIFFRX.all=0x0028; +// SciaRegs.SCIFFRX.all=0x0022; + SciaRegs.SCIFFRX.bit.RXFFIL = 1; // 4:0 Interrupt level + SciaRegs.SCIFFRX.bit.RXFFIENA = 1; // Interrupt enable + + SciaRegs.SCIFFCT.all=0x00; // FIFO control register + SciaRegs.SCIFFCT.bit.ABDCLR=1; + SciaRegs.SCIFFCT.bit.CDC=0; + SciaRegs.SCIFFCT.bit.FFTXDLY = 0;//100; + + +// SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + SciaRegs.SCICTL1.bit.SWRESET = 1; // Relinquish SCI from Reset + + SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1; + SciaRegs.SCIFFRX.bit.RXFIFORESET=1; + + EALLOW; + PieVectTable.RXAINT = &RSA_RX_Handler; + PieVectTable.TXAINT = &RSA_TX_Handler; + PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1 + PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2 + IER |= M_INT9; // Enable CPU INT + EDIS; + + SetupArrCmdLength(); + clear_buffers_rs(&rs_a); + + RS_SetControllerLeading(&rs_a,false); + + RS_LineToReceive(commnumber); // RS485 + EnableUART_Int_RX(commnumber); // UART + + RS_SetBitMode(&rs_a,9); + rs_a.RS_PrevCmd = 0; // + SCIa_RX_IntClear(); + SCIa_TX_IntClear(); // clear TX FIFO interrupts + + resetup_mpu_rs(&rs_a); + + + + } + + if(commnumber==COM_2) + { +// Initialize SCI-B: +// Note: Clocks were turned on to the SCIA peripheral +// in the InitSysCtrl() function + + ScibRegs.SCIPRI.bit.FREE = 1; + ScibRegs.SCIPRI.bit.SOFT = 0; + + EALLOW; + GpioMuxRegs.GPGMUX.bit.SCIRXDB_GPIOG5=1; + GpioMuxRegs.GPGMUX.bit.SCITXDB_GPIOG4=1; + GpioMuxRegs.GPBMUX.bit.C5TRIP_GPIOB14=0; + + GpioMuxRegs.GPBDIR.bit.GPIOB14=1; + + EDIS; + RS_SetLineMode(commnumber,8,'N',1); + +/////// + ScibRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + + ScibRegs.SCICTL1.all = 0; +// SciaRegs.SCICTL1.bit.RXENA = 1; // enable RX, +// SciaRegs.SCICTL1.bit.TXENA = 1; // enable TX + ScibRegs.SCICTL1.bit.RXENA = 0; // disable RX, + ScibRegs.SCICTL1.bit.TXENA = 0; // disable TX + ScibRegs.SCICTL1.bit.RXERRINTENA = 1; //Receive error interrupt enabled + ScibRegs.SCICTL1.bit.TXWAKE = 0; + ScibRegs.SCICTL1.bit.SLEEP = 0; + + ScibRegs.SCICTL2.bit.TXINTENA = 0;//1; + ScibRegs.SCICTL2.bit.RXBKINTENA =0;// 1; + + + RS_SetLineSpeed(commnumber,speed_baud); /* */ + + ScibRegs.SCICCR.bit.LOOPBKENA = 0; // Enable loop back + +// SciaRegs.SCIFFTX.all=0xC028; +//SCIFFTX + ScibRegs.SCIFFTX.bit.SCIFFENA=1; // SCI FIFO enable + + ScibRegs.SCIFFTX.bit.TXFFILIL = 0;//1; // TXFFIL40 Transmit FIFO interrupt level bits. Transmit FIFO will generate interrupt when the FIFO + // status bits (TXFFST40) and FIFO level bits (TXFFIL40 ) match (less than or equal to). + + ScibRegs.SCIFFTX.bit.TXFIFOXRESET=0; + ScibRegs.SCIFFTX.bit.TXFFST = 0; + ScibRegs.SCIFFTX.bit.TXFFINT = 0; + ScibRegs.SCIFFTX.bit.TXINTCLR = 0; + ScibRegs.SCIFFTX.bit.TXFFIENA = 0; // Transmit FIFO interrrupt enable + + ScibRegs.SCIFFTX.bit.SCIRST = 1; + +//SCIFFRX +// SciaRegs.SCIFFRX.all=0x0028; +// SciaRegs.SCIFFRX.all=0x0022; + ScibRegs.SCIFFRX.bit.RXFFIL = 1; // 4:0 Interrupt level + ScibRegs.SCIFFRX.bit.RXFFIENA = 1; // Interrupt enable + + ScibRegs.SCIFFCT.all=0x00; // FIFO control register + ScibRegs.SCIFFCT.bit.ABDCLR=1; + ScibRegs.SCIFFCT.bit.CDC=0; + ScibRegs.SCIFFCT.bit.FFTXDLY = 0;//100; + + ScibRegs.SCICTL1.bit.SWRESET = 1; // Relinquish SCI from Reset + ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1; + ScibRegs.SCIFFRX.bit.RXFIFORESET=1; + + EALLOW; + PieVectTable.RXBINT = &RSB_RX_Handler; + PieVectTable.TXBINT = &RSB_TX_Handler; + + PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3 + PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4 + + IER |= M_INT9; // Enable CPU INT + EDIS; + + SetupArrCmdLength(); + clear_buffers_rs(&rs_b); + + + RS_SetControllerLeading(&rs_b,false); + + RS_LineToReceive(commnumber); // RS485 + EnableUART_Int_RX(commnumber); // UART + + RS_SetBitMode(&rs_b,9); + rs_b.RS_PrevCmd = 0; // + SCIb_RX_IntClear(); + SCIb_TX_IntClear(); // clear TX FIFO interrupts + + resetup_mpu_rs(&rs_b); + + } + + + + +} +#else +// +void SetupUART(char commnumber, unsigned long speed_baud) +{ + + if(commnumber==COM_1) + { +// Initialize SCI-A: +// Note: Clocks were turned on to the SCIA peripheral +// in the InitSysCtrl() function + + EALLOW; + GpioMuxRegs.GPFMUX.bit.SCIRXDA_GPIOF5=1; + GpioMuxRegs.GPFMUX.bit.SCITXDA_GPIOF4=1; + EDIS; + + RS_SetLineMode(commnumber,8,'N',1); + +// enable TX, RX, internal SCICLK, +// Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCIFFCT.bit.ABDCLR=1; + SciaRegs.SCIFFCT.bit.CDC=0; + + SciaRegs.SCICTL1.bit.RXERRINTENA=0; + SciaRegs.SCICTL1.bit.SWRESET=0; + SciaRegs.SCICTL1.bit.TXWAKE=0; + SciaRegs.SCICTL1.bit.SLEEP=0; + SciaRegs.SCICTL1.bit.TXENA=1; + SciaRegs.SCICTL1.bit.RXENA=1; + + SciaRegs.SCIFFTX.bit.SCIFFENA=0; // fifo off + SciaRegs.SCIFFRX.bit.RXFFIL=1; // + + EALLOW; + PieVectTable.RXAINT = &RSA_RX_Handler; + PieVectTable.TXAINT = &RSA_TX_Handler; + PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1 + PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2 + IER |= M_INT9; // Enable CPU INT + EDIS; + + SetupArrCmdLength(); + RS_SetLineSpeed(commnumber,speed_baud); /* */ + RS_SetControllerLeading(&rs_a,false); + + RS_LineToReceive(commnumber); // RS485 + EnableUART_Int(commnumber); // UART + + RS_SetBitMode(&rs_a,9); + rs_a.RS_PrevCmd = 0; // + SCI_RX_IntClear(commnumber); + + SciaRegs.SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset +// SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1; +// SciaRegs.SCIFFRX.bit.RXFIFORESET=1; + } + + if(commnumber==COM_2) + { +// Initialize SCI-B: +// Note: Clocks were turned on to the SCIA peripheral +// in the InitSysCtrl() function + + EALLOW; + GpioMuxRegs.GPGMUX.bit.SCIRXDB_GPIOG5=1; + GpioMuxRegs.GPGMUX.bit.SCITXDB_GPIOG4=1; + GpioMuxRegs.GPBMUX.bit.C5TRIP_GPIOB14=0; + + GpioMuxRegs.GPBDIR.bit.GPIOB14=1; + + EDIS; + RS_SetLineMode(commnumber,8,'N',1); + +// enable TX, RX, internal SCICLK, +// Disable RX ERR, SLEEP, TXWAKE + ScibRegs.SCIFFCT.bit.CDC=0; + ScibRegs.SCIFFCT.bit.ABDCLR=1; + ScibRegs.SCICTL1.bit.RXERRINTENA=0; + ScibRegs.SCICTL1.bit.SWRESET=0; + ScibRegs.SCICTL1.bit.TXWAKE=0; + ScibRegs.SCICTL1.bit.SLEEP=0; + ScibRegs.SCICTL1.bit.TXENA=1; + ScibRegs.SCICTL1.bit.RXENA=1; + + ScibRegs.SCIFFTX.bit.SCIFFENA=0; // fifo off + ScibRegs.SCIFFRX.bit.RXFFIL=1; // + + EALLOW; + PieVectTable.RXBINT = &RSB_RX_Handler; + PieVectTable.TXBINT = &RSB_TX_Handler; + + PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, INT3 + PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, INT4 + IER |= M_INT9; // Enable CPU INT + EDIS; + + SetupArrCmdLength(); + RS_SetLineSpeed(commnumber,speed_baud); /* */ + RS_SetControllerLeading(&rs_b,false); + + RS_LineToReceive(commnumber); // RS485 + EnableUART_Int(commnumber); // UART + + RS_SetBitMode(&rs_b,9); + rs_b.RS_PrevCmd = 0; // + SCI_RX_IntClear(commnumber); + + ScibRegs.SCICTL1.bit.SWRESET=1; // Relinquish SCI from Reset + +// SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1; +// SciaRegs.SCIFFRX.bit.RXFIFORESET=1; + + } + + +} +#endif + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void SCI_Send(char commnumber, char bs) +{ + switch (commnumber) + { + case COM_1: SCIa_Send(bs); + break; + case COM_2: SCIb_Send(bs); + break; + } + +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + + +#ifdef _USE_RS_FIFO + +void RS_Wait4OK(char commnumber) +{ + switch (commnumber) + { + case COM_1: while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}//SCIa_Wait4OK(); + break; + case COM_2: while (ScibRegs.SCIFFTX.bit.TXFFST != 0) {}//SCIb_Wait4OK(); + break; + } +} + +void RS_Wait4OK_TXRDY(char commnumber) +{ + switch (commnumber) + { + case COM_1: while (SciaRegs.SCICTL2.bit.TXEMPTY != 0) {} + break; + case COM_2: while (ScibRegs.SCICTL2.bit.TXEMPTY != 0) {} + break; + } +} + + +#else +void RS_Wait4OK(char commnumber) +{ + switch (commnumber) + { + case COM_1: SCIa_Wait4OK(); + break; + case COM_2: SCIb_Wait4OK(); + break; + } +} +#endif + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + + + +void SetCntrlAddr (int cntrl_addr,int cntrl_addr_for_all) +{ + CNTRL_ADDR = cntrl_addr; + ADDR_FOR_ALL = cntrl_addr_for_all; +} + +void Poke(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned long Address; + unsigned int Data; + + Address = RS232_Arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (RS232_Arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (RS232_Arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (RS232_Arr->RS_Header[2] & 0xFF); + + Data = 0; + Data = (Data<<8) | (RS232_Arr->RS_Header[7] & 0xFF); + Data = (Data<<8) | (RS232_Arr->RS_Header[6] & 0xFF); + + WriteMemory(Address,Data); + + Answer(RS232_Arr, CMD_RS232_POKE); +} + +void Peek(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned long Address; + unsigned int Data, crc; + + Address = RS232_Arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (RS232_Arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (RS232_Arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (RS232_Arr->RS_Header[2] & 0xFF); + + Data = 0; + Data = i_ReadMemory(Address); + + RS232_Arr->buffer[0] = RS232_Arr->addr_recive; //CNTRL_ADDR; + RS232_Arr->buffer[1] = CMD_RS232_PEEK; + + RS232_Arr->buffer[2] = LOBYTE(Data); + RS232_Arr->buffer[3] = HIBYTE(Data); + RS232_Arr->buffer[4] = 0; + RS232_Arr->buffer[5] = 0; + + crc = 0xffff; + crc = GetCRC16_IBM(crc, RS232_Arr->buffer, 6); + + RS232_Arr->buffer[6] = LOBYTE(crc); + RS232_Arr->buffer[7] = HIBYTE(crc); + RS232_Arr->buffer[8] = 0; + RS232_Arr->buffer[9] = 0; + + RS_Send(RS232_Arr,RS232_Arr->buffer, 10); +} + +static char _GetByte(unsigned int *addr, int32 offs) +{ + unsigned int *address; + unsigned int byte; + + address = addr + offs/2; + byte = *address; + if(offs%2) return LOBYTE(byte); + else return HIBYTE(byte); +} + +void Answer(RS_DATA_STRUCT *RS232_Arr,int n) +{ + int crc; + + RS232_Arr->buffer[0] = RS232_Arr->addr_recive; //CNTRL_ADDR; + RS232_Arr->buffer[1] = n; + + crc = 0xffff; + crc = GetCRC16_IBM( crc, RS232_Arr->buffer, 2); + + RS232_Arr->buffer[2] = LOBYTE(crc); + RS232_Arr->buffer[3] = HIBYTE(crc); + + RS232_Arr->buffer[4] = 0; + RS232_Arr->buffer[5] = 0; + RS_Send(RS232_Arr,RS232_Arr->buffer, 6); +} + + + +void Load(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned int rcrc, crc; + + crc = (_GetByte(RS232_Arr->pRecvPtr, RS232_Arr->RS_Length-1) << 8) + + _GetByte(RS232_Arr->pRecvPtr, RS232_Arr->RS_Length-2); + + RS232_Arr->RS_Header[0] = RS232_Arr->addr_recive; + +// CNTRL_ADDR; + RS232_Arr->RS_Header[1]=CMD_RS232_LOAD; + + rcrc = 0xffff; + rcrc = GetCRC16_IBM( rcrc, RS232_Arr->RS_Header, 2); + rcrc = GetCRC16_B( rcrc, RS232_Arr->pRecvPtr, RS232_Arr->RS_Length-2); + + if(rcrc == crc) + { + Answer(RS232_Arr,CMD_RS232_LOAD); + RS232_Arr->BS_LoadOK = true; + } + else + { + RS232_Arr->BS_LoadOK = false; + RS_LineToReceive(RS232_Arr->commnumber); // RS485 + RS_SetBitMode(RS232_Arr,9); + } +} + +void InitLoad(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned long Address; + + Address = RS232_Arr->RS_Header[5] & 0xFF; + Address = (Address<<8) | (RS232_Arr->RS_Header[4] & 0xFF); + Address = (Address<<8) | (RS232_Arr->RS_Header[3] & 0xFF); + Address = (Address<<8) | (RS232_Arr->RS_Header[2] & 0xFF); + + RS232_Arr->RS_Length = RS232_Arr->RS_Header[9] & 0xFF; + RS232_Arr->RS_Length = (RS232_Arr->RS_Length<<8) | (RS232_Arr->RS_Header[8] & 0xFF); + RS232_Arr->RS_Length = (RS232_Arr->RS_Length<<8) | (RS232_Arr->RS_Header[7] & 0xFF); + RS232_Arr->RS_Length = (RS232_Arr->RS_Length<<8) | (RS232_Arr->RS_Header[6] & 0xFF); + + RS232_Arr->RS_Length += 2; + RS232_Arr->pRS_RecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + RS232_Arr->pRecvPtr = (unsigned int *)Address; //(unsigned int *)Address; + + Answer(RS232_Arr,CMD_RS232_INITLOAD); +} + +int GetCommand(RS_DATA_STRUCT *RS232_Arr) +{ + int cmd; + unsigned int crc, rcrc; + + if(RS232_Arr->RS_DataReady) // RS + { + RS232_Arr->RS_DataReady = false; + cmd = RS232_Arr->RS_Header[1]; // + + // CRC + if((RS_Len[cmd]<3) || (RS_Len[cmd]>MAX_RECEIVE_LENGTH)) + { + (RS232_Arr->count_recive_bad)++; + RS_LineToReceive(RS232_Arr->commnumber); // RS485 + RS_SetBitMode(RS232_Arr,9); + + if (RS232_Arr->RS_DataSended) + RS232_Arr->RS_DataSended = 0; + return -1; + } + if(cmd == 4) { + asm(" NOP "); + } + + if(cmd == CMD_RS232_LOAD) // + { + RS232_Arr->RS_PrevCmd = cmd; + return cmd; // crc + } + else // + { + // crc + crc = (RS232_Arr->RS_Header[RS_Len[cmd]-1] << 8) | + (RS232_Arr->RS_Header[RS_Len[cmd]-2]) ; + } + // crc + rcrc = 0xffff; + rcrc = GetCRC16_IBM( rcrc, RS232_Arr->RS_Header, (RS_Len[cmd]-2) ); + + if(crc == rcrc) // crc + { + (RS232_Arr->count_recive_ok)++; + + RS232_Arr->RS_PrevCmd = cmd; + if (RS232_Arr->RS_DataSended) + { + RS232_Arr->RS_DataSended = 0; + RS232_Arr->RS_DataReadyAnswer = 1; + } + return cmd; + } + else + { + (RS232_Arr->count_recive_error_crc)++; + + RS_SetAdrAnswerController(RS232_Arr,0); + RS_SetControllerLeading(RS232_Arr, false); + + RS_LineToReceive(RS232_Arr->commnumber); // RS485 + RS_SetBitMode(RS232_Arr,9); + + if (RS232_Arr->RS_DataSended) + RS232_Arr->RS_DataSended = 0; + + } } + + return -1; +} + +void ExtendBios(RS_DATA_STRUCT *RS232_Arr) +{ + volatile unsigned long Address1,Address2; + volatile unsigned long Length, LengthW,i; + unsigned int code1,code2, crc; + + unsigned long AdrOut1,AdrOut2,LengthOut; + unsigned int cerr, repl, count_ok, return_code, old_started; + volatile unsigned int go_to_reset = 0, go_to_set_baud = 0; + unsigned long set_baud; + + //int code_eeprom; + old_started = x_parallel_bus_project.flags.bit.started; + + + + Address1 = RS232_Arr->RS_Header[5] & 0xFF; + Address1 = (Address1<<8) | (RS232_Arr->RS_Header[4] & 0xFF); + Address1 = (Address1<<8) | (RS232_Arr->RS_Header[3] & 0xFF); + Address1 = (Address1<<8) | (RS232_Arr->RS_Header[2] & 0xFF); + + Address2 = RS232_Arr->RS_Header[9] & 0xFF; + Address2 = (Address2<<8) | (RS232_Arr->RS_Header[8] & 0xFF); + Address2 = (Address2<<8) | (RS232_Arr->RS_Header[7] & 0xFF); + Address2 = (Address2<<8) | (RS232_Arr->RS_Header[6] & 0xFF); + + Length = RS232_Arr->RS_Header[13] & 0xFF; + Length = (Length<<8) | (RS232_Arr->RS_Header[12] & 0xFF); + Length = (Length<<8) | (RS232_Arr->RS_Header[11] & 0xFF); + Length = (Length<<8) | (RS232_Arr->RS_Header[10] & 0xFF); + + LengthW = Length/2; + if (LengthW*2RS_Header[14] & 0xFF; + code2=RS232_Arr->RS_Header[15] & 0xFF; + + AdrOut1 = 0; + AdrOut2 = 0; + LengthOut = 0; + + for (i=0;i<1000;i++) + { + DINT; + } + + DRTM; + DINT; + switch ( code1 ) + { + // Xilinx flash + case 1: + x_parallel_bus_project.stop(&x_parallel_bus_project); + load_xilinx_new(0x130000,SIZE_XILINX200); + project.reload_all_plates_with_reset_no_stop_error(); + project.clear_errors_all_plates(); + if (old_started) project_start_parallel_bus(); + + + break; + + /* 6713 Flash + 2812 !!!! + */ + //case 2: select_reset28_for_load67(); break; // + + // Xilinx RAM + case 3: load_xilinx_new(0x80000,SIZE_XILINX200); break; + + //4 5 EEPROM Slave + + case 6: + // for Spartan2 + x_parallel_bus_project.stop(&x_parallel_bus_project); + xflash_remote_eeprom(code2, Address1, Address2, LengthW,&AdrOut1,&AdrOut2,&LengthOut ); + project.reload_all_plates_with_reset_no_stop_error(); + project.clear_errors_all_plates(); + if (old_started) project_start_parallel_bus(); + break; + + case 7: + x_parallel_bus_project.stop(&x_parallel_bus_project); + xread_remote_eeprom(code2, Address1, Address2, LengthW, &AdrOut1,&AdrOut2,&LengthOut ); + project.reload_all_plates_with_reset_no_stop_error(); + project.clear_errors_all_plates(); + if (old_started) project_start_parallel_bus(); + +// xread_remote_eeprom_byte(code2, Address1, Address2, Length, &AdrOut1,&AdrOut2,&LengthOut ); + break; + case 17: + x_parallel_bus_project.stop(&x_parallel_bus_project); + xverify_remote_eeprom(code2, Address1, Address2, LengthW, &AdrOut1,&AdrOut2,&LengthOut ); + project.reload_all_plates_with_reset_no_stop_error(); + project.clear_errors_all_plates(); + if (old_started) project_start_parallel_bus(); +// xread_remote_eeprom_byte(code2, Address1, Address2, Length, &AdrOut1,&AdrOut2,&LengthOut ); + break; + + + case 8: + // reload al plates + x_parallel_bus_project.stop(&x_parallel_bus_project); + project.reload_all_plates_with_reset_no_stop_error(); + project.clear_errors_all_plates(); + if (old_started) project_start_parallel_bus(); + + break; + + + case 9: + go_to_reset = 1; +// SetLoad28_FromResetInternalFlash(); +// SelectReset28(); + + break; + + case 10: + // for Spartan6 + memWrite(code2, Address1, Address2, LengthW,&AdrOut1,&AdrOut2,&LengthOut); + break; + + case 11: + // flash + if(!RS232_Arr->BS_LoadOK) + { + RS_LineToReceive(RS232_Arr->commnumber); // RS485 + RS_SetBitMode(RS232_Arr,9); + return; + } + + return_code = RunFlashData(Address1, Address2, LengthW, &cerr, &repl, &count_ok ); + AdrOut1 = cerr; + AdrOut2 = repl; + LengthOut = return_code+1; + + break; + + case 12: + // Verify flash + if(!RS232_Arr->BS_LoadOK) + { + RS_LineToReceive(RS232_Arr->commnumber); // RS485 + RS_SetBitMode(RS232_Arr,9); + return; + } + + return_code = VerifyFlashData(Address1, Address2, LengthW, &cerr, &repl, &count_ok ); + AdrOut1 = cerr; + AdrOut2 = repl; + LengthOut = return_code+1; + + break; + + case 100: + go_to_set_baud = 1; + set_baud = Address1; +// SetLoad28_FromResetInternalFlash(); +// SelectReset28(); + //speed_baud = Address1; + + + break; + + + + default: break; + } + + EnableInterrupts(); + ERTM; // Enable Global realtime interrupt DBGM + + RS232_Arr->buffer[0] = RS232_Arr->addr_recive; //CNTRL_ADDR; + RS232_Arr->buffer[1] = CMD_RS232_EXTEND; + + RS232_Arr->buffer[2] = BYTE0(AdrOut1); + RS232_Arr->buffer[3] = BYTE1(AdrOut1); + RS232_Arr->buffer[4] = BYTE2(AdrOut1); + RS232_Arr->buffer[5] = BYTE3(AdrOut1); + + RS232_Arr->buffer[6] = BYTE0(AdrOut2); + RS232_Arr->buffer[7] = BYTE1(AdrOut2); + RS232_Arr->buffer[8] = BYTE2(AdrOut2); + RS232_Arr->buffer[9] = BYTE3(AdrOut2); + + RS232_Arr->buffer[10] = BYTE0(LengthOut); + RS232_Arr->buffer[11] = BYTE1(LengthOut); + RS232_Arr->buffer[12] = BYTE2(LengthOut); + RS232_Arr->buffer[13] = BYTE3(LengthOut); + + + crc = 0xffff; + crc = GetCRC16_IBM(crc, RS232_Arr->buffer, 14); + + RS232_Arr->buffer[14] = LOBYTE(crc); + RS232_Arr->buffer[15] = HIBYTE(crc); + RS232_Arr->buffer[16] = 0; + RS232_Arr->buffer[17] = 0; + + RS_Send(RS232_Arr,RS232_Arr->buffer, 18); + + + if (go_to_reset) + { + for (i=0;i<2;i++) + DELAY_US(1000000); + + DRTM; + DINT; + + for (i=0;i<2;i++) + DELAY_US(1000000); + + SetLoad28_FromResetInternalFlash(); + SelectReset28(); + + go_to_reset = 0; + + } + + + if (go_to_set_baud) + { + // for (i=0;i<2;i++) + DELAY_US(1000000); + +// DRTM; +// DINT; + +// for (i=0;i<2;i++) +// DELAY_US(1000000); + + RS_SetLineSpeed(RS232_Arr->commnumber, set_baud); /* */ + + go_to_set_baud = 0; + + } + return; + +} + +void create_uart_vars(char size_cmd15_set, char size_cmd16_set) +{ + + size_cmd15=size_cmd15_set; + size_cmd16=size_cmd16_set; + + rs_a.commnumber=COM_1; + rs_b.commnumber=COM_2; + +} + + + + +////////////////////////////////////////////////////// +/// +////////////////////////////////////////////////////// +int RS_Send(RS_DATA_STRUCT *RS232_Arr,unsigned int *pBuf,unsigned long len) +{ + unsigned int i; + + + if (RS232_Arr->RS_DataWillSend) + { +// RS232_Arr->RS_DataReadyAnswer = 0; + RS232_Arr->RS_DataReadyAnswer = 0; + RS232_Arr->RS_DataSended = 0; + } + + //for (i=0; i <= 30000; i++){} /* PC 30000*/ + + RS_LineToSend(RS232_Arr->commnumber); /* RS485 */ + + //for (i=0; i <= 10000; i++){} /* PC10000 */ + + RS232_Arr->RS_SLength = len; /* */ +// RS232_Arr->pRS_SendPtr = pBuf + 1; + RS232_Arr->pRS_SendPtr = pBuf; + + RS232_Arr->RS_SendBlockMode = BM_CHAR32; + +// RS_Wait4OK(RS232_Arr->commnumber); /* */ + RS_SetBitMode(RS232_Arr,8); /* 8- */ + + RS232_Arr->RS_SendLen = 0; /* */ + +// if(len > 1) +// { + EnableUART_Int_TX(RS232_Arr->commnumber); /* */ + // SCI_Send(RS232_Arr->commnumber, *pBuf); // +// } +// else +// { +// SCI_Send(RS232_Arr->commnumber, *pBuf); // +// RS_Wait4OK(RS232_Arr->commnumber); /* */ +// for (i=0; i <= TIME_WAIT_RS232_BYTE_OUT; i++){} /* PC */ +// RS_SetBitMode(RS232_Arr,9); /* 9- */ +// RS_LineToReceive(RS232_Arr->commnumber); /* RS485 */ +// } + return 0; +} + +void RS232_TuneUp(unsigned long speed_baud_a, unsigned long speed_baud_b) +{ +#if (USE_TEST_TERMINAL) + create_uart_vars(sizeof(CMD_TO_TMS_STRUCT), sizeof(CMD_TO_TMS_TEST_ALL_STRUCT)); +#else + create_uart_vars(100, 100); +#endif + + SetupUART(COM_1, speed_baud_a); + SetupUART(COM_2, speed_baud_b); +} + + +void RS232_WorkingWith(unsigned int enable_rs_a, unsigned int enable_rs_b, unsigned int enable_int_timeout) +{ + + if (enable_int_timeout) + inc_RS_timeout_cicle(); + + if (enable_rs_a) + { + resetup_rs_on_timeout_lost(COM_1); + switch (GetCommand(&rs_a)) + { + case CMD_RS232_INIT: break; + + case CMD_RS232_INITLOAD: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + InitLoad(&rs_a); + break; + + case CMD_RS232_LOAD: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + Load(&rs_a); + break; + + case CMD_RS232_RUN: break; + + case CMD_RS232_PEEK: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + Peek(&rs_a); + //Led1_Toggle(); + break; + +//#if USE_MODBUS_TABLE_SVU +// case CMD_RS232_MODBUS_3: +// if (rs_a.flag_LEADING) +// ReceiveAnswerCommandModbus3(&rs_a); +// else +// ReceiveCommandModbus3(&rs_a); +// break; +// case CMD_RS232_MODBUS_16: +// if (rs_a.flag_LEADING) +// ReceiveAnswerCommandModbus16(&rs_a); +// else +// ReceiveCommandModbus16(&rs_a); +// break; +//#endif + +#if (USE_TEST_TERMINAL) + case CMD_RS232_STD: + rs_a.RS_DataReadyRequest = 1; + flag_special_mode_rs = 0; + ReceiveCommand(&rs_a); + break; + + case CMD_RS232_TEST_ALL: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + ReceiveCommandTestAll(&rs_a); + break; +#endif + case CMD_RS232_POKE: + if (disable_flag_special_mode_rs) + break; + + + flag_special_mode_rs = 1; + Poke(&rs_a); + Led2_Toggle(); + break; + case CMD_RS232_UPLOAD: +// flag_special_mode_rs = 1; + Upload(&rs_a); + break; + case CMD_RS232_TFLASH: + if (disable_flag_special_mode_rs) + break; + + + flag_special_mode_rs = 1; + T_Flash(&rs_a); + break; + case CMD_RS232_EXTEND: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + ExtendBios(&rs_a); + break; + + default: break; + } // end switch + } // end if (enable_rs_a) + + + if (enable_rs_b) + { + resetup_rs_on_timeout_lost(COM_2); + switch (GetCommand(&rs_b)) + { + case CMD_RS232_INIT: break; + + case CMD_RS232_INITLOAD: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + InitLoad(&rs_b); + break; + + case CMD_RS232_LOAD: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + Load(&rs_b); + break; + + case CMD_RS232_RUN: break; + case CMD_RS232_PEEK: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + Peek(&rs_b); + break; + +#if USE_MODBUS_TABLE_SVU + + case CMD_RS232_MODBUS_1: + if (rs_b.flag_LEADING) + { + ModbusRTUreceiveAnswer1(&rs_b); + rs_b.RS_DataReadyAnswerAnalyze = 1; + rs_b.RS_DataReadyRequest = 1; + } + break; + case CMD_RS232_MODBUS_3: + if (rs_b.flag_LEADING) + { + ModbusRTUreceiveAnswer3(&rs_b); + rs_b.RS_DataReadyAnswerAnalyze = 1; + rs_b.RS_DataReadyRequest = 1; + } + else + ModbusRTUreceive3(&rs_b); + + break; + case CMD_RS232_MODBUS_4: + if (rs_b.flag_LEADING) + { + + ModbusRTUreceiveAnswer4(&rs_b); + rs_b.RS_DataReadyAnswerAnalyze = 1; + rs_b.RS_DataReadyRequest = 1; + } + else + ModbusRTUreceive4(&rs_b); + break; + case CMD_RS232_MODBUS_5: + + if (rs_b.flag_LEADING) + { + ModbusRTUreceiveAnswer5(&rs_b); + rs_b.RS_DataReadyAnswerAnalyze = 1; + rs_b.RS_DataReadyRequest = 1; + } + break; + case CMD_RS232_MODBUS_6: + + + + if (rs_b.flag_LEADING) + { + ModbusRTUreceiveAnswer6(&rs_b); + rs_b.RS_DataReadyAnswerAnalyze = 1; + rs_b.RS_DataReadyRequest = 1; + } + break; + + + case CMD_RS232_MODBUS_15: + if (rs_b.flag_LEADING) + { +//#if (USE_CONTROL_STATION==1) +// control_station.count_error_modbus_15[CONTROL_STATION_INGETEAM_PULT_RS485]--; +//#endif + ModbusRTUreceiveAnswer15(&rs_b); + rs_b.RS_DataReadyAnswerAnalyze = 1; + rs_b.RS_DataReadyRequest = 1; + } + else + ModbusRTUreceive15(&rs_b); + + break; + case CMD_RS232_MODBUS_16: + if (rs_b.flag_LEADING) + { +//#if (USE_CONTROL_STATION==1) +// control_station.count_error_modbus_16[CONTROL_STATION_INGETEAM_PULT_RS485]--; +//#endif + ModbusRTUreceiveAnswer16(&rs_b); + rs_b.RS_DataReadyAnswerAnalyze = 1; + rs_b.RS_DataReadyRequest = 1; + } + else + ModbusRTUreceive16(&rs_b); + break; + +#endif + +#if (USE_TEST_TERMINAL) + case CMD_RS232_STD: flag_special_mode_rs = 0; + ReceiveCommand(&rs_b); + break; + case CMD_RS232_TEST_ALL: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + ReceiveCommandTestAll(&rs_b); + break; +#endif + case CMD_RS232_POKE: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + Poke(&rs_b); + break; + case CMD_RS232_UPLOAD: +// flag_special_mode_rs = 1; + + Upload(&rs_b); + break; + case CMD_RS232_TFLASH: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + T_Flash(&rs_b); + break; + case CMD_RS232_EXTEND: + if (disable_flag_special_mode_rs) + break; + + flag_special_mode_rs = 1; + ExtendBios(&rs_b); + break; + + default: break; + } // end switch + } // end if (enable_rs_b) + +} + diff --git a/Inu/Src/N12_Xilinx/RS_Functions.h b/Inu/Src/N12_Xilinx/RS_Functions.h new file mode 100644 index 0000000..df08ebe --- /dev/null +++ b/Inu/Src/N12_Xilinx/RS_Functions.h @@ -0,0 +1,142 @@ +#ifndef _RS_FUNCTIONS_H +#define _RS_FUNCTIONS_H + + +#define MAX_RECEIVE_LENGTH 254 +#define MAX_SEND_LENGTH 400 //266 //254 + +#define CMD_RS232_MODBUS_1 1 +#define CMD_RS232_MODBUS_3 3 +#define CMD_RS232_MODBUS_4 4 +#define CMD_RS232_MODBUS_5 5 +#define CMD_RS232_MODBUS_6 6 +#define CMD_RS232_MODBUS_15 15 +#define CMD_RS232_MODBUS_16 16 + +#define RS_TIME_OUT 6000 +#define RS_TIME_OUT_MPU 6000//6000 // +#define RS_TIME_OUT_HMI 1000 +#define RS_TIME_OUT_MAX 10000 +#define RS_TIME_OUT_LOST 1000 + + + +typedef unsigned char CHAR; + +// Message RS declaration +typedef struct { + unsigned int commnumber; // + unsigned long RS_Length; // + + unsigned int *pRS_RecvPtr; // + unsigned int *pRS_SendPtr; // + unsigned int *pRS_SendPtr_stage1; // + unsigned int *pRS_SendPtr_stage2; // + unsigned int *pRecvPtr; + + unsigned int RS_PrevCmd; // + unsigned int RS_Cmd; // + unsigned int RS_Header[MAX_RECEIVE_LENGTH]; // + + unsigned int flag_TIMEOUT_to_Send; // + unsigned int flag_TIMEOUT_to_Receive; // + unsigned int RS_DataReady; // RS + unsigned int buffer[MAX_SEND_LENGTH]; // RS + unsigned int buffer_stage1[8]; // RS +// unsigned int buffer_stage2[8]; // RS + + unsigned int addr_answer; // + unsigned int addr_recive;// + unsigned int flag_LEADING; // ( ) + unsigned long RS_RecvLen; + unsigned long RS_SLength; // + unsigned long RS_SendLen; // + + unsigned long RS_SLength_stage1; // + unsigned long RS_SLength_stage2; // + + unsigned int time_wait_rs_out; + unsigned int time_wait_rs_out_mpu; + unsigned int time_wait_rs_lost; // - !!! + + + char RS_SendBlockMode; /* */ + char RS_SendBlockMode_stage1; /* */ + char RS_SendBlockMode_stage2; /* */ + char RS_Flag9bit; /* RS485???????? */ + + int BS_LoadOK;/** */ + int RS_FlagBegin; + int RS_HeaderCnt; + int RS_FlagSkiping; + + int RS_DataReadyAnswer; // , , + int RS_DataReadyAnswerAnalyze; // , , + + int RS_DataSended; // , , + int RS_DataWillSend; // , + + int RS_DataReadyRequest; // , , + int RS_DataReadyFullUpdate; // , + + int RS_OnTransmitedData ; // + int current_tx_stage; + int cmd_tx_stage; + + unsigned int count_recive_ok; // crc, + unsigned int count_recive_error_crc; // crc + unsigned int count_recive_dirty; // crc, + unsigned int count_recive_bad; // c + unsigned int count_recive_bytes_all; // + unsigned int count_recive_bytes_skipped; // + unsigned int count_recive_cmd_skipped; // + unsigned int count_recive_rxerror; // + + unsigned int do_resetup_rs; // . + + int RS_DataWillSend2; // 2, + + + + + } RS_DATA_STRUCT; + +#define RS_DATA_STRUCT_DEFAULT {0,0,0,0,0,0,0,0,0,{0}, 0,0,0,{0},{0}, 0,0,0,0,0,0, 0,0, 0,0, 0,0,0,0, 0,0, 0,0,0, 0, 0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0} +////////////////////////////////////////////////////////// + +#define TMS_TO_TERMINAL_TEST_ALL_STRUCT_DEFAULT {{0}, {0}, {0}, 0, 0, 0} + +enum { + CMD_RS232_LOAD = 51, CMD_RS232_UPLOAD, CMD_RS232_RUN, CMD_RS232_XFLASH, CMD_RS232_TFLASH, + CMD_RS232_PEEK, CMD_RS232_POKE, CMD_RS232_INITLOAD, CMD_RS232_INIT,CMD_RS232_EXTEND, + CMD_RS232_VECTOR = 61, CMD_RS232_IMPULSE, CMD_RS232_STD = 65, CMD_RS232_TEST_ALL, CMD_RS232_STD_ANS, + CMD_RS232_LAST + }; + +enum { + false = 0, true + }; + +#define RS_LEN_CMD CMD_RS232_LAST + +//extern RS_DATA_STRUCT RS232_A, RS232_B; +extern RS_DATA_STRUCT rs_a,rs_b; + +int RS_Send(RS_DATA_STRUCT *rs_arr,unsigned int *pBuf,unsigned long len); +void RS232_WorkingWith(unsigned int enable_rs_a, unsigned int enable_rs_b, unsigned int enable_int_timeout); +void RS232_TuneUp(unsigned long speed_baud_a, unsigned long speed_baud_b); +void inc_RS_timeout_cicle(void); +void resetup_rs_on_timeout_lost(int rsp); + +void resetup_rs(RS_DATA_STRUCT *rs_arr); +void resetup_mpu_rs(RS_DATA_STRUCT *rs_arr); +int test_rs_live(RS_DATA_STRUCT *rs_arr); +void RS_SetControllerLeading(RS_DATA_STRUCT *RS232_Arr,int bool); +void RS_SetAdrAnswerController(RS_DATA_STRUCT *RS232_Arr,int set_addr_answer); +void SetCntrlAddr (int cntrl_addr,int cntrl_addr_for_all); + +extern float KmodTerm, freqTerm; +extern unsigned int RS_Len[RS_LEN_CMD]; +extern int flag_special_mode_rs, disable_flag_special_mode_rs; + +#endif diff --git a/Inu/Src/N12_Xilinx/RS_modbus_svu.c b/Inu/Src/N12_Xilinx/RS_modbus_svu.c new file mode 100644 index 0000000..c254171 --- /dev/null +++ b/Inu/Src/N12_Xilinx/RS_modbus_svu.c @@ -0,0 +1,328 @@ +#include "RS_modbus_svu.h" + +#include +#include + +#include "modbus_table_v2.h" +#include "options_table.h" +#include "DSP281x_Device.h" +#include "CRC_Functions.h" +#include "MemoryFunctions.h" +#include "RS_Functions.h" + + +int err_modbus3 = 1; +int err_modbus16 = 1; +int cmd_3_or_16 = 0; +int err_send_log_16 = 0; //Switch between command 3 and 16 +unsigned int flag_send_answer_rs = 0; //This flag enables fast answer to SVU when values changed + + +unsigned int adr_read_from_modbus3 = 0; +unsigned int flag_received_first_mess_from_MPU = 0; + + + + +void ReceiveCommandModbus3(RS_DATA_STRUCT *RS232_Arr) +{ + // y + unsigned int crc, Address_MB, Length_MB, i/*, Data*/; +// int buf_out[200]; + +/* y. */ + Address_MB =(RS232_Arr->RS_Header[2] << 8) | RS232_Arr->RS_Header[3]; + +/* */ + Length_MB = (RS232_Arr->RS_Header[4] << 8 ) | RS232_Arr->RS_Header[5]; + + ///////////////////////////////////////////////// + // + /* */ + +// f.RScount = SECOND*3; + + RS232_Arr->buffer[0] = RS232_Arr->addr_recive; //CNTRL_ADDR; + RS232_Arr->buffer[1] = CMD_RS232_MODBUS_3; + RS232_Arr->buffer[2] = Length_MB*2; + + for (i=0;i=ADR_MODBUS_TABLE && Address_MB<0xe00) + { + RS232_Arr->buffer[3+i*2 ]=modbus_table_rs_out[Address_MB-ADR_MODBUS_TABLE+i].byte.HB; + RS232_Arr->buffer[3+i*2+1]=modbus_table_rs_out[Address_MB-ADR_MODBUS_TABLE+i].byte.LB; + } + + if (Address_MB>=0xe00 && Address_MB<0xf00) + { + RS232_Arr->buffer[3+i*2 ]=options_controller[Address_MB-0xe00+i].byte.HB; + RS232_Arr->buffer[3+i*2+1]=options_controller[Address_MB-0xe00+i].byte.LB; + } + + } + + crc = 0xffff; + crc = GetCRC16_IBM(crc, RS232_Arr->buffer, Length_MB*2+3); + + RS232_Arr->buffer[Length_MB*2+3] = LOBYTE(crc); + RS232_Arr->buffer[Length_MB*2+4] = HIBYTE(crc); + + RS232_Arr->buffer[Length_MB*2+5] = 0; + RS232_Arr->buffer[Length_MB*2+6] = 0; + RS_Send(RS232_Arr,RS232_Arr->buffer, Length_MB*2+7); + + return; +} + +/***************************************************************/ +/***************************************************************/ +/* ModBus - 3 + */ +/***************************************************************/ +/***************************************************************/ +void SendCommandModbus3(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start,unsigned int count_word) +{ + // + unsigned int crc; //, Address_MB, Length_MB, i, Data; +// int buf_out[200]; +// int buf_in[200]; + +// rs_arr->buffer[0]= + rs_arr->buffer[0] = LOBYTE(adr_contr); + rs_arr->buffer[1] = CMD_RS232_MODBUS_3; + rs_arr->buffer[2] = HIBYTE(adr_start); + rs_arr->buffer[3] = LOBYTE(adr_start); + rs_arr->buffer[4] = 0; + rs_arr->buffer[5] = LOBYTE(count_word); + + crc = 0xffff; + crc = GetCRC16_IBM( crc, rs_arr->buffer, 6); +// crc = get_crc_ccitt( crc, rs_arr->buffer, 6); + + + rs_arr->buffer[6] = LOBYTE(crc); + rs_arr->buffer[7] = HIBYTE(crc); + + rs_arr->buffer[8] = 0; + rs_arr->buffer[9] = 0; + + RS_Send(rs_arr,rs_arr->buffer, 11); + + /* */ + if (adr_contr>0 && adr_contr<0xff) + { + + RS_Len[CMD_RS232_MODBUS_3]=5+count_word*2; + + adr_read_from_modbus3=adr_start; + RS_SetControllerLeading(rs_arr,true); + RS_SetAdrAnswerController(rs_arr,adr_contr); + + } + + + return; +} + + +void ReceiveCommandModbus16(RS_DATA_STRUCT *RS232_Arr) +{ + // y + unsigned int crc, Address_MB, Length_MB, Bytecnt_MB, i/*, Data1,Data2,Quantity*/; + int /*Data,*/i1,i2; + +/* y. */ + Address_MB = RS232_Arr->RS_Header[3] | ( RS232_Arr->RS_Header[2] << 8); + +/* quantity. */ + //Quantity = RS232_Arr->RS_Header[5] | ( RS232_Arr->RS_Header[4] << 8); + +/* */ +// Length_MB = (RS232_Arr->RS_Header[4] << 8 ) | RS232_Arr->RS_Header[5]; + + Bytecnt_MB = RS232_Arr->RS_Header[6]; + + Length_MB = Bytecnt_MB>>1; + + + for (i=0;i=ADR_MODBUS_TABLE && Address_MB<0xe00) + { + RS232_Arr->buffer[3+i*2 ]=modbus_table_rs_out[Address_MB-ADR_MODBUS_TABLE+i].byte.HB; + RS232_Arr->buffer[3+i*2+1]=modbus_table_rs_out[Address_MB-ADR_MODBUS_TABLE+i].byte.LB; + } + + if (Address_MB>=0xe00 && Address_MB<0xf00) + { + options_controller[Address_MB-0xe00+i].byte.HB=RS232_Arr->RS_Header[7+i*2 ]; + options_controller[Address_MB-0xe00+i].byte.LB=RS232_Arr->RS_Header[7+i*2+1]; + } + + } + + + if (Address_MB>=0xe00 && Address_MB<0xf00) + { + i1 = options_controller[0].all; + i2 = options_controller[1].all; + store_data_flash(options_controller,sizeof(options_controller)); + SetCntrlAddr(i1, i2); /* */ + } + + + ///////////////////////////////////////////////// + // + // + + RS232_Arr->buffer[0] = RS232_Arr->addr_recive; + RS232_Arr->buffer[1] = CMD_RS232_MODBUS_16; + RS232_Arr->buffer[2] = HIBYTE(Address_MB); + RS232_Arr->buffer[3] = LOBYTE(Address_MB); + RS232_Arr->buffer[4] = 0; + RS232_Arr->buffer[5] = 2; + + crc = 0xffff; + crc = GetCRC16_IBM( crc, RS232_Arr->buffer, 6); + + RS232_Arr->buffer[6] = LOBYTE(crc); + RS232_Arr->buffer[7] = HIBYTE(crc); + + RS232_Arr->buffer[8] = 0; + RS232_Arr->buffer[9] = 0; + RS_Send(RS232_Arr,RS232_Arr->buffer, 10); + + return; + + +} +/***************************************************************/ +/***************************************************************/ +/***************************************************************/ +/* ModBus - 16 + */ +/***************************************************************/ +/***************************************************************/ +/***************************************************************/ + +void SendCommandModbus16(RS_DATA_STRUCT *rs_arr,int adr_contr, unsigned int adr_start,unsigned int count_word) +{ + + // + unsigned int crc, Address_MB, i; //, Length_MB; //, Bytecnt_MB, Data1,Data2; +// int Data, digital, ust_I, ust_Time; + + //Length_MB = count_word; + Address_MB = adr_start; + + + // + // + + rs_arr->buffer[0] = adr_contr; + rs_arr->buffer[1] = CMD_RS232_MODBUS_16; + + rs_arr->buffer[2] = HIBYTE(adr_start); + rs_arr->buffer[3] = LOBYTE(adr_start); + + rs_arr->buffer[4] = HIBYTE(count_word); + rs_arr->buffer[5] = LOBYTE(count_word); + + rs_arr->buffer[6] = LOBYTE(count_word*2); + + + + for (i=0;ibuffer[7+i*2 ]=modbus_table_rs_out[Address_MB-ADR_MODBUS_TABLE+i].byte.HB; + rs_arr->buffer[7+i*2+1]=modbus_table_rs_out[Address_MB-ADR_MODBUS_TABLE+i].byte.LB;//LOBYTE(buffer_out_data[Address_MB+i]); + } + + crc = 0xffff; +// crc = get_crc_ccitt(crc, rs_arr->buffer, Length_MB*2+7); + crc = GetCRC16_IBM(crc, rs_arr->buffer, (unsigned long)(count_word*2+7)); + + rs_arr->buffer[count_word*2+7] = LOBYTE(crc); + rs_arr->buffer[count_word*2+8] = HIBYTE(crc); + + rs_arr->buffer[count_word*2+9] = 0; + rs_arr->buffer[count_word*2+10] = 0; + + RS_Send(rs_arr,rs_arr->buffer,( count_word*2+10+2)); + + + // + if (adr_contr>0 && adr_contr<0xff) + { + RS_Len[CMD_RS232_MODBUS_16]=8; + RS_SetControllerLeading(rs_arr,true); + RS_SetAdrAnswerController(rs_arr,adr_contr); + } + +} + + +void ReceiveAnswerCommandModbus3(RS_DATA_STRUCT *RS232_Arr) +{ + unsigned int Address_MB, Length_MB, i; + MODBUS_REG_STRUCT elementData; + +/* . */ + Address_MB = adr_read_from_modbus3; + +/* */ + Length_MB = RS232_Arr->RS_Header[2] >> 1; + + ///////////////////////////////////////////////// + // + /* */ + + for (i=0;iRS_Header[3+i*2]; + elementData.byte.LB = RS232_Arr->RS_Header[3+i*2+1]; + if (elementData.all != modbus_table_rs_in[Address_MB-ADR_MODBUS_TABLE+i].all) { + flag_send_answer_rs = 1; + } + modbus_table_rs_in[Address_MB-ADR_MODBUS_TABLE+i].all = elementData.all; + // modbus_table_rs_in[Address_MB-ADR_MODBUS_TABLE+i].byte.HB=RS232_Arr->RS_Header[3+i*2]; + // modbus_table_rs_in[Address_MB-ADR_MODBUS_TABLE+i].byte.LB=RS232_Arr->RS_Header[3+i*2+1]; + //Commented, because of out table can be rewrited before new value had been sent to SVO + modbus_table_rs_out[Address_MB-ADR_MODBUS_TABLE+i].all = modbus_table_rs_in[Address_MB-ADR_MODBUS_TABLE+i].all; + } + + + RS_SetControllerLeading(RS232_Arr,false); + RS_SetAdrAnswerController(RS232_Arr, 0); + err_modbus3=0; + cmd_3_or_16=1; + flag_received_first_mess_from_MPU=1; + return; +} + +void ReceiveAnswerCommandModbus16(RS_DATA_STRUCT *RS232_Arr) +{ + // + //unsigned int crc, Address_MB, Length_MB, Bytecnt_MB/*, i, Data1,Data2*/; + //int Data, digital, ust_I, ust_Time; + +/* . */ + //Address_MB = RS232_Arr->RS_Header[3] | ( RS232_Arr->RS_Header[2] << 8); + +/* */ + //Length_MB = (RS232_Arr->RS_Header[4] << 8 ) | RS232_Arr->RS_Header[5]; + + //Bytecnt_MB = RS232_Arr->RS_Header[6]; + + RS_SetAdrAnswerController(RS232_Arr,0); + RS_SetControllerLeading(RS232_Arr,false); + err_modbus16 = 0; + cmd_3_or_16 = 0; + flag_received_first_mess_from_MPU=1; + return; +} + + + + diff --git a/Inu/Src/N12_Xilinx/RS_modbus_svu.h b/Inu/Src/N12_Xilinx/RS_modbus_svu.h new file mode 100644 index 0000000..a6a3d88 --- /dev/null +++ b/Inu/Src/N12_Xilinx/RS_modbus_svu.h @@ -0,0 +1,27 @@ +#ifndef _RS_MODBUS_SVU_H +#define _RS_MODBUS_SVU_H + +#include "RS_Functions.h" + +void ReceiveCommandModbus3(RS_DATA_STRUCT *RS232_Arr); +void ReceiveCommandModbus16(RS_DATA_STRUCT *RS232_Arr); +void SendCommandModbus3(RS_DATA_STRUCT *rs_arr, int adr_contr, unsigned int adr_start,unsigned int count_word); +void SendCommandModbus16(RS_DATA_STRUCT *rs_arr,int adr_contr, unsigned int adr_start,unsigned int count_word); +void ReceiveAnswerCommandModbus3(RS_DATA_STRUCT *RS232_Arr); +void ReceiveAnswerCommandModbus16(RS_DATA_STRUCT *RS232_Arr); + + +extern int err_modbus3; +extern int err_modbus16; +extern int cmd_3_or_16; +extern int err_send_log_16; +extern unsigned int flag_received_first_mess_from_MPU; + +extern unsigned int flag_send_answer_rs; + +extern unsigned int adr_read_from_modbus3; + + + +#endif + diff --git a/Inu/Src/N12_Xilinx/Spartan2E_Adr.h b/Inu/Src/N12_Xilinx/Spartan2E_Adr.h new file mode 100644 index 0000000..e8c5b2b --- /dev/null +++ b/Inu/Src/N12_Xilinx/Spartan2E_Adr.h @@ -0,0 +1,90 @@ +#ifndef _SPARTAN2E_ADR_H +#define _SPARTAN2E_ADR_H + +// EEPROM +#define ADR_CONTR_REG_FOR_WRITE 0x2020 +#define ADR_CONTR_REG_FOR_READ 0x2028 + +//serial bus +#define ADR_SERIAL_BUS_DATA_WRITE 0x200A +#define ADR_SERIAL_BUS_CMD 0x200B + +#define ADR_SERIAL_BUS_DATA_READ 0x200F + +//Er workith +#define ADR_BUS_ERROR_READ 0x2012 +#define ADR_ERRORS_TOTAL_INFO 0x2026 + + +//parallel bus +#define ADR_PARALLEL_BUS_CMD 0x200C +#define ADR_PARALLEL_BUS_ADR_TABLE 0x200D +#define ADR_PARALLEL_BUS_SET_TABLE 0x200E + +//async bus +#define ADR_ASYNC_BUS_TABLE 0x2029 + + +//build, test +#define ADR_CONTROLLER_BUILD 0x2014 +#define ADR_XTEST_REG 0x2013 + + +// adr free block in memory TMS +#define ADR_FIRST_FREE 0x2040 +#define ADR_LAST_FREE 0x207F + + +//hwp +#define ADR_HWP_SERVICE_0 0x2009 +#define ADR_HWP_SERVICE_1 0x2008 +#define ADR_HWP_DATA_RECEVED_0 0x2010 +#define ADR_HWP_DATA_RECEVED_1 0x2011 +#define ADR_HWP_TEST_TIMER 0x2027 + +//sensor rotor +#define ADR_SENSOR_S1_T_PERIOD 0x2015 +#define ADR_SENSOR_S1_COUNT_IMPULS 0x2016 + +#define ADR_SENSOR_S2_T_PERIOD 0x2017 +#define ADR_SENSOR_S2_COUNT_IMPULS 0x2018 + +#define ADR_SENSOR_CMD 0x2019 + +#define ADR_SENSOR_S1_T_PERIOD_LOW_ONE_IMPULS 0x2021 +#define ADR_SENSOR_S1_T_PERIOD_HIGH_ONE_IMPULS 0x2022 +#define ADR_SENSOR_S2_T_PERIOD_LOW_ONE_IMPULS 0x2023 +#define ADR_SENSOR_S2_T_PERIOD_HIGH_ONE_IMPULS 0x2024 + +//pwm + +#define ADR_PWM_WDOG 0x2025 + +#define ADR_PWM_DIRECT 0x2000 +#define ADR_PWM_DIRECT2 0x2030 +#define ADR_PWM_DRIVE_MODE 0x2001 +#define ADR_PWM_DEAD_TIME 0x2002 +#define ADR_PWM_KEY_NUMBER 0x2003 +#define ADR_PWM_PERIOD 0x2004 +#define ADR_PWM_SAW_DIRECT 0x2005 +#define ADR_PWM_START_STOP 0x2006 +#define ADR_PWM_TIMING 0x2007 + +#define ADR_SAW_REQUEST 0x2031 +#define ADR_SAW_VALUE 0x2032 +#define ADR_TK_MASK_0 0x2033 +#define ADR_TK_MASK_1 0x2034 +#define ADR_PWM_IT_TYPE 0x2035 + + + +//optical bus +#define SI_OPTICS_WORD_TO_SEND_1 0x2036 +#define SI_OPTICS_WORD_TO_SEND_2 0x2037 +#define SI_OPTICS_WORD_TO_SEND_3 0x2038 +#define SI_OPTICS_WORD_TO_SEND_4 0x2039 + + + +#endif + diff --git a/Inu/Src/N12_Xilinx/Spartan2E_Functions.c b/Inu/Src/N12_Xilinx/Spartan2E_Functions.c new file mode 100644 index 0000000..9da7fa4 --- /dev/null +++ b/Inu/Src/N12_Xilinx/Spartan2E_Functions.c @@ -0,0 +1,896 @@ +#include + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +//#include "xerror.h" + +//#include "SpaceVectorPWM.h" +//#include "v_pwm24_v2.h" +//#include "PWMTools.h" + + + +#define SelectLoadXilinx() WriteOper(0,0,0,1) + +//#define TypeAccess_Is_SerialBus 21 + +#define dat_xilinx_line_do(bitb) \ + GpioDataRegs.GPEDAT.bit.GPIOE0=bitb + +#define setup_xilinx_line_do_on() \ + GpioMuxRegs.GPEDIR.bit.GPIOE0=1;\ + GpioDataRegs.GPEDAT.bit.GPIOE0=1 + +#define reset_xilinx() WriteOper(1,1,0,1) + +#define XSEEPROM_WRITE_REPEAT 3 +#define XSEEPROM_READ_REPEAT 3 +#define XSEEPROM_MAX_ERROR_CONSECUTIVE_FRAME 20 // threshold +#define XSEEPROM_MIN_LENTH 7 // max 7 => 1 word = 2 byte + +#define XSEEPROM_MAX_ERROR_CONSECUTIVE_BREAK (XSEEPROM_MAX_ERROR_CONSECUTIVE_FRAME + 10) + +#define xseeprom_pause { } + +#pragma DATA_SECTION(xeeprom_controll_fast,".fast_vars"); +unsigned int xeeprom_controll_fast; + +//XSerial_bus XSerial_bus0; +//Xmemory_uni Xmemory_uni0; + +//XSerial_bus_stats XSerial_bus_stats0; + +#pragma DATA_SECTION(Controll, ".fast_vars"); +XControll_reg Controll; + +unsigned int xeeprom_controll_store; + +void write_bit_xilinx(unsigned char bitb); +int xseeprom_read_all(unsigned int Mode_is_Verify, XSeeprom_t * Ptr); +int xseeprom_write_all(XSeeprom_t * Ptr); +void xseeprom_adr(unsigned int adr); +//unsigned int xseeprom_case_xilinx (void); +void xseeprom_delay(void); +void xseeprom_init(void); +void xControll_wr(); +unsigned int xseeprom_read_byte(unsigned int use_ack); +void xseeprom_set_mode_ON (unsigned int set_mode); +void xseeprom_start(void); +void xseeprom_stop(void); +void xseeprom_undo (void); +unsigned int xseeprom_write_byte(unsigned int byte); +void xseeprom_clk (unsigned int clk); +unsigned int xseeprom_din (void); +void xseeprom_dout (unsigned int data); +void xseeprom_mode_wr (unsigned int mode); +void ResetPeriphPlane(); + + +unsigned int time = 0; + +void write_byte_xilinx(unsigned char bx) +{ + int i; + + for (i=0;i<=7;i++) + write_bit_xilinx( (bx >> i) & 1); + +} + +void write_bit_xilinx(unsigned char bitb) +{ + pause_1000(1); + EALLOW; + + GpioDataRegs.GPBDAT.bit.GPIOB8=1; + dat_xilinx_line_do(bitb); + + pause_1000(1); + GpioDataRegs.GPBDAT.bit.GPIOB8=0; + + pause_1000(1); + GpioDataRegs.GPBDAT.bit.GPIOB8=1; + EDIS; +} + +void setup_xilinx_line() +{ + EALLOW; + GpioMuxRegs.GPBMUX.bit.CAP4Q1_GPIOB8=0; + GpioMuxRegs.GPAMUX.bit.CAP2Q2_GPIOA9=0; + + + GpioMuxRegs.GPBDIR.bit.GPIOB8=1; + GpioMuxRegs.GPADIR.bit.GPIOA9=0; + GpioDataRegs.GPBDAT.bit.GPIOB8=1; + + // init line + GpioMuxRegs.GPEMUX.bit.XNMI_XINT13_GPIOE2=0; // as io + GpioMuxRegs.GPEDIR.bit.GPIOE2 = 0; // as input + + setup_xilinx_line_do_on(); + + EDIS; +} + +unsigned int read_init_xilinx() +{ + unsigned int i; + EALLOW; + i=GpioDataRegs.GPEDAT.bit.GPIOE2; + EDIS; + return (i); +} + +unsigned int read_done_xilinx() +{ +unsigned int i; + EALLOW; + i=GpioDataRegs.GPADAT.bit.GPIOA9; + EDIS; + return (i); +} + +long xverify_remote_eeprom(unsigned int adr_device, unsigned long adr, + unsigned long adr_eeprom, unsigned long size, unsigned long *ok_write, + unsigned long *write_error, unsigned long *repeat_error ) +{ + int i; + static XSeeprom_t rom; + unsigned long repeat_er=0; + unsigned int er_wr=0; + unsigned int er_rd=0; + + rom.Adr_device=adr_device; + rom.Adr=adr; + rom.Adr_seeprom=adr_eeprom; + rom.size=size; + + if (er_wr) + return 0; + + for (i=0; i>8) & 0xff); + write_byte_xilinx( wx & 0xff); + } + + +// slow part of loading + adr_x=adr_int; + wx=i_ReadMemory(adr_x+adr); + write_byte_xilinx( (wx>>8) & 0xff); + pause_1000(10000); + write_byte_xilinx( wx & 0xff); + pause_1000(10000); + adr_int++; + +// final part of loading + for (adr_x=adr_int;adr_x<(size+1);adr_x++) + { + unsigned int bx; + int i; + + done_line=read_done_xilinx(); + if(done_line==1) + break; + + wx=i_ReadMemory(adr_x+adr); + bx=(wx>>8) & 0xff; + for (i=0;i<=7;i++) + { + write_bit_xilinx( (bx >> i) & 1); + done_line=read_done_xilinx(); + if(done_line==1) + break; + } + if(done_line==1) + break; + + wx=i_ReadMemory(adr_x+adr); + bx= wx & 0xff; + for (i=0;i<=7;i++) + { + write_bit_xilinx( (bx >> i) & 1); + done_line=read_done_xilinx(); + if(done_line==1) + break; + } + if(done_line==1) + break; + } +// configure line DO as input +// EALLOW; +// setup_xilinx_line_do_off(); +// EDIS; + + +// activation part of loading +// restore peripheral frequency +// xfrequency_peripheral_is_slow(Clk_mode_store); + + + // DONE activate on clock 2 + + write_bit_xilinx(1); // clock 3, activate GWE + + write_bit_xilinx(1); // clock 4, activate GSR + + write_bit_xilinx(1); // clock 5, activate GTS. Led is work. + + write_bit_xilinx(1); // clock 6, activate DLL + + write_bit_xilinx(0); // clock 7 + + write_bit_xilinx(1); + pause_1000(100); + + write_bit_xilinx(0); + pause_1000(100); + +// controll line DONE + Value=read_done_xilinx(); // there must be level '1' + if(Value != 1) + return xerror(xtools_er_ID(2),(void *)0); + +// pause for DLL in Xilinx + pause_1000(10000); + + return 0; +} + + + +int xseeprom_write_all(XSeeprom_t * Ptr) +{ + + union XSeeprom_command_reg command; + unsigned int data; + unsigned int i; + unsigned int er=0; + unsigned long er_ack=0; + unsigned int er_for_one_pack=0; + unsigned int er_consecutive=0; + unsigned long adr_x=Ptr->Adr; + unsigned long adr_eeprom=Ptr->Adr_seeprom; + unsigned int count_word=128; + unsigned int wx; + + command.bit.bit7=1; + command.bit.bit6=0; + command.bit.bit5=1; + command.bit.bit4=0; + command.bit.bit3=0; + command.bit.A1=1; + command.bit.WR0=0; + + Ptr->ok_write=0; + Ptr->repeat_error=0; + Ptr->write_error=0; + + xseeprom_init(); + pause_1000(100); + xseeprom_adr(Ptr->Adr_device); + // xseeprom_set_mode_ON(1); + + xeeprom_controll_fast=Controll.all; + + pause_1000(100); + + while ((adr_x-Ptr->Adr)<(Ptr->size)) { // while size + er=0; + for(;;){ + Led2_Toggle(); + xseeprom_start(); + command.bit.P0=(adr_eeprom>>15 & 0x0001); + er=xseeprom_write_byte(command.all); + if(er) + break; + + data=adr_eeprom>>7 & 0x00ff; + er=xseeprom_write_byte(data); + if(er) + break; + + data=adr_eeprom<<1 & 0x00ff; + er=xseeprom_write_byte(data); + break; + } + + i=0; + while ( (iAdr)<(Ptr->size)) && ((adr_eeprom<<1 & 0x00ff)+2*i < 0x00ff) ) { + wx=i_ReadMemory(adr_x+i); + er=xseeprom_write_byte(wx>>8); + if(er) + break; + er=xseeprom_write_byte(wx); + if(er) + break; + i+=1; + } + + xseeprom_stop(); + xseeprom_delay(); + + if (er == 0) { + adr_x+=i; + adr_eeprom+=i; + Ptr->ok_write+=i; + er_consecutive=0; + } else { + er_consecutive++; + er_ack++; + if (er_consecutive > XSEEPROM_MAX_ERROR_CONSECUTIVE_FRAME) { + if (er_for_one_pack < XSEEPROM_MIN_LENTH) { + er_for_one_pack +=1; + er_consecutive=0; + } + } + Led1_Toggle(); + } + + switch (er_for_one_pack) { + case 0 : count_word = 128; break; + case 1 : count_word = 64; break; + case 2 : count_word = 32; break; + case 3 : count_word = 16; break; + case 4 : count_word = 8; break; + case 5 : count_word = 4; break; + case 6 : count_word = 2; break; + case 7 : count_word = 1; break; + default : break; + } + + Ptr->repeat_error=er_ack; + if(er_consecutive > XSEEPROM_MAX_ERROR_CONSECUTIVE_BREAK) { + xseeprom_undo(); + return(4); + } + } // while size + xseeprom_undo(); + return 0; +} + +int xseeprom_read_all(unsigned int Mode_is_Verify, XSeeprom_t * Ptr) +{ + union XSeeprom_command_reg command; + unsigned int data; +// unsigned int i; + + unsigned long i; + + unsigned int er; + unsigned long er_ack=0; + unsigned int er_consecutive=0; + unsigned long adr_x=Ptr->Adr; + unsigned long adr_eeprom=Ptr->Adr_seeprom; + unsigned int count_word=128; + unsigned int data_rd; + unsigned int wx; + + command.bit.bit7=1; + command.bit.bit6=0; + command.bit.bit5=1; + command.bit.bit4=0; + command.bit.bit3=0; + command.bit.A1=1; + + Ptr->ok_write=0; + Ptr->repeat_error=0; + Ptr->write_error=0; + + xseeprom_init(); + xseeprom_adr(Ptr->Adr_device); + // xseeprom_set_mode_ON(1); + + xeeprom_controll_fast=Controll.all; + + + pause_1000(100); + + while ((adr_x-Ptr->Adr)<(Ptr->size)) { // while size + er=0; + for(;;){ + Led2_Toggle(); + xseeprom_start(); + command.bit.P0=(adr_eeprom>>15 & 0x0001); + command.bit.WR0=0; + er=xseeprom_write_byte(command.all); + if(er) + break; + + data=adr_eeprom>>7 & 0x00ff; + er=xseeprom_write_byte(data); + if(er) + break; + + data=adr_eeprom<<1 & 0x00ff; + er=xseeprom_write_byte(data); + if(er) + break; + + xseeprom_start(); + command.bit.WR0=1; + er=xseeprom_write_byte(command.all); + break; + } + + i=0; + while ( (iAdr)<(Ptr->size)) && (( adr_eeprom<<1 & 0x00ff)+2*i < 0x00ff) ) { + data_rd=xseeprom_read_byte(1); + data_rd<<=8; + if( ((i+1)!=count_word) && ((adr_x-Ptr->Adr)<(Ptr->size-1)) && ((adr_eeprom<<1 & 0x00ff)+2*i+1 < 0x00ff) ) + data_rd|=xseeprom_read_byte(1); // use ack + else + data_rd|=xseeprom_read_byte(0); // don't use ack + if(Mode_is_Verify==0) + { + i_WriteMemory((adr_x),data_rd); + } + else { + wx=i_ReadMemory(adr_x); + if(wx!=data_rd) + Ptr->write_error++; + } + i++; + adr_x++; + } + + xseeprom_stop(); +// xseeprom_delay(); + + if (er == 0) { + adr_eeprom+=i; + Ptr->ok_write+=i; + er_consecutive=0; + } else { + er_consecutive++; + er_ack++; + Led1_Toggle(); + } + + Ptr->repeat_error=er_ack; + if(er_consecutive > XSEEPROM_MAX_ERROR_CONSECUTIVE_BREAK) { + xseeprom_undo(); + return(4); + } + } // while size + ResetPeriphPlane(); + xseeprom_undo(); + return 0; +} + +void xseeprom_adr(unsigned int adr) +{ + Controll.bit.line_P7_4_Sorce_Is_Tms=1; + Controll.bit.line_P7_4_Is=adr; + xControll_wr(); +} + +void xseeprom_delay(void) +{ + pause_1000(10000); +} + +void ResetNPeriphPlane(unsigned int np) +{ + + Controll.bit.line_P7_4_Is = np; + + Controll.bit.OE_BUF_Is_ON = 1; + Controll.bit.line_Z_ER0_OUT_Is = 0; + Controll.bit.line_SET_MODE_Is = 1; + xControll_wr(); + pause_1000(10000); + + + + Controll.bit.line_P7_4_Is = 0x0; + Controll.bit.line_Z_ER0_OUT_Is = 1; + xControll_wr(); + + + +// Controll.bit.RemotePlane_Is_Reset = 1; + xControll_wr(); + pause_1000(10000); +// Controll.bit.RemotePlane_Is_Reset = 0; + Controll.bit.line_P7_4_Is = 0x0; +} + +void ResetPeriphPlane() +{ + Controll.bit.line_P7_4_Is = 0xf; +// Controll.bit.RemotePlane_Is_Reset = 1; + xControll_wr(); + pause_1000(10000); +// Controll.bit.RemotePlane_Is_Reset = 0; + Controll.bit.line_P7_4_Is = 0x0; + xControll_wr(); +} + +void xseeprom_init(void) +{ + xeeprom_controll_store=Controll.all; + Controll.bit.line_CLKS_Sorce_Is_Tms=1; + Controll.bit.line_CLKS_Is=1; + Controll.bit.line_ER0_OUT_Sorce_Is_Tms=1; + Controll.bit.line_ER0_OUT_Is=1; + Controll.bit.line_P7_4_Sorce_Is_Tms=1; + Controll.bit.line_P7_4_Is=0xf; + Controll.bit.line_Z_ER0_OUT_Is=0; // read + Controll.bit.line_SET_MODE_Is=0; // off + // + Controll.bit.OE_BUF_Is_ON=0;//1; + // + Controll.bit.RemotePlane_Is_Reset=0; + xControll_wr(); +} + +void xControll_wr() +{ + i_WriteMemory(ADR_CONTR_REG_FOR_WRITE, Controll.all); +} +/* +unsigned int xseeprom_case_xilinx (void) { + xinput_new_uni_rd_status(&Xinput_new_uni_tms0); + return Xinput_new_uni_tms0.ChanalsPtr.ChanalPtr[XINPUT_NEW_TMS0_NUMBER_LINE_CASE_XILINX].rd_status; +} +*/ +unsigned int xseeprom_read_byte(unsigned int use_ack){ + int i; + unsigned int data=0; + + xseeprom_dout(1); + xseeprom_mode_wr(0); + for (i=7;i>=0;i--) + { + xseeprom_pause + xseeprom_clk(1); + xseeprom_pause + data=data<<1|(xseeprom_din() & 0x0001); + xseeprom_clk(0); + xseeprom_pause + } + + pause_1000(10); + + xseeprom_mode_wr(1); + xseeprom_dout(!use_ack); // ack + xseeprom_pause + xseeprom_clk(1); + xseeprom_pause + xseeprom_clk(0); + xseeprom_pause + xseeprom_dout(1); + xseeprom_mode_wr(0); + + + pause_1000(10); + return data; +} + +void xseeprom_set_mode_ON (unsigned int set_mode) { + Controll.bit.line_SET_MODE_Is=~set_mode; + xControll_wr(); +} + +void xseeprom_start(void) { + xseeprom_clk(1); + xseeprom_dout(1); + xseeprom_mode_wr(1); + xseeprom_pause + xseeprom_dout(0); // start + xseeprom_pause + xseeprom_clk(0); + xseeprom_pause +} + +void xseeprom_stop(void) { + xseeprom_mode_wr(1); + xseeprom_dout(0); + pause_1000(10); + xseeprom_clk(1); + pause_1000(10); + xseeprom_dout(1); + pause_1000(10); +} + +void xseeprom_undo (void){ + Controll.all=xeeprom_controll_store; + Controll.bit.OE_BUF_Is_ON=1; + xControll_wr(); +} + +unsigned int xseeprom_write_byte(unsigned int byte){ + int i; + unsigned int ack; + + xseeprom_mode_wr(1); + for (i=7;i>=0;i--) + { + xseeprom_dout((byte >> i) & 1); + xseeprom_pause + xseeprom_clk(1); + xseeprom_pause + xseeprom_clk(0); + xseeprom_pause + } + + xseeprom_dout(1); + xseeprom_mode_wr(0); + pause_1000(10); + + xseeprom_pause + xseeprom_clk(1); + pause_1000(10); + xseeprom_pause + ack=xseeprom_din(); + xseeprom_clk(0); + xseeprom_pause + + pause_1000(10); + + /* +// xseeprom_dout(1); + xseeprom_mode_wr(0); + pause_1000(10); + +// xseeprom_mode_wr(0); + xseeprom_dout(1); + xseeprom_pause + xseeprom_clk(1); + xseeprom_pause + ack=xseeprom_din(); + xseeprom_clk(0); + xseeprom_pause + + pause_1000(10); + */ + return ack; // '0' - ok! +} + +void xseeprom_clk (unsigned int clk) { + xeeprom_controll_fast&=0xfdff; + xeeprom_controll_fast|=(clk<<9 & 0x0200); + i_WriteMemory(ADR_CONTR_REG_FOR_WRITE,xeeprom_controll_fast); +} + +unsigned int xseeprom_din (void) { + return (i_ReadMemory(ADR_CONTR_REG_FOR_READ)>>15 & 0x0001); +} + +void xseeprom_dout (unsigned int data) { + xeeprom_controll_fast&=0xff7f; + xeeprom_controll_fast|=(data<<7 & 0x0080); + i_WriteMemory(ADR_CONTR_REG_FOR_WRITE,xeeprom_controll_fast); +} + +void xseeprom_mode_wr (unsigned int mode) { // '1' - write, '0' - read + xeeprom_controll_fast&=0xffef; + xeeprom_controll_fast|=(mode<<4 & 0x0010); + i_WriteMemory(ADR_CONTR_REG_FOR_WRITE,xeeprom_controll_fast); +} + + + + + +/*********************** example ****************************************** +* i=xilinx_live_smart(0x5aaa); +* i=i|xilinx_live_smart(0x0000) +***************************************************************************/ +unsigned int xilinx_live_smart(unsigned int d) // dout(15:0) = din(11:8) & din(15:12) & not din(7:0); +{ + unsigned int dout; + unsigned int d_rd; + + i_WriteMemory(ADR_XTEST_REG,d); + dout = ~d; + d_rd = i_ReadMemory(ADR_XTEST_REG); + if (d_rd!=dout) + return 1; + return 0; +} + + + +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// + +int enable_er0_control(void) +{ + return xilinx_live_smart(0x5AA5); +} + + + +int test_xilinx_live(void) +{ + unsigned int i; + //test xilinx controller on read/write operation + for(i=0;i<10000;i++) + if(xilinx_live_smart(i)) + return xerror(main_er_ID(1),(void *)0); + return 0; +} + +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// + + + + + diff --git a/Inu/Src/N12_Xilinx/Spartan2E_Functions.h b/Inu/Src/N12_Xilinx/Spartan2E_Functions.h new file mode 100644 index 0000000..be1577a --- /dev/null +++ b/Inu/Src/N12_Xilinx/Spartan2E_Functions.h @@ -0,0 +1,264 @@ +#ifndef _SPARTAN2E_FUNCTIONS_H +#define _SPARTAN2E_FUNCTIONS_H + +#include "DSP281x_Device.h" + +#define SIZE_XILINX200 90126 // count words + +struct XControll_reg_bit { + unsigned int OE_BUF_Is_ON:1; + unsigned int RemotePlane_Is_Reset:1; + unsigned int Int_for_XNMI_XINT13_ON:1; + unsigned int Int_for_XINT1_XBIO_ON:1; + unsigned int line_Z_ER0_OUT_Is:1; + unsigned int line_SET_MODE_Is:1; + unsigned int line_ER0_OUT_Sorce_Is_Tms:1; + unsigned int line_ER0_OUT_Is:1; + unsigned int line_CLKS_Sorce_Is_Tms:1; + unsigned int line_CLKS_Is:1; + unsigned int line_P7_4_Sorce_Is_Tms:1; + unsigned int line_P7_4_Is:4; // 4 bits + unsigned int line_ER0_IN_Is:1; // WR has no effect + }; + typedef union { + unsigned int all; + struct XControll_reg_bit bit; + } XControll_reg; + +union XSeeprom_command_reg { + unsigned int all; + struct { + unsigned int WR0:1; + unsigned int P0:1; + unsigned int A1:1; + unsigned int bit3:1; + unsigned int bit4:1; + unsigned int bit5:1; + unsigned int bit6:1; + unsigned int bit7:1; + } bit; + }; + +struct XSerial_bus_config_bit { + unsigned int Use_Config:1; + unsigned int Number_of_Frequency_is:3; + unsigned int Use_Timer:1; + unsigned int Range_CountTimer:4; + unsigned int Use_Filtr_on_din:1; + unsigned int Use_only_fast_Filtr_on_din:1; + unsigned int Use_Tweaking:1; + unsigned int Use_compensation_delay_on_Tweaking:1; + unsigned int Use_SyncRdWr:1; + unsigned int reserve_bits:2; // unused 2 bits + }; + +union XSerial_bus_config_reg { + unsigned int all; + struct XSerial_bus_config_bit bit; + }; + +struct XSerial_bus_intc_din_bit { + unsigned int State_Is_Idle:1; + unsigned int Error_CRC:1; + unsigned int Error_Comand:1; + unsigned int Timeout_Is_Complete:1; + unsigned int Mode_Is_Config:1; + unsigned int rezerv:3; + }; + +typedef volatile union { + unsigned int all; + struct XSerial_bus_intc_din_bit bit; + } XSerial_bus_intc_din_reg; + +struct XSerial_bus_adr_bit { + unsigned int AdrPlane:4; + unsigned int reserve_bits:3; // unused 3 bits + unsigned int RdWR:1; // '0' - WR, '1' - RD + unsigned int AdrReg:8; + }; + +union XSerial_bus_adr_reg { + unsigned int all; + struct XSerial_bus_adr_bit bit; + }; + +typedef struct { + unsigned int TypeAccess; + unsigned int AdrPlane; + unsigned int AdrReg; + unsigned int DataWr; + unsigned int DataRd; + } Xmemory_uni; + +typedef volatile struct { + unsigned int BaseAddress; // Base address of registers // + unsigned int DataWr; // Data for write to selected register // + unsigned int DataRd; // Reading data from selected register // + union XSerial_bus_adr_reg Adr; + XSerial_bus_intc_din_reg ISR; + union XSerial_bus_config_reg Config; + unsigned int IsReady:1; // Device is initialized and ready // + } XSerial_bus; + +struct XSeeprom_s { + unsigned int Adr_device; + unsigned long Adr; + unsigned long Adr_seeprom; + unsigned long size; + unsigned long ok_write; + unsigned long write_error; + unsigned long repeat_error; + }; + +typedef volatile struct XSeeprom_s XSeeprom_t; + +struct XSerial_bus_intc_mer_bit { + unsigned int Master_Enable:1; + unsigned int Hardware_Int_Enable:1; + }; + +union XSerial_bus_intc_mer_reg { + unsigned int all; + struct XSerial_bus_intc_mer_bit bit; + }; + +struct XSerial_bus_INTC { + XSerial_bus_intc_din_reg ISR; + XSerial_bus_intc_din_reg IER; + XSerial_bus_intc_din_reg IPR; + union XSerial_bus_intc_mer_reg MER; + }; + +struct XSerial_Tweaking_Data { + unsigned int Tweaking_tr_line:4; + unsigned int Tweaking_rec_line:4; + }; +/* +struct XSerial_bus_Config_Data { + unsigned int Constant_for_Timer; + unsigned int Number_Wait_State_for_TrRec:4; + unsigned int Number_Wait_State_for_Pause:4; + struct XSerial_Tweaking_Data Tweaking_chanal[8]; + unsigned int Delay_clk_for_Tr:7; + unsigned int Delay_clk_for_Rec:7; + unsigned int Use_fast_Filtr:1; + unsigned int Use_fast_Transmit:1; + unsigned int Tweaking_tbuf_en:4; + }; + */ +/* +typedef volatile struct { + unsigned int PlaneIsLive; // For selected DelayLine chanal is visible: QualityTrRec = 100%, bit per chanal + unsigned int CountErrors; // count errors transmit-recieve + XSerial_bus *Bus; + struct XSerial_bus_INTC INTC; + struct XSerial_bus_Config_Data Config_Data; + unsigned int Number_Chanal; + } XSerial_bus_stats; +*/ + +/* +struct PARALLEL_BITS { // bits description + Uint16 res0:1; // 0 + Uint16 res1:1; // 1 + Uint16 res2:1; // 2 + Uint16 res3:1; // 3 + Uint16 res4:1; // 4 + Uint16 res5:1; // 5 + Uint16 res6:1; // 6 + Uint16 res7:1; // 7 + Uint16 res8:1; // 8 + Uint16 res9:1; // 9 + Uint16 res10:1; // 10 + Uint16 res11:1; // 11 + Uint16 res12:1; // 12 + Uint16 res13:1; // 13 + Uint16 res14:1; // 14 + Uint16 res15:1; // 15 +}; + +struct PARALLEL_STATUS_BITS { // bits description + Uint16 err_crc:1; // 0 + Uint16 not_ready:1; // 1 + Uint16 res2:1; // 2 + Uint16 res3:1; // 3 + Uint16 res4:1; // 4 + Uint16 res5:1; // 5 + Uint16 res6:1; // 6 + Uint16 res7:1; // 7 + Uint16 res8:1; // 8 + Uint16 res9:1; // 9 + Uint16 res10:1; // 10 + Uint16 res11:1; // 11 + Uint16 res12:1; // 12 + Uint16 res13:1; // 13 + Uint16 res14:1; // 14 + Uint16 res15:1; // 15 +}; + + +union PARALLEL1_REG { + Uint16 all; + struct PARALLEL_BITS bit; +}; + +union PARALLEL2_REG { + Uint16 all; + struct PARALLEL_BITS bit; +}; + +union PARALLEL3_REG { + Uint16 all; + struct PARALLEL_BITS bit; +}; + +union PARALLEL4_REG { + Uint16 all; + struct PARALLEL_BITS bit; +}; + +union PARALLEL5_REG { + Uint16 all; + struct PARALLEL_BITS bit; +}; + +union PARALLEL_STATUS_REG { + Uint16 all; + struct PARALLEL_STATUS_BITS bit; +}; + +typedef volatile struct { // bits description + union PARALLEL1_REG reg1; + union PARALLEL2_REG reg2; + union PARALLEL3_REG reg3; + union PARALLEL4_REG reg4; + union PARALLEL5_REG reg5; + union PARALLEL_STATUS_REG status; +} PARALLEL_REGS; +*/ + +int load_xilinx_new(unsigned long adr,unsigned long size); + +int xflash_remote_eeprom(unsigned int adr_device, unsigned long adr, + unsigned long adr_eeprom, unsigned long size, unsigned long *ok_write, + unsigned long *write_error, unsigned long *repeat_error ); + +long xread_remote_eeprom(unsigned int adr_device, unsigned long adr_eeprom, + unsigned long adr, unsigned long size, unsigned long *ok_write, + unsigned long *write_error, unsigned long *repeat_error ); + +long xverify_remote_eeprom(unsigned int adr_device, unsigned long adr, + unsigned long adr_eeprom, unsigned long size, unsigned long *ok_write, + unsigned long *write_error, unsigned long *repeat_error ); + + +int test_xilinx_live(void); + +int enable_er0_control(void); + +void ResetNPeriphPlane(unsigned int np); + + + +#endif diff --git a/Inu/Src/N12_Xilinx/TuneUpPlane.c b/Inu/Src/N12_Xilinx/TuneUpPlane.c new file mode 100644 index 0000000..9dd05b3 --- /dev/null +++ b/Inu/Src/N12_Xilinx/TuneUpPlane.c @@ -0,0 +1,340 @@ +#include "TuneUpPlane.h" + +#include "DSP281x_Examples.h" +#include "DSP281x_Device.h" +#include "DSP281x_Xintf.h" + +#define SelectWorkWithFlash() WriteOper(0,0,0,0) +#define SelectStrob67_ForFlash() WriteOper(1,0,1,0) + +unsigned int cl_led1 = 0; +unsigned int cl_led2 = 0; + +void SetupOperLine(); + +#pragma CODE_SECTION(Led1_Toggle,".fast_run"); +#pragma CODE_SECTION(Led2_Toggle,".fast_run"); + +#pragma CODE_SECTION(i_led2_on_off,".fast_run"); +void i_led2_on_off(int i) +{ + EALLOW; + + if (i) GpioDataRegs.GPDSET.bit.GPIOD6=1; + else GpioDataRegs.GPDCLEAR.bit.GPIOD6=1; + + + EDIS; +} + +#pragma CODE_SECTION(i_led1_on_off,".fast_run"); +void i_led1_on_off(int i) +{ + EALLOW; + if (i) GpioDataRegs.GPASET.bit.GPIOA10=1; + else GpioDataRegs.GPACLEAR.bit.GPIOA10=1; + + EDIS; +} + + +//#pragma CODE_SECTION(i_led2_on_off_special,".fast_run"); +//void i_led2_on_off_special(int i) +//{ +// EALLOW; +// +// if (i) GpioDataRegs.GPDSET.bit.GPIOD6=1; +// else GpioDataRegs.GPDCLEAR.bit.GPIOD6=1; +// +// +// EDIS; +//} + +#pragma CODE_SECTION(i_led1_on_off_special,".fast_run"); +void i_led1_on_off_special(int i) +{ + EALLOW; + if (i) + { + GpioDataRegs.GPASET.bit.GPIOA10=1; + cl_led1++; + } + else + { + if (cl_led1) + cl_led1--; + + if (cl_led1 == 0) + GpioDataRegs.GPACLEAR.bit.GPIOA10=1; + } + + EDIS; +} + +#pragma CODE_SECTION(i_led2_on_off_special,".fast_run"); +void i_led2_on_off_special(int i) +{ + EALLOW; + if (i) + { + GpioDataRegs.GPDSET.bit.GPIOD6=1; + cl_led2++; + } + else + { + if (cl_led2) + cl_led2--; + + if (cl_led2 == 0) + GpioDataRegs.GPDCLEAR.bit.GPIOD6=1; + } + + EDIS; +} + + +void Led1_Toggle() +{ + EALLOW; + GpioDataRegs.GPATOGGLE.bit.GPIOA10=1; + EDIS; +} + + +void Led2_Toggle() +{ + EALLOW; + GpioDataRegs.GPDTOGGLE.bit.GPIOD6=1; + EDIS; +} + +void SetupLedsLine() +{ + EALLOW; + GpioMuxRegs.GPDMUX.bit.T4CTRIP_SOCB_GPIOD6 = 0; + GpioDataRegs.GPDDAT.bit.GPIOD6 = 0; + GpioMuxRegs.GPDDIR.bit.GPIOD6 = 1; + + GpioMuxRegs.GPAMUX.bit.CAP3QI1_GPIOA10 = 0; + GpioDataRegs.GPADAT.bit.GPIOA10 = 0; + GpioMuxRegs.GPADIR.bit.GPIOA10 = 1; + EDIS; + +} + +#pragma CODE_SECTION(pause_1000,".fast_run"); +void pause_1000(unsigned long t) +{ + unsigned long i; + + t = t >> 1; + + for (i = 0; i < t; i++) + { + DSP28x_usDelay(40L); + } +} +//Xilinx Zone +void XintfZone0_Timing(void) +{ + // Zone 0------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING0.bit.XWRLEAD = 3;//2; + XintfRegs.XTIMING0.bit.XWRACTIVE = 5;//2;//1; // 1 + XintfRegs.XTIMING0.bit.XWRTRAIL = 1;//0; + // Zone read timing + XintfRegs.XTIMING0.bit.XRDLEAD = 3; + XintfRegs.XTIMING0.bit.XRDACTIVE = 5;//1 + XintfRegs.XTIMING0.bit.XRDTRAIL = 1;//1 + + // do not double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING0.bit.X2TIMING = 0; + + // Zone will not sample READY + XintfRegs.XTIMING0.bit.USEREADY = 0;//1; + XintfRegs.XTIMING0.bit.READYMODE = 0;//1; + + // Size must be 1,1 - other values are reserved + XintfRegs.XTIMING0.bit.XSIZE = 3; + + + + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + asm(" RPT #7 || NOP"); +} + +void XintfZone6_And7_Timing(void) +{ + + // All Zones--------------------------------- + // Timing for all zones based on XTIMCLK = SYSCLKOUT/2 + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + // Buffer up to 0 writes + XintfRegs.XINTCNF2.bit.WRBUFF = 0; + // XCLKOUT is enabled + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + // XCLKOUT = XTIMCLK +#ifdef XLOW_FREQUENCY_MODE + XintfRegs.XINTCNF2.bit.CLKMODE = 1; +#else + XintfRegs.XINTCNF2.bit.CLKMODE = 0; +#endif + XintfRegs.XINTCNF2.bit.MPNMC = 0; + + + // Zone 6------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING6.bit.XWRLEAD = 3; + XintfRegs.XTIMING6.bit.XWRACTIVE = 7; + XintfRegs.XTIMING6.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING6.bit.XRDLEAD = 3; + XintfRegs.XTIMING6.bit.XRDACTIVE = 7;//3; + XintfRegs.XTIMING6.bit.XRDTRAIL = 3; + + // do not double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING6.bit.X2TIMING = 0; + + // Zone will not sample READY + XintfRegs.XTIMING6.bit.USEREADY = 0;//1; + XintfRegs.XTIMING6.bit.READYMODE = 0;//1; + + // Size must be 1,1 - other values are reserved + XintfRegs.XTIMING6.bit.XSIZE = 3; + + + // Zone 7------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING7.bit.XWRLEAD = 3; + XintfRegs.XTIMING7.bit.XWRACTIVE = 7; + XintfRegs.XTIMING7.bit.XWRTRAIL = 3; + // Zone read timing + XintfRegs.XTIMING7.bit.XRDLEAD = 3; + XintfRegs.XTIMING7.bit.XRDACTIVE = 3; + XintfRegs.XTIMING7.bit.XRDTRAIL = 3; + + // don't double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING7.bit.X2TIMING = 0; + + // Zone will not sample XREADY signal + XintfRegs.XTIMING7.bit.USEREADY = 0; + XintfRegs.XTIMING7.bit.READYMODE = 0; + + // Size must be 1,1 - other values are reserved + XintfRegs.XTIMING7.bit.XSIZE = 3; + + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + asm(" RPT #7 || NOP"); +} + +void XintfZone2_Timing(void) +{ + + // All Zones--------------------------------- + // Timing for all zones based on XTIMCLK = SYSCLKOUT/2 + XintfRegs.XINTCNF2.bit.XTIMCLK = 1; + // Buffer up to 0 writes + XintfRegs.XINTCNF2.bit.WRBUFF = 0; + // XCLKOUT is enabled + XintfRegs.XINTCNF2.bit.CLKOFF = 0; + // XCLKOUT = XTIMCLK + XintfRegs.XINTCNF2.bit.CLKMODE = 0; + + XintfRegs.XINTCNF2.bit.MPNMC = 0; + + + // Zone 6------------------------------------ + // When using ready, ACTIVE must be 1 or greater + // Lead must always be 1 or greater + // Zone write timing + XintfRegs.XTIMING2.bit.XWRLEAD = 3;//2; + XintfRegs.XTIMING2.bit.XWRACTIVE = 4;//2; + XintfRegs.XTIMING2.bit.XWRTRAIL = 2;//2; + // Zone read timing + XintfRegs.XTIMING2.bit.XRDLEAD = 2; + XintfRegs.XTIMING2.bit.XRDACTIVE = 3; //1; + XintfRegs.XTIMING2.bit.XRDTRAIL = 1;//2;//0; + + // do not double all Zone read/write lead/active/trail timing + XintfRegs.XTIMING2.bit.X2TIMING = 0; + + // Zone will not sample READY + XintfRegs.XTIMING2.bit.USEREADY = 0;//1; + XintfRegs.XTIMING2.bit.READYMODE = 0;//1; + + // Size must be 1,1 - other values are reserved + XintfRegs.XTIMING2.bit.XSIZE = 3; + + + + //Force a pipeline flush to ensure that the write to + //the last register configured occurs before returning. + asm(" RPT #7 || NOP"); +} + +void FlashInit() +{ + SetupOperLine(); + + SelectStrob67_ForFlash(); + + XintfZone6_And7_Timing(); + SelectWorkWithFlash(); +} + +void SetupOperLine() +{ + EALLOW; + + GpioMuxRegs.GPAMUX.bit.C1TRIP_GPIOA13=0; + GpioMuxRegs.GPAMUX.bit.C2TRIP_GPIOA14=0; + GpioMuxRegs.GPAMUX.bit.C3TRIP_GPIOA15=0; + GpioMuxRegs.GPBMUX.bit.C4TRIP_GPIOB13=0; + GpioMuxRegs.GPBMUX.bit.C6TRIP_GPIOB15=0; + + GpioMuxRegs.GPADIR.bit.GPIOA13=1; + GpioMuxRegs.GPADIR.bit.GPIOA14=1; + GpioMuxRegs.GPADIR.bit.GPIOA15=1; + GpioMuxRegs.GPBDIR.bit.GPIOB13=1; + GpioMuxRegs.GPBDIR.bit.GPIOB15=1; + + GpioMuxRegs.GPAQUAL.all=0; + GpioMuxRegs.GPBQUAL.all=0; + EDIS; + + WriteOper(1,1,1,1); + +} + +void WriteOper(unsigned char oper_mode1,unsigned char oper_mode2, unsigned char oper_mode3, unsigned char oper_mode4) +{ + EALLOW; + GpioDataRegs.GPADAT.bit.GPIOA13=oper_mode1; + GpioDataRegs.GPADAT.bit.GPIOA14=oper_mode2; + GpioDataRegs.GPADAT.bit.GPIOA15=oper_mode3; + GpioDataRegs.GPBDAT.bit.GPIOB13=oper_mode4; + + asm(" NOP"); + GpioDataRegs.GPBDAT.bit.GPIOB15=0; + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + GpioDataRegs.GPBDAT.bit.GPIOB15=1; + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + GpioDataRegs.GPBDAT.bit.GPIOB15=0; + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + + EDIS; +} diff --git a/Inu/Src/N12_Xilinx/TuneUpPlane.h b/Inu/Src/N12_Xilinx/TuneUpPlane.h new file mode 100644 index 0000000..1388b59 --- /dev/null +++ b/Inu/Src/N12_Xilinx/TuneUpPlane.h @@ -0,0 +1,38 @@ +#ifndef _TUNE_UP_PLANE_H +#define _TUNE_UP_PLANE_H + +#include "DSP281x_Device.h" + +void WriteOper(unsigned char oper_mode1,unsigned char oper_mode2, unsigned char oper_mode3, unsigned char oper_mode4); +void pause_1000(unsigned long t); +void XintfZone0_Timing(void); +void XintfZone6_And7_Timing(void); +void XintfZone2_Timing(void); +void FlashInit(); + +//extern void DSP28x_usDelay(long LoopCount); + +void Led1_Toggle(); +void Led2_Toggle(); + +void i_led2_on_off(int i); +void i_led1_on_off(int i); + +void i_led2_on_off_special(int i); +void i_led1_on_off_special(int i); + + +#define i_led1_on() {EALLOW;GpioDataRegs.GPASET.bit.GPIOA10 = 1;EDIS;} +#define i_led1_off() {EALLOW;GpioDataRegs.GPACLEAR.bit.GPIOA10 = 1;;EDIS;} + +#define i_led2_on() {EALLOW;GpioDataRegs.GPDSET.bit.GPIOD6 = 1;EDIS;} +#define i_led2_off() {EALLOW;GpioDataRegs.GPDCLEAR.bit.GPIOD6 = 1;;EDIS;} + +#define i_led1_toggle() {EALLOW; GpioDataRegs.GPATOGGLE.bit.GPIOA10 = 1; EDIS;} +#define i_led2_toggle() {EALLOW; GpioDataRegs.GPDTOGGLE.bit.GPIOD6 = 1; EDIS;} + + + +void SetupLedsLine(); + +#endif diff --git a/Inu/Src/N12_Xilinx/modbus_struct.h b/Inu/Src/N12_Xilinx/modbus_struct.h new file mode 100644 index 0000000..d3dec6e --- /dev/null +++ b/Inu/Src/N12_Xilinx/modbus_struct.h @@ -0,0 +1,39 @@ +#ifndef _MODBUS_STRUCT_H +#define _MODBUS_STRUCT_H + +//#include "RS_Functions.h" + +struct MODBUS_WORD_STRUCT { // bit description + unsigned int LB:8; // 16:23 High word low byte + unsigned int HB:8; // 24:31 High word high byte +}; + + +struct MODBUS_BITS_STRUCT { // bit description + unsigned int bit0: 1; + unsigned int bit1: 1; + unsigned int bit2: 1; + unsigned int bit3: 1; + unsigned int bit4: 1; + unsigned int bit5: 1; + unsigned int bit6: 1; + unsigned int bit7: 1; + unsigned int bit8: 1; + unsigned int bit9: 1; + unsigned int bit10: 1; + unsigned int bit11: 1; + unsigned int bit12: 1; + unsigned int bit13: 1; + unsigned int bit14: 1; + unsigned int bit15: 1; +}; + +typedef union { + //unsigned int all; + int all; + struct MODBUS_BITS_STRUCT bit; + struct MODBUS_WORD_STRUCT byte; +} MODBUS_REG_STRUCT; + +#endif + diff --git a/Inu/Src/N12_Xilinx/not_use/xp_rotation_sensor.c b/Inu/Src/N12_Xilinx/not_use/xp_rotation_sensor.c new file mode 100644 index 0000000..61fb47f --- /dev/null +++ b/Inu/Src/N12_Xilinx/not_use/xp_rotation_sensor.c @@ -0,0 +1,267 @@ +#include "xp_project.h" +#include "xp_rotation_sensor.h" + +#include "xp_project.h" + + +T_rotation_sensor rotation_sensor = T_CDS_ROTATION_SENSOR_DEFAULTS; + +//, +#define SAMPLING_TIME_NS 1 // 16,666667ns +#define SAMPLING_TIME_MS 0 // 1,666667us +// , . +// "" +// +#define LEVEL_SWITCH_NANOSEC 327 +#define LEVEL_SWITCH_MICROSEC 0xC000 + + +static void read_in_sensor_line1(T_cds_in_rotation_sensor *rs); +static void read_in_sensor_line2(T_cds_in_rotation_sensor *rs); +static void read_command_reg(T_cds_in_rotation_sensor *rs); +static void write_command_reg(T_cds_in_rotation_sensor *rs); +static void tune_sampling_time(T_rotation_sensor *rs); +static void wait_for_registers_updated(T_cds_in_rotation_sensor *rs); +static void read_direction_in_plane(T_cds_in_rotation_sensor *rs); + +void rot_sensor_set(T_rotation_sensor *rs) +{ + + if(rs->use_sensor1 || rs->use_sensor2) + { + rs->in_plane.set(&rs->in_plane); + } + if(rs->use_angle_plane) + { + rs->rotation_plane.set(&rs->rotation_plane); + } +} + +void in_plane_set(T_cds_in_rotation_sensor* rs) +{ + if(!rs->cds_in->useit) + { + return; + } + + rs->cds_in->write.sbus.enabled_channels.all = rs->write.sbus.enabled_channels.all; + rs->cds_in->write.sbus.first_sensor.all = rs->write.sbus.first_sensor_inputs.all; + rs->cds_in->write.sbus.second_sensor.all = rs->write.sbus.second_sensor_inputs.all; + // rs->cds_in->write_sbus(rs->cds_in); + write_command_reg(rs); + +} + + +void angle_plane_set(T_cds_angle_sensor *rs) +{ + if((rs->cds_rs == NULL) || (!rs->cds_rs->useit)) + { + return; + } + + rs->cds_rs->write.sbus.config.all = rs->write.sbus.config.all; + rs->cds_rs->write_sbus(rs->cds_rs); +} + +void sensor_read(T_rotation_sensor *rs) +{ + if(rs->use_sensor1 || rs->use_sensor2 || rs->use_angle_plane) + { + wait_for_registers_updated(&rs->in_plane); + read_direction_in_plane(&rs->in_plane); + } + else + { + return; + } + if(rs->use_sensor1) + { + rs->in_plane.read_sensor1(&rs->in_plane); + } + if(rs->use_sensor2) + { + rs->in_plane.read_sensor2(&rs->in_plane); + } + if(rs->use_angle_plane) + { + rs->rotation_plane.read_sensor(&rs->rotation_plane); + } +#ifdef AUTO_CHANGE_SAMPLING_TIME + tune_sampling_time(rs); +#endif +} + +void in_sensor_read1(T_cds_in_rotation_sensor *rs) +{ + read_in_sensor_line1(rs); +#if C_PROJECT_TYPE != PROJECT_BALZAM + rs->out.Impulses1 = rs->read.regs.n_impulses_line1; + rs->out.Time1 = rs->read.regs.time_line1 / 60; + //Counter`s freq is 60 => N/60 = time in mksec +#endif + rs->out.CountZero1 = rs->read.regs.zero_time_line1; + rs->out.CountOne1 = rs->read.regs.one_time_line1; + + rs->out.counter_freq1 = rs->read.regs.comand_reg.bit.sampling_time1; + + rs->out.direction1 = rs->read.pbus.direction.bit.sensor1; +} + +void in_sensor_read2(T_cds_in_rotation_sensor *rs) +{ + read_in_sensor_line2(rs); +#if C_PROJECT_TYPE != PROJECT_BALZAM + rs->out.Impulses2 = rs->read.regs.n_impulses_line2; + rs->out.Time2 = rs->read.regs.time_line2 / 60; +#endif + rs->out.CountZero2 = rs->read.regs.zero_time_line2; + rs->out.CountOne2 = rs->read.regs.one_time_line2; + + rs->out.counter_freq2 = rs->read.regs.comand_reg.bit.sampling_time2; + + rs->out.direction2 = rs->read.pbus.direction.bit.sensor2; +} + +void read_in_sensor_line1(T_cds_in_rotation_sensor *rs) +{ + if(!rs->read.regs.comand_reg.bit.update_registers) + { +#if C_PROJECT_TYPE != PROJECT_BALZAM + rs->read.regs.time_line1 = i_ReadMemory(ADR_SENSOR_S1_T_PERIOD);//TODO check time when turn off + rs->read.regs.n_impulses_line1 = i_ReadMemory(ADR_SENSOR_S1_COUNT_IMPULS); +#endif + rs->read.regs.zero_time_line1 = i_ReadMemory(ADR_SENSOR_S1_T_PERIOD_LOW_ONE_IMPULS); + rs->read.regs.one_time_line1 = i_ReadMemory(ADR_SENSOR_S1_T_PERIOD_HIGH_ONE_IMPULS); + } +} + +void read_in_sensor_line2(T_cds_in_rotation_sensor *rs) +{ + if(!rs->read.regs.comand_reg.bit.update_registers) + { +#if C_PROJECT_TYPE != PROJECT_BALZAM + rs->read.regs.time_line2 = i_ReadMemory(ADR_SENSOR_S2_T_PERIOD); + rs->read.regs.n_impulses_line2 = i_ReadMemory(ADR_SENSOR_S2_COUNT_IMPULS); +#endif + rs->read.regs.zero_time_line2 = i_ReadMemory(ADR_SENSOR_S2_T_PERIOD_LOW_ONE_IMPULS); + rs->read.regs.one_time_line2 = i_ReadMemory(ADR_SENSOR_S2_T_PERIOD_HIGH_ONE_IMPULS); + } +} + +void write_command_reg(T_cds_in_rotation_sensor *rs) +{ + WriteMemory(ADR_SENSOR_CMD, rs->write.regs.comand_reg.all); +} + +void read_command_reg(T_cds_in_rotation_sensor *rs) +{ + rs->read.regs.comand_reg.all = i_ReadMemory(ADR_SENSOR_CMD); +} + +void update_sensors_data_r(T_rotation_sensor *rs) +{ + rs->in_plane.write.regs.comand_reg.bit.update_registers = 1; + write_command_reg(&rs->in_plane); +// rs->in_plane.write.regs.comand_reg.bit.update_registers = 0; +} + +void read_direction_in_plane(T_cds_in_rotation_sensor *rs) +{ +/* + rs->read.pbus.direction.bit.sensor1 = rs->cds_in->read.pbus.direction_in.bit.dir0 == 2 ? 1 : + rs->cds_in->read.pbus.direction_in.bit.dir0 == 1 ? -1 : + 0; + rs->read.pbus.direction.bit.sensor2 = rs->cds_in->read.pbus.direction_in.bit.dir1 == 2 ? 1 : + rs->cds_in->read.pbus.direction_in.bit.dir1 == 1 ? -1 : + 0; + rs->read.pbus.direction.bit.sens_err1 = rs->cds_in->read.pbus.direction_in.bit.dir0 == 3; + rs->read.pbus.direction.bit.sens_err2 = rs->cds_in->read.pbus.direction_in.bit.dir1 == 3; +*/ + //Direction changes not often. May be, it`s enough to read it in main cycle. +} + +void wait_for_registers_updated(T_cds_in_rotation_sensor *rs) +{ + int counter_in_while = 0; + read_command_reg(rs); + while(rs->read.regs.comand_reg.bit.update_registers) + { + read_command_reg(rs); + (rs->count_wait_for_update_registers)++; + counter_in_while++; + if(counter_in_while > 1000) + { + (rs->error_update)++; + break; + } + } +} + +void tune_sampling_time(T_rotation_sensor *rs) +{ + if((rs->use_sensor1 && (rs->in_plane.read.regs.zero_time_line1 < LEVEL_SWITCH_NANOSEC)) + || (rs->use_sensor2 && (rs->in_plane.read.regs.zero_time_line2 < LEVEL_SWITCH_NANOSEC))) + { + rs->in_plane.write.regs.comand_reg.bit.set_sampling_time = SAMPLING_TIME_NS; + } + + if((rs->use_sensor1 && (rs->in_plane.read.regs.zero_time_line1 > LEVEL_SWITCH_MICROSEC)) + || (rs->use_sensor2 && (rs->in_plane.read.regs.zero_time_line2 > LEVEL_SWITCH_MICROSEC))) + { + rs->in_plane.write.regs.comand_reg.bit.set_sampling_time = SAMPLING_TIME_MS; + } +} + +void angle_sensor_read(T_cds_angle_sensor *as) +{ + as->cds_rs->read_pbus(as->cds_rs); + + if(as->cds_rs->read.sbus.config.bit.channel1_enable) + { +// logpar.log15 = as->cds_rs->read.pbus.sensor[0].turned_angle; +// logpar.log16 = as->cds_rs->read.pbus.sensor[0].angle; + + as->out.Delta_angle1 = as->cds_rs->read.pbus.sensor[0].turned_angle; + as->out.Current_angle1 = as->cds_rs->read.pbus.sensor[0].angle << 3; + } + else + { + as->out.Delta_angle1 = 0; + as->out.Current_angle1 = 0; + } + if(as->cds_rs->read.sbus.config.bit.channel2_enable) + { + as->out.Delta_angle2 = as->cds_rs->read.pbus.sensor[1].turned_angle; + as->out.Current_angle2 = as->cds_rs->read.pbus.sensor[1].angle << 3; + } + else + { + as->out.Delta_angle2 = 0; + as->out.Current_angle2 = 0; + } + if(as->cds_rs->read.sbus.config.bit.channel3_enable) + { + as->out.Delta_angle3 = as->cds_rs->read.pbus.sensor[2].turned_angle; + as->out.Current_angle3 = as->cds_rs->read.pbus.sensor[2].angle << 3; + } + else + { + as->out.Delta_angle3 = 0; + as->out.Current_angle3 = 0; + } + if(as->cds_rs->read.sbus.config.bit.channel4_enable) + { + as->out.Delta_angle4 = as->cds_rs->read.pbus.sensor[3].turned_angle; + as->out.Current_angle4 = as->cds_rs->read.pbus.sensor[3].angle << 3; + } + else + { + as->out.Delta_angle4 = 0; + as->out.Current_angle4 = 0; + } + + as->out.survey_time_mks = (as->read.sbus.config.bit.survey_time + 1) * 10; + +} + diff --git a/Inu/Src/N12_Xilinx/not_use/xp_rotation_sensor.h b/Inu/Src/N12_Xilinx/not_use/xp_rotation_sensor.h new file mode 100644 index 0000000..7111a0c --- /dev/null +++ b/Inu/Src/N12_Xilinx/not_use/xp_rotation_sensor.h @@ -0,0 +1,346 @@ +#ifndef XP_ROT_SENS_H +#define XP_ROT_SENS_H + +#include "x_basic_types.h" +#include "xp_cds_in.h" +#include "xp_cds_rs.h" + + +//RS speed of angle sensor +#define TS400 0 +#define TS350 1 +#define TS300 2 +#define TS250 3 +#define TS200 4 + +//, +#define SAMPLING_TIME_NS 1 // 16,666667ns +#define SAMPLING_TIME_MS 0 // 1,666667us + +// , +// 1 . +//#define AUTO_CHANGE_SAMPLING_TIME +/* + , + rotation_sensor.read_sensors(&rotation_sensor); + IN + rotation_sensor.in_plane.out.... + RS + rotation_sensor.rotation_plane.out.... +*/ + +///////////////////////////////////////////////////////////// +// IN plane +///////////////////////////////////////////////////////////// + +// Registers with data for rotation sensor + +typedef union { + unsigned int all; + struct { + unsigned int filter_sensitivity:12; + unsigned int set_sampling_time:1; //(1)-16,666667ns (0)-1,666667us + unsigned int sampling_time2:1; //(1)-16,666667ns (0)-1,666667us + unsigned int sampling_time1:1; + unsigned int update_registers:1; //0 - updated + }bit; +}T_cds_in_comand; + +#define R_CDS_IN_COMAND_DEFAULT 0 + +typedef struct { + unsigned int time_line1; + unsigned int n_impulses_line1; + unsigned int time_line2; + unsigned int n_impulses_line2; + + unsigned int zero_time_line1; + unsigned int one_time_line1; + unsigned int zero_time_line2; + unsigned int one_time_line2; + + T_cds_in_comand comand_reg; + +} T_cds_in_rotation_sensor_read_regs; + +#define T_CDS_IN_ROTATION_SENSOR_READ_REGS_DEFAULTS {0,0,0,0, 0,0,0,0, R_CDS_IN_COMAND_DEFAULT} + +typedef struct { + T_cds_in_comand comand_reg; + +} T_cds_in_rotation_sensor_write_regs; + +#define T_CDS_IN_ROTATION_SENSOR_WRITE_REGS_DEFAULTS {R_CDS_IN_COMAND_DEFAULT} + +///////////////////////////////////////////////////////////// +//read reg parallel bus +///////////////////////////////////////////////////////////// +typedef struct { + union { + unsigned int all; + struct { + int sensor1:4; + int sensor2:4; + unsigned int sens_err1:1; + unsigned int sens_err2:1; + unsigned int reserved:6; + } bit; + } direction; + +} T_cds_in_rotation_sensor_read_pbus; + +#define T_CDS_IN_ROTATION_SENSOR_READ_PBUS_DEFAULTS {0} + +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +typedef struct { + //0 + union + { + UInt16 all; + struct{ + UInt16 discret : 8; + UInt16 reserv : 7; + UInt16 sens_2_inv_ch_90deg : 1; + UInt16 sens_2_direct_ch_90deg : 1; + UInt16 sens_2_inv_ch : 1; + UInt16 sens_2_direct_ch : 1; + UInt16 sens_1_inv_ch_90deg : 1; + UInt16 sens_1_direct_ch_90deg : 1; + UInt16 sens_1_inv_ch : 1; + UInt16 sens_1_direct_ch : 1; + }bit; + }enabled_channels; + + //1 + union + { + UInt16 all; + struct{ + UInt16 inv_ch_90deg : 4; + UInt16 direct_ch_90deg : 4; + UInt16 inv_ch : 4; + UInt16 direct_ch : 4; + }bit; + }first_sensor_inputs; + +//2 + union + { + UInt16 all; + struct{ + UInt16 inv_ch_90deg : 4; + UInt16 direct_ch_90deg : 4; + UInt16 inv_ch : 4; + UInt16 direct_ch : 4; + }bit; + }second_sensor_inputs; + +} T_cds_in_rotation_sensor_write_sbus; + +#define T_CDS_IN_ROTATION_SENSOR_WRITE_SBUS_DEFAULTS {0, 0, 0} + +//////////////////////////////////////////////////////// +typedef struct { + T_cds_in_rotation_sensor_read_pbus pbus; + T_cds_in_rotation_sensor_read_regs regs; +}T_cds_in_rotation_sensor_read; + +#define T_CDS_IN_ROTATION_SENSOR_READ_DEFAULTS \ + {T_CDS_IN_ROTATION_SENSOR_READ_PBUS_DEFAULTS, \ + T_CDS_IN_ROTATION_SENSOR_READ_REGS_DEFAULTS} + +typedef struct { + T_cds_in_rotation_sensor_write_sbus sbus; + T_cds_in_rotation_sensor_read_regs regs; +}T_cds_in_rotation_sensor_write; + +#define T_CDS_IN_ROTATION_SENSOR_WRITE_DEFAULTS \ + {T_CDS_IN_ROTATION_SENSOR_WRITE_SBUS_DEFAULTS, \ + T_CDS_IN_ROTATION_SENSOR_WRITE_REGS_DEFAULTS} + + +////// Rotation sensor with IN plane +typedef struct { + //UInt16 plane_address; + unsigned int count_wait_for_update_registers; + unsigned int error_update; + + struct { + + unsigned int Time1; // Sensor's survey time in mksec + unsigned int Impulses1; // Quantity of full impulses during survey time + unsigned int CountZero1; // Value of the zero-half-period counter + unsigned int CountOne1; // Value of the one-half-period counter + unsigned int counter_freq1; // 1 - 60MHz; 0 - 600KHz + int direction1; // 1 - direct; 0 - reverse + + unsigned int Time2; // Sensor's survey time in mksec + unsigned int Impulses2; // Quantity of full impulses during survey time + unsigned int CountZero2; // Value of the zero-half-period counter + unsigned int CountOne2; // Value of the one-half-period counter + unsigned int counter_freq2; // 1 - 60MHz; 0 - 600KHz + int direction2; // 1 - direct; 0 - reverse + } out; + + T_cds_in *cds_in; + + T_cds_in_rotation_sensor_write write; + T_cds_in_rotation_sensor_read read; + + void (*set)(); // Pointer to calculation function + + void (*read_sensor1)(); + + void (*read_sensor2)(); + +} T_cds_in_rotation_sensor; + +#define T_CDS_IN_ROTATION_SENSOR_DEFAULT \ + {0, 0, \ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ + NULL, \ + T_CDS_IN_ROTATION_SENSOR_WRITE_DEFAULTS, \ + T_CDS_IN_ROTATION_SENSOR_READ_DEFAULTS, \ + in_plane_set, \ + in_sensor_read1, \ + in_sensor_read2} + + +/////////////////////////////////////////////////////////////////////////// +///// Rotation Plane +/////////////////////////////////////////////////////////////////////////// +typedef union { + unsigned int all; + struct { + unsigned int survey_time:8; // 10 (0==10, 1==20,...) + unsigned int channel4_enable:1; + unsigned int channel3_enable:1; + unsigned int channel2_enable:1; + unsigned int channel1_enable:1; + unsigned int transmition_speed:3; + unsigned int plane_is_master:1; + }bit; +} T_cds_rotation_plane_config; + +#define T_CDS_ROTATION_PLANE_CONFIG_DEFAULT 0xA031 //{49, 1, 0, 0, 0, 2, 1} + +typedef struct { + T_cds_rotation_plane_config config; +} T_cds_rotation_plane_write_sbus; + +#define T_CDS_ROTATION_PLANE_WRITE_SBUS_DEFAULT \ + {T_CDS_ROTATION_PLANE_CONFIG_DEFAULT} + +typedef struct { + int direction; + unsigned int turned_angle; + unsigned int angle; +} RsSensor; + +#define SENSOR_DEFAULT {0, 0, 0} + +typedef struct { + RsSensor sensor[4]; +} T_cds_rotation_plane_read_pbus; + +#define T_CDS_ROTATION_PLANE_READ_PBUS_DEFAULT { \ + {SENSOR_DEFAULT, SENSOR_DEFAULT, SENSOR_DEFAULT, SENSOR_DEFAULT}} + +typedef struct { + T_cds_rotation_plane_config config; +} T_cds_rotation_plane_read_sbus; + +#define T_CDS_ROTATION_PLANE_READ_SBUS_DEFAULT {T_CDS_ROTATION_PLANE_CONFIG_DEFAULT} + +typedef struct { + T_cds_rotation_plane_write_sbus sbus; +} T_cds_rotation_plane_write; + +#define T_CDS_ROTATION_PLANE_WRITE_DEFAULT \ + {T_CDS_ROTATION_PLANE_WRITE_SBUS_DEFAULT} + +typedef struct { + T_cds_rotation_plane_read_pbus pbus; + T_cds_rotation_plane_read_sbus sbus; +} T_cds_rotation_plane_read; + +#define T_CDS_ROTATION_PLANE_READ_DEFAULT \ + {T_CDS_ROTATION_PLANE_READ_PBUS_DEFAULT, T_CDS_ROTATION_PLANE_READ_SBUS_DEFAULT} + +typedef struct { + + struct { + unsigned long Delta_angle1; + unsigned long Delta_angle2; + unsigned long Delta_angle3; + unsigned long Delta_angle4; + unsigned long Current_angle1; + unsigned long Current_angle2; + unsigned long Current_angle3; + unsigned long Current_angle4; + unsigned int survey_time_mks; // + unsigned int direction; + } out; + + unsigned int error; + + T_cds_rs *cds_rs; + + T_cds_rotation_plane_read read; + T_cds_rotation_plane_write write; + + void (*set)(); // Pointer to calculation function + + void (*read_sensor)(); + +} T_cds_angle_sensor; + +#define T_CDS_ANGLE_SENSOR_DEFAULT { \ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ + 0, NULL, \ + T_CDS_ROTATION_PLANE_READ_DEFAULT, \ + T_CDS_ROTATION_PLANE_WRITE_DEFAULT, \ + angle_plane_set, angle_sensor_read} + + +////////////////////////////////////////////////////////////////////////////////// +//// +////////////////////////////////////////////////////////////////////////////////// + +typedef struct { + UInt16 use_sensor1; + UInt16 use_sensor2; + UInt16 use_angle_plane; + + T_cds_in_rotation_sensor in_plane; + T_cds_angle_sensor rotation_plane; + + void (*set)(); // Pointer to calculation function + void (*read_sensors)(); + void (*update_registers)(); + +} T_rotation_sensor; + +#define T_CDS_ROTATION_SENSOR_DEFAULTS {0, 0, 0, \ + T_CDS_IN_ROTATION_SENSOR_DEFAULT, \ + T_CDS_ANGLE_SENSOR_DEFAULT, \ + rot_sensor_set, \ + sensor_read, \ + update_sensors_data_r} + +//Public functions +void rot_sensor_set(T_rotation_sensor *rs); +void sensor_read(T_rotation_sensor *rs); +void update_sensors_data_r(T_rotation_sensor *rs); +void angle_plane_set(T_cds_angle_sensor *rs); +void angle_sensor_read(T_cds_angle_sensor *as); +void in_plane_set(T_cds_in_rotation_sensor* rs); +void in_sensor_read1(T_cds_in_rotation_sensor *rs); +void in_sensor_read2(T_cds_in_rotation_sensor *rs); + + +//extern T_rotation_sensor rotation_sensor; + +#endif //XP_ROT_SENS_H diff --git a/Inu/Src/N12_Xilinx/profile_interrupt.c b/Inu/Src/N12_Xilinx/profile_interrupt.c new file mode 100644 index 0000000..207a1e5 --- /dev/null +++ b/Inu/Src/N12_Xilinx/profile_interrupt.c @@ -0,0 +1,36 @@ +/* + * profile_interrupt.c + * + * Created on: 6 . 2024 . + * Author: yura + */ + +#include "profile_interrupt.h" + +t_profile_interrupt profile_interrupt = T_PROFILE_INTERRUPT_DEFAULT; + + +void init_profile_interrupt(void) +{ + profile_interrupt.for_led1.bits.timer1 = 1; + profile_interrupt.for_led1.bits.timer2 = 1; + profile_interrupt.for_led1.bits.timer3 = 1; + profile_interrupt.for_led1.bits.timer4 = 1; + profile_interrupt.for_led1.bits.can = 1; + profile_interrupt.for_led1.bits.pwm = 1; + profile_interrupt.for_led1.bits.rsa = 1; + profile_interrupt.for_led1.bits.rsb = 1; + profile_interrupt.for_led1.bits.sync = 1; + + + profile_interrupt.for_led2.bits.timer1 = 1; + profile_interrupt.for_led2.bits.timer2 = 1; + profile_interrupt.for_led2.bits.timer3 = 1; + profile_interrupt.for_led2.bits.timer4 = 1; + profile_interrupt.for_led2.bits.can = 1; + profile_interrupt.for_led2.bits.pwm = 1; + profile_interrupt.for_led2.bits.rsa = 1; + profile_interrupt.for_led2.bits.rsb = 1; + profile_interrupt.for_led2.bits.sync = 1; + +} diff --git a/Inu/Src/N12_Xilinx/profile_interrupt.h b/Inu/Src/N12_Xilinx/profile_interrupt.h new file mode 100644 index 0000000..bf4db16 --- /dev/null +++ b/Inu/Src/N12_Xilinx/profile_interrupt.h @@ -0,0 +1,48 @@ +/* + * profile_interrupt.h + * + * Created on: 6 . 2024 . + * Author: yura + */ + +#ifndef SRC_N12_XILINX_PROFILE_INTERRUPT_H_ +#define SRC_N12_XILINX_PROFILE_INTERRUPT_H_ + + +typedef union { + unsigned int all; + struct { + unsigned int timer1: 1; + unsigned int timer2: 1; + unsigned int timer3: 1; + unsigned int timer4: 1; + + unsigned int sync: 1; + unsigned int can: 1; + unsigned int rsa: 1; + unsigned int rsb: 1; + + unsigned int pwm: 1; + unsigned int reserv: 7; + } bits; +} t_enable_profile; + + + + +typedef struct +{ + t_enable_profile for_led1; + t_enable_profile for_led2; + +} t_profile_interrupt; + +#define T_PROFILE_INTERRUPT_DEFAULT {0,0} + + + +extern t_profile_interrupt profile_interrupt; +void init_profile_interrupt(void); + + +#endif /* SRC_N12_XILINX_PROFILE_INTERRUPT_H_ */ diff --git a/Inu/Src/N12_Xilinx/xHWP.c b/Inu/Src/N12_Xilinx/xHWP.c new file mode 100644 index 0000000..8599431 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xHWP.c @@ -0,0 +1,11 @@ +#include "xHWP.h" + +#include "DSP281x_Examples.h" +#include "DSP281x_Device.h" +#include "x_parallel_bus.h" +#include "xerror.h" + + + + + diff --git a/Inu/Src/N12_Xilinx/xHWP.h b/Inu/Src/N12_Xilinx/xHWP.h new file mode 100644 index 0000000..efb1a9e --- /dev/null +++ b/Inu/Src/N12_Xilinx/xHWP.h @@ -0,0 +1,6 @@ +#ifndef _XHWP_H +#define _XHWP_H + + +#endif + diff --git a/Inu/Src/N12_Xilinx/xPeriphSP6_loader.c b/Inu/Src/N12_Xilinx/xPeriphSP6_loader.c new file mode 100644 index 0000000..ccd10f7 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xPeriphSP6_loader.c @@ -0,0 +1,561 @@ +#include "xPeriphSP6_loader.h" + +#include "DSP281x_Examples.h" +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "Spartan2E_Functions.h" +#include "TuneUpPlane.h" +#include "x_parallel_bus.h" +#include "xp_project.h" + + + +Byte byte; //used 8 most significant bits +Word word; +ControlReg controlReg; + +volatile AddrToSent addrToSent; +WordToReverse wordToReverse; +WordReversed wordReversed; + + +volatile int fail = 0; +volatile unsigned long length = 0; +volatile int tryNumb = 0; +int manufactorerAndProductID = 0; +static int countInMemWrite = 0; + +void initState(int adr_device){ + controlReg.all = 0x0000; + controlReg.bit.cs = 1; + controlReg.bit.rw = 1; + controlReg.bit.plane_addr = adr_device; + controlReg.bit.clock = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); +} + + + +void sendByte(void){ + int bitCnt = 8; + + controlReg.bit.clock = 0; + controlReg.bit.data = byte.bit.data; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + + while (bitCnt > 0) { + if (controlReg.bit.clock == 1) { + controlReg.bit.clock = 0; + controlReg.bit.data = byte.bit.data; + // bitCnt--; + } else { + controlReg.bit.clock = 1; + byte.all = byte.all << 1; + bitCnt--; + } + + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + } +} + + +void sendWord(void){ + int bitCnt = 16; + + controlReg.bit.clock = 0; + controlReg.bit.data = word.bit.data; +// controlReg.bit.data = word.bit.dataReceived; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + + while (bitCnt > 0) { + if (controlReg.bit.clock == 1) { + controlReg.bit.clock = 0; +// controlReg.bit.data = word.bit.dataReceived; + controlReg.bit.data = word.bit.data; + } else { + controlReg.bit.clock = 1; +// word.all = word.all >> 1; + word.all = word.all << 1; + bitCnt--; + } + + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + } +} + + + +void readByte(void){ + int bitCnt = 8; + controlReg.bit.clock = 0; + controlReg.bit.rw = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); +// byte.all = 0x0000; + while (bitCnt > 0) { + if (controlReg.bit.clock == 1) { + byte.all = byte.all << 1; + controlReg.all = i_ReadMemory(ADR_CONTR_REG_FOR_READ); + byte.bit.dataReceived = controlReg.bit.eeprom_read; + controlReg.bit.clock = 0; + bitCnt--; + } else { + controlReg.all = i_ReadMemory(ADR_CONTR_REG_FOR_READ); + controlReg.bit.clock = 1; + } + + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + } +} + +void readWord(void){ + int bitCnt = 16; + word.all = 0x0000; + while (bitCnt > 0) { + if (controlReg.bit.clock == 1) { + word.all = word.all << 1; + // word.all = word.all >> 1; + controlReg.all = i_ReadMemory(ADR_CONTR_REG_FOR_READ); + word.bit.dataReceived = controlReg.bit.eeprom_read; + // word.bit.data = controlReg.bit.eeprom_read; + controlReg.bit.clock = 0; + bitCnt--; + } else { + controlReg.all = i_ReadMemory(ADR_CONTR_REG_FOR_READ); + controlReg.bit.clock = 1; + } + + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + } +} + + + + +void WREN(void) { + controlReg.bit.cs = 0; + byte.all= 0x0600; + sendByte(); + + controlReg.bit.clock = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + controlReg.bit.cs = 1; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); +} + +void WRDI(void) { + controlReg.bit.cs = 0; + byte.all= 0x0400; + sendByte(); + + controlReg.bit.clock = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + controlReg.bit.cs = 1; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); +} + +void WRSR(void) { + controlReg.bit.cs = 0; + byte.all= 0x0100; + sendByte(); + + byte.all= 0x0200; + sendByte(); + + controlReg.bit.clock = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + controlReg.bit.cs = 1; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); +} + +void RDSR(void) { + controlReg.bit.cs = 0; + controlReg.bit.rw = 1; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + byte.all= 0x0500; + sendByte(); + + + readByte(); + + controlReg.bit.cs = 1; + controlReg.bit.rw = 1; + controlReg.bit.clock = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + +} + +void RDID(void) { + controlReg.bit.cs = 0; + controlReg.bit.rw = 1; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + if (manufactorerAndProductID == 0) + byte.all = 0x1500; + else + byte.all = 0x9F00; + sendByte(); + + + readByte(); + + controlReg.bit.cs = 1; + controlReg.bit.rw = 1; + controlReg.bit.clock = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + +} + +void ERASE(void) { + controlReg.bit.cs = 0; + if (manufactorerAndProductID == 0) + byte.all = 0x6200; + else + byte.all = 0xC700; + sendByte(); + + controlReg.bit.clock = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + controlReg.bit.cs = 1; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); +} + + + +void READ(void) { + controlReg.bit.cs = 0; + byte.all= 0x0300; + sendByte(); +} + +void PROGRAM(void) { + controlReg.bit.cs = 0; + byte.all= 0x0200; + sendByte(); +} + +void ADDR3bytes(FlashAddr flashAddr) { + int bitCnt = 24; + addrToSent.all= flashAddr.all; + addrToSent.all= addrToSent.all << 8; + + + controlReg.bit.clock = 0; + controlReg.bit.data = addrToSent.bit.data; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + + while (bitCnt > 0) { + if (controlReg.bit.clock == 1) { + controlReg.bit.clock = 0; + controlReg.bit.data = addrToSent.bit.data; + // bitCnt--; + } else { + controlReg.bit.clock = 1; + addrToSent.all = addrToSent.all << 1; + bitCnt--; + } + + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + } + +} + + + +void DataW256Bytes(volatile unsigned long addrToRead) { + unsigned long WordNum = 0; + + while (WordNum < 128) { + wordToReverse.all= i_ReadMemory(addrToRead + WordNum); + + wordReversed.bit.bit0 = wordToReverse.bit.bit7; + wordReversed.bit.bit1 = wordToReverse.bit.bit6; + wordReversed.bit.bit2 = wordToReverse.bit.bit5; + wordReversed.bit.bit3 = wordToReverse.bit.bit4; + wordReversed.bit.bit4 = wordToReverse.bit.bit3; + wordReversed.bit.bit5 = wordToReverse.bit.bit2; + wordReversed.bit.bit6 = wordToReverse.bit.bit1; + wordReversed.bit.bit7 = wordToReverse.bit.bit0; + + wordReversed.bit.bit8 = wordToReverse.bit.bit15; + wordReversed.bit.bit9 = wordToReverse.bit.bit14; + wordReversed.bit.bit10 = wordToReverse.bit.bit13; + wordReversed.bit.bit11 = wordToReverse.bit.bit12; + wordReversed.bit.bit12 = wordToReverse.bit.bit11; + wordReversed.bit.bit13 = wordToReverse.bit.bit10; + wordReversed.bit.bit14 = wordToReverse.bit.bit9; + wordReversed.bit.bit15 = wordToReverse.bit.bit8; + + word.all= wordReversed.all; + sendWord(); + WordNum++; + } + + controlReg.bit.clock = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + controlReg.bit.cs = 1; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + +} + +void DataR256Bytes(volatile unsigned long addrToRead) { + + unsigned long WordNum = 0; + + controlReg.bit.clock = 0; + controlReg.bit.rw = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); + + while (WordNum < 128) { + if ((addrToRead + WordNum) <= length) { + readWord(); + + wordToReverse.all= i_ReadMemory(addrToRead + WordNum); + + wordReversed.bit.bit0 = wordToReverse.bit.bit7; + wordReversed.bit.bit1 = wordToReverse.bit.bit6; + wordReversed.bit.bit2 = wordToReverse.bit.bit5; + wordReversed.bit.bit3 = wordToReverse.bit.bit4; + wordReversed.bit.bit4 = wordToReverse.bit.bit3; + wordReversed.bit.bit5 = wordToReverse.bit.bit2; + wordReversed.bit.bit6 = wordToReverse.bit.bit1; + wordReversed.bit.bit7 = wordToReverse.bit.bit0; + + wordReversed.bit.bit8 = wordToReverse.bit.bit15; + wordReversed.bit.bit9 = wordToReverse.bit.bit14; + wordReversed.bit.bit10 = wordToReverse.bit.bit13; + wordReversed.bit.bit11 = wordToReverse.bit.bit12; + wordReversed.bit.bit12 = wordToReverse.bit.bit11; + wordReversed.bit.bit13 = wordToReverse.bit.bit10; + wordReversed.bit.bit14 = wordToReverse.bit.bit9; + wordReversed.bit.bit15 = wordToReverse.bit.bit8; + + if (word.all != wordReversed.all) { + fail++; + WordNum =128; + } else { + fail = 0; + } + WordNum++; + } else { + // flashAddr.bit.addr2 = 0xFF; + WordNum =128; //finish flash writing + } + } + + controlReg.bit.cs = 1; + controlReg.bit.rw = 1; + controlReg.bit.clock = 0; + controlReg.bit.data = 0; + WriteMemory(ADR_CONTR_REG_FOR_WRITE, controlReg.all); +} + + + + + +void memWrite (unsigned int adr_device, volatile unsigned long adr, + volatile unsigned long adr_eeprom, volatile unsigned long size, unsigned long *ok_write, + unsigned long *write_error, unsigned long *repeat_error ) +{ + +/////////********************** +/////////before start procedure +/////////********************** + volatile int failNumb = 0; + volatile int checkNumb = 0; + volatile unsigned long addrToRead = 0; + volatile FlashAddr flashAddr; + + + Led1_Toggle(); + Led2_Toggle(); + + *ok_write= size; + + + countInMemWrite++; + + failNumb = 0; + checkNumb = 0; + addrToRead = adr; + length = size + addrToRead; + addrToRead = adr +8; + + *write_error = 0; + *repeat_error = 0; + + project.stop_parallel_bus(); + + initState(adr_device); + + + WREN(); + manufactorerAndProductID = 0; + RDID(); + if (byte.all != 0x1F00) { + manufactorerAndProductID = 1; + RDID(); + if ((byte.all != 0x2000) && (byte.all != 0xEF00)) *write_error = 5; //TODO: make defines with flash ID NAMES + } + WREN(); + WRSR(); + RDSR(); + + while (byte.all > 0) { + if (checkNumb < 3) { + DELAY_US(150); + RDSR(); //check that flash is not busy + +// byte.all = 1; // for test! + + if (failNumb > 1000) { +// if (failNumb > 30000) { //1000 // for test! + WREN(); + WRSR(); + RDSR(); + failNumb = 0; + checkNumb++; + } + failNumb++; + } else { + *write_error = 1; + *ok_write= 0; + failNumb = 1000; + byte.all = 0x0000; + tryNumb++; + } + } + + +// failNumb = 1000; // for test! + + if (failNumb < 1000) { + + failNumb = 0; + checkNumb = 0; + + + WREN(); + ERASE(); + RDSR(); + while (byte.all > 0) { + DELAY_US(70000); + RDSR(); //check that flash is not busy + if (failNumb > 1000) { + *ok_write= 0; + *write_error = 2; + byte.all = 0x0000; + tryNumb++; + } + failNumb++; + } + } + + if (failNumb < 1000) { + failNumb = 0; + + flashAddr.all = 0; + + + /////////********************** + /////////before start procedure finished + /////////********************** + + while (flashAddr.bit.addr2 < 0x08){ + WREN(); + PROGRAM(); + ADDR3bytes(flashAddr); + DataW256Bytes(addrToRead); + RDSR(); + Led1_Toggle(); + failNumb = 0; + checkNumb = 0; + while (byte.all != 0x0000){ + if (byte.all != 0x0200) { + if (checkNumb < 30) { + DELAY_US(3500); + RDSR(); //check that flash is not busy + checkNumb++; + } else { + byte.all = 0x0200; + } + + } else { //programming the page not completed, it's still "data ready" + if (failNumb < 20) { + WREN(); + PROGRAM(); //complete procedure again + ADDR3bytes(flashAddr); + DataW256Bytes(addrToRead); + RDSR(); + checkNumb = 0; + failNumb++; + } else { + *ok_write= addrToRead - adr-8; + *write_error = 3; + byte.all = 0x0000; + flashAddr.bit.addr2 = 0x08; + tryNumb++; + // asm (" ESTOP0"); //for save flash life + } + } + } + + if (failNumb < 20){ + READ(); + ADDR3bytes(flashAddr); + DataR256Bytes(addrToRead); + Led2_Toggle(); + if (fail ==0) { //if page written correctly, go to the next + if (flashAddr.bit.addr1 < 0xff) { + flashAddr.bit.addr1++; + } else { + flashAddr.bit.addr1 = 0; + flashAddr.bit.addr2++; + } + addrToRead += 0x00000080; + } else if (fail > 7) { + *ok_write= addrToRead - adr - 8; + *write_error = 4; + *repeat_error = fail; + flashAddr.bit.addr2 = 0x08; + tryNumb++; + // asm (" ESTOP0"); //for save flash life + } + } + + } + if ((*write_error != 0) && (tryNumb < 3) && (countInMemWrite < 3)) { + memWrite (adr_device, adr, adr_eeprom, size, ok_write, write_error, repeat_error ); + } + countInMemWrite = 0; + } + + + tryNumb =0; + + WriteMemory(ADR_CONTR_REG_FOR_WRITE, 0xffff); + WriteMemory(ADR_CONTR_REG_FOR_READ, 0xffff); + + project.reload_all_plates_without_reset_no_stop_error();// wait_start_cds + load_cfg + + + + WriteMemory(ADR_BUS_ERROR_READ, 0); + + if(i_ReadMemory(ADR_ERRORS_TOTAL_INFO)) // . + { + xerror(main_er_ID(3),(void *)0); + } + + + project.start_parallel_bus(); +} diff --git a/Inu/Src/N12_Xilinx/xPeriphSP6_loader.h b/Inu/Src/N12_Xilinx/xPeriphSP6_loader.h new file mode 100644 index 0000000..a9fa2bf --- /dev/null +++ b/Inu/Src/N12_Xilinx/xPeriphSP6_loader.h @@ -0,0 +1,133 @@ +#ifndef _XPERIPHSP6_LOADER_H +#define _XPERIPHSP6_LOADER_H + +typedef union{ + unsigned int all; + struct{ + unsigned int loader_on:1; + unsigned int cs:1; + unsigned int reserved0:2; + unsigned int rw:1; + unsigned int mode:1; + unsigned int reserved1:1; + unsigned int data:1; + unsigned int reserved2:1; + unsigned int clock:1; + unsigned int reserved3:1; + unsigned int plane_addr:4; + unsigned int eeprom_read:1; + }bit; +}ControlReg; + + +typedef union{ + unsigned long all; + struct{ + unsigned int addr0:8; + unsigned int addr1:8; + unsigned int addr2:8; + unsigned int reserved:8; + }bit; +}FlashAddr; + +typedef union{ + unsigned long all; + struct{ + unsigned int reserved:16; + unsigned int reserved1:15; + unsigned int data:1; + }bit; +}AddrToSent; + + +typedef union{ + unsigned int all; + struct{ + unsigned int reserved0:8; + unsigned int dataReceived:1; + unsigned int reserved1:6; + unsigned int data:1; + }bit; +}Byte; + +typedef union{ + unsigned int all; + struct{ + unsigned int dataReceived:1; + unsigned int reserved1:14; + unsigned int data:1; + }bit; +}Word; + +typedef union{ + unsigned int all; + struct{ + unsigned int bit0:1; + unsigned int bit1:1; + unsigned int bit2:1; + unsigned int bit3:1; + + unsigned int bit4:1; + unsigned int bit5:1; + unsigned int bit6:1; + unsigned int bit7:1; + + unsigned int bit8:1; + unsigned int bit9:1; + unsigned int bit10:1; + unsigned int bit11:1; + + unsigned int bit12:1; + unsigned int bit13:1; + unsigned int bit14:1; + unsigned int bit15:1; + + }bit; +}WordToReverse; + +typedef union{ + unsigned int all; + struct{ + unsigned int bit0:1; + unsigned int bit1:1; + unsigned int bit2:1; + unsigned int bit3:1; + + unsigned int bit4:1; + unsigned int bit5:1; + unsigned int bit6:1; + unsigned int bit7:1; + + unsigned int bit8:1; + unsigned int bit9:1; + unsigned int bit10:1; + unsigned int bit11:1; + + unsigned int bit12:1; + unsigned int bit13:1; + unsigned int bit14:1; + unsigned int bit15:1; + }bit; +}WordReversed; + + + +void memWrite (unsigned int adr_device, volatile unsigned long adr, + volatile unsigned long adr_eeprom, volatile unsigned long size, unsigned long *ok_write, + unsigned long *write_error, unsigned long *repeat_error ); + + +void RDID(void); +void RDSR(void); +void WREN(void); +void WRDI(void); +void WRSR(void); +void RDSR(void); +void ERASE(void); +void READ(void); +void PROGRAM(void); + + + +#endif + diff --git a/Inu/Src/N12_Xilinx/x_basic_types.h b/Inu/Src/N12_Xilinx/x_basic_types.h new file mode 100644 index 0000000..2991441 --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_basic_types.h @@ -0,0 +1,111 @@ +#ifndef X_BASIC_TYPES_H /* prevent circular inclusions */ +#define X_BASIC_TYPES_H /* by using protection macros */ + + + +#ifndef TRUE + #define TRUE 1 +#endif + +#ifndef FALSE + #define FALSE 0 +#endif + +#ifndef NULL + #define NULL 0 +#endif + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +typedef signed char Int8; +typedef signed int Int16; +typedef signed long Int32; +typedef signed long long Int64; + +typedef unsigned char UInt8; +typedef unsigned int UInt16; +typedef unsigned long UInt32; +typedef unsigned long long UInt64; + +#ifndef real +typedef float real; +#endif + + +typedef enum { + component_NotReady = 0x1, // , + component_Ready = 0x2, // , + component_Started = 0x4, // , , , component_Error + component_Error = 0x8, // . + component_Detected = 0x10, // , . . + component_NotFinded = 0x20, // , . + component_NotDetected = 0x40, // , . . + component_ErrorSBus = 0x80, // SBUS + component_ErrorPBus = 0x100 // PBUS +} T_component_status; + +typedef enum { + local_status_NotReady = 0x1, // , + local_status_Ok = 0x2, // + local_status_Error = 0x4 // . +} T_local_status; + + +typedef enum { + status_Success = 0, + status_Failed = 1 +} T_status_ReturnType; + + + +//typedef UInt16 T_Status; + + +#define HiWord(l)((UInt16)(((UInt32)(l)>>16)&0xFFFF)) +#define LoWord(l)((UInt16)( (UInt32)(l) &0xFFFF)) + +#define HiByte(w)((UInt8)(((UInt16)(w)>>8)&0xFF)) +#define LoByte(w)((UInt8)( (UInt16)(w) &0xFF)) + +#define Byte3(l)((UInt8)(((UInt32)(l)>>24)&0xFF)) +#define Byte2(l)((UInt8)(((UInt32)(l)>>16)&0xFF)) +#define Byte1(l)((UInt8)(((UInt32)(l)>> 8)&0xFF)) +#define Byte0(l)((UInt8)( (UInt32)(l) &0xFF)) + +#define Bit_UInt32(bit_index, value) ((UInt32)((((UInt32)(value)) >> (bit_index)) & 0x01)) + + +#define UInt16_Byte0(c) ((((UInt16)(c)) << 0) & 0x00ff) +#define UInt16_Byte1(c) ((((UInt16)(c)) << 8) & 0xff00) + +#define UInt32_Byte0(c) ((((UInt32)(c)) << 0) & 0x000000ff) +#define UInt32_Byte1(c) ((((UInt32)(c)) << 8) & 0x0000ff00) +#define UInt32_Byte2(c) ((((UInt32)(c)) << 16) & 0x00ff0000) +#define UInt32_Byte3(c) ((((UInt32)(c)) << 24) & 0xff000000) + +#define UInt32_LoWord(w) ((((UInt32)(w)) << 0) & 0x0000ffff) +#define UInt32_HiWord(w) ((((UInt32)(w)) << 16) & 0xffff0000) + +#define UInt16_Bit(index, value) ((((UInt16)(value)) & 0x0001) << (index)) +#define UInt32_Bit(index, value) ((((UInt32)(value)) & 0x00000001) << (index)) + + + +#define X_ASSERT_ESTOP0(useit) \ +{ \ + if(useit == TRUE) \ + { \ + X_Stop(); \ + asm (" ESTOP0"); \ + } \ +} + + +/*------------------------------------------------------------------------------ + Prototypes for the functions in x_basic_types.c +------------------------------------------------------------------------------*/ + +void X_Stop(); + +#endif diff --git a/Inu/Src/N12_Xilinx/x_int13.c b/Inu/Src/N12_Xilinx/x_int13.c new file mode 100644 index 0000000..fe5f9d1 --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_int13.c @@ -0,0 +1,218 @@ +#include "x_int13.h" + +#include <281xEvTimersInit.h> +#include + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "TuneUpPlane.h" +#include "xp_write_xpwm_time.h" +#include "params.h" +#include "pwm_test_lines.h" +#include "sync_tools.h" +#include "profile_interrupt.h" + +//Pointers to handler functions +void (*int13_handler)() = NULL; + + +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// + +//unsigned int enable_profile_led1_pwm = 1; +//unsigned int enable_profile_led2_pwm = 1; + + + +int InitXilinxSpartan2E(void (*int_handler)()) +{ + int err; + + project.controller.status = component_NotReady; + + err = load_xilinx_new(0x130000, SIZE_XILINX200); + if (err) + return err; + + err = test_xilinx_live(); + + +#ifdef ENABLE_XINTC_INT13 + if (int_handler) + XIntcInterruptSetup(int_handler); + else + err = 1; +#endif + + if (err == 0) + project.controller.status = component_Ready; + + return err; +} + +#pragma CODE_SECTION(XIntc_INT13_Handler,".fast_run2"); +interrupt void XIntc_INT13_Handler(void) +{ + static int l2; + + IER &= MINT13; // Set "global" priority + + if (xpwm_time.disable_sync_out==0) + { + if (xpwm_time.do_sync_out) + { + i_sync_pin_on(); + + #if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) + PWM_LINES_TK_17_ON; + #endif + + + } + else + { + i_sync_pin_off(); + + #if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) + PWM_LINES_TK_17_OFF; + #endif + + } + } + + if (xpwm_time.what_next_interrupt==PWM_LOW_LEVEL_INTERRUPT) + { + l2 = 1; + } + else + l2 = 0; + + + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.pwm && l2) + i_led1_on_off_special(1); +#endif + +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.pwm && l2) + i_led2_on_off_special(1); + +#endif + + + + + EINT; + + // Insert ISR Code here....... + + +// i_led2_on_off(1); +// IER &= 0xEFFF; + + if (project.controller.write.setup.bit.use_int13 == 1) + { + +// EnableInterrupts(); + // , , - +// stop_eva_timer1(); + + if(int13_handler) + { + int13_handler(); + } + // +//// start_eva_timer1(); +// DINT; +// +// IFR &= 0xefff; // ! +// IER |= M_INT13; + } + else + { +// IFR &= 0xefff; // ! +// IER |= M_INT13; + + } + + +// EnableInterrupts(); +// c = IFR; // & 0x0100 +// if (c) +// { +// count_lost_interrupt++; +// IFR &= 0xfeff; // ! +// } +// EnableInterrupts(); +// i_led2_on_off(0); + +// IFR &= 0xfeff; // ! +// EINT; + + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.pwm) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.pwm) + if (l2) + i_led2_on_off_special(0); +#endif + + +} + +int XIntcInterruptSetup(void (*int_handler)()) +{ + int result = 0; + + EALLOW; + + GpioMuxRegs.GPEMUX.bit.XNMI_XINT13_GPIOE2=1; +// GpioMuxRegs.GPEDIR.bit.GPIOE2 = 0; +// GpioDataRegs.GPESET.bit.GPIOE2 = 1; + + PieVectTable.XINT13=&XIntc_INT13_Handler; + int13_handler = int_handler; +// PieCtrlRegs.PIECRTL.bit. + XIntruptRegs.XNMICR.bit.POLARITY=0; + XIntruptRegs.XNMICR.bit.SELECT=1; + XIntruptRegs.XNMICR.bit.ENABLE=0; + +// Enable interrupt 13 + // IER |= M_INT13; + + project.controller.read.status.bit.int13_inited = 1; + +// EDIS; +// EnableInterrupts(); + + /* + * Start the interrupt controller in simulation mode. + */ + // result = XIntc_Start(Ptr, intc_mode_is_Sim); // sim mode +// if (!(result == status_Success)) + return result; + +// return status_Success; +} + +void start_int13_interrupt(void) +{ + // Enable interrupt 13 + IER |= M_INT13; +} + +void stop_int13_interrupt(void) +{ + // Disable interrupt 13 +// IER &= ~(M_INT13); + IER &= MINT13; // Set "global" priority +} diff --git a/Inu/Src/N12_Xilinx/x_int13.h b/Inu/Src/N12_Xilinx/x_int13.h new file mode 100644 index 0000000..ebe2b50 --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_int13.h @@ -0,0 +1,36 @@ +#ifndef _X_INT13_H +#define _X_INT13_H + +#include + + + + + +#if(C_PROJECT_TYPE==PROJECT_22220) +#define ENABLE_XINTC_INT13 1 +#endif + +#if(C_PROJECT_TYPE==PROJECT_BALZAM) +#define ENABLE_XINTC_INT13 1 +#endif + + +#if(C_PROJECT_TYPE==PROJECT_23550) +#define ENABLE_XINTC_INT13 1 +#endif + + + +////////////////////////////////////////// + + +int InitXilinxSpartan2E(void (*int_handler)()); + +int XIntcInterruptSetup(void (*int_handler)()); + +void start_int13_interrupt(void); +void stop_int13_interrupt(void); + + +#endif diff --git a/Inu/Src/N12_Xilinx/x_parallel_bus.c b/Inu/Src/N12_Xilinx/x_parallel_bus.c new file mode 100644 index 0000000..ea4001d --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_parallel_bus.c @@ -0,0 +1,238 @@ + +#include "x_parallel_bus.h" + +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "Spartan2E_Functions.h" +#include "xp_controller.h" +#include "xerror.h" + + +X_PARALLEL_BUS x_parallel_bus_project = X_PARALLEL_BUS_DEFAULTS; + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void x_parallel_bus_run_cmd(X_PARALLEL_BUS *v) +{ + volatile unsigned int d_wr; + + d_wr = ( (v->flags.bit.cmd_start & 0x1) << 15 ) | ( (v->setup.setup_error_count_read & 0xf) << 8 ) | ((v->setup.size_table - 1) & 0xff); + WriteMemory(ADR_PARALLEL_BUS_CMD, d_wr); + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + + + + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void x_parallel_bus_clear_table(X_PARALLEL_BUS *v) +{ + v->setup.size_table = -1; + v->setup.free_table = -1; + + v->flags.bit.cmd_start = 1; + x_parallel_bus_run_cmd(v); + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +int x_parallel_bus_check_free_table(X_PARALLEL_BUS *v) +{ + + if ( (v->setup.size_table + v->setup.tms_adr_data_start) <= v->setup.tms_adr_data_finish) + { + return 1; + } + return 0; + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void x_parallel_bus_add_table(X_PARALLEL_BUS *v) +{ + volatile unsigned int d_wr; + + if (v->flags.bit.started) + { + v->stop(v); + } + +// if (v->setup.size_table != 0) +// v->setup.size_table++; + if ( (v->setup.size_table + v->setup.tms_adr_data_start) > v->setup.tms_adr_data_finish) + { + // !!! + xerror(xparall_bus_er_ID(1),(void *)0); + return; + } + + d_wr = v->setup.size_table & 0xff; + WriteMemory(ADR_PARALLEL_BUS_ADR_TABLE, d_wr); + d_wr = ( (v->slave_addr & 0xf) << 12 ) | ( (v->reg_addr & 0xf) << 8 ) | (( (v->setup.tms_adr_data_start & 0xff) + v->setup.size_table) & 0xff); + WriteMemory(ADR_PARALLEL_BUS_SET_TABLE, d_wr); + + v->setup.free_table = (v->setup.tms_adr_data_finish - v->setup.tms_adr_data_start) - v->setup.size_table; + +// x_parallel_bus_run_cmd(v); + + + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void x_parallel_bus_start(X_PARALLEL_BUS *v) +{ + if (v->setup.size_table != 0) + { + v->flags.bit.error = 0; + v->flags.bit.cmd_start = 1; + v->flags.bit.was_started = 0; + + x_parallel_bus_run_cmd(v); + v->flags.bit.started = 1; + } +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void x_parallel_bus_stop(X_PARALLEL_BUS *v) +{ + v->flags.bit.cmd_start = 0; + x_parallel_bus_run_cmd(v); + v->flags.bit.started = 0; + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void x_parallel_bus_restart(X_PARALLEL_BUS *v) +{ + v->flags.bit.cmd_start = 0; + x_parallel_bus_run_cmd(v); + v->flags.bit.started = 0; + + v->flags.bit.error = 0; + v->flags.bit.cmd_start = 1; + x_parallel_bus_run_cmd(v); + v->flags.bit.started = 1; + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void x_parallel_bus_init(X_PARALLEL_BUS *v) +{ + if (v->flags.bit.init) + return; + + v->setup.size_table = 0;//-1; + v->setup.tms_adr_data_start = ADR_FIRST_FREE; + v->setup.tms_adr_data_finish = ADR_LAST_FREE; + v->setup.setup_error_count_read = MAX_WAIT_ERROR_PARALLEL_BUS; + v->setup.free_table = v->setup.tms_adr_data_finish - v->setup.tms_adr_data_start; + + + v->flags.all = 0; + + v->slave_addr = 0; + v->reg_addr = 0; + v->error_count_start = 0; + v->count_read = 0; + + v->stop(v); + + v->flags.bit.init = 1; + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void x_parallel_bus_read_status(X_PARALLEL_BUS *v) +{ +// volatile unsigned int d_rd; + static unsigned int prev_error = 0; + T_controller_read r_c; + +// check prev status? + if (v->flags.bit.error) + return; + +// read status bus + r_c.errors_buses.all = i_ReadMemory(ADR_BUS_ERROR_READ); + + v->flags.bit.count_error = r_c.errors_buses.bit.count_error_pbus;// ((d_rd >> 8) & 0xf); + v->flags.bit.slave_addr_error = r_c.errors_buses.bit.slave_addr_error; // ((d_rd >> 4) & 0xf); + + if ( v->flags.bit.count_error >= v->setup.setup_error_count_read ) + { + v->flags.bit.error = 1; + } + else + v->flags.bit.error = 0; + + if ((prev_error != v->flags.bit.error ) && (v->flags.bit.error)) + { + v->error_count_start++; + if (v->flags.bit.started) + { + v->flags.bit.was_started = 1; + x_parallel_bus_stop(v); + } + } + + prev_error = v->flags.bit.error; + + if ( v->flags.bit.started && (v->flags.bit.error == 0)) + v->count_read++; + + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(x_parallel_bus_read_one_data,".fast_run"); +void x_parallel_bus_read_one_data(X_PARALLEL_BUS *v) +{ +// read data from parallel bus + v->data_table_read = i_ReadMemory(ADR_FIRST_FREE + v->adr_table_read); +} +//////////////////////////////////////////////////////////////// + + + + diff --git a/Inu/Src/N12_Xilinx/x_parallel_bus.h b/Inu/Src/N12_Xilinx/x_parallel_bus.h new file mode 100644 index 0000000..493b96b --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_parallel_bus.h @@ -0,0 +1,127 @@ +#ifndef _X_PARALLEL_BUS_H +#define _X_PARALLEL_BUS_H + +#define MAX_WAIT_ERROR_PARALLEL_BUS 3 // . - + + + +typedef union { + unsigned int all; + struct { + unsigned int started:1; + unsigned int error:1; + unsigned int cmd_start:1; + unsigned int count_error:4; + unsigned int slave_addr_error:4; + unsigned int init:1; + unsigned int was_started:1; + unsigned int rezerv:3; + + } bit; +} X_PARALLEL_BUS_flags; + + +typedef struct { + unsigned int setup_error_count_read; // - + int size_table; // - ( add_table + unsigned int tms_adr_data_finish; // TMS , + unsigned int tms_adr_data_start; // TMS , + int free_table; // - +} X_PARALLEL_BUS_Setup; + +#define X_PARALLEL_BUS_Setup_DEFAULTS {MAX_WAIT_ERROR_PARALLEL_BUS, -1, 0, 0, -1} + +typedef struct { X_PARALLEL_BUS_flags flags; // + X_PARALLEL_BUS_Setup setup; // + unsigned int slave_addr; // . + unsigned int reg_addr; // . . + unsigned int error_count_start; // - + unsigned int count_read; // - + unsigned int adr_table_read; // = 0 _ (size_table-1) , + // adr_table_read + tms_adr_data_start + unsigned int data_table_read; // parallel bus, + + +// unsigned int error_count_write; // - +// unsigned int error_count_hold; // - + void (*clear_table)(); // Pointer to read function + void (*add_table)(); // Pointer to read function + void (*start)(); // Pointer to read function + void (*stop)(); // Pointer to read function + void (*restart)(); // Pointer to read function + void (*init)(); // Pointer to init function + void (*read_status)(); // Pointer to init function + void (*read_one_data)(); // Pointer to init function + int (*check_free_table)(); // Pointer to init function + + }X_PARALLEL_BUS; + + + +/* +// +#define TIME_OUT_SERIAL_BUS 10000 // max 65535 + + +#define CMD_SERIAL_BUS_READ 0x0000 +#define CMD_SERIAL_BUS_WRITE 0x8000 + +*/ + + +typedef X_PARALLEL_BUS *X_PARALLEL_BUS_handle; + +#define X_PARALLEL_BUS_DEFAULTS { 0, \ + X_PARALLEL_BUS_Setup_DEFAULTS, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + (void (*)(Uint32))x_parallel_bus_clear_table,\ + (void (*)(Uint32))x_parallel_bus_add_table,\ + (void (*)(Uint32))x_parallel_bus_start,\ + (void (*)(Uint32))x_parallel_bus_stop,\ + (void (*)(Uint32))x_parallel_bus_restart,\ + (void (*)(Uint32))x_parallel_bus_init,\ + (void (*)(Uint32))x_parallel_bus_read_status,\ + (void (*)(Uint32))x_parallel_bus_read_one_data,\ + (int (*)(Uint32))x_parallel_bus_check_free_table\ + } + + +void x_parallel_bus_clear_table(X_PARALLEL_BUS_handle); +void x_parallel_bus_add_table(X_PARALLEL_BUS_handle); +void x_parallel_bus_start(X_PARALLEL_BUS_handle); +void x_parallel_bus_stop(X_PARALLEL_BUS_handle); + +void x_parallel_bus_restart(X_PARALLEL_BUS_handle); +void x_parallel_bus_init(X_PARALLEL_BUS_handle); + +void x_parallel_bus_read_status(X_PARALLEL_BUS_handle); + +void x_parallel_bus_read_one_data(X_PARALLEL_BUS_handle); +int x_parallel_bus_check_free_table(X_PARALLEL_BUS_handle); + +extern X_PARALLEL_BUS x_parallel_bus_project; + + +#define read_pbus_value(bit,adr,res) {if (bit) res = i_ReadMemory(adr++); else res = 0; } +#define read_pbus_value_full(bit,adr,res) {res = i_ReadMemory(adr++); } + +#define read_pbus_adc_value(bit,adr,res) {if (bit) res = i_ReadMemory(adr++) & 0xfff; else res = 0; } +#define read_pbus_adc_value_full(bit,adr,res) {res = i_ReadMemory(adr++) & 0xfff; } + +// ver 2 +#define read_pbus_value_v2(bit,adr,res) {if (bit) { res = i_ReadMemory(adr); i_WriteMemory(adr++,0x0); } else res = 0; } +#define read_pbus_value_full_v2(bit,adr,res) {res = i_ReadMemory(adr); i_WriteMemory(adr++,0x0); } +#define read_pbus_value_full_v3(bit,adr,res) {res = i_ReadMemory(adr++); } + +#define read_pbus_adc_value_v2(bit,adr,res) {if (bit) { res = i_ReadMemory(adr) & 0xfff; i_WriteMemory(adr++,0x0);} else res = 0; } +#define read_pbus_adc_value_full_v2(bit,adr,res) {res = i_ReadMemory(adr) & 0xfff; i_WriteMemory(adr++,0x0); } + + + +#endif // end _X_PARALLEL_BUS_H + diff --git a/Inu/Src/N12_Xilinx/x_project_useit.h b/Inu/Src/N12_Xilinx/x_project_useit.h new file mode 100644 index 0000000..0ce3a1b --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_project_useit.h @@ -0,0 +1,7 @@ +#ifndef PROJECT_USEIT_H +#define PROJECT_USEIT_H + + + +#endif // end PROJECT_USEIT_H + diff --git a/Inu/Src/N12_Xilinx/x_serial_bus.c b/Inu/Src/N12_Xilinx/x_serial_bus.c new file mode 100644 index 0000000..fbc0dbc --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_serial_bus.c @@ -0,0 +1,319 @@ +#include "x_serial_bus.h" + +#include "DSP281x_Examples.h" +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "Spartan2E_Functions.h" +#include "TuneUpPlane.h" +#include "x_parallel_bus.h" +#include "xp_controller.h" + + + +X_SERIAL_BUS x_serial_bus_project = X_SERIAL_BUS_DEFAULTS; +T_controller_read r_c_sbus; + +static unsigned int counterSBWriteErrors = 0; + +/////////////////////////////////////////////////////// +// +// +// Example use: +// +// x_serial_bus_project.init(&x_serial_bus_project); +// +// x_serial_bus_project.reg_addr = 1; // adr memory in plate +// x_serial_bus_project.slave_addr = 6; // number plate +// +// x_serial_bus_project.read(&x_serial_bus_project); // read +// +// if (x_serial_bus_project.flags.bit.read_error==0) // check error +// { +// x_serial_bus_project.write_data = 1000; // write data +// x_serial_bus_project.write(&x_serial_bus_project); // make write +// } +// +// check return data: +// +// x_serial_bus_project.flags.bit.read_error - error +// x_serial_bus_project.flags.bit.write_error - error +// x_serial_bus_project.error_count_read - sum count read +// x_serial_bus_project.error_count_write - sum count write +/////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// Read from serial bus +//////////////////////////////////////////////////////////////// +int x_serial_bus_read(X_SERIAL_BUS *v) +{ + volatile unsigned int d_rd, d_wr; + unsigned int time_out = 0; + int err = 0; + + if (v->slave_addr>0xf) +// overfull adr - error? + return 1; +// check bus hold? + if (v->flags.bit.count_hold_bus) + // bus hold - error? + return 1; + +// test hold bus + v->flags.bit.count_hold_bus++; + if (v->flags.bit.count_hold_bus>1) + { + // parallel hold - error? + v->error_count_hold++; + return 1; + } + +// clear bus flags + d_rd = i_ReadMemory(ADR_SERIAL_BUS_DATA_READ); + +// read status bus +// d_rd = i_ReadMemory(ADR_BUS_ERROR_READ); + r_c_sbus.errors_buses.all = i_ReadMemory(ADR_BUS_ERROR_READ); + v->flags.bit.error = r_c_sbus.errors_buses.bit.err_sbus;// ((d_rd >> 14) & 0x1); + v->flags.bit.trans_compl = r_c_sbus.errors_buses.bit.sbus_updated;//((d_rd >> 15) & 0x1); + +// check status bits - all clear? +// if (v->flags.bit.error || v->flags.bit.trans_compl) + if (v->flags.bit.trans_compl) + { + v->flags.bit.read_error = 2; + v->error_count_read++; + return 1; + } + +// write cmd + d_wr = CMD_SERIAL_BUS_READ | ( (v->slave_addr & 0xf) << 4 ) | (v->reg_addr & 0xf); + WriteMemory(ADR_SERIAL_BUS_CMD, d_wr); + +// wait transmited data + v->flags.bit.trans_compl = 0; + v->flags.bit.error_timeout = 0; + time_out = 0; + + DELAY_US(200); + while (!v->flags.bit.trans_compl) + { +// read status bus +// d_rd = i_ReadMemory(ADR_BUS_ERROR_READ); + r_c_sbus.errors_buses.all = i_ReadMemory(ADR_BUS_ERROR_READ); + v->flags.bit.error = r_c_sbus.errors_buses.bit.err_sbus;//((d_rd >> 14) & 0x1); + v->flags.bit.trans_compl = r_c_sbus.errors_buses.bit.sbus_updated; //((d_rd >> 15) & 0x1); + +//check timeout + time_out++; + if (time_out>TIME_OUT_SERIAL_BUS) + { +// time out - error! + v->flags.bit.error_timeout = 1; + break; + } + + if (v->flags.bit.trans_compl) + { +// check error + if (v->flags.bit.error==0) + { +// data ready - read it! + d_rd = i_ReadMemory(ADR_SERIAL_BUS_DATA_READ); + v->read_data = d_rd; + } + } + } +// clear bus flags + d_rd = i_ReadMemory(ADR_SERIAL_BUS_DATA_READ); + if (v->flags.bit.error_timeout || v->flags.bit.error) + { + v->flags.bit.read_error = 1; + v->error_count_read++; + err = 1; + } + else + { + v->flags.bit.read_error = 0; + v->ok_count_read++; + } + +// unhold bus + v->flags.bit.count_hold_bus = 0; + v->count_timer = time_out; + + + return err; +} + + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// Write to serial bus +//////////////////////////////////////////////////////////////// +int x_serial_bus_write(X_SERIAL_BUS *v) +{ + volatile unsigned int d_rd, d_wr; + unsigned int time_out = 0; + int err = 0; + + if (v->slave_addr>0xf) +// overfull adr - error? + return 1; + +// check bus hold? + if (v->flags.bit.count_hold_bus) + return 1; + +// test hold bus + if (v->flags.bit.count_hold_bus<8) + v->flags.bit.count_hold_bus++; + + if (v->flags.bit.count_hold_bus>1) + { + // parallel hold - error? + v->error_count_hold++; + v->flags.bit.count_hold_bus = 0; + return 1; + } + + + //cycle to write several times if there was some errors + counterSBWriteErrors = 0; + do{ + +// clear bus flags + d_rd = i_ReadMemory(ADR_SERIAL_BUS_DATA_READ); + +// read status bus +// d_rd = i_ReadMemory(ADR_BUS_ERROR_READ); + r_c_sbus.errors_buses.all = i_ReadMemory(ADR_BUS_ERROR_READ); + v->flags.bit.error = r_c_sbus.errors_buses.bit.err_sbus;//((d_rd >> 14) & 0x1); + v->flags.bit.trans_compl = r_c_sbus.errors_buses.bit.sbus_updated; //((d_rd >> 15) & 0x1); + +// check status bits - all clear? +// if (v->flags.bit.error || v->flags.bit.trans_compl) + if (v->flags.bit.trans_compl) + { + v->flags.bit.read_error = 2; + v->error_count_write++; + v->flags.bit.count_hold_bus = 0; + return 1; + } + +// write data + WriteMemory(ADR_SERIAL_BUS_DATA_WRITE, v->write_data); + +// write cmd + d_wr = CMD_SERIAL_BUS_WRITE | ( (v->slave_addr & 0xf) << 4 ) | (v->reg_addr & 0xf); + WriteMemory(ADR_SERIAL_BUS_CMD, d_wr); + +// wait transmited data + v->flags.bit.trans_compl = 0; + v->flags.bit.error_timeout = 0; + time_out = 0; + + while (!v->flags.bit.trans_compl) + { +// read status bus + d_rd = i_ReadMemory(ADR_BUS_ERROR_READ); + v->flags.bit.error = ((d_rd >> 14) & 0x1); + v->flags.bit.trans_compl = ((d_rd >> 15) & 0x1); + +//check timeout + time_out++; + if (time_out>TIME_OUT_SERIAL_BUS) + { +// time out - error! + v->flags.bit.error_timeout = 1; + break; + } + + if (v->flags.bit.trans_compl) + { +// d_rd = i_ReadMemory(ADR_BUS_ERROR_READ); +// if (v->flags.bit.error==0) +// { +// } + break; + } + + } + + if (v->flags.bit.error) + { + counterSBWriteErrors++; // , + } + else + { + break; // , + } + + + }while(counterSBWriteErrors <= SB_ERROR_REPEATS); + + +// clear bus flags + d_rd = i_ReadMemory(ADR_SERIAL_BUS_DATA_READ); + + if (v->flags.bit.error_timeout || v->flags.bit.error) + { + v->flags.bit.write_error = 1; + v->error_count_write++; + err = 1; + } + else + v->ok_count_write++; + + v->count_timer = time_out; + +// unhold bus + v->flags.bit.count_hold_bus = 0; + return err; + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +void x_serial_bus_check(X_SERIAL_BUS *v) +{ + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + +void x_serial_bus_init(X_SERIAL_BUS *v) +{ + v->flags.all = 0; + + v->count_timer = 0; + v->read_data = 0x0; + v->write_data = 0x0; + v->reg_addr = 0; + v->slave_addr = 0; + + v->error_count_read = 0; + v->error_count_write = 0; + v->error_count_hold = 0; + v->ok_count_read = 0; + v->ok_count_write = 0; +} + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + +void x_serial_bus_clear_stat_error(X_SERIAL_BUS *v) +{ + v->error_count_read = 0; + v->error_count_write = 0; + v->error_count_hold = 0; + v->count_timer = 0; + + v->ok_count_read = 0; + v->ok_count_write = 0; + +} diff --git a/Inu/Src/N12_Xilinx/x_serial_bus.h b/Inu/Src/N12_Xilinx/x_serial_bus.h new file mode 100644 index 0000000..5d591fa --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_serial_bus.h @@ -0,0 +1,87 @@ +#ifndef _X_SERIAL_BUS_H +#define _X_SERIAL_BUS_H + +// +#define TIME_OUT_SERIAL_BUS 1000 //10000 // max 65535 + + +#define CMD_SERIAL_BUS_READ 0x0000 +#define CMD_SERIAL_BUS_WRITE 0x8000 + +#define SB_ERROR_REPEATS 7 + + + +typedef union { + unsigned int all; + struct { + unsigned int data_ready:1; + unsigned int trans_compl:1; + unsigned int error:1; + unsigned int write_error:1; + unsigned int read_error:2; + unsigned int error_timeout:1; + unsigned int count_hold_bus:3; + unsigned int rezerv:6; + } bit; +} X_SERIAL_BUS_flags; + + + +typedef struct { X_SERIAL_BUS_flags flags; // + unsigned int slave_addr; // . + unsigned int reg_addr; // . + unsigned int write_data; // + unsigned int read_data; // + unsigned int count_timer; // + unsigned int error_count_read; // - + unsigned int error_count_write; // - + unsigned int error_count_hold; // - + unsigned int ok_count_read; // - + unsigned int ok_count_write; // - + + int (*read)(); // Pointer to read function + int (*write)(); // Pointer to write function + void (*check)(); // Pointer to check function + void (*init)(); // Pointer to init function + void (*clear_stat)(); // Pointer to init function + }X_SERIAL_BUS; + + + + + +typedef X_SERIAL_BUS *X_SERIAL_BUS_handle; + +#define X_SERIAL_BUS_DEFAULTS { 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + (int (*)(Uint32))x_serial_bus_read,\ + (int (*)(Uint32))x_serial_bus_write,\ + (void (*)(Uint32))x_serial_bus_check,\ + (void (*)(Uint32))x_serial_bus_init,\ + (void (*)(Uint32))x_serial_bus_clear_stat_error\ + } + + +int x_serial_bus_read(X_SERIAL_BUS_handle); +int x_serial_bus_write(X_SERIAL_BUS_handle); +void x_serial_bus_check(X_SERIAL_BUS_handle); +void x_serial_bus_init(X_SERIAL_BUS_handle); +void x_serial_bus_clear_stat_error(X_SERIAL_BUS_handle); + +void xPeriphReadyCheck(void); + +extern X_SERIAL_BUS x_serial_bus_project; + + +#endif // end _X_SERIAL_BUS_H + diff --git a/Inu/Src/N12_Xilinx/x_wdog.c b/Inu/Src/N12_Xilinx/x_wdog.c new file mode 100644 index 0000000..c6a6501 --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_wdog.c @@ -0,0 +1,23 @@ +/* + * x_wdog.c + * + * Created on: 10 . 2020 . + * Author: yura + */ + +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" + + +void stop_wdog(void) +{ + i_WriteMemory(ADR_PWM_WDOG, 0x000e); +} + +void start_wdog(void) +{ + i_WriteMemory(ADR_PWM_WDOG, 0x800f); +} + + + diff --git a/Inu/Src/N12_Xilinx/x_wdog.h b/Inu/Src/N12_Xilinx/x_wdog.h new file mode 100644 index 0000000..b5e61f6 --- /dev/null +++ b/Inu/Src/N12_Xilinx/x_wdog.h @@ -0,0 +1,18 @@ +/* + * x_wdog.h + * + * Created on: 10 . 2020 . + * Author: yura + */ + +#ifndef _X_WDOG_H_ +#define _X_WDOG_H_ + + + +void stop_wdog(void); +void start_wdog(void); + + + +#endif /* _X_WDOG_H_ */ diff --git a/Inu/Src/N12_Xilinx/xerror.c b/Inu/Src/N12_Xilinx/xerror.c new file mode 100644 index 0000000..b3fdc10 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xerror.c @@ -0,0 +1,428 @@ +#include "xerror.h" + + + +/* +#pragma CODE_SECTION(xassert,".fast_run"); +int xassert(unsigned int er, unsigned int er_ID, void *CallBackRef){ + if(er) + return xerror(er_ID, CallBackRef); + return 0; +} +*/ + +int xerror(unsigned int er_ID, void *CallBackRef) +{ + + switch(er_ID){ + + +//main + + // error test Xilinx. Xilinx dead. + case main_er_ID(1): XERROR_DEBUG_MODE; break; + +// , + case main_er_ID(2): XERROR_DEBUG_MODE; break; + +// err0 + case main_er_ID(3): XERROR_DEBUG_MODE; break; + +//xtools + + // error load Xilinx. faulse level on line INIT + case xtools_er_ID(1): XERROR_DEBUG_MODE; break; + + // error load Xilinx. faulse level on line DONE + case xtools_er_ID(2): XERROR_DEBUG_MODE; break; + + + +//xseeprom + + //error write to serial eeprom. xseeprom_write_all + case xseeprom_er_ID(1): XERROR_DEBUG_MODE; break; + + // error read from serial eeprom. xseeprom_read_all + case xseeprom_er_ID(2): XERROR_DEBUG_MODE; break; + + // error compare serial eeprom. + case xseeprom_er_ID(3): XERROR_DEBUG_MODE; break; + + +//serialBus + + //error write to serial bus + case xserial_bus_er_ID(1): XERROR_DEBUG_MODE; break; + //error find plates on serial bus + case xserial_bus_er_ID(2): XERROR_DEBUG_MODE; break; + +//PBus + + //error setup to parall bus, overfull size pbus array! + case xparall_bus_er_ID(1): XERROR_DEBUG_MODE; break; + //error run parall bus! + case xparall_bus_er_ID(2): XERROR_DEBUG_MODE; break; + + default: XERROR_DEBUG_MODE; break; + + } + + + + return 1; + +} + + + + + +/* +int xerror(unsigned int er_ID, void *CallBackRef){ + + unsigned int er=1; + unsigned int Value; + static int count_error=0; + + // XIn_Plane XIn_Plane0; + +// if(x_mask_er) +// return 0; + +// asm (" ESTOP0"); + + switch(er_ID){ + + // error write/read + case main_er_ID(1): XERROR_DEBUG_MODE; xReady_reg_reset(); break; + + // error in write/read + //case xinput_new_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY +// case xinput_new_er_ID(2): XERROR_DEBUG_MODE; break; + case xinput_new_er_ID(2): XERROR_DEBUG_MODE_INPUT_NEW_NOT_READY; if (XERROR_DEBUG_LEVEL==1) {er=0;} break; + + // config information is empty + case xinput_new_er_ID(3): XERROR_DEBUG_MODE; break; + + // bad input parameter + case xinput_new_er_ID(4): XERROR_DEBUG_MODE; break; + + // too large parameter max,high or low + case xinput_new_er_ID(5): XERROR_DEBUG_MODE; break; + + // High_value must be more 0 + case xinput_new_er_ID(6): XERROR_DEBUG_MODE; break; + + // too large parameter Max_value + case xinput_new_er_ID(7): XERROR_DEBUG_MODE; break; + + // triggeing data is NOT READY + case xinput_new_er_ID(8): XERROR_DEBUG_MODE; break; + + // test write/read is failure + case xinput_new_er_ID(9): XERROR_DEBUG_MODE; break; + + + + // error in write/read + //case xintc_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + case xintc_er_ID(2): XERROR_DEBUG_MODE; break; + + // unknown mode + case xintc_er_ID(3): XERROR_DEBUG_MODE; break; + + // Id is not exist + case xintc_er_ID(4): XERROR_DEBUG_MODE; break; + + // Handle is Null + case xintc_er_ID(5): XERROR_DEBUG_MODE; break; + + //self-test is failure because mode is Real or + //simulate of interrupt is failure because mode is Real + case xintc_er_ID(6): XERROR_DEBUG_MODE; break; + + //self-test is failure + case xintc_er_ID(7): XERROR_DEBUG_MODE; break; + + + + // error in write/read + case xserial_bus_er_ID(1): //XERROR_DEBUG_MODE; + count_error++; + Value=((XSerial_bus *)CallBackRef)->Adr.bit.AdrPlane; + break; + + // structure is NOT READY + case xserial_bus_er_ID(2): XERROR_DEBUG_MODE; break; + + // config information is empty + case xserial_bus_er_ID(3): XERROR_DEBUG_MODE; break; + + // PicoBlaze is not found in hardware + case xserial_bus_er_ID(4): XERROR_DEBUG_MODE; break; + + // serial bus is hang up + case xserial_bus_er_ID(5): XERROR_DEBUG_MODE; write_memory(((XSerial_bus *)CallBackRef)->BaseAddress+adr_Xserial_iar_ipr,0xffff); break; + + + + // error in write/read + case xserial_bus_simple_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + case xserial_bus_simple_er_ID(2): XERROR_DEBUG_MODE; break; + + // config information is empty + case xserial_bus_simple_er_ID(3): XERROR_DEBUG_MODE; break; + + // self-test is failure + case xserial_bus_simple_er_ID(4): XERROR_DEBUG_MODE; break; + + // tune is failure + case xserial_bus_simple_er_ID(5): XERROR_DEBUG_MODE; break; + + + + // error in write/read + //case xsoft_fifo_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + case xsoft_fifo_er_ID(2): XERROR_DEBUG_MODE; break; + + + + // error in write/read + //case xtimer_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + case xtimer_er_ID(2): XERROR_DEBUG_MODE; break; + + // config information is empty + case xtimer_er_ID(3): XERROR_DEBUG_MODE; break; + + // self-test is failure + case xtimer_er_ID(4): XERROR_DEBUG_MODE; break; + + // start is failure + case xtimer_er_ID(5): XERROR_DEBUG_MODE; break; + + // value_us must be more 0 + case xtimer_er_ID(6): XERROR_DEBUG_MODE; break; + + // hw is't compatible with software: RangeCount_Is too small or time_us too large + case xtimer_er_ID(7): XERROR_DEBUG_MODE; break; + + + + // error in write/read + //case xplane_hwp_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + case xplane_hwp_er_ID(2): XERROR_DEBUG_MODE_HWP_NOT_READY; if (XERROR_DEBUG_LEVEL==1) {er=0;} break; + + // config information is empty or bad + case xplane_hwp_er_ID(3): XERROR_DEBUG_MODE; break; + + // test er_line is failure + case xplane_hwp_er_ID(4): XERROR_DEBUG_MODE; break; + + // error in write/read in dac + case xplane_hwp_er_ID(5): XERROR_DEBUG_MODE; break; + + // no error test is failure + case xplane_hwp_er_ID(6): XERROR_DEBUG_MODE; break; + + // watch timer test is failure + case xplane_hwp_er_ID(7): XERROR_DEBUG_MODE; break; + + // reference test is failure + case xplane_hwp_er_ID(8): XERROR_DEBUG_MODE; break; + + // define voltage test is failure + case xplane_hwp_er_ID(9): XERROR_DEBUG_MODE; break; + + // voltage test is failure + case xplane_hwp_er_ID(10): XERROR_DEBUG_MODE; break; + + + + // error in write/read + //case xtools_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + //case xtools_er_ID(2): XERROR_DEBUG_MODE; break; + + // config information is empty + //case xtools_er_ID(3): XERROR_DEBUG_MODE; break; + + // bad input parameter Time_Unit_Is + case xtools_er_ID(4): XERROR_DEBUG_MODE; break; + + // bad input parameter Time_Unit_Is + case xtools_er_ID(5): XERROR_DEBUG_MODE; break; + + // too large parameter Value + case xtools_er_ID(6): XERROR_DEBUG_MODE; break; + + // faulse level on line INIT + case xtools_er_ID(7): XERROR_DEBUG_MODE; break; + + // faulse level on line DONE + case xtools_er_ID(8): XERROR_DEBUG_MODE; break; + + + + + // error in write/read + //case xtk_plane_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + case xtk_plane_er_ID(2): XERROR_DEBUG_MODE_TK_NOT_READY; if (XERROR_DEBUG_LEVEL==1) {er=0;} break; + + // config information is empty + case xtk_plane_er_ID(3): XERROR_DEBUG_MODE; ((XTk_Plane *)CallBackRef)->IsReady=0; break; + + // self-test is failure + case xtk_plane_er_ID(4): XERROR_DEBUG_MODE; ((XTk_Plane *)CallBackRef)->IsReady=0; break; + + // no connection on serial bus + case xtk_plane_er_ID(5): XERROR_DEBUG_MODE; ((XTk_Plane *)CallBackRef)->IsReady=0; if (XERROR_DEBUG_LEVEL==1) {er=0;} break; + + // test Tk_Bus is failure + case xtk_plane_er_ID(6): XERROR_DEBUG_MODE; ((XTk_Plane *)CallBackRef)->IsReady=0; break; + + + + // error in write/read + //case xtk_plane_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + case xin_plane_er_ID(2): XERROR_DEBUG_MODE_IN_NOT_READY; if (XERROR_DEBUG_LEVEL==1) {er=0;} break; + + // config information is empty + case xin_plane_er_ID(3): XERROR_DEBUG_MODE; ((XIn_Plane *)CallBackRef)->IsReady=0; break; + + // self-test is failure + case xin_plane_er_ID(4): XERROR_DEBUG_MODE; ((XIn_Plane *)CallBackRef)->IsReady=0; break; + + // no connection on serial bus + case xin_plane_er_ID(5): XERROR_DEBUG_MODE; ((XIn_Plane *)CallBackRef)->IsReady=0; if (XERROR_DEBUG_LEVEL==1) {er=0;}; break; + + // bad configuration of InputNew + case xin_plane_er_ID(6): XERROR_DEBUG_MODE; ((XIn_Plane *)CallBackRef)->IsReady=0; break; + + // error in set Real mode + case xin_plane_er_ID(7): XERROR_DEBUG_MODE; ((XIn_Plane *)CallBackRef)->IsReady=0; break; + + + + // error in write/read + //case xtk_plane_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + case xout_plane_er_ID(2): XERROR_DEBUG_MODE_OUT_NOT_READY; if (XERROR_DEBUG_LEVEL==1) {er=0;} break; + + // config information is empty + case xout_plane_er_ID(3): XERROR_DEBUG_MODE; ((XOut_Plane *)CallBackRef)->IsReady=0; break; + + // self-test is failure + case xout_plane_er_ID(4): XERROR_DEBUG_MODE; ((XOut_Plane *)CallBackRef)->IsReady=0; break; + + // no connection on serial bus + case xout_plane_er_ID(5): XERROR_DEBUG_MODE; ((XOut_Plane *)CallBackRef)->IsReady=0; if (XERROR_DEBUG_LEVEL==1) {er=0;}; break; + + // bad configuration of InputNew + //case xout_plane_er_ID(6): XERROR_DEBUG_MODE; break; + + // error in set Real mode + //case xout_plane_er_ID(7): XERROR_DEBUG_MODE; break; + + + + // error in write/read + //case xspeed_sensor_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + //case xspeed_sensor_er_ID(2): XERROR_DEBUG_MODE; break; + + // config information is empty + //case xspeed_sensor_er_ID(3): XERROR_DEBUG_MODE; break; + + // self-test is failure + //case xspeed_sensor_er_ID(4): XERROR_DEBUG_MODE; break; + + // bad configuration of InputNew + case xspeed_sensor_er_ID(5): XERROR_DEBUG_MODE; break; + + // too large parameter Filtr_Max + case xspeed_sensor_er_ID(6): XERROR_DEBUG_MODE; break; + + // too large parameter Lenth_Min + //case xspeed_sensor_er_ID(7): XERROR_DEBUG_MODE; break; + + // compare predefine macros is failure + case xspeed_sensor_er_ID(8): XERROR_DEBUG_MODE; break; + + // maximum of reriod is small + case xspeed_sensor_er_ID(9): XERROR_DEBUG_MODE; break; + + // maximum of reriod is small => overrun count_max_by_hw + case xspeed_sensor_er_ID(10): XERROR_DEBUG_MODE; break; + + // count_max_by_sw must be less count_max_by_hw + case xspeed_sensor_er_ID(11): XERROR_DEBUG_MODE; break; + + + + + // error in write/read + //case xcontroller_plane_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + //case xcontroller_plane_er_ID(2): XERROR_DEBUG_MODE; break; + + // config information is failure + case xcontroller_plane_er_ID(3): XERROR_DEBUG_MODE; break; + + // self-test is failure + //case xcontroller_plane_er_ID(4): XERROR_DEBUG_MODE; break; + + + + + + // error in write/read + //case xplane_analog_er_ID(1): XERROR_DEBUG_MODE; break; + + // structure is NOT READY + case xplane_analog_er_ID(2): XERROR_DEBUG_MODE_ANALOG_NOT_READY; if (XERROR_DEBUG_LEVEL==1) {er=0;} break; + + // config information is empty or bad + case xplane_analog_er_ID(3): XERROR_DEBUG_MODE; break; + + // test er_line is failure + // case xplane_analog_er_ID(4): XERROR_DEBUG_MODE; break; + + // error in write/read in dac + case xplane_analog_er_ID(5): XERROR_DEBUG_MODE_ANALOG; break; // xplane_analog_chanals_init(&XPlane_Analog_Chanals0); break; + + + + + default: break; + } + + x_er|=er; + xReady_reg_update(); + + return 1; +} + +*/ + + diff --git a/Inu/Src/N12_Xilinx/xerror.h b/Inu/Src/N12_Xilinx/xerror.h new file mode 100644 index 0000000..5694774 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xerror.h @@ -0,0 +1,66 @@ +#ifndef X_ERROR_H +#define X_ERROR_H + +#define XERROR_DEBUG_LEVEL 2 + +#define XERROR_DEBUG_MODE_ANALOG asm (" NOP") + + +#if (XERROR_DEBUG_LEVEL == 0) + #define XERROR_DEBUG_MODE asm (" NOP") +#else + #define XERROR_DEBUG_MODE asm (" ESTOP0") +#endif + + +#if (XERROR_DEBUG_LEVEL <= 1) + #define XERROR_DEBUG_MODE_TK_NOT_READY asm (" NOP") + #define XERROR_DEBUG_MODE_IN_NOT_READY asm (" NOP") + #define XERROR_DEBUG_MODE_OUT_NOT_READY asm (" NOP") + #define XERROR_DEBUG_MODE_HWP_NOT_READY asm (" NOP") + #define XERROR_DEBUG_MODE_ANALOG_NOT_READY asm (" NOP") + #define XERROR_DEBUG_MODE_INPUT_NEW_NOT_READY asm (" NOP") +#else + #define XERROR_DEBUG_MODE_TK_NOT_READY asm (" ESTOP0") + #define XERROR_DEBUG_MODE_IN_NOT_READY asm (" ESTOP0") + #define XERROR_DEBUG_MODE_OUT_NOT_READY asm (" ESTOP0") + #define XERROR_DEBUG_MODE_HWP_NOT_READY asm (" ESTOP0") + #define XERROR_DEBUG_MODE_ANALOG_NOT_READY asm (" ESTOP0") + #define XERROR_DEBUG_MODE_INPUT_NEW_NOT_READY asm (" ESTOP0") + #define XERROR_DEBUG_MODE_HWP_ERROR_SET_LEVEL_PROTECT asm (" ESTOP0") +#endif + + + + #define main_er_ID(er_ID) ( 0 + er_ID) + #define xseeprom_er_ID(er_ID) (100 + er_ID) + #define xtools_er_ID(er_ID) (200 + er_ID) + #define xserial_bus_er_ID(er_ID) (300 + er_ID) + #define xparall_bus_er_ID(er_ID) (400 + er_ID) + #define xplane_hwp_er_ID(er_ID) (700 + er_ID) + #define xtk_plane_er_ID(er_ID) (900 + er_ID) + #define xin_plane_er_ID(er_ID) (1000 + er_ID) + +/* + #define xinput_new_er_ID(er_ID) (100 + er_ID) + #define xintc_er_ID(er_ID) (200 + er_ID) + #define xserial_bus_er_ID(er_ID) (300 + er_ID) + #define xserial_bus_simple_er_ID(er_ID) (400 + er_ID) + #define xsoft_fifo_er_ID(er_ID) (500 + er_ID) + #define xtimer_er_ID(er_ID) (600 + er_ID) + #define xplane_hwp_er_ID(er_ID) (700 + er_ID) + #define xtk_plane_er_ID(er_ID) (900 + er_ID) + #define xin_plane_er_ID(er_ID) (1000 + er_ID) + #define xout_plane_er_ID(er_ID) (1100 + er_ID) + #define xspeed_sensor_er_ID(er_ID) (1200 + er_ID) + #define xcontroller_plane_er_ID(er_ID) (1300 + er_ID) + #define xplane_analog_er_ID(er_ID) (1400 + er_ID) +*/ + int xerror(unsigned int er_ID, void *CallBackRef); +// int xassert(unsigned int er, unsigned int er_ID, void *CallBackRef); + +// #define XERROR_DEBUG_MODE_HWP_NOT_READY asm (" ESTOP0") + +void xPeriphErrReset(void); + +#endif //X_ERROR_H diff --git a/Inu/Src/N12_Xilinx/xp_adc.c b/Inu/Src/N12_Xilinx/xp_adc.c new file mode 100644 index 0000000..4df1e8e --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_adc.c @@ -0,0 +1,643 @@ + +#include "xp_adc.h" + +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "TuneUpPlane.h" +#include "x_parallel_bus.h" +#include "x_serial_bus.h" +#include "xp_tools.h" +#include "xerror.h" + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void adc_init(T_adc *v) +{ + int old_started = 0; + unsigned int i, k; + + if (v->useit == 0) + { + clear_adr_sync_table(v->plane_address); + return ; + } + set_adr_sync_table(v->plane_address); + + if (x_parallel_bus_project.flags.bit.init==0) + x_parallel_bus_project.init(&x_parallel_bus_project); + + + old_started = x_parallel_bus_project.flags.bit.started; + + if (x_parallel_bus_project.flags.bit.started) + x_parallel_bus_project.stop(&x_parallel_bus_project); + + + x_parallel_bus_project.slave_addr = v->plane_address; + + // for (i=0;isetup_pbus.count_elements_pbus;i++) + for (i=0;i<16;i++) + { + if (v->setup_pbus.use_reg_in_pbus.all & (1<adr_pbus.adr_table[i] = x_parallel_bus_project.setup.size_table; + x_parallel_bus_project.add_table(&x_parallel_bus_project); + x_parallel_bus_project.reg_addr++; + x_parallel_bus_project.setup.size_table++; + } + else + { + // !!! + xerror(xparall_bus_er_ID(1),(void *)0); + v->setup_pbus.use_reg_in_pbus.all &= (~(1<useit == 0) + return 0; + + adc_read_sbus(v); + adc_read_pbus(v); + return 0; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + +int adc_write_all(T_adc *v) +{ + if (v->useit == 0) + return 0; + + adc_write_sbus(v); + adc_write_pbus(v); + return 0; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int adc_write_sbus(T_adc *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 test reg + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.test; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + + if (v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + + +//6 protect_error + if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) + v->write.sbus.protect_error.bit.err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + + + + } + +//// + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int adc_write_pbus(T_adc *v) +{ + if (v->useit == 0) + return 0; + + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int adc_read_sbus(T_adc *v) +{ + + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 test + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.test = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//14 id_plate + x_serial_bus_project.reg_addr = 14; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.id_plate.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->type_cds_xilinx = v->read.type_cds_xilinx; + if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) // SP6 + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + + + if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP2) + { + //6 protect_error + v->read.sbus.protect_error.all = 0; + //7 lock_status_error + v->read.sbus.lock_status_error.all = 0; + } + else // TYPE_CDS_XILINX_SP6 + { + //6 protect_error + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + //7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + } +/////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +#pragma CODE_SECTION(adc_read_pbus,".fast_run"); +int adc_read_pbus(T_adc *v) +{ + unsigned int i,k; + + if (v->useit == 0) + return 0; + + if (v->status & (component_Started | component_Ready | component_Error | component_ErrorSBus)) + { + + + for (i=0,k=0;isetup_pbus.count_elements_pbus;i++) + { + if (v->setup_pbus.use_reg_in_pbus.all & (1<adr_pbus.adr_table[k]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.adc_value[i] = (x_parallel_bus_project.data_table_read & 0xfff); // , .. . + k++; + } + else + { + v->read.pbus.adc_value[i] = 0xffff; + } + } + + } + else + { + + v->read.pbus.adc_value[0] = 0; + v->read.pbus.adc_value[1] = 0; + v->read.pbus.adc_value[2] = 0; + v->read.pbus.adc_value[3] = 0; + v->read.pbus.adc_value[4] = 0; + v->read.pbus.adc_value[5] = 0; + v->read.pbus.adc_value[6] = 0; + v->read.pbus.adc_value[7] = 0; + v->read.pbus.adc_value[8] = 0; + v->read.pbus.adc_value[9] = 0; + v->read.pbus.adc_value[10] = 0; + v->read.pbus.adc_value[11] = 0; + v->read.pbus.adc_value[12] = 0; + v->read.pbus.adc_value[13] = 0; + v->read.pbus.adc_value[14] = 0; + v->read.pbus.adc_value[15] = 0; + + } + return 0; +} + + + +//#define read_adc_value(bit,adr,res) {if (bit) res = i_ReadMemory(adr++) & 0xfff; else res = 0xffff; } +//#define read_adc_value(bit,adr,res) {if (bit) res = i_ReadMemory(adr++) & 0xfff; } +//#define read_adc_value_full(bit,adr,res) {res = i_ReadMemory(adr++) & 0xfff; } + + + +#pragma CODE_SECTION(adc_read_pbus_without_cycle,".fast_run"); +int adc_read_pbus_without_cycle(T_adc *v) +{ + unsigned long adr_adc; + unsigned int a_adc,i; + + if (v->useit == 0) + return 0; + + if (v->status & (component_Started | component_Ready | component_Error | component_ErrorSBus)) + { +//i_led2_on(); + adr_adc = v->adr_pbus.adr_table[0] + ADR_FIRST_FREE; +// a_adc = 0; +/* + v->read.pbus.adc_value[0] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[1] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[2] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[3] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[4] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[5] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[6] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[7] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[8] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[9] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[10] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[11] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[12] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[13] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[14] = i_ReadMemory(ADR_FIRST_FREE); + v->read.pbus.adc_value[15] = i_ReadMemory(ADR_FIRST_FREE); +*/ + +// if (v->setup_pbus.use_reg_in_pbus.all == 0xffff) +// { + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg0,adr_adc,v->read.pbus.adc_value[0]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg1,adr_adc,v->read.pbus.adc_value[1]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg2,adr_adc,v->read.pbus.adc_value[2]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg3,adr_adc,v->read.pbus.adc_value[3]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg4,adr_adc,v->read.pbus.adc_value[4]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg5,adr_adc,v->read.pbus.adc_value[5]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg6,adr_adc,v->read.pbus.adc_value[6]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg7,adr_adc,v->read.pbus.adc_value[7]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg8,adr_adc,v->read.pbus.adc_value[8]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg9,adr_adc,v->read.pbus.adc_value[9]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg10,adr_adc,v->read.pbus.adc_value[10]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg11,adr_adc,v->read.pbus.adc_value[11]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg12,adr_adc,v->read.pbus.adc_value[12]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg13,adr_adc,v->read.pbus.adc_value[13]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg14,adr_adc,v->read.pbus.adc_value[14]); + read_pbus_adc_value_full(v->setup_pbus.use_reg_in_pbus.bit.reg15,adr_adc,v->read.pbus.adc_value[15]); +// } +// else +// { +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg0,adr_adc,v->read.pbus.adc_value[0]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg1,adr_adc,v->read.pbus.adc_value[1]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg2,adr_adc,v->read.pbus.adc_value[2]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg3,adr_adc,v->read.pbus.adc_value[3]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg4,adr_adc,v->read.pbus.adc_value[4]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg5,adr_adc,v->read.pbus.adc_value[5]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg6,adr_adc,v->read.pbus.adc_value[6]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg7,adr_adc,v->read.pbus.adc_value[7]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg8,adr_adc,v->read.pbus.adc_value[8]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg9,adr_adc,v->read.pbus.adc_value[9]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg10,adr_adc,v->read.pbus.adc_value[10]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg11,adr_adc,v->read.pbus.adc_value[11]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg12,adr_adc,v->read.pbus.adc_value[12]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg13,adr_adc,v->read.pbus.adc_value[13]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg14,adr_adc,v->read.pbus.adc_value[14]); +// read_pbus_adc_value(v->setup_pbus.use_reg_in_pbus.bit.reg15,adr_adc,v->read.pbus.adc_value[15]); +// } + +/* + if (v->setup_pbus.use_reg_in_pbus.bit.reg0) + { +// v->read.pbus.adc_value[0] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; +// a_adc++; + } + else + v->read.pbus.adc_value[0] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg1) + { +// v->read.pbus.adc_value[1] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[1] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[1] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg2) + { + v->read.pbus.adc_value[2] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[2] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg3) + { + v->read.pbus.adc_value[3] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[3] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg4) + { + v->read.pbus.adc_value[4] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[4] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg5) + { + v->read.pbus.adc_value[5] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[5] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg6) + { + v->read.pbus.adc_value[6] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[6] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg7) + { + v->read.pbus.adc_value[7] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[7] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg8) + { + v->read.pbus.adc_value[8] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[8] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg9) + { + v->read.pbus.adc_value[9] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[9] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg10) + { + v->read.pbus.adc_value[10] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[10] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg11) + { + v->read.pbus.adc_value[11] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[11] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg12) + { + v->read.pbus.adc_value[12] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[12] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg13) + { + v->read.pbus.adc_value[13] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + v->read.pbus.adc_value[0] = i_ReadMemory(adr_adc++) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[13] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg14) + { + v->read.pbus.adc_value[14] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[14] = 0xffff; + + if (v->setup_pbus.use_reg_in_pbus.bit.reg15) + { + v->read.pbus.adc_value[15] = i_ReadMemory(ADR_FIRST_FREE + adr_adc + a_adc) & 0xfff; + a_adc++; + } + else + v->read.pbus.adc_value[15] = 0xffff; +*/ +//i_led2_off(); + } + else + { + v->read.pbus.adc_value[0] = 0; + v->read.pbus.adc_value[1] = 0; + v->read.pbus.adc_value[2] = 0; + v->read.pbus.adc_value[3] = 0; + v->read.pbus.adc_value[4] = 0; + v->read.pbus.adc_value[5] = 0; + v->read.pbus.adc_value[6] = 0; + v->read.pbus.adc_value[7] = 0; + v->read.pbus.adc_value[8] = 0; + v->read.pbus.adc_value[9] = 0; + v->read.pbus.adc_value[10] = 0; + v->read.pbus.adc_value[11] = 0; + v->read.pbus.adc_value[12] = 0; + v->read.pbus.adc_value[13] = 0; + v->read.pbus.adc_value[14] = 0; + v->read.pbus.adc_value[15] = 0; + } + return 0; +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void adc_reset_error(T_adc *v) +{ + if (v->useit == 0) + return ; + + if (v->status == component_Error || v->status == component_ErrorSBus) + v->status = component_Started; + + clear_cur_stat_sbus(&v->status_serial_bus); + + if (v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + + clear_cur_stat_pbus(&v->status_parallel_bus); + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//7 cmd_reset_error + + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + } + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void adc_store_disable_error(T_adc *v) +{ + if (v->useit == 0) + return ; + + if (v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + + v->store_protect_error = v->write.sbus.protect_error.all; + v->write.sbus.protect_error.all = 0; // disable all error. + + adc_write_sbus(v); + + } + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void adc_restore_enable_error(T_adc *v) +{ + if (v->useit == 0) + return ; + + if (v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + + v->write.sbus.protect_error.all = v->store_protect_error; // restore all setup error. + adc_write_sbus(v); + + } + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + + + diff --git a/Inu/Src/N12_Xilinx/xp_adc.h b/Inu/Src/N12_Xilinx/xp_adc.h new file mode 100644 index 0000000..eae3c84 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_adc.h @@ -0,0 +1,267 @@ +#ifndef XP_ADC_H +#define XP_ADC_H + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + +#define T_ADC_COUNT_ADR_PBUS 16 // count max elements in parallel bus + +#define T_ADC_SETUP_USE_ADR_PBUS 0xffff // - PBUS, 0xffff - + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + UInt16 test; +//6 + union + { + UInt16 all; + struct + { + UInt16 reserv :14; + UInt16 err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :14; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; + +//14 + union + { + UInt16 all; + struct + { + UInt16 revision :5; + UInt16 version :6; + T_plate_type plate_type :5; + } bit; + } id_plate; + +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :14; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + +} T_adc_read_sbus; + +#define T_ADC_READ_SBUS_DEFAULTS {0,0,0,0,0} +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + UInt16 test; + +//6 + union + { + UInt16 all; + struct + { + UInt16 reserv :14; + UInt16 err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; + +//7 + UInt16 cmd_reset_error; + +} T_adc_write_sbus; + +#define T_ADC_WRITE_SBUS_DEFAULTS {0,0,0} +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//read reg parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 adc_value[T_ADC_COUNT_ADR_PBUS]; +} T_adc_read_pbus; + +#define T_ADC_READ_PBUS_DEFAULTS {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} + +///////////////////////////////////////////////////////////// +// Table for adr parallel bus +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 adr_table[T_ADC_COUNT_ADR_PBUS]; +} T_adc_adr_pbus; + +#define T_ADC_ADR_PBUS_DEFAULTS {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} + + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//setup parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 count_elements_pbus; +// use_or_not? + union + { + UInt16 all; + struct{ + UInt16 reg0 : 1; + UInt16 reg1 : 1; + UInt16 reg2 : 1; + UInt16 reg3 : 1; + + UInt16 reg4 : 1; + UInt16 reg5 : 1; + UInt16 reg6 : 1; + UInt16 reg7 : 1; + + UInt16 reg8 : 1; + UInt16 reg9 : 1; + UInt16 reg10 : 1; + UInt16 reg11 : 1; + + UInt16 reg12 : 1; + UInt16 reg13 : 1; + UInt16 reg14 : 1; + UInt16 reg15 : 1; + }bit; + } use_reg_in_pbus; + +} T_adc_setup_pbus; + +#define T_ADC_SETUP_PBUS_DEFAULTS {T_ADC_COUNT_ADR_PBUS,T_ADC_SETUP_USE_ADR_PBUS} +////////////////////////////////////////////////////////////// + + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + +typedef struct{ + T_adc_read_pbus pbus; + T_adc_read_sbus sbus; + Int16 type_cds_xilinx; +} T_adc_read; + +typedef struct{ + T_adc_write_sbus sbus; +} T_adc_write; + +////////////////////////////////////////////////////////////// + +typedef struct TS_adc{ + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + T_adc_setup_pbus setup_pbus; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_adc_write write; + T_adc_read read; + T_adc_adr_pbus adr_pbus; + + UInt16 store_protect_error; + + UInt16 timer_wait_load; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + +} T_adc; + +typedef T_adc *T_adc_handle; + +/*----------------------------------------------------------------------------- +Default initalizer for object. +-----------------------------------------------------------------------------*/ +#define T_adc_DEFAULTS { 0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_ADC_SETUP_PBUS_DEFAULTS, \ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + T_ADC_WRITE_SBUS_DEFAULTS,\ + {T_ADC_READ_PBUS_DEFAULTS,T_ADC_READ_SBUS_DEFAULTS,TYPE_CDS_XILINX_DEFAULTS},\ + T_ADC_ADR_PBUS_DEFAULTS,\ + 0,\ + 0, \ + (void (*)(Uint32))adc_init, \ + (int (*)(Uint32))adc_read_all, \ + (int (*)(Uint32))adc_write_all, \ + (int (*)(Uint32))adc_read_sbus, \ + (int (*)(Uint32))adc_write_sbus, \ + (int (*)(Uint32))adc_read_pbus_without_cycle, \ + (int (*)(Uint32))adc_write_pbus, \ + (void (*)(Uint32))adc_reset_error, \ + (void (*)(Uint32))adc_store_disable_error, \ + (void (*)(Uint32))adc_restore_enable_error \ + } + +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +void adc_init(T_adc_handle); + +int adc_read_all(T_adc_handle); +int adc_write_all(T_adc_handle); + +int adc_read_sbus(T_adc_handle); +int adc_write_sbus(T_adc_handle); + +int adc_read_pbus(T_adc_handle); +int adc_write_pbus(T_adc_handle); +int adc_read_pbus_without_cycle(T_adc_handle); + +void adc_reset_error(T_adc_handle); +void adc_store_disable_error(T_adc_handle); +void adc_restore_enable_error(T_adc_handle); + +//------------------------------------------------------------------------------ +// Return Type +//------------------------------------------------------------------------------ + +#endif diff --git a/Inu/Src/N12_Xilinx/xp_cds_in.c b/Inu/Src/N12_Xilinx/xp_cds_in.c new file mode 100644 index 0000000..96a2c35 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_in.c @@ -0,0 +1,440 @@ +#include "MemoryFunctions.h" +#include "xp_cds_in.h" + +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "Spartan2E_Adr.h" +#include "TuneUpPlane.h" +#include "x_parallel_bus.h" +#include "x_serial_bus.h" +#include "xp_tools.h" +#include "xerror.h" + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void cds_in_init(T_cds_in *v) +{ + int old_started = 0; + unsigned int i; + + if (v->useit == 0) + { + clear_adr_sync_table(v->plane_address); + return ; + } + set_adr_sync_table(v->plane_address); + + if (x_parallel_bus_project.flags.bit.init==0) + x_parallel_bus_project.init(&x_parallel_bus_project); + + + old_started = x_parallel_bus_project.flags.bit.started; + + if (x_parallel_bus_project.flags.bit.started) + x_parallel_bus_project.stop(&x_parallel_bus_project); + + + x_parallel_bus_project.slave_addr = v->plane_address; + +// for (i=0;isetup_pbus.count_elements_pbus;i++) + for (i=0;i<16;i++) + { + if (v->setup_pbus.use_reg_in_pbus.all & (1<adr_pbus.adr_table[i] = x_parallel_bus_project.setup.size_table; + x_parallel_bus_project.add_table(&x_parallel_bus_project); + x_parallel_bus_project.reg_addr++; + x_parallel_bus_project.setup.size_table++; + } + else + { + // !!! + xerror(xparall_bus_er_ID(1),(void *)0); + v->setup_pbus.use_reg_in_pbus.all &= (~(1<useit == 0) + return 0; + + err = cds_in_read_sbus(v); + err |= cds_in_read_pbus(v); + + return err; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + +int cds_in_write_all(T_cds_in *v) +{ + int err = 0; + + if (v->useit == 0) + return 0; + + err = cds_in_write_sbus(v); + err |= cds_in_write_pbus(v); + + return err; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_in_write_sbus(T_cds_in *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 enabled channels + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.enabled_channels.all;//use_invers_sensor_speed.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//1 first sensor connection + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.first_sensor.all;//sensor_combo; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//2 second sensor connection + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.second_sensor.all;//sensor_combo; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + if (v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { +//3 zero sensor connection + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.zero_sensors.all;//sensor_combo; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + } + + +//6 protect_error +// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) +// v->write.sbus.protect_error.bit.enable_err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + +//7 cmd_reset_error +/* + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_error++; +*/ + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_in_write_pbus(T_cds_in *v) +{ + if (v->useit == 0) + return 0; + + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_in_read_sbus(T_cds_in *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 enabled_channels + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.enabled_channels.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//1 first_sensor + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.first_sensor.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//2 second_sensor + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.second_sensor.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->type_cds_xilinx = v->read.type_cds_xilinx; + + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + + + +//3 zero sensors + if (v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.zero_sensors.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + } +//6 protect_error + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//14 id_plate + x_serial_bus_project.reg_addr = 14; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.id_plate.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//////////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_in_read_pbus(T_cds_in *v) +{ + unsigned long adr_pbus; + unsigned int t; + + if (v->useit == 0) + return 0; + + if (v->status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + adr_pbus = v->adr_pbus.adr_table[0] + ADR_FIRST_FREE; + + if ((v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) && (v->type_plate == cds_in_type_in_1)) + { + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg0,adr_pbus, t); + v->read.pbus.data_in.all = (t & 0xff00) | ((~t) & 0x00ff); + } + else + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg0,adr_pbus,v->read.pbus.data_in.all); + + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg1,adr_pbus,v->read.pbus.ready_in.all); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg2,adr_pbus,v->read.pbus.direction_in.all); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg3,adr_pbus,v->read.pbus.SpeedS1_cnt); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg4,adr_pbus,v->read.pbus.SpeedS1_cnt90); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg5,adr_pbus,v->read.pbus.SpeedS2_cnt); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg6,adr_pbus,v->read.pbus.SpeedS2_cnt90); + if ((v->type_cds_xilinx == TYPE_CDS_XILINX_SP6)) + { + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg7,adr_pbus,v->read.pbus.Time_since_zero_point_S1); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg8,adr_pbus,v->read.pbus.Impulses_since_zero_point_Rising_S1); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg9,adr_pbus,v->read.pbus.Impulses_since_zero_point_Falling_S1); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg10,adr_pbus,v->read.pbus.Time_since_zero_point_S2); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg11,adr_pbus,v->read.pbus.Impulses_since_zero_point_Rising_S2); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg12,adr_pbus,v->read.pbus.Impulses_since_zero_point_Falling_S2); + read_pbus_value(v->setup_pbus.use_reg_in_pbus.bit.reg13,adr_pbus,v->read.pbus.channel_alive.all); + } + + } + else + { + v->read.pbus.data_in.all = 0; + v->read.pbus.ready_in.all = 0; + v->read.pbus.direction_in.all = 0; + v->read.pbus.SpeedS1_cnt = 0; + v->read.pbus.SpeedS1_cnt90 = 0; + v->read.pbus.SpeedS2_cnt = 0; + v->read.pbus.SpeedS2_cnt90 = 0; + v->read.pbus.Time_since_zero_point_S1 = 0; + v->read.pbus.Impulses_since_zero_point_Rising_S1 = 0; + v->read.pbus.Impulses_since_zero_point_Falling_S1 = 0; + v->read.pbus.Time_since_zero_point_S2 = 0; + v->read.pbus.Impulses_since_zero_point_Rising_S2 = 0; + v->read.pbus.Impulses_since_zero_point_Falling_S2 = 0; + v->read.pbus.channel_alive.all = 0; + } + + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void cds_in_reset_error(T_cds_in *v) +{ + if (v->useit == 0) + return ; + + if (v->status == component_Error || v->status == component_ErrorSBus) + v->status = component_Started; + clear_cur_stat_sbus(&v->status_serial_bus); + clear_cur_stat_pbus(&v->status_parallel_bus); + + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//7 cmd_reset_error + + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void cds_in_store_disable_error(T_cds_in *v) +{ + if (v->useit == 0) + return ; + + v->store_protect_error = v->write.sbus.protect_error.all; + v->write.sbus.protect_error.all = 0; // disable all error. + + cds_in_write_sbus(v); + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void cds_in_restore_enable_error(T_cds_in *v) +{ + if (v->useit == 0) + return ; + + v->write.sbus.protect_error.all = v->store_protect_error; // restore all setup error. + cds_in_write_sbus(v); + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_in.h b/Inu/Src/N12_Xilinx/xp_cds_in.h new file mode 100644 index 0000000..dc73d10 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_in.h @@ -0,0 +1,517 @@ +#ifndef XP_CDS_IN_H +#define XP_CDS_IN_H + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + +// IN1 IN2 +typedef enum { + cds_in_type_in_1 = 0x0, // IN1 + cds_in_type_in_2 = 0x1, // IN2 + cds_in_type_not_inited = -1 // +} T_cds_in_type_plate; + +#define C_cds_in_dout_range 4 +// xSENS - number sensors +// FIRST_x_x_SECOND_x_x - number sens pairs +// 0 pair = in0+in1 +// 1 pair = in2+in3 +// 2 pair = in4+in5 +// 3 pair = in6+in7 + +#define T_CDS_IN_COUNT_ADR_PBUS 14 // count max elements in parallel bus + +#define T_CDS_IN_COUNT_ADR_PBUS_SP2 8 // 8 , .. SP2 . +#define T_CDS_IN_COUNT_ADR_PBUS_SP6 T_CDS_IN_COUNT_ADR_PBUS + + +#define T_CDS_IN_SETUP_USE_ADR_PBUS 0xffff // - PBUS, 0xffff - , 0x0000 - + +#define SENSOR_COMBO_2SENS_FIRST_0_1_SECOND_2_3 1 +#define SENSOR_COMBO_2SENS_FIRST_0_3_SECOND_1_2 2 +#define SENSOR_COMBO_2SENS_FIRST_0_2_SECOND_1_3 3 +#define SENSOR_COMBO_1SENS_FIRST_0_1 4 +#define SENSOR_COMBO_1SENS_FIRST_1_2 5 +#define SENSOR_COMBO_1SENS_FIRST_2_3 6 +#define SENSOR_COMBO_1SENS_FIRST_0_2 7 +#define SENSOR_COMBO_1SENS_FIRST_0_3 8 +#define SENSOR_COMBO_1SENS_FIRST_1_3 9 + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + +//0 + union + { + UInt16 all; + struct{ + UInt16 discret : 1; + UInt16 reserv : 7; + UInt16 sens_2_inv_ch_90deg : 1; + UInt16 sens_2_direct_ch_90deg : 1; + UInt16 sens_2_inv_ch : 1; + UInt16 sens_2_direct_ch : 1; + UInt16 sens_1_inv_ch_90deg : 1; + UInt16 sens_1_direct_ch_90deg : 1; + UInt16 sens_1_inv_ch : 1; + UInt16 sens_1_direct_ch : 1; + }bit; + }enabled_channels; + +//1 + union + { + UInt16 all; + struct{ + UInt16 inv_ch_90deg : 4; + UInt16 direct_ch_90deg : 4; + UInt16 inv_ch : 4; + UInt16 direct_ch : 4; + }bit; + }first_sensor; + +//2 + union + { + UInt16 all; + struct{ + UInt16 inv_ch_90deg : 4; + UInt16 direct_ch_90deg : 4; + UInt16 inv_ch : 4; + UInt16 direct_ch : 4; + }bit; + }second_sensor; + +//3 // for SP6 only + union + { + UInt16 all; + struct{ + UInt16 enable_sensor2 : 1; // 0 - disable, 1 - enable + UInt16 enable_sensor1 : 1; // 0 - disable, 1 - enable + UInt16 reserv : 6; + UInt16 for_sensor2 : 4; + UInt16 for_sensor1 : 4; + }bit; + }zero_sensors; + + //UInt16 sensor_combo; +//6 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; + +//7 + UInt16 cmd_reset_error; + +} T_cds_in_write_sbus; + +#define T_CDS_IN_WRITE_SBUS_DEFAULTS {0,0,0,0,0xc000,0} + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//read reg parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 PB + union + { + UInt16 all; + struct{ + UInt16 in0 : 1; + UInt16 in1 : 1; + UInt16 in2 : 1; + UInt16 in3 : 1; + UInt16 in4 : 1; + UInt16 in5 : 1; + UInt16 in6 : 1; + UInt16 in7 : 1; + UInt16 in8 : 1; + UInt16 in9 : 1; + UInt16 in10 : 1; + UInt16 in11 : 1; + UInt16 in12 : 1; + UInt16 in13 : 1; + UInt16 in14 : 1; + UInt16 in15 : 1; + }bit; + } data_in; +//1 PB + union + { + UInt16 all; + struct{ + UInt16 in0 : 1; + UInt16 in1 : 1; + UInt16 in2 : 1; + UInt16 in3 : 1; + UInt16 in4 : 1; + UInt16 in5 : 1; + UInt16 in6 : 1; + UInt16 in7 : 1; + UInt16 in8 : 1; + UInt16 in9 : 1; + UInt16 in10 : 1; + UInt16 in11 : 1; + UInt16 in12 : 1; + UInt16 in13 : 1; + UInt16 in14 : 1; + UInt16 in15 : 1; + }bit; + } ready_in; +//2 PB + union + { + UInt16 all; + struct{ + UInt16 dir_sens_1 : 2; // 00 - stop, 10-"+" 01-"-" 11-error + UInt16 dir_sens_2 : 2; // 00 - stop, 10-"+" 01-"-" 11-error + UInt16 reserv : 4; + UInt16 mode_sensor2_90 : 1; // , 1 - 20ns 0 - 2us. + UInt16 mode_sensor2_direct : 1; // , 1 - 20ns 0 - 2us. + UInt16 mode_sensor1_90 : 1; // , 1 - 20ns 0 - 2us. + UInt16 mode_sensor1_direct : 1; // , 1 - 20ns 0 - 2us. + UInt16 value_vaild_sensor2_90 : 1;//1- 0 - , + UInt16 value_vaild_sensor2_direct: 1; + UInt16 value_vaild_sensor1_90 : 1; + UInt16 value_vaild_sensor1_direct: 1; + }bit; + } direction_in; + + +//3 PB + UInt16 SpeedS1_cnt; +//4 PB + UInt16 SpeedS1_cnt90; +//5 PB + UInt16 SpeedS2_cnt; +//6 PB + UInt16 SpeedS2_cnt90; +//7 PB + UInt16 Time_since_zero_point_S1; +//8 PB + UInt16 Impulses_since_zero_point_Rising_S1; +//9 PB + UInt16 Impulses_since_zero_point_Falling_S1; +//10 PB + UInt16 Time_since_zero_point_S2; +//11 PB + UInt16 Impulses_since_zero_point_Rising_S2; +//12 PB + UInt16 Impulses_since_zero_point_Falling_S2; +//13 PB + union + { + UInt16 all; + struct{ + UInt16 reserv : 8; + UInt16 sens_2_inv_ch_90deg : 1; + UInt16 sens_2_direct_ch_90deg : 1; + UInt16 sens_2_inv_ch : 1; + UInt16 sens_2_direct_ch : 1; + UInt16 sens_1_inv_ch_90deg : 1; + UInt16 sens_1_direct_ch_90deg : 1; + UInt16 sens_1_inv_ch : 1; + UInt16 sens_1_direct_ch : 1; + }bit; + } channel_alive; + +} T_cds_in_read_pbus; + +#define T_CDS_IN_READ_PBUS_DEFAULTS {0,0,0,0,0,0,0,0,0,0,0,0,0,0} +///////////////////////////////////////////////////////////// +// Table for adr parallel bus +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 adr_table[T_CDS_IN_COUNT_ADR_PBUS]; +} T_cds_in_adr_pbus; + +#define T_CDS_IN_ADR_PBUS_DEFAULTS {0,0,0,0,0,0,0,0,0,0,0,0,0} + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct{ + UInt16 discret : 1; + UInt16 reserv : 7; + UInt16 sens_2_inv_ch_90deg : 1; + UInt16 sens_2_direct_ch_90deg : 1; + UInt16 sens_2_inv_ch : 1; + UInt16 sens_2_direct_ch : 1; + UInt16 sens_1_inv_ch_90deg : 1; + UInt16 sens_1_direct_ch_90deg : 1; + UInt16 sens_1_inv_ch : 1; + UInt16 sens_1_direct_ch : 1; + }bit; + }enabled_channels; + +//1 + union + { + UInt16 all; + struct{ + UInt16 inv_ch_90deg : 4; + UInt16 direct_ch_90deg : 4; + UInt16 inv_ch : 4; + UInt16 direct_ch : 4; + }bit; + }first_sensor; + +//2 + union + { + UInt16 all; + struct{ + UInt16 inv_ch_90deg : 4; + UInt16 direct_ch_90deg : 4; + UInt16 inv_ch : 4; + UInt16 direct_ch : 4; + }bit; + }second_sensor; + +//3 // for SP6 only + union + { + UInt16 all; + struct{ + UInt16 enable_sensor2 : 1; // 0 - disable, 1 - enable + UInt16 enable_sensor1 : 1; // 0 - disable, 1 - enable + UInt16 reserv : 6; + UInt16 for_sensor1 : 4; + UInt16 for_sensor2 : 4; + }bit; + }zero_sensors; + +//6 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; + +//14 + union + { + UInt16 all; + struct + { + UInt16 revision :5; + UInt16 version :6; + T_plate_type plate_type :5; + } bit; + } id_plate; + + +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + + +} T_cds_in_read_sbus; + +#define T_CDS_IN_READ_SBUS_DEFAULTS {0,0,0,0,0} + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + + +typedef struct{ + T_cds_in_write_sbus sbus; +} T_cds_in_write; + +typedef struct{ + T_cds_in_read_sbus sbus; + T_cds_in_read_pbus pbus; + Int16 type_cds_xilinx; +} T_cds_in_read; + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//setup parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 count_elements_pbus; +// use_or_not? + union + { + UInt16 all; + struct{ + UInt16 reg0 : 1; + UInt16 reg1 : 1; + UInt16 reg2 : 1; + UInt16 reg3 : 1; + UInt16 reg4 : 1; + UInt16 reg5 : 1; + UInt16 reg6 : 1; + UInt16 reg7 : 1; + UInt16 reg8 : 1; + UInt16 reg9 : 1; + UInt16 reg10 : 1; + UInt16 reg11 : 1; + UInt16 reg12 : 1; + UInt16 reg13 : 1; + UInt16 reg14 : 1; + UInt16 reg15 : 1; + }bit; + } use_reg_in_pbus; + +} T_cds_in_setup_pbus; + +#define T_CDS_IN_SETUP_PBUS_DEFAULTS {T_CDS_IN_COUNT_ADR_PBUS,T_CDS_IN_SETUP_USE_ADR_PBUS} +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + + +typedef struct TS_cds_in{ + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + T_cds_in_type_plate type_plate; + + T_cds_in_setup_pbus setup_pbus; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_in_write write; + T_cds_in_read read; + T_cds_in_adr_pbus adr_pbus; + + UInt16 store_protect_error; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + +} T_cds_in; + + +typedef T_cds_in *T_cds_in_handle; + +/*----------------------------------------------------------------------------- +Default initalizer for object. +-----------------------------------------------------------------------------*/ +#define T_cds_in_DEFAULTS { 0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + cds_in_type_not_inited,\ + T_CDS_IN_SETUP_PBUS_DEFAULTS,\ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + {T_CDS_IN_WRITE_SBUS_DEFAULTS},\ + {T_CDS_IN_READ_SBUS_DEFAULTS,T_CDS_IN_READ_PBUS_DEFAULTS,TYPE_CDS_XILINX_DEFAULTS},\ + T_CDS_IN_ADR_PBUS_DEFAULTS, \ + 0, \ + (void (*)(Uint32))cds_in_init, \ + (int (*)(Uint32))cds_in_read_all, \ + (int (*)(Uint32))cds_in_write_all, \ + (int (*)(Uint32))cds_in_read_sbus, \ + (int (*)(Uint32))cds_in_write_sbus, \ + (int (*)(Uint32))cds_in_read_pbus, \ + (int (*)(Uint32))cds_in_write_pbus, \ + (void (*)(Uint32))cds_in_reset_error, \ + (void (*)(Uint32))cds_in_store_disable_error, \ + (void (*)(Uint32))cds_in_restore_enable_error \ + } + +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +void cds_in_init(T_cds_in_handle); + +int cds_in_read_all(T_cds_in_handle); +int cds_in_write_all(T_cds_in_handle); + +int cds_in_read_sbus(T_cds_in_handle); +int cds_in_write_sbus(T_cds_in_handle); + +int cds_in_read_pbus(T_cds_in_handle); +int cds_in_write_pbus(T_cds_in_handle); + +void cds_in_reset_error(T_cds_in_handle); +void cds_in_store_disable_error(T_cds_in_handle); +void cds_in_restore_enable_error(T_cds_in_handle); + + + +#endif diff --git a/Inu/Src/N12_Xilinx/xp_cds_out.c b/Inu/Src/N12_Xilinx/xp_cds_out.c new file mode 100644 index 0000000..56200f4 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_out.c @@ -0,0 +1,310 @@ +#include "x_serial_bus.h" +#include "xp_cds_out.h" + +#include "x_serial_bus.h" +#include "xp_tools.h" + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void cds_out_init(T_cds_out *v) +{ + if (v->useit == 0) + { + clear_adr_sync_table(v->plane_address); + return ; + } + set_adr_sync_table(v->plane_address); + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + +int cds_out_read_all(T_cds_out *v) +{ + int err = 0; + + if (v->useit == 0) + return 0; + + err = cds_out_read_sbus(v); + err |= cds_out_read_pbus(v); + + return err; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + +int cds_out_write_all(T_cds_out *v) +{ + int err = 0; + + if (v->useit == 0) + return 0; + + err = cds_out_write_sbus(v); + err |= cds_out_write_pbus(v); + + return err; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_out_write_sbus(T_cds_out *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + static unsigned int e; + static unsigned int c_ok=0; + + if (v->useit == 0) + return 0; + + e = 0; + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 data_out + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.data_out.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + { + v->status_serial_bus.count_write_error++; + e |= 1; + } + +//1 enable_protect_out + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.enable_protect_out.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + { + v->status_serial_bus.count_write_error++; + e |= 2; + } + +//6 protect_error +// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) +// v->write.sbus.protect_error.bit.enable_err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + { + v->status_serial_bus.count_write_error++; + e |= 4; + } + + +//7 cmd_reset_error +/* + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_error++; +*/ + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + c_ok++; + err = 0; // no errors + } + else + { + err = 1; // !errors! + c_ok = 0; + } + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_out_write_pbus(T_cds_out *v) +{ + + if (v->useit == 0) + return 0; + + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_out_read_sbus(T_cds_out *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 data_out + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.data_out.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//1 enable_protect_out + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.enable_protect_out.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//6 protect_error + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->type_cds_xilinx = v->read.type_cds_xilinx; + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + + +/////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_out_read_pbus(T_cds_out *v) +{ + if (v->useit == 0) + return 0; + + + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void cds_out_reset_error(T_cds_out *v) +{ + + if (v->useit == 0) + return ; + + if (v->status == component_Error || v->status == component_ErrorSBus) + v->status = component_Started; + clear_cur_stat_sbus(&v->status_serial_bus); + clear_cur_stat_pbus(&v->status_parallel_bus); + + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//7 cmd_reset_error + + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void cds_out_store_disable_error(T_cds_out *v) +{ + if (v->useit == 0) + return ; + + v->store_protect_error = v->write.sbus.protect_error.all; + v->write.sbus.protect_error.all = 0; // disable all error. + + cds_out_write_sbus(v); + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void cds_out_restore_enable_error(T_cds_out *v) +{ + + if (v->useit == 0) + return ; + + v->write.sbus.protect_error.all = v->store_protect_error; // restore all setup error. + cds_out_write_sbus(v); + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_out.h b/Inu/Src/N12_Xilinx/xp_cds_out.h new file mode 100644 index 0000000..0494910 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_out.h @@ -0,0 +1,286 @@ +#ifndef XP_CDS_OUT_H +#define XP_CDS_OUT_H + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct{ + UInt16 dout0 : 1; + UInt16 dout1 : 1; + UInt16 dout2 : 1; + UInt16 dout3 : 1; + UInt16 dout4 : 1; + UInt16 dout5 : 1; + UInt16 dout6 : 1; + UInt16 dout7 : 1; + UInt16 dout8 : 1; + UInt16 dout9 : 1; + UInt16 dout10 : 1; + UInt16 dout11 : 1; + UInt16 dout12 : 1; + UInt16 dout13 : 1; + UInt16 dout14 : 1; + UInt16 dout15 : 1; + }bit; + } data_out; +//1 + union + { + UInt16 all; + struct{ + UInt16 dout0 : 1; + UInt16 dout1 : 1; + UInt16 dout2 : 1; + UInt16 dout3 : 1; + UInt16 dout4 : 1; + UInt16 dout5 : 1; + UInt16 dout6 : 1; + UInt16 dout7 : 1; + UInt16 dout8 : 1; + UInt16 dout9 : 1; + UInt16 dout10 : 1; + UInt16 dout11 : 1; + UInt16 dout12 : 1; + UInt16 dout13 : 1; + UInt16 dout14 : 1; + UInt16 dout15 : 1; + }bit; + } enable_protect_out; +//6 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + UInt16 cmd_reset_error; + +} T_cds_out_write_sbus; + +#define T_CDS_OUT_WRITE_SBUS_DEFAULTS {0xffff,0xffff,0xf000,0} + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct{ + UInt16 dout0 : 1; + UInt16 dout1 : 1; + UInt16 dout2 : 1; + UInt16 dout3 : 1; + UInt16 dout4 : 1; + UInt16 dout5 : 1; + UInt16 dout6 : 1; + UInt16 dout7 : 1; + UInt16 dout8 : 1; + UInt16 dout9 : 1; + UInt16 dout10 : 1; + UInt16 dout11 : 1; + UInt16 dout12 : 1; + UInt16 dout13 : 1; + UInt16 dout14 : 1; + UInt16 dout15 : 1; + }bit; + } data_out; +//1 + union + { + UInt16 all; + struct{ + UInt16 dout0 : 1; + UInt16 dout1 : 1; + UInt16 dout2 : 1; + UInt16 dout3 : 1; + UInt16 dout4 : 1; + UInt16 dout5 : 1; + UInt16 dout6 : 1; + UInt16 dout7 : 1; + UInt16 dout8 : 1; + UInt16 dout9 : 1; + UInt16 dout10 : 1; + UInt16 dout11 : 1; + UInt16 dout12 : 1; + UInt16 dout13 : 1; + UInt16 dout14 : 1; + UInt16 dout15 : 1; + }bit; + } enable_protect_out; + +//6 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; + +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + + +} T_cds_out_read_sbus; + +#define T_CDS_OUT_READ_SBUS_DEFAULTS {0,0,0,0,0} +///////////////////////////////////////////////////////////////// + + +typedef struct{ + T_cds_out_write_sbus sbus; +} T_cds_out_write; + +typedef struct{ + T_cds_out_read_sbus sbus; + Int16 type_cds_xilinx; +} T_cds_out_read; + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// main struct +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct TS_cds_out{ + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_out_write write; + T_cds_out_read read; + + UInt16 store_protect_error; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + +} T_cds_out; + +typedef T_cds_out *T_cds_out_handle; + +/*----------------------------------------------------------------------------- +Default initalizer for object. +-----------------------------------------------------------------------------*/ +#define T_cds_out_DEFAULTS { 0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + {T_CDS_OUT_WRITE_SBUS_DEFAULTS},\ + {T_CDS_OUT_READ_SBUS_DEFAULTS,TYPE_CDS_XILINX_DEFAULTS},\ + 0,\ + (void (*)(Uint32))cds_out_init, \ + (int (*)(Uint32))cds_out_read_all, \ + (int (*)(Uint32))cds_out_write_all, \ + (int (*)(Uint32))cds_out_read_sbus, \ + (int (*)(Uint32))cds_out_write_sbus, \ + (int (*)(Uint32))cds_out_read_pbus, \ + (int (*)(Uint32))cds_out_write_pbus, \ + (void (*)(Uint32))cds_out_reset_error, \ + (void (*)(Uint32))cds_out_store_disable_error, \ + (void (*)(Uint32))cds_out_restore_enable_error \ + } + +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +void cds_out_init(T_cds_out_handle); + +int cds_out_read_all(T_cds_out_handle); +int cds_out_write_all(T_cds_out_handle); + +int cds_out_read_sbus(T_cds_out_handle); +int cds_out_write_sbus(T_cds_out_handle); + +int cds_out_read_pbus(T_cds_out_handle); +int cds_out_write_pbus(T_cds_out_handle); + +void cds_out_reset_error(T_cds_out_handle); +void cds_out_store_disable_error(T_cds_out_handle); +void cds_out_restore_enable_error(T_cds_out_handle); + +#endif diff --git a/Inu/Src/N12_Xilinx/xp_cds_rs.c b/Inu/Src/N12_Xilinx/xp_cds_rs.c new file mode 100644 index 0000000..b19acde --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_rs.c @@ -0,0 +1,399 @@ +#include "x_parallel_bus.h" +#include "xp_cds_rs.h" + +#include "x_parallel_bus.h" +#include "x_serial_bus.h" +#include "xp_tools.h" +#include "xp_tools.h" +#include "xerror.h" + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void cds_rs_init(T_cds_rs *v) +{ + int old_started = 0; + unsigned int i; + + if (v->useit == 0) + { + clear_adr_sync_table(v->plane_address); + return ; + } + set_adr_sync_table(v->plane_address); + + if (x_parallel_bus_project.flags.bit.init==0) + x_parallel_bus_project.init(&x_parallel_bus_project); + + + old_started = x_parallel_bus_project.flags.bit.started; + + if (x_parallel_bus_project.flags.bit.started) + x_parallel_bus_project.stop(&x_parallel_bus_project); + + + x_parallel_bus_project.slave_addr = v->plane_address; + + // for (i=0;isetup_pbus.count_elements_pbus;i++) + for (i=0;i<16;i++) + { + if (v->setup_pbus.use_reg_in_pbus.all & (1<adr_pbus.adr_table[i] = x_parallel_bus_project.setup.size_table; + x_parallel_bus_project.add_table(&x_parallel_bus_project); + x_parallel_bus_project.reg_addr++; + x_parallel_bus_project.setup.size_table++; + } + else + { + // !!! + xerror(xparall_bus_er_ID(1),(void *)0); + v->setup_pbus.use_reg_in_pbus.all &= (~(1<useit == 0) + return 0; + + cds_rs_read_sbus(v); + cds_rs_read_pbus(v); + return 0; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + +int cds_rs_write_all(T_cds_rs *v) +{ + if (v->useit == 0) + return 0; + + cds_rs_write_sbus(v); + cds_rs_write_pbus(v); + return 0; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_rs_write_sbus(T_cds_rs *v) +{ + unsigned int old_err; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//8 config rs speed, master/slave and period of survey + x_serial_bus_project.reg_addr = 8; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.config.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + return 0; // no errors + } + + return 1; // !error! + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_rs_write_pbus(T_cds_rs *v) +{ + if (v->useit == 0) + return 0; + + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_rs_read_sbus(T_cds_rs *v) +{ + unsigned int old_err; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 + if(v->write.sbus.config.bit.channel1_enable) + { + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.sbus.sensor[0].direction = (x_parallel_bus_project.data_table_read >> 15) & 1; + v->read.sbus.sensor[0].turned_angle = (x_parallel_bus_project.data_table_read & 0x7FFF) << 3; + } + else + v->status_serial_bus.count_read_error++; + } + +//1 + if(v->write.sbus.config.bit.channel2_enable) + { + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.sbus.sensor[1].direction = (x_parallel_bus_project.data_table_read >> 15) & 1; + v->read.sbus.sensor[1].turned_angle = (x_parallel_bus_project.data_table_read & 0x7FFF) << 3; + } + else + v->status_serial_bus.count_read_error++; + } +//2 + if(v->write.sbus.config.bit.channel3_enable) + { + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.sbus.sensor[2].direction = (x_parallel_bus_project.data_table_read >> 15) & 1; + v->read.sbus.sensor[2].turned_angle = (x_parallel_bus_project.data_table_read & 0x7FFF) << 3; + } + else + v->status_serial_bus.count_read_error++; + } +//3 + if(v->write.sbus.config.bit.channel4_enable) + { + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.sbus.sensor[3].direction = (x_parallel_bus_project.data_table_read >> 15) & 1; + v->read.sbus.sensor[3].turned_angle = (x_parallel_bus_project.data_table_read & 0x7FFF) << 3; + } + else + v->status_serial_bus.count_read_error++; + } +//4 + if(v->write.sbus.config.bit.channel1_enable) + { + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.sbus.sensor[0].angle = x_parallel_bus_project.data_table_read << 2; + } + else + v->status_serial_bus.count_read_error++; + } +//5 + if(v->write.sbus.config.bit.channel2_enable) + { + x_serial_bus_project.reg_addr = 5; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.sbus.sensor[1].angle = x_parallel_bus_project.data_table_read << 2; + } + else + v->status_serial_bus.count_read_error++; + } +//6 + if(v->write.sbus.config.bit.channel3_enable) + { + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.sbus.sensor[2].angle = x_parallel_bus_project.data_table_read << 2; + } + else + v->status_serial_bus.count_read_error++; + } +//7 + if(v->write.sbus.config.bit.channel4_enable) + { + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.sbus.sensor[3].angle = x_parallel_bus_project.data_table_read << 2; + } + else + v->status_serial_bus.count_read_error++; + } + +//8 + x_serial_bus_project.reg_addr = 8; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.sbus.config.all = x_parallel_bus_project.data_table_read; + } + else + v->status_serial_bus.count_read_error++; + + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; +// v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + + +//////////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + return 0; // no errors + } + + return 1; // !errors! +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_rs_read_pbus(T_cds_rs *v) +{ + if (v->useit == 0) + return 0; + + if (v->status & (component_Started | component_Ready | component_Error | component_ErrorSBus)) + { +//0 + if(v->write.sbus.config.bit.channel1_enable && v->setup_pbus.use_reg_in_pbus.bit.reg0) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[0]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.sensor[0].direction = (x_parallel_bus_project.data_table_read >> 15) & 1; + v->read.pbus.sensor[0].turned_angle = (x_parallel_bus_project.data_table_read & 0x7FFF) << 3; + } +//1 + if(v->write.sbus.config.bit.channel2_enable && v->setup_pbus.use_reg_in_pbus.bit.reg1) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[1]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.sensor[1].direction = (x_parallel_bus_project.data_table_read >> 15) & 1; + v->read.pbus.sensor[1].turned_angle = (x_parallel_bus_project.data_table_read & 0x7FFF) << 3; + } +//2 + if(v->write.sbus.config.bit.channel3_enable && v->setup_pbus.use_reg_in_pbus.bit.reg2) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[2]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.sensor[2].direction = (x_parallel_bus_project.data_table_read >> 15) & 1; + v->read.pbus.sensor[2].turned_angle = (x_parallel_bus_project.data_table_read & 0x7FFF) << 3; + } +//3 + if(v->write.sbus.config.bit.channel4_enable && v->setup_pbus.use_reg_in_pbus.bit.reg3) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[3]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.sensor[3].direction = (x_parallel_bus_project.data_table_read >> 15) & 1; + v->read.pbus.sensor[3].turned_angle = (x_parallel_bus_project.data_table_read & 0x7FFF) << 3; + } +//4 + if(v->write.sbus.config.bit.channel1_enable && v->setup_pbus.use_reg_in_pbus.bit.reg4) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[4]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.sensor[0].angle = x_parallel_bus_project.data_table_read << 2; + } +//5 + if(v->write.sbus.config.bit.channel2_enable && v->setup_pbus.use_reg_in_pbus.bit.reg5) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[5]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.sensor[1].angle = x_parallel_bus_project.data_table_read << 2; + } +//6 + if(v->write.sbus.config.bit.channel3_enable && v->setup_pbus.use_reg_in_pbus.bit.reg6) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[6]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.sensor[2].angle = x_parallel_bus_project.data_table_read << 2; + } +//7 + if(v->write.sbus.config.bit.channel4_enable && v->setup_pbus.use_reg_in_pbus.bit.reg7) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[7]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.sensor[3].angle = x_parallel_bus_project.data_table_read << 2; + } + } + else + { + v->read.pbus.sensor[0].direction = 0; + v->read.pbus.sensor[0].turned_angle = 0; + v->read.pbus.sensor[0].angle = 0; + + v->read.pbus.sensor[1].direction = 0; + v->read.pbus.sensor[1].turned_angle = 0; + v->read.pbus.sensor[1].angle = 0; + + v->read.pbus.sensor[2].direction = 0; + v->read.pbus.sensor[2].turned_angle = 0; + v->read.pbus.sensor[2].angle = 0; + + v->read.pbus.sensor[3].direction = 0; + v->read.pbus.sensor[3].turned_angle = 0; + v->read.pbus.sensor[3].angle = 0; + } + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + diff --git a/Inu/Src/N12_Xilinx/xp_cds_rs.h b/Inu/Src/N12_Xilinx/xp_cds_rs.h new file mode 100644 index 0000000..c9b04c2 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_rs.h @@ -0,0 +1,182 @@ +#ifndef XP_CDS_RS_H +#define XP_CDS_RS_H + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + +#define T_CDS_RS_COUNT_ADR_PBUS 8 // count max elements in parallel bus +#define T_CDS_RS_SETUP_USE_ADR_PBUS 0xffff // - PBUS, 0xffff - + +#define USED_RS_SENSORS 4 // Number of measuring channels + +typedef union { + unsigned int all; + struct { + unsigned int survey_time:8; // 10 (0==10, 1==20,...) + unsigned int channel4_enable:1; + unsigned int channel3_enable:1; + unsigned int channel2_enable:1; + unsigned int channel1_enable:1; + unsigned int transmition_speed:3; + unsigned int plane_is_master:1; + }bit; +} T_cds_rs_config; + +#define T_CDS_RS_CONFIG_DEFAULT {0xA131} + +typedef struct { + T_cds_rs_config config; +} T_cds_rs_write_sbus; + +#define T_CDS_RS_WRITE_SBUS_DEFAULT \ + {T_CDS_RS_CONFIG_DEFAULT} + +typedef struct { + int direction; + unsigned long turned_angle; + unsigned long angle; +} Sensor; + +#define SENSOR_DEFAULT {0, 0, 0} + +typedef struct { + Sensor sensor[USED_RS_SENSORS]; +} T_cds_rs_read_pbus; + +#define T_CDS_RS_READ_PBUS_DEFAULT { \ + {SENSOR_DEFAULT, SENSOR_DEFAULT, SENSOR_DEFAULT, SENSOR_DEFAULT}} + +typedef struct { + Sensor sensor[USED_RS_SENSORS]; + T_cds_rs_config config; +} T_cds_rs_read_sbus; + +#define T_CDS_RS_READ_SBUS_DEFAULT { \ + {SENSOR_DEFAULT, SENSOR_DEFAULT, SENSOR_DEFAULT, SENSOR_DEFAULT}, \ + T_CDS_RS_CONFIG_DEFAULT} + +typedef struct { + T_cds_rs_write_sbus sbus; +} T_cds_rs_write; + +#define T_CDS_RS_WRITE_DEFAULT \ + {T_CDS_RS_WRITE_SBUS_DEFAULT} + +typedef struct { + T_cds_rs_read_pbus pbus; + T_cds_rs_read_sbus sbus; + Int16 type_cds_xilinx; +} T_cds_rs_read; + +#define T_CDS_RS_READ_DEFAULT \ + {T_CDS_RS_READ_PBUS_DEFAULT, T_CDS_RS_READ_SBUS_DEFAULT,TYPE_CDS_XILINX_DEFAULTS} + +///////////////////////////////////////////////////////////// +// Table for adr parallel bus +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 adr_table[T_CDS_RS_COUNT_ADR_PBUS]; +} T_cds_rs_adr_pbus; + +#define T_CDS_RS_ADR_PBUS_DEFAULTS {0,0,0,0,0,0,0,0} + + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//setup parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 count_elements_pbus; +// use_or_not? + union + { + UInt16 all; + struct{ + UInt16 reg0 : 1; + UInt16 reg1 : 1; + UInt16 reg2 : 1; + UInt16 reg3 : 1; + + UInt16 reg4 : 1; + UInt16 reg5 : 1; + UInt16 reg6 : 1; + UInt16 reg7 : 1; + + UInt16 res : 8; + }bit; + } use_reg_in_pbus; + +} T_cds_rs_setup_pbus; + +#define T_CDS_RS_SETUP_PBUS_DEFAULTS {T_CDS_RS_COUNT_ADR_PBUS,T_CDS_RS_SETUP_USE_ADR_PBUS} +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + + + +typedef struct { + UInt16 plane_address; + UInt16 useit; + Int16 type_cds_xilinx; + T_cds_rs_setup_pbus setup_pbus; + + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_rs_write write; + T_cds_rs_read read; + T_cds_rs_adr_pbus adr_pbus; + + void(*init)(); + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + +} T_cds_rs; + +typedef T_cds_rs *T_cds_rs_handle; + +/*----------------------------------------------------------------------------- +Default initalizer for object. +-----------------------------------------------------------------------------*/ +#define T_cds_rs_DEFAULTS { 0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_CDS_RS_SETUP_PBUS_DEFAULTS,\ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + T_CDS_RS_WRITE_DEFAULT,\ + T_CDS_RS_READ_DEFAULT, \ + T_CDS_RS_ADR_PBUS_DEFAULTS, \ + (void (*)(Uint32))cds_rs_init, \ + (int (*)(Uint32))cds_rs_read_all, \ + (int (*)(Uint32))cds_rs_write_all, \ + (int (*)(Uint32))cds_rs_read_sbus, \ + (int (*)(Uint32))cds_rs_write_sbus, \ + (int (*)(Uint32))cds_rs_read_pbus, \ + (int (*)(Uint32))cds_rs_write_pbus, \ + } + +void cds_rs_init(T_cds_rs *v); +int cds_rs_read_all(T_cds_rs *v); +int cds_rs_write_all(T_cds_rs *v); +int cds_rs_write_sbus(T_cds_rs *v); +int cds_rs_write_pbus(T_cds_rs *v); +int cds_rs_read_sbus(T_cds_rs *v); +int cds_rs_read_pbus(T_cds_rs *v); + + +#endif //XP_CDS_RS_H diff --git a/Inu/Src/N12_Xilinx/xp_cds_status_bus.c b/Inu/Src/N12_Xilinx/xp_cds_status_bus.c new file mode 100644 index 0000000..3718d57 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_status_bus.c @@ -0,0 +1,217 @@ +#include "xp_cds_status_bus.h" +//#include "xp_tools.h" + + +void clear_cur_stat_sbus(T_cds_status_serial_bus *v) +{ + v->cur_read_error = 0; + v->cur_write_error = 0; +} + +void clear_cur_stat_pbus(T_cds_status_parallel_bus *v) +{ + v->cur_read_error = 0; + v->cur_write_error = 0; +} + +void clear_cur_stat_hwpbus(T_cds_status_hwp_bus *v) +{ + v->cur_read_error = 0; + v->cur_write_error = 0; +} + + +//////////////////////////////////////////// +//////////////////////////////////////////// + + +void clear_stat_sbus(T_cds_status_serial_bus *v) +{ + v->count_read_error = 0; + v->count_write_error = 0; + v->count_read_ok = 0; + v->count_write_ok = 0; + v->cur_read_error = 0; + v->cur_write_error = 0; + + v->status = 0; +} + +void clear_stat_pbus(T_cds_status_parallel_bus *v) +{ + v->count_read_error = 0; + v->count_write_error = 0; + v->count_read_ok = 0; + v->count_write_ok = 0; + v->cur_read_error = 0; + v->cur_write_error = 0; + + v->status = 0; +} + +void clear_stat_hwpbus(T_cds_status_hwp_bus *v) +{ + v->count_read_error = 0; + v->count_write_error = 0; + v->count_read_ok = 0; + v->count_write_ok = 0; + + v->cur_read_error = 0; + v->cur_write_error = 0; + + v->status = 0; +} + + +int check_cds_ready_sbus(int err, int wr_rd, T_cds_status_serial_bus *v) +{ + + if (wr_rd == ITS_WRITE_BUS) // write + { + if (err) + { + if (v->cur_write_error < v->max_write_error) + v->cur_write_error++; + } + else + { + if (v->cur_write_error > 0) + v->cur_write_error--; + } + } + + + if (wr_rd == ITS_READ_BUS) // read + { + + if (err) + { + if (v->cur_read_error < v->max_read_error) + v->cur_read_error++; + } + else + { + if (v->cur_read_error > 0) + v->cur_read_error--; + } + } + + + if ( (v->cur_write_error >= v->max_write_error) || ( v->cur_read_error >= v->max_read_error) ) + return 1; + + + return 0; +} + + + +int check_cds_ready_pbus(int err, int wr_rd, T_cds_status_parallel_bus *v) +{ + + if (wr_rd == ITS_WRITE_BUS) // write + { + if (err) + { + if (v->cur_write_error < v->max_write_error) + v->cur_write_error++; + } + else + { + if (v->cur_write_error > 0) + v->cur_write_error--; + } + } + + + if (wr_rd == ITS_READ_BUS) // read + { + + if (err) + { + if (v->cur_read_error < v->max_read_error) + v->cur_read_error++; + } + else + { + if (v->cur_read_error > 0) + v->cur_read_error--; + } + } + + + if ( (v->cur_write_error >= v->max_write_error) || ( v->cur_read_error >= v->max_read_error) ) + return 1; + + + return 0; +} + + + +int check_cds_ready_hwpbus(int err, int wr_rd, T_cds_status_hwp_bus *v) +{ + + if (wr_rd == ITS_WRITE_BUS) // write + { + if (err) + { + v->count_write_error++; + if (v->cur_write_error < v->max_write_error) + v->cur_write_error++; + } + else + { + if (v->cur_write_error > 0) + v->cur_write_error--; + v->count_write_ok++; + + } + } + + + if (wr_rd == ITS_READ_BUS) // read + { + + if (err) + { + v->count_read_error++; + if (v->cur_read_error < v->max_read_error) + v->cur_read_error++; + } + else + { + if (v->cur_read_error > 0) + v->cur_read_error--; + v->count_read_ok++; + } + } + + + if ( (v->cur_write_error >= v->max_write_error) || ( v->cur_read_error >= v->max_read_error) ) + return 1; + + + return 0; +} + + + + +void set_status_cds(int err_ready, T_component_status *ss) +{ + + if (err_ready == 0) // all ok + { + if ((*ss == component_NotReady) || (*ss == component_Started)) + *ss = component_Ready; + } + + if (err_ready == 1) // all !bad! + { + *ss = component_ErrorSBus;//component_Error; + } + +} + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_status_bus.h b/Inu/Src/N12_Xilinx/xp_cds_status_bus.h new file mode 100644 index 0000000..092be0e --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_status_bus.h @@ -0,0 +1,95 @@ +#ifndef XP_CDS_STATUS_BUS_H +#define XP_CDS_STATUS_BUS_H + +#include "x_basic_types.h" + +#define ITS_WRITE_BUS 0 +#define ITS_READ_BUS 1 + +#define TYPE_CDS_XILINX_NOT_INITED -1 +#define TYPE_CDS_XILINX_SP2 0 +#define TYPE_CDS_XILINX_SP6 1 + + +#define MAX_WRITE_ERROR_SBUS_DEFAULT 1 // - Ready +#define MAX_READ_ERROR_SBUS_DEFAULT 1 // - Ready + +#define MAX_WRITE_ERROR_PBUS_DEFAULT 1 // - Ready +#define MAX_READ_ERROR_PBUS_DEFAULT 1 // - Ready + +#define MAX_WRITE_ERROR_HWPBUS_DEFAULT 1 // - Ready +#define MAX_READ_ERROR_HWPBUS_DEFAULT 1 // - Ready + +#define T_cds_status_serial_bus_DEFAULT {0,0,0,0,0,0,0,MAX_WRITE_ERROR_SBUS_DEFAULT,MAX_READ_ERROR_SBUS_DEFAULT} +#define T_cds_status_parallel_bus_DEFAULT {0,0,0,0,0,0,0,MAX_WRITE_ERROR_PBUS_DEFAULT,MAX_READ_ERROR_PBUS_DEFAULT} +#define T_cds_status_hwp_bus_DEFAULT {0,0,0,0,0,0,0,MAX_WRITE_ERROR_HWPBUS_DEFAULT,MAX_READ_ERROR_HWPBUS_DEFAULT} + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ + +typedef struct { + UInt16 status; + UInt16 count_read_ok; + UInt16 count_write_ok; + UInt16 count_read_error; + UInt16 count_write_error; + UInt16 cur_read_error; + UInt16 cur_write_error; + UInt16 max_write_error; + UInt16 max_read_error; +} T_cds_status_serial_bus; + + +typedef struct { + UInt16 status; + UInt16 count_read_ok; + UInt16 count_write_ok; + UInt16 count_read_error; + UInt16 count_write_error; + UInt16 cur_read_error; + UInt16 cur_write_error; + UInt16 max_write_error; + UInt16 max_read_error; +} T_cds_status_parallel_bus; + +typedef struct { + UInt16 status; + UInt16 count_read_ok; + UInt16 count_write_ok; + UInt16 count_read_error; + UInt16 count_write_error; + UInt16 cur_read_error; + UInt16 cur_write_error; + UInt16 max_write_error; + UInt16 max_read_error; +} T_cds_status_hwp_bus; + +typedef struct { + UInt16 type_xilinx; +} T_cds_type_xilinx; + + +#define TYPE_CDS_XILINX_DEFAULTS TYPE_CDS_XILINX_NOT_INITED +#define TYPE_IN_1_2_DEFAULTS TYPE_IN_1_2_NOT_INITED + +void clear_stat_sbus(T_cds_status_serial_bus *v); +void clear_stat_pbus(T_cds_status_parallel_bus *v); +void clear_stat_hwpbus(T_cds_status_hwp_bus *v); + +void clear_cur_stat_sbus(T_cds_status_serial_bus *v); +void clear_cur_stat_pbus(T_cds_status_parallel_bus *v); +void clear_cur_stat_hwpbus(T_cds_status_hwp_bus *v); + + +int check_cds_ready_sbus(int err, int wr_rd, T_cds_status_serial_bus *v); +int check_cds_ready_pbus(int err, int wr_rd, T_cds_status_parallel_bus *v); +int check_cds_ready_hwpbus(int err, int wr_rd, T_cds_status_hwp_bus *v); + +void set_status_cds(int err_ready, T_component_status *ss); + + + + +#endif + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk.c b/Inu/Src/N12_Xilinx/xp_cds_tk.c new file mode 100644 index 0000000..6248104 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk.c @@ -0,0 +1,196 @@ +#include "x_parallel_bus.h" +#include "xp_cds_tk.h" + +#include "x_parallel_bus.h" +#include "x_serial_bus.h" +#include "xp_tools.h" +#include "xerror.h" + +/* tk */ + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void cds_tk_init(T_cds_tk *v) +{ +//#if (Cds_Tk_Xilinx_SP6 == 1) && (C_PROJECT_TYPE == PROJECT_22220) + int old_started = 0; + unsigned int i; +//#endif + if (v->useit == 0) + { + clear_adr_sync_table(v->plane_address); + return ; + } + set_adr_sync_table(v->plane_address); + +//#if (Cds_Tk_Xilinx_SP6 == 1) && (C_PROJECT_TYPE == PROJECT_22220) +#if (C_PROJECT_TYPE == PROJECT_22220) || (C_PROJECT_TYPE == PROJECT_23550) + if (v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + if (x_parallel_bus_project.flags.bit.init==0) + x_parallel_bus_project.init(&x_parallel_bus_project); + + + old_started = x_parallel_bus_project.flags.bit.started; + + if (x_parallel_bus_project.flags.bit.started) + x_parallel_bus_project.stop(&x_parallel_bus_project); + + + x_parallel_bus_project.slave_addr = v->plane_address; + + // for (i=0;isetup_pbus.count_elements_pbus;i++) + for (i=0;i<16;i++) + { + if (v->setup_pbus.use_reg_in_pbus.all & (1<adr_pbus.adr_table[i] = x_parallel_bus_project.setup.size_table; + x_parallel_bus_project.add_table(&x_parallel_bus_project); + x_parallel_bus_project.reg_addr++; + x_parallel_bus_project.setup.size_table++; + } + else + { + // !!! + xerror(xparall_bus_er_ID(1),(void *)0); + v->setup_pbus.use_reg_in_pbus.all &= (~(1<useit == 0) + return 0; + + err = v->read_sbus(v); + err |= v->read_pbus(v); + + return err; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + +int cds_tk_write_all(T_cds_tk *v) +{ + int err = 0; + + if (v->useit == 0) + return 0; + + err = v->write_sbus(v); + err |= v->write_pbus(v); + + return err; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_write_pbus(T_cds_tk *v) +{ + if (v->useit == 0) + return 0; + + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_read_pbus(T_cds_tk *v) +{ + if (v->useit == 0) + return 0; + + return 0; +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + +void cds_tk_reset_error(T_cds_tk *v) +{ + if (v->useit == 0) + return ; + + if (v->status == component_Error || v->status == component_ErrorSBus) + v->status = component_Started; + + clear_cur_stat_sbus(&v->status_serial_bus); + clear_cur_stat_pbus(&v->status_parallel_bus); + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//7 cmd_reset_error + + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void cds_tk_store_disable_error(T_cds_tk *v) +{ + if (v->useit == 0) + return ; + + v->store_protect_error = v->write.sbus.protect_error.all; + v->write.sbus.protect_error.all = 0; // disable all error. + + v->write_sbus(v); + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void cds_tk_restore_enable_error(T_cds_tk *v) +{ + if (v->useit == 0) + return ; + + v->write.sbus.protect_error.all = v->store_protect_error; // restore all setup error. + v->write_sbus(v); + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk.h b/Inu/Src/N12_Xilinx/xp_cds_tk.h new file mode 100644 index 0000000..6979039 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk.h @@ -0,0 +1,114 @@ +#ifndef XP_CDS_TK_H +#define XP_CDS_TK_H + + +#include + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_cds_tk_10510.h" +#include "xp_cds_tk_21180.h" +#include "xp_cds_tk_21300.h" +#include "xp_cds_tk_22220.h" +#include "xp_cds_tk_23470.h" +#include "xp_cds_tk_23550.h" +#include "xp_cds_tk_balzam.h" +#include "xp_id_plate_info.h" +#include "xp_plane_adr.h" + + + + + +///////////////////////////////////////////////////////////////// +/*----------------------------------------------------------------------------- +Default initalizer for object. +-----------------------------------------------------------------------------*/ + +#if (C_PROJECT_TYPE == PROJECT_21180) +#define T_cds_tk_DEFAULTS T_cds_tk_DEFAULTS_21180 +#define T_cds_tk T_cds_tk_21180 +typedef T_cds_tk_21180 *T_cds_tk_handle; +#endif + +#if (C_PROJECT_TYPE == PROJECT_23470) +#define T_cds_tk_DEFAULTS T_cds_tk_DEFAULTS_23470 +#define T_cds_tk T_cds_tk_23470 +typedef T_cds_tk_23470 *T_cds_tk_handle; +#endif + +#if (C_PROJECT_TYPE == PROJECT_21300) +#define T_cds_tk_DEFAULTS T_cds_tk_DEFAULTS_21300 +#define T_cds_tk T_cds_tk_21300 +typedef T_cds_tk_21300 *T_cds_tk_handle; +#endif + +#if (C_PROJECT_TYPE == PROJECT_22220) +#define T_cds_tk_DEFAULTS T_cds_tk_DEFAULTS_22220 +#define T_cds_tk T_cds_tk_22220 +typedef T_cds_tk_22220 *T_cds_tk_handle; +#endif + +#if (C_PROJECT_TYPE == PROJECT_BALZAM) +#define T_cds_tk_DEFAULTS T_cds_tk_DEFAULTS_BALZAM +#define T_cds_tk T_cds_tk_balzam +typedef T_cds_tk_balzam *T_cds_tk_handle; +#endif + + +#if (C_PROJECT_TYPE == PROJECT_23550) +#define T_cds_tk_DEFAULTS T_cds_tk_DEFAULTS_23550 +#define T_cds_tk T_cds_tk_23550 +typedef T_cds_tk_23550 *T_cds_tk_handle; +#endif + +#if (C_PROJECT_TYPE == PROJECT_10510) +#define T_cds_tk_DEFAULTS T_cds_tk_DEFAULTS_10510 +#define T_cds_tk T_cds_tk_10510 +typedef T_cds_tk_10510 *T_cds_tk_handle; +#endif + + +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +void cds_tk_init(T_cds_tk_handle); + +int cds_tk_read_all(T_cds_tk_handle); +int cds_tk_write_all(T_cds_tk_handle); +/// +int cds_tk_read_sbus_21300(T_cds_tk_handle_21300); +int cds_tk_write_sbus_21300(T_cds_tk_handle_21300); + +int cds_tk_read_sbus_22220(T_cds_tk_handle_22220); +int cds_tk_write_sbus_22220(T_cds_tk_handle_22220); +int cds_tk_read_pbus_22220(T_cds_tk_handle_22220); + +int cds_tk_read_sbus_balzam(T_cds_tk_handle_balzam); +int cds_tk_write_sbus_balzam(T_cds_tk_handle_balzam); + +int cds_tk_read_sbus_21180(T_cds_tk_handle_21180); +int cds_tk_write_sbus_21180(T_cds_tk_handle_21180); + +int cds_tk_read_sbus_23470(T_cds_tk_handle_23470); +int cds_tk_write_sbus_23470(T_cds_tk_handle_23470); + +int cds_tk_read_sbus_23550(T_cds_tk_handle_23550); +int cds_tk_write_sbus_23550(T_cds_tk_handle_23550); +int cds_tk_read_pbus_23550(T_cds_tk_handle_23550); + +int cds_tk_read_sbus_10510(T_cds_tk_handle_10510); +int cds_tk_write_sbus_10510(T_cds_tk_handle_10510); + + +//// +int cds_tk_read_pbus(T_cds_tk_handle); +int cds_tk_write_pbus(T_cds_tk_handle); + +void cds_tk_reset_error(T_cds_tk_handle); +void cds_tk_store_disable_error(T_cds_tk_handle); +void cds_tk_restore_enable_error(T_cds_tk_handle); + +#endif + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_10510.c b/Inu/Src/N12_Xilinx/xp_cds_tk_10510.c new file mode 100644 index 0000000..1d4ee36 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_10510.c @@ -0,0 +1,280 @@ +#include "x_serial_bus.h" +#include "xp_cds_tk.h" +#include "xp_tools.h" + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +// 10510 +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_write_sbus_10510(T_cds_tk_10510 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_protect_tk.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + +//4 protect_error +// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) +// v->write.sbus.protect_error.bit.enable_err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_tk_out_40pin.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//1 deadtime + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.deadtime.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.ack_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + + + +//7 cmd_reset_error +/* + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_error++; +*/ + +//9 mintime + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mintime.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_read_sbus_10510(T_cds_tk_10510 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_tk_out_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//1 deadtime + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.deadtime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.ack_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_protect_tk.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//4 protect_error + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//5 status_tk_40pin + x_serial_bus_project.reg_addr = 5; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//6 status_tk_96pin + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_96pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//8 status_protect_current_ack + x_serial_bus_project.reg_addr = 8; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_current_ack.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//9 mintime + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mintime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//10 status_protect_deadtime_mintime + x_serial_bus_project.reg_addr = 10; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_deadtime_mintime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//11 time_err_tk0_tk1 + x_serial_bus_project.reg_addr = 11; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk0_tk1 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//12 time_err_tk2_tk3 + x_serial_bus_project.reg_addr = 12; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk2_tk3 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//13 time_err_tk4_tk5 + x_serial_bus_project.reg_addr = 13; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk4_tk5 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//14 time_err_tk6_tk7 + x_serial_bus_project.reg_addr = 14; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk6_tk7 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + + +/////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_10510.h b/Inu/Src/N12_Xilinx/xp_cds_tk_10510.h new file mode 100644 index 0000000..2de6424 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_10510.h @@ -0,0 +1,460 @@ +#ifndef XP_CDS_TK_10510_H +#define XP_CDS_TK_10510_H + + +#include + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//// 10510 +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + +#define T_CDS_TK_COUNT_ADR_PBUS_10510 0 // count max elements in parallel bus + +#define T_CDS_TK_SETUP_USE_ADR_PBUS_10510 0x0 // - PBUS, 0xffff - + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) fclk=50000kHz + UInt16 enable :1; + } bit; + } deadtime; + +//2 + union + { + UInt16 all; + struct + { + UInt16 time0 :8; + UInt16 delay :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + UInt16 cmd_reset_error; +//9 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) - 2 fclk=50000kHz + UInt16 enable :1; + } bit; + } mintime; +// + +} T_cds_tk_write_sbus_10510; + +#define T_CDS_TK_WRITE_SBUS_DEFAULTS_10510 {0x0000,0x5f5f,0x0909,0x0000,0x0000,0x0000, 0x0105}//{0,0,0,0,0,0,0} + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) fclk=50000kHz + UInt16 reserv :1; + } bit; + } deadtime; + +//2 + union + { + UInt16 all; + struct + { + UInt16 time0 :8; + UInt16 delay :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//5 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + } bit; + } status_tk_40pin; +//6 + union + { + UInt16 all; + struct + { + UInt16 tk0_a4 :1; + UInt16 tk1_b4 :1; + UInt16 tk2_c4 :1; + UInt16 tk3_a5 :1; + UInt16 tk4_b5 :1; + UInt16 tk5_c5 :1; + UInt16 tk6_a6 :1; + UInt16 tk7_b6 :1; + UInt16 tk8_c6 :1; + UInt16 tk9_a7 :1; + UInt16 tk10_b7 :1; + UInt16 tk11_c7 :1; + UInt16 tk12_a8 :1; + UInt16 tk13_b8 :1; + UInt16 tk14_a9 :1; + UInt16 tk15_b9 :1; + } bit; + } status_tk_96pin; +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; +//8 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } status_protect_current_ack; +//9 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) + 2 fclk=50000kHz + UInt16 enable :1; + } bit; + } mintime; +//10 + union + { + UInt16 all; + struct + { + UInt16 tk0_deadtime :1; + UInt16 tk1_deadtime :1; + UInt16 tk2_deadtime :1; + UInt16 tk3_deadtime :1; + UInt16 tk4_deadtime :1; + UInt16 tk5_deadtime :1; + UInt16 tk6_deadtime :1; + UInt16 tk7_deadtime :1; + UInt16 tk0_mintime :1; + UInt16 tk1_mintime :1; + UInt16 tk2_mintime :1; + UInt16 tk3_mintime :1; + UInt16 tk4_mintime :1; + UInt16 tk5_mintime :1; + UInt16 tk6_mintime :1; + UInt16 tk7_mintime :1; + } bit; + } status_protect_deadtime_mintime; +//11 + UInt16 time_err_tk0_tk1; +//12 + UInt16 time_err_tk2_tk3; +//13 + UInt16 time_err_tk4_tk5; +//14 + UInt16 time_err_tk6_tk7; +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + + +} T_cds_tk_read_sbus_10510; + + +#define T_CDS_TK_READ_SBUS_DEFAULTS_10510 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} + + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//setup parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 count_elements_pbus; +// use_or_not? + union + { + UInt16 all; + struct{ + UInt16 res : 16; + }bit; + } use_reg_in_pbus; + +} T_cds_tk_setup_pbus_10510; + +#define T_CDS_TK_SETUP_PBUS_DEFAULTS_10510 {T_CDS_TK_COUNT_ADR_PBUS_10510,T_CDS_TK_SETUP_USE_ADR_PBUS_10510} +////////////////////////////////////////////////////////////// + + + +///////////////////////////////////////////////////////////////// + + +typedef struct{ + T_cds_tk_write_sbus_10510 sbus; +} T_cds_tk_write_10510; + +typedef struct{ + T_cds_tk_read_sbus_10510 sbus; + Int16 type_cds_xilinx; +} T_cds_tk_read_10510; + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +typedef struct { + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + T_cds_tk_setup_pbus_10510 setup_pbus; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_tk_write_10510 write; + T_cds_tk_read_10510 read; + + UInt16 store_protect_error; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + +} T_cds_tk_10510; + + + + +#define T_cds_tk_DEFAULTS_10510 { 0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_CDS_TK_SETUP_PBUS_DEFAULTS_10510, \ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + {T_CDS_TK_WRITE_SBUS_DEFAULTS_10510},\ + {T_CDS_TK_READ_SBUS_DEFAULTS_10510,TYPE_CDS_XILINX_DEFAULTS},\ + 0, \ + (void (*)(Uint32))cds_tk_init, \ + (int (*)(Uint32))cds_tk_read_all, \ + (int (*)(Uint32))cds_tk_write_all, \ + (int (*)(Uint32))cds_tk_read_sbus_10510, \ + (int (*)(Uint32))cds_tk_write_sbus_10510, \ + (int (*)(Uint32))cds_tk_read_pbus, \ + (int (*)(Uint32))cds_tk_write_pbus, \ + (void (*)(Uint32))cds_tk_reset_error, \ + (void (*)(Uint32))cds_tk_store_disable_error, \ + (void (*)(Uint32))cds_tk_restore_enable_error \ + } + + +typedef T_cds_tk_10510 *T_cds_tk_handle_10510; + + + +#endif // XP_CDS_TK_10510_H + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_21180.c b/Inu/Src/N12_Xilinx/xp_cds_tk_21180.c new file mode 100644 index 0000000..fa39ccf --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_21180.c @@ -0,0 +1,280 @@ +#include "x_serial_bus.h" +#include "xp_cds_tk.h" +#include "xp_tools.h" + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +// 21180 +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_write_sbus_21180(T_cds_tk_21180 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_protect_tk.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + +//4 protect_error +// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) +// v->write.sbus.protect_error.bit.enable_err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_tk_out_40pin.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//1 deadtime + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.deadtime.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.ack_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + + + +//7 cmd_reset_error +/* + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_error++; +*/ + +//9 mintime + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mintime.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_read_sbus_21180(T_cds_tk_21180 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_tk_out_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//1 deadtime + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.deadtime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.ack_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_protect_tk.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//4 protect_error + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//5 status_tk_40pin + x_serial_bus_project.reg_addr = 5; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//6 status_tk_96pin + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_96pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//8 status_protect_current_ack + x_serial_bus_project.reg_addr = 8; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_current_ack.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//9 mintime + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mintime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//10 status_protect_deadtime_mintime + x_serial_bus_project.reg_addr = 10; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_deadtime_mintime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//11 time_err_tk0_tk2 + x_serial_bus_project.reg_addr = 11; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk0_tk2 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//12 time_err_tk2_tk3 + x_serial_bus_project.reg_addr = 12; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk1_tk3 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//13 time_err_tk4_tk5 + x_serial_bus_project.reg_addr = 13; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk4_tk6 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//14 time_err_tk6_tk7 + x_serial_bus_project.reg_addr = 14; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk5_tk7 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + + +/////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_21180.h b/Inu/Src/N12_Xilinx/xp_cds_tk_21180.h new file mode 100644 index 0000000..a9b6063 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_21180.h @@ -0,0 +1,459 @@ +#ifndef XP_CDS_TK_21180_H +#define XP_CDS_TK_21180_H + + +#include + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//// 21180 +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + + +#define T_CDS_TK_COUNT_ADR_PBUS_21180 0 // count max elements in parallel bus + +#define T_CDS_TK_SETUP_USE_ADR_PBUS_21180 0x0 // - PBUS, 0xffff - + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) fclk=50000kHz + UInt16 enable :1; + } bit; + } deadtime; + +//2 + union + { + UInt16 all; + struct + { + UInt16 time0 :8; + UInt16 delay :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + UInt16 cmd_reset_error; +//9 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) - 2 fclk=50000kHz + UInt16 enable :1; + } bit; + } mintime; +// + +} T_cds_tk_write_sbus_21180; + +#define T_CDS_TK_WRITE_SBUS_DEFAULTS_21180 {0x0000,0x5f5f,0x0909,0x0000,0x0000,0x0000, 0x0105}//{0,0,0,0,0,0,0} + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) fclk=50000kHz + UInt16 reserv :1; + } bit; + } deadtime; + +//2 + union + { + UInt16 all; + struct + { + UInt16 time0 :8; + UInt16 delay :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//5 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + } bit; + } status_tk_40pin; +//6 + union + { + UInt16 all; + struct + { + UInt16 tk0_a4 :1; + UInt16 tk1_b4 :1; + UInt16 tk2_c4 :1; + UInt16 tk3_a5 :1; + UInt16 tk4_b5 :1; + UInt16 tk5_c5 :1; + UInt16 tk6_a6 :1; + UInt16 tk7_b6 :1; + UInt16 tk8_c6 :1; + UInt16 tk9_a7 :1; + UInt16 tk10_b7 :1; + UInt16 tk11_c7 :1; + UInt16 tk12_a8 :1; + UInt16 tk13_b8 :1; + UInt16 tk14_a9 :1; + UInt16 tk15_b9 :1; + } bit; + } status_tk_96pin; +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; +//8 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } status_protect_current_ack; +//9 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) + 2 fclk=50000kHz + UInt16 enable :1; + } bit; + } mintime; +//10 + union + { + UInt16 all; + struct + { + UInt16 tk0_deadtime :1; + UInt16 tk1_deadtime :1; + UInt16 tk2_deadtime :1; + UInt16 tk3_deadtime :1; + UInt16 tk4_deadtime :1; + UInt16 tk5_deadtime :1; + UInt16 tk6_deadtime :1; + UInt16 tk7_deadtime :1; + UInt16 tk0_mintime :1; + UInt16 tk1_mintime :1; + UInt16 tk2_mintime :1; + UInt16 tk3_mintime :1; + UInt16 tk4_mintime :1; + UInt16 tk5_mintime :1; + UInt16 tk6_mintime :1; + UInt16 tk7_mintime :1; + } bit; + } status_protect_deadtime_mintime; +//11 + UInt16 time_err_tk0_tk2; +//12 + UInt16 time_err_tk1_tk3; +//13 + UInt16 time_err_tk4_tk6; +//14 + UInt16 time_err_tk5_tk7; +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + + +} T_cds_tk_read_sbus_21180; + + +#define T_CDS_TK_READ_SBUS_DEFAULTS_21180 {0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0} + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//setup parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 count_elements_pbus; +// use_or_not? + union + { + UInt16 all; + struct{ + UInt16 res : 16; + }bit; + } use_reg_in_pbus; + +} T_cds_tk_setup_pbus_21180; + +#define T_CDS_TK_SETUP_PBUS_DEFAULTS_21180 {T_CDS_TK_COUNT_ADR_PBUS_21180,T_CDS_TK_SETUP_USE_ADR_PBUS_21180} +////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////// + + +typedef struct{ + T_cds_tk_write_sbus_21180 sbus; +} T_cds_tk_write_21180; + +typedef struct{ + T_cds_tk_read_sbus_21180 sbus; + Int16 type_cds_xilinx; +} T_cds_tk_read_21180; + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +typedef struct { + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + T_cds_tk_setup_pbus_21180 setup_pbus; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_tk_write_21180 write; + T_cds_tk_read_21180 read; + + UInt16 store_protect_error; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + +} T_cds_tk_21180; + + + + + +#define T_cds_tk_DEFAULTS_21180 { 0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_CDS_TK_SETUP_PBUS_DEFAULTS_21180, \ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + {T_CDS_TK_WRITE_SBUS_DEFAULTS_21180},\ + {T_CDS_TK_READ_SBUS_DEFAULTS_21180,TYPE_CDS_XILINX_DEFAULTS},\ + 0, \ + (void (*)(Uint32))cds_tk_init, \ + (int (*)(Uint32))cds_tk_read_all, \ + (int (*)(Uint32))cds_tk_write_all, \ + (int (*)(Uint32))cds_tk_read_sbus_21180, \ + (int (*)(Uint32))cds_tk_write_sbus_21180, \ + (int (*)(Uint32))cds_tk_read_pbus, \ + (int (*)(Uint32))cds_tk_write_pbus, \ + (void (*)(Uint32))cds_tk_reset_error, \ + (void (*)(Uint32))cds_tk_store_disable_error, \ + (void (*)(Uint32))cds_tk_restore_enable_error \ + } + + + +typedef T_cds_tk_21180 *T_cds_tk_handle_21180; + + +#endif // XP_CDS_TK_21180_H + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_21300.c b/Inu/Src/N12_Xilinx/xp_cds_tk_21300.c new file mode 100644 index 0000000..662fa78 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_21300.c @@ -0,0 +1,280 @@ +#include "x_serial_bus.h" +#include "xp_cds_tk.h" +#include "xp_tools.h" + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +// 21300 +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_write_sbus_21300(T_cds_tk_21300 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_protect_tk.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + +//4 protect_error +// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) +// v->write.sbus.protect_error.bit.enable_err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_tk_out_40pin.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//1 deadtime + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.deadtime.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.ack_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + + + +//7 cmd_reset_error +/* + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_error++; +*/ + +//9 mintime + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mintime.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_read_sbus_21300(T_cds_tk_21300 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_tk_out_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//1 deadtime + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.deadtime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.ack_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_protect_tk.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//4 protect_error + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//5 status_tk_40pin + x_serial_bus_project.reg_addr = 5; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//6 status_tk_96pin + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_96pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//8 status_protect_current_ack + x_serial_bus_project.reg_addr = 8; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_current_ack.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//9 mintime + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mintime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//10 status_protect_deadtime_mintime + x_serial_bus_project.reg_addr = 10; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_deadtime_mintime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//11 time_err_tk0_tk1 + x_serial_bus_project.reg_addr = 11; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk0_tk1 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//12 time_err_tk2_tk3 + x_serial_bus_project.reg_addr = 12; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk2_tk3 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//13 time_err_tk4_tk5 + x_serial_bus_project.reg_addr = 13; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk4_tk5 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//14 time_err_tk6_tk7 + x_serial_bus_project.reg_addr = 14; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk6_tk7 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + + +/////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_21300.h b/Inu/Src/N12_Xilinx/xp_cds_tk_21300.h new file mode 100644 index 0000000..5b91533 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_21300.h @@ -0,0 +1,460 @@ +#ifndef XP_CDS_TK_21300_H +#define XP_CDS_TK_21300_H + + +#include + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//// 21300 +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + +#define T_CDS_TK_COUNT_ADR_PBUS_21300 0 // count max elements in parallel bus + +#define T_CDS_TK_SETUP_USE_ADR_PBUS_21300 0x0 // - PBUS, 0xffff - + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) fclk=50000kHz + UInt16 enable :1; + } bit; + } deadtime; + +//2 + union + { + UInt16 all; + struct + { + UInt16 time0 :8; + UInt16 delay :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + UInt16 cmd_reset_error; +//9 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) - 2 fclk=50000kHz + UInt16 enable :1; + } bit; + } mintime; +// + +} T_cds_tk_write_sbus_21300; + +#define T_CDS_TK_WRITE_SBUS_DEFAULTS_21300 {0x0000,0x5f5f,0x0909,0x0000,0x0000,0x0000, 0x0105}//{0,0,0,0,0,0,0} + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) fclk=50000kHz + UInt16 reserv :1; + } bit; + } deadtime; + +//2 + union + { + UInt16 all; + struct + { + UInt16 time0 :8; + UInt16 delay :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//5 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + } bit; + } status_tk_40pin; +//6 + union + { + UInt16 all; + struct + { + UInt16 tk0_a4 :1; + UInt16 tk1_b4 :1; + UInt16 tk2_c4 :1; + UInt16 tk3_a5 :1; + UInt16 tk4_b5 :1; + UInt16 tk5_c5 :1; + UInt16 tk6_a6 :1; + UInt16 tk7_b6 :1; + UInt16 tk8_c6 :1; + UInt16 tk9_a7 :1; + UInt16 tk10_b7 :1; + UInt16 tk11_c7 :1; + UInt16 tk12_a8 :1; + UInt16 tk13_b8 :1; + UInt16 tk14_a9 :1; + UInt16 tk15_b9 :1; + } bit; + } status_tk_96pin; +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; +//8 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } status_protect_current_ack; +//9 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) + 2 fclk=50000kHz + UInt16 enable :1; + } bit; + } mintime; +//10 + union + { + UInt16 all; + struct + { + UInt16 tk0_deadtime :1; + UInt16 tk1_deadtime :1; + UInt16 tk2_deadtime :1; + UInt16 tk3_deadtime :1; + UInt16 tk4_deadtime :1; + UInt16 tk5_deadtime :1; + UInt16 tk6_deadtime :1; + UInt16 tk7_deadtime :1; + UInt16 tk0_mintime :1; + UInt16 tk1_mintime :1; + UInt16 tk2_mintime :1; + UInt16 tk3_mintime :1; + UInt16 tk4_mintime :1; + UInt16 tk5_mintime :1; + UInt16 tk6_mintime :1; + UInt16 tk7_mintime :1; + } bit; + } status_protect_deadtime_mintime; +//11 + UInt16 time_err_tk0_tk1; +//12 + UInt16 time_err_tk2_tk3; +//13 + UInt16 time_err_tk4_tk5; +//14 + UInt16 time_err_tk6_tk7; +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + + +} T_cds_tk_read_sbus_21300; + + +#define T_CDS_TK_READ_SBUS_DEFAULTS_21300 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} + + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//setup parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 count_elements_pbus; +// use_or_not? + union + { + UInt16 all; + struct{ + UInt16 res : 16; + }bit; + } use_reg_in_pbus; + +} T_cds_tk_setup_pbus_21300; + +#define T_CDS_TK_SETUP_PBUS_DEFAULTS_21300 {T_CDS_TK_COUNT_ADR_PBUS_21300,T_CDS_TK_SETUP_USE_ADR_PBUS_21300} +////////////////////////////////////////////////////////////// + + + +///////////////////////////////////////////////////////////////// + + +typedef struct{ + T_cds_tk_write_sbus_21300 sbus; +} T_cds_tk_write_21300; + +typedef struct{ + T_cds_tk_read_sbus_21300 sbus; + Int16 type_cds_xilinx; +} T_cds_tk_read_21300; + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +typedef struct { + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + T_cds_tk_setup_pbus_21300 setup_pbus; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_tk_write_21300 write; + T_cds_tk_read_21300 read; + + UInt16 store_protect_error; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + +} T_cds_tk_21300; + + + + +#define T_cds_tk_DEFAULTS_21300 { 0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_CDS_TK_SETUP_PBUS_DEFAULTS_21300, \ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + {T_CDS_TK_WRITE_SBUS_DEFAULTS_21300},\ + {T_CDS_TK_READ_SBUS_DEFAULTS_21300,TYPE_CDS_XILINX_DEFAULTS},\ + 0, \ + (void (*)(Uint32))cds_tk_init, \ + (int (*)(Uint32))cds_tk_read_all, \ + (int (*)(Uint32))cds_tk_write_all, \ + (int (*)(Uint32))cds_tk_read_sbus_21300, \ + (int (*)(Uint32))cds_tk_write_sbus_21300, \ + (int (*)(Uint32))cds_tk_read_pbus, \ + (int (*)(Uint32))cds_tk_write_pbus, \ + (void (*)(Uint32))cds_tk_reset_error, \ + (void (*)(Uint32))cds_tk_store_disable_error, \ + (void (*)(Uint32))cds_tk_restore_enable_error \ + } + + +typedef T_cds_tk_21300 *T_cds_tk_handle_21300; + + + +#endif // XP_CDS_TK_21300_H + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_22220.c b/Inu/Src/N12_Xilinx/xp_cds_tk_22220.c new file mode 100644 index 0000000..8c87148 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_22220.c @@ -0,0 +1,302 @@ +#include "x_parallel_bus.h" +#include "x_serial_bus.h" +#include "xp_cds_tk.h" +#include "xp_tools.h" + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +// 22220 +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_write_sbus_22220(T_cds_tk_22220 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_protect_tk.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + +//4 protect_error +// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) +// v->write.sbus.protect_error.bit.enable_err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_tk_out_40pin.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//1 dead_min_time + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.dead_min_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.ack_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + + + + +//7 cmd_reset_error +/* + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_error++; +*/ + +//9 delay_ack_ignore + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.filter_time_current_protect.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_read_sbus_22220(T_cds_tk_22220 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_tk_out_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//1 dead_min_time + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.dead_min_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.ack_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_protect_tk.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//4 protect_error + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//5 status_tk_40pin + x_serial_bus_project.reg_addr = 5; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//6 status_tk_96pin + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_96pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//8 status_protect_current_ack + x_serial_bus_project.reg_addr = 8; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_current_ack.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//9 delay_ack_ignore + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.filter_time_current_protect.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//11 time_err_tk_all + x_serial_bus_project.reg_addr = 11; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk_all.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + +/////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_read_pbus_22220(T_cds_tk_22220 *v) +{ + if (v->useit == 0) + return 0; + +//#if (Cds_Tk_Xilinx_SP6 == 1) && (C_PROJECT_TYPE == PROJECT_22220) + if (v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { +//0 + if (v->setup_pbus.use_reg_in_pbus.bit.reg0) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[0]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.DataReg0.all = x_parallel_bus_project.data_table_read; + } +//1 + if (v->setup_pbus.use_reg_in_pbus.bit.reg1) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[1]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.DataReg1.all = x_parallel_bus_project.data_table_read; + } + +//2 + if (v->setup_pbus.use_reg_in_pbus.bit.reg2) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[2]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.DataReg2.all = x_parallel_bus_project.data_table_read; + } + +//3 + if (v->setup_pbus.use_reg_in_pbus.bit.reg3) + { + x_parallel_bus_project.adr_table_read = v->adr_pbus.adr_table[3]; + x_parallel_bus_project.read_one_data(&x_parallel_bus_project); + v->read.pbus.DataReg3.all = x_parallel_bus_project.data_table_read; + } + } +//#endif + + return 0; +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_22220.h b/Inu/Src/N12_Xilinx/xp_cds_tk_22220.h new file mode 100644 index 0000000..6e322ca --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_22220.h @@ -0,0 +1,539 @@ +#ifndef XP_CDS_TK_22220_H +#define XP_CDS_TK_22220_H + + +#include + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//// 22220 +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//#define Cds_Tk_Xilinx_SP6 0 + +//#if Cds_Tk_Xilinx_SP6 == 1 +#define T_CDS_TK_COUNT_ADR_PBUS_22220 4 // count max elements in parallel bus +//#else +// #define T_CDS_TK_COUNT_ADR_PBUS_22220 0 // count max elements in parallel bus +//#endif //Cds_Tk_Xilinx_SP6 + +#define T_CDS_TK_SETUP_USE_ADR_PBUS_22220 0xffff // - PBUS, 0xffff - + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 mintime :8; // N=mintime * fclk fclk=5000kHz + UInt16 deadtime :8; // N=deadtime * fclk fclk=5000kHz + } bit; + } dead_min_time; +//2 + union + { + UInt16 all; + struct + { + UInt16 delay_off :8; + UInt16 delay_on :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :5; + UInt16 enable_mask_err_serial_2 :1; // for SP6 + UInt16 enable_uksi_serial_2 :1; // for SP6 + UInt16 enable_mask_err_serial_1 :1; // for SP6 + UInt16 enable_uksi_serial_1 :1; // for SP6 + UInt16 reserv9 :1; + UInt16 enable_line_err :1; + UInt16 disable_err_mintime :1; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + UInt16 cmd_reset_error; +//9 + union + { + UInt16 all; + struct + { + UInt16 filter_time :8; // fclk=5000kHz + UInt16 reserv :8; // + } bit; + } filter_time_current_protect; + +// + +} T_cds_tk_write_sbus_22220; + +#define T_CDS_TK_WRITE_SBUS_DEFAULTS_22220 {0x0000,0x5f5f,0x0909,0x0000,0x0000,0x0000,0x0105} + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; + +//1 + union + { + UInt16 all; + struct + { + UInt16 mintime :8; // N=mintime * fclk fclk=5000kHz + UInt16 deadtime :8; // N=deadtime * fclk fclk=5000kHz + } bit; + } dead_min_time; + +//2 + union + { + UInt16 all; + struct + { + UInt16 delay_off :8; + UInt16 delay_on :8; + } bit; + } ack_time; + +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; + +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :5; + UInt16 enable_mask_err_serial_2 :1; // for SP6 + UInt16 enable_uksi_serial_2 :1; // for SP6 + UInt16 enable_mask_err_serial_1 :1; // for SP6 + UInt16 enable_uksi_serial_1 :1; // for SP6 + UInt16 reserv9 :1; + UInt16 enable_line_err :1; + UInt16 disable_err_mintime :1; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; + +//5 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + } bit; + } status_tk_40pin; + +//6 + union + { + UInt16 all; + struct + { + UInt16 tk0_a4 :1; + UInt16 tk1_b4 :1; + UInt16 tk2_c4 :1; + UInt16 tk3_a5 :1; + UInt16 tk4_b5 :1; + UInt16 tk5_c5 :1; + UInt16 tk6_a6 :1; + UInt16 tk7_b6 :1; + UInt16 tk8_c6 :1; + UInt16 tk9_a7 :1; + UInt16 tk10_b7 :1; + UInt16 tk11_c7 :1; + UInt16 tk12_a8 :1; + UInt16 tk13_b8 :1; + UInt16 tk14_a9 :1; + UInt16 tk15_b9 :1; + } bit; + } status_tk_96pin; + +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :5; + UInt16 sp6_err_recive_serial_2 :1; // for SP6 + UInt16 sp6_err_recive_serial_1 :1; // for SP6 + UInt16 line_err_keys_3210 :1; + UInt16 line_err_keys_7654 :1; + UInt16 mintime_err_keys_3210 :1; + UInt16 mintime_err_keys_7654 :1; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; + +//8 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } status_protect_current_ack; + +//9 + union + { + UInt16 all; + struct + { + UInt16 filter_time :8; // fclk=5000kHz + UInt16 reserv :8; // fclk=5000kHz + } bit; + } filter_time_current_protect; + +//11 + union + { + UInt16 all; + struct + { + UInt16 tk_3210 :8; + UInt16 tk_7654 :8; + } bit; + } time_err_tk_all; + +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :9; + UInt16 sp6_err_recive_UKSI_2 :1; + UInt16 sp6_err_recive_UKSI_1 :1; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + +} T_cds_tk_read_sbus_22220; + + +#define T_CDS_TK_READ_SBUS_DEFAULTS_22220 {0,0,0,0,0,0,0,0,0,0,0,0} + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + + +typedef struct { + //0 + union { + UInt16 all; + struct { + UInt16 UKSI_upper_bits:15; + UInt16 parity_bit:1; + } bit; + } DataReg0; + //1 + union { + UInt16 all; + struct { + UInt16 reserved:6; + UInt16 UKSI_upper_bits:9; + UInt16 parity_bit:1; + } bit; + } DataReg1; + //2 + union { + UInt16 all; + struct { + UInt16 UKSI_upper_bits:15; + UInt16 parity_bit:1; + } bit; + } DataReg2; + //3 + union { + UInt16 all; + struct { + UInt16 reserved:6; + UInt16 UKSI_upper_bits:9; + UInt16 parity_bit:1; + } bit; + } DataReg3; +} T_cds_tk_read_pbus_22220; + +#define T_CDS_TK_READ_PBUS_DEFAULTS_22220 {0,0,0,0} + + +///////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//setup parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 count_elements_pbus; +// use_or_not? + union + { + UInt16 all; + struct{ + UInt16 reg0 : 1; + UInt16 reg1 : 1; + UInt16 reg2 : 1; + UInt16 reg3 : 1; + + UInt16 res : 12; + }bit; + } use_reg_in_pbus; + +} T_cds_tk_setup_pbus_22220; + +#define T_CDS_TK_SETUP_PBUS_DEFAULTS_22220 {T_CDS_TK_COUNT_ADR_PBUS_22220,T_CDS_TK_SETUP_USE_ADR_PBUS_22220} +////////////////////////////////////////////////////////////// + + + + +typedef struct{ + T_cds_tk_write_sbus_22220 sbus; +} T_cds_tk_write_22220; + +typedef struct{ + T_cds_tk_read_sbus_22220 sbus; + T_cds_tk_read_pbus_22220 pbus; + Int16 type_cds_xilinx; +} T_cds_tk_read_22220; + +#define T_CDS_TK_READ_DEFAULTS_22220 {T_CDS_TK_READ_SBUS_DEFAULTS_22220,T_CDS_TK_READ_PBUS_DEFAULTS_22220,TYPE_CDS_XILINX_DEFAULTS} + +typedef struct { + UInt16 adr_table[T_CDS_TK_COUNT_ADR_PBUS_22220]; +} T_cds_tk_adr_pbus_22220; + +#define T_CDS_TK_ADR_PBUS_DEFAULTS_22220 {0,0,0,0} + + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +typedef struct { + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + T_cds_tk_setup_pbus_22220 setup_pbus; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_tk_write_22220 write; + T_cds_tk_read_22220 read; +//#if Cds_Tk_Xilinx_SP6 == 1 + T_cds_tk_adr_pbus_22220 adr_pbus; +//#endif + UInt16 store_protect_error; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + +} T_cds_tk_22220; + + + +#define T_cds_tk_DEFAULTS_22220 {0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_CDS_TK_SETUP_PBUS_DEFAULTS_22220,\ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + {T_CDS_TK_WRITE_SBUS_DEFAULTS_22220},\ + T_CDS_TK_READ_DEFAULTS_22220,\ + T_CDS_TK_ADR_PBUS_DEFAULTS_22220,\ + 0,\ + (void (*)(Uint32))cds_tk_init,\ + (int (*)(Uint32))cds_tk_read_all,\ + (int (*)(Uint32))cds_tk_write_all,\ + (int (*)(Uint32))cds_tk_read_sbus_22220,\ + (int (*)(Uint32))cds_tk_write_sbus_22220,\ + (int (*)(Uint32))cds_tk_read_pbus_22220,\ + (int (*)(Uint32))cds_tk_write_pbus,\ + (void (*)(Uint32))cds_tk_reset_error,\ + (void (*)(Uint32))cds_tk_store_disable_error,\ + (void (*)(Uint32))cds_tk_restore_enable_error\ + } + + + + + + +typedef T_cds_tk_22220 *T_cds_tk_handle_22220; + + +#endif // XP_CDS_TK_22220_H diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_23470.c b/Inu/Src/N12_Xilinx/xp_cds_tk_23470.c new file mode 100644 index 0000000..a9a4aa2 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_23470.c @@ -0,0 +1,280 @@ +#include "x_serial_bus.h" +#include "xp_cds_tk.h" +#include "xp_tools.h" + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +// 21180 +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_write_sbus_23470(T_cds_tk_23470 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_protect_tk.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + +//4 protect_error +// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) +// v->write.sbus.protect_error.bit.enable_err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_tk_out_40pin.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//1 deadtime + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.deadtime.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.ack_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + + + +//7 cmd_reset_error +/* + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_error++; +*/ + +//9 mintime + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mintime.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_read_sbus_23470(T_cds_tk_23470 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_tk_out_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//1 deadtime + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.deadtime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.ack_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_protect_tk.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//4 protect_error + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//5 status_tk_40pin + x_serial_bus_project.reg_addr = 5; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//6 status_tk_96pin + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_96pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//8 status_protect_current_ack + x_serial_bus_project.reg_addr = 8; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_current_ack.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//9 mintime + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mintime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//10 status_protect_deadtime_mintime + x_serial_bus_project.reg_addr = 10; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_deadtime_mintime.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//11 time_err_tk0_tk1 + x_serial_bus_project.reg_addr = 11; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk0_tk1 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; +//12 time_err_tk2_tk3 + x_serial_bus_project.reg_addr = 12; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk2_tk3 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//13 time_err_tk4_tk5 + x_serial_bus_project.reg_addr = 13; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk4_tk5 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//14 time_err_tk6_tk7 + x_serial_bus_project.reg_addr = 14; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk6_tk7 = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + + +/////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_23470.h b/Inu/Src/N12_Xilinx/xp_cds_tk_23470.h new file mode 100644 index 0000000..9c19268 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_23470.h @@ -0,0 +1,459 @@ +#ifndef XP_CDS_TK_23470_H +#define XP_CDS_TK_23470_H + + +#include + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//// 23470 +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + +#define T_CDS_TK_COUNT_ADR_PBUS_23470 0 // count max elements in parallel bus + +#define T_CDS_TK_SETUP_USE_ADR_PBUS_23470 0x0 // - PBUS, 0xffff - + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) fclk=50000kHz + UInt16 enable :1; + } bit; + } deadtime; + +//2 + union + { + UInt16 all; + struct + { + UInt16 time0 :8; + UInt16 delay :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + UInt16 cmd_reset_error; +//9 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) - 2 fclk=50000kHz + UInt16 enable :1; + } bit; + } mintime; +// + +} T_cds_tk_write_sbus_23470; + +#define T_CDS_TK_WRITE_SBUS_DEFAULTS_23470 {0x0000,0x5f5f,0x0909,0x0000,0x0000,0x0000, 0x0105}//{0,0,0,0,0,0,0} + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) fclk=50000kHz + UInt16 reserv :1; + } bit; + } deadtime; + +//2 + union + { + UInt16 all; + struct + { + UInt16 time0 :8; + UInt16 delay :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :12; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//5 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + } bit; + } status_tk_40pin; +//6 + union + { + UInt16 all; + struct + { + UInt16 tk0_a4 :1; + UInt16 tk1_b4 :1; + UInt16 tk2_c4 :1; + UInt16 tk3_a5 :1; + UInt16 tk4_b5 :1; + UInt16 tk5_c5 :1; + UInt16 tk6_a6 :1; + UInt16 tk7_b6 :1; + UInt16 tk8_c6 :1; + UInt16 tk9_a7 :1; + UInt16 tk10_b7 :1; + UInt16 tk11_c7 :1; + UInt16 tk12_a8 :1; + UInt16 tk13_b8 :1; + UInt16 tk14_a9 :1; + UInt16 tk15_b9 :1; + } bit; + } status_tk_96pin; +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; +//8 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } status_protect_current_ack; +//9 + union + { + UInt16 all; + struct + { + UInt16 value :15; // N=(mintime * fclk) + 2 fclk=50000kHz + UInt16 enable :1; + } bit; + } mintime; +//10 + union + { + UInt16 all; + struct + { + UInt16 tk0_deadtime :1; + UInt16 tk1_deadtime :1; + UInt16 tk2_deadtime :1; + UInt16 tk3_deadtime :1; + UInt16 tk4_deadtime :1; + UInt16 tk5_deadtime :1; + UInt16 tk6_deadtime :1; + UInt16 tk7_deadtime :1; + UInt16 tk0_mintime :1; + UInt16 tk1_mintime :1; + UInt16 tk2_mintime :1; + UInt16 tk3_mintime :1; + UInt16 tk4_mintime :1; + UInt16 tk5_mintime :1; + UInt16 tk6_mintime :1; + UInt16 tk7_mintime :1; + } bit; + } status_protect_deadtime_mintime; +//11 + UInt16 time_err_tk0_tk1; +//12 + UInt16 time_err_tk2_tk3; +//13 + UInt16 time_err_tk4_tk5; +//14 + UInt16 time_err_tk6_tk7; +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + + +} T_cds_tk_read_sbus_23470; + + +#define T_CDS_TK_READ_SBUS_DEFAULTS_23470 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} + + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//setup parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 count_elements_pbus; +// use_or_not? + union + { + UInt16 all; + struct{ + UInt16 res : 16; + }bit; + } use_reg_in_pbus; + +} T_cds_tk_setup_pbus_23470; + +#define T_CDS_TK_SETUP_PBUS_DEFAULTS_23470 {T_CDS_TK_COUNT_ADR_PBUS_23470,T_CDS_TK_SETUP_USE_ADR_PBUS_23470} +////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////// + + +typedef struct{ + T_cds_tk_write_sbus_23470 sbus; +} T_cds_tk_write_23470; + +typedef struct{ + T_cds_tk_read_sbus_23470 sbus; + Int16 type_cds_xilinx; +} T_cds_tk_read_23470; + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +typedef struct { + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + T_cds_tk_setup_pbus_23470 setup_pbus; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_tk_write_23470 write; + T_cds_tk_read_23470 read; + + UInt16 store_protect_error; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + +} T_cds_tk_23470; + + + +#define T_cds_tk_DEFAULTS_23470 { 0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_CDS_TK_SETUP_PBUS_DEFAULTS_23470, \ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + {T_CDS_TK_WRITE_SBUS_DEFAULTS_23470},\ + {T_CDS_TK_READ_SBUS_DEFAULTS_23470,TYPE_CDS_XILINX_DEFAULTS},\ + 0, \ + (void (*)(Uint32))cds_tk_init, \ + (int (*)(Uint32))cds_tk_read_all, \ + (int (*)(Uint32))cds_tk_write_all, \ + (int (*)(Uint32))cds_tk_read_sbus_23470, \ + (int (*)(Uint32))cds_tk_write_sbus_23470, \ + (int (*)(Uint32))cds_tk_read_pbus, \ + (int (*)(Uint32))cds_tk_write_pbus, \ + (void (*)(Uint32))cds_tk_reset_error, \ + (void (*)(Uint32))cds_tk_store_disable_error, \ + (void (*)(Uint32))cds_tk_restore_enable_error \ + } + + +typedef T_cds_tk_23470 *T_cds_tk_handle_23470; + + + + + +#endif // XP_CDS_TK_23470_H + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_23550.c b/Inu/Src/N12_Xilinx/xp_cds_tk_23550.c new file mode 100644 index 0000000..ea8424b --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_23550.c @@ -0,0 +1,560 @@ +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "TuneUpPlane.h" +#include "x_parallel_bus.h" +#include "x_serial_bus.h" +#include "xp_cds_tk.h" +#include "xp_tools.h" + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +// 23550 +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_write_sbus_23550(T_cds_tk_23550 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_protect_tk.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + +//4 protect_error +// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) +// v->write.sbus.protect_error.bit.enable_err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_tk_out_40pin.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//1 dead_min_time + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.dead_min_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.ack_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + +//10 time_after_err + x_serial_bus_project.reg_addr = 10; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.time_after_err; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + + +//7 cmd_reset_error +/* + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_error++; +*/ + + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_read_sbus_23550(T_cds_tk_23550 *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_tk_out_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//1 dead_min_time + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.dead_min_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.ack_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_protect_tk.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//4 protect_error + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//5 status_tk_40pin + x_serial_bus_project.reg_addr = 5; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//6 status_tk_96pin + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_96pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//8 status_protect_current_ack + x_serial_bus_project.reg_addr = 8; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_current_ack.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//9 id_plate + x_serial_bus_project.reg_addr = 9; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.id_plate.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//10 time_after_err + x_serial_bus_project.reg_addr = 10; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_after_err = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//11 time_err_tk_all + x_serial_bus_project.reg_addr = 11; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk_all.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->type_cds_xilinx = v->read.type_cds_xilinx; + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + +/////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +#pragma CODE_SECTION(cds_tk_read_pbus_23550,".fast_run2"); +int cds_tk_read_pbus_23550(T_cds_tk_23550 *v) +{ + unsigned long adr_pbus; + + if (v->useit == 0 || v->setup_pbus.use_reg_in_pbus.all==0) + return 0; + + if (v->status & (component_Started | component_Ready | component_Error | component_ErrorSBus)) + { +//#if (Cds_Tk_Xilinx_SP6 == 1) && (C_PROJECT_TYPE == PROJECT_23550) + if (v->type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + adr_pbus = v->adr_pbus.adr_table[0] + ADR_FIRST_FREE; + read_pbus_value_full_v3(v->setup_pbus.use_reg_in_pbus.bit.reg0,adr_pbus,v->read.pbus.status1.all); + read_pbus_value_full_v3(v->setup_pbus.use_reg_in_pbus.bit.reg1,adr_pbus,v->read.pbus.DataReg0.all); + read_pbus_value_full_v3(v->setup_pbus.use_reg_in_pbus.bit.reg2,adr_pbus,v->read.pbus.DataReg1.all); + read_pbus_value_full_v3(v->setup_pbus.use_reg_in_pbus.bit.reg3,adr_pbus,v->read.pbus.DataReg2.all); + read_pbus_value_full_v3(v->setup_pbus.use_reg_in_pbus.bit.reg4,adr_pbus,v->read.pbus.DataReg3.all); + read_pbus_value_full_v3(v->setup_pbus.use_reg_in_pbus.bit.reg5,adr_pbus,v->read.pbus.status2.all); + } + } + else + { + v->read.pbus.status1.all = 0; + v->read.pbus.DataReg0.all = 0; + v->read.pbus.DataReg1.all = 0; + v->read.pbus.DataReg2.all = 0; + v->read.pbus.DataReg3.all = 0; + v->read.pbus.status2.all = 0; + } + +//#endif + + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +#pragma CODE_SECTION(cds_tk_optical_bus_write_data,".fast_run"); +void cds_tk_optical_bus_write_data(T_cds_tk_23550 *v) +{ + if (v->useit == 0) + return ; + + i_WriteMemory(SI_OPTICS_WORD_TO_SEND_1,v->optical_data_out.buf[0]); + i_WriteMemory(SI_OPTICS_WORD_TO_SEND_2,v->optical_data_out.buf[1]); + i_WriteMemory(SI_OPTICS_WORD_TO_SEND_3,v->optical_data_out.buf[2]); + i_WriteMemory(SI_OPTICS_WORD_TO_SEND_4,v->optical_data_out.buf[3]); + v->optical_data_out.count_send++; + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +#pragma CODE_SECTION(cds_tk_optical_bus_check_error_read,".fast_run"); +void cds_tk_optical_bus_check_error_read(T_cds_tk_23550 *v) +{ + unsigned int delta_id_sbus = 0; +// static unsigned int prev_id_sbus = 0; + + if (v->useit == 0) + return ; + + // i_led2_on_off(1); + + v->optical_data_in.status_1.all = v->read.pbus.status1.all; + v->optical_data_in.status_2.all = v->read.pbus.status2.all; + +// if ( (v->read.pbus.status1.all == v->read.pbus.status2.all) +// && (v->read.pbus.status1.bit.receiver_busy==0) +// && (v->read.pbus.status1.bit.receiver_error==0) +// ) + + if ( v->optical_data_in.status_1.bit.id_sbus == v->optical_data_in.status_2.bit.id_sbus + && v->optical_data_in.status_1.bit.id == v->optical_data_in.status_2.bit.id +// && (v->read.pbus.status1.bit.receiver_error==0) +// && (v->read.pbus.status2.bit.receiver_error==0) + ) + { + // , , .. PBUS + // , , . + v->optical_data_in.status_read.bit.receiver_busy = v->optical_data_in.status_1.bit.receiver_busy || v->optical_data_in.status_2.bit.receiver_busy; + + // may be data new and ok? + // + if (v->optical_data_in.status_1.bit.id_sbus == v->optical_data_in.prev_id_sbus) { + // data old + v->optical_data_in.status_read.bit.old_data = 1; + v->optical_data_in.same_id_count += 1; + + if (v->optical_data_in.same_id_count_between < v->optical_data_in.setup_count_error_between) + v->optical_data_in.same_id_count_between += 1; + else + // , ? + v->optical_data_in.ready = 0; + } + else + { + // + v->optical_data_in.same_id_count_between = 0; + v->optical_data_in.local_count_error = 0; + v->optical_data_in.raw_local_error = 0; + v->optical_data_in.ready = 1; + + // ? + if (v->optical_data_in.status_1.bit.id_sbus >= v->optical_data_in.prev_id_sbus) + delta_id_sbus = v->optical_data_in.status_1.bit.id_sbus - v->optical_data_in.prev_id_sbus; + else + delta_id_sbus = 0x10 + v->optical_data_in.status_1.bit.id_sbus - v->optical_data_in.prev_id_sbus; + + if (delta_id_sbus == 1 ) + { + // . + v->optical_data_in.count_ok++; + } + else + { + // + v->optical_data_in.count_lost += (delta_id_sbus - 1); + v->optical_data_in.count_ok++; + v->optical_data_in.status_read.bit.lost_data = 1; + } + + // ? + if (v->optical_data_in.status_read.bit.new_data_ready) + v->optical_data_in.status_read.bit.overfull_new_data = 1; // , + + // + v->optical_data_in.buf[0] = v->read.pbus.DataReg0.all; + v->optical_data_in.buf[1] = v->read.pbus.DataReg1.all; + v->optical_data_in.buf[2] = v->read.pbus.DataReg2.all; + v->optical_data_in.buf[3] = v->read.pbus.DataReg3.all; + + + v->optical_data_in.status_read.bit.new_data_ready = 1; + + } + + v->optical_data_in.prev_id_sbus = v->read.pbus.status1.bit.id_sbus; + } + else + { + if ((v->optical_data_in.status_1.bit.id_sbus != v->optical_data_in.status_2.bit.id_sbus) + || (v->optical_data_in.status_1.bit.id != v->optical_data_in.status_2.bit.id) ) + v->optical_data_in.status_read.bit.bad_status12 = 1; + + if (v->read.pbus.status1.bit.receiver_error==1 || v->read.pbus.status2.bit.receiver_error==1) + v->optical_data_in.status_read.bit.receiver_error = 1; + + v->optical_data_in.raw_local_error = 1; + v->optical_data_in.full_count_error++; + + if (v->optical_data_in.local_count_error >= v->optical_data_in.setup_count_error) + { + v->optical_data_in.ready = 0; + +// v->optical_data_in.buf[0] = 0; +// v->optical_data_in.buf[1] = 0; +// v->optical_data_in.buf[2] = 0; +// v->optical_data_in.buf[3] = 0; + } + else + { + v->optical_data_in.local_count_error++; + } + + } + + +// +// +// if ( (v->read.pbus.status1.all == v->read.pbus.status2.all) +// && (v->read.pbus.status1.bit.id_sbus != v->optical_data_in.prev_id_sbus ) +// && (v->read.pbus.status1.bit.receiver_busy==0) +// && (v->read.pbus.status1.bit.receiver_error==0) +// ) +// { +// +// +// if (v->read.pbus.status1.bit.id_sbus >= v->optical_data_in.prev_id_sbus) +// delta_id_sbus = v->read.pbus.status1.bit.id_sbus - v->optical_data_in.prev_id_sbus; +// else +// delta_id_sbus = 0x10 + v->read.pbus.status1.bit.id_sbus - v->optical_data_in.prev_id_sbus; +// +// v->optical_data_in.local_count_error = 0; +// v->optical_data_in.raw_local_error = 0; +// v->optical_data_in.ready = 1; +// +// +// +// if (delta_id_sbus == 1 ) +// v->optical_data_in.count_ok++; +// else +// { +// v->optical_data_in.count_lost += (delta_id_sbus - 1); +// v->optical_data_in.count_ok++; +// } +// +// v->optical_data_in.buf[0] = v->read.pbus.DataReg0.all; +// v->optical_data_in.buf[1] = v->read.pbus.DataReg1.all; +// v->optical_data_in.buf[2] = v->read.pbus.DataReg2.all; +// v->optical_data_in.buf[3] = v->read.pbus.DataReg3.all; +// +// // ? +// if (v->optical_data_in.new_data_ready) +// v->optical_data_in.overfull_new_data = 1; // , +// +// v->optical_data_in.new_data_ready = 1; +// +// } +// else +// { +//// Led1_Toggle(); +// +//// i_led1_on_off(1); +// +// v->optical_data_in.raw_local_error = 1; +// +// if (v->read.pbus.status1.bit.id_sbus != v->optical_data_in.prev_id_sbus) { +// v->optical_data_in.same_id_count += 1; +// } +// v->optical_data_in.full_count_error++; +// if (v->optical_data_in.local_count_error >= v->optical_data_in.setup_count_error) +// { +// v->optical_data_in.ready = 0; +// +// v->optical_data_in.buf[0] = 0; +// v->optical_data_in.buf[1] = 0; +// v->optical_data_in.buf[2] = 0; +// v->optical_data_in.buf[3] = 0; +// +// } +// else +// { +// v->optical_data_in.local_count_error++; +//// i_led2_toggle(); +// } +// +//// i_led1_on_off(0); +// } +// v->optical_data_in.prev_id_sbus = v->read.pbus.status1.bit.id_sbus; +// // i_led2_on_off(0); +// +// +//// v->write.sbus.protect_error.all = v->store_protect_error; // restore all setup error. +//// v->write_sbus(v); +// + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +#pragma CODE_SECTION(cds_tk_optical_bus_check_error_write,".fast_run"); +void cds_tk_optical_bus_check_error_write(T_cds_tk_23550 *v) +{ + if (v->useit == 0) + return ; + + if ( (v->read.pbus.status1.all == v->read.pbus.status2.all) + && (v->read.pbus.status1.bit.trans_busy==0) + && (v->read.pbus.status1.bit.trans_error==0) + ) + { + v->optical_data_out.local_count_error = 0; + v->optical_data_out.ready = 1; + v->optical_data_out.raw_local_error = 0; + } + else + { + v->optical_data_out.raw_local_error = 1; + v->optical_data_out.full_count_error++; + if (v->optical_data_out.local_count_error >= v->optical_data_out.setup_count_error) + v->optical_data_out.ready = 0; + else + { + v->optical_data_out.local_count_error++; + } + + } + +// v->write.sbus.protect_error.all = v->store_protect_error; // restore all setup error. +// v->write_sbus(v); + + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_23550.h b/Inu/Src/N12_Xilinx/xp_cds_tk_23550.h new file mode 100644 index 0000000..f12da6d --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_23550.h @@ -0,0 +1,616 @@ +#ifndef XP_CDS_TK_23550_H +#define XP_CDS_TK_23550_H + + +#include + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//// 23550 +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//#define Cds_Tk_Xilinx_SP6 0 + +//#if Cds_Tk_Xilinx_SP6 == 1 +#define T_CDS_TK_COUNT_ADR_PBUS_23550 6 // count max elements in parallel bus +//#else +// #define T_CDS_TK_COUNT_ADR_PBUS_23550 0 // count max elements in parallel bus +//#endif //Cds_Tk_Xilinx_SP6 + +#define T_CDS_TK_SETUP_USE_ADR_PBUS_23550 0xffff // - PBUS, 0xffff - + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 mintime :8; // N=mintime * fclk fclk=5000kHz + UInt16 deadtime :8; // N=deadtime * fclk fclk=5000kHz + } bit; + } dead_min_time; +//2 + union + { + UInt16 all; + struct + { + UInt16 time :8; + UInt16 reserv :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :8; + UInt16 detect_soft_disconnect :1; + UInt16 enable_soft_disconnect :1; + UInt16 enable_line_err :1; + UInt16 disable_err_mintime :1; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + UInt16 cmd_reset_error; + +//10 + UInt16 time_after_err; //time_after_err = 4000<-DEC * 0.02 = 80mc + +} T_cds_tk_write_sbus_23550; + +#define T_CDS_TK_WRITE_SBUS_DEFAULTS_23550 {0x0000,0x5f5f,0x0909,0x0000,0x0000,0x0105} + + +//////////////////////////////////// ///////////////////////// +///////////////////////////////////////////////////////////// +// read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; + +//1 + union + { + UInt16 all; + struct + { + UInt16 mintime :8; // N=mintime * fclk fclk=5000kHz + UInt16 deadtime :8; // N=deadtime * fclk fclk=5000kHz + } bit; + } dead_min_time; + +//2 + union + { + UInt16 all; + struct + { + UInt16 time :8; + UInt16 reserv :8; + } bit; + } ack_time; + +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; + +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :8; + UInt16 detect_soft_disconnect :1; + UInt16 enable_soft_disconnect :1; + UInt16 enable_line_err :1; + UInt16 disable_err_mintime :1; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; + +//5 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + } bit; + } status_tk_40pin; + +//6 + union + { + UInt16 all; + struct + { + UInt16 tk0_a4 :1; + UInt16 tk1_b4 :1; + UInt16 tk2_c4 :1; + UInt16 tk3_a5 :1; + UInt16 tk4_b5 :1; + UInt16 tk5_c5 :1; + UInt16 tk6_a6 :1; + UInt16 tk7_b6 :1; + UInt16 tk8_c6 :1; + UInt16 tk9_a7 :1; + UInt16 tk10_b7 :1; + UInt16 tk11_c7 :1; + UInt16 tk12_a8 :1; + UInt16 tk13_b8 :1; + UInt16 tk14_a9 :1; + UInt16 tk15_b9 :1; + } bit; + } status_tk_96pin; + +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :5; + UInt16 ErrorSoftShutdownForbidComb :1; + UInt16 ErrorSoftShutdownFromErr0 :1; + UInt16 line_err_keys_3210 :1; + UInt16 line_err_keys_7654 :1; + UInt16 mintime_err_keys_3210 :1; + UInt16 mintime_err_keys_7654 :1; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; + +//8 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } status_protect_current_ack; + +//9 + union + { + UInt16 all; + struct + { + UInt16 revision :5; + UInt16 version :6; + T_plate_type plate_type :5; + } bit; + } id_plate; + +//10 + + UInt16 time_after_err; + + +//11 + union + { + UInt16 all; + struct + { + UInt16 tk_3210 :8; + UInt16 tk_7654 :8; + } bit; + } time_err_tk_all; + +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + +} T_cds_tk_read_sbus_23550; + + +#define T_CDS_TK_READ_SBUS_DEFAULTS_23550 {0,0,0,0,0,0,0,0,0,0,0} + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + +typedef union { + UInt16 all; + struct { + UInt16 id:4; // - ( ). + // ( ) + UInt16 id_sbus:4; // , . +1 + + UInt16 count_receiver_error:4; // ( ) + UInt16 trans_busy:1; // busy 1- , 0- ( ) + UInt16 trans_error:1; // ( ) + UInt16 receiver_busy :1; // busy 1- , 0- ( ) + UInt16 receiver_error:1; // ( ) + } bit; +} STATUS_OPT_BUS; + +///////////////////////////////////////////////////////////// + +typedef struct { + //0 + STATUS_OPT_BUS status1; + //1 + union { + UInt16 all; + } DataReg0; + //2 + union { + UInt16 all; + } DataReg1; + //3 + union { + UInt16 all; + } DataReg2; + //4 + union { + UInt16 all; + } DataReg3; + //5 + STATUS_OPT_BUS status2; + +} T_cds_tk_read_pbus_23550; +// 15, 14, 11-8 , 13, 12 - , +// - 15, , , 13, . +//busy , . +// , (12), (13) , . +// 1, , - , +// 15 14, 15 14 = 0, , 15 = 1, 0, , +// , . +// - , , , , , +// #0 #5 PBUS +//id + + +#define T_CDS_TK_READ_PBUS_DEFAULTS_23550 {0,0,0,0,0,0} + + +///////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//setup parallel bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + UInt16 count_elements_pbus; +// use_or_not? + union + { + UInt16 all; + struct{ + UInt16 reg0 : 1; + UInt16 reg1 : 1; + UInt16 reg2 : 1; + UInt16 reg3 : 1; + UInt16 reg4 : 1; + UInt16 reg5 : 1; + UInt16 res : 10; + }bit; + } use_reg_in_pbus; + +} T_cds_tk_setup_pbus_23550; + +#define T_CDS_TK_SETUP_PBUS_DEFAULTS_23550 {T_CDS_TK_COUNT_ADR_PBUS_23550,T_CDS_TK_SETUP_USE_ADR_PBUS_23550} +////////////////////////////////////////////////////////////// + + + + +typedef struct{ + T_cds_tk_write_sbus_23550 sbus; +} T_cds_tk_write_23550; + +typedef struct{ + T_cds_tk_read_sbus_23550 sbus; + T_cds_tk_read_pbus_23550 pbus; + Int16 type_cds_xilinx; +} T_cds_tk_read_23550; + +#define T_CDS_TK_READ_DEFAULTS_23550 {T_CDS_TK_READ_SBUS_DEFAULTS_23550,T_CDS_TK_READ_PBUS_DEFAULTS_23550,TYPE_CDS_XILINX_DEFAULTS} + +typedef struct { + UInt16 adr_table[T_CDS_TK_COUNT_ADR_PBUS_23550]; +} T_cds_tk_adr_pbus_23550; + +#define T_CDS_TK_ADR_PBUS_DEFAULTS_23550 {0,0,0,0,0,0} + + +////////////////////////////////////////////////////////////// +typedef struct { + UInt16 setup_count_error; + UInt16 full_count_error; + UInt16 local_count_error; + UInt16 count_send; + UInt16 ready; + UInt16 error_not_ready_count; + UInt16 raw_local_error; + UInt16 buf[4]; +} T_cds_optical_bus_data_out; + +#define T_CDS_OPTICAL_BUS_DATA_OUT_DEFAULTS {15,0,0,0,0,0,0,{0,0,0,0}} + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + +typedef union { + UInt16 all; + struct { + UInt16 new_data_ready:1; // + UInt16 overfull_new_data:1; // + UInt16 old_data:1; // + UInt16 lost_data:1; // , . + UInt16 bad_status12:1; // , + UInt16 receiver_busy:1; //busy 1- , 0- ( ) + UInt16 receiver_error:1; // ( ) + + } bit; +} STATUS_DATA_READ_OPT_BUS; + +///////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +typedef struct { + UInt16 setup_count_error; // + UInt16 setup_count_error_between; // + UInt16 full_count_error; // + UInt16 local_count_error; // , setup_count_error ready, + UInt16 count_ok; // + UInt16 count_lost; // ( id_sbus) + UInt16 ready; // , setup_count_error + UInt16 same_id_count; // , .. . + UInt16 same_id_count_between; // , , .. . + UInt16 error_not_ready_count; // ready + UInt16 raw_local_error; // , + UInt16 buf[4]; // + STATUS_OPT_BUS status_1; // status 1 + STATUS_OPT_BUS status_2; // status 2 + UInt16 prev_id_sbus; // . id_sbus + STATUS_DATA_READ_OPT_BUS status_read;// + STATUS_DATA_READ_OPT_BUS prev_status_read;// +} T_cds_optical_bus_data_in; + +#define T_CDS_OPTICAL_BUS_DATA_IN_DEFAULTS {15,50,0,0,0,0,0,0,0,0,0,{0,0,0,0},0,0,0,0,0} + +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +typedef struct { + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + T_cds_tk_setup_pbus_23550 setup_pbus; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_tk_write_23550 write; + T_cds_tk_read_23550 read; +//#if Cds_Tk_Xilinx_SP6 == 1 + T_cds_tk_adr_pbus_23550 adr_pbus; +//#endif + UInt16 store_protect_error; + + T_cds_optical_bus_data_out optical_data_out; + T_cds_optical_bus_data_in optical_data_in; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*optical_bus_write_data)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + + void (*optical_bus_check_error_read)(); // Pointer to calculation function + void (*optical_bus_check_error_write)(); // Pointer to calculation function + +} T_cds_tk_23550; + + + +#define T_cds_tk_DEFAULTS_23550 {0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_CDS_TK_SETUP_PBUS_DEFAULTS_23550,\ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + {T_CDS_TK_WRITE_SBUS_DEFAULTS_23550},\ + T_CDS_TK_READ_DEFAULTS_23550,\ + T_CDS_TK_ADR_PBUS_DEFAULTS_23550,\ + 0,\ + T_CDS_OPTICAL_BUS_DATA_OUT_DEFAULTS,\ + T_CDS_OPTICAL_BUS_DATA_IN_DEFAULTS,\ + (void (*)(Uint32))cds_tk_init,\ + (int (*)(Uint32))cds_tk_read_all,\ + (int (*)(Uint32))cds_tk_write_all,\ + (int (*)(Uint32))cds_tk_read_sbus_23550,\ + (int (*)(Uint32))cds_tk_write_sbus_23550,\ + (int (*)(Uint32))cds_tk_read_pbus_23550,\ + (int (*)(Uint32))cds_tk_write_pbus,\ + (void (*)(Uint32))cds_tk_optical_bus_write_data,\ + (void (*)(Uint32))cds_tk_reset_error,\ + (void (*)(Uint32))cds_tk_store_disable_error,\ + (void (*)(Uint32))cds_tk_restore_enable_error,\ + (void (*)(Uint32))cds_tk_optical_bus_check_error_read,\ + (void (*)(Uint32))cds_tk_optical_bus_check_error_write\ + } + + + + + + +typedef T_cds_tk_23550 *T_cds_tk_handle_23550; + +void cds_tk_optical_bus_write_data(T_cds_tk_23550 *v); +void cds_tk_optical_bus_check_error_read(T_cds_tk_23550 *v); +void cds_tk_optical_bus_check_error_write(T_cds_tk_23550 *v); + +#endif // XP_CDS_TK_23550_H diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_balzam.c b/Inu/Src/N12_Xilinx/xp_cds_tk_balzam.c new file mode 100644 index 0000000..5564462 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_balzam.c @@ -0,0 +1,236 @@ +#include "x_serial_bus.h" +#include "xp_cds_tk.h" +#include "xp_tools.h" + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +// BALZAM +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_write_sbus_balzam(T_cds_tk_balzam *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_write_error; + x_serial_bus_project.slave_addr = v->plane_address; // number plate + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_protect_tk.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + +//4 protect_error +// if (v->read.type_cds_xilinx == TYPE_CDS_XILINX_SP6) +// v->write.sbus.protect_error.bit.enable_err_switch = 0; // SP6 , .. + + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.protect_error.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.mask_tk_out_40pin.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//1 dead_min_time + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.dead_min_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.ack_time.all; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_write_error++; + + + + +//7 cmd_reset_error +/* + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.write_data = v->write.sbus.cmd_reset_error; // write data + + if (x_serial_bus_project.write(&x_serial_bus_project)) // make write + v->status_serial_bus.count_error++; +*/ + + if (old_err == v->status_serial_bus.count_write_error)// no errors + { + v->status_serial_bus.count_write_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_WRITE_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; + + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int cds_tk_read_sbus_balzam(T_cds_tk_balzam *v) +{ + unsigned int old_err, err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + old_err = v->status_serial_bus.count_read_error; + + x_serial_bus_project.slave_addr = v->plane_address; // number plate + +//0 mask_tk_out_40pin + x_serial_bus_project.reg_addr = 0; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_tk_out_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//1 dead_min_time + x_serial_bus_project.reg_addr = 1; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.dead_min_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//2 ack_time + x_serial_bus_project.reg_addr = 2; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.ack_time.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + + +//3 mask_protect_tk + x_serial_bus_project.reg_addr = 3; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.mask_protect_tk.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//4 protect_error + x_serial_bus_project.reg_addr = 4; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.protect_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//5 status_tk_40pin + x_serial_bus_project.reg_addr = 5; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_40pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//6 status_tk_96pin + x_serial_bus_project.reg_addr = 6; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_tk_96pin.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//7 lock_status_error + x_serial_bus_project.reg_addr = 7; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.lock_status_error.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//8 status_protect_current_ack + x_serial_bus_project.reg_addr = 8; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.status_protect_current_ack.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//11 time_err_tk_all + x_serial_bus_project.reg_addr = 11; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + v->read.sbus.time_err_tk_all.all = x_serial_bus_project.read_data; + else + v->status_serial_bus.count_read_error++; + +//15 current_status_error + x_serial_bus_project.reg_addr = 15; // adr memory in plate + x_serial_bus_project.read(&x_serial_bus_project); // read + + if (x_serial_bus_project.flags.bit.read_error == 0) // check error + { + v->read.type_cds_xilinx = x_serial_bus_project.read_data & 0x1; + v->read.sbus.current_status_error.all = x_serial_bus_project.read_data & 0xfffe; + } + else + v->status_serial_bus.count_read_error++; + + +/////////// + + if (old_err == v->status_serial_bus.count_read_error)// no errors + { + v->status_serial_bus.count_read_ok++; + err = 0; // no errors + } + else + err = 1; // !errors! + + err_ready = check_cds_ready_sbus( err, ITS_READ_BUS, &v->status_serial_bus); + set_status_cds(err_ready, &v->status); + + return err_ready; +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + diff --git a/Inu/Src/N12_Xilinx/xp_cds_tk_balzam.h b/Inu/Src/N12_Xilinx/xp_cds_tk_balzam.h new file mode 100644 index 0000000..35eedda --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_cds_tk_balzam.h @@ -0,0 +1,403 @@ +#ifndef XP_CDS_TK_BALZAM_H +#define XP_CDS_TK_BALZAM_H + + +#include + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//// BALZAM +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + +#define T_CDS_TK_COUNT_ADR_PBUS_BALZAM 0 // count max elements in parallel bus + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +// write serial bus reg +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 mintime :8; // N=mintime * fclk fclk=6250kHz + UInt16 deadtime :8; // N=deadtime * fclk fclk=6250kHz + } bit; + } dead_min_time; +//2 + union + { + UInt16 all; + struct + { + UInt16 time0 :8; + UInt16 reserv :8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :10; + UInt16 enable_line_err :1; + UInt16 disable_err_mintime :1; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//7 + UInt16 cmd_reset_error; +// + +} T_cds_tk_write_sbus_balzam; + +#define T_CDS_TK_WRITE_SBUS_DEFAULTS_BALZAM {0x0000,0x5f5f,0x0909,0x0000,0x0000,0x0000}//{0,0,0,0,0,0,0} + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg serial bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 + union + { + UInt16 all; + struct + { + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + UInt16 reserv :8; + } bit; + } mask_tk_out_40pin; +//1 + union + { + UInt16 all; + struct + { + UInt16 mintime :8; // N=mintime * fclk fclk=6250kHz + UInt16 deadtime :8; // N=deadtime * fclk fclk=6250kHz + } bit; + } dead_min_time; +//2 + union + { + UInt16 all; + struct + { + UInt16 time :8; + UInt16 reserv : 8; + } bit; + } ack_time; +//3 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } mask_protect_tk; +//4 + union + { + UInt16 all; + struct + { + UInt16 reserv :10; + UInt16 enable_line_err :1; + UInt16 disable_err_mintime :1; + UInt16 disable_err_hwp :1; + UInt16 disable_err0_in :1; + UInt16 enable_err_switch :1; + UInt16 enable_err_power :1; + } bit; + } protect_error; +//5 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0 :1; + UInt16 tk1 :1; + UInt16 tk2 :1; + UInt16 tk3 :1; + UInt16 tk4 :1; + UInt16 tk5 :1; + UInt16 tk6 :1; + UInt16 tk7 :1; + } bit; + } status_tk_40pin; +//6 + union + { + UInt16 all; + struct + { + UInt16 tk0_a4 :1; + UInt16 tk1_b4 :1; + UInt16 tk2_c4 :1; + UInt16 tk3_a5 :1; + UInt16 tk4_b5 :1; + UInt16 tk5_c5 :1; + UInt16 tk6_a6 :1; + UInt16 tk7_b6 :1; + UInt16 tk8_c6 :1; + UInt16 tk9_a7 :1; + UInt16 tk10_b7 :1; + UInt16 tk11_c7 :1; + UInt16 tk12_a8 :1; + UInt16 tk13_b8 :1; + UInt16 tk14_a9 :1; + UInt16 tk15_b9 :1; + } bit; + } status_tk_96pin; +//7 + union + { + UInt16 all; + struct + { + UInt16 reserv :7; + UInt16 line_err_keys_3210 :1; + UInt16 line_err_keys_7654 :1; + UInt16 mintime_err_keys_3210 :1; + UInt16 mintime_err_keys_7654 :1; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } lock_status_error; +//8 + union + { + UInt16 all; + struct + { + UInt16 tk0_ack :1; + UInt16 tk1_ack :1; + UInt16 tk2_ack :1; + UInt16 tk3_ack :1; + UInt16 tk4_ack :1; + UInt16 tk5_ack :1; + UInt16 tk6_ack :1; + UInt16 tk7_ack :1; + UInt16 tk0_current :1; + UInt16 tk1_current :1; + UInt16 tk2_current :1; + UInt16 tk3_current :1; + UInt16 tk4_current :1; + UInt16 tk5_current :1; + UInt16 tk6_current :1; + UInt16 tk7_current :1; + } bit; + } status_protect_current_ack; +//11 + union + { + UInt16 all; + struct + { + UInt16 tk_3210 :8; + UInt16 tk_7654 :8; + } bit; + } time_err_tk_all; +//15 + union + { + UInt16 all; + struct + { + UInt16 reserv :11; + UInt16 err0_local :1; + UInt16 err_hwp :1; + UInt16 err0_in :1; + UInt16 err_switch :1; + UInt16 err_power :1; + } bit; + } current_status_error; + + +} T_cds_tk_read_sbus_balzam; + + +#define T_CDS_TK_READ_SBUS_DEFAULTS_BALZAM {0,0,0,0, 0,0,0,0, 0,0,0} + + + + + +///////////////////////////////////////////////////////////////// + + +typedef struct{ + T_cds_tk_write_sbus_balzam sbus; +} T_cds_tk_write_balzam; + +typedef struct{ + T_cds_tk_read_sbus_balzam sbus; + Int16 type_cds_xilinx; +} T_cds_tk_read_balzam; + +////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +typedef struct { + UInt16 plane_address; // 0 to 15 + UInt16 useit; + Int16 type_cds_xilinx; + UInt16 count_elements_pbus; + T_cds_status_serial_bus status_serial_bus; + T_cds_status_parallel_bus status_parallel_bus; + T_component_status status; + T_local_status local_status; + + T_cds_tk_write_balzam write; + T_cds_tk_read_balzam read; + + UInt16 store_protect_error; + + void (*init)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*read_sbus)(); // Pointer to calculation function + int (*write_sbus)(); // Pointer to calculation function + + int (*read_pbus)(); // Pointer to calculation function + int (*write_pbus)(); // Pointer to calculation function + + void (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + +} T_cds_tk_balzam; + + + +#define T_cds_tk_DEFAULTS_BALZAM { 0,\ + 0,\ + TYPE_CDS_XILINX_DEFAULTS,\ + T_CDS_TK_COUNT_ADR_PBUS_BALZAM, \ + T_cds_status_serial_bus_DEFAULT,\ + T_cds_status_parallel_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + {T_CDS_TK_WRITE_SBUS_DEFAULTS_BALZAM},\ + {T_CDS_TK_READ_SBUS_DEFAULTS_BALZAM,TYPE_CDS_XILINX_DEFAULTS},\ + 0, \ + (void (*)(Uint32))cds_tk_init, \ + (int (*)(Uint32))cds_tk_read_all, \ + (int (*)(Uint32))cds_tk_write_all, \ + (int (*)(Uint32))cds_tk_read_sbus_balzam, \ + (int (*)(Uint32))cds_tk_write_sbus_balzam, \ + (int (*)(Uint32))cds_tk_read_pbus, \ + (int (*)(Uint32))cds_tk_write_pbus, \ + (void (*)(Uint32))cds_tk_reset_error, \ + (void (*)(Uint32))cds_tk_store_disable_error, \ + (void (*)(Uint32))cds_tk_restore_enable_error \ + } + + +typedef T_cds_tk_balzam *T_cds_tk_handle_balzam; + + + + + + +#endif // XP_CDS_TK_BALZAM_H + + diff --git a/Inu/Src/N12_Xilinx/xp_controller.c b/Inu/Src/N12_Xilinx/xp_controller.c new file mode 100644 index 0000000..87118a6 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_controller.c @@ -0,0 +1,58 @@ +#include "xp_controller.h" + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "TuneUpPlane.h" +#include "xerror.h" + + + + +void controller_init(T_controller *v) +{ + +} + +void controller_int13_enable(T_controller *v) +{ + if (v->read.status.bit.int13_inited) + v->write.setup.bit.use_int13 = 1; + else + { + + + } +} + +void controller_int13_disable(T_controller *v) +{ + v->write.setup.bit.use_int13 = 0; +} + +/* +T_controller_read controller_read_errors(T_controller *v) +{ + T_controller_read r; + + r.errors.all = i_ReadMemory (ADR_ERRORS_TOTAL_INFO); + r.errors_buses.all = i_ReadMemory (ADR_BUS_ERROR_READ); + + return r; +} +*/ + +int controller_read_all(T_controller *v) +{ + + v->read.errors.all = ReadMemory (ADR_ERRORS_TOTAL_INFO); + v->read.errors_buses.all = ReadMemory (ADR_BUS_ERROR_READ); + return 0; +} + + + + + + diff --git a/Inu/Src/N12_Xilinx/xp_controller.h b/Inu/Src/N12_Xilinx/xp_controller.h new file mode 100644 index 0000000..2d26af4 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_controller.h @@ -0,0 +1,144 @@ +#ifndef X_CONTROLLER_H +#define X_CONTROLLER_H + +#include "x_basic_types.h" +#include "xp_id_plate_info.h" +#include "xp_plane_adr.h" + +//#include "xp_controller_fpga.h" +//#include "xp_controller_cpld.h" +//#include "x_command.h" + +/*----------------------------------------------------------------------------- +Define the types +-----------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// write reg +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { +//0 +// + union + { + UInt16 all; + struct + { + UInt16 use_int13 :1; + UInt16 reserv :15; + } bit; + + } setup; + +} T_controller_write; + +#define T_CONTROLLER_WRITE_DEFAULTS {0} +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// read reg +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + union + { + UInt16 all; + struct + { + UInt16 reserv :9; + + UInt16 errHWP_trig :1; //TODO: , !!! + UInt16 pwm_wdog :1; + UInt16 errHWP :1; + + UInt16 status_er0 :1; + UInt16 error_pbus :1; + UInt16 er0_trig :1; //er0+erHWP + UInt16 er0_out :1; + } bit; + } errors; + + union + { + UInt16 all; + struct + { + UInt16 reserv0_3 :4; + UInt16 slave_addr_error :4; // , . + + UInt16 count_error_pbus :4; // ParallelBus - number of errors. if errrors > failCnt then ER0 = active. ( 200) + UInt16 reserv12 :1; // + UInt16 err_transmit_hwp_bus :1; // HWP data transmit fail + UInt16 err_sbus :1; // serialBus_Error + UInt16 sbus_updated :1; // serialBus_DataUpdated + } bit; + } errors_buses; + + union + { + UInt16 all; + struct + { + UInt16 int13_inited :1; + UInt16 reserv0 :15; + } bit; + } status; + + +} T_controller_read; + +#define T_CONTROLLER_READ_DEFAULTS {0,0,0} +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// main struct +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct TS_controller +{ + T_component_status status; + unsigned int build; + T_controller_write write; + T_controller_read read; + + void (*init)(); // Pointer to calculation function + int (*read_all)(); // Pointer to calculation function + void (*enable_int13)(); // Pointer to calculation function + void (*disable_int13)(); // Pointer to calculation function + + +} T_controller; + +typedef T_controller *T_controller_handle; + +// command type +/*typedef enum { + controller_Command_ReadParameters = 1 + +} T_controller_Command; +*/ + +#define T_controller_DEFAULTS { component_NotReady,\ +0,\ +T_CONTROLLER_WRITE_DEFAULTS,\ +T_CONTROLLER_READ_DEFAULTS,\ +(void (*)(Uint32))controller_init,\ +(int (*)(Uint32))controller_read_all,\ +(void (*)(Uint32))controller_int13_enable,\ +(void (*)(Uint32))controller_int13_disable\ +} + + +/*------------------------------------------------------------------------------ + Prototypes for the functions +------------------------------------------------------------------------------*/ + +void controller_init(T_controller_handle); +int controller_read_all(T_controller_handle); + +//T_controller_read controller_read_errors(T_controller_handle); + +void controller_int13_enable(T_controller_handle); +void controller_int13_disable(T_controller_handle); + + +#endif diff --git a/Inu/Src/N12_Xilinx/xp_hwp.c b/Inu/Src/N12_Xilinx/xp_hwp.c new file mode 100644 index 0000000..37a7d0d --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_hwp.c @@ -0,0 +1,1419 @@ +#include "xp_hwp.h" + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "TuneUpPlane.h" +#include "xerror.h" +#include "xp_controller.h" + + +T_controller_read r_controller; + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +/////////////////////////////////////// ////////////////////// +unsigned int calcVoltsToDACUop(unsigned int miliVolts) +{ + static unsigned int voltsOut = 0; + static float rez = 0; + static float volts = 0.0; + static float percent = 0.0; + + volts = miliVolts / 3.0; // 3 . Uop + percent = (float)(volts / UrefDAC); + rez = 4095.0 * percent; + voltsOut = (int)rez; // = 4095.0 * miliVolts / (UrefDAC*3.0); + + return voltsOut; +} +///////////////////////////////////////////////////////////// +unsigned int voltsForChanals(int miliVolts, unsigned int miliVoltsUop) +{ + static float volts = 0.0; + static float percent = 0.0; + static float rez = 0; + static unsigned int voltsOut = 0; + + volts = miliVoltsUop - miliVolts; // , .. : ACP_XX = (-1) * ACPXX + percent = (float)(volts / UrefDAC); + rez = 4095.0 * percent; + voltsOut = (int)rez; // = 4095.0 * miliVolts / UrefDAC; + + return voltsOut; +} + +///////////////////////////////////////////////////////////// +unsigned int calcVoltsToDACUtest(unsigned int miliVolts) +{ + static unsigned int voltsOut = 0; + static float rez = 0; + static float volts = 0.0; + static float percent = 0.0; + + volts = miliVolts; // = 3*Uop - (Utest + ACPx) + percent = (float)(volts / UrefDAC); + rez = 4095.0 * percent; + voltsOut = (int)rez; // = 4095.0 * miliVolts / (UrefDAC*3.0); + + return voltsOut; +} + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + +int convert_values(T_hwp *v) +{ + int i; + v->low_setup.DACValues[0] = calcVoltsToDACUtest(v->write.U_test); + v->low_setup.DACValues[1] = calcVoltsToDACUop(v->write.U_opora); + + + + for (i=0;i<16;i++) + { + if (i == 0 || i == 1) + { + if (i==0) + v->low_setup.DACValues[2] = voltsForChanals(v->write.values[i].plus, HWP_U_OPORA_DEFINE/*v->write.U_opora*/ ); + if (i==1) + v->low_setup.DACValues[3] = voltsForChanals(v->write.values[i].plus, HWP_U_OPORA_DEFINE/*v->write.U_opora*/); + } + else + { + v->low_setup.DACValues[i*2] = voltsForChanals(v->write.values[i].plus, HWP_U_OPORA_DEFINE/*v->write.U_opora*/); + v->low_setup.DACValues[i*2+1] = voltsForChanals(-v->write.values[i].minus, HWP_U_OPORA_DEFINE/*v->write.U_opora*/); + } + } + + return 0; +} + + +/////////////////////////////////////////////// +int convert_masks(T_hwp *v) +{ + + v->low_setup.mask_13to0.all = 0; + v->low_setup.mask_29to14.all = 0; + +// + v->write.mask.plus.all |= (v->write.use_channel.plus.all); + v->write.mask.minus.all |= (v->write.use_channel.minus.all); + +//set masks on UREF0_29 + v->low_setup.mask_13to0.bit.DACCh0 = v->write.mask.plus.bit.ch0; + v->low_setup.mask_13to0.bit.DACCh1 = v->write.mask.plus.bit.ch1; + + v->low_setup.mask_13to0.bit.DACCh2 = v->write.mask.plus.bit.ch2; + v->low_setup.mask_13to0.bit.DACCh3 = v->write.mask.minus.bit.ch2; + + v->low_setup.mask_13to0.bit.DACCh4 = v->write.mask.plus.bit.ch3; + v->low_setup.mask_13to0.bit.DACCh5 = v->write.mask.minus.bit.ch3; + + v->low_setup.mask_13to0.bit.DACCh6 = v->write.mask.plus.bit.ch4; + v->low_setup.mask_13to0.bit.DACCh7 = v->write.mask.minus.bit.ch4; + + v->low_setup.mask_13to0.bit.DACCh8 = v->write.mask.plus.bit.ch5; + v->low_setup.mask_13to0.bit.DACCh9 = v->write.mask.minus.bit.ch5; + + v->low_setup.mask_13to0.bit.DACCh10 = v->write.mask.plus.bit.ch6; + v->low_setup.mask_13to0.bit.DACCh11 = v->write.mask.minus.bit.ch6; + + v->low_setup.mask_13to0.bit.DACCh12 = v->write.mask.plus.bit.ch7; + v->low_setup.mask_13to0.bit.DACCh13 = v->write.mask.minus.bit.ch7; + + v->low_setup.mask_29to14.bit.DACCh14 = v->write.mask.plus.bit.ch8; + v->low_setup.mask_29to14.bit.DACCh15 = v->write.mask.minus.bit.ch8; + + v->low_setup.mask_29to14.bit.DACCh16 = v->write.mask.plus.bit.ch9; + v->low_setup.mask_29to14.bit.DACCh17 = v->write.mask.minus.bit.ch9; + + v->low_setup.mask_29to14.bit.DACCh18 = v->write.mask.plus.bit.ch10; + v->low_setup.mask_29to14.bit.DACCh19 = v->write.mask.minus.bit.ch10; + + v->low_setup.mask_29to14.bit.DACCh20 = v->write.mask.plus.bit.ch11; + v->low_setup.mask_29to14.bit.DACCh21 = v->write.mask.minus.bit.ch11; + + v->low_setup.mask_29to14.bit.DACCh22 = v->write.mask.plus.bit.ch12; + v->low_setup.mask_29to14.bit.DACCh23 = v->write.mask.minus.bit.ch12; + + v->low_setup.mask_29to14.bit.DACCh24 = v->write.mask.plus.bit.ch13; + v->low_setup.mask_29to14.bit.DACCh25 = v->write.mask.minus.bit.ch13; + + v->low_setup.mask_29to14.bit.DACCh26 = v->write.mask.plus.bit.ch14; + v->low_setup.mask_29to14.bit.DACCh27 = v->write.mask.minus.bit.ch14; + + v->low_setup.mask_29to14.bit.DACCh28 = v->write.mask.plus.bit.ch15; + v->low_setup.mask_29to14.bit.DACCh29 = v->write.mask.minus.bit.ch15; + + return 0; +} + + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void hwp_init(T_hwp *v) +{ + + if (v->useit == 0) + return ; + + convert_values(v); + convert_masks(v); + +#if (USE_HWP_0) + if (v->plane_address == C_hwp0_address) + v->low_setup.dac_config.bit.HWPAddress = 0; +#endif + +#if (USE_HWP_1) + if (v->plane_address == C_hwp1_address) + v->low_setup.dac_config.bit.HWPAddress = 1; +#endif + +#if (USE_HWP_2) +// if (v->plane_address == C_hwp2_address) +// v->low_setup.dac_config.bit.HWPAddress = /0/1/2; +#endif + + +#if (HWP_SPEED_VERSION_DEFINE==MODE_HWP_SPEED_NORMAL) +// v->low_setup.dac_config.bit.HWP_Speed = MODE_HWP_SPEED_NORMAL;//HWP_SPEED_VERSION_DEFINE; // new version hwp with low speed serial hwp + v->write.HWP_Speed = MODE_HWP_SPEED_NORMAL; +#endif + +#if (HWP_SPEED_VERSION_DEFINE==MODE_HWP_SPEED_SLOW) +// v->low_setup.dac_config.bit.HWP_Speed = MODE_HWP_SPEED_SLOW;//HWP_SPEED_VERSION_DEFINE; // new version hwp with low speed serial hwp + v->write.HWP_Speed = MODE_HWP_SPEED_SLOW; +#endif + +#if (HWP_SPEED_VERSION_DEFINE==MODE_HWP_SPEED_AUTO) +// v->low_setup.dac_config.bit.HWP_Speed = MODE_HWP_SPEED_AUTO;//HWP_SPEED_VERSION_DEFINE; // new version hwp with low speed serial hwp + v->write.HWP_Speed = MODE_HWP_SPEED_AUTO; +#endif + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +int run_internal_test(T_hwp *v) +{ + int i,k,err, may_be_err_ch; + + if (v->useit == 0) + return 0; + + + + for (i=0;i<16;i++) + { + v->write.values[i].plus = HWP_DEF_LEVEL_ERROR; + v->write.values[i].minus = HWP_DEF_LEVEL_ERROR; + } +// prepare for test plus + + v->write.U_test = HWP_U_TEST_DEFINE; + v->write.U_opora = HWP_U_OPORA_DEFINE; +// + v->write.mask.minus.all = HWP_ENABLE_ALL_MASK; + v->write.mask.plus.all = HWP_ENABLE_ALL_MASK; + + convert_values(v); + convert_masks(v); + + err = 0; + err += hwp_write_all_dacs(v); + err += hwp_write_all_mask(v); + +// DELAY_US(200); + + if (err) + { + v->status = component_Error; + return 1; + } + + err += hwp_reset_error(v); + hwp_read_error(v); + + // , ! + err += hwp_read_comparators(v); + + if (v->read.errors.er0_HWP || err) + { + v->status = component_Error; + // er0_hwp + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + + +// start plus + for (i=0;i<16;i++) + { +// DELAY_US(200000); // + + v->write.mask.plus.all = HWP_ENABLE_ALL_MASK; + convert_masks(v); +// DELAY_US(20000);//+ + err = hwp_write_all_mask(v); + + err = 0; + v->read.test_passed.plus.all &= ~(1 << i); + + if (!(v->write.use_channel.plus.all & (1 << i))) + { + // + v->real_delays.plus[i] = HWP_MAX_ERROR_DELAY_DEFINE*10; // - + may_be_err_ch = 1; + if (v->write.test_all_channel==0) + continue; + } + else + may_be_err_ch = 0; + + + v->write.U_test = HWP_U_TEST_LEVEL_FOR_PREPARE_PLUS_TEST; + v->write.U_opora = HWP_U_OPORA_LEVEL_FOR_PREPARE_PLUS_TEST; + + for (k=0;k<16;k++) + { + if (k==i) + v->write.values[k].plus = HWP_U_LEVEL_COMP_FOR_TEST_DEFINE; // + else + v->write.values[k].plus = HWP_DEF_LEVEL_ERROR; + } + + convert_values(v); + + err += hwp_write_all_dacs(v); +// DELAY_US(20000);//+ + err += hwp_write_all_dacs(v); +// DELAY_US(20000); // + + err += hwp_reset_error(v); +// DELAY_US(20000); + DELAY_US(2000); + + hwp_read_error(v); +// DELAY_US(20000);//+ + +/* + if (v->read.errors.er0_HWP) + { + DELAY_US(20000); + DELAY_US(20000); + DELAY_US(20000); + DELAY_US(20000); + + i_led2_on_off(1); +// err += hwp_write_all_dacs(v); +// DELAY_US(2000); // + + err += hwp_reset_error(v); + DELAY_US(20000); + DELAY_US(20000); + + i_led2_on_off(0); + + hwp_read_error(v); + DELAY_US(20000);//+ + + if (v->read.errors.er0_HWP) + { + i_led2_on_off(1); + // err += hwp_write_all_dacs(v); + // DELAY_US(2000); // + + err += hwp_reset_error(v); + DELAY_US(20000); + DELAY_US(20000); + DELAY_US(20000); + DELAY_US(20000); + + i_led2_on_off(0); + + hwp_read_error(v); + DELAY_US(20000);//+ + DELAY_US(20000); + + if (v->read.errors.er0_HWP==0) + { + DELAY_US(20000); + err += hwp_reset_error(v); + err += hwp_reset_error(v); + err += hwp_reset_error(v); + } + + } + else + { + DELAY_US(20000); + err += hwp_reset_error(v); + err += hwp_reset_error(v); + err += hwp_reset_error(v); + } + } + +*/ + + + + err += hwp_read_comparators(v); +// DELAY_US(20000);//+ + + + if (v->read.errors.er0_HWP || err) + { + v->real_delays.plus[i] = HWP_MAX_ERROR_DELAY_DEFINE*2; // - + if (may_be_err_ch) + continue; // , + v->status = component_Error; + // er0_hwp DAC + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + + +// +// , ! + + v->write.mask.plus.all = (1 << i); // clear mask + convert_masks(v); + err += hwp_write_all_mask(v); + + // , ! + err += hwp_read_comparators(v); + if (v->read.comp_s.plus.all || err) + { + // - ! + // , er0_hwp, + // + v->real_delays.plus[i] = HWP_MAX_ERROR_DELAY_DEFINE*3; // - + if (may_be_err_ch) + continue; // , + + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + +// , +// ! + v->write.mask.plus.all = HWP_DISABLE_ALL_MASK; // clear all mask +// v->write.mask.plus.all = (1 << i); // clear mask + if (may_be_err_ch==0) + v->write.mask.plus.all = v->write.use_channel.plus.all; + + convert_masks(v); + err += hwp_write_all_mask(v); + + // , ! + err += hwp_read_comparators(v); + if (v->read.comp_s.plus.all || err) + { + // - ! + // , er0_hwp, + // + v->real_delays.plus[i] = HWP_MAX_ERROR_DELAY_DEFINE*4; // - + if (may_be_err_ch) + continue; // , + + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + +// ERR0_HWP + v->write.mask.plus.all = (1 << i); // will wait it status + + err += hwp_read_comparators(v); + + hwp_read_error(v); + if ((v->read.errors.er0_HWP && v->read.comp_s.plus.all==0)|| err) + { + v->real_delays.plus[i] = HWP_MAX_ERROR_DELAY_DEFINE*5; // - + if (may_be_err_ch) + continue; // , + v->status = component_Error; + + // er0_hwp, DAC + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + + err += hwp_read_comparators(v); + + if ( (v->read.comp_s.plus.all && v->read.errors.er0_HWP==0) || err) + { +// v->status = component_Error; + v->real_delays.plus[i] = HWP_MAX_ERROR_DELAY_DEFINE*6; // - + if (may_be_err_ch) + continue; // , + + // , er0_hwp, + // + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + +// + hwp_clear_delay(); + v->write.U_test = HWP_U_TEST_LEVEL_FOR_DO_PLUS_TEST; + convert_values(v); + err += hwp_write_u_test_dacs(v); + + + if (err) + { + if (may_be_err_ch) + continue; // , + + v->status = component_Error; + // DAC U_test + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + + DELAY_US(2000); + + hwp_read_error(v); + err = hwp_read_delay(v); + err += hwp_read_comparators(v); + + if (!v->read.errors.er0_HWP) + { +// v->status = component_Error; + v->real_delays.plus[i] = HWP_MAX_ERROR_DELAY_DEFINE*7; // - + if (may_be_err_ch) + continue; // , + + // er0_hwp, + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + + + if (v->read.comp_s.plus.all != v->write.mask.plus.all) + err++; + + if (v->low_setup.delay.bit.ready == 0 || err) + { + v->real_delays.plus[i] = HWP_MAX_ERROR_DELAY_DEFINE; // - + } + else + { + v->real_delays.plus[i] = v->low_setup.delay.bit.counter/6; + if (v->real_delays.plus[i]>=MINIMAL_TEST_TIME_ERROR_HWP && v->real_delays.plus[i]<=MAXIMAL_TEST_TIME_ERROR_HWP) + v->read.test_passed.plus.all |= (1 << i); + } + + v->write.values[i].plus = HWP_DEF_LEVEL_ERROR; + } + + +// prepare for test minus + // = 3500 mV + v->write.U_opora = 3500;//HWP_U_OPORA_DEFINE; + // 1500 mV + v->write.U_test = 1500;//HWP_U_TEST_DEFINE; + // 2000 mV. + // =0V . + + v->write.mask.minus.all = HWP_ENABLE_ALL_MASK; + v->write.mask.plus.all = HWP_ENABLE_ALL_MASK; + + convert_values(v); + convert_masks(v); + + err = 0; + err += hwp_write_all_dacs(v); + err += hwp_write_all_mask(v); + + if (err) + { + v->status = component_Error; + // DAC + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + + err += hwp_reset_error(v); + DELAY_US(2000); + hwp_read_error(v); + + if (v->read.errors.er0_HWP || err) + { + v->status = component_Error; + // er0_hwp, + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + +// minus + + for (i=2;i<16;i++) + { + v->write.mask.minus.all = HWP_ENABLE_ALL_MASK; + convert_masks(v); + err = hwp_write_all_mask(v); + + + err = 0; + v->read.test_passed.minus.all &= ~(1 << i); + + if (!(v->write.use_channel.minus.all & (1 << i))) + { + // + v->real_delays.minus[i] = HWP_MAX_ERROR_DELAY_DEFINE*10; // - + may_be_err_ch = 1; + if (v->write.test_all_channel==0) + continue; + } + else + may_be_err_ch = 0; + + + v->write.U_test = HWP_U_TEST_LEVEL_FOR_PREPARE_MINUS_TEST;//HWP_U_TEST_DEFINE; + v->write.U_opora = HWP_U_OPORA_LEVEL_FOR_PREPARE_MINUS_TEST;//HWP_U_OPORA_DEFINE; + + for (k=2;k<16;k++) + { + if (k==i) + v->write.values[k].minus = HWP_U_LEVEL_COMP_FOR_TEST_DEFINE; // + else + v->write.values[k].minus = HWP_DEF_LEVEL_ERROR; + } + + convert_values(v); + err += hwp_write_all_dacs(v); + + err += hwp_reset_error(v); + DELAY_US(2000); + + hwp_read_error(v); + err += hwp_read_comparators(v); + if (v->read.errors.er0_HWP || err) + { + v->real_delays.minus[i] = HWP_MAX_ERROR_DELAY_DEFINE*2; // - + if (may_be_err_ch) + continue; // , + + v->status = component_Error; + // er0_hwp, + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + + err += hwp_read_comparators(v); + + if (v->read.comp_s.minus.all || err) + { +// v->status = component_Error; + v->real_delays.minus[i] = HWP_MAX_ERROR_DELAY_DEFINE*3; // - + if (may_be_err_ch) + continue; // , + + // , er0_hwp, + // + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + +// , +// ! + v->write.mask.minus.all = HWP_DISABLE_ALL_MASK; // clear all mask + // v->write.mask.minus.all = (1 << i); // clear mask + if (may_be_err_ch==0) + v->write.mask.minus.all = v->write.use_channel.minus.all; + + + convert_masks(v); + err += hwp_write_all_mask(v); + + // , ! + err += hwp_read_comparators(v); + if (v->read.comp_s.minus.all || err) + { + v->real_delays.minus[i] = HWP_MAX_ERROR_DELAY_DEFINE*4; // - + if (may_be_err_ch) + continue; // , + // - ! + // , er0_hwp, + // + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + +// +// , ! + + v->write.mask.minus.all = (1 << i); // clear mask + convert_masks(v); + err += hwp_write_all_mask(v); + + // , ! + err += hwp_read_comparators(v); + if (v->read.comp_s.minus.all || err) + { + v->real_delays.minus[i] = HWP_MAX_ERROR_DELAY_DEFINE*5; // - + if (may_be_err_ch) + continue; // , + // - ! + // , er0_hwp, + // + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + + +// ERR0_HWP + + v->write.mask.minus.all = (1 << i); // will wait it status + + hwp_read_error(v); + if ((v->read.errors.er0_HWP && v->read.comp_s.minus.all==0) || err) + { + v->real_delays.minus[i] = HWP_MAX_ERROR_DELAY_DEFINE*6; // - + if (may_be_err_ch) + continue; // , + v->status = component_Error; + // er0_hwp, + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + + hwp_clear_delay(); + v->write.U_test = HWP_U_TEST_LEVEL_FOR_DO_MINUS_TEST; + convert_values(v); + err += hwp_write_u_test_dacs(v); + + if (err) + { + v->status = component_Error; + // DAC U_test + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + + DELAY_US(2000); + + hwp_read_error(v); + err = hwp_read_delay(v); + err += hwp_read_comparators(v); + + if (!v->read.errors.er0_HWP) + { + v->real_delays.minus[i] = HWP_MAX_ERROR_DELAY_DEFINE*7; // - + if (may_be_err_ch) + continue; // , +// v->status = component_Error; + // er0_hwp, + XERROR_DEBUG_MODE_HWP_NOT_READY; + continue; +// return 1; + } + + hwp_read_delay(v); + + err += hwp_read_comparators(v); + + if (v->read.comp_s.minus.all != v->write.mask.minus.all) + err++; + + if (v->low_setup.delay.bit.ready == 0 || err) + { + v->real_delays.minus[i] = HWP_MAX_ERROR_DELAY_DEFINE; // - + } + else + { + v->real_delays.minus[i] = v->low_setup.delay.bit.counter/6; + if (v->real_delays.minus[i]>=MINIMAL_TEST_TIME_ERROR_HWP && v->real_delays.minus[i]<=MAXIMAL_TEST_TIME_ERROR_HWP) + v->read.test_passed.minus.all |= (1 << i); + } + v->write.values[i].minus = HWP_DEF_LEVEL_ERROR; + + } + + +// m = (v->read.test_passed.minus.all & v->write.use_channel.minus.all); +// p = (v->read.test_passed.plus.all & v->write.use_channel.plus.all); + +// if ((v->write.use_channel.minus.all != v->read.test_passed.minus.all ) || (v->write.use_channel.plus.all != v->read.test_passed.plus.all ) ) + if ((v->write.use_channel.minus.all != (v->read.test_passed.minus.all & v->write.use_channel.minus.all) ) + || (v->write.use_channel.plus.all != (v->read.test_passed.plus.all & v->write.use_channel.plus.all ) ) ) + { + v->status = component_Error; + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + + +// finish + + v->write.U_test = HWP_U_TEST_DEFINE; + v->write.U_opora = HWP_U_OPORA_DEFINE; + + v->write.mask.minus.all = HWP_ENABLE_ALL_MASK; + v->write.mask.plus.all = HWP_ENABLE_ALL_MASK; + + convert_values(v); + convert_masks(v); + + err = 0; + err += hwp_write_all_dacs(v); + err += hwp_write_all_mask(v); + + if (err) + { + v->status = component_Error; + // DAC + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + + err += hwp_reset_error(v); + + hwp_read_error(v); + + if (v->read.errors.er0_HWP || err) + { + v->status = component_Error; + // er0_hwp, + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + return 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +int hwp_internal_test(T_hwp *v) +{ + int i,err; + T_hwp_channels old_mask; + unsigned int old_U_test, old_U_opora; + T_hwp_cannel_values old_channel_values[16]; + + if (v->useit == 0) + return 0; + + if (v->status != component_Ready) + return 1; + + // + for (i=0;i<16;i++) + { + if (v->write.values[i].plus>=HWP_U_OPORA_DEFINE) + { + XERROR_DEBUG_MODE_HWP_ERROR_SET_LEVEL_PROTECT; // , HWP_U_OPORA_DEFINE + v->status = component_Error; + return 1; + } + + if (v->write.values[i].minus>=HWP_U_OPORA_DEFINE) + { + XERROR_DEBUG_MODE_HWP_ERROR_SET_LEVEL_PROTECT; // , HWP_U_OPORA_DEFINE + v->status = component_Error; + return 1; + } + + } + + + + old_mask = v->write.mask; + old_U_test = v->write.U_test; + old_U_opora = v->write.U_opora; + for (i=0;i<16;i++) + old_channel_values[i] = v->write.values[i]; + + err = run_internal_test(v); + + v->write.mask = old_mask; + v->write.U_test = old_U_test; + v->write.U_opora = old_U_opora; + for (i=0;i<16;i++) + v->write.values[i] = old_channel_values[i]; + + convert_values(v); + convert_masks(v); + + err += hwp_write_all_dacs(v); + err += hwp_write_all_mask(v); + + if (err) + { +// XERROR_DEBUG_MODE_HWP_NOT_READY; + v->status = component_Error; + return 1; + } + + err += hwp_reset_error(v); + hwp_read_error(v); + + if (v->read.errors.er0_HWP || err) + { + v->status = component_Error; + // er0_hwp + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + + return 0; +} + +/////////////////////////////////////////////// +int hwp_read_delay(T_hwp *v) +{ + unsigned int cnt_wait_tr; + + if (v->useit == 0) + return 0; + + + v->low_setup.delay.bit.ready = 0; + cnt_wait_tr = MAX_WAIT_TEST_ERROR_HWP; + + // wait finish transmit data + while((v->low_setup.delay.bit.ready==0) && (cnt_wait_tr!=0)) + { + v->low_setup.delay.all = i_ReadMemory(ADR_HWP_TEST_TIMER); + cnt_wait_tr--; + } + + if (cnt_wait_tr==0) + return 1; // error + else + return 0; // all ok + + +} + + +/////////////////////////////////////////////// +void hwp_clear_delay(void) +{ + WriteMemory(ADR_HWP_TEST_TIMER, 0x0); +} + + +/////////////////////////////////////////////// +void hwp_autospeed_detect(T_hwp *v) +{ + int err1 = 0, err2 = 0; + + + // auto set speed? + if (v->write.HWP_Speed == MODE_HWP_SPEED_AUTO) + { + if (v->write.flag_detect_HWP_Speed == HWP_AUTOSPEED_NOTDETECTED) + { + v->low_setup.dac_config.bit.HWP_Speed = MODE_HWP_SPEED_SLOW; +// v->write.HWP_Speed = MODE_HWP_SPEED_SLOW; + + err1 = hwp_read_comparators(v); + + v->low_setup.dac_config.bit.HWP_Speed = MODE_HWP_SPEED_NORMAL; +// v->write.HWP_Speed = MODE_HWP_SPEED_NORMAL; + + err2 = hwp_read_comparators(v); + + + if (err1==0 /*&& err2==1*/) // - hwp !? !!! + { + v->write.flag_detect_HWP_Speed = HWP_AUTOSPEED_DETECTED; + v->write.HWP_Speed = MODE_HWP_SPEED_SLOW; + hwp_read_comparators(v); + return; + } + else + if (err1==1 && err2==0) + { + v->write.flag_detect_HWP_Speed = HWP_AUTOSPEED_DETECTED; + v->write.HWP_Speed = MODE_HWP_SPEED_NORMAL; + hwp_read_comparators(v); + return; + } + else + { + v->write.flag_detect_HWP_Speed = HWP_AUTOSPEED_FIALED; + v->write.HWP_Speed = MODE_HWP_SPEED_SLOW; + XERROR_DEBUG_MODE_HWP_NOT_READY; + return; + + } + + } // HWP_AUTOSPEED_NOTDETECTED + } // MODE_HWP_SPEED_AUTO + else + if (v->write.flag_detect_HWP_Speed == HWP_AUTOSPEED_NOTDETECTED) + v->write.flag_detect_HWP_Speed = HWP_AUTOSPEED_OFF; + +} + +/////////////////////////////////////////////// + +int hwp_read_all(T_hwp *v) +{ + int err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + if (v->status == component_Error || v->status == component_NotFinded) + return 2; + +// hwp_autospeed_detect(v); + + if (v->write.flag_detect_HWP_Speed == HWP_AUTOSPEED_FIALED) + { + if (v->status==component_NotReady) + v->status = component_NotFinded; + else + v->status = component_Error; + + return 2; + } + + v->low_setup.dac_config.bit.HWP_Speed = v->write.HWP_Speed; + err = hwp_read_comparators(v); + err_ready = check_cds_ready_hwpbus( err, ITS_READ_BUS, &v->status_hwp_bus); + + set_status_cds(err_ready, &v->status); + + return err_ready; +} + + +/////////////////////////////////////////////// +int hwp_read_comparators(T_hwp *v) +{ + + if (v->useit == 0) + return 0; + +// send cmd to read comparators + v->low_setup.dac_config.bit.DACOrMask = 1; + v->low_setup.dac_config.bit.R_W_Direction = 1; + + v->low_setup.transmitErr = wait_hwp_transfer(v); + + v->low_setup.dac_config.bit.DACOrMask = 0; + v->low_setup.dac_config.bit.R_W_Direction = 0; + + if (v->low_setup.transmitErr) + { + // HWP +// if (v->write.HWP_Speed != MODE_HWP_SPEED_AUTO) +// XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + + v->low_setup.comp_29to14.all = i_ReadMemory(ADR_HWP_DATA_RECEVED_0); + v->low_setup.comp_13to0.all = i_ReadMemory(ADR_HWP_DATA_RECEVED_1); + + + v->read.comp_s.plus.bit.ch0 = v->low_setup.comp_13to0.bit.DACCh0; + v->read.comp_s.plus.bit.ch1 = v->low_setup.comp_13to0.bit.DACCh1; + + v->read.comp_s.plus.bit.ch2 = v->low_setup.comp_13to0.bit.DACCh2; + v->read.comp_s.minus.bit.ch2 = v->low_setup.comp_13to0.bit.DACCh3; + + v->read.comp_s.plus.bit.ch3 = v->low_setup.comp_13to0.bit.DACCh4; + v->read.comp_s.minus.bit.ch3 = v->low_setup.comp_13to0.bit.DACCh5; + + v->read.comp_s.plus.bit.ch4 = v->low_setup.comp_13to0.bit.DACCh6; + v->read.comp_s.minus.bit.ch4 = v->low_setup.comp_13to0.bit.DACCh7; + + v->read.comp_s.plus.bit.ch5 = v->low_setup.comp_13to0.bit.DACCh8; + v->read.comp_s.minus.bit.ch5 = v->low_setup.comp_13to0.bit.DACCh9; + + v->read.comp_s.plus.bit.ch6 = v->low_setup.comp_13to0.bit.DACCh10; + v->read.comp_s.minus.bit.ch6 = v->low_setup.comp_13to0.bit.DACCh11; + + v->read.comp_s.plus.bit.ch7 = v->low_setup.comp_13to0.bit.DACCh12; + v->read.comp_s.minus.bit.ch7 = v->low_setup.comp_13to0.bit.DACCh13; + +// + v->read.comp_s.plus.bit.ch8 = v->low_setup.comp_29to14.bit.DACCh14; + v->read.comp_s.minus.bit.ch8 = v->low_setup.comp_29to14.bit.DACCh15; + + v->read.comp_s.plus.bit.ch9 = v->low_setup.comp_29to14.bit.DACCh16; + v->read.comp_s.minus.bit.ch9 = v->low_setup.comp_29to14.bit.DACCh17; + + v->read.comp_s.plus.bit.ch10 = v->low_setup.comp_29to14.bit.DACCh18; + v->read.comp_s.minus.bit.ch10 = v->low_setup.comp_29to14.bit.DACCh19; + + v->read.comp_s.plus.bit.ch11 = v->low_setup.comp_29to14.bit.DACCh20; + v->read.comp_s.minus.bit.ch11 = v->low_setup.comp_29to14.bit.DACCh21; + + v->read.comp_s.plus.bit.ch12 = v->low_setup.comp_29to14.bit.DACCh22; + v->read.comp_s.minus.bit.ch12 = v->low_setup.comp_29to14.bit.DACCh23; + + v->read.comp_s.plus.bit.ch13 = v->low_setup.comp_29to14.bit.DACCh24; + v->read.comp_s.minus.bit.ch13 = v->low_setup.comp_29to14.bit.DACCh25; + + v->read.comp_s.plus.bit.ch14 = v->low_setup.comp_29to14.bit.DACCh26; + v->read.comp_s.minus.bit.ch14 = v->low_setup.comp_29to14.bit.DACCh27; + + v->read.comp_s.plus.bit.ch15 = v->low_setup.comp_29to14.bit.DACCh28; + v->read.comp_s.minus.bit.ch15 = v->low_setup.comp_29to14.bit.DACCh29; + + return 0; + +} +/////////////////////////////////////////////// + + +int hwp_write_all_mask(T_hwp *v) +{ + if (v->useit == 0) + return 0; + + WriteMemory(ADR_HWP_DATA_RECEVED_0, v->low_setup.mask_29to14.all); + WriteMemory(ADR_HWP_DATA_RECEVED_1, v->low_setup.mask_13to0.all); + +// send cmd to write masks + v->low_setup.dac_ch.bit.DACChannelNumb = 0; + v->low_setup.dac_config.bit.DACOrMask = 1; + v->low_setup.dac_config.bit.ErrReset = 0; + v->low_setup.dac_config.bit.R_W_Direction = 0; + v->low_setup.dac_config.bit.DACNumber = 0; + + v->low_setup.transmitErr = wait_hwp_transfer(v); + + v->low_setup.dac_config.bit.DACOrMask = 0; + + if (v->low_setup.transmitErr) + { + // HWP + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 1; + } + + return 0; +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// +int hwp_write_u_test_dacs(T_hwp *v) +{ + + if (v->useit == 0) + return 0; + + v->low_setup.dac_ch.bit.DACChannelNumb = 0; + v->low_setup.dac_config.bit.DACOrMask = 0; + v->low_setup.dac_config.bit.ErrReset = 0; + v->low_setup.dac_config.bit.R_W_Direction = 0; + v->low_setup.dac_config.bit.DACNumber = 0; + + //HWP LOAD___________________ + + v->low_setup.dac_ch.bit.DACValue = v->low_setup.DACValues[0]; + v->low_setup.dac_ch.bit.DACChannelNumb = 0; + WriteMemory(ADR_HWP_SERVICE_1, v->low_setup.dac_ch.all); + + v->low_setup.transmitErr = wait_hwp_transfer(v); + + if(v->low_setup.transmitErr) + { + v->read.errors.transmit_data = 1; + return 1; + } + + return 0; +} +/////////////////////////////////////////////// +// return - 0 - all ok +// 1 - timeout send +// 2 - error transfer +/////////////////////////////////////////////// +int wait_hwp_transfer(T_hwp *v) +{ + unsigned int cnt_wait_tr; + volatile unsigned int r_hwp; + int err; + + err = 1; + cnt_wait_tr = MAX_WAIT_TRANSMIT_TO_HWP; + + v->low_setup.dac_config.bit.transfer_finished = 0; + WriteMemory(ADR_HWP_SERVICE_0, v->low_setup.dac_config.all); + + DELAY_US(500); + + // wait finish transmit data + while(err && (cnt_wait_tr!=0)) + { + r_hwp = ReadMemory (ADR_HWP_SERVICE_0); + if (r_hwp & 0x1) + err = 0; + cnt_wait_tr--; + DELAY_US(10); + } + + if (err) + return err; + + // error transmit? + r_hwp = ReadMemory (ADR_HWP_SERVICE_0); + + if (r_hwp & 0x2) + return 2; + else + return 0; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +int hwp_write_all_dacs(T_hwp *v) +{ + int i = 0, j = 0; + + if (v->useit == 0) + return 0; + + v->low_setup.dac_ch.bit.DACChannelNumb = 0; + v->low_setup.dac_config.bit.DACOrMask = 0; + v->low_setup.dac_config.bit.ErrReset = 0; + v->low_setup.dac_config.bit.R_W_Direction = 0; + v->low_setup.dac_config.bit.DACNumber = 0; + + //HWP LOAD___________________ + + while(i < 32) + { + DELAY_US(200); + DELAY_US(200); + + v->low_setup.dac_ch.bit.DACValue = v->low_setup.DACValues[i]; + if ((i%8 == 0) && i!=0) + { + j = 0; + v->low_setup.dac_config.bit.DACNumber++; + } + v->low_setup.dac_ch.bit.DACChannelNumb = j; + WriteMemory(ADR_HWP_SERVICE_1, v->low_setup.dac_ch.all); + DELAY_US(200); + DELAY_US(200); + + v->low_setup.transmitErr = wait_hwp_transfer(v); + + if(v->low_setup.transmitErr) + { + v->read.errors.transmit_data = 0; + + if (i<16) + v->low_setup.error_transfer_to_dac_0_1.all |= (1 << i); + + if (i>=16) + v->low_setup.error_transfer_to_dac_2_3.all |= (1 << (i-16)); + + i++; + j++; + } + else + { + i++; + j++; + } + + } + + if ( (v->low_setup.error_transfer_to_dac_0_1.all == 0xffff) + && (v->low_setup.error_transfer_to_dac_2_3.all == 0xffff)) + { + v->read.errors.transmit_data = 1; + // DAC + // ! + XERROR_DEBUG_MODE_HWP_NOT_READY; + return 2; + } + + + if (v->low_setup.error_transfer_to_dac_0_1.all || v->low_setup.error_transfer_to_dac_2_3.all) + { + v->read.errors.transmit_data = 1; + // DAC + XERROR_DEBUG_MODE_HWP_NOT_READY; + } + + if (v->read.errors.transmit_data) + return 1; + else + return 0; + +} + + + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + +int hwp_write_all(T_hwp *v) +{ + + int err = 0, err_ready = 0; + + if (v->useit == 0) + return 0; + + if (v->status == component_Error || v->status == component_NotFinded) + return 1; + + hwp_autospeed_detect(v); + + if (v->write.flag_detect_HWP_Speed == HWP_AUTOSPEED_FIALED) + { + if (v->status==component_NotReady) + v->status = component_NotFinded; + else + v->status = component_Error; + return 1; + } + + if (v->write.HWP_Speed>1) // 0 1, 16 + { + // , , . + XERROR_DEBUG_MODE_HWP_NOT_READY; + } + v->low_setup.dac_config.bit.HWP_Speed = v->write.HWP_Speed; + + convert_values(v); + convert_masks(v); + + err = hwp_write_all_dacs(v); + + if (err == 0) + err = hwp_write_all_mask(v); + + + if (err) + { + if (v->status==component_NotReady) + v->status = component_NotFinded; + else + v->status = component_Error; + } + else + v->status = component_Ready; + + err_ready = check_cds_ready_hwpbus( err, ITS_WRITE_BUS, &v->status_hwp_bus); + + + return 0; + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void hwp_read_error(T_hwp *v) +{ + if (v->useit == 0) + return ; + + r_controller.errors.all = i_ReadMemory (ADR_ERRORS_TOTAL_INFO); + v->read.errors.er0_HWP = r_controller.errors.bit.errHWP; + + +} +/////////////////////////////////////////////// + +int hwp_reset_error(T_hwp *v) +{ + int err; + + if (v->useit == 0) + return 0; + + if (v->status == component_NotReady || v->status == component_NotFinded) + return 1; + + + if (v->status == component_Error) + v->status = component_Started; + clear_cur_stat_hwpbus(&v->status_hwp_bus); + + + + err = 0; + v->low_setup.dac_config.bit.ErrReset = 1; + + v->low_setup.transmitErr = wait_hwp_transfer(v); + + if (v->low_setup.transmitErr) + { + // HWP + XERROR_DEBUG_MODE_HWP_NOT_READY; + err = 1; + } + + + DELAY_US(200); + + v->low_setup.dac_config.bit.ErrReset = 0; + + return err; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void hwp_store_disable_error(T_hwp *v) +{ + if (v->useit == 0) + return ; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void hwp_restore_enable_error(T_hwp *v) +{ + if (v->useit == 0) + return ; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + + + + + + + + + + + + + + + + + + + diff --git a/Inu/Src/N12_Xilinx/xp_hwp.h b/Inu/Src/N12_Xilinx/xp_hwp.h new file mode 100644 index 0000000..2fbec28 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_hwp.h @@ -0,0 +1,445 @@ +#ifndef XP_HWP_H +#define XP_HWP_H + +#include "x_basic_types.h" +#include "xp_cds_status_bus.h" +#include "xp_id_plate_info.h" + + +#define MODE_HWP_SPEED_NORMAL 0 // 0 - HWP ( ) +#define MODE_HWP_SPEED_SLOW 1 // 1 - HWP ( ) +#define MODE_HWP_SPEED_AUTO 16 // 16 - : 0 and 1 + + +enum {HWP_AUTOSPEED_NOTDETECTED=0, + HWP_AUTOSPEED_DETECTED, + HWP_AUTOSPEED_FIALED, + HWP_AUTOSPEED_OFF +}; + +#define HWP_SPEED_VERSION_DEFINE MODE_HWP_SPEED_AUTO // MODE_HWP_SPEED_NORMAL + +#define UrefDAC 4000.0 // 4V Uref DAC - +#define HWP_U_OPORA_DEFINE 2000 // mV = 2 - +#define HWP_U_TEST_DEFINE 0 // mV = 0 + +#define HWP_ENABLE_ALL_MASK 0x0 // 0 = = +#define HWP_DISABLE_ALL_MASK 0xffff // 1 = = + +#define MAX_WAIT_TRANSMIT_TO_HWP 1000 // HWP +#define MAX_WAIT_TEST_ERROR_HWP 50000 // , DELAY +#define HWP_U_LEVEL_COMP_FOR_TEST_DEFINE 1000 // mV - +#define HWP_MAX_ERROR_DELAY_DEFINE 1000 // . + +#define HWP_U_TEST_LEVEL_FOR_DO_PLUS_TEST 1100 //mV - U_TEST +#define HWP_U_TEST_LEVEL_FOR_DO_MINUS_TEST 0 //mV- U_TEST + +#define HWP_U_TEST_LEVEL_FOR_PREPARE_MINUS_TEST 1500 //mV - U_TEST +#define HWP_U_OPORA_LEVEL_FOR_PREPARE_MINUS_TEST 3500 //mV- U_OPORA +#define HWP_U_TEST_LEVEL_FOR_PREPARE_PLUS_TEST 0 //mV - U_TEST +#define HWP_U_OPORA_LEVEL_FOR_PREPARE_PLUS_TEST 2000 //mV - U_OPORA + + +#define HWP_DEF_LEVEL_ERROR 1900 // mV - + +/////////////////////////////// +#define MINIMAL_TEST_TIME_ERROR_HWP 15 // mks*10 , - +#define MAXIMAL_TEST_TIME_ERROR_HWP 200 //mks*10 , - + +#define HWP_DEFAULT_USE_CHANNEL_PLUS 0xffff // +#define HWP_DEFAULT_USE_CHANNEL_MINUS 0xfffc // , 0 1. . + + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + +typedef union{ + unsigned int all; + struct{ + unsigned int DACValue:12; + unsigned int DACChannelNumb:4; + }bit; +}DAC_Channals; + +typedef union{ + unsigned int all; + struct{ + unsigned int transfer_finished:1; + unsigned int transmitErr:1; + unsigned int Reserv:7; + unsigned int HWP_Speed:1; + unsigned int DACNumber:2; + unsigned int ErrReset:1; + unsigned int DACOrMask:1; + unsigned int R_W_Direction:1; + unsigned int HWPAddress:1; + }bit; +}HWPDACConfig; + +typedef union{ + unsigned int all; + struct{ + unsigned int DACCh14:1; + unsigned int DACCh15:1; + unsigned int DACCh16:1; + unsigned int DACCh17:1; + unsigned int DACCh18:1; + unsigned int DACCh19:1; + unsigned int DACCh20:1; + unsigned int DACCh21:1; + unsigned int DACCh22:1; + unsigned int DACCh23:1; + unsigned int DACCh24:1; + unsigned int DACCh25:1; + unsigned int DACCh26:1; + unsigned int DACCh27:1; + unsigned int DACCh28:1; + unsigned int DACCh29:1; + }bit; +}MaskDACs_29to14; + +typedef union{ + unsigned int all; + struct{ + unsigned int Reserve:2; + unsigned int DACCh0:1; + unsigned int DACCh1:1; + unsigned int DACCh2:1; + unsigned int DACCh3:1; + unsigned int DACCh4:1; + unsigned int DACCh5:1; + unsigned int DACCh6:1; + unsigned int DACCh7:1; + unsigned int DACCh8:1; + unsigned int DACCh9:1; + unsigned int DACCh10:1; + unsigned int DACCh11:1; + unsigned int DACCh12:1; + unsigned int DACCh13:1; + }bit; +}MaskDACs_13to0; + +typedef struct{ + DAC_Channals dac_ch; + HWPDACConfig dac_config; + MaskDACs_29to14 mask_29to14; + MaskDACs_13to0 mask_13to0; + MaskDACs_29to14 comp_29to14; + MaskDACs_13to0 comp_13to0; + unsigned int transmitErr; + unsigned int DACValues[32]; + + union + { + UInt16 all; + struct + { + UInt16 counter :15; + UInt16 ready :1; + } bit; + } delay; + + union + { + UInt16 all; + struct + { + unsigned int DAC0Ch0:1; + unsigned int DAC0Ch1:1; + unsigned int DAC0Ch2:1; + unsigned int DAC0Ch3:1; + unsigned int DAC0Ch4:1; + unsigned int DAC0Ch5:1; + unsigned int DAC0Ch6:1; + unsigned int DAC0Ch7:1; + + unsigned int DAC1Ch0:1; + unsigned int DAC1Ch1:1; + unsigned int DAC1Ch2:1; + unsigned int DAC1Ch3:1; + unsigned int DAC1Ch4:1; + unsigned int DAC1Ch5:1; + unsigned int DAC1Ch6:1; + unsigned int DAC1Ch7:1; + } bit; + } error_transfer_to_dac_0_1; + + union + { + UInt16 all; + struct + { + unsigned int DAC2Ch0:1; + unsigned int DAC2Ch1:1; + unsigned int DAC2Ch2:1; + unsigned int DAC2Ch3:1; + unsigned int DAC2Ch4:1; + unsigned int DAC2Ch5:1; + unsigned int DAC2Ch6:1; + unsigned int DAC2Ch7:1; + + unsigned int DAC3Ch0:1; + unsigned int DAC3Ch1:1; + unsigned int DAC3Ch2:1; + unsigned int DAC3Ch3:1; + unsigned int DAC3Ch4:1; + unsigned int DAC3Ch5:1; + unsigned int DAC3Ch6:1; + unsigned int DAC3Ch7:1; + } bit; + } error_transfer_to_dac_2_3; + +}HWPstr; + + +#define HWPstr_DEFAULTS {0,0,0,0,0,0,0,{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},0,0,0} + + + + + + +unsigned int calcVoltsToDACUop(unsigned int miliVolts); +unsigned int voltsForChanals(int miliVolts, unsigned int miliVoltsUop); +unsigned int calcVoltsToDACUtest(unsigned int miliVolts); + + +typedef struct{ + union + { + UInt16 all; + struct + { + UInt16 ch0 :1; + UInt16 ch1 :1; + UInt16 ch2 :1; + UInt16 ch3 :1; + + UInt16 ch4 :1; + UInt16 ch5 :1; + UInt16 ch6 :1; + UInt16 ch7 :1; + + UInt16 ch8 :1; + UInt16 ch9 :1; + UInt16 ch10 :1; + UInt16 ch11 :1; + + UInt16 ch12 :1; + UInt16 ch13 :1; + UInt16 ch14 :1; + UInt16 ch15 :1; + + } bit; + } minus; + + union + { + UInt16 all; + struct + { + UInt16 ch0 :1; + UInt16 ch1 :1; + UInt16 ch2 :1; + UInt16 ch3 :1; + + UInt16 ch4 :1; + UInt16 ch5 :1; + UInt16 ch6 :1; + UInt16 ch7 :1; + + UInt16 ch8 :1; + UInt16 ch9 :1; + UInt16 ch10 :1; + UInt16 ch11 :1; + + UInt16 ch12 :1; + UInt16 ch13 :1; + UInt16 ch14 :1; + UInt16 ch15 :1; + + } bit; + } plus; +} T_hwp_channels; + + + +typedef struct{ + unsigned int minus; + unsigned int plus; +} T_hwp_cannel_values; + +#define T_HWP_CANNEL_VALUES_DEFAULTS {HWP_DEF_LEVEL_ERROR, HWP_DEF_LEVEL_ERROR} + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +//write reg hwp bus +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + +typedef struct{ + + T_hwp_channels mask; + T_hwp_channels use_channel; + + unsigned int U_test; + unsigned int U_opora; + + unsigned int HWP_Speed; + + unsigned int flag_detect_HWP_Speed; + unsigned int test_all_channel; // , + + T_hwp_cannel_values values[16]; +} T_hwp_write; + + +#define T_HWP_WRITE_DEFAULTS {\ + {0xffff,0xffff},\ + { HWP_DEFAULT_USE_CHANNEL_MINUS, HWP_DEFAULT_USE_CHANNEL_PLUS },\ + HWP_U_TEST_DEFINE,HWP_U_OPORA_DEFINE,HWP_SPEED_VERSION_DEFINE, HWP_AUTOSPEED_NOTDETECTED, 0, \ + { T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, \ + T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, \ + T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, \ + T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS, T_HWP_CANNEL_VALUES_DEFAULTS\ + }\ + } + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct{ + union + { + UInt16 all; + struct + { + UInt16 counter :14; + UInt16 ready :1; + } bit; + } timer; +} T_hwp_delay; + +////////////////////////////////////////////////////////////// +typedef struct{ + unsigned int er0_HWP; + unsigned int transmit_data; + +} T_hwp_errors; + +#define T_HWP_ERRORS_DEFAULTS {0,0} +////////////////////////////////////////////////////////////// +typedef struct{ + T_hwp_errors errors; + T_hwp_channels comp_s; + T_hwp_channels test_passed; +} T_hwp_read; + + +#define T_HWP_READ_DEFAULTS {T_HWP_ERRORS_DEFAULTS,{0,0},{0,0}} +////////////////////////////////////////////////////////////// + +typedef struct{ + unsigned int plus[16]; + unsigned int minus[16]; +} T_hwp_delays; +#define T_HWP_DELAYS_DEFAULTS {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}} +////////////////////////////////////////////////////////////// + + +typedef struct TS_hwp{ + UInt16 plane_address; // 0 to 15 + UInt16 useit; + T_cds_status_hwp_bus status_hwp_bus; + T_component_status status; + T_local_status local_status; + + T_hwp_delays real_delays; + + T_hwp_read read; + T_hwp_write write; + + HWPstr low_setup; + + + void (*init)(); // Pointer to calculation function + int (*internal_test)(); // Pointer to calculation function + + int (*read_all)(); // Pointer to calculation function + int (*write_all)(); // Pointer to calculation function + + int (*convert_values)(); // Pointer to calculation function + + int (*reset_error)(); // Pointer to calculation function + void (*store_disable_error)(); // Pointer to calculation function + void (*restore_enable_error)(); // Pointer to calculation function + void (*autospeed_detect)(); // Pointer to calculation function +} T_hwp; + + +typedef T_hwp *T_hwp_handle; + +//----------------------------------------------------------------------------- +// Default initalizer for object. +//----------------------------------------------------------------------------- +#define T_hwp_DEFAULTS { 0,\ + 0,\ + T_cds_status_hwp_bus_DEFAULT,\ + component_NotReady,\ + local_status_NotReady,\ + T_HWP_DELAYS_DEFAULTS,\ + T_HWP_READ_DEFAULTS,\ + T_HWP_WRITE_DEFAULTS,\ + HWPstr_DEFAULTS,\ + (void (*)(Uint32))hwp_init,\ + (int (*)(Uint32))hwp_internal_test,\ + (int (*)(Uint32))hwp_read_all,\ + (int (*)(Uint32))hwp_write_all,\ + (int (*)(Uint32))convert_values,\ + (int (*)(Uint32))hwp_reset_error,\ + (void (*)(Uint32))hwp_store_disable_error,\ + (void (*)(Uint32))hwp_restore_enable_error,\ + (void (*)(Uint32))hwp_autospeed_detect\ +} + +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +void hwp_init(T_hwp_handle); + +int run_internal_test(T_hwp_handle); + +int hwp_internal_test(T_hwp_handle); +int hwp_read_all(T_hwp_handle); +int hwp_write_all(T_hwp_handle); +void hwp_autospeed_detect(T_hwp_handle); + + +int convert_values(T_hwp_handle); +int convert_masks(T_hwp_handle); + + +int hwp_reset_error(T_hwp_handle); +void hwp_store_disable_error(T_hwp_handle); +void hwp_restore_enable_error(T_hwp_handle); + +int hwp_write_all_mask(T_hwp_handle); +int hwp_write_all_dacs(T_hwp_handle); + +int hwp_read_comparators(T_hwp_handle); +int hwp_read_delay(T_hwp_handle); +void hwp_clear_delay(void); + +void hwp_read_error(T_hwp_handle); +int hwp_write_u_test_dacs(T_hwp_handle); + +int wait_hwp_transfer(T_hwp_handle); +//------------------------------------------------------------------------------ +// Return Type +//------------------------------------------------------------------------------ + +#endif diff --git a/Inu/Src/N12_Xilinx/xp_id_plate_info.h b/Inu/Src/N12_Xilinx/xp_id_plate_info.h new file mode 100644 index 0000000..3a9ac66 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_id_plate_info.h @@ -0,0 +1,71 @@ +#ifndef XP_ID_PLATE_INFO_H +#define XP_ID_PLATE_INFO_H + + +#define PLATE_TYPE_RESERVED 1 +#define PLATE_TYPE_IN 1 +#define PLATE_TYPE_TK_ICEBREAKER 1 +#define PLATE_TYPE_TK_BALZAM 1 +#define PLATE_TYPE_ADC 1 +#define PLATE_TYPE_TK_21300 1 +#define PLATE_TYPE_TK_23550 1 +#define PLATE_TYPE_OUT 1 +#define PLATE_TYPE_TK_EDRK 1 +#define PLATE_TYPE_ROT_SENSOR_PLATE 1 + + +typedef enum { + plate_type_undefined= 0, + plate_type_reserved, + plate_type_IN, + plate_type_TK_ICEBREAKER = 5, + plate_type_TK_BALZAM, + plate_type_ADC, + plate_type_TK_21300 = 9, + plate_type_TK_23550 = 10, + plate_type_OUT = 11, + plate_type_TK_EDRK = 13, + plate_type_ROT_SENSOR_PLATE = 14 +} T_plate_type; + +/* + +"BITS (15:11) - plate type +0 -undefined, +1-RESERVED +2-IN +3-RESERVED +4-RESERVED +5-TK-ICEBREAKER +6-TK-BALZAM +7-ADC +8-RESERVED +9-TK-21300(2 LEVEL INV STANDART_TYPE) +10-TK-23550(BALSAM Modification with optics serial interface) +11-OUT +12-RESERVED +13-TK_EDRK +14-ROT_SENSOR_PLATE +15-to 31 RESERVED + +BITS (10:5) -Version +0-UNDEFINED , 51, = 50 + +BITS (4:0) - Revision +0-UNDEFINED, 1- A, 2-B.. 26-Z +" +*/ + + + + + +/*------------------------------------------------------------------------------ + Plane counter +------------------------------------------------------------------------------*/ + + +#endif // end XP_ID_PLATE_INFO_H + + + diff --git a/Inu/Src/N12_Xilinx/xp_inc_sensor.c b/Inu/Src/N12_Xilinx/xp_inc_sensor.c new file mode 100644 index 0000000..493c106 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_inc_sensor.c @@ -0,0 +1,396 @@ +#include "xp_project.h" +#include "xp_inc_sensor.h" + +#include "xp_project.h" + + +T_inc_sensor inc_sensor = T_INC_SENSOR_DEFAULT; + +//, +#define SAMPLING_TIME_NS 1 // 16,666667ns +#define SAMPLING_TIME_MS 0 // 1,666667us +// , . +// "" +// +#define LEVEL_SWITCH_NANOSEC 300 +#define LEVEL_SWITCH_MICROSEC 40000 + + +static void read_in_sensor_line1(T_inc_sensor *inc_s); +static void read_in_sensor_line2(T_inc_sensor *inc_s); +static void read_command_reg(T_inc_sensor *inc_s); +static void write_command_reg(T_inc_sensor *inc_s); +static void tune_sampling_time(T_inc_sensor *inc_s); +static void wait_for_registers_updated(T_inc_sensor *inc_s); +static void read_direction_in_plane(T_inc_sensor *inc_s); +static void detect_break_sensor_1_2(T_inc_sensor *inc_s); + +void sensor_set(T_inc_sensor *inc_s) +{ +/* + if(inc_s->use_sensor1 || inc_s->use_sensor2) + { + inc_s->in_plane.set(&inc_s->in_plane); + } + if(inc_s->use_angle_plane) + { + inc_s->rotation_plane.set(&inc_s->rotation_plane); + } +*/ +} + +void inc_sensor_set(T_inc_sensor *inc_s) +{ +/* + if(!inc_s->cds_in->useit) + { + return; + } + + inc_s->cds_in->write.sbus.enabled_channels.all = inc_s->write.sbus.enabled_channels.all; + inc_s->cds_in->write.sbus.first_sensor.all = inc_s->write.sbus.first_sensor_inputs.all; + inc_s->cds_in->write.sbus.second_sensor.all = inc_s->write.sbus.second_sensor_inputs.all; + // inc_s->cds_in->write_sbus(inc_s->cds_in); + write_command_reg(inc_s); +*/ + + write_command_reg(inc_s); + +} + + +void inc_sensor_read(T_inc_sensor *inc_s) +{ + if (inc_s->use_sensor1 || inc_s->use_sensor2) + { + wait_for_registers_updated(inc_s); + read_direction_in_plane(inc_s); + } + else + { + return; + } + + if (inc_s->use_sensor1) + { + inc_s->read_sensor1(inc_s); + } + + if (inc_s->use_sensor2) + { + inc_s->read_sensor2(inc_s); + } + + detect_break_sensor_1_2(inc_s); + +#ifdef AUTO_CHANGE_SAMPLING_TIME + tune_sampling_time(inc_s); +#endif +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// +#define MAX_COUNT_OVERFULL_DISCRET_3 150 +#pragma CODE_SECTION(inc_sensor_read1,".fast_run"); +void inc_sensor_read1(T_inc_sensor *inc_s) +{ + read_in_sensor_line1(inc_s); + +//#if C_PROJECT_TYPE != PROJECT_BALZAM + inc_s->data.Impulses1 = inc_s->pm67regs.n_impulses_line1; + inc_s->data.Time1 = inc_s->pm67regs.time_line1/60; + //Counter`s freq is 60 => N/60 = time in mksec + + if (inc_s->pm67regs.n_impulses_line1>=2) + { + inc_s->data.TimeCalcFromImpulses1 = (unsigned long)inc_s->pm67regs.time_line1*1000/inc_s->pm67regs.n_impulses_line1; + inc_s->data.TimeCalcFromImpulses1 /= 60; + } + else + inc_s->data.TimeCalcFromImpulses1 = 0; + + +//#endif + //inc_s->data.CountZero1 = inc_s->pm67regs.zero_time_line1; + + if (inc_s->pm67regs.zero_time_line1==0) + { + if (inc_s->data.countCountZero1==MAX_COUNT_OVERFULL_DISCRET_3) + { + inc_s->data.prev_CountZero1 = inc_s->data.CountZero1 = 0; + } + else + { + inc_s->data.CountZero1 = inc_s->data.prev_CountZero1; + inc_s->data.countCountZero1++; + } + } + else + { + inc_s->data.countCountZero1 = 0; + inc_s->data.CountZero1 = inc_s->pm67regs.zero_time_line1; + inc_s->data.prev_CountZero1 = inc_s->pm67regs.zero_time_line1; + } + +// inc_s->data.CountOne1 = inc_s->pm67regs.one_time_line1; + if (inc_s->pm67regs.one_time_line1==0) + { + if (inc_s->data.countCountOne1==MAX_COUNT_OVERFULL_DISCRET_3) + { + inc_s->data.prev_CountOne1 = inc_s->data.CountOne1 = 0; + } + else + { + inc_s->data.CountOne1 = inc_s->data.prev_CountOne1; + inc_s->data.countCountOne1++; + } + } + else + { + inc_s->data.countCountOne1 = 0; + inc_s->data.CountOne1 = inc_s->pm67regs.one_time_line1; + inc_s->data.prev_CountOne1 = inc_s->pm67regs.one_time_line1; + } + + + inc_s->data.counter_freq1 = inc_s->pm67regs.read_comand_reg.bit.sampling_time1; + +// inc_s->data.direction1 = inc_s->read.pbus.direction.bit.sensor1; +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// +#pragma CODE_SECTION(inc_sensor_read2,".fast_run"); +void inc_sensor_read2(T_inc_sensor *inc_s) +{ + read_in_sensor_line2(inc_s); + +//#if C_PROJECT_TYPE != PROJECT_BALZAM + inc_s->data.Impulses2 = inc_s->pm67regs.n_impulses_line2; + inc_s->data.Time2 = inc_s->pm67regs.time_line2 / 60; + //Counter`s freq is 60 => N/60 = time in mksec + + if (inc_s->pm67regs.n_impulses_line2>=2) + { + inc_s->data.TimeCalcFromImpulses2 = (unsigned long)inc_s->pm67regs.time_line2*1000/inc_s->pm67regs.n_impulses_line2; + inc_s->data.TimeCalcFromImpulses2 /= 60; + } + else + inc_s->data.TimeCalcFromImpulses2 = 0; + +//#endif + //inc_s->data.CountZero1 = inc_s->pm67regs.zero_time_line1; + + if (inc_s->pm67regs.zero_time_line2==0) + { + if (inc_s->data.countCountZero2==MAX_COUNT_OVERFULL_DISCRET_3) + { + inc_s->data.prev_CountZero2 = inc_s->data.CountZero2 = 0; + } + else + { + inc_s->data.CountZero2 = inc_s->data.prev_CountZero2; + inc_s->data.countCountZero2++; + } + } + else + { + inc_s->data.countCountZero2 = 0; + inc_s->data.CountZero2 = inc_s->pm67regs.zero_time_line2; + inc_s->data.prev_CountZero2 = inc_s->pm67regs.zero_time_line2; + } + +// inc_s->data.CountOne1 = inc_s->pm67regs.one_time_line1; + if (inc_s->pm67regs.one_time_line2==0) + { + if (inc_s->data.countCountOne2==MAX_COUNT_OVERFULL_DISCRET_3) + { + inc_s->data.prev_CountOne2 = inc_s->data.CountOne2 = 0; + } + else + { + inc_s->data.CountOne2 = inc_s->data.prev_CountOne2; + inc_s->data.countCountOne2++; + } + } + else + { + inc_s->data.countCountOne2 = 0; + inc_s->data.CountOne2 = inc_s->pm67regs.one_time_line2; + inc_s->data.prev_CountOne2 = inc_s->pm67regs.one_time_line2; + } + + inc_s->data.counter_freq2 = inc_s->pm67regs.read_comand_reg.bit.sampling_time2; + +// inc_s->data.direction2 = inc_s->read.pbus.direction.bit.sensor2; + +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void read_in_sensor_line1(T_inc_sensor *inc_s) +{ + + if(!inc_s->pm67regs.read_comand_reg.bit.update_registers) + { + + inc_s->pm67regs.time_line1 = i_ReadMemory(ADR_SENSOR_S1_T_PERIOD);//TODO check time when turn off + inc_s->pm67regs.n_impulses_line1 = i_ReadMemory(ADR_SENSOR_S1_COUNT_IMPULS); + + inc_s->pm67regs.zero_time_line1 = i_ReadMemory(ADR_SENSOR_S1_T_PERIOD_LOW_ONE_IMPULS); + inc_s->pm67regs.one_time_line1 = i_ReadMemory(ADR_SENSOR_S1_T_PERIOD_HIGH_ONE_IMPULS); + } + +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void read_in_sensor_line2(T_inc_sensor *inc_s) +{ + if(!inc_s->pm67regs.read_comand_reg.bit.update_registers) + { + + inc_s->pm67regs.time_line2 = i_ReadMemory(ADR_SENSOR_S2_T_PERIOD);//TODO check time when turn off + inc_s->pm67regs.n_impulses_line2 = i_ReadMemory(ADR_SENSOR_S2_COUNT_IMPULS); + + inc_s->pm67regs.zero_time_line2 = i_ReadMemory(ADR_SENSOR_S2_T_PERIOD_LOW_ONE_IMPULS); + inc_s->pm67regs.one_time_line2 = i_ReadMemory(ADR_SENSOR_S2_T_PERIOD_HIGH_ONE_IMPULS); + } +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void write_command_reg(T_inc_sensor *inc_s) +{ + WriteMemory(ADR_SENSOR_CMD, inc_s->pm67regs.write_comand_reg.all); +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void read_command_reg(T_inc_sensor *inc_s) +{ + inc_s->pm67regs.read_comand_reg.all = i_ReadMemory(ADR_SENSOR_CMD); +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void update_sensors_data_s(T_inc_sensor *inc_s) +{ + inc_s->pm67regs.write_comand_reg.bit.update_registers = 1; + write_command_reg(inc_s); +// inc_s->in_plane.write.regs.comand_reg.bit.update_registers = 0; +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void read_direction_in_plane(T_inc_sensor *inc_s) +{ +/* + inc_s->read.pbus.direction.bit.sensor1 = inc_s->cds_in->read.pbus.direction_in.bit.dir0 == 2 ? 1 : + inc_s->cds_in->read.pbus.direction_in.bit.dir0 == 1 ? -1 : + 0; + inc_s->read.pbus.direction.bit.sensor2 = inc_s->cds_in->read.pbus.direction_in.bit.dir1 == 2 ? 1 : + inc_s->cds_in->read.pbus.direction_in.bit.dir1 == 1 ? -1 : + 0; + inc_s->read.pbus.direction.bit.sens_err1 = inc_s->cds_in->read.pbus.direction_in.bit.dir0 == 3; + inc_s->read.pbus.direction.bit.sens_err2 = inc_s->cds_in->read.pbus.direction_in.bit.dir1 == 3; + //Direction changes not often. May be, it`s enough to read it in main cycle. +*/ +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void wait_for_registers_updated(T_inc_sensor *inc_s) +{ + int counter_in_while = 0; + read_command_reg(inc_s); + while(inc_s->pm67regs.read_comand_reg.bit.update_registers) + { + read_command_reg(inc_s); + inc_s->count_wait_for_update_registers++; + counter_in_while++; + if(counter_in_while > 1000) + { + inc_s->error_update++; + break; + } + } +} + +//////////////////////////////////////////////////////// +void detect_break_sensor_1_2(T_inc_sensor *inc_s) +{ + unsigned int f1 = (inc_s->data.CountOne1 || inc_s->data.CountZero1); + unsigned int f2 = (inc_s->data.CountOne2 || inc_s->data.CountZero2); + + + if (f1 && f2==0) + { + inc_s->break_sensor1 = 0; + inc_s->break_sensor2 = 1; + } + + if (f1==0 && f2) + { + inc_s->break_sensor1 = 1; + inc_s->break_sensor2 = 0; + } + + if ((f1==0 && f2==0) || (f1 && f2)) + { + inc_s->break_sensor1 = 0; + inc_s->break_sensor2 = 0; + } + + +} +//////////////////////////////////////////////////////// + + +void tune_sampling_time(T_inc_sensor *inc_s) +{ + +// , .. , = 0. + + if( + (inc_s->use_sensor1 && inc_s->break_sensor1==0 && (inc_s->data.CountOne1 > LEVEL_SWITCH_MICROSEC) && (inc_s->data.CountZero1 > LEVEL_SWITCH_MICROSEC) ) + || (inc_s->use_sensor2 && inc_s->break_sensor2==0 && (inc_s->data.CountOne2 > LEVEL_SWITCH_MICROSEC) && (inc_s->data.CountZero2 > LEVEL_SWITCH_MICROSEC) ) + ) + { + inc_s->pm67regs.write_comand_reg.bit.set_sampling_time = SAMPLING_TIME_MS; + return; + } + +// + if( + (inc_s->use_sensor1 && inc_s->break_sensor1==0 && (inc_s->data.CountOne1 < LEVEL_SWITCH_NANOSEC) && (inc_s->data.CountZero1 < LEVEL_SWITCH_NANOSEC) ) + || (inc_s->use_sensor2 && inc_s->break_sensor2==0 && (inc_s->data.CountOne2 < LEVEL_SWITCH_NANOSEC) && (inc_s->data.CountZero2 < LEVEL_SWITCH_NANOSEC) ) + ) + { + inc_s->pm67regs.write_comand_reg.bit.set_sampling_time = SAMPLING_TIME_NS; + } + +} + + + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// diff --git a/Inu/Src/N12_Xilinx/xp_inc_sensor.h b/Inu/Src/N12_Xilinx/xp_inc_sensor.h new file mode 100644 index 0000000..6c4684d --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_inc_sensor.h @@ -0,0 +1,137 @@ +#ifndef XP_INC_SENS_H +#define XP_INC_SENS_H + +#include "x_basic_types.h" +#include "xp_cds_in.h" +#include "xp_id_plate_info.h" + + + +//, +#define SAMPLING_TIME_NS 1 // 16,666667ns +#define SAMPLING_TIME_MS 0 // 1,666667us + +// , +// 1 . +#define AUTO_CHANGE_SAMPLING_TIME 1 +/* + , + rotation_sensor.read_sensors(&rotation_sensor); + IN + rotation_sensor.in_plane.out.... +*/ + +///////////////////////////////////////////////////////////// +// IN plane +///////////////////////////////////////////////////////////// +// Registers with data for incremental sensor +///////////////////////////////////////////////////////////// +typedef union { + unsigned int all; + struct { + unsigned int filter_sensitivity:12; + unsigned int set_sampling_time:1; //(1)-16,666667ns (0)-1,666667us + unsigned int sampling_time2:1; //(1)-16,666667ns (0)-1,666667us + unsigned int sampling_time1:1; + unsigned int update_registers:1; //0 - updated + }bit; +}T_inc_sensor_comand; + +#define T_INC_COMAND_DEFAULT 0 +//////////////////////////////////////////////////////////// +typedef struct { + unsigned int time_line1; + unsigned int n_impulses_line1; + unsigned int time_line2; + unsigned int n_impulses_line2; + + unsigned int zero_time_line1; + unsigned int one_time_line1; + unsigned int zero_time_line2; + unsigned int one_time_line2; + + T_inc_sensor_comand write_comand_reg; + T_inc_sensor_comand read_comand_reg; + +} T_inc_sensor_regs; + +#define T_INC_SENSOR_REGS_DEFAULTS {0,0,0,0, 0,0,0,0, T_INC_COMAND_DEFAULT, T_INC_COMAND_DEFAULT} + + +//////////////////////////////////////////////// +////// incremental sensors with IN plane +/////////////////////////////////////////////// +typedef struct { + //UInt16 plane_address; + unsigned int count_wait_for_update_registers; + unsigned int error_update; + unsigned int use_sensor1; + unsigned int use_sensor2; + unsigned int break_sensor1; + unsigned int break_sensor2; + unsigned int break_direction; + + + struct { + + unsigned int Time1; // Sensor's survey time in mksec + unsigned int Impulses1; // Quantity of full impulses during survey time + unsigned int CountZero1; // Value of the zero-half-period counter + unsigned int CountOne1; // Value of the one-half-period counter + unsigned int prev_CountZero1; // Value of the prev zero-half-period counter + unsigned int prev_CountOne1; // Value of the prev one-half-period counter + unsigned int countCountZero1; // Value of the zero-half-period counter + unsigned int countCountOne1; // Value of the one-half-period counter + unsigned int counter_freq1; // 1 - 60MHz; 0 - 600KHz + unsigned long TimeCalcFromImpulses1; // Impulses1 Time1 + int direction1; // 1 - direct; 0 - reverse + + unsigned int Time2; // Sensor's survey time in mksec + unsigned int Impulses2; // Quantity of full impulses during survey time + unsigned int CountZero2; // Value of the zero-half-period counter + unsigned int CountOne2; // Value of the one-half-period counter + unsigned int prev_CountZero2; // Value of the prev zero-half-period counter + unsigned int prev_CountOne2; // Value of the prev one-half-period counter + unsigned int countCountZero2; // Value of the zero-half-period counter + unsigned int countCountOne2; // Value of the one-half-period counter + unsigned int counter_freq2; // 1 - 60MHz; 0 - 600KHz + unsigned long TimeCalcFromImpulses2; // Impulses1 Time1 + int direction2; // 1 - direct; 0 - reverse + } data; + + T_inc_sensor_regs pm67regs; + + void (*set)(); // Pointer to calculation function + + void (*update_sensors)(); + void (*read_sensors)(); + void (*read_sensor1)(); + void (*read_sensor2)(); + +} T_inc_sensor; + +#define T_INC_SENSOR_DEFAULT {0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0,0,0,0}, \ + T_INC_SENSOR_REGS_DEFAULTS, \ + inc_sensor_set,\ + update_sensors_data_s, \ + inc_sensor_read, \ + inc_sensor_read1, \ + inc_sensor_read2 \ + } + +////////////////////////////////////////////////////////////////////////////////// +//// +////////////////////////////////////////////////////////////////////////////////// + +//Public functions + +void inc_sensor_set(T_inc_sensor *inc_s); +void inc_sensor_read1(T_inc_sensor *inc_s); +void inc_sensor_read2(T_inc_sensor *inc_s); +void inc_sensor_read(T_inc_sensor *inc_s); +void update_sensors_data_s(T_inc_sensor *inc_s); + + +extern T_inc_sensor inc_sensor; + +#endif //XP_INC_SENS_H diff --git a/Inu/Src/N12_Xilinx/xp_incremental_sensors.c b/Inu/Src/N12_Xilinx/xp_incremental_sensors.c new file mode 100644 index 0000000..45756f0 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_incremental_sensors.c @@ -0,0 +1,235 @@ +#include "xp_project.h" +#include "xp_incremental_sensors.h" + +#include "xp_project.h" + +#pragma DATA_SECTION(incr_sensors,".slow_vars"); +T_Incremental_sensors incr_sensors;// = T_Incremental_sensors_DEFAULT; + + + +//static void read_in_sensor_line1(T_inc_sensor *inc_s); +//static void read_in_sensor_line2(T_inc_sensor *inc_s); + +static void incremental_sensors_read_cmd_pm67(T_Incremental_sensors *inc_s); +static void incremental_sensors_write_cmd_pm67(T_Incremental_sensors *inc_s); + +static void incremental_sensors_tune_sampling_time_pm67(T_Incremental_sensors *inc_s); +static void incremental_sensors_wait_for_registers_updated_pm67(T_Incremental_sensors *inc_s); + +void incremental_sensors_read_data_pm67(T_Incremental_sensors *inc_s); +void incremental_sensors_read_pm67(T_Incremental_sensors *inc_s); + + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void incremental_sensors_write_cmd_pm67(T_Incremental_sensors *inc_s) +{ + WriteMemory(ADR_SENSOR_CMD, inc_s->write_comand_reg_pm67.all); +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void incremental_sensors_wait_for_registers_updated_pm67(T_Incremental_sensors *inc_s) +{ +// int counter_in_while = 0; + + incremental_sensors_read_cmd_pm67(inc_s); + + if (inc_s->read_comand_reg_pm67.bit.update_registers) + { + inc_s->error_alarms_counters.for_pm67.error_update_registers = 0; + } + else + while(inc_s->read_comand_reg_pm67.bit.update_registers) + { + incremental_sensors_read_cmd_pm67(inc_s); + + inc_s->error_alarms_counters.for_pm67.error_update_registers++; + inc_s->error_alarms_stat.for_pm67.error_update_registers++; + + if(inc_s->error_alarms_counters.for_pm67.error_update_registers > inc_s->config.error_alarms_timeouts.for_pm67.error_update_registers) + { + inc_s->error_alarms_status.for_pm67.error_update_registers |= 1; + break; + } + } + +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + +void incremental_sensors_read_cmd_pm67(T_Incremental_sensors *inc_s) +{ + inc_s->read_comand_reg_pm67.all = i_ReadMemory(ADR_SENSOR_CMD); +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void incremental_sensors_tune_sampling_time_pm67(T_Incremental_sensors *inc_s) +{ +// - (one_time_line) +// one_time_line zero_time_line = 50% + +// , .. , = 0. + if((inc_s->config.for_pm67.use_s1 && (inc_s->data_from_pm67.data_from_xilinx.one_time_line1 > LEVEL_SWITCH_TUNE_TIME_PM67_MICROSEC)) + || (inc_s->config.for_pm67.use_s2 && (inc_s->data_from_pm67.data_from_xilinx.one_time_line2 > LEVEL_SWITCH_TUNE_TIME_PM67_MICROSEC))) + { + inc_s->write_comand_reg_pm67.bit.set_sampling_time = SAMPLING_TIME_PM67_MS; + return; + } + +// + if((inc_s->config.for_pm67.use_s1 && (inc_s->data_from_pm67.data_from_xilinx.one_time_line1 < LEVEL_SWITCH_TUNE_TIME_PM67_NANOSEC)) + || (inc_s->config.for_pm67.use_s2 && (inc_s->data_from_pm67.data_from_xilinx.one_time_line2 < LEVEL_SWITCH_TUNE_TIME_PM67_NANOSEC))) + { + inc_s->write_comand_reg_pm67.bit.set_sampling_time = SAMPLING_TIME_PM67_NS; + } + +} + + + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void incremental_sensors_init(T_Incremental_sensors *inc_s) +{ + +/* + if(!inc_s->cds_in->useit) + { + return; + } + + inc_s->cds_in->write.sbus.enabled_channels.all = inc_s->write.sbus.enabled_channels.all; + inc_s->cds_in->write.sbus.first_sensor.all = inc_s->write.sbus.first_sensor_inputs.all; + inc_s->cds_in->write.sbus.second_sensor.all = inc_s->write.sbus.second_sensor_inputs.all; + // inc_s->cds_in->write_sbus(inc_s->cds_in); + write_command_reg(inc_s); +*/ + + incremental_sensors_write_cmd_pm67(inc_s); + +} + + +void incremental_sensors_read_pm67(T_Incremental_sensors *inc_s) +{ + if(inc_s->config.for_pm67.use_s1 || inc_s->config.for_pm67.use_s2) + { + incremental_sensors_wait_for_registers_updated_pm67(inc_s); + } + else + { + return; + } + + incremental_sensors_read_data_pm67(inc_s); + + if (inc_s->config.for_pm67.ModeAutoDiscret != MODE_OFF_SPEED_TUNE_PM67) + incremental_sensors_tune_sampling_time_pm67(inc_s); + +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + +void incremental_sensors_read_data_pm67(T_Incremental_sensors *inc_s) +{ + if (inc_s->read_comand_reg_pm67.bit.update_registers) + { + inc_s->data_from_pm67.data_from_xilinx.time_line1 = i_ReadMemory(ADR_SENSOR_S1_T_PERIOD); + inc_s->data_from_pm67.data_from_xilinx.n_impulses_line1 = i_ReadMemory(ADR_SENSOR_S1_COUNT_IMPULS); + + inc_s->data_from_pm67.data_from_xilinx.zero_time_line1 = i_ReadMemory(ADR_SENSOR_S1_T_PERIOD_LOW_ONE_IMPULS); + inc_s->data_from_pm67.data_from_xilinx.one_time_line1 = i_ReadMemory(ADR_SENSOR_S1_T_PERIOD_HIGH_ONE_IMPULS); + + inc_s->data_from_pm67.data_from_xilinx.time_line2 = i_ReadMemory(ADR_SENSOR_S2_T_PERIOD); + inc_s->data_from_pm67.data_from_xilinx.n_impulses_line2 = i_ReadMemory(ADR_SENSOR_S2_COUNT_IMPULS); + + inc_s->data_from_pm67.data_from_xilinx.zero_time_line2 = i_ReadMemory(ADR_SENSOR_S2_T_PERIOD_LOW_ONE_IMPULS); + inc_s->data_from_pm67.data_from_xilinx.one_time_line2 = i_ReadMemory(ADR_SENSOR_S2_T_PERIOD_HIGH_ONE_IMPULS); + } + + + if (inc_s->config.for_pm67.use_s1) + { + inc_s->data_from_pm67.raw_solo.time_s1 = inc_s->data_from_pm67.data_from_xilinx.one_time_line1 + inc_s->data_from_pm67.data_from_xilinx.zero_time_line1; + + //Counter`s freq is 60 => N/60 = time in mksec + if (inc_s->data_from_pm67.data_from_xilinx.n_impulses_line1>2) + inc_s->data_from_pm67.raw_pulses.TimeCalcS1 = inc_s->data_from_pm67.data_from_xilinx.time_line1*1000/inc_s->data_from_pm67.data_from_xilinx.n_impulses_line1/60; + else + inc_s->data_from_pm67.raw_pulses.TimeCalcS1 = 0; + } + else + { + inc_s->data_from_pm67.raw_solo.time_s1 = 0; + inc_s->data_from_pm67.raw_pulses.TimeCalcS1 = 0; + } + + if (inc_s->config.for_pm67.use_s2) + { + inc_s->data_from_pm67.raw_solo.time_s2 = inc_s->data_from_pm67.data_from_xilinx.one_time_line2 + inc_s->data_from_pm67.data_from_xilinx.zero_time_line2; + + //Counter`s freq is 60 => N/60 = time in mksec + if (inc_s->data_from_pm67.data_from_xilinx.n_impulses_line2>2) + inc_s->data_from_pm67.raw_pulses.TimeCalcS2 = inc_s->data_from_pm67.data_from_xilinx.time_line2*1000/inc_s->data_from_pm67.data_from_xilinx.n_impulses_line2/60; + else + inc_s->data_from_pm67.raw_pulses.TimeCalcS2 = 0; + } + else + { + inc_s->data_from_pm67.raw_solo.time_s2 = 0; + inc_s->data_from_pm67.raw_pulses.TimeCalcS2 = 0; + } + +// inc_s->data.counter_freq1 = inc_s->pm67regs.read_comand_reg.bit.sampling_time1; +// inc_s->data.direction1 = inc_s->read.pbus.direction.bit.sensor1; +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + +void incremental_sensors_update_sensors_data_pm67(T_Incremental_sensors *inc_s) +{ + inc_s->write_comand_reg_pm67.bit.update_registers = 1; + incremental_sensors_write_cmd_pm67(inc_s); +// inc_s->in_plane.write.regs.comand_reg.bit.update_registers = 0; +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// + + +void read_direction_in_plane(T_Incremental_sensors *inc_s) +{ +/* + inc_s->read.pbus.direction.bit.sensor1 = inc_s->cds_in->read.pbus.direction_in.bit.dir0 == 2 ? 1 : + inc_s->cds_in->read.pbus.direction_in.bit.dir0 == 1 ? -1 : + 0; + inc_s->read.pbus.direction.bit.sensor2 = inc_s->cds_in->read.pbus.direction_in.bit.dir1 == 2 ? 1 : + inc_s->cds_in->read.pbus.direction_in.bit.dir1 == 1 ? -1 : + 0; + inc_s->read.pbus.direction.bit.sens_err1 = inc_s->cds_in->read.pbus.direction_in.bit.dir0 == 3; + inc_s->read.pbus.direction.bit.sens_err2 = inc_s->cds_in->read.pbus.direction_in.bit.dir1 == 3; + //Direction changes not often. May be, it`s enough to read it in main cycle. +*/ +} + +//////////////////////////////////////////////////////// +//////////////////////////////////////////////////////// diff --git a/Inu/Src/N12_Xilinx/xp_incremental_sensors.h b/Inu/Src/N12_Xilinx/xp_incremental_sensors.h new file mode 100644 index 0000000..67ce10d --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_incremental_sensors.h @@ -0,0 +1,531 @@ +#ifndef XP_INCREMENTAL_SENSORS_H +#define XP_INCREMENTAL_SENSORS_H + +#include "IQmathLib.h" +#include "x_basic_types.h" +#include "xp_cds_in.h" +#include "xp_id_plate_info.h" + +#define INCREMENTAL_SENSOR_SAMPLING_TIME_PM67_MS 0 +#define INCREMENTAL_SENSOR_SAMPLING_TIME_PM67_NS 1 + +#define LEVEL_SWITCH_TUNE_TIME_PM67_MICROSEC 40000 +#define LEVEL_SWITCH_TUNE_TIME_PM67_NANOSEC 300 + +//, +#define SAMPLING_TIME_PM67_NS 1 // 16,666667ns +#define SAMPLING_TIME_PM67_MS 0 // 1,666667us + +#define MODE_OFF_SPEED_TUNE_PM67 0 +#define MODE_AUTO_SPEED_TUNE_PM67 1 +#define MODE_LOW_SPEED_TUNE_PM67 2 +#define MODE_FAST_SPEED_TUNE_PM67 3 + + +///////////////////////////////////////////////////////////// +// IN plane +///////////////////////////////////////////////////////////// +// Registers with data for incremental sensor +///////////////////////////////////////////////////////////// +typedef union { + unsigned int all; + struct { + unsigned int filter_sensitivity:12; + unsigned int set_sampling_time:1; //(1)-16,666667ns (0)-1,666667us + unsigned int sampling_time2:1; //(1)-16,666667ns (0)-1,666667us + unsigned int sampling_time1:1; + unsigned int update_registers:1; //0 - updated + }bit; +}T_inc_sensor_comand_pm67; + +#define T_INC_COMAND_DEFAULT 0 +//////////////////////////////////////////////////////////// +typedef struct { + unsigned int time_line1; + unsigned int n_impulses_line1; + unsigned int time_line2; + unsigned int n_impulses_line2; + + unsigned int zero_time_line1; + unsigned int one_time_line1; + unsigned int zero_time_line2; + unsigned int one_time_line2; + +} T_inc_sensor_data_pm67; + +#define T_INC_SENSOR_DATA_PM67 {0,0,0,0,0,0,0,0} +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// + + + + +typedef struct +{ +//////////////////////// +//////////////////////// +// data_from_pm67 // +//////////////////////// + struct { + + struct { + _iq time_s1; + _iq time_s2; + } raw_solo; + + struct { + _iq before_time_s1; + _iq before_time_s2; + + _iq time_s1; + _iq time_s2; + } filter_solo; + + struct { + _iq TimeCalcS1; + _iq TimeCalcS2; + + } raw_pulses; + + struct { + _iq before_ch0_s1; + _iq before_ch1_s1; + + _iq before_ch0_s2; + _iq before_ch1_s2; + + _iq ch0_s1; + _iq ch1_s1; + + _iq ch0_s2; + _iq ch1_s2; + + } filter_pulses; + + +// _iq solo_time_s1; +// _iq solo_time_s2; + +// _iq pulses_time_s1; +// _iq pulses_time_s2; + + T_inc_sensor_data_pm67 data_from_xilinx; + + } data_from_pm67; + +//////////////////////// +//////////////////////// +//////////////////////// +// data_from_in // +//////////////////////// + + struct { + + struct { + _iq speed_s1; + _iq speed_90_s1; + + _iq speed_s2; + _iq speed_90_s2; + + _iq zero_point_s1; + _iq zero_point_rising_s1; + _iq zero_point_falling_s1; + + _iq zero_point_s2; + _iq zero_point_rising_s2; + _iq zero_point_falling_s2; + + unsigned int dir_s1; + unsigned int dir_s2; + + _iq angle_f_s1; + _iq angle_r_s1; + + _iq angle_f_s2; + _iq angle_r_s2; + + int status_s1; + int status_s2; + + } raw; + + struct { + + _iq speed_s1; + _iq speed_90_s1; + + _iq speed_s2; + _iq speed_90_s2; + + _iq zero_point_s1; + _iq zero_point_rising_s1; + _iq zero_point_falling_s1; + + _iq zero_point_s2; + _iq zero_point_rising_s2; + _iq zero_point_falling_s2; + + + unsigned int dir_s1; + unsigned int dir_s2; + + } filter; + + +//////////////////////// + + } data_from_in; + +//////////////////////// +//////////////////////// +/// config // +//////////////////////// + struct { + + struct { + _iq KoefNormMS; + _iq KoefNormNS; + _iq koefW; + long long KoefNormImpulses; + unsigned int use; + unsigned int use_s1; + unsigned int use_s2; + unsigned int ModeAutoDiscret;// 1 -auto, 2-low speed, 3- fast speed + unsigned int time_level_discret_1to0; + unsigned int time_level_discret_0to1; + + } for_pm67; +//////////////////////// + + struct { + + unsigned int use_it; + unsigned int use_sp6; + struct { + unsigned int ModeAutoDiscret;// 1 -auto, 2-low speed, 3- fast speed + unsigned int use_s1; + unsigned int use_s2; + unsigned int decoder_zero_level; + unsigned int decoder_max_level; + unsigned int max_count_overfull_discret; + unsigned int max_count_zero_discret; + unsigned int time_level_discret_1to0; + unsigned int time_level_discret_0to1; + long long KoefNorm_discret0; + long long KoefNorm_discret1; + } incremental_sensors; + + struct { + long long KoefNorm_angle; + unsigned int use_z1; + unsigned int use_z2; + } zero_sensors; + } for_in; + +//////////////////////// + + struct { + unsigned int count_impulses; // one oborots + } inc_sensor; + +//////////////////////// + + struct { + + struct { + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int error_s1_s2; + unsigned int error_update_registers; + } for_pm67; + + struct { + + struct { + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int alarm_dir1; + unsigned int alarm_dir2; + unsigned int error_s1_s2; + unsigned int error_dir1_dir2; + } incremental_sensors; + + struct { + unsigned int alarm_z1; + unsigned int alarm_z2; + unsigned int error_z1_z2; + } zero_sensors; + } for_in; + + } error_alarms_timeouts; + +//////////////////////// + + struct { + + struct { + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int error_s1_s2; + } for_pm67; + + struct { + + struct { + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int alarm_dir1; + unsigned int alarm_dir2; + unsigned int error_s1_s2; + unsigned int error_dir1_dir2; + } incremental_sensors; + + struct { + unsigned int alarm_z1; + unsigned int alarm_z2; + unsigned int error_z1_z2; + } zero_sensors; + } for_in; + + } error_alarms_on_off; + + } config; +//////////////////////// +// error_alarms_stat +//////////////////////// + + struct { + + struct { + unsigned int error_update_registers; + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int error_s1_s2; + } for_pm67; + + struct { + + struct { + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int alarm_dir1; + unsigned int alarm_dir2; + unsigned int error_s1_s2; + unsigned int error_dir1_dir2; + } incremental_sensors; + + struct { + unsigned int alarm_z1; + unsigned int alarm_z2; + unsigned int error_z1_z2; + } zero_sensors; + } for_in; + + } error_alarms_stat; +//////////////////////// +// error_alarms_status +//////////////////////// + struct { + + struct { + unsigned int error_update_registers; + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int error_s1_s2; + } for_pm67; + + struct { + + struct { + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int alarm_dir1; + unsigned int alarm_dir2; + unsigned int error_s1_s2; + unsigned int error_dir1_dir2; + } incremental_sensors; + + struct { + unsigned int alarm_z1; + unsigned int alarm_z2; + unsigned int error_z1_z2; + } zero_sensors; + } for_in; + + } error_alarms_status; +//////////////////////// +//////////////////////// +// error_alarms_counters +//////////////////////// + struct { + + struct { + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int error_s1_s2; + unsigned int error_update_registers; + } for_pm67; + + struct { + + struct { + unsigned int alarm_s1; + unsigned int alarm_s2; + unsigned int alarm_dir1; + unsigned int alarm_dir2; + unsigned int error_s1_s2; + unsigned int error_dir1_dir2; + } incremental_sensors; + + struct { + unsigned int alarm_z1; + unsigned int alarm_z2; + unsigned int error_z1_z2; + } zero_sensors; + } for_in; + + } error_alarms_counters; + +//////////////////////// + T_inc_sensor_comand_pm67 write_comand_reg_pm67; + T_inc_sensor_comand_pm67 read_comand_reg_pm67; + +//////////////////////// + +//////////////////////// +//////////////////////// + +// int RotorDirection1; +// int RotorDirection2; + + void (*init)(); // Pointer to calculation function + +// void (*request_data_from_sensors_pm67)(); + void (*read_sensors_pm67)(); + void (*read_sensors_in)(); + void (*update_regs_sensors_pm67)(); +// void (*update_regs_sensors_in)(); + +} T_Incremental_sensors; + +#define T_Incremental_sensors_DEFAULT {} + +void incremental_sensors_init(T_Incremental_sensors *inc_s); +void incremental_sensors_read_pm67(T_Incremental_sensors *inc_s); +void incremental_sensors_update_sensors_data_pm67(T_Incremental_sensors *inc_s); + +/* + + + + + + +// , +// 1 . +#define AUTO_CHANGE_SAMPLING_TIME 1 +// +// , +// rotation_sensor.read_sensors(&rotation_sensor); +// IN +// rotation_sensor.in_plane.out.... +// + +///////////////////////////////////////////////////////////// +// IN plane +///////////////////////////////////////////////////////////// +// Registers with data for incremental sensor +///////////////////////////////////////////////////////////// +typedef union { + unsigned int all; + struct { + unsigned int filter_sensitivity:12; + unsigned int set_sampling_time:1; //(1)-16,666667ns (0)-1,666667us + unsigned int sampling_time2:1; //(1)-16,666667ns (0)-1,666667us + unsigned int sampling_time1:1; + unsigned int update_registers:1; //0 - updated + }bit; +}T_inc_sensor_comand; + +#define T_INC_COMAND_DEFAULT 0 +//////////////////////////////////////////////////////////// +typedef struct { + unsigned int time_line1; + unsigned int n_impulses_line1; + unsigned int time_line2; + unsigned int n_impulses_line2; + + unsigned int zero_time_line1; + unsigned int one_time_line1; + unsigned int zero_time_line2; + unsigned int one_time_line2; + + T_inc_sensor_comand write_comand_reg; + T_inc_sensor_comand read_comand_reg; + +} T_inc_sensor_regs; + +#define T_INC_SENSOR_REGS_DEFAULTS {0,0,0,0, 0,0,0,0, T_INC_COMAND_DEFAULT, T_INC_COMAND_DEFAULT} + + +//////////////////////////////////////////////// +////// incremental sensors with IN plane +/////////////////////////////////////////////// +typedef struct { + //UInt16 plane_address; + unsigned int count_wait_for_update_registers; + unsigned int error_update; + unsigned int use_sensor1; + unsigned int use_sensor2; + + struct { + + unsigned int Time1; // Sensor's survey time in mksec + unsigned int Impulses1; // Quantity of full impulses during survey time + unsigned int CountZero1; // Value of the zero-half-period counter + unsigned int CountOne1; // Value of the one-half-period counter + unsigned int counter_freq1; // 1 - 60MHz; 0 - 600KHz + unsigned long TimeCalcFromImpulses1; // Impulses1 Time1 + int direction1; // 1 - direct; 0 - reverse + + unsigned int Time2; // Sensor's survey time in mksec + unsigned int Impulses2; // Quantity of full impulses during survey time + unsigned int CountZero2; // Value of the zero-half-period counter + unsigned int CountOne2; // Value of the one-half-period counter + unsigned int counter_freq2; // 1 - 60MHz; 0 - 600KHz + unsigned long TimeCalcFromImpulses2; // Impulses1 Time1 + int direction2; // 1 - direct; 0 - reverse + } data; + + T_inc_sensor_regs pm67regs; + + void (*set)(); // Pointer to calculation function + + void (*update_sensors)(); + void (*read_sensors)(); + void (*read_sensor1)(); + void (*read_sensor2)(); + +} T_inc_sensor; + +#define T_INC_SENSOR_DEFAULT {0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, T_INC_SENSOR_REGS_DEFAULTS, inc_sensor_set, update_sensors_data, inc_sensor_read, inc_sensor_read1, inc_sensor_read2} + +////////////////////////////////////////////////////////////////////////////////// +//// +////////////////////////////////////////////////////////////////////////////////// + +//Public functions + +void inc_sensor_set(T_inc_sensor *inc_s); +void inc_sensor_read1(T_inc_sensor *inc_s); +void inc_sensor_read2(T_inc_sensor *inc_s); +void inc_sensor_read(T_inc_sensor *inc_s); +void update_sensors_data(T_inc_sensor *inc_s); + + +extern T_inc_sensor inc_sensor; +*/ + + +#endif //XP_INCREMENTAL_SENSORS_H diff --git a/Inu/Src/N12_Xilinx/xp_optlink_tms2tms.c b/Inu/Src/N12_Xilinx/xp_optlink_tms2tms.c new file mode 100644 index 0000000..c1b7769 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_optlink_tms2tms.c @@ -0,0 +1,98 @@ + +#include "xp_optlink_tms2tms.h" + +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "Spartan2E_Functions.h" +#include "xp_controller.h" + + + +X_OPTLINK_TMS2TMS x_optlink_tms2tms_project = X_OPTLINK_TMS2TMS_DEFAULTS; + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// + + +void x_optlink_tms2tms_read_data(X_OPTLINK_TMS2TMS *v) +{ + volatile unsigned int d_wr; + +// v->data_receiver[0] = ReadMemory(ADR_FIRST_FREE + v->adr_table_read); +// d_wr = v->; +// WriteMemory(ADR_PARALLEL_BUS_CMD, d_wr); + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + + + +void x_optlink_tms2tms_write_data(X_OPTLINK_TMS2TMS *v) +{ + volatile unsigned int d_wr; + + +// d_wr = v->; +// WriteMemory(ADR_PARALLEL_BUS_CMD, d_wr); + +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + + + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +void x_optlink_tms2tms_init(X_OPTLINK_TMS2TMS *v) +{ + if (v->flags.bit.init) + return; +/* + v->setup.size_table = 0;//-1; + v->setup.tms_adr_data_start = ADR_FIRST_FREE; + v->setup.tms_adr_data_finish = ADR_LAST_FREE; + v->setup.setup_error_count_read = MAX_WAIT_ERROR_PARALLEL_BUS; + + v->flags.all = 0; + + v->slave_addr = 0; + v->reg_addr = 0; + v->error_count_start = 0; + v->count_read = 0; + + v->stop(v); + + v->flags.bit.init = 1; +*/ +} +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////// +/* +#pragma CODE_SECTION(x_parallel_bus_read_one_data,".fast_run"); +void x_parallel_bus_read_one_data(X_OPTLINK_TMS2TMS *v) +{ +// read data from parallel bus +// v->data_table_read = ReadMemory(ADR_FIRST_FREE + v->adr_table_read); +} +*/ +//////////////////////////////////////////////////////////////// + + + + diff --git a/Inu/Src/N12_Xilinx/xp_optlink_tms2tms.h b/Inu/Src/N12_Xilinx/xp_optlink_tms2tms.h new file mode 100644 index 0000000..227d3b6 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_optlink_tms2tms.h @@ -0,0 +1,110 @@ +#ifndef _X_OPTLINK_TMS2TMS_H +#define _X_OPTLINK_TMS2TMS_H + +#define MAX_WAIT_ERROR_X_OPTLINK_TMS2TMS 1 // . - + + +typedef union { + unsigned int all; + struct { + unsigned int id:8; + unsigned int count_receiver_error:4; + unsigned int trans_busy:1; // + unsigned int trans_error:1; // + unsigned int receiver_busy :1; // + unsigned int receiver_error:1; // + } bit; +} X_OPTLINK_TMS2TMS_status; + + + + +typedef union { + unsigned int all; + struct { + unsigned int started:1; + unsigned int error:1; + unsigned int cmd_start:1; + unsigned int count_error:4; + unsigned int slave_addr_error:4; + unsigned int init:1; + unsigned int was_started:1; + unsigned int rezerv:3; + + } bit; +} X_OPTLINK_TMS2TMS_flags; + + + + +typedef struct { + unsigned int setup_error_count_read; // - +} X_OPTLINK_TMS2TMS_Setup; + + + +typedef struct { X_OPTLINK_TMS2TMS_flags flags; // + X_OPTLINK_TMS2TMS_Setup setup; // + + X_OPTLINK_TMS2TMS_status status1; // 1 + X_OPTLINK_TMS2TMS_status status2; // 2 + + unsigned int data_receiver[4]; // - 0..3 + unsigned int data_send[4]; // - 0..3 + + unsigned int error_count_send; // - + unsigned int error_count_receiver; // - + unsigned int count_receiver; // - + unsigned int count_send; // - + +// unsigned int error_count_write; // - +// unsigned int error_count_hold; // - + + void (*init)(); // Pointer to init function + void (*read_data)(); // Pointer to init function + void (*write_data)(); // Pointer to init function + }X_OPTLINK_TMS2TMS; + + + +/* +// +#define TIME_OUT_SERIAL_BUS 10000 // max 65535 + + +#define CMD_SERIAL_BUS_READ 0x0000 +#define CMD_SERIAL_BUS_WRITE 0x8000 + +*/ + + +typedef X_OPTLINK_TMS2TMS *X_OPTLINK_TMS2TMS_handle; + +#define X_OPTLINK_TMS2TMS_DEFAULTS { 0, \ + 0,0,\ + MAX_WAIT_ERROR_X_OPTLINK_TMS2TMS, \ + {0,0,0,0},\ + {0,0,0,0},\ + 0, \ + 0, \ + 0, \ + 0, \ + (void (*)(Uint32))x_optlink_tms2tms_init,\ + (void (*)(Uint32))x_optlink_tms2tms_read_data,\ + (void (*)(Uint32))x_optlink_tms2tms_write_data\ + } + + +void x_optlink_tms2tms_init(X_OPTLINK_TMS2TMS_handle); + +void x_optlink_tms2tms_read_data(X_OPTLINK_TMS2TMS_handle); + +void x_optlink_tms2tms_write_data(X_OPTLINK_TMS2TMS_handle); + + +extern X_OPTLINK_TMS2TMS x_optlink_tms2tms_project; + + + +#endif // end _X_OPTLINK_TMS2TMS_H + diff --git a/Inu/Src/N12_Xilinx/xp_plane_adr.h b/Inu/Src/N12_Xilinx/xp_plane_adr.h new file mode 100644 index 0000000..04b6e96 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_plane_adr.h @@ -0,0 +1,175 @@ +#ifndef XP_PLANE_ADR_H +#define XP_PLANE_ADR_H +#include +/*------------------------------------------------------------------------------ + Plane counter +------------------------------------------------------------------------------*/ +///////////////////////////////////////////////////////////////////// +// , +///////////////////////////////////////////////////////////////////// + +#if (C_PROJECT_TYPE==PROJECT_10510) + +// + +// +// project. +// .. , . +// , +// +#define MAX_C_CDS_TK_NUMBER 6 // max 8 +#define MAX_C_CDS_IN_NUMBER 3 // max 3 +#define MAX_C_CDS_OUT_NUMBER 3 // max 3 +#define MAX_C_ADC_NUMBER 3 // max 3 +#define MAX_C_HWP_NUMBER 3 // max 3 +#define MAX_C_CDS_RS_NUMBER 1 // max 1 + +/*------------------------------------------------------------------------------ + Plane address +------------------------------------------------------------------------------*/ +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define C_controller_address 1 +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define C_cds_in0_address 2 +#define C_cds_in1_address 3 +#define C_cds_in2_address 4 +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define C_cds_tk0_address 6 +#define C_cds_tk1_address 7 +#define C_cds_tk2_address 8 +#define C_cds_tk3_address 9 +#define C_cds_tk4_address 10 +#define C_cds_tk5_address 11 +//#define C_cds_tk6_address 19 +//#define C_cds_tk7_address 20 +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define C_cds_out0_address 5 +#define C_cds_out1_address 21 +#define C_cds_out2_address 22 +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define C_adc0_address 13 +#define C_adc1_address 15 +#define C_adc2_address 12 +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define C_cds_rs0_address 14 +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define C_hwp0_address 16 +#define C_hwp1_address 17 +#define C_hwp2_address 18 +#else +///////////////////////////////////////// +// +//////////////////////////////////////// + +// + +// +// project. +// .. , . +// , +// +#define MAX_C_CDS_TK_NUMBER 4 // max 8 +#define MAX_C_CDS_IN_NUMBER 3 // max 3 +#define MAX_C_CDS_OUT_NUMBER 3 // max 3 +#define MAX_C_ADC_NUMBER 2 // max 3 +#define MAX_C_HWP_NUMBER 2 // max 3 +#define MAX_C_CDS_RS_NUMBER 1 // max 1 + +/*------------------------------------------------------------------------------ + Plane number address +------------------------------------------------------------------------------*/ +#define C_controller_address 1 + +#define C_cds_in0_address 2 +#define C_cds_in1_address 3 +#define C_cds_in2_address 4 + +#define C_cds_tk0_address 5 +#define C_cds_tk1_address 6 +#define C_cds_tk2_address 9 +#define C_cds_tk3_address 10 + +//#define C_cds_tk4_address 255 +//#define C_cds_tk5_address 255 +//#define C_cds_tk6_address 255 +//#define C_cds_tk7_address 255 + +#define C_cds_out0_address 11 +#define C_cds_out1_address 12 +#define C_cds_out2_address 13 + +#define C_adc0_address 7 +#define C_adc1_address 8 +//#define C_adc2_address 255 + +#define C_cds_rs0_address 14 + +#define C_hwp0_address 16 +#define C_hwp1_address 17 +//#define C_hwp2_address 255 + +#endif + + + +/////////////////////////////////////////////////////// +// +// MAX_C_CDS_TK_NUMBER (.) +// +/////////////////////////////////////////////////////// + + + + + +#if (MAX_COUNT_PLATES_CDS_TK>MAX_C_CDS_TK_NUMBER) +#define C_cds_tk_number MAX_COUNT_PLATES_CDS_TK // max 8 +#else +#define C_cds_tk_number MAX_COUNT_PLATES_CDS_TK // max 8 +#endif + + +#if (MAX_COUNT_PLATES_ADC>MAX_C_ADC_NUMBER) +#define C_adc_number MAX_C_ADC_NUMBER // max 3 +#else +#define C_adc_number MAX_COUNT_PLATES_ADC // max 3 +#endif + +#if (MAX_COUNT_PLATES_HWP>=MAX_C_HWP_NUMBER) +#define C_hwp_number MAX_C_HWP_NUMBER // max 3 +#else +#define C_hwp_number MAX_COUNT_PLATES_HWP // max 3 +#endif + + +#if (MAX_COUNT_PLATES_OUT>MAX_C_CDS_OUT_NUMBER) +#define C_cds_out_number MAX_C_CDS_OUT_NUMBER // max 3 +#else +#define C_cds_out_number MAX_COUNT_PLATES_OUT // max 3 +#endif + + +#if (MAX_COUNT_PLATES_IN>MAX_C_CDS_IN_NUMBER) +#define C_cds_in_number MAX_C_CDS_IN_NUMBER // max 3 +#else +#define C_cds_in_number MAX_COUNT_PLATES_IN // max 3 +#endif + + +#if (MAX_COUNT_PLATES_CDS_RS>MAX_C_CDS_RS_NUMBER) +#define C_cds_rs_number MAX_COUNT_PLATES_CDS_RS // max 1 +#else +#define C_cds_rs_number MAX_COUNT_PLATES_CDS_RS // max 1 +#endif + + + +//#define C_cds_in_number MAX_C_CDS_IN_NUMBER // max 3 +//#define C_cds_out_number MAX_C_CDS_OUT_NUMBER // max 3 +//#define C_cds_rs_number MAX_C_CDS_RS_NUMBER // max 1 + + +#endif // end XP_PLANE_ADR_H + + + diff --git a/Inu/Src/N12_Xilinx/xp_project.c b/Inu/Src/N12_Xilinx/xp_project.c new file mode 100644 index 0000000..b9be18e --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_project.c @@ -0,0 +1,1986 @@ + +#include "xp_project.h" + +#include "x_serial_bus.h" +#include "xp_controller.h" + + +#pragma DATA_SECTION(project,".fast_vars"); +//#pragma DATA_SECTION(project,".slow_vars"); +T_project project = PROJECT_DEFAULTS; + + +void project_enable_all_interrupts(void) +{ + + + KickDog(); + EDIS; + EnableInterrupts(); + ERTM;// Enable Global realtime interrupt DBGM + KickDog(); +} + +void project_disable_all_interrupts(void) +{ +// KickDog(); + DINT; +// DRTM; +// DisableInterrupts(); + +} + + + +////////////////////////////////////////////////////////////////////// +// +////////////////////////////////////////////////////////////////////// +#define get_status_err_plates(p) ((p.local_status & ( local_status_Error)) != 0) +void project_update_all_err_status_plates(void) +{ + +#if(C_cds_tk_number>=1) + project.all_status_plates.tk0 = project.cds_tk[0].status; + project.all_err_plates.errors_tk.bit.tk0 = get_status_err_plates(project.cds_tk[0]);// ((project.cds_tk[0].status & ( component_Error | component_ErrorSBus)) != 0) ;// (project.cds_tk[0].status == component_Error); +#endif + +#if(C_cds_tk_number>=2) + project.all_status_plates.tk1 = project.cds_tk[1].status; + project.all_err_plates.errors_tk.bit.tk1 = get_status_err_plates(project.cds_tk[1]);// == component_Error); +#endif + +#if(C_cds_tk_number>=3) + project.all_status_plates.tk2 = project.cds_tk[2].status; + project.all_err_plates.errors_tk.bit.tk2 = get_status_err_plates(project.cds_tk[2]);// == component_Error); +#endif + +#if(C_cds_tk_number>=4) + project.all_status_plates.tk3 = project.cds_tk[3].status; + project.all_err_plates.errors_tk.bit.tk3 = get_status_err_plates(project.cds_tk[3]);// == component_Error); +#endif + +#if(C_cds_tk_number>=5) + project.all_status_plates.tk4 = project.cds_tk[3].status; + project.all_err_plates.errors_tk.bit.tk4 = get_status_err_plates(project.cds_tk[4]);// == component_Error); +#endif +#if(C_cds_tk_number>=6) + project.all_status_plates.tk5 = project.cds_tk[3].status; + project.all_err_plates.errors_tk.bit.tk5 = get_status_err_plates(project.cds_tk[5]);// == component_Error); +#endif +#if(C_cds_tk_number>=7) + project.all_status_plates.tk6 = project.cds_tk[3].status; + project.all_err_plates.errors_tk.bit.tk6 = get_status_err_plates(project.cds_tk[6]);// == component_Error); +#endif +#if(C_cds_tk_number>=8) + project.all_status_plates.tk7 = project.cds_tk[3].status; + project.all_err_plates.errors_tk.bit.tk7 = get_status_err_plates(project.cds_tk[7]);// == component_Error); +#endif + + +#if(C_cds_out_number>=1) + project.all_status_plates.out0 = project.cds_out[0].status; + project.all_err_plates.errors.bit.out0 = get_status_err_plates(project.cds_out[0]);// == component_Error); +#endif + +#if(C_cds_out_number>=2) + project.all_status_plates.out1 = project.cds_out[1].status; + project.all_err_plates.errors.bit.out1 = get_status_err_plates(project.cds_out[1]);// == component_Error); +#endif + +#if(C_cds_out_number>=3) + project.all_status_plates.out2 = project.cds_out[2].status; + project.all_err_plates.errors.bit.out2 = get_status_err_plates(project.cds_out[2]);// == component_Error); +#endif + + + +#if(C_cds_in_number>=1) + project.all_status_plates.in0 = project.cds_in[0].status; + project.all_err_plates.errors.bit.in0 = get_status_err_plates(project.cds_in[0]);// == component_Error); +#endif + +#if(C_cds_in_number>=2) + project.all_status_plates.in1 = project.cds_in[1].status; + project.all_err_plates.errors.bit.in1 = get_status_err_plates(project.cds_in[1]);// == component_Error); +#endif + +#if(C_cds_in_number>=3) + project.all_status_plates.in2 = project.cds_in[2].status; + project.all_err_plates.errors.bit.in2 = get_status_err_plates(project.cds_in[2]);// == component_Error); +#endif + + +#if(C_adc_number>=1) + project.all_status_plates.adc0 = project.adc[0].status; + project.all_err_plates.errors.bit.adc0 = get_status_err_plates(project.adc[0]);// == component_Error); +#endif +#if(C_adc_number>=2) + project.all_status_plates.adc1 = project.adc[1].status; + project.all_err_plates.errors.bit.adc1 = get_status_err_plates(project.adc[1]);// == component_Error); +#endif +#if(C_adc_number>=3) + project.all_status_plates.adc2 = project.adc[2].status; + project.all_err_plates.errors.bit.adc2 = get_status_err_plates(project.adc[2]);// == component_Error); +#endif + + +#if(C_hwp_number>=1) + project.all_status_plates.hwp0 = project.hwp[0].status; + project.all_err_plates.errors.bit.hwp0 = get_status_err_plates(project.hwp[0]);// == component_Error); +#endif +#if(C_hwp_number>=2) + project.all_status_plates.hwp1 = project.hwp[1].status; + project.all_err_plates.errors.bit.hwp1 = get_status_err_plates(project.hwp[1]);// == component_Error); +#endif +#if(C_hwp_number>=3) + project.all_status_plates.hwp2 = project.hwp[2].status; + project.all_err_plates.errors.bit.hwp2 = get_status_err_plates(project.hwp[2]);// == component_Error); +#endif + +#if(C_cds_rs_number>=1) + project.all_status_plates.rs0 = project.cds_rs[0].status; + project.all_err_plates.errors.bit.rs0 = get_status_err_plates(project.cds_rs[0]);// == component_Error); +#endif + +} + + +void project_all_test_hwp(void) +{ + + if (project.controller.status != component_Ready) + return; + + project.write_all_hwp(); + +#if(C_hwp_number>=1) + project.hwp[0].internal_test(&project.hwp[0]); +#endif +#if(C_hwp_number>=2) + project.hwp[1].internal_test(&project.hwp[1]); +#endif +#if(C_hwp_number>=3) + project.hwp[2].internal_test(&project.hwp[2]); +#endif + + +} + + +//////////////////////////////////////////////////////////////// +// . HWP +//////////////////////////////////////////////////////////////// +void project_load_cfg_to_plates(void) +{ + + if (project.controller.status != component_Ready) + return; + + project.write_all_hwp(); + project.write_all_sbus(); + +} + + +///////////////////////////////////////////////////// +///////////////////////////////////////////////////// +///////////////////////////////////////////////////// +///////////////////////////////////////////////////// + + + + +void project_clear(void) +{ +// UInt16 i; +// for(i=0;i=1) + project.adc[0].plane_address = C_adc0_address; +#endif +#if(C_adc_number>=2) + project.adc[1].plane_address = C_adc1_address; +#endif +#if(C_adc_number>=3) + project.adc[2].plane_address = C_adc2_address; +#endif + +#if(C_cds_in_number>=1) + project.cds_in[0].plane_address = C_cds_in0_address; +#endif +#if(C_cds_in_number>=2) + project.cds_in[1].plane_address = C_cds_in1_address; +#endif +#if(C_cds_in_number>=3) + project.cds_in[2].plane_address = C_cds_in2_address; +#endif + +#if(C_cds_out_number>=1) + project.cds_out[0].plane_address = C_cds_out0_address; +#endif +#if(C_cds_out_number>=2) + project.cds_out[1].plane_address = C_cds_out1_address; +#endif +#if(C_cds_out_number>=3) + project.cds_out[2].plane_address = C_cds_out2_address; +#endif + + + +#if(C_cds_tk_number>=1) +#if(C_cds_tk0_address<1) +#error " C_cds_tk0_address xp_plane_adr.h" +#endif + project.cds_tk[0].plane_address = C_cds_tk0_address; +#endif +#if(C_cds_tk_number>=2) +#if(C_cds_tk1_address<1) +#error " C_cds_tk1_address xp_plane_adr.h" +#endif + project.cds_tk[1].plane_address = C_cds_tk1_address; +#endif +#if(C_cds_tk_number>=3) +#if(C_cds_tk2_address<1) +#error " C_cds_tk2_address xp_plane_adr.h" +#endif + project.cds_tk[2].plane_address = C_cds_tk2_address; +#endif +#if(C_cds_tk_number>=4) +#if(C_cds_tk3_address<1) +#error " C_cds_tk3_address xp_plane_adr.h" +#endif + project.cds_tk[3].plane_address = C_cds_tk3_address; +#endif +#if(C_cds_tk_number>=5) +#if(C_cds_tk4_address<1) +#error " C_cds_tk4_address xp_plane_adr.h" +#endif + project.cds_tk[4].plane_address = C_cds_tk4_address; +#endif +#if(C_cds_tk_number>=6) +#if(C_cds_tk5_address<1) +#error " C_cds_tk5_address xp_plane_adr.h" +#endif + project.cds_tk[5].plane_address = C_cds_tk5_address; +#endif +#if(C_cds_tk_number>=7) +#if(C_cds_tk6_address<1) +#error " C_cds_tk6_address xp_plane_adr.h" +#endif + project.cds_tk[6].plane_address = C_cds_tk6_address; +#endif +#if(C_cds_tk_number>=8) +#if(C_cds_tk7_address<1) +#error " C_cds_tk7_address xp_plane_adr.h" +#endif + project.cds_tk[7].plane_address = C_cds_tk7_address; +#endif + + + + + +#if(C_cds_rs_number>=1) + project.cds_rs[0].plane_address = C_cds_rs0_address; +#endif + +#if(C_hwp_number>=1) + project.hwp[0].plane_address = C_hwp0_address; + project.hwp[0].init(&project.hwp[0]); +#endif +#if(C_hwp_number>=2) + project.hwp[1].plane_address = C_hwp1_address; + project.hwp[1].init(&project.hwp[1]); +#endif +#if(C_hwp_number>=3) + project.hwp[2].plane_address = C_hwp2_address; + project.hwp[2].init(&project.hwp[2]); +#endif + + + if (project.controller.status == component_Ready) + project.controller.build = i_ReadMemory(ADR_CONTROLLER_BUILD); + else + project.controller.build = 0xffff; + + + + project.inited = 1; // ! + +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +// . +/////////////////////////////////////////////////////////// +void project_run_init_all_plates(void) +{ + if (project.controller.status == component_Ready) + { + + #if(C_adc_number>=1) + if (project.adc[0].status & (component_Started | component_Ready | component_Error )) + project.adc[0].init(&project.adc[0]); + #endif + #if(C_adc_number>=2) + if (project.adc[1].status & (component_Started | component_Ready | component_Error )) + project.adc[1].init(&project.adc[1]); + #endif + #if(C_adc_number>=3) + if (project.adc[2].status & (component_Started | component_Ready | component_Error )) + project.adc[2].init(&project.adc[2]); + #endif + + #if(C_cds_tk_number>=1) + if (project.cds_tk[0].status & (component_Started | component_Ready | component_Error )) + project.cds_tk[0].init(&project.cds_tk[0]); + #endif + #if(C_cds_tk_number>=2) + if (project.cds_tk[1].status & (component_Started | component_Ready | component_Error )) + project.cds_tk[1].init(&project.cds_tk[1]); + #endif + #if(C_cds_tk_number>=3) + if (project.cds_tk[2].status & (component_Started | component_Ready | component_Error )) + project.cds_tk[2].init(&project.cds_tk[2]); + #endif + #if(C_cds_tk_number>=4) + if (project.cds_tk[3].status & (component_Started | component_Ready | component_Error )) + project.cds_tk[3].init(&project.cds_tk[3]); + #endif + #if(C_cds_tk_number>=5) + if (project.cds_tk[4].status & (component_Started | component_Ready | component_Error )) + project.cds_tk[4].init(&project.cds_tk[4]); + #endif + #if(C_cds_tk_number>=6) + if (project.cds_tk[5].status & (component_Started | component_Ready | component_Error )) + project.cds_tk[5].init(&project.cds_tk[5]); + #endif + #if(C_cds_tk_number>=7) + if (project.cds_tk[6].status & (component_Started | component_Ready | component_Error )) + project.cds_tk[6].init(&project.cds_tk[6]); + #endif + #if(C_cds_tk_number>=8) + if (project.cds_tk[7].status & (component_Started | component_Ready | component_Error )) + project.cds_tk[7].init(&project.cds_tk[7]); + #endif + +#if(C_cds_in_number>=1) + if (project.cds_in[0].status & (component_Started | component_Ready | component_Error )) + project.cds_in[0].init(&project.cds_in[0]); +#endif +#if(C_cds_in_number>=2) + if (project.cds_in[1].status & (component_Started | component_Ready | component_Error )) + project.cds_in[1].init(&project.cds_in[1]); +#endif +#if(C_cds_in_number>=3) + if (project.cds_in[2].status & (component_Started | component_Ready | component_Error )) + project.cds_in[2].init(&project.cds_in[2]); +#endif + +#if(C_cds_out_number>=1) + if (project.cds_out[0].status & (component_Started | component_Ready | component_Error )) + project.cds_out[0].init(&project.cds_out[0]); +#endif +#if(C_cds_out_number>=2) + if (project.cds_out[1].status & (component_Started | component_Ready | component_Error )) + project.cds_out[1].init(&project.cds_out[1]); +#endif +#if(C_cds_out_number>=3) + if (project.cds_out[2].status & (component_Started | component_Ready | component_Error )) + project.cds_out[2].init(&project.cds_out[2]); +#endif + +#if(C_cds_rs_number>=1) + if (project.cds_rs[0].status & (component_Started | component_Ready | component_Error )) + project.cds_rs[0].init(&project.cds_rs[0]); +#endif + + project_all_test_hwp(); +// +//#if(C_hwp_number>=1) +// if (project.hwp[0].status & (component_Started | component_Ready | component_Error )) +// project.hwp[0].init(&project.hwp[0]); +//#endif +//#if(C_hwp_number>=2) +// if (project.hwp[1].status & (component_Started | component_Ready | component_Error )) +// project.hwp[1].init(&project.hwp[1]); +//#endif +//#if(C_hwp_number>=3) +// if (project.hwp[2].status & (component_Started | component_Ready | component_Error )) +// project.hwp[2].init(&project.hwp[2]); +//#endif + } + + + + +} + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +#define set_local_status(p) p.local_status = p.read.sbus.lock_status_error.all ? local_status_Error : local_status_Ok +#define set_local_status_hwp(p) p.local_status = (p.read.comp_s.minus.all || p.read.comp_s.plus.all) ? local_status_Error : local_status_Ok +/////////////////////////////////////////////////////////// + +void project_read_all_sbus(void) +{ + + if (project.controller.status == component_Ready) + { +#if(C_adc_number>=1) + if (project.adc[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus)) + { + project.adc[0].read_sbus(&project.adc[0]); + set_local_status(project.adc[0]); + } +#endif +#if(C_adc_number>=2) + if (project.adc[1].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.adc[1].read_sbus(&project.adc[1]); + set_local_status(project.adc[1]); + } + +#endif +#if(C_adc_number>=3) + if (project.adc[2].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.adc[2].read_sbus(&project.adc[2]); + set_local_status(project.adc[2]); + } +#endif + +#if(C_cds_tk_number>=1) + if (project.cds_tk[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_tk[0].read_sbus(&project.cds_tk[0]); + set_local_status(project.cds_tk[0]); + } +#endif +#if(C_cds_tk_number>=2) + if (project.cds_tk[1].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_tk[1].read_sbus(&project.cds_tk[1]); + set_local_status(project.cds_tk[1]); + } +#endif +#if(C_cds_tk_number>=3) + if (project.cds_tk[2].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_tk[2].read_sbus(&project.cds_tk[2]); + set_local_status(project.cds_tk[2]); + } +#endif +#if(C_cds_tk_number>=4) + if (project.cds_tk[3].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_tk[3].read_sbus(&project.cds_tk[3]); + set_local_status(project.cds_tk[3]); + } +#endif +#if(C_cds_tk_number>=5) + if (project.cds_tk[4].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_tk[4].read_sbus(&project.cds_tk[4]); + set_local_status(project.cds_tk[4]); + } +#endif +#if(C_cds_tk_number>=6) + if (project.cds_tk[5].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_tk[5].read_sbus(&project.cds_tk[5]); + set_local_status(project.cds_tk[5]); + } +#endif +#if(C_cds_tk_number>=7) + if (project.cds_tk[6].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_tk[6].read_sbus(&project.cds_tk[6]); + set_local_status(project.cds_tk[6]); + } +#endif +#if(C_cds_tk_number>=8) + if (project.cds_tk[7].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_tk[7].read_sbus(&project.cds_tk[7]); + set_local_status(project.cds_tk[7]); + } +#endif + +#if(C_cds_in_number>=1) + if (project.cds_in[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_in[0].read_sbus(&project.cds_in[0]); + set_local_status(project.cds_in[0]); + } +#endif +#if(C_cds_in_number>=2) + if (project.cds_in[1].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_in[1].read_sbus(&project.cds_in[1]); + set_local_status(project.cds_in[1]); + } +#endif +#if(C_cds_in_number>=3) + if (project.cds_in[2].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_in[2].read_sbus(&project.cds_in[2]); + set_local_status(project.cds_in[2]); + } +#endif + +#if(C_cds_rs_number>=1) + if (project.cds_rs[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_rs[0].read_sbus(&project.cds_rs[0]); + // set_local_status(project.cds_rs[0]); + } +#endif + +#if(C_cds_out_number>=1) + if (project.cds_out[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_out[0].read_sbus(&project.cds_out[0]); + set_local_status(project.cds_out[0]); + } +#endif +#if(C_cds_out_number>=2) + if (project.cds_out[1].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_out[1].read_sbus(&project.cds_out[1]); + set_local_status(project.cds_out[1]); + } +#endif +#if(C_cds_out_number>=3) + if (project.cds_out[2].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { + project.cds_out[2].read_sbus(&project.cds_out[2]); + set_local_status(project.cds_out[2]); + } +#endif + +#if(C_hwp_number>=1) + if (project.hwp[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { +// project.cds_out[0].read_sbus(&project.cds_out[0]); + set_local_status_hwp(project.hwp[0]); + } +#endif +#if(C_hwp_number>=2) + if (project.hwp[1].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { +// project.cds_out[0].read_sbus(&project.cds_out[0]); + set_local_status_hwp(project.hwp[1]); + } +#endif +#if(C_hwp_number>=3) + if (project.hwp[2].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + { +// project.cds_out[0].read_sbus(&project.cds_out[0]); + set_local_status_hwp(project.hwp[2]); + } +#endif + + + + project_update_all_err_status_plates(); + + } + +} + + +void project_read_all_pbus(void) +{ + + if (project.controller.status == component_Ready) + { + + x_parallel_bus_project.read_status(&x_parallel_bus_project); + +#if(C_adc_number>=1) + project.adc[0].read_pbus(&project.adc[0]); +#endif +#if(C_adc_number>=2) + project.adc[1].read_pbus(&project.adc[1]); +#endif +#if(C_adc_number>=3) + project.adc[2].read_pbus(&project.adc[2]); +#endif + +#if(C_cds_tk_number>=1) + project.cds_tk[0].read_pbus(&project.cds_tk[0]); +#endif +#if(C_cds_tk_number>=2) + project.cds_tk[1].read_pbus(&project.cds_tk[1]); +#endif +#if(C_cds_tk_number>=3) + project.cds_tk[2].read_pbus(&project.cds_tk[2]); +#endif +#if(C_cds_tk_number>=4) + project.cds_tk[3].read_pbus(&project.cds_tk[3]); +#endif +#if(C_cds_tk_number>=5) + project.cds_tk[4].read_pbus(&project.cds_tk[4]); +#endif +#if(C_cds_tk_number>=6) + project.cds_tk[5].read_pbus(&project.cds_tk[5]); +#endif +#if(C_cds_tk_number>=7) + project.cds_tk[6].read_pbus(&project.cds_tk[6]); +#endif +#if(C_cds_tk_number>=8) + project.cds_tk[7].read_pbus(&project.cds_tk[7]); +#endif + + +#if(C_cds_in_number>=1) + project.cds_in[0].read_pbus(&project.cds_in[0]); +#endif +#if(C_cds_in_number>=2) + project.cds_in[1].read_pbus(&project.cds_in[1]); +#endif +#if(C_cds_in_number>=3) + project.cds_in[2].read_pbus(&project.cds_in[2]); +#endif + +#if(C_cds_rs_number>=1) + project.cds_rs[0].read_pbus(&project.cds_rs[0]); +#endif + +#if(C_cds_out_number>=1) + project.cds_out[0].read_pbus(&project.cds_out[0]); +#endif +#if(C_cds_out_number>=2) + project.cds_out[1].read_pbus(&project.cds_out[1]); +#endif +#if(C_cds_out_number>=3) + project.cds_out[2].read_pbus(&project.cds_out[2]); +#endif + + } + +} + +///////////////////////////////////////////////////// +// . +///////////////////////////////////////////////////// +void project_write_all_sbus(void) +{ + + if (project.controller.status == component_Ready) + { + +#if(C_adc_number>=1) + if (project.adc[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.adc[0].write_sbus(&project.adc[0]); +#endif +#if(C_adc_number>=2) + if (project.adc[1].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.adc[1].write_sbus(&project.adc[1]); +#endif +#if(C_adc_number>=3) + if (project.adc[2].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.adc[2].write_sbus(&project.adc[2]); +#endif + +#if(C_cds_tk_number>=1) + if (project.cds_tk[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_tk[0].write_sbus(&project.cds_tk[0]); +#endif +#if(C_cds_tk_number>=2) + if (project.cds_tk[1].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_tk[1].write_sbus(&project.cds_tk[1]); +#endif +#if(C_cds_tk_number>=3) + if (project.cds_tk[2].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_tk[2].write_sbus(&project.cds_tk[2]); +#endif +#if(C_cds_tk_number>=4) + if (project.cds_tk[3].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_tk[3].write_sbus(&project.cds_tk[3]); +#endif +#if(C_cds_tk_number>=5) + if (project.cds_tk[4].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_tk[4].write_sbus(&project.cds_tk[4]); +#endif +#if(C_cds_tk_number>=6) + if (project.cds_tk[5].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_tk[5].write_sbus(&project.cds_tk[5]); +#endif +#if(C_cds_tk_number>=7) + if (project.cds_tk[6].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_tk[6].write_sbus(&project.cds_tk[6]); +#endif +#if(C_cds_tk_number>=8) + if (project.cds_tk[7].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_tk[7].write_sbus(&project.cds_tk[7]); +#endif + +#if(C_cds_in_number>=1) + if (project.cds_in[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_in[0].write_sbus(&project.cds_in[0]); +#endif +#if(C_cds_in_number>=2) + if (project.cds_in[1].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_in[1].write_sbus(&project.cds_in[1]); +#endif +#if(C_cds_in_number>=3) + if (project.cds_in[2].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_in[2].write_sbus(&project.cds_in[2]); +#endif + +#if(C_cds_rs_number>=1) + if (project.cds_rs[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_rs[0].write_sbus(&project.cds_rs[0]); +#endif + +#if(C_cds_out_number>=1) + if (project.cds_out[0].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_out[0].write_sbus(&project.cds_out[0]); +#endif +#if(C_cds_out_number>=2) + if (project.cds_out[1].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_out[1].write_sbus(&project.cds_out[1]); +#endif +#if(C_cds_out_number>=3) + if (project.cds_out[2].status & (component_Started | component_Ready | component_Error | component_ErrorSBus )) + project.cds_out[2].write_sbus(&project.cds_out[2]); +#endif + + project_update_all_err_status_plates(); + + } + + + +} + +///////////////////////////////////////////////////// +// HWP hwp +///////////////////////////////////////////////////// +void project_write_all_hwp(void) +{ + + if (project.controller.status == component_Ready) + { +#if(C_hwp_number>=1) + project.hwp[0].write_all(&project.hwp[0]); +#endif +#if(C_hwp_number>=2) + project.hwp[1].write_all(&project.hwp[1]); +#endif +#if(C_hwp_number>=3) + project.hwp[2].write_all(&project.hwp[2]); +#endif + + } + +} + + + + +///////////////////////////////////////////////////// +// HWP hwp +///////////////////////////////////////////////////// +void project_read_all_hwp(void) +{ + + if (project.controller.status == component_Ready) + { +#if(C_hwp_number>=1) + project.hwp[0].read_all(&project.hwp[0]); +#endif +#if(C_hwp_number>=2) + project.hwp[1].read_all(&project.hwp[1]); +#endif +#if(C_hwp_number>=3) + project.hwp[2].read_all(&project.hwp[2]); +#endif + } + +} + + +///////////////////////////////////////////////////// +// HWP hwp +///////////////////////////////////////////////////// +void project_autospeed_all_hwp(void) +{ + + if (project.controller.status == component_Ready) + { +#if(C_hwp_number>=1) + project.hwp[0].autospeed_detect(&project.hwp[0]); +#endif +#if(C_hwp_number>=2) + project.hwp[1].autospeed_detect(&project.hwp[1]); +#endif +#if(C_hwp_number>=3) + project.hwp[2].autospeed_detect(&project.hwp[2]); +#endif + } + +} + + + + + +#define PAUSE_WAIT_SBUS 10000 +#define MAX_COUNT_ERR_READ_SBUS 1100 //2000 2 +#define MAX_COUNT_ERR_READ_SBUS_2 600 //2000 2 + +#define MAX_COUNT_OR_READ_SBUS 20//200 + + +////////////////////////////////////////////////////////////// +// . . +// flag_reset == 1 +// enable_find_all_plates = 1 USE_???? +////////////////////////////////////////////////////////////// +unsigned int project_wait_load_all_cds(int flag_reset) +{ + unsigned long counterErr = 0; + unsigned int counterOk = 0, err; + unsigned int i,count_find_plat; + unsigned int old_status_max_read_error = 0; + unsigned int prev_count_one_find_plat = 0, count_one_find_plat = 0; + unsigned int max_count_err_read_sbus = MAX_COUNT_ERR_READ_SBUS; +// unsigned int erReg, rd; +/* + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i= max_count_err_read_sbus) + { + if (flag_reset == 0) + xerror(xserial_bus_er_ID(2), (void *)0); + err = 1; + break; + } + // test ok read - stable? + if (counterOk >= MAX_COUNT_OR_READ_SBUS) + { + err = 0; + // all ok! + break; + } + if (count_find_plat == 0) // nothing find! + { + err = 0; + // all ok! + break; + } + + + } + + +// clear statistics on serial bus + + x_serial_bus_project.clear_stat(&x_serial_bus_project); + +/////////////////////////////////////// +//ADC +#if(C_adc_number>=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i=1) + for (i=0;i + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_GlobalPrototypes.h" +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "DSP281x_Ev.h" // DSP281x Examples Include File +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "Spartan2E_Functions.h" +#include "TuneUpPlane.h" +#include "x_int13.h" +#include "x_parallel_bus.h" +#include "x_serial_bus.h" +#include "xerror.h" +#include "xp_adc.h" +#include "xp_cds_in.h" +#include "xp_cds_out.h" +#include "xp_cds_rs.h" +#include "xp_cds_tk.h" +#include "xp_controller.h" +#include "xp_hwp.h" +#include "xp_inc_sensor.h" +#include "xPeriphSP6_loader.h" + + +#define WITH_RESET_ALL_PLATES 1 +#define WITHOUT_RESET_ALL_PLATES 0 +#define WITHOUT_RESET_ALL_PLATES_NO_STOP_ERROR 2 +#define WITH_RESET_ALL_PLATES_NO_STOP_ERROR 3 + + + +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +typedef struct { + +#if(C_cds_tk_number>=1) + T_component_status tk0; +#endif +#if(C_cds_tk_number>=2) + T_component_status tk1; +#endif +#if(C_cds_tk_number>=3) + T_component_status tk2; +#endif +#if(C_cds_tk_number>=4) + T_component_status tk3; +#endif +#if(C_cds_tk_number>=5) + T_component_status tk4; +#endif +#if(C_cds_tk_number>=6) + T_component_status tk5; +#endif +#if(C_cds_tk_number>=7) + T_component_status tk6; +#endif +#if(C_cds_tk_number>=8) + T_component_status tk7; +#endif + +#if(C_adc_number>=1) + T_component_status adc0; +#endif +#if(C_adc_number>=2) + T_component_status adc1; +#endif +#if(C_adc_number>=3) + T_component_status adc2; +#endif + +#if(C_cds_in_number>=1) + T_component_status in0; +#endif +#if(C_cds_in_number>=2) + T_component_status in1; +#endif + +#if(C_cds_in_number>=3) + T_component_status in2; +#endif +#if(C_cds_out_number>=1) + T_component_status out0; +#endif +#if(C_cds_out_number>=2) + T_component_status out1; +#endif +#if(C_cds_out_number>=3) + T_component_status out2; +#endif + +#if (C_cds_rs_number>=1) + T_component_status rs0; +#endif + +#if(C_hwp_number>=1) + T_component_status hwp0; +#endif +#if(C_hwp_number>=2) + T_component_status hwp1; +#endif +#if(C_hwp_number>=3) + T_component_status hwp2; +#endif + +} T_project_all_status_plates; + + + + + + + +typedef struct { + union + { + UInt16 all; + struct + { +#if(C_cds_tk_number>=1) + UInt16 tk0 :1; +#endif +#if(C_cds_tk_number>=2) + UInt16 tk1 :1; +#endif +#if(C_cds_tk_number>=3) + UInt16 tk2 :1; +#endif +#if(C_cds_tk_number>=4) + UInt16 tk3 :1; +#endif +#if(C_cds_tk_number>=5) + UInt16 tk4 :1; +#endif +#if(C_cds_tk_number>=6) + UInt16 tk5 :1; +#endif +#if(C_cds_tk_number>=7) + UInt16 tk6 :1; +#endif +#if(C_cds_tk_number>=8) + UInt16 tk7 :1; +#endif + + UInt16 res :(16-C_cds_tk_number); + + } bit; + } errors_tk; + union + { + UInt16 all; + struct + { + +#if(C_adc_number>=1) + UInt16 adc0 :1; +#endif +#if(C_adc_number>=2) + UInt16 adc1 :1; +#endif +#if(C_adc_number>=3) + UInt16 adc2 :1; +#endif + +#if(C_cds_in_number>=1) + UInt16 in0 :1; +#endif +#if(C_cds_in_number>=2) + UInt16 in1 :1; +#endif +#if(C_cds_in_number>=3) + UInt16 in2 :1; +#endif + +#if(C_cds_out_number>=1) + UInt16 out0 :1; +#endif +#if(C_cds_out_number>=2) + UInt16 out1 :1; +#endif +#if(C_cds_out_number>=3) + UInt16 out2 :1; +#endif + +#if (C_cds_rs_number>=1) + UInt16 rs0 :1; +#endif + +#if(C_hwp_number>=1) + UInt16 hwp0 :1; +#endif +#if(C_hwp_number>=2) + UInt16 hwp1 :1; +#endif +#if(C_hwp_number>=3) + UInt16 hwp2 :1; +#endif + + UInt16 res :1; + + } bit; + } errors; + +} T_project_all_errors_plates; + +#define T_PROJECT_ALL_ERRORS_PLATES_DEFAULTS {0,0} +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// + + + + +typedef struct TS_project{ + T_controller controller; +// int controller; + T_project_all_errors_plates all_err_plates; + T_project_all_status_plates all_status_plates; + T_cds_tk cds_tk[C_cds_tk_number]; + T_adc adc[C_adc_number]; + T_cds_in cds_in[C_cds_in_number]; + T_cds_out cds_out[C_cds_out_number]; +#if (C_cds_rs_number>=1) + T_cds_rs cds_rs[C_cds_rs_number]; +#endif + T_hwp hwp[C_hwp_number]; +// T_omega omega[C_omega_number]; +// T_dispatcher dispatcher; +// T_project_soft_info soft_info; + X_SERIAL_BUS *x_serial_bus; + X_PARALLEL_BUS *x_parallel_bus; + + int inited; + + + void (*init)(); // Pointer to calculation function + void (*read_all_sbus)(); // Pointer to calculation function + void (*read_all_pbus)(); + void (*write_all_sbus)(); + void (*reload_all_plates_with_reset)(); // + void (*reload_all_plates_without_reset)(); // + void (*reload_all_plates_with_reset_no_stop_error)(); // + void (*reload_all_plates_without_reset_no_stop_error)(); // + void (*write_all_hwp)(); + void (*read_all_hwp)(); + void (*send_reset_all_plates)(); + void (*stop_parallel_bus)(); + void (*start_parallel_bus)(); + void (*clear)(); + void (*read_errors_controller)(); + void (*reset_errors_controller)(); + void (*load_cfg_to_plates)(); + void (*clear_errors_all_plates)(); + void (*disable_all_interrupt)(); + void (*enable_all_interrupt)(); + void (*enable_int13)(); + void (*disable_int13)(); + void (*find_all_cds)(); + + + +} T_project; + +extern T_project project; + + +#if(C_cds_tk_number==8) +#define PROJECT_DEFAULTS_CDS_TK {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS} +#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady +#endif +#if(C_cds_tk_number==7) +#define PROJECT_DEFAULTS_CDS_TK {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS} +#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady +#endif +#if(C_cds_tk_number==6) +#define PROJECT_DEFAULTS_CDS_TK {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS, T_cds_tk_DEFAULTS} +#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady +#endif +#if(C_cds_tk_number==5) +#define PROJECT_DEFAULTS_CDS_TK {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS} +#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady,component_NotReady +#endif +#if(C_cds_tk_number==4) +#define PROJECT_DEFAULTS_CDS_TK {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS} +#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady,component_NotReady +#endif +#if(C_cds_tk_number==3) +#define PROJECT_DEFAULTS_CDS_TK {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS} +#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady +#endif +#if(C_cds_tk_number==2) +#define PROJECT_DEFAULTS_CDS_TK {T_cds_tk_DEFAULTS,T_cds_tk_DEFAULTS} +#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady +#endif +#if(C_cds_tk_number==1) +#define PROJECT_DEFAULTS_CDS_TK {T_cds_tk_DEFAULTS} +#define CDS_TK_STATUS_PLATES_DEFAULTS component_NotReady +#endif + +#if(C_adc_number==1) +#define PROJECT_DEFAULTS_ADC {T_adc_DEFAULTS} +#define ADC_STATUS_PLATES_DEFAULTS component_NotReady +#endif +#if(C_adc_number==2) +#define PROJECT_DEFAULTS_ADC {T_adc_DEFAULTS,T_adc_DEFAULTS} +#define ADC_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady +#endif +#if(C_adc_number==3) +#define PROJECT_DEFAULTS_ADC {T_adc_DEFAULTS,T_adc_DEFAULTS,T_adc_DEFAULTS} +#define ADC_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady +#endif + + +#if(C_hwp_number==1) +#define PROJECT_DEFAULTS_HWP T_hwp_DEFAULTS +#define HWP_STATUS_PLATES_DEFAULTS component_NotReady +#endif +#if(C_hwp_number==2) +#define PROJECT_DEFAULTS_HWP {T_hwp_DEFAULTS, T_hwp_DEFAULTS} +#define HWP_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady +#endif +#if(C_hwp_number==3) +#define PROJECT_DEFAULTS_HWP {T_hwp_DEFAULTS, T_hwp_DEFAULTS, T_hwp_DEFAULTS} +#define HWP_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady +#endif + + +#if(C_cds_out_number==1) +#define PROJECT_DEFAULTS_OUT {T_cds_out_DEFAULTS} +#define OUT_STATUS_PLATES_DEFAULTS component_NotReady +#endif +#if(C_cds_out_number==2) +#define PROJECT_DEFAULTS_OUT {T_cds_out_DEFAULTS,T_cds_out_DEFAULTS} +#define OUT_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady +#endif +#if(C_cds_out_number==3) +#define PROJECT_DEFAULTS_OUT {T_cds_out_DEFAULTS,T_cds_out_DEFAULTS,T_cds_out_DEFAULTS} +#define OUT_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady +#endif + +#if(C_cds_in_number==1) +#define PROJECT_DEFAULTS_IN {T_cds_in_DEFAULTS} +#define IN_STATUS_PLATES_DEFAULTS component_NotReady +#endif +#if(C_cds_in_number==2) +#define PROJECT_DEFAULTS_IN {T_cds_in_DEFAULTS,T_cds_in_DEFAULTS} +#define IN_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady +#endif +#if(C_cds_in_number==3) +#define PROJECT_DEFAULTS_IN {T_cds_in_DEFAULTS,T_cds_in_DEFAULTS,T_cds_in_DEFAULTS} +#define IN_STATUS_PLATES_DEFAULTS component_NotReady,component_NotReady,component_NotReady +#endif + + + +#if(C_cds_rs_number>=1) +#define PROJECT_DEFAULTS_CDS_RS {T_cds_rs_DEFAULTS}, +#define CDS_RS_STATUS_PLATES_DEFAULTS ,component_NotReady +#else +#define PROJECT_DEFAULTS_CDS_RS +#define CDS_RS_STATUS_PLATES_DEFAULTS +#endif + + +#define T_PROJECT_ALL_STATUS_PLATES_DEFAULTS {HWP_STATUS_PLATES_DEFAULTS, ADC_STATUS_PLATES_DEFAULTS, CDS_TK_STATUS_PLATES_DEFAULTS, OUT_STATUS_PLATES_DEFAULTS, IN_STATUS_PLATES_DEFAULTS CDS_RS_STATUS_PLATES_DEFAULTS} + + + + +#define PROJECT_DEFAULTS { T_controller_DEFAULTS, \ + T_PROJECT_ALL_ERRORS_PLATES_DEFAULTS, T_PROJECT_ALL_STATUS_PLATES_DEFAULTS, \ + PROJECT_DEFAULTS_CDS_TK, \ + PROJECT_DEFAULTS_ADC, \ + PROJECT_DEFAULTS_IN, \ + PROJECT_DEFAULTS_OUT, \ + PROJECT_DEFAULTS_CDS_RS \ + PROJECT_DEFAULTS_HWP, \ + NULL, NULL, \ + 0,\ + (void (*)(Uint32))project_init, \ + (void (*)(Uint32))project_read_all_sbus, \ + (void (*)(Uint32))project_read_all_pbus,\ + (void (*)(Uint32))project_write_all_sbus,\ + (void (*)(Uint32))project_reload_all_plates_with_reset, \ + (void (*)(Uint32))project_reload_all_plates_without_reset, \ + (void (*)(Uint32))project_reload_all_plates_with_reset_no_stop_error, \ + (void (*)(Uint32))project_reload_all_plates_without_reset_no_stop_error, \ + (void (*)(Uint32))project_write_all_hwp, \ + (void (*)(Uint32))project_read_all_hwp, \ + (void (*)(Uint32))send_reset_all_plates, \ + (void (*)(Uint32))project_stop_parallel_bus, \ + (void (*)(Uint32))project_start_parallel_bus, \ + (void (*)(Uint32))project_clear, \ + (void (*)(Uint32))project_read_errors_controller,\ + (void (*)(Uint32))project_reset_errors_controller, \ + (void (*)(Uint32))project_load_cfg_to_plates, \ + (void (*)(Uint32))project_clear_errors_all_plates, \ + (void (*)(Uint32))project_disable_all_interrupts, \ + (void (*)(Uint32))project_enable_all_interrupts,\ + (void (*)(Uint32))project_enable_int13,\ + (void (*)(Uint32))project_disable_int13,\ + (void (*)(Uint32))project_find_all_cds\ + } + + +void project_init(void); +void project_read_all_sbus(void); +void project_read_all_pbus(void); +void project_write_all_sbus(void); +void project_reload_all_plates_with_reset(void); +void project_reload_all_plates_without_reset(void); +void project_reload_all_plates_with_reset_no_stop_error(void); +void project_reload_all_plates_without_reset_no_stop_error(void); +void project_write_all_hwp(void); +void project_read_all_hwp(void); +void project_autospeed_all_hwp(void); + +void send_reset_all_plates(void); + + +unsigned int project_wait_load_all_cds(int flag_reset); +void project_find_all_cds(void); + +void project_stop_parallel_bus(void); +void project_start_parallel_bus(void); +void project_load_cfg_to_plates(void); + +void project_clear(void); +void project_read_errors_controller(void); + +void project_reset_errors_controller(void); + + + +void project_reload_all_plates(int reset); + +void project_clear_errors_all_plates(void); + +void project_all_test_hwp(void); + +////////////////////////////////////////////////////////////////////// +// +////////////////////////////////////////////////////////////////////// +void project_update_all_err_status_plates(void); + + +void project_enable_all_interrupts(void); +void project_disable_all_interrupts(void); + + +void project_enable_int13(void); +void project_disable_int13(void); + +void project_run_init_all_plates(void); + +#endif // end XP_PROJECT_H diff --git a/Inu/Src/N12_Xilinx/xp_tools.c b/Inu/Src/N12_Xilinx/xp_tools.c new file mode 100644 index 0000000..15c8f82 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_tools.c @@ -0,0 +1,41 @@ +#include "MemoryFunctions.h" +#include "xp_tools.h" +#include "xp_tools.h" + +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" + + + +////////////////////////////////////// +////////////////////////////////////// +// ADR_ASYNC_BUS_TABLE +////////////////////////////////////// +////////////////////////////////////// +void set_adr_sync_table(int np) +{ + unsigned int active_address; + + active_address = i_ReadMemory(ADR_ASYNC_BUS_TABLE); + active_address |= (1 << np); + + WriteMemory(ADR_ASYNC_BUS_TABLE, active_address); +} + + +////////////////////////////////////// +////////////////////////////////////// +// ADR_ASYNC_BUS_TABLE +////////////////////////////////////// +////////////////////////////////////// +void clear_adr_sync_table(int np) +{ + unsigned int active_address; + + active_address = i_ReadMemory(ADR_ASYNC_BUS_TABLE); + active_address &= (~(1 << np)); + + WriteMemory(ADR_ASYNC_BUS_TABLE, active_address); +} + + diff --git a/Inu/Src/N12_Xilinx/xp_tools.h b/Inu/Src/N12_Xilinx/xp_tools.h new file mode 100644 index 0000000..7382290 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_tools.h @@ -0,0 +1,16 @@ +#ifndef _XP_TOOLS_H +#define _XP_TOOLS_H + + + + +void set_adr_sync_table(int np); +void clear_adr_sync_table(int np); + + + + + + +#endif // END _XP_TOOLS_H + diff --git a/Inu/Src/N12_Xilinx/xp_write_xpwm_time.c b/Inu/Src/N12_Xilinx/xp_write_xpwm_time.c new file mode 100644 index 0000000..580483d --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_write_xpwm_time.c @@ -0,0 +1,671 @@ +/* + * xp_write_xpwm_time.c + * + * Created on: 03 . 2018 . + * Author: stud + */ + +#include "xp_write_xpwm_time.h" + +#include + +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "xerror.h" + + + + +#pragma DATA_SECTION(xpwm_time,".fast_vars1"); +XPWM_TIME xpwm_time = DEFAULT_XPWM_TIME; + + +#define set_default_tclosed(k,b) {if (b) k = p->Tclosed_saw_direct_1; else k = p->Tclosed_saw_direct_0;} +/////////////////////////////////////////////////////// +/////////////////////////////////////////////////////// +/////////////////////////////////////////////////////// +void set_mode_soft_x24(void) +{ + i_WriteMemory(ADR_PWM_START_STOP, (i_ReadMemory(ADR_PWM_START_STOP) | 0x8000) ); +} + +void set_mode_hard_x24(void) +{ + i_WriteMemory(ADR_PWM_START_STOP, (i_ReadMemory(ADR_PWM_START_STOP) & 0x7fff) ); +} + +void set_start_pwm_x24(void) +{ + i_WriteMemory(ADR_PWM_START_STOP, (i_ReadMemory(ADR_PWM_START_STOP) | 0x0001) ); +} + +void set_stop_pwm_x24(void) +{ + i_WriteMemory(ADR_PWM_START_STOP, (i_ReadMemory(ADR_PWM_START_STOP) & 0xfffe) ); +} + +////////////////////////////////////////////////////////// + + + +void initXpwmTimeStructure(XPWM_TIME *p) +{ + + set_default_tclosed(p->Ta0_0, p->saw_direct.bits.bit0); + set_default_tclosed(p->Ta0_1, p->saw_direct.bits.bit1); + set_default_tclosed(p->Tb0_0, p->saw_direct.bits.bit2); + set_default_tclosed(p->Tb0_1, p->saw_direct.bits.bit3); + set_default_tclosed(p->Tc0_0, p->saw_direct.bits.bit4); + set_default_tclosed(p->Tc0_1, p->saw_direct.bits.bit5); + + set_default_tclosed(p->Ta1_0, p->saw_direct.bits.bit6); + set_default_tclosed(p->Ta1_1, p->saw_direct.bits.bit7); + set_default_tclosed(p->Tb1_0, p->saw_direct.bits.bit8); + set_default_tclosed(p->Tb1_1, p->saw_direct.bits.bit9); + set_default_tclosed(p->Tc1_0, p->saw_direct.bits.bit10); + set_default_tclosed(p->Tc1_1, p->saw_direct.bits.bit11); + + p->Tbr0_0 = 0; + p->Tbr0_1 = 0; + p->Tbr1_0 = 0; + p->Tbr1_1 = 0; + + if (p->freq_pwm == 0) + { + xerror(main_er_ID(2),(void *)1); // 0 !!! + } + + + p->inited = 1; +} + +#pragma CODE_SECTION(xpwm_write_zero_1,".fast_run1"); +void xpwm_write_zero_1(XPWM_TIME *p) +{ + unsigned int tclose; + + //a + set_default_tclosed(tclose, p->saw_direct.bits.bit0); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_A1_PLUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Ta0_0 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit1); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_A1_MINUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Ta0_1 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit2); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_B1_PLUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Tb0_0 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit3); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_B1_MINUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Tb0_1 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit4); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_C1_PLUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Tc0_0 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit5); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_C1_MINUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Tc0_1 = tclose; + +} + +#pragma CODE_SECTION(xpwm_write_zero_2,".fast_run1"); +void xpwm_write_zero_2(XPWM_TIME *p) +{ + unsigned int tclose; + +//b + set_default_tclosed(tclose, p->saw_direct.bits.bit6); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_A2_PLUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Ta1_0 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit7); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_A2_MINUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Ta1_1 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit8); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_B2_PLUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Tb1_0 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit9); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_B2_MINUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Tb1_1 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit10); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_C2_PLUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Tc1_0 = tclose; + + set_default_tclosed(tclose, p->saw_direct.bits.bit11); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_C2_MINUS); + i_WriteMemory(ADR_PWM_TIMING, tclose); + p->Tc1_1 = tclose; + +} + +#pragma CODE_SECTION(xpwm_write_zero_break_1,".fast_run1"); +void xpwm_write_zero_break_1(XPWM_TIME *p) +{ + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_BR1_PLUS); + i_WriteMemory(ADR_PWM_TIMING, 0); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_BR1_MINUS); + i_WriteMemory(ADR_PWM_TIMING, 0); + + p->Tbr0_0 = 0; + p->Tbr0_1 = 0; + +} + +#pragma CODE_SECTION(xpwm_write_zero_break_2,".fast_run1"); +void xpwm_write_zero_break_2(XPWM_TIME *p) +{ + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_BR2_PLUS); + i_WriteMemory(ADR_PWM_TIMING, 0); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_BR2_MINUS); + i_WriteMemory(ADR_PWM_TIMING, 0); + + p->Tbr1_0 = 0; + p->Tbr1_1 = 0; +} + +#pragma CODE_SECTION(xpwm_write_zero_winding_break_times_16_lines,".fast_run1"); +void xpwm_write_zero_winding_break_times_16_lines(XPWM_TIME *p) +{ + xpwm_write_zero_1(p); + xpwm_write_zero_2(p); + xpwm_write_zero_break_1(p); + xpwm_write_zero_break_2(p); +} + +#pragma CODE_SECTION(xpwm_write_1_2_winding_break_times_16_lines,".fast_run1"); +void xpwm_write_1_2_winding_break_times_16_lines(XPWM_TIME *p) +{ + if (!(i_ReadMemory(ADR_ERRORS_TOTAL_INFO))) + { +//a + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit0==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_A1_PLUS); + i_WriteMemory(ADR_PWM_TIMING, p->Ta0_0); + } + + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit1 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit1==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_A1_MINUS); + i_WriteMemory(ADR_PWM_TIMING, p->Ta0_1); + } + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit2 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit2==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_B1_PLUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tb0_0); + } + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit3 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit3==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_B1_MINUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tb0_1); + } + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit4 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit4==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_C1_PLUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tc0_0); + } + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit5 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit5==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_C1_MINUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tc0_1); + } +//b + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit6 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit6==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_A2_PLUS); + i_WriteMemory(ADR_PWM_TIMING, p->Ta1_0); + } + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit7 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit7==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_A2_MINUS); + i_WriteMemory(ADR_PWM_TIMING, p->Ta1_1); + } + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit8 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit8==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_B2_PLUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tb1_0); + } + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit9 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit9==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_B2_MINUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tb1_1); + } + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit10 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit10==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_C2_PLUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tc1_0); + } + if ((p->mode_reload==PWM_MODE_RELOAD_FORCE) + || (p->saw_direct.bits.bit11 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_HIGH) + || (p->saw_direct.bits.bit11==0 && p->mode_reload==PWM_MODE_RELOAD_LEVEL_LOW) ) + { + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_C2_MINUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tc1_1); + } + +//br1 br2 + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_BR1_PLUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tbr0_0); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_BR1_MINUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tbr0_1); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_BR2_PLUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tbr1_0); + i_WriteMemory(ADR_PWM_KEY_NUMBER, PWM_KEY_NUMBER_BR2_MINUS); + i_WriteMemory(ADR_PWM_TIMING, p->Tbr1_1); + } + else + { + hard_stop_x24_pwm_all(); + xpwm_write_zero_winding_break_times_16_lines(p); + } +} + +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_start_x24_break_1,".fast_run2") +void soft_start_x24_break_1(void) +{ + unsigned int mask_tk_lines; + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines &= ENABLE_PWM_BREAK_1; + + set_mode_soft_x24(); + + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + + set_start_pwm_x24(); + +// if (!(i_ReadMemory(ADR_PWM_START_STOP) & 0x1)) +// i_WriteMemory(ADR_PWM_START_STOP, PWM_START_SOFT); // soft start + +} +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_start_x24_break_2,".fast_run2") +void soft_start_x24_break_2(void) +{ + unsigned int mask_tk_lines; + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines &= ENABLE_PWM_BREAK_2; + + set_mode_soft_x24(); + + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + + set_start_pwm_x24(); + +// if (!(i_ReadMemory(ADR_PWM_START_STOP) & 0x1)) +// i_WriteMemory(ADR_PWM_START_STOP, PWM_START_SOFT); // soft start +} +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_start_x24_break_all,".fast_run2") +void soft_start_x24_break_all(void) +{ + unsigned int mask_tk_lines; + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines &= ENABLE_PWM_BREAK_ALL; + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + + set_start_pwm_x24(); + +// if (!(i_ReadMemory(ADR_PWM_START_STOP) & 0x1)) +// i_WriteMemory(ADR_PWM_START_STOP, PWM_START_SOFT); // soft start +} + +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(soft_start_x24_pwm_1,".fast_run"); +void soft_start_x24_pwm_1(void) +{ + unsigned int mask_tk_lines; + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines &= ENABLE_PWM_1; + +#if (TK_DISABLE_OUTPUT_A1) + mask_tk_lines |= DISABLE_PWM_A1; +#endif +#if (TK_DISABLE_OUTPUT_B1) + mask_tk_lines |= DISABLE_PWM_B1; +#endif +#if (TK_DISABLE_OUTPUT_C1) + mask_tk_lines |= DISABLE_PWM_C1; +#endif + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + + set_start_pwm_x24(); + +// if (!(i_ReadMemory(ADR_PWM_START_STOP) & 0x1)) +// i_WriteMemory(ADR_PWM_START_STOP, PWM_START_SOFT); // soft start + +} +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_start_x24_pwm_2,".fast_run"); +void soft_start_x24_pwm_2(void) +{ + unsigned int mask_tk_lines; +// mPWM_b = 1; + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines &= ENABLE_PWM_2; + +#if (TK_DISABLE_OUTPUT_A2) + mask_tk_lines |= DISABLE_PWM_A2; +#endif +#if (TK_DISABLE_OUTPUT_B2) + mask_tk_lines |= DISABLE_PWM_B2; +#endif +#if (TK_DISABLE_OUTPUT_C2) + mask_tk_lines |= DISABLE_PWM_C2; +#endif + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + set_start_pwm_x24(); + +// if (!(i_ReadMemory(ADR_PWM_START_STOP) & 0x1)) +// i_WriteMemory(ADR_PWM_START_STOP, PWM_START_SOFT); // soft start + +} +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_start_x24_pwm_1_2,".fast_run"); +void soft_start_x24_pwm_1_2(void) +{ + unsigned int mask_tk_lines; +// mPWM_a = 1; +// mPWM_b = 1; + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines &= ENABLE_PWM_1_2; + +#if (TK_DISABLE_OUTPUT_A1) + mask_tk_lines |= DISABLE_PWM_A1; +#endif +#if (TK_DISABLE_OUTPUT_B1) + mask_tk_lines |= DISABLE_PWM_B1; +#endif +#if (TK_DISABLE_OUTPUT_C1) + mask_tk_lines |= DISABLE_PWM_C1; +#endif +#if (TK_DISABLE_OUTPUT_A2) + mask_tk_lines |= DISABLE_PWM_A2; +#endif +#if (TK_DISABLE_OUTPUT_B2) + mask_tk_lines |= DISABLE_PWM_B2; +#endif +#if (TK_DISABLE_OUTPUT_C2) + mask_tk_lines |= DISABLE_PWM_C2; +#endif + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + set_start_pwm_x24(); + +// if (!(i_ReadMemory(ADR_PWM_START_STOP) & 0x1)) +// i_WriteMemory(ADR_PWM_START_STOP, PWM_START_SOFT); // soft start + +} + +//////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(soft_start_x24_pwm_all,".fast_run"); +void soft_start_x24_pwm_all(void) +{ + unsigned int mask_tk_lines; +// mPWM_a = 1; +// mPWM_b = 1; + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines &= ENABLE_PWM_ALL; + +#if (TK_DISABLE_OUTPUT_A1) + mask_tk_lines |= DISABLE_PWM_A1; +#endif +#if (TK_DISABLE_OUTPUT_B1) + mask_tk_lines |= DISABLE_PWM_B1; +#endif +#if (TK_DISABLE_OUTPUT_C1) + mask_tk_lines |= DISABLE_PWM_C1; +#endif +#if (TK_DISABLE_OUTPUT_A2) + mask_tk_lines |= DISABLE_PWM_A2; +#endif +#if (TK_DISABLE_OUTPUT_B2) + mask_tk_lines |= DISABLE_PWM_B2; +#endif +#if (TK_DISABLE_OUTPUT_C2) + mask_tk_lines |= DISABLE_PWM_C2; +#endif + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + set_start_pwm_x24(); + +// if (!(i_ReadMemory(ADR_PWM_START_STOP) & 0x1)) +// i_WriteMemory(ADR_PWM_START_STOP, PWM_START_SOFT); // soft start + +} + +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(hard_stop_x24_pwm_all,".fast_run"); +void hard_stop_x24_pwm_all(void) +{ + unsigned int mask_tk_lines; + + xpwm_write_zero_1(&xpwm_time); + xpwm_write_zero_2(&xpwm_time); + + xpwm_write_zero_break_1(&xpwm_time); + xpwm_write_zero_break_2(&xpwm_time); + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines |= DISABLE_PWM_ALL; + + set_mode_hard_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + set_stop_pwm_x24(); + +// i_WriteMemory(ADR_PWM_START_STOP, PWM_STOP_HARD); + +} + +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(soft_stop_x24_pwm_all,".fast_run"); +void soft_stop_x24_pwm_all(void) +{ + unsigned int mask_tk_lines; + + xpwm_write_zero_1(&xpwm_time); + xpwm_write_zero_2(&xpwm_time); + + xpwm_write_zero_break_1(&xpwm_time); + xpwm_write_zero_break_2(&xpwm_time); + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines |= DISABLE_PWM_ALL; + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + set_stop_pwm_x24(); + +// i_WriteMemory(ADR_PWM_START_STOP, PWM_STOP_SOFT); + +} +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_stop_x24_pwm_1_2,".fast_run"); +void soft_stop_x24_pwm_1_2(void) +{ + unsigned int mask_tk_lines; + + xpwm_write_zero_1(&xpwm_time); + xpwm_write_zero_2(&xpwm_time); + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines |= DISABLE_PWM_1_2; + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + if (mask_tk_lines == DISABLE_PWM_ALL) + set_stop_pwm_x24(); +// WriteMemory(ADR_PWM_START_STOP, PWM_STOP_SOFT); + +} +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_stop_x24_pwm_1,".fast_run"); +void soft_stop_x24_pwm_1(void) +{ + unsigned int mask_tk_lines; + + xpwm_write_zero_1(&xpwm_time); +// xpwm_write_zero_2(&xpwm_time); + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines |= DISABLE_PWM_1; + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + if (mask_tk_lines == DISABLE_PWM_ALL) + set_stop_pwm_x24(); + +} +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_stop_x24_pwm_2,".fast_run"); +void soft_stop_x24_pwm_2(void) +{ + unsigned int mask_tk_lines; + +// xpwm_write_zero_1(&xpwm_time); + xpwm_write_zero_2(&xpwm_time); + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines |= DISABLE_PWM_2; + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + if (mask_tk_lines == DISABLE_PWM_ALL) + set_stop_pwm_x24(); +} +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_stop_x24_break_1,".fast_run2") +void soft_stop_x24_break_1(void) +{ + unsigned int mask_tk_lines; + + xpwm_write_zero_break_1(&xpwm_time); +// xpwm_write_zero_break_2(&xpwm_time); + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines |= DISABLE_PWM_BREAK_1; + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + if (mask_tk_lines == DISABLE_PWM_ALL) + set_stop_pwm_x24(); + +} +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_stop_x24_break_2,".fast_run2") +void soft_stop_x24_break_2(void) +{ + unsigned int mask_tk_lines; + +// xpwm_write_zero_break_1(&xpwm_time); + xpwm_write_zero_break_2(&xpwm_time); + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines |= DISABLE_PWM_BREAK_2; + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + if (mask_tk_lines == DISABLE_PWM_ALL) + set_stop_pwm_x24(); +} +////////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(soft_stop_x24_break_all,".fast_run2") +void soft_stop_x24_break_all(void) +{ + unsigned int mask_tk_lines; + + xpwm_write_zero_break_1(&xpwm_time); + xpwm_write_zero_break_2(&xpwm_time); + + mask_tk_lines = i_ReadMemory(ADR_TK_MASK_0); + mask_tk_lines |= DISABLE_PWM_BREAK_ALL; + + set_mode_soft_x24(); + i_WriteMemory(ADR_TK_MASK_0, mask_tk_lines); + if (mask_tk_lines == DISABLE_PWM_ALL) + set_stop_pwm_x24(); +} +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// + diff --git a/Inu/Src/N12_Xilinx/xp_write_xpwm_time.h b/Inu/Src/N12_Xilinx/xp_write_xpwm_time.h new file mode 100644 index 0000000..22293a9 --- /dev/null +++ b/Inu/Src/N12_Xilinx/xp_write_xpwm_time.h @@ -0,0 +1,228 @@ +/* + * xp_write_xpwm_time.h + * + * Created on: 03 . 2018 . + * Author: stud + */ + +#ifndef XP_WRITE_TIME_H_ +#define XP_WRITE_TIME_H_ + + +#include "word_structurs.h" + + + +#define PWM_ERROR_LEVEL_INTERRUPT 0 // , !!! +#define PWM_LOW_LEVEL_INTERRUPT 1 // +#define PWM_HIGH_LEVEL_INTERRUPT 2 // + + +#define PWM_MODE_RELOAD_FORCE 0 // +#define PWM_MODE_RELOAD_LEVEL_LOW 1 // , saw_direct=1 +#define PWM_MODE_RELOAD_LEVEL_HIGH 2 // , saw_direct=0 + + + + + +#define PWM_KEY_NUMBER_A1_PLUS 0 +#define PWM_KEY_NUMBER_A1_MINUS 1 +#define PWM_KEY_NUMBER_B1_PLUS 2 +#define PWM_KEY_NUMBER_B1_MINUS 3 +#define PWM_KEY_NUMBER_C1_PLUS 4 +#define PWM_KEY_NUMBER_C1_MINUS 5 + +#define PWM_KEY_NUMBER_A2_PLUS 6 +#define PWM_KEY_NUMBER_A2_MINUS 7 +#define PWM_KEY_NUMBER_B2_PLUS 8 +#define PWM_KEY_NUMBER_B2_MINUS 9 +#define PWM_KEY_NUMBER_C2_PLUS 10 +#define PWM_KEY_NUMBER_C2_MINUS 11 + +#define PWM_KEY_NUMBER_BR1_PLUS 12 +#define PWM_KEY_NUMBER_BR1_MINUS 13 + +#define PWM_KEY_NUMBER_BR2_PLUS 14 +#define PWM_KEY_NUMBER_BR2_MINUS 15 + +////////////////////////////////////////////////////////////////////// +#define ENABLE_PWM_BREAK_ALL 0x0fff +#define ENABLE_PWM_BREAK_1 0xcfff +#define ENABLE_PWM_BREAK_2 0x3fff + +#define ENABLE_PWM_1 0xffc0 +#define ENABLE_PWM_2 0xf03f +#define ENABLE_PWM_1_2 0xf000 + +#define ENABLE_PWM_ALL 0x0000 + +// +#define DISABLE_PWM_BREAK_ALL 0xf000 +#define DISABLE_PWM_BREAK_1 0x3000 +#define DISABLE_PWM_BREAK_2 0xc000 + +#define DISABLE_PWM_1 0x003f +#define DISABLE_PWM_2 0x0fc0 +#define DISABLE_PWM_1_2 0x0fff + +#define DISABLE_PWM_ALL 0xffff + +/// +#define DISABLE_PWM_A1 0x0003 +#define DISABLE_PWM_B1 0x000c +#define DISABLE_PWM_C1 0x0030 + +#define DISABLE_PWM_A2 0x00c0 +#define DISABLE_PWM_B2 0x0300 +#define DISABLE_PWM_C2 0x0c00 +// +////////////////////////////////////////////////////////////////////// +/* + * PWM - Start Stop + * (15) - Soft start-stop m0de 1- soft mode enabled, 0 -disabled. , + * (0)- = 0, ( )., - . + * - soft mode . + * ! . + * (0) - 1 -start, 0 - stop + */ +#define PWM_START_SOFT 0x8001 +#define PWM_START_HARD 0x0001 + +#define PWM_STOP_SOFT 0x8000 +#define PWM_STOP_HARD 0x0000 + +///////////////////////////////////// + + + + +///////////////////////////////////// +typedef struct +{ + // Winding 1 times + unsigned int Ta0_0; + unsigned int Ta0_1; + unsigned int Tb0_0; + unsigned int Tb0_1; + unsigned int Tc0_0; + unsigned int Tc0_1; + // Winding 2 times + unsigned int Ta1_0; + unsigned int Ta1_1; + unsigned int Tb1_0; + unsigned int Tb1_1; + unsigned int Tc1_0; + unsigned int Tc1_1; + // Break transistors + unsigned int Tbr0_0; + unsigned int Tbr0_1; + unsigned int Tbr1_0; + unsigned int Tbr1_1; + //Level transistors closed + unsigned int Tclosed_high; +// unsigned int Tclosed_1; + unsigned int pwm_tics; + unsigned int half_pwm_tics; + unsigned int inited; + unsigned int freq_pwm; + unsigned int Tclosed_saw_direct_0; + unsigned int Tclosed_saw_direct_1; + unsigned int current_period; + unsigned int where_interrupt; + unsigned int mode_reload; + unsigned int one_or_two_interrupts_run; + unsigned int what_next_interrupt; + unsigned int do_sync_out; + unsigned int disable_sync_out; + WORD_UINT2BITS_STRUCT saw_direct; + void (*write_1_2_winding_break_times)(); + void (*write_zero_winding_break_times)(); + void (*init)(); +} XPWM_TIME; + +#define DEFAULT_XPWM_TIME {0,0,0,0,0,0, 0,0,0,0,0,0,0, 0,0,0,0,0, 0,0,0, 0, 0, 0, 0, 0,0,0, 0,0, {0}, \ + xpwm_write_1_2_winding_break_times_16_lines, \ + xpwm_write_zero_winding_break_times_16_lines, \ + initXpwmTimeStructure \ + } + +void xpwm_write_1_2_winding_break_times_16_lines(XPWM_TIME *p); +void xpwm_write_zero_winding_break_times_16_lines(XPWM_TIME *p); + +void initXpwmTimeStructure(XPWM_TIME *p); + +extern XPWM_TIME xpwm_time; + +#define write_winding1_fase_a(T0, T1) \ + { i_WriteMemory(ADR_PWM_KEY_NUMBER, 0); i_WriteMemory(ADR_PWM_TIMING, T0); \ + i_WriteMemory(ADR_PWM_KEY_NUMBER, 1); i_WriteMemory(ADR_PWM_TIMING, T1);} + +#define write_winding1_fase_b(T0, T1) \ + { i_WriteMemory(ADR_PWM_KEY_NUMBER, 2); i_WriteMemory(ADR_PWM_TIMING, T0); \ + i_WriteMemory(ADR_PWM_KEY_NUMBER, 3); i_WriteMemory(ADR_PWM_TIMING, T1); } + +#define write_winding1_fase_c(T0, T1) \ + { i_WriteMemory(ADR_PWM_KEY_NUMBER, 4); i_WriteMemory(ADR_PWM_TIMING, T0); \ + i_WriteMemory(ADR_PWM_KEY_NUMBER, 5); i_WriteMemory(ADR_PWM_TIMING, T1); } + +#define write_winding2_fase_a(T0, T1) \ + { i_WriteMemory(ADR_PWM_KEY_NUMBER, 6); i_WriteMemory(ADR_PWM_TIMING, T0); \ + i_WriteMemory(ADR_PWM_KEY_NUMBER, 7); i_WriteMemory(ADR_PWM_TIMING, T1); } + +#define write_winding2_fase_b(T0, T1) \ + { i_WriteMemory(ADR_PWM_KEY_NUMBER, 8); i_WriteMemory(ADR_PWM_TIMING, T0); \ + i_WriteMemory(ADR_PWM_KEY_NUMBER, 9); i_WriteMemory(ADR_PWM_TIMING, T1); } + +#define write_winding2_fase_c(T0, T1) \ + { i_WriteMemory(ADR_PWM_KEY_NUMBER, 10); i_WriteMemory(ADR_PWM_TIMING, T0); \ + i_WriteMemory(ADR_PWM_KEY_NUMBER, 11); i_WriteMemory(ADR_PWM_TIMING, T1); } +#define write_break_winding1(T0, T1) \ + { i_WriteMemory(ADR_PWM_KEY_NUMBER, 12); i_WriteMemory(ADR_PWM_TIMING, T0); \ + i_WriteMemory(ADR_PWM_KEY_NUMBER, 13); i_WriteMemory(ADR_PWM_TIMING, T1); } + +#define write_break_winding2(T0, T1) \ + { i_WriteMemory(ADR_PWM_KEY_NUMBER, 14); i_WriteMemory(ADR_PWM_TIMING, T0); \ + i_WriteMemory(ADR_PWM_KEY_NUMBER, 15); i_WriteMemory(ADR_PWM_TIMING, T1); } + + +//// +// stop +void hard_stop_x24_pwm_all(void); +void soft_stop_x24_pwm_all(void); + +void soft_stop_x24_pwm_1_2(void); + +void soft_stop_x24_pwm_1(void); +void soft_stop_x24_pwm_2(void); + +void soft_stop_x24_break_1(void); +void soft_stop_x24_break_2(void); + +void soft_stop_x24_break_all(void); + +//// +// start +void soft_start_x24_pwm_all(void); + +void soft_start_x24_pwm_1(void); +void soft_start_x24_pwm_2(void); +void soft_start_x24_pwm_1_2(void); + +void soft_start_x24_break_1(void); +void soft_start_x24_break_2(void); +void soft_start_x24_break_all(void); + + + +/////////////// +void set_mode_soft_x24(void); +void set_mode_hard_x24(void); + +void set_start_pwm_x24(void); +void set_stop_pwm_x24(void); +//////////////// + + + +#endif /* XP_WRITE_TIME_H_ */ diff --git a/Inu/Src/main_matlab/IQmathLib.h b/Inu/Src/main_matlab/IQmathLib.h index 67bfcf2..4b20f9e 100644 --- a/Inu/Src/main_matlab/IQmathLib.h +++ b/Inu/Src/main_matlab/IQmathLib.h @@ -624,6 +624,8 @@ long exp_fixedN(long x, unsigned int n); #define _IQ18div(A,B) divideN(A,B,18) #define _IQsin(A) sin_fixed(A) #define _IQcos(A) cos_fixed(A) +#define _IQsinPU(A) sin_fixed(A) +#define _IQcosPU(A) cos_fixed(A) #define _IQsqrt(A) sqrt_fixed(A) #define _IQexp(A) exp_fixed(A) #define _IQ18exp(A) exp_fixedN(A,18) diff --git a/Inu/Src/main_matlab/main_matlab.c b/Inu/Src/main_matlab/main_matlab.c index 5bd97c3..0bb5ff0 100644 --- a/Inu/Src/main_matlab/main_matlab.c +++ b/Inu/Src/main_matlab/main_matlab.c @@ -1,39 +1,21 @@ - #include "DSP281x_Device.h" +#include "edrk_main.h" #include "vector.h" -#include "v_rotor.h" -//#include "xp_rotation_sensor.h" -#include "log_to_mem.h" -#include "main_matlab.h" +#include "vector_control.h" + #include "xp_project.h" - -// #define PROJECT_DEFAULTS2 { -// (void (*)(Uint32))project_read_all_pbus2 \ -// } -// typedef struct TS_project{ -// void (*read_all_pbus)(); -// } T_project2; - +#include "xp_write_xpwm_time.h" +#include "edrk_main.h" +#include "vector.h" +#include "vector_control.h" T_project project = {0}; -#pragma DATA_SECTION(modbus_table_in,".logs"); -MODBUS_REG_STRUCT modbus_table_in[1024]; - -#pragma DATA_SECTION(modbus_table_out,".logs"); -MODBUS_REG_STRUCT modbus_table_out[1024]; - -FLAG f; WINDING a; EDRK edrk = EDRK_DEFAULT; - -//T_rotation_sensor rotation_sensor = T_CDS_ROTATION_SENSOR_DEFAULTS; -int Unites[128][256]; - - -_iq temperature_limit_koeff = _IQ(1.0); +FLAG f = FLAG_DEFAULTS; void project_read_all_pbus2() @@ -41,11 +23,6 @@ void project_read_all_pbus2() } -#pragma DATA_SECTION(logpar, ".fast_vars1"); -LOGSPARAMS logpar = LOGSPARAMS_DEFAULTS; -int LOAG[10]; -float logpar_matlab[50]; - #pragma DATA_SECTION(break_result_1,".fast_vars"); _iq break_result_1 = 0; @@ -136,15 +113,18 @@ int xerror(unsigned int er_ID, void* CallBackRef) }; unsigned int ReadMemory(unsigned long addr) { - return (*(volatile int *)(addr)); + //return (*(volatile int *)(addr)); + return 0; } void WriteMemory(unsigned long addr, unsigned int data) { - (*(volatile int *)( addr )) = data; + //(*(volatile int *)( addr )) = data; } + + void start_pwm(void) { // mPWM_a = 1; @@ -170,6 +150,10 @@ void stop_break_pwm() { } +void stop_wdog() { + +} + void start_pwm_b() { } diff --git a/Inu/Src/main_matlab/adc_tools.h b/Inu/Src/main_matlab/old/adc_tools.h similarity index 100% rename from Inu/Src/main_matlab/adc_tools.h rename to Inu/Src/main_matlab/old/adc_tools.h diff --git a/Inu/Src/main_matlab/adc_tools_matlab.c b/Inu/Src/main_matlab/old/adc_tools_matlab.c similarity index 100% rename from Inu/Src/main_matlab/adc_tools_matlab.c rename to Inu/Src/main_matlab/old/adc_tools_matlab.c diff --git a/Inu/Src/main_matlab/errors_matlab.c b/Inu/Src/main_matlab/old/errors_matlab.c similarity index 100% rename from Inu/Src/main_matlab/errors_matlab.c rename to Inu/Src/main_matlab/old/errors_matlab.c diff --git a/Inu/Src/main_matlab/io_verbal_names.h b/Inu/Src/main_matlab/old/io_verbal_names.h similarity index 100% rename from Inu/Src/main_matlab/io_verbal_names.h rename to Inu/Src/main_matlab/old/io_verbal_names.h diff --git a/Inu/Src/main_matlab/rotation_speed_matlab.c b/Inu/Src/main_matlab/old/rotation_speed_matlab.c similarity index 100% rename from Inu/Src/main_matlab/rotation_speed_matlab.c rename to Inu/Src/main_matlab/old/rotation_speed_matlab.c diff --git a/Inu/Src/main_matlab/v_pwm24_matlab.c b/Inu/Src/main_matlab/old/v_pwm24_matlab.c similarity index 100% rename from Inu/Src/main_matlab/v_pwm24_matlab.c rename to Inu/Src/main_matlab/old/v_pwm24_matlab.c diff --git a/Inu/Src/main_matlab/xp_write_xpwm_time_matlab.c b/Inu/Src/main_matlab/old/xp_write_xpwm_time_matlab.c similarity index 100% rename from Inu/Src/main_matlab/xp_write_xpwm_time_matlab.c rename to Inu/Src/main_matlab/old/xp_write_xpwm_time_matlab.c diff --git a/Inu/Src2/551/VectorControl/abc_to_alphabeta.c b/Inu/Src2/551/VectorControl/abc_to_alphabeta.c new file mode 100644 index 0000000..e0ea922 --- /dev/null +++ b/Inu/Src2/551/VectorControl/abc_to_alphabeta.c @@ -0,0 +1,23 @@ +#include "IQmathLib.h" // Include header for IQmath library +#include "abc_to_alphabeta.h" + + + + +///////////////////////////////////////////////// + + +#pragma CODE_SECTION(abc_to_alphabeta_calc,".fast_run"); +void abc_to_alphabeta_calc(ABC_TO_ALPHABETA *v) +{ + static _iq iq_1_sqrt3 = _IQ(0.57735026918962576450914878050196); // = 1/sqrt(3) + static _iq iq_2_sqrt3 = _IQ(1.1547005383792515290182975610039); // =2/sqrt(3) + + v->Ualpha = v->Ua; + v->Ubeta = _IQmpy(iq_1_sqrt3,v->Ua) + _IQmpy(iq_2_sqrt3,v->Ub); + +} + + + +///////////////////////////////////////////////// diff --git a/Inu/Src2/551/VectorControl/abc_to_alphabeta.h b/Inu/Src2/551/VectorControl/abc_to_alphabeta.h new file mode 100644 index 0000000..8d3f23b --- /dev/null +++ b/Inu/Src2/551/VectorControl/abc_to_alphabeta.h @@ -0,0 +1,39 @@ +#ifndef __ABC_ALPHABETA_H__ +#define __ABC_ALPHABETA_H__ + + + +typedef struct { _iq Ua; //phase A voltage, input + _iq Ub; //phase B voltage, input + _iq Uc; //phase C voltage, input +// _iq Tetta; //phase angle, input + _iq Ualpha; // axis d voltage, output + _iq Ubeta; // axis q voltage, output + void (*calc)(); // Pointer to calculation function + }ABC_TO_ALPHABETA; + + + + + +typedef ABC_TO_ALPHABETA *ABC_TO_ALPHABETA_handle; + +#define ABC_TO_ALPHABETA_DEFAULTS { 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + (void (*)(unsigned long))abc_to_alphabeta_calc\ + } + + +void abc_to_alphabeta_calc(ABC_TO_ALPHABETA_handle); + + + + + + + + +#endif // end __ABC_ALPHABETA_H diff --git a/Inu/Src2/551/VectorControl/abc_to_dq.c b/Inu/Src2/551/VectorControl/abc_to_dq.c new file mode 100644 index 0000000..8044f2c --- /dev/null +++ b/Inu/Src2/551/VectorControl/abc_to_dq.c @@ -0,0 +1,39 @@ +#include "IQmathLib.h" // Include header for IQmath library +#include "abc_to_dq.h" + + + + + + + + + +///////////////////////////////////////////////// + + +#pragma CODE_SECTION(abc_to_dq_calc,".fast_run"); +void abc_to_dq_calc(ABC_TO_DQ *v) +{ + static _iq iq_two_third_pi = _IQ(6.283185307179586476925286766559/3.0); + static _iq iq_two_third = _IQ(2.0/3.0); + + v->Id = _IQmpy(iq_two_third,_IQmpy(v->Ia, _IQsin(v->Tetta)) + _IQmpy(v->Ib, _IQsin(v->Tetta - iq_two_third_pi)) + _IQmpy(v->Ic, _IQsin(v->Tetta + iq_two_third_pi))); + v->Iq = _IQmpy(iq_two_third,_IQmpy(v->Ia, _IQcos(v->Tetta)) + _IQmpy(v->Ib, _IQcos(v->Tetta - iq_two_third_pi)) + _IQmpy(v->Ic, _IQcos(v->Tetta + iq_two_third_pi))); +} + + +#pragma CODE_SECTION(abc_to_dq_calc_v2,".fast_run"); +void abc_to_dq_calc_v2(ABC_TO_DQ *v) +{ + static _iq iq_two_third_pi = _IQ(6.283185307179586476925286766559/3.0); + static _iq iq_two_third = _IQ(2.0/3.0); + + v->Id = _IQmpy(iq_two_third,_IQmpy(v->Ia, _IQcos(v->Tetta)) + _IQmpy(v->Ib, _IQcos(v->Tetta - iq_two_third_pi)) + _IQmpy(v->Ic, _IQcos(v->Tetta + iq_two_third_pi))); + v->Iq = _IQmpy(iq_two_third,_IQmpy(-v->Ia, _IQsin(v->Tetta)) - _IQmpy(v->Ib, _IQcos(v->Tetta - iq_two_third_pi)) - _IQmpy(v->Ic, _IQcos(v->Tetta + iq_two_third_pi))); +} + + +///////////////////////////////////////////////// + + diff --git a/Inu/Src2/551/VectorControl/abc_to_dq.h b/Inu/Src2/551/VectorControl/abc_to_dq.h new file mode 100644 index 0000000..57e3de6 --- /dev/null +++ b/Inu/Src2/551/VectorControl/abc_to_dq.h @@ -0,0 +1,42 @@ +#ifndef __ABC_DQ_H__ +#define __ABC_DQ_H__ + + + +typedef struct { _iq Ia; //phase A voltage, input + _iq Ib; //phase B voltage, input + _iq Ic; //phase C voltage, input + _iq Tetta; //phase angle, input + _iq Id; // axis d voltage, output + _iq Iq; // axis q voltage, output + void (*calc)(); // Pointer to calculation function + void (*calc_v2)(); // Pointer to calculation function + }ABC_TO_DQ; + + + + + +typedef ABC_TO_DQ *ABC_TO_DQ_handle; + +#define ABC_TO_DQ_DEFAULTS { 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + (void (*)(Uint32))abc_to_dq_calc, \ + (void (*)(Uint32))abc_to_dq_calc_v2 } + + +void abc_to_dq_calc(ABC_TO_DQ_handle); +void abc_to_dq_calc_v2(ABC_TO_DQ_handle); + + + + + + + + +#endif // end __ABC_DQ_H diff --git a/Inu/Src2/551/VectorControl/alg_pll.c b/Inu/Src2/551/VectorControl/alg_pll.c new file mode 100644 index 0000000..b7f3a9c --- /dev/null +++ b/Inu/Src2/551/VectorControl/alg_pll.c @@ -0,0 +1,577 @@ +#include "IQmathLib.h" +#include "alg_pll.h" +#include "params_pll.h" + +#include "params_norma.h" + +//#define NORMA_ACP 3000 +//#define FREQ_PWM_VIPR 1975 + +//#define SIZE_PLL_AVG 50 + +//_iq w_in_avg[SIZE_PLL_AVG]; +//_iq w_out_avg[SIZE_PLL_AVG]; + +#define DETECT_PLL_D (2000.0/NORMA_ACP) // ampl +#define DETECT_PLL_Q (500.0/NORMA_ACP) // zero + +_iq iqDetect_PLL_d=_IQ(DETECT_PLL_D); +_iq iqDetect_PLL_q=_IQ(DETECT_PLL_Q); + +#define MAX_COUNT_ERR_PLL 5000 //20 + +#ifdef USE_SMOOTH_FOR_CALC_WC +SMOOTH mysmooth=SMOOTH_DEFAULTS; +#endif + + +// +/////////////////////////////////////////// +//PLL_REC pll2 = PLL_REC_DEFAULT; +/////////////////////////////////////////// + + +ABC_TO_ALPHABETA abc_to_alphabeta_u_input = ABC_TO_ALPHABETA_DEFAULTS; +ALPHABETA_TO_DQ alphabeta_to_dq_u_input = ALPHABETA_TO_DQ_DEFAULTS; +PIDREG3 pidUdq = PIDREG3_DEFAULTS; + +//int count_wait_pll=0; +int count_err_pll = 0; + + +//int c_start=0; +//int c_stop=0; + +#define MAX_TIME_WAIT_PLL 5000 + + +//_iq iqUab=0, iqUbc=0, iqUca=0; + + +//_iq koef_Um_filter = _IQ(0.000125/0.09); + + +//_iq koef_AddIq_minus_1_filter = _IQ(0.00034/0.009);//9576244354248046875 + +#pragma CODE_SECTION(minus_plus_2_pi,".fast_run"); +_iq minus_plus_2_pi(_iq a) +{ + + while (a>=CONST_IQ_2PI) + a -= CONST_IQ_2PI; + + while (a<=-CONST_IQ_2PI) + a += CONST_IQ_2PI; + + return a; +} + + +#pragma CODE_SECTION(minus_plus_2_pi_v2,".fast_run"); +_iq minus_plus_2_pi_v2(_iq a) +{ + + while (a>=CONST_IQ_2PI) + a -= CONST_IQ_2PI; + + while (a<0) + a += CONST_IQ_2PI; + + return a; +} + + + +#pragma CODE_SECTION(AB_BC_CA_To_ABC,".fast_run"); +void AB_BC_CA_To_ABC(_iq U_AB, _iq U_BC, _iq U_CA, _iq *Ua, _iq *Ub, _iq *Uc) +{ +// static _iq c2 = _IQ(2.0); + +// static _iq c13_sqrt = _IQ(1.7320508075688772935274463415059 / 3.0); + + *Ua = U_AB; + *Ub = U_BC; + *Uc = U_CA; +/* + + + *Ua = _IQmpy(c13_sqrt, (_IQmpy(c2,U_AB)+U_BC));// 2*U_AB/3+U_BC/3; + *Ub = _IQmpy(c13_sqrt, (_IQmpy(c2,U_BC)+U_CA));// 2*U_BC/3+U_CA/3; + *Uc = _IQmpy(c13_sqrt, (_IQmpy(c2,U_CA)+U_AB));// 2*U_CA/3+U_AB/3; +*/ +} + + + + +///////////////////////////////////////////////// +#pragma CODE_SECTION(PLLController,".fast_run"); +///////////////////////////////////////////////// +void PLLController(PLL_REC *v) +{ + static unsigned int count_wait_pll=0; + static _iq prev_Tetta_z=0; + _iq Tetta_z_t=0; + static int prev_flag_find_pll = 0; + static int flag_reset_Tetta_p = 0; +// static _iq prev_Tetta_v2 = 0; + + + v->vars.Uab = v->input.Input_U_AB - v->vars.iqZeroUAB; + v->vars.Ubc = v->input.Input_U_BC - v->vars.iqZeroUBC; + v->vars.Uca = v->input.Input_U_CA - v->vars.iqZeroUCA; + + v->vars.sum_zeroU_AB_BC_CA = v->vars.Uab + v->vars.Ubc + v->vars.Uca; + + if (v->setup.rotation_u_cba) + { + AB_BC_CA_To_ABC(v->vars.Uab, v->vars.Uca, v->vars.Ubc, &v->vars.Ua, &v->vars.Ub, &v->vars.Uc); + } + else + { + AB_BC_CA_To_ABC(v->vars.Uab,v->vars.Ubc,v->vars.Uca, &v->vars.Ua, &v->vars.Ub, &v->vars.Uc); + } +#ifdef ROTATION_U_CBA + +#else + +#endif + + v->vars.sum_zeroU_A_B_C = v->vars.Ua + v->vars.Ub + v->vars.Uc; + + abc_to_alphabeta_u_input.Ua = v->vars.Ua; + abc_to_alphabeta_u_input.Ub = v->vars.Ub; + abc_to_alphabeta_u_input.Uc = v->vars.Uc; + + abc_to_alphabeta_u_input.calc(&abc_to_alphabeta_u_input); + + + v->vars.Ualpha = abc_to_alphabeta_u_input.Ualpha; + v->vars.Ubeta = abc_to_alphabeta_u_input.Ubeta; + + + alphabeta_to_dq_u_input.Ualpha = v->vars.Ualpha; + alphabeta_to_dq_u_input.Ubeta = v->vars.Ubeta; + alphabeta_to_dq_u_input.Tetta = v->vars.Tetta; + + alphabeta_to_dq_u_input.calc(&alphabeta_to_dq_u_input); + + + v->vars.pll_Ud = alphabeta_to_dq_u_input.Ud; + v->vars.pll_Uq = alphabeta_to_dq_u_input.Uq; + + +// pidUdq.Fdb = v->pll_Ud;//.pll_Uq; //err = Ref - Fdb +// pidUdq.Ref = 0; + + pidUdq.Ref = v->vars.pll_Uq; //err = Ref - Fdb + pidUdq.Fdb = 0; + + pidUdq.calc(&pidUdq); + v->vars.wc = pidUdq.Out; + + + if (prev_flag_find_pll==0) + { + flag_reset_Tetta_p = 0; + } + + if (v->output.flag_find_pll) + { +#ifdef USE_SMOOTH_FOR_CALC_WC + mysmooth.input = _IQtoIQ23(v->vars.wc); + mysmooth.add(&mysmooth); + mysmooth.calc(&mysmooth); + v->vars.w_shtrih = _IQ23toIQ(mysmooth.av); +#else + v->vars.w_shtrih = v->vars.wc; +#endif + } + else + { + v->vars.w_shtrih = v->vars.wc; + } + + + v->vars.Tetta += v->vars.wc; + v->vars.Tetta = minus_plus_2_pi(v->vars.Tetta); // +- 2PI + + if (v->output.flag_find_pll) + { + v->vars.dwc = v->vars.wc - v->vars.w_shtrih; + + v->vars.Tetta_p += v->vars.dwc; + v->vars.Tetta_p = minus_plus_2_pi(v->vars.Tetta_p); // +- 2PI + + v->vars.dTetta = v->vars.Tetta - v->vars.Tetta_p;// + iq_05Pi; + + v->vars.dTetta = minus_plus_2_pi(v->vars.dTetta); // +- 2PI + + v->vars.Tetta_z = v->vars.dTetta; + +// if (v->Tetta_z>=iq_05Pi && prev_Tetta_zTetta_p = 0; + + Tetta_z_t = minus_plus_2_pi_v2(v->vars.Tetta_z); + + if ( (Tetta_z_t>=0) && (Tetta_z_t(CONST_IQ_2PI-CONST_IQ_PI05)) ) ) + { + if (flag_reset_Tetta_p==0) + { + v->vars.Tetta_p = 0; +// flag_reset_Tetta_p = 1; + } + } + + + prev_Tetta_z = Tetta_z_t; + +#ifdef USE_FILTER_TETTA +//use filter teta + v->vars.Tetta_v2 = v->vars.Tetta_z;//v->Tetta; +#else +//use mgnoven teta + v->vars.Tetta_v2 = v->vars.Tetta; +#endif + v->vars.delta_Tetta_c = v->vars.Tetta_z - v->vars.Tetta; + +// prev_Tetta_v2 = v->Tetta_v2; + + } + else + { + v->vars.Tetta_v2 = v->vars.Tetta; + flag_reset_Tetta_p = 0; + } + + +// PLL OK? +//count_wait_pll=0 +//new alg find pll + if (v->vars.w_shtrih >= v->vars.find_min_w_strih && v->vars.w_shtrih <= v->vars.find_max_w_strih) + { + if (v->vars.count_wait_pll_w_shtrih < v->vars.max_time_wait_pll_w_strih) + v->vars.count_wait_pll_w_shtrih++; + } + else + { + if (v->vars.count_wait_pll_w_shtrih>0) + v->vars.count_wait_pll_w_shtrih--; + } + + if (v->vars.count_wait_pll_w_shtrih == v->vars.max_time_wait_pll_w_strih) + v->output.flag_find_pll = 1; + + if (v->vars.count_wait_pll_w_shtrih == 0) + v->output.flag_find_pll = 0; + +//end new alg find pll + + + + if ( (_IQabs(v->vars.pll_Uq)<=_IQabs(iqDetect_PLL_q)) // zero + && (_IQabs(v->vars.pll_Ud)>=_IQabs(iqDetect_PLL_d) ) //ampl + ) + { + count_err_pll=0; + if (count_wait_plloutput.flag_find_pll = 1; + } + else + { + if (count_err_pll>=MAX_COUNT_ERR_PLL) + { + // fail find pll + count_wait_pll=0; + + v->output.flag_find_pll = 0; + + if (v->output.flag_find_pll==1) + { + v->vars.pll_Uq = 0; + v->vars.pll_Ud = 0; + } + + } + else + { + count_err_pll++; + if ((v->output.flag_find_pll==0) && (count_wait_pll>0)) + count_wait_pll--; + } + } + +// end PLL Ok? + + + v->vars.pi_teta_u_out = pidUdq.Out; + v->vars.pi_teta_u_i = pidUdq.Ui; + v->vars.pi_teta_u_p = pidUdq.Up; + + + prev_flag_find_pll = v->output.flag_find_pll; +} + +////////////////////////////////////////////////// +////////////////////////////////////////////////// +////////////////////////////////////////////////// +///////////////////////////////////////////////// +//#pragma CODE_SECTION(pll_get_freq,".fast_run"); +///////////////////////////////////////////////// +void pll_get_freq_float(PLL_REC *v) +{ + + if (v->output.flag_find_pll) + { + v->output.int_freq_net = _IQtoF( v->vars.w_shtrih) * v->setup.freq_run_pll / PI * 50.00; // freq*100 + } + else + { + v->output.int_freq_net = 0; + } + +} + +////////////////////////////////////////////////// +////////////////////////////////////////////////// +void pll_get_freq_iq(PLL_REC *v) +{ + + if (v->output.flag_find_pll) + { + v->output.iq_freq_net = v->vars.w_shtrih;//_IQtoF( v->vars.w_shtrih) * v->setup.freq_run_pll / PI * 50.00; // freq*100 + } + else + { + v->output.iq_freq_net = 0; + } + +} + +////////////////////////////////////////////////// +//#pragma CODE_SECTION(detect_phase_count,".fast_run"); +void detect_phase_count(PLL_REC *v) +{ + static _iq prev_Ua = 0; + static int prev_flag_find_pll=0; + + + +// abc_to_dq.Ua + + if ((v->output.flag_find_pll != prev_flag_find_pll) && (v->output.flag_find_pll == 1)) + { + prev_Ua = v->vars.Ua; + v->vars.enable_detect_phase_count = 1; + v->vars.error_phase_count = 0; + } + + + if (v->output.flag_find_pll==0) + v->vars.enable_detect_phase_count = 0; + + + if (v->output.flag_find_pll) + { + if (v->vars.enable_detect_phase_count) + { + if ( (prev_Ua<0) && (v->vars.Ua>=0) ) + { + + if (v->vars.Uc > v->vars.Ub) + v->vars.enable_detect_phase_count = 0; + + if (v->vars.Ub > v->vars.Uc) + { + v->vars.enable_detect_phase_count = 0; + v->vars.error_phase_count = 1; + } + } + } + } + + + prev_flag_find_pll = v->output.flag_find_pll; + prev_Ua = v->vars.Ua; + +} +///////////////////////////////////////////////// + + +//////////////////////////////////////////////// + +#pragma CODE_SECTION(Find_zero_Uabc,".fast_run"); +void Find_zero_Uabc(PLL_REC *v) +{ + static int c_a=0; +// static int c_b=0; +// static int c_c=0; + + static _iq sum_a=0; + static _iq sum_b=0; + static _iq sum_c=0; + + _iq22 sum_t,c_t; + + _iq22 sum_div; + + +// AB_BC_CA_To_ABC(analog.iqUin_AB-iqZeroUABC, analog.iqUin_BC-iqZeroUABC, analog.iqUin_CA-iqZeroUABC); + + + sum_a += v->input.Input_U_AB; // analog.iqUin_AB; + sum_b += v->input.Input_U_BC; // analog.iqUin_BC; + sum_c += v->input.Input_U_CA; // analog.iqUin_CA; + + c_a++; + + if (c_a >= v->vars.count_sum_find_zero_uabc) + { + sum_div = v->vars.sum_div_find_zero_uabc; + + sum_t = _IQtoIQ22(sum_a); + c_t = _IQ22div(sum_t,sum_div); + v->vars.iqZeroUAB = _IQ22toIQ(c_t); + + sum_t = _IQtoIQ22(sum_b); + c_t = _IQ22div(sum_t,sum_div); + v->vars.iqZeroUBC = _IQ22toIQ(c_t); + + sum_t = _IQtoIQ22(sum_c); + c_t = _IQ22div(sum_t,sum_div); + v->vars.iqZeroUCA = _IQ22toIQ(c_t); + + sum_a = 0; + sum_b = 0; + sum_c = 0; + c_a = 0; + } + +} + + + + + +void pll_init(PLL_REC *v) +{ + v->output.status = STATUS_PLL_NOT_INITED; + + abc_to_alphabeta_u_input.Ua = 0; + abc_to_alphabeta_u_input.Ub = 0; + abc_to_alphabeta_u_input.Uc = 0; + abc_to_alphabeta_u_input.Ualpha = 0; + abc_to_alphabeta_u_input.Ubeta = 0; + + alphabeta_to_dq_u_input.Tetta = 0; + alphabeta_to_dq_u_input.Ualpha = 0; + alphabeta_to_dq_u_input.Ubeta = 0; + alphabeta_to_dq_u_input.Ud = 0; + alphabeta_to_dq_u_input.Uq = 0; + + v->vars.count_wait_pll_w_shtrih = 0; + + v->vars.pll_Ud = 0; + v->vars.pll_Uq = 0; + v->vars.Tetta = 0; + v->vars.Tetta_p = 0; + + v->vars.Ua = 0; + v->vars.Ub = 0; + v->vars.Uc = 0; + + v->vars.Ualpha = 0; + v->vars.Ubeta = 0; + +// count_wait_pll = 0; + count_err_pll = 0; + v->output.flag_find_pll = 0; + + pidUdq.Kp = _IQ(v->setup.pid_kp_pll); + pidUdq.Ki = _IQ(v->setup.pid_ki_pll); + + pidUdq.Kc = _IQ(PID_KC_PLL); + pidUdq.Kd = _IQ(0.0); + + pidUdq.OutMax = _IQ(K_PLL_MAX); + pidUdq.OutMin = _IQ(K_PLL_MIN); + + pidUdq.Err = 0; + pidUdq.Out = 0; + pidUdq.OutPreSat = 0; + pidUdq.SatErr = 0; + + if (v->setup.freq_run_pll == 0) + v->setup.freq_run_pll = DEFAULT_FREQ_RUN_PLL; + + pidUdq.Ui = _IQ(2.0*PI*DEFAULT_FREQ_NET/(v->setup.freq_run_pll)); + +// iqDetect_PLL_d = iqDetect_PLL_d; +// iqDetect_PLL_q = iqDetect_PLL_q; + +#ifdef USE_SMOOTH_FOR_CALC_WC + mysmooth.init(&mysmooth); +#endif + + + v->vars.count_sum_find_zero_uabc = v->setup.freq_run_pll/DEFAULT_FREQ_NET; //79*2 //1975/50*2 + v->vars.sum_div_find_zero_uabc = _IQ22(v->vars.count_sum_find_zero_uabc); + + v->vars.find_max_w_strih = _IQ(FIND_MAX_W_STRIH*2.0*PI*DEFAULT_FREQ_NET/(v->setup.freq_run_pll)); + v->vars.find_min_w_strih = _IQ(FIND_MIN_W_STRIH*2.0*PI*DEFAULT_FREQ_NET/(v->setup.freq_run_pll)); + + v->vars.max_time_wait_pll_w_strih = (v->vars.count_sum_find_zero_uabc * MAX_PERIOD_WAIT_PLL_W_SHTRIH); + + v->output.status = STATUS_PLL_INITED; + +} + + + + +#pragma CODE_SECTION(read_error_find_pll,".fast_run2"); +int read_error_find_pll(PLL_REC *v) +{ +// static int enable_detect_pll_err=0; +// static int prev_flag_find_pll=0; + static int err_pll=0; + + + err_pll = 0; +/* + if ((v->output.flag_find_pll!=prev_flag_find_pll) + && (v->output.flag_find_pll==1)) + { + enable_detect_pll_err = 1; + } + prev_flag_find_pll = v->output.flag_find_pll; + + if (v->input.enable_find_pll==0) + enable_detect_pll_err = 0; + + if ((enable_detect_pll_err) && (v->output.flag_find_pll==0) && (v->input.enable_find_pll==1)) + { + err_pll = 1; + } +*/ + return err_pll; +} + + + + +#pragma CODE_SECTION(pll_calc,".fast_run"); +void pll_calc(PLL_REC *v) +{ + if (v->output.status >= STATUS_PLL_INITED) + { + Find_zero_Uabc(v); + PLLController(v); +// detect_phase_count(v); + v->output.status = STATUS_PLL_OK; + } + +} diff --git a/Inu/Src2/551/VectorControl/alg_pll.h b/Inu/Src2/551/VectorControl/alg_pll.h new file mode 100644 index 0000000..0a63dde --- /dev/null +++ b/Inu/Src2/551/VectorControl/alg_pll.h @@ -0,0 +1,188 @@ +#ifndef __ALG_PLL_H__ +#define __ALG_PLL_H__ + +#include "IQmathLib.h" +#include "math_pi.h" +#include "pid_reg3.h" +#include "abc_to_alphabeta.h" +#include "alphabeta_to_dq.h" +#include "smooth.h" +#include "smooth.h" + + +#define DEFAULT_FREQ_NET 50.00 // Hz + +#define DEFAULT_FREQ_RUN_PLL 4000 // Hz + +#define DEFAULT_PID_KP_PLL 0.0375 +#define DEFAULT_PID_KI_PLL 0.0128 + +#define STATUS_PLL_OK 10 + +#define STATUS_PLL_ERROR 2 +#define STATUS_PLL_INITED 1 +#define STATUS_PLL_NOT_INITED 0 + +#define FIND_MAX_W_STRIH 1.5 //0.12 //75Hz +#define FIND_MIN_W_STRIH 0.5 //0.045 //33Hz + +#define MAX_PERIOD_WAIT_PLL_W_SHTRIH 3 + + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// + +typedef struct { + float pid_kp_pll; // . Kp + float pid_ki_pll; // . Ki + int freq_run_pll; // , . + int rotation_u_cba; // : 0 - A-B-C, 1 - A-C-B + } PLL_SETUP; + +#define PLL_SETUP_DEFAULT {DEFAULT_PID_KP_PLL, DEFAULT_PID_KI_PLL, DEFAULT_FREQ_RUN_PLL,0} + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// + +typedef struct { _iq Input_U_AB; // Uab + _iq Input_U_BC; // Ubc + _iq Input_U_CA; // Uca + } PLL_INPUT; + +#define PLL_INPUT_DEFAULT {0, 0, 0} + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// + +typedef struct { int flag_find_pll; + int int_freq_net; + _iq iq_freq_net; + int status; + } PLL_OUTPUT; + +#define PLL_OUTPUT_DEFAULT {0, 0, 0, STATUS_PLL_NOT_INITED} + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// + +typedef struct { + int enable_detect_phase_count; + int error_phase_count; + + _iq pll_Ud; + _iq pll_Uq; + _iq Tetta; + _iq Tetta_v2; + + _iq wc; + _iq dwc; + _iq w_shtrih; + + _iq Tetta_z; + _iq Tetta_p; + _iq dTetta; + + _iq zeroPLL; + _iq pi_teta_u_out; + _iq pi_teta_u_p; + _iq pi_teta_u_i; + _iq add_teta; + _iq add_teta2; + + _iq Ua; + _iq Ub; + _iq Uc; + + + _iq Uab; + _iq Ubc; + _iq Uca; + + _iq Ualpha; + _iq Ubeta; + + _iq iqZeroUAB; + _iq iqZeroUBC; + _iq iqZeroUCA; + + _iq sum_zeroU_AB_BC_CA; + _iq sum_zeroU_A_B_C; + + _iq delta_Tetta_c; + _iq22 sum_div_find_zero_uabc; + int count_sum_find_zero_uabc; + + _iq find_max_w_strih; + _iq find_min_w_strih; + + int count_wait_pll_w_shtrih; + int max_time_wait_pll_w_strih;//MAX_TIME_WAIT_PLL_W_SHTRIH + + int enable_find_pll; + + + }PLL_VARS;//39 + +#define PLL_VARS_DEFAULT {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} + + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// + +typedef struct { PLL_INPUT input; + PLL_OUTPUT output; + PLL_SETUP setup; + PLL_VARS vars; + void (*init)(); // Pointer to calculation function + void (*calc_pll)(); // Pointer to calculation function + void (*get_freq_float)(); // Pointer to calculation function + void (*get_freq_iq)(); + }PLL_REC; + +typedef PLL_REC *PLL_REC_handle; + +#define PLL_REC_DEFAULT {\ + PLL_INPUT_DEFAULT,\ + PLL_OUTPUT_DEFAULT,\ + PLL_SETUP_DEFAULT,\ + PLL_VARS_DEFAULT,\ + (void (*)(unsigned long))pll_init,\ + (void (*)(unsigned long))pll_calc,\ + (void (*)(unsigned long))pll_get_freq_float,\ + (void (*)(unsigned long))pll_get_freq_iq \ + } + +void pll_init(PLL_REC_handle); +void pll_calc(PLL_REC_handle); +void pll_get_freq_float(PLL_REC_handle); +void pll_get_freq_iq(PLL_REC_handle); + +void Find_zero_Uabc(PLL_REC_handle); +void PLLController(PLL_REC *v); +void AB_BC_CA_To_ABC(_iq U_AB, _iq U_BC, _iq U_CA, _iq *Ua, _iq *Ub, _iq *Uc); +void detect_phase_count(PLL_REC *v); +int read_error_find_pll(PLL_REC *v); + + + +_iq minus_plus_2_pi(_iq a); +_iq minus_plus_2_pi_v2(_iq a); + + + + + + + +#endif + + + + + + diff --git a/Inu/Src2/551/VectorControl/alphabeta_to_dq.c b/Inu/Src2/551/VectorControl/alphabeta_to_dq.c new file mode 100644 index 0000000..ffa5a73 --- /dev/null +++ b/Inu/Src2/551/VectorControl/alphabeta_to_dq.c @@ -0,0 +1,24 @@ +#include "IQmathLib.h" // Include header for IQmath library + +#include "alphabeta_to_dq.h" + + + + + + + + + +///////////////////////////////////////////////// + + +#pragma CODE_SECTION(alphabeta_to_dq_calc,".fast_run"); +void alphabeta_to_dq_calc(ALPHABETA_TO_DQ *v) +{ + + v->Ud = _IQmpy(v->Ualpha, _IQcos(v->Tetta)) + _IQmpy(v->Ubeta, _IQsin(v->Tetta)); + v->Uq = -_IQmpy(v->Ualpha, _IQsin(v->Tetta)) + _IQmpy(v->Ubeta, _IQcos(v->Tetta)); + +} +///////////////////////////////////////////////// diff --git a/Inu/Src2/551/VectorControl/alphabeta_to_dq.h b/Inu/Src2/551/VectorControl/alphabeta_to_dq.h new file mode 100644 index 0000000..8484e14 --- /dev/null +++ b/Inu/Src2/551/VectorControl/alphabeta_to_dq.h @@ -0,0 +1,32 @@ +#ifndef __ALPHABETA_DQ_H__ +#define __ALPHABETA_DQ_H__ + + + +typedef struct { _iq Ualpha; //phase A voltage, input + _iq Ubeta; //phase B voltage, input + _iq Tetta; //phase angle, input + _iq Ud; // axis d voltage, output + _iq Uq; // axis q voltage, output + void (*calc)(); // Pointer to calculation function + }ALPHABETA_TO_DQ; + + + + + +typedef ALPHABETA_TO_DQ *ALPHABETA_TO_DQ_handle; + +#define ALPHABETA_TO_DQ_DEFAULTS { 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + (void (*)(unsigned long))alphabeta_to_dq_calc \ + } + + +void alphabeta_to_dq_calc(ALPHABETA_TO_DQ_handle); + + +#endif // end __ALPHABETA_DQ_H diff --git a/Inu/Src2/551/VectorControl/dq_to_alphabeta_cos.c b/Inu/Src2/551/VectorControl/dq_to_alphabeta_cos.c new file mode 100644 index 0000000..d075df4 --- /dev/null +++ b/Inu/Src2/551/VectorControl/dq_to_alphabeta_cos.c @@ -0,0 +1,39 @@ +#include "IQmathLib.h" // Include header for IQmath library +#include "dq_to_alphabeta_cos.h" + + + + + + +///////////////////////////////////////////////// + + +//#pragma CODE_SECTION(dq_to_alphabeta_calc,".fast_run2"); +void dq_to_alphabeta_calc(DQ_TO_ALPHABETA_handle v) +{ + + v->Ualpha = _IQmpy(v->Ud, _IQcos(v->Tetta)) + _IQmpy(v->Uq, _IQsin(v->Tetta)); + v->Ubeta = -_IQmpy(v->Ud, _IQsin(v->Tetta)) + _IQmpy(v->Uq, _IQcos(v->Tetta)); + +} + + +//#pragma CODE_SECTION(dq_to_alphabeta_calc2,".fast_run2"); +void dq_to_alphabeta_calc2(DQ_TO_ALPHABETA_handle v) +{ + + v->Ualpha = _IQmpy(v->Ud, _IQsin(v->Tetta)) + _IQmpy(v->Uq, _IQcos(v->Tetta)); + v->Ubeta = -_IQmpy(v->Ud, _IQcos(v->Tetta)) + _IQmpy(v->Uq, _IQsin(v->Tetta)); + +} + +//#pragma CODE_SECTION(dq_to_alphabeta_calc_cos,".fast_run2"); +void dq_to_alphabeta_calc_cos(DQ_TO_ALPHABETA_handle v) +{ + + v->Ualpha = _IQmpy(v->Ud, _IQcos(v->Tetta)) - _IQmpy(v->Uq, _IQsin(v->Tetta)); + v->Ubeta = _IQmpy(v->Ud, _IQsin(v->Tetta)) + _IQmpy(v->Uq, _IQcos(v->Tetta)); + +} +///////////////////////////////////////////////// diff --git a/Inu/Src2/551/VectorControl/dq_to_alphabeta_cos.h b/Inu/Src2/551/VectorControl/dq_to_alphabeta_cos.h new file mode 100644 index 0000000..b261ced --- /dev/null +++ b/Inu/Src2/551/VectorControl/dq_to_alphabeta_cos.h @@ -0,0 +1,40 @@ + + + +#ifndef __DQ_ALPHABETA_H__ +#define __DQ_ALPHABETA_H__ + +#include "IQmathLib.h" + +typedef struct { _iq Ualpha; //phase A voltage, input + _iq Ubeta; //phase B voltage, input + _iq Tetta; //phase angle, input + _iq Ud; // axis d voltage, output + _iq Uq; // axis q voltage, output + void (*calc)(); // Pointer to calculation function + void (*calc2)(); // Pointer to calculation function. Like in MATLAB + void (*calc_cos)(); // Pointer to calculation function, Ualpha = Uq*Cos(Tetta) + }DQ_TO_ALPHABETA; + + + + + +typedef DQ_TO_ALPHABETA *DQ_TO_ALPHABETA_handle; + +#define DQ_TO_ALPHABETA_DEFAULTS { 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + (void (*)(Uint32))dq_to_alphabeta_calc, \ + (void (*)(Uint32))dq_to_alphabeta_calc2, \ + (void (*)(Uint32))dq_to_alphabeta_calc_cos \ + } + + +void dq_to_alphabeta_calc(DQ_TO_ALPHABETA_handle); +void dq_to_alphabeta_calc2(DQ_TO_ALPHABETA_handle); +void dq_to_alphabeta_calc_cos(DQ_TO_ALPHABETA_handle); + +#endif // end __DQ_ALPHABETA_H__ diff --git a/Inu/Src2/551/VectorControl/params_pll.h b/Inu/Src2/551/VectorControl/params_pll.h new file mode 100644 index 0000000..2ec9466 --- /dev/null +++ b/Inu/Src2/551/VectorControl/params_pll.h @@ -0,0 +1,41 @@ +#ifndef __PARAMS_PLL_H__ +#define __PARAMS_PLL_H__ + + +//#define USE_SMOOTH_FOR_CALC_WC 1 // . + + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +// stend params +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +//////////// +//PLL +/////////// + +//23470 params +//#define PID_KP_PLL 0.00375 +//#define PID_KI_PLL 0.128 + +//ship1 +#define DEFAULT_PID_KP_PLL 0.0375 +#define DEFAULT_PID_KI_PLL 0.0128 + + +// + +#define PID_KC_PLL 1.000 //0.16 //0.05 //0.1 //20 //200 +// +#define K_PLL_MAX 10.0 //1000000 +#define K_PLL_MIN -10.0 //-1000000 +// + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +// end params +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + +#endif + diff --git a/Inu/Src2/551/VectorControl/regul_power.c b/Inu/Src2/551/VectorControl/regul_power.c new file mode 100644 index 0000000..d78f216 --- /dev/null +++ b/Inu/Src2/551/VectorControl/regul_power.c @@ -0,0 +1,88 @@ +/* + * regul_power.c + * + * Created on: 16 . 2020 . + * Author: star + */ +#include "IQmathLib.h" +#include "regul_power.h" + +#include +#include +#include +#include +#include +#include "math.h" + +#include "mathlib.h" + +#define TIME_RMP_SLOW 20.0 //sec +#define TIME_RMP_FAST 20.0 //sec + +POWER power = POWER_DEFAULTS; + +void init_Pvect(void) { + power.pidP.Ref = 0; + power.pidP.Kp = _IQ(1); + power.pidP.Ki = _IQ(0.1); + power.pidP.Kc = _IQ(0.5); + power.pidP.OutMax = _IQ(MOTOR_CURRENT_MAX / 2.0 / NORMA_ACP); + power.pidP.OutMin = -_IQ(MOTOR_CURRENT_MAX / 2.0 / NORMA_ACP); + + power.Pzad_rmp = 0; + power.koef_fast = _IQ(FROT_NOMINAL / (float)NORMA_FROTOR / TIME_RMP_FAST / (float)FREQ_PWM); + power.koef_slow = _IQ(FROT_NOMINAL / (float)NORMA_FROTOR / TIME_RMP_SLOW / (float)FREQ_PWM); + power.Iq_out_max = _IQ(MOTOR_CURRENT_MAX / 2.0 / NORMA_ACP); + power.Pnominal = _IQ(P_NOMINAL * 1000.0 / NORMA_ACP / NORMA_ACP); +} + +#pragma CODE_SECTION(vector_power,".fast_run"); +_iq vector_power(_iq Pzad, _iq P_measured, int n_alg, unsigned int master, + _iq Iq_measured, _iq Iq_limit, _iq *Iq_zad, int reset) +{ + static int prev_n_alg = 0; + _iq Iq_out = 0; + _iq koef_rmp = 0; + if (n_alg != ALG_MODE_FOC_POWER || !edrk.Go || master != MODE_MASTER || reset) { + power.pidP.Ui = Iq_measured; + power.pidP.Out = Iq_measured; + if (reset) { power.Pzad_rmp = 0; } + } + if (n_alg == ALG_MODE_FOC_OBOROTS) { + Pzad = power.Pnominal; + } + if (master == MODE_SLAVE) { + power.Pzad_rmp = P_measured; + return *Iq_zad; + } + + // , + //.. + if (n_alg == ALG_MODE_FOC_POWER && prev_n_alg != ALG_MODE_FOC_POWER) { + power.Pzad_rmp = P_measured; + } + + if((_IQabs(power.Pzad_rmp) <= _IQabs(Pzad)) && + (((Pzad >= 0) && (power.Pzad_rmp >= 0)) || ((Pzad < 0) && (power.Pzad_rmp < 0)))) + { + koef_rmp = power.koef_slow; + } + else + { + koef_rmp = power.koef_fast; + } + power.Pzad_rmp = zad_intensiv_q(koef_rmp, koef_rmp, power.Pzad_rmp, Pzad); + + power.pidP.OutMax = Iq_limit; + power.pidP.OutMin = -Iq_limit; + power.pidP.Ref = power.Pzad_rmp; + power.pidP.Fdb = P_measured; + power.pidP.calc(&power.pidP); + Iq_out = power.pidP.Out; + Iq_out = _IQsat(Iq_out, Iq_limit, -Iq_limit); + *Iq_zad = Iq_out; + + prev_n_alg = n_alg; + + return Iq_out; +} diff --git a/Inu/Src2/551/VectorControl/regul_power.h b/Inu/Src2/551/VectorControl/regul_power.h new file mode 100644 index 0000000..80d3e06 --- /dev/null +++ b/Inu/Src2/551/VectorControl/regul_power.h @@ -0,0 +1,30 @@ +/* + * regul_power.h + * + * Created on: 16 . 2020 . + * Author: star + */ + +#ifndef SRC_VECTORCONTROL_NIO12_REGUL_POWER_H_ +#define SRC_VECTORCONTROL_NIO12_REGUL_POWER_H_ + +#include "pid_reg3.h" + +typedef struct { + PIDREG3 pidP; + _iq Pzad_rmp; + _iq koef_fast; + _iq koef_slow; + _iq Iq_out_max; + _iq Pnominal; +} POWER; + +#define POWER_DEFAULTS {PIDREG3_DEFAULTS, 0,0,0,0,0} + +_iq vector_power(_iq Pzad, _iq P_measured, int mode, unsigned int master, + _iq Iq_measured, _iq Iq_limit, _iq* Frot_zad, int reset); +void init_Pvect(void); + +extern POWER power; + +#endif /* SRC_VECTORCONTROL_NIO12_REGUL_POWER_H_ */ diff --git a/Inu/Src2/551/VectorControl/regul_turns.c b/Inu/Src2/551/VectorControl/regul_turns.c new file mode 100644 index 0000000..95ca611 --- /dev/null +++ b/Inu/Src2/551/VectorControl/regul_turns.c @@ -0,0 +1,143 @@ +#include "DSP281x_Device.h" +#include "IQmathLib.h" + +#include "regul_turns.h" + +#include +#include +#include +#include +#include +#include +#include +#include "math.h" +#include "mathlib.h" +#include "pid_reg3.h" +#include "vector_control.h" + +#pragma DATA_SECTION(turns,".fast_vars1"); +TURNS turns = TURNS_DEFAULTS; + + //IQ_OUT_NOM TODO:set Iq nominal + +#define IQ_165_RPM 2306867 //165/ +#define IQ_170_RPM 2376772 //170/ +#define IQ_5_RPM 69905 //5/ + +#define TIME_RMP_FAST 10.0 //sec +#define TIME_RMP_SLOW 30.0 //sec +#define F_DEST 3.0 //Hz + +void init_Fvect() +{ + turns.pidFvect.Ref = 0; + turns.pidFvect.Kp = _IQ(5); // //_IQ(30); + turns.pidFvect.Ki = _IQ(0.005); //_IQ(0.008);//_IQ(0.002); // + turns.pidFvect.Kc = _IQ(0.5); + turns.pidFvect.OutMax = _IQ(MOTOR_CURRENT_MAX / 2.0 / NORMA_ACP); + turns.pidFvect.OutMin = -_IQ(MOTOR_CURRENT_MAX / 2.0 / NORMA_ACP); + + turns.Fzad_rmp = 0; + turns.Fnominal = _IQ(FROT_MAX / NORMA_FROTOR); + turns.koef_fast = + _IQ(F_DEST / (float)NORMA_FROTOR / TIME_RMP_SLOW / (float)FREQ_PWM / 1.0); + turns.koef_slow = + _IQ(F_DEST / (float)NORMA_FROTOR / TIME_RMP_SLOW / (float)FREQ_PWM / 1.0); + turns.Iq_out_max = _IQ(MOTOR_CURRENT_MAX / NORMA_ACP); + turns.Id_out_max = 0;//_IQ(ID_OUT_NOM / NORMA_ACP); + turns.mzz_zad_int = 0; +} + +void reset_F_pid() +{ + turns.pidFvect.Up = 0; + turns.pidFvect.Up1 = 0; + turns.pidFvect.Ui = 0; + turns.pidFvect.Ud = 0; + turns.pidFvect.Out = 0; +} + +//#pragma CODE_SECTION(vector_turns,".fast_run2"); +void vector_turns(_iq Fzad, _iq Frot, + _iq Iq_measured, _iq Iq_limit, int n_alg, + unsigned int master, _iq *Iq_zad, int reset) +{ + static int prev_n_alg = 0; + _iq koef_rmp; //, koef_spad; + _iq Iq_out_unsat, Iq_out_sat, Id_out_sat, Id_out_unsat; + _iq deltaVar; + +// turns.mzz_zad_int = zad_intensiv_q(35480, 35480, turns.mzz_zad_int, Iq_limit); + turns.mzz_zad_int = Iq_limit; + + turns.pidFvect.OutMax = turns.mzz_zad_int; + turns.pidFvect.OutMin = -turns.mzz_zad_int; + + // + if (Fzad >= 0 && Frot > 0) + { + turns.pidFvect.OutMin = 0; + } + if (Fzad <= 0 && Frot < 0) + { + turns.pidFvect.OutMax = 0; + } + if (reset) { turns.Fzad_rmp = Frot;} + + if ((n_alg < ALG_MODE_FOC_OBOROTS) || (!edrk.Go)) + // -, + { // + turns.Fzad_rmp = Frot; +// prev_Fzad = Frot; + reset_F_pid(); // , - + turns.pidFvect.Ui = Iq_measured; + turns.pidFvect.Out = Iq_measured; + *Iq_zad = Iq_measured; + + if (!edrk.Go) + { + *Iq_zad = 0; + } + + return; + } + if (master == MODE_SLAVE) { + turns.Fzad_rmp = Frot; + turns.pidFvect.Ui = Iq_measured; + turns.pidFvect.Out = Iq_measured; + return; + } + // + if (n_alg == ALG_MODE_FOC_POWER) { + Fzad = turns.Fnominal; + } + // + // + if (n_alg == ALG_MODE_FOC_OBOROTS && prev_n_alg != ALG_MODE_FOC_OBOROTS) { + turns.Fzad_rmp = Frot; + } + + if (_IQabs(turns.Fzad_rmp) <= _IQabs(Fzad) + && (((Fzad >= 0) && (turns.Fzad_rmp >= 0)) + || ((Fzad < 0) && (turns.Fzad_rmp < 0)))) + { + koef_rmp = turns.koef_slow; + } + else + { + koef_rmp = turns.koef_fast; + } + + turns.Fzad_rmp = zad_intensiv_q(koef_rmp, koef_rmp, turns.Fzad_rmp, Fzad); + + turns.pidFvect.Ref = turns.Fzad_rmp; + turns.pidFvect.Fdb = Frot; + + turns.pidFvect.calc(&turns.pidFvect); + Iq_out_unsat = turns.pidFvect.Out; + + Iq_out_sat = _IQsat(Iq_out_unsat, turns.mzz_zad_int, -turns.mzz_zad_int); //Test + *Iq_zad = Iq_out_sat; + + prev_n_alg = n_alg; +} diff --git a/Inu/Src2/551/VectorControl/regul_turns.h b/Inu/Src2/551/VectorControl/regul_turns.h new file mode 100644 index 0000000..f765b88 --- /dev/null +++ b/Inu/Src2/551/VectorControl/regul_turns.h @@ -0,0 +1,29 @@ +#ifndef REGUL_TURNS +#define REGUL_TURNS +#include "IQmathLib.h" +#include "pid_reg3.h" + +typedef struct { + PIDREG3 pidFvect; + + _iq Fzad_rmp; + _iq Fnominal; + _iq koef_fast; + _iq koef_slow; + _iq Iq_out_max; + _iq Id_out_max; + _iq mzz_zad_int; +} TURNS; + +#define TURNS_DEFAULTS {PIDREG3_DEFAULTS, 0,0,0,0,0,0,0} + +void init_Fvect(void); +void vector_turns(_iq Fzad, _iq Frot, + _iq Iq, _iq Iq_limit, int mode, + unsigned int master, _iq *Iq_zad, int reset); + +extern TURNS turns; + +#endif //REGUL_TURNS + + diff --git a/Inu/Src2/551/VectorControl/smooth.c b/Inu/Src2/551/VectorControl/smooth.c new file mode 100644 index 0000000..dcf63c8 --- /dev/null +++ b/Inu/Src2/551/VectorControl/smooth.c @@ -0,0 +1,180 @@ +#include "IQmathLib.h" // Include header for IQmath library + +#include "smooth.h" +#include "math_pi.h" +#include "math_pi.h" + + +#define SIZE_SMOOTH_INPUT 180 + + +#pragma CODE_SECTION(my_mean,".fast_run"); +_iq23 my_mean(int cnt, SMOOTH *v) +{ + _iq23 summ = 0; + int start; + + + start = v->current_pos_buf_input; + if (start==0) + start = (MAX_SIZE_SMOOTH_INPUT-1); + + while(cnt>0) + { + cnt--; + start--; + summ += v->buf_input[start]; + if (start==0) + start = (MAX_SIZE_SMOOTH_INPUT-1); + } + return summ; + +} + + + +void smooth_init(SMOOTH *v) +{ + int i=0; + + v->c = 1; + v->av = 0; + v->w = _IQ23(WINDOW_START); + + for (i=0;ibuf_input[i] = 0; + } +// current_pos_buf_input = 0; + v->current_pos_buf_input = 0; + +} + +#pragma CODE_SECTION(smooth_add,".fast_run"); +void smooth_add(SMOOTH *v) +{ + volatile int i; + + i = v->current_pos_buf_input; + v->buf_input[i] = v->input; + + v->current_pos_buf_input++; + if (v->current_pos_buf_input>=MAX_SIZE_SMOOTH_INPUT) + v->current_pos_buf_input = 0; + +} + + +#pragma CODE_SECTION(smooth_calc,".fast_run"); +void smooth_calc(SMOOTH *v) +{ + _iq23 e=0; + _iq23 summ=0; + _iq23 w_new; + long w_int; + + w_int = _IQ23int(v->w); + + if (v->c <= (WINDOW_START*2)) + { + summ = my_mean(v->c,v); + v->av = _IQ23div(summ,_IQ23(v->c)); + e = 0; + } + else + { + e = _IQ23div(CONST_IQ_2PI,v->av) - v->w; //(2*pi*fs/av) - w + v->ee = v->ee + _IQ23mpy(v->kp,(e - v->e0)) + _IQ23mpy(v->ki, e); + w_new = v->w + v->ee; + + if (w_new>_IQ23(SIZE_SMOOTH_INPUT)) + w_new = _IQ23(SIZE_SMOOTH_INPUT); + + w_int = _IQ23int(w_new); + summ = my_mean(w_int,v); + v->w = _IQ23(w_int); + v->av = _IQ23div(summ, v->w); + + } + + if (v->cc++; + + v->e0 = e; + v->w_int = w_int; +} + + +#pragma CODE_SECTION(smooth_simple_calc,".fast_run"); +void smooth_simple_calc(SMOOTH *v) +{ + volatile _iq23 summ=0; + + if (v->c <= v->w_int_simple ) + { + summ = my_mean(v->c, v); + v->summ = summ; + v->av = _IQ23div(summ,_IQ23(v->c)); + } + else + { + summ = my_mean(v->w_int_simple, v); + v->summ = summ; + v->av = _IQ23div(summ, _IQ23(v->w_int_simple)); + } + + if (v->cc++; + + +} + + + + +void iq_smooth (_iq23 *input, _iq23 *output, int n, int window) +{ + int i,j,z,k1,k2,hw; + int fm1,fm2; + + _iq23 tmp; + + + fm1 = window/2; + fm2 = fm1*2; + if ((window-fm2)==0) + window++; + + hw = (window-1)/2; + output[0] = input[0]; + + for (i=1;i(n-1)) + { + k1=i-n+i+1; + k2=n-1; + z=k2-k1+1; + } + else + { + k1=i-hw; + k2=i+hw; + z=window; + } + + for (j=k1;j<=k2;j++) + { + tmp=tmp + input[j]; + } + output[i] = _IQ23div(tmp,_IQ23(z)); + } + +} diff --git a/Inu/Src2/551/VectorControl/smooth.h b/Inu/Src2/551/VectorControl/smooth.h new file mode 100644 index 0000000..c91e6f1 --- /dev/null +++ b/Inu/Src2/551/VectorControl/smooth.h @@ -0,0 +1,78 @@ +#ifndef __SMOOTH_H__ +#define __SMOOTH_H__ + +#define WINDOW_START 79.0 //39.0 +#define MAX_SIZE_SMOOTH_INPUT 180 + +typedef struct { int current_pos_buf_input; + _iq23 kp; + _iq23 ki; + int c; + int w_int_simple; + _iq23 w; + long w_int; + _iq23 ee; + _iq23 e0; + _iq23 av; + _iq23 input; + _iq23 summ; + _iq23 buf_input[MAX_SIZE_SMOOTH_INPUT]; + void (*init)(); // Pointer to calculation function + void (*add)(); // Pointer to calculation function + void (*calc)(); // Pointer to calculation function + void (*simple_calc)(); // Pointer to calculation function + + }SMOOTH; + + + + + +typedef SMOOTH *SMOOTH_handle; + +#define SMOOTH_DEFAULTS { 0, \ + _IQ23(0.1), \ + _IQ23(0.01), \ + 1, \ + 1, \ + _IQ23(WINDOW_START), \ + WINDOW_START, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + {0},\ + (void (*)(unsigned long))smooth_init,\ + (void (*)(unsigned long))smooth_add,\ + (void (*)(unsigned long))smooth_calc,\ + (void (*)(unsigned long))smooth_simple_calc\ + } + + +void smooth_calc(SMOOTH_handle); +void smooth_init(SMOOTH_handle); +void smooth_add(SMOOTH_handle); +void smooth_simple_calc(SMOOTH_handle); + + + + + + +void iq_smooth (_iq23 *input, _iq23 *output, int n, int window); + + + + +#endif // end __ABC_ALPHABETA_H + + + + + + + + + + diff --git a/Inu/Src2/551/VectorControl/teta_calc.c b/Inu/Src2/551/VectorControl/teta_calc.c new file mode 100644 index 0000000..8a64daf --- /dev/null +++ b/Inu/Src2/551/VectorControl/teta_calc.c @@ -0,0 +1,91 @@ +#include "IQmathLib.h" + +#include "teta_calc.h" + +#include +#include +#include +#include +#include + +#include "mathlib.h" +#include "pid_reg3.h" + + +#define CONST_IQ_2PI 105414357 +#define PI 3.1415926535897932384626433832795 + +#define MAX_Ud_Pid_Out_Id 176160 //0.2 ~ 167772 //0.21 ~ 176160 +#define BPSI_START 0.17 //0.15 + +TETTA_CALC tetta_calc = TETTA_CALC_DEF; + +void init_teta_calc_struct() +{ + float Tr_cm = (L_M + L_SIGMA_R) / (R_ROTOR_SHTRIH / SLIP_NOM); +// tetta_calc.k_r = _IQ(1 / FREQ_PWM / Tr_cm); +// tetta_calc.k_t = _IQ(R_ROTOR / (L_M + L_SIGMA_R) / 2.0 / 3.14 / 50 / NORMA_FROTOR); + tetta_calc.k_r = _IQ(0.005168); //_IQ(0.015); + tetta_calc.k_t = _IQ(0.0074); //_IQ(0.0045); + tetta_calc.Imds = 0; + tetta_calc.theta = 0; + tetta_calc.hz_to_angle = _IQ(2.0 * PI * NORMA_FROTOR / FREQ_PWM); +} + +//#pragma CODE_SECTION(calc_teta_Id,".fast_run"); +void calc_teta_Id(_iq Frot, _iq Id, _iq Iq, _iq *theta_out, _iq *theta_to_slave, _iq *Fsl_out, _iq *Fstator_out, + unsigned int master, int reset) { + + _iq Fsl, Fst; + _iq add_to_tic = 0; + _iq to_slave = 0; + + if (reset) { + tetta_calc.Imds = 0; + } + + tetta_calc.Imds = tetta_calc.Imds + _IQmpy(tetta_calc.k_r, (Id - tetta_calc.Imds)); + + if (master == MODE_SLAVE){ + return; + } + + Fsl = _IQmpy(tetta_calc.k_t, Iq); + if (tetta_calc.Imds != 0) { + Fsl = _IQdiv(Fsl, tetta_calc.Imds); + } else { + Fsl = 0; + } + + if (Fsl > MAX_Ud_Pid_Out_Id) { Fsl = MAX_Ud_Pid_Out_Id;} + if (Fsl < -MAX_Ud_Pid_Out_Id) { Fsl = -MAX_Ud_Pid_Out_Id;} +// if (Fsl < 0) { Fsl = 0;} + + Fst = Frot * POLUS + Fsl; + add_to_tic = _IQmpy(Fst, tetta_calc.hz_to_angle); + tetta_calc.theta += add_to_tic; + to_slave = tetta_calc.theta + add_to_tic; + + if (tetta_calc.theta > CONST_IQ_2PI) { + tetta_calc.theta -= CONST_IQ_2PI; + } else if (tetta_calc.theta < 0) { + tetta_calc.theta += CONST_IQ_2PI; + } + + if (to_slave > CONST_IQ_2PI) { + to_slave -= CONST_IQ_2PI; + } else if (to_slave < 0) { + to_slave += CONST_IQ_2PI; + } + + *Fsl_out = Fsl; + *theta_out = tetta_calc.theta; + *theta_to_slave = to_slave; + *Fstator_out = Fst; + +// logpar.log26 = (int16)(_IQtoIQ15(Fsl)); +// logpar.log27 = (int16)(_IQtoIQ15(tetta_calc.Imds)); +// logpar.log28 = (int16)(_IQtoIQ15(Iq)); +// logpar.log3 = (int16)(_IQtoIQ15(Id)); +} + diff --git a/Inu/Src2/551/VectorControl/teta_calc.h b/Inu/Src2/551/VectorControl/teta_calc.h new file mode 100644 index 0000000..d2e7b03 --- /dev/null +++ b/Inu/Src2/551/VectorControl/teta_calc.h @@ -0,0 +1,36 @@ +#ifndef TETA_CALC +#define TETA_CALC + +#include "IQmathLib.h" +#include "pid_reg3.h" + +void calc_teta_Id(_iq Frot, _iq Id, _iq Iq, _iq *tetta_out, _iq *theta_to_slave, _iq *Fsl_out, _iq *Fstator_out, + unsigned int master, int reset); +void init_teta_calc_struct(void); + +// k_r = Ts / Tr_cm +// Tr_cm = Lr / Rr +// Lr - +// Rr - +// +// k_t = 1 / (Tr_cm * 2 * Pi * f_b) +// f_b = NORMA_FROT +// K = Ts * f_b +// f_b - (12 ) +// Ts - (840 ) + +typedef struct { + _iq Imds; + _iq theta; + + _iq hz_to_angle; + _iq k_r; + _iq k_t; +} TETTA_CALC; + +#define TETTA_CALC_DEF {0,0,0,0,0} + +extern TETTA_CALC tetta_calc; + +#endif //TETA_CALC + diff --git a/Inu/Src2/551/VectorControl/vector_control.c b/Inu/Src2/551/VectorControl/vector_control.c new file mode 100644 index 0000000..901b75d --- /dev/null +++ b/Inu/Src2/551/VectorControl/vector_control.c @@ -0,0 +1,297 @@ +/* + * vector_control.c + * + * Created on: 16 . 2020 . + * Author: star + */ +#include "IQmathLib.h" + +#include "vector_control.h" + +#include +#include +#include +#include +#include +#include +#include "math.h" +#include "mathlib.h" +#include "filter_v1.h" +#include "abc_to_dq.h" +#include "regul_power.h" +#include "regul_turns.h" +#include "teta_calc.h" + +//#define CALC_TWO_WINDINGS + +#define I_ZERO_LEVEL_IQ 27962 // 111848 ~ 20A //279620 ~ 50A //55924 ~ 10A + + +#pragma DATA_SECTION(vect_control,".fast_vars"); +VECTOR_CONTROL vect_control = VECTOR_CONTROL_DEFAULTS; + + +void Idq_to_Udq_2_windings(_iq Id_zad, _iq Iq_zad, + _iq Id_measured1, _iq Iq_measured1, _iq* Ud_zad1, _iq* Uq_zad1, + _iq Id_measured2, _iq Iq_measured2, _iq* Ud_zad2, _iq* Uq_zad2, int reset); +void analog_Udq_calc(_iq Ud1, _iq Uq1, _iq Ud2, _iq Uq2); +void analog_dq_calc(_iq winding_displacement); +_iq calcId(_iq Iq_limit, _iq Iq, int reset, int prepare_stop_PWM); +inline void calcUdUqCompensation(_iq Frot); + +void initVectorControl() { + vect_control.pidD1.Kp = _IQ(0.3);//_IQ(0.2); + vect_control.pidD1.Ki = _IQ(0.01);//_IQ(0.9); + vect_control.pidD1.OutMax = _IQ(0.9); + vect_control.pidD1.OutMin = -_IQ(0.9); + vect_control.pidQ1.Kp = _IQ(0.3); + vect_control.pidQ1.Ki = _IQ(0.01); + vect_control.pidQ1.OutMax = _IQ(0.9); + vect_control.pidQ1.OutMin = -_IQ(0.9); + vect_control.pidD2.Kp = _IQ(0.3); + vect_control.pidD2.Ki = _IQ(0.3); + vect_control.pidD2.OutMax = _IQ(0.9); + vect_control.pidD2.OutMin = -_IQ(0.9); + vect_control.pidQ2.Kp = _IQ(0.3); + vect_control.pidQ2.Ki = _IQ(0.3); + vect_control.pidQ2.OutMax = _IQ(0.9); + vect_control.pidQ2.OutMin = -_IQ(0.9); + +// vect_control.iqId_nominal = _IQ(MOTOR_CURRENT_NOMINAL * sqrtf(1 - COS_FI * COS_FI) / NORMA_ACP); + vect_control.iqId_nominal = _IQ(MOTOR_CURRENT_NOMINAL * 0.4 / NORMA_ACP); + vect_control.iqId_min = _IQ(200 / NORMA_ACP); + vect_control.iqId_start = _IQ(200.0 / NORMA_ACP); + vect_control.koef_rmp_Id = (_iq)(vect_control.iqId_nominal / FREQ_PWM); + vect_control.koef_filt_I = _IQ(0.5); + + + vect_control.koef_Ud_comp = _IQ((L_SIGMA_S + L_M * L_SIGMA_R / (L_M + L_SIGMA_R)) * 2 * 3.14 * NORMA_FROTOR); //Lsigm_s + Lm*Lsigm_r / (Lm + Lsigm_r) + vect_control.koef_Uq_comp = _IQ((L_M + L_SIGMA_S) * 2 * 3.14 * NORMA_FROTOR); //Lm + Lsigm_s +// vect_control.koef_Ud_comp = _IQ(0.0002369 * 2 * 3.14 * NORMA_FROTOR); //Lsigm_s + Lm*Lsigm_r / (Lm + Lsigm_r) +// vect_control.koef_Uq_comp = _IQ(0.0043567 * 2 * 3.14 * NORMA_FROTOR); //Lm + Lsigm_s + vect_control.koef_zero_Uzad = _IQ(0.993); //_IQ(0.993); //_IQ(0.03); + init_Pvect(); + init_Fvect(); + init_teta_calc_struct(); +} + +void vectorControlConstId (_iq Pzad, _iq Fzad, int direction, _iq Frot, + int n_alg, unsigned int master, _iq mzz_zad, + _iq winding_displacement, + _iq theta_from_master, _iq Iq_from_master, _iq P_from_slave, + _iq *theta_to_slave, _iq *Iq_to_slave, _iq *P_to_master, + int reset, int prepare_stop_PWM) { + _iq Iq_zad = 0, Iq_zad_power = 0, Id_zad = 0; + _iq P_measured = 0; + static _iq Ud_zad1 = 0, Uq_zad1 = 0, Ud_zad2 = 0, Uq_zad2 = 0; + +// if(direction < 0) { Frot = -Frot; } + + if (reset) { + Ud_zad1 = 0; + Uq_zad1 = 0; + Ud_zad2 = 0; + Uq_zad2 = 0; + } + analog_dq_calc(winding_displacement); + + P_measured = vect_control.iqPvsi1 + vect_control.iqPvsi2; + *P_to_master = P_measured; + P_measured += P_from_slave; + + + + vector_power(Pzad, P_measured, n_alg, master, (vect_control.iqIq1 + vect_control.iqIq2), + edrk.zadanie.iq_Izad_rmp, &Iq_zad_power, reset); + vector_turns(Fzad, Frot, (vect_control.iqIq1 + vect_control.iqIq2), + Iq_zad_power, n_alg, master, &Iq_zad, reset); + + Id_zad = calcId(edrk.zadanie.iq_Izad, Iq_zad, reset, prepare_stop_PWM); + + if (master == MODE_SLAVE) { + vect_control.iqTheta = theta_from_master; + *theta_to_slave = theta_from_master; + Iq_zad = Iq_from_master; + Iq_zad_power = Iq_from_master; + } else { +// calc_teta_Id(Frot, vect_control.iqId1, vect_control.iqIq1, &vect_control.iqTheta, theta_to_slave, +// &vect_control.iqFsl, &vect_control.iqFstator, master, reset); + calc_teta_Id(Frot, Id_zad, Iq_zad, &vect_control.iqTheta, theta_to_slave, + &vect_control.iqFsl, &vect_control.iqFstator, master, reset); + } + + calcUdUqCompensation(Frot); + + if (prepare_stop_PWM && Id_zad == 0) { + vect_control.iqUdKm = _IQmpy(vect_control.iqUdKm, vect_control.koef_zero_Uzad); + vect_control.iqUqKm = _IQmpy(vect_control.iqUqKm, vect_control.koef_zero_Uzad); + } else { + Idq_to_Udq_2_windings((Id_zad >> 1), (Iq_zad >> 1), + vect_control.iqId1, vect_control.iqIq1, &Ud_zad1, &Uq_zad1, + vect_control.iqId2, vect_control.iqIq2, &Ud_zad2, &Uq_zad2, reset); + + vect_control.iqUdKm = Ud_zad1 + vect_control.iqUdCompensation; + vect_control.iqUqKm = Uq_zad1 + vect_control.iqUqCompensation; + } + + vect_control.sqrtIdq1 = _IQsqrt(_IQmpy(vect_control.iqId1, vect_control.iqId1) + _IQmpy(vect_control.iqIq1, vect_control.iqIq1)); + analog_Udq_calc(Ud_zad1, Uq_zad1, Ud_zad2, Uq_zad2); + *Iq_to_slave = Iq_zad; + + vect_control.Iq_zad1 = Iq_zad; + vect_control.Id_zad1 = Id_zad; + +} + + +#pragma CODE_SECTION(analog_dq_calc,".fast_run"); +void analog_dq_calc(_iq winding_displacement) +{ + ABC_TO_DQ abc_dq_converter = ABC_TO_DQ_DEFAULTS; + + abc_dq_converter.Ia = analog.iqIu_1; + abc_dq_converter.Ib = analog.iqIv_1; + abc_dq_converter.Ic = analog.iqIw_1; + abc_dq_converter.Tetta = vect_control.iqTheta + winding_displacement; + abc_dq_converter.calc(&abc_dq_converter); + vect_control.iqId1 = abc_dq_converter.Id; + vect_control.iqIq1 = abc_dq_converter.Iq; + vect_control.iqId1_filt = exp_regul_iq(vect_control.koef_filt_I, vect_control.iqId1_filt, vect_control.iqId1); + vect_control.iqIq1_filt = exp_regul_iq(vect_control.koef_filt_I, vect_control.iqIq1_filt, vect_control.iqIq1); + + abc_dq_converter.Ia = analog.iqIu_2; + abc_dq_converter.Ib = analog.iqIv_2; + abc_dq_converter.Ic = analog.iqIw_2; + abc_dq_converter.Tetta = vect_control.iqTheta + winding_displacement; + abc_dq_converter.calc(&abc_dq_converter); + vect_control.iqId2 = abc_dq_converter.Id; + vect_control.iqIq2 = abc_dq_converter.Iq; + vect_control.iqId2_filt = exp_regul_iq(vect_control.koef_filt_I, vect_control.iqId2_filt, vect_control.iqId2); + vect_control.iqIq2_filt = exp_regul_iq(vect_control.koef_filt_I, vect_control.iqIq2_filt, vect_control.iqIq2); + + + if (_IQabs(vect_control.iqId1) < I_ZERO_LEVEL_IQ) { vect_control.iqId1 = 0; } + if (_IQabs(vect_control.iqIq1) < I_ZERO_LEVEL_IQ) { vect_control.iqIq1 = 0; } + if (_IQabs(vect_control.iqId2) < I_ZERO_LEVEL_IQ) { vect_control.iqId2 = 0; } + if (_IQabs(vect_control.iqIq2) < I_ZERO_LEVEL_IQ) { vect_control.iqIq2 = 0; } + + vect_control.iqPvsi1 = _IQmpy(_IQmpy(vect_control.iqIq1, _IQabs(vect_control.iqUq1)), 25165824L); + vect_control.iqPvsi2 = _IQmpy(_IQmpy(vect_control.iqIq2, _IQabs(vect_control.iqUq2)), 25165824L); + +} + +#pragma CODE_SECTION(analog_dq_calc_external,".fast_run"); +void analog_dq_calc_external(_iq winding_displacement, _iq theta) +{ + ABC_TO_DQ abc_dq_converter = ABC_TO_DQ_DEFAULTS; + + abc_dq_converter.Ia = analog.iqIu_1; + abc_dq_converter.Ib = analog.iqIv_1; + abc_dq_converter.Ic = analog.iqIw_1; + abc_dq_converter.Tetta = theta + winding_displacement; + abc_dq_converter.calc(&abc_dq_converter); + vect_control.iqId1 = abc_dq_converter.Id; + vect_control.iqIq1 = abc_dq_converter.Iq; + + + abc_dq_converter.Ia = analog.iqIu_2; + abc_dq_converter.Ib = analog.iqIv_2; + abc_dq_converter.Ic = analog.iqIw_2; + abc_dq_converter.Tetta = theta + winding_displacement; + abc_dq_converter.calc(&abc_dq_converter); + vect_control.iqId2 = abc_dq_converter.Id; + vect_control.iqIq2 = abc_dq_converter.Iq; + + if (_IQabs(vect_control.iqId1) < I_ZERO_LEVEL_IQ) { vect_control.iqId1 = 0; } + if (_IQabs(vect_control.iqIq1) < I_ZERO_LEVEL_IQ) { vect_control.iqIq1 = 0; } + if (_IQabs(vect_control.iqId2) < I_ZERO_LEVEL_IQ) { vect_control.iqId2 = 0; } + if (_IQabs(vect_control.iqIq2) < I_ZERO_LEVEL_IQ) { vect_control.iqIq2 = 0; } + + vect_control.iqPvsi1 = _IQmpy(_IQmpy(vect_control.iqIq1, _IQabs(vect_control.iqUq1)), 25165824L); + vect_control.iqPvsi2 = _IQmpy(_IQmpy(vect_control.iqIq2, _IQabs(vect_control.iqUq2)), 25165824L); + +} + +void Idq_to_Udq_2_windings(_iq Id_zad, _iq Iq_zad, + _iq Id_measured1, _iq Iq_measured1, _iq* Ud_zad1, _iq* Uq_zad1, + _iq Id_measured2, _iq Iq_measured2, _iq* Ud_zad2, _iq* Uq_zad2, int reset) +{ + if (reset) { + vect_control.pidD1.Ui = 0; + vect_control.pidD1.Out = 0; + vect_control.pidQ1.Ui = 0; + vect_control.pidQ1.Out = 0; +#ifdef CALC_TWO_WINDINGS + vect_control.pidD2.Ui = 0; + vect_control.pidD2.Out = 0; + vect_control.pidQ2.Ui = 0; + vect_control.pidQ2.Out = 0; +#endif + } + vect_control.pidD1.Ref = Id_zad; + vect_control.pidD1.Fdb = Id_measured1; + vect_control.pidD1.calc(&vect_control.pidD1); + *Ud_zad1 = vect_control.pidD1.Out; + + vect_control.pidQ1.Ref = Iq_zad; + vect_control.pidQ1.Fdb = Iq_measured1; + vect_control.pidQ1.calc(&vect_control.pidQ1); + *Uq_zad1 = vect_control.pidQ1.Out; +#ifdef CALC_TWO_WINDINGS + vect_control.pidD2.Ref = Id_zad; + vect_control.pidD2.Fdb = Id_measured2; + vect_control.pidD2.calc(&vect_control.pidD2); + *Ud_zad2 = vect_control.pidD2.Out; + + vect_control.pidQ2.Ref = Iq_zad; + vect_control.pidQ2.Fdb = Iq_measured2; + vect_control.pidQ2.calc(&vect_control.pidQ2); + *Uq_zad2 = vect_control.pidQ2.Out; +#else + *Ud_zad2 = *Ud_zad1; + *Uq_zad2 = *Ud_zad1; +// *Uq_zad2 = *Uq_zad1; +#endif +} + +#pragma CODE_SECTION(analog_Udq_calc,".fast_run"); +void analog_Udq_calc(_iq Ud1, _iq Uq1, _iq Ud2, _iq Uq2) +{ + _iq Uzpt = filter.iqU_1_long + filter.iqU_2_long; + vect_control.iqUd1 = _IQmpy(Ud1, _IQmpy(Uzpt, 8388608L)); // 8388608 = _IQ(0.5) + vect_control.iqUq1 = _IQmpy(Uq1, _IQmpy(Uzpt, 8388608L)); + vect_control.iqUd2 = _IQmpy(Ud2, _IQmpy(Uzpt, 8388608L)); + vect_control.iqUq2 = _IQmpy(Uq2, _IQmpy(Uzpt, 8388608L)); + +} + +_iq calcId(_iq Iq_limit, _iq Iq, int reset, int prepare_stop_PWM) { + static _iq Id_rmp = 0; + _iq Id_zad = 0; + if (reset) { + Id_rmp = 0; + } + + + if (prepare_stop_PWM) { + Id_zad = 0; + } else if (Iq < vect_control.iqId_min) { + Id_zad = vect_control.iqId_min; + } else if (Iq > vect_control.iqId_nominal) { + Id_zad = vect_control.iqId_nominal; + } else { + Id_zad = Iq; + } +// Id_zad = Iq_limit < vect_control.iqId_nominal ? Iq_limit : vect_control.iqId_nominal; + Id_rmp = zad_intensiv_q(vect_control.koef_rmp_Id, vect_control.koef_rmp_Id << 1, Id_rmp, Id_zad); + return Id_rmp; +} + +void calcUdUqCompensation(_iq Frot) { + _iq Uzpt = (filter.iqU_1_long + filter.iqU_2_long) >> 1; + _iq UdVolt = _IQmpy(_IQmpy(Frot, vect_control.koef_Ud_comp), vect_control.iqIq1 + vect_control.iqIq2); + _iq UqVolt = _IQmpy(_IQmpy(Frot, vect_control.koef_Uq_comp), vect_control.iqId1 + vect_control.iqId2); + vect_control.iqUdCompensation = -_IQdiv(UdVolt, Uzpt); + vect_control.iqUqCompensation = _IQdiv(UqVolt, Uzpt); +} + diff --git a/Inu/Src2/551/VectorControl/vector_control.h b/Inu/Src2/551/VectorControl/vector_control.h new file mode 100644 index 0000000..3307fb1 --- /dev/null +++ b/Inu/Src2/551/VectorControl/vector_control.h @@ -0,0 +1,82 @@ +/* + * vector_control.h + * + * Created on: 16 . 2020 . + * Author: star + */ + +#ifndef SRC_VECTORCONTROL_NIO12_VECTOR_CONTROL_H_ +#define SRC_VECTORCONTROL_NIO12_VECTOR_CONTROL_H_ + +#include "pid_reg3.h" +#include "regul_power.h" +#include "regul_turns.h" + +typedef struct { + PIDREG3 pidD1; + PIDREG3 pidQ1; + PIDREG3 pidD2; + PIDREG3 pidQ2; + + _iq iqId1; + _iq iqIq1; + _iq iqId2; + _iq iqIq2; + _iq iqUd1; + _iq iqUq1; + _iq iqUd2; + _iq iqUq2; + _iq iqUdKm; + _iq iqUqKm; + _iq iqUdCompensation; + _iq iqUqCompensation; + + _iq iqId1_filt; + _iq iqIq1_filt; + _iq iqId2_filt; + _iq iqIq2_filt; + + _iq iqPvsi1; + _iq iqPvsi2; + _iq iqTheta; + _iq iqFsl; + _iq iqFstator; + _iq iqId_nominal; + _iq iqId_min; + _iq iqId_start; + _iq koef_rmp_Id; + _iq koef_filt_I; + _iq koef_Ud_comp; + _iq koef_Uq_comp; + _iq koef_zero_Uzad; + _iq add_tetta; + + _iq sqrtIdq1; + _iq sqrtIdq2; + + _iq Iq_zad1; + _iq Id_zad1; + + _iq add_bpsi; + +} VECTOR_CONTROL; + +#define VECTOR_CONTROL_DEFAULTS {PIDREG3_DEFAULTS, PIDREG3_DEFAULTS, \ + PIDREG3_DEFAULTS, PIDREG3_DEFAULTS, \ + 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} + +void vectorControlConstId (_iq Pzad, _iq Fzad, int direction, _iq Frot, + int n_alg, unsigned int master, _iq mzz_zad, + _iq winding_displacement, + _iq theta_from_master, _iq Iq_from_master, _iq P_from_slave, + _iq *theta_to_slave, _iq *Iq_to_slave, _iq *P_to_master, + int reset, int prepare_stop_PWM); + +void analog_dq_calc_external(_iq winding_displacement, _iq theta); +void initVectorControl(); + +extern VECTOR_CONTROL vect_control; + + +#endif /* SRC_VECTORCONTROL_NIO12_VECTOR_CONTROL_H_ */ diff --git a/Inu/Src2/551/main/281xEvTimersInit.c b/Inu/Src2/551/main/281xEvTimersInit.c new file mode 100644 index 0000000..59b7005 --- /dev/null +++ b/Inu/Src2/551/main/281xEvTimersInit.c @@ -0,0 +1,636 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: July 2, 2007 11:32:13 $ +//########################################################################### +// +// FILE: Example_281xEvTimerPeriod.c +// +// TITLE: DSP281x Event Manager GP Timer example program. +// +// ASSUMPTIONS: +// +// This program requires the DSP281x V1.00 header files. +// As supplied, this project is configured for "boot to H0" operation. +// +// Other then boot mode pin configuration, no other hardware configuration +// is required. +// +// DESCRIPTION: +// +// This program sets up EVA Timer 1, EVA Timer 2, EVB Timer 3 +// and EVB Timer 4 to fire an interrupt on a period overflow. +// A count is kept each time each interrupt passes through +// the interrupt service routine. +// +// EVA Timer 1 has the shortest period while EVB Timer4 has the +// longest period. +// +// Watch Variables: +// +// EvaTimer1InterruptCount; +// EvaTimer2InterruptCount; +// EvbTimer3InterruptCount; +// EvbTimer4InterruptCount; +// +//########################################################################### +// $TI Release: DSP281x C/C++ Header Files V1.20 $ +// $Release Date: July 27, 2009 $ +//########################################################################### + +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "DSP281x_Examples.h" // DSP281x Examples Include File + +#include <281xEvTimersInit.h> +#include + +#include "TuneUpPlane.h" +#include "profile_interrupt.h" + +// Prototype statements for functions found within this file. +interrupt void eva_timer1_isr(void); +interrupt void eva_timer2_isr(void); +interrupt void evb_timer3_isr(void); +interrupt void evb_timer4_isr(void); + + +// Global counts used in this example +Uint32 EvaTimer1InterruptCount = 0; +Uint32 EvaTimer2InterruptCount = 0; +Uint32 EvbTimer3InterruptCount = 0; +Uint32 EvbTimer4InterruptCount = 0; + +//unsigned int enable_profile_led1_Timer1 = 1; +//unsigned int enable_profile_led1_Timer2 = 1; +//unsigned int enable_profile_led1_Timer3 = 1; +//unsigned int enable_profile_led1_Timer4 = 1; +// +//unsigned int enable_profile_led2_Timer1 = 0; +//unsigned int enable_profile_led2_Timer2 = 0; +//unsigned int enable_profile_led2_Timer3 = 0; +//unsigned int enable_profile_led2_Timer4 = 0; + +//Pointers to handler functions +void (*timer1_handler)() = NULL; +void (*timer2_handler)() = NULL; +void (*timer3_handler)() = NULL; +void (*timer4_handler)() = NULL; + +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void init_eva_timer1(int freq, void (*timer_handler)()) +{ + // Initialize EVA Timer 1: + // Setup Timer 1 Registers (EV A) + EvaRegs.GPTCONA.all = 0; + + // Set the Period for the GP timer 1 to 0x0200; + EvaRegs.T1PR = 0x0200; // Period + EvaRegs.T1CMPR = 0x0000; // Compare Reg + + // Enable Period interrupt bits for GP timer 1 + // Count up, x128, internal clk, enable compare, use own period + EvaRegs.EVAIMRA.bit.T1PINT = 0;//1; + EvaRegs.EVAIFRA.all = BIT7; +// EvaRegs.EVAIFRA.bit.T1PINT = 1; + + // Clear the counter for GP timer 1 + EvaRegs.T1CNT = 0x0000; +// EvaRegs.T1PR = (float64)HSPCLK/(float64)(freq / 2); + EvaRegs.T1PR = (float64)HSPCLK/(float64)(freq); + EvaRegs.T1CON.all = FREE_RUN_FLAG + TIMER_CONT_UP + TIMER_CLK_PRESCALE_X_1 + + TIMER_ENABLE_BY_OWN + TIMER_ENABLE + TIMER_ENABLE_COMPARE; // + + // Start EVA ADC Conversion on timer 1 Period interrupt + EvaRegs.GPTCONA.bit.T1TOADC = 2; + + // Save pointer to handler in variable + timer1_handler = timer_handler; + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.T1PINT = &eva_timer1_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // Enable PIE group 2 interrupt 4 for T1PINT +// PieCtrlRegs.PIEIER2.all = M_INT4; + PieCtrlRegs.PIEIER2.bit.INTx4 = 1; + + // Enable CPU INT2 for T1PINT, INT3 for T2PINT, INT4 for T3PINT + // and INT5 for T4PINT: + // IER |= M_INT2; +} + +void stop_eva_timer1() +{ + IER &= ~(M_INT2); + EvaRegs.EVAIMRA.bit.T1PINT = 0; +} + +void start_eva_timer1() +{ + IER |= (M_INT2); + EvaRegs.EVAIFRA.all = BIT7; + EvaRegs.EVAIMRA.bit.T1PINT = 1; +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void init_eva_timer2(int freq, void (*timer_handler)()) +{ + // Initialize EVA Timer 2: + // Setup Timer 2 Registers (EV A) + EvaRegs.GPTCONA.all = 0; + + // Set the Period for the GP timer 2 to 0x0200; + EvaRegs.T2PR = 0x0400; // Period + EvaRegs.T2CMPR = 0x0000; // Compare Reg + + // Enable Period interrupt bits for GP timer 2 + // Count up, x128, internal clk, enable compare, use own period + EvaRegs.EVAIMRB.bit.T2PINT = 0;//1; + EvaRegs.EVAIFRB.all = BIT0; + // EvaRegs.EVAIFRB.bit.T2PINT = 1; + + // Clear the counter for GP timer 2 + EvaRegs.T2CNT = 0x0000; +// EvaRegs.T2PR = (float64)HSPCLK/(float64)(freq / 2); + EvaRegs.T2PR = (float64)HSPCLK/(float64)(freq); + EvaRegs.T2CON.all = FREE_RUN_FLAG + TIMER_CONT_UP + TIMER_CLK_PRESCALE_X_1 + + TIMER_ENABLE_BY_OWN + TIMER_ENABLE + TIMER_ENABLE_COMPARE; // + + // Start EVA ADC Conversion on timer 2 Period interrupt + EvaRegs.GPTCONA.bit.T2TOADC = 2; + + // Save pointer to handler in variable + timer2_handler = timer_handler; + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.T2PINT = &eva_timer2_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // Enable PIE group 3 interrupt 1 for T2PINT +// PieCtrlRegs.PIEIER3.all = M_INT1; + PieCtrlRegs.PIEIER3.bit.INTx1 = 1;//M_INT1; + + // Enable CPU INT2 for T1PINT, INT3 for T2PINT, INT4 for T3PINT + // and INT5 for T4PINT: +// IER |= (M_INT3); +} + +void stop_eva_timer2() +{ + IER &= ~(M_INT3); + EvaRegs.EVAIMRB.bit.T2PINT = 0; +} + +void start_eva_timer2() +{ + IER |= (M_INT3); + EvaRegs.EVAIFRB.all = BIT0; + EvaRegs.EVAIMRB.bit.T2PINT = 1; +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void init_evb_timer3(int freq, void (*timer_handler)()) +{ + // Initialize EVB Timer 3: + // Setup Timer 3 Registers (EV B) + EvbRegs.GPTCONB.all = 0; + + // Set the Period for the GP timer 3 to 0x0200; + EvbRegs.T3PR = 0x0800; // Period + EvbRegs.T3CMPR = 0x0000; // Compare Reg + + // Enable Period interrupt bits for GP timer 3 + // Count up, x128, internal clk, enable compare, use own period + EvbRegs.EVBIMRA.bit.T3PINT = 0;//1; + EvbRegs.EVBIFRA.all = BIT7; + // EvbRegs.EVBIFRA.bit.T3PINT = 1; + + // Clear the counter for GP timer 3 + EvbRegs.T3CNT = 0x0000; +// EvbRegs.T3PR = (float64)HSPCLK/(float64)(freq / 2); + EvbRegs.T3PR = (float64)HSPCLK/(float64)(freq); + EvbRegs.T3CON.all = FREE_RUN_FLAG + TIMER_CONT_UP + TIMER_CLK_PRESCALE_X_1 + + TIMER_ENABLE_BY_OWN + TIMER_ENABLE + TIMER_ENABLE_COMPARE; +// EvbRegs.T3CON.all = SOFT_STOP_FLAG + TIMER_CONT_UP + TIMER_CLK_PRESCALE_X_1 + // + TIMER_ENABLE_BY_OWN + TIMER_ENABLE + TIMER_ENABLE_COMPARE; + + // Save pointer to handler in variable + timer3_handler = timer_handler; + + // Start EVA ADC Conversion on timer 3 Period interrupt + EvbRegs.GPTCONB.bit.T3TOADC = 2; + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.T3PINT = &evb_timer3_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // Enable PIE group 4 interrupt 4 for T3PINT +// PieCtrlRegs.PIEIER4.all = M_INT4; + PieCtrlRegs.PIEIER4.bit.INTx4 = 1; + + // Enable CPU INT2 for T1PINT, INT3 for T2PINT, INT4 for T3PINT + // and INT5 for T4PINT: + // IER |= M_INT4; +} + +void stop_evb_timer3() +{ + IER &= ~(M_INT4); + EvbRegs.EVBIMRA.bit.T3PINT = 0; +} + +void start_evb_timer3() +{ + IER |= (M_INT4); + + // Make sure PIEACK for group 2 is clear (default after reset) +// PieCtrlRegs.PIEACK.all = M_INT4; + EvbRegs.EVBIFRA.all = BIT7; + EvbRegs.EVBIMRA.bit.T3PINT = 1; +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +void init_evb_timer4(int freq, void (*timer_handler)()) +{ + // Initialize EVB Timer 4: + // Setup Timer 4 Registers (EV B) + EvbRegs.GPTCONB.all = 0; + + // Set the Period for the GP timer 4 to 0x0200; + EvbRegs.T4PR = 0x1000; // Period + EvbRegs.T4CMPR = 0x0000; // Compare Reg + + // Enable Period interrupt bits for GP timer 4 + // Count up, x128, internal clk, enable compare, use own period + EvbRegs.EVBIMRB.bit.T4PINT = 0;//1; + EvbRegs.EVBIFRB.all = BIT0; +// EvbRegs.EVBIFRB.bit.T4PINT = 1; + + // Clear the counter for GP timer 4 + EvbRegs.T4CNT = 0x0000; +// EvbRegs.T4PR = (float64)HSPCLK/(float64)(freq / 2); + EvbRegs.T4PR = (float64)HSPCLK/(float64)(freq); + EvbRegs.T4CON.all = FREE_RUN_FLAG + TIMER_CONT_UP + TIMER_CLK_PRESCALE_X_1 + + TIMER_ENABLE_BY_OWN + TIMER_ENABLE + TIMER_ENABLE_COMPARE; + + // Start EVA ADC Conversion on timer 4 Period interrupt + EvbRegs.GPTCONB.bit.T4TOADC = 2; + + // Save pointer to handler in variable + timer4_handler = timer_handler; + + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.T4PINT = &evb_timer4_isr; + EDIS; // This is needed to disable write to EALLOW protected registers + + // Enable PIE group 5 interrupt 1 for T4PINT +// PieCtrlRegs.PIEIER5.all = M_INT1; + PieCtrlRegs.PIEIER5.bit.INTx1 = 1; + + // Enable CPU INT2 for T1PINT, INT3 for T2PINT, INT4 for T3PINT + // and INT5 for T4PINT: + // IER |= M_INT5; +} + +void stop_evb_timer4() +{ + IER &= ~(M_INT5); + EvbRegs.EVBIMRB.bit.T4PINT = 0; +} + +void start_evb_timer4() +{ + IER |= (M_INT5); + EvbRegs.EVBIFRB.all = BIT0; + EvbRegs.EVBIMRB.bit.T4PINT = 1; +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(eva_timer1_isr,".fast_run2"); +interrupt void eva_timer1_isr(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER2.all; + IER |= M_INT2; + IER &= MINT2; // Set "global" priority + PieCtrlRegs.PIEIER2.all &= MG24; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.timer1) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.timer1) + i_led2_on_off_special(1); +#endif + EINT; + + // Insert ISR Code here....... + if(timer1_handler) + { + timer1_handler(); + } + + // Next line for debug only (remove after inserting ISR Code): +// ESTOP0; + EvaRegs.EVAIFRA.all = BIT7; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER2.all = TempPIEIER; +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.timer1) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.timer1) + i_led2_on_off_special(0); +#endif + +// +// +// IER &= ~(M_INT2);// stop_eva_timer1(); +// // Enable more interrupts from this timer +// EvaRegs.EVAIMRA.bit.T1PINT = 1; +// +// // Note: To be safe, use a mask value to write to the entire +// // EVAIFRA register. Writing to one bit will cause a read-modify-write +// // operation that may have the result of writing 1's to clear +// // bits other then those intended. +//// EvaRegs.EVAIFRA.bit.T1PINT = 1; +// EvaRegs.EVAIFRA.all = BIT7; +// +// // Acknowledge interrupt to receive more interrupts from PIE group 2 +// PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; +// +// // EINT; +// +// +// if(timer1_handler) +// { +// timer1_handler(); +// } + +// DINT; +// IER |= (M_INT2);//start_eva_timer1(); +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(eva_timer2_isr,".fast_run2"); +interrupt void eva_timer2_isr(void) +{ + + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER3.all; + IER |= M_INT3; + IER &= MINT3; // Set "global" priority + PieCtrlRegs.PIEIER3.all &= MG31; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.timer2) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.timer2) + i_led2_on_off_special(1); +#endif + + EINT; + + // Insert ISR Code here....... + if(timer2_handler) + { + timer2_handler(); + } + + // Next line for debug only (remove after inserting ISR Code): +// ESTOP0; + EvaRegs.EVAIFRB.all = BIT0; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER3.all = TempPIEIER; + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.timer2) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.timer2) + i_led2_on_off_special(0); +#endif + + + +// +// +// // IER &= ~(M_INT3);// stop_eva_timer2(); +// +// // Enable more interrupts from this timer +// EvaRegs.EVAIMRB.bit.T2PINT = 1; +// +// // Note: To be safe, use a mask value to write to the entire +// // EVAIFRB register. Writing to one bit will cause a read-modify-write +// // operation that may have the result of writing 1's to clear +// // bits other then those intended. +// EvaRegs.EVAIFRB.all = BIT0; +//// EvaRegs.EVAIFRB.bit.T2PINT = 1; +// +// +// // Acknowledge interrupt to receive more interrupts from PIE group 3 +// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; +// +// +//// EnableInterrupts(); +// +// if(timer2_handler) +// { +// timer2_handler(); +// } + + +// DINT; + // IER |= (M_INT3);//start_eva_timer2(); + + +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(evb_timer3_isr,".fast_run2"); +interrupt void evb_timer3_isr(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER4.all; + IER |= M_INT4; + IER &= MINT4; // Set "global" priority + PieCtrlRegs.PIEIER4.all &= MG44; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.timer3) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.timer3) + i_led2_on_off_special(1); +#endif + + EINT; + + // Insert ISR Code here....... + if(timer3_handler) + { + timer3_handler(); + } + + // Next line for debug only (remove after inserting ISR Code): +// ESTOP0; + +// EvbRegs.EVBIMRA.bit.T3PINT = 1; + EvbRegs.EVBIFRA.all = BIT7; +// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; // Enable PIE interrupts + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER4.all = TempPIEIER; + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.timer3) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.timer3) + i_led2_on_off_special(0); +#endif + + +// +// +// IER &= ~(M_INT4);//stop_evb_timer3(); +// +// // Enable more interrupts from this timer +// EvbRegs.EVBIMRA.bit.T3PINT = 1; +// +// +// // IER &= ~(M_INT4); +// //EvbTimer3InterruptCount++; +// // Note: To be safe, use a mask value to write to the entire +// // EVBIFRA register. Writing to one bit will cause a read-modify-write +// // operation that may have the result of writing 1's to clear +// // bits other then those intended. +// EvbRegs.EVBIFRA.all = BIT7; +// +// // Acknowledge interrupt to receive more interrupts from PIE group 4 +// PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; +// +// EINT; +// +// +// if(timer3_handler) +// { +// timer3_handler(); +// } +// // IFR &= ~(M_INT4); // ! +// // IER |= (M_INT4); +// +// DINT; +// IER |= (M_INT4);//start_evb_timer3(); +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(evb_timer4_isr,".fast_run2"); +interrupt void evb_timer4_isr(void) +{ + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG51; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.timer4) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.timer4) + i_led2_on_off_special(1); +#endif + + EINT; + + // Insert ISR Code here....... + if(timer4_handler) + { + timer4_handler(); + } + + // Next line for debug only (remove after inserting ISR Code): +// ESTOP0; + EvbRegs.EVBIFRB.all = BIT0; + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.timer4) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.timer4) + i_led2_on_off_special(0); +#endif + +// +// +// +// IER &= ~(M_INT5);//stop_evb_timer4(); +// +// EvbRegs.EVBIMRB.bit.T4PINT = 1; +// //EvbTimer4InterruptCount++; +// // Note: To be safe, use a mask value to write to the entire +// // EVBIFRB register. Writing to one bit will cause a read-modify-write +// // operation that may have the result of writing 1's to clear +// // bits other then those intended. +// EvbRegs.EVBIFRB.all = BIT0; +// +// // Acknowledge interrupt to receive more interrupts from PIE group 5 +// PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; +// EINT; +// +// +// if(timer4_handler) +// { +// timer4_handler(); +// } +// +// DINT; +// IER |= (M_INT5);//start_evb_timer4(); +} +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////// + + +//=========================================================================== +// No more. +//=========================================================================== diff --git a/Inu/Src2/551/main/281xEvTimersInit.h b/Inu/Src2/551/main/281xEvTimersInit.h new file mode 100644 index 0000000..2498fc9 --- /dev/null +++ b/Inu/Src2/551/main/281xEvTimersInit.h @@ -0,0 +1,18 @@ +#ifndef EV_TIMERS +#define EV_TIMERS + +void init_eva_timer1(int freqHz, void (*timer_handler)()); +void init_eva_timer2(int freqHz, void (*timer_handler)()); +void init_evb_timer3(int freqHz, void (*timer_handler)()); +void init_evb_timer4(int freqHz, void (*timer_handler)()); + +void start_eva_timer1(); +void stop_eva_timer1(); +void start_eva_timer2(); +void stop_eva_timer2(); +void start_evb_timer3(); +void stop_evb_timer3(); +void start_evb_timer4(); +void stop_evb_timer4(); + +#endif //EV_TIMERS diff --git a/Inu/Src2/551/main/CAN_project.h b/Inu/Src2/551/main/CAN_project.h new file mode 100644 index 0000000..3454f1e --- /dev/null +++ b/Inu/Src2/551/main/CAN_project.h @@ -0,0 +1,256 @@ +/* + * CAN_project.h + * + * Created on: 21 2020 . + * Author: yura + */ + +#ifndef SRC_MAIN_CAN_PROJECT_H_ +#define SRC_MAIN_CAN_PROJECT_H_ + + +#include "can_protocol_ukss.h" + +////////////////////////////////////////////////////////////////// +// CAN +// PCH_1 PCH_2 67 +////////////////////////////////////////////////////////////////// +#define CAN_BASE_ADR_MPU_PCH_1 0x0CEB0E1 +#define CAN_BASE_ADR_MPU_PCH_2 0x0CEB0E1 //0x0CEB0E2 +////////////////////////////////////// +#define CAN_BASE_ADR_TERMINAL_PCH_1 0x0EEEE01 +#define CAN_BASE_ADR_TERMINAL_PCH_2 0x0EEEE03 +////////////////////////////////////// +#define CAN_BASE_ADR_UNITS_PCH_1 0x235500 +#define CAN_BASE_ADR_UNITS_PCH_2 0x235500 +////////////////////////////////////// +#define CAN_BASE_ADR_ALARM_LOG_PCH_1 0x0BCDEF01 +#define CAN_BASE_ADR_ALARM_LOG_PCH_2 0x0BCDEF02 +////////////////////////////////////////////////////////////////// + +//#define CAN_PROTOCOL_VERSION 1 +#define CAN_PROTOCOL_VERSION 2 + +#define CAN_SPEED_BITS 125000 +//#define CAN_SPEED_BITS 250000 +//#define CAN_SPEED_BITS 500000 + + + +#define ENABLE_CAN_SEND_TO_UKSS_FROM_MAIN 1 +#define ENABLE_CAN_SEND_TO_MPU_FROM_MAIN 1 +#define ENABLE_CAN_SEND_TO_TERMINAL_FROM_MAIN 0//1 +#define ENABLE_CAN_SEND_TO_TERMINAL_OSCIL 0//1 +#define ENABLE_CAN_SEND_TO_ANOTHER_BSU_FROM_MAIN 1 + + +////////////////////////////////////////////////////// + +#ifndef ENABLE_CAN_SEND_TO_UKSS_FROM_MAIN +#define ENABLE_CAN_SEND_TO_UKSS_FROM_MAIN 0 +#endif + +#ifndef ENABLE_CAN_SEND_TO_MPU_FROM_MAIN +#define ENABLE_CAN_SEND_TO_MPU_FROM_MAIN 0 +#endif + + +#ifndef ENABLE_CAN_SEND_TO_TERMINAL_FROM_MAIN +#define ENABLE_CAN_SEND_TO_TERMINAL_FROM_MAIN 0 +#endif + +#ifndef ENABLE_CAN_SEND_TO_TERMINAL_OSCIL +#define ENABLE_CAN_SEND_TO_TERMINAL_OSCIL 0 +#endif + +#ifndef ENABLE_CAN_SEND_TO_ANOTHER_BSU_FROM_MAIN +#define ENABLE_CAN_SEND_TO_ANOTHER_BSU_FROM_MAIN 0 +#endif + +/////////////////////////////////////////////////////////////////// +// setup ukss boxs +/////////////////////////////////////////////////////////////////// + +// +#define USE_UKSS_0 1 +#define USE_UKSS_1 1 +#define USE_UKSS_2 1 +#define USE_UKSS_3 1 +#define USE_UKSS_4 1 +//#define USE_UKSS_5 1 +//#define USE_UKSS_6 1 +//#define USE_UKSS_7 1 +//#define USE_UKSS_8 1 +//#define USE_UKSS_9 1 +//#define USE_UKSS_10 1 +//#define USE_UKSS_11 1 +//#define USE_UKSS_12 1 +//#define USE_UKSS_13 1 +//#define USE_UKSS_14 1 +//#define USE_UKSS_15 1 + + + +#define OFFSET_CAN_ADR_UNITS 0x10 + +// + +#if USE_UKSS_0 +#define ZADATCHIK_CAN 0 //Zadatchik +#endif + +#if USE_UKSS_1 +#define VPU_CAN 1 //VPU +#endif + +#if USE_UKSS_2 +#define UMU_CAN_DEVICE 2 //Voltage control UMU +#endif + +#if USE_UKSS_3 +#define BKSSD_CAN_DEVICE 3 //AC DRIVE +#endif + + +#if USE_UKSS_4 +#define ANOTHER_BSU1_CAN_DEVICE 4 //Another BSU1 +// Unites revers box or not +// revers box used only on CAN between BS1 BS2 +//#define USE_R_B_4 1 //0 +#endif + + +//#if USE_UKSS_5 +//#define ANOTHER_BSU2_CAN_DEVICE 5 //Another BSU2 +//// Unites revers box or not +//// revers box used only on CAN between BS1 BS2 +////#define USE_R_B_5 1 //0 +//#endif + + + + +/////////////////////////////////////////////////////////////////// +// setup mpu boxes +/////////////////////////////////////////////////////////////////// + +// +#define USE_MPU_0 1 +#define USE_MPU_1 1 +//#define USE_MPU_2 1 +//#define USE_MPU_3 1 + + +#define OFFSET_CAN_ADR_MPU 0x10 + +//#define MPU_CAN_DEVICE 2 // MPU +#define TIME_PAUSE_CAN_FROM_MPU 1000 + + + + +/////////////////////////////////////////////////////////////////// +// setup terminal boxes +/////////////////////////////////////////////////////////////////// +// +#define USE_TERMINAL_1_OSCIL 1 +#define USE_TERMINAL_1_CMD 1 +#define USE_TERMINAL_2_OSCIL 1 +#define USE_TERMINAL_2_CMD 1 + + +#define OFFSET_CAN_ADR_TERMINAL 0x10 +#define TIME_PAUSE_CAN_FROM_TERMINAL 2 + +/////////////////////////////////////////////////////////////////// +// setup ALARM_LOG box +/////////////////////////////////////////////////////////////////// +#define USE_ALARM_LOG_0 1 + +/////////////////////////////////////////////////////////////////// +// setup can_open boxes +/////////////////////////////////////////////////////////////////// +//#define BWC_CAN_DEVICE 7 // Water cooler +//#define INGITIM 9 + +//#define BWC_CAN_FATEC 1 +//#define BWC_CAN_SIEMENS 1 +//#define INGITIM_CAN_OPEN 1 + + +#define CANOPENUNIT_LEN 30 + + +/////////words from zadatchik from Ingitim +#define PDO1_W1_ADR 0x11 +#define PDO1_W2_ADR 0x12 +#define PDO1_W3_ADR 0x13 +#define PDO1_W4_ADR 0x14 +#define PDO2_W1_ADR 0x15 +#define PDO2_W2_ADR 0x16 +#define PDO2_W3_ADR 0x17 +#define PDO2_W4_ADR 0x18 +#define PDO3_W1_ADR 0x19 +#define PDO3_W2_ADR 0x1A +#define PDO3_W3_ADR 0x1B +#define PDO3_W4_ADR 0x1C +#define PDO5_W1_ADR 0x1D +#define PDO5_W2_ADR 0x1E +#define PDO5_W3_ADR 0x1F +#define PDO5_W4_ADR 0x20 +#define PDO6_W1_ADR 0x21 +#define PDO6_W2_ADR 0x22 +#define PDO6_W3_ADR 0x23 +#define PDO6_W4_ADR 0x24 +////////////////////////////////////// + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +#define UNITS_NUMERATION_FROM_0_OR_1 0 //1 + + +#define MAX_CAN_WAIT_TIMEOUT 7500 // 2500 +//-------------------------------------------------// + +//#define CAN_ADR_TEST_LAMP 0x0CE031 //0x1CE030 + + +/////////////////////////////////////////////////////////////////// + + + + + + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +// ukss +////////////////////////////////////////////////////////////////// +#define ADR_CAN_NUMBER1_ON_ZAD 0x00 +#define ADR_CAN_NUMBER2_ON_ZAD 0x01 +#define ADR_CAN_LAMPS_ON_ZAD 0x02 +#define ADR_CAN_LAMPS_2_ON_ZAD 0x03 +#define ADR_CAN_KEY_ON_ZAD 0x10 + +////////////////////////////////////// +////////////////////////////////////// + +#define CAN_SPEED_UKSS8 10 +#define CAN_SPEED_VPU1 20 +#define CAN_SPEED_VPU2 20 +#define CAN_SPEED_UMP1 5//30 + +//#define ADR_CAN_SPEED 99 +//#define ADR_CAN_LENGTH_FINISH_ADR 97 +//#define ADR_CAN_CMD 127 +//#define ADR_CAN_KEY_ON_VPU 16 // +//#define ADR_CAN_DOOR 0 // + + +////////////////////////////////////// +////////////////////////////////////// + + + +#endif /* SRC_MAIN_CAN_PROJECT_H_ */ diff --git a/Inu/Src2/551/main/Main.c b/Inu/Src2/551/main/Main.c new file mode 100644 index 0000000..9716206 --- /dev/null +++ b/Inu/Src2/551/main/Main.c @@ -0,0 +1,126 @@ +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" + +#include +#include "RS_Functions.h" +#include "xp_project.h" +#include "x_wdog.h" + +void main() +{ + // Step 1. Initialize System Control: + // PLL, WatchDog, enable Peripheral Clocks + // This example function is found in the DSP281x_SysCtrl.c file. + InitSysCtrl(); + + XintfZone0_Timing();//Xilinx Zone + XintfZone6_And7_Timing();//Flash Zone + XintfZone2_Timing();//External RAM Zone + + // Step 2. Initalize GPIO: + // This example function is found in the DSP281x_Gpio.c file and + // illustrates how to set the GPIO to it's default state. + // InitGpio(); // Skipped for this example + + // For this example use the following configuration: + //Gpio_select(); + + // Step 3. Clear all interrupts and initialize PIE vector table: + // Disable CPU interrupts + DINT; + +// status_interrupts = __disable_interrupts(); + + // Initialize PIE control registers to their default state. + // The default state is all PIE interrupts disabled and flags + // are cleared. + // This function is found in the DSP281x_PieCtrl.c file. + + InitPieCtrl(); + +// __disable_interrupts(); + + // Disable CPU interrupts and clear all CPU interrupt flags: + IER = 0x0000; + IFR = 0x0000; + + // Initialize the PIE vector table with pointers to the shell Interrupt + // Service Routines (ISR). + // This will populate the entire table, even if the interrupt + // is not used in this example. This is useful for debug purposes. + // The shell ISR routines are found in DSP281x_DefaultIsr.c. + // This function is found in DSP281x_PieVect.c. + + InitPieVectTable(); + + // Step 4. Initialize all the Device Peripherals: + // This function is found in DSP281x_InitPeripherals.c + // InitPeripherals(); // Not required for this example + + FlashInit(); + + SetupLedsLine(); +//while(1) +{ + i_led2_on_off(0); + i_led1_on_off(1); + DELAY_US(500000); + i_led2_on_off(1); + i_led1_on_off(0); + DELAY_US(500000); + i_led2_on_off(0); + i_led1_on_off(0); +} + + + RS232_TuneUp(RS232_SPEED_A, RS232_SPEED_B); + + KickDog(); + + // , ! + edrk_init_before_main(); + + // , RS232 + project.enable_all_interrupt(); + + + DINT; + i_led2_on_off(1); + i_led1_on_off(1); + DELAY_US(500000); + i_led2_on_off(0); + i_led1_on_off(0); + DELAY_US(500000); + i_led2_on_off(1); + i_led1_on_off(1); + DELAY_US(500000); + i_led2_on_off(0); + i_led1_on_off(0); + DELAY_US(500000); + project.enable_all_interrupt(); + + // + edrk_init_before_loop(); + + // main + for(;;) + { + // , + + edrk_go_main(); + // rs232 + RS232_WorkingWith(1,0,0); +// static int fff=0; +// if (fff) +// { +// Answer(&rs_a, CMD_RS232_POKE); +// fff = 0; +// } + + } + + +} + + diff --git a/Inu/Src2/551/main/PWMTMSHandle.c b/Inu/Src2/551/main/PWMTMSHandle.c new file mode 100644 index 0000000..2fe71b1 --- /dev/null +++ b/Inu/Src2/551/main/PWMTMSHandle.c @@ -0,0 +1,510 @@ + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File + + +#include +#include +#include +#include +#include +#include + +#include "CAN_Setup.h" +#include "global_time.h" +#include "RS_Functions.h" + + + +int + m_PWM = 1, /* 1- , 0- */ + Dpwm = 12500, + Fpwm = 1000, + Dpwm2 = 6250, + Dpwm4 = 3125, + Zpwm = 1; // +//TODO +static int mPWM_a = 0, mPWM_b = 0; // b 1 - ., 0 - . + +PWMGEND pwmd = PWMGEND_DEFAULTS; + + +#if (TMSPWMGEN==1) + +#define DMIN 750 // 15mks Dminimum + +interrupt void PWM_Handler(void) +{ + +// static unsigned int time_tick_sec_mks=0; + static unsigned int pwm_run=0; + + // Enable more interrupts from this timer + EvaRegs.EVAIMRA.bit.T1PINT = 1; + + // Note: To be safe, use a mask value to write to the entire + // EVAIFRA register. Writing to one bit will cause a read-modify-write + // operation that may have the result of writing 1's to clear + // bits other then those intended. + EvaRegs.EVAIFRA.all = BIT7; + + // Acknowledge interrupt to receive more interrupts from PIE group 2 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + + + + // PWM_ticks++; + + if (pwm_run==1) + { +// stop_pwm(); + } + else + { + + pwm_run=1; + + + EnableInterrupts(); + + + // if (time_tick_sec_mks>FREQ_PWM) +// { +// time_tick_sec++; +// time_tick_sec_mks=0; + // } +// else + // time_tick_sec_mks++; + + // rs_a.time_wait_rs_out++; +// rs_b.time_wait_rs_out++; + // rs_a.time_wait_rs_out_mpu++; +// rs_b.time_wait_rs_out_mpu++; + + + global_time.calc(&global_time); + inc_RS_timeout_cicle(); + inc_CAN_timeout_cicle(); + +// led1_on_off(1); + PWM_interrupt(); /* y */ +// led1_on_off(0); + + pwm_run=0; + + } +/* + // Enable more interrupts from this timer + EvaRegs.EVAIMRA.bit.T1PINT = 1; + + // Note: To be safe, use a mask value to write to the entire + // EVAIFRA register. Writing to one bit will cause a read-modify-write + // operation that may have the result of writing 1's to clear + // bits other then those intended. + EvaRegs.EVAIFRA.all = BIT7; + + // Acknowledge interrupt to receive more interrupts from PIE group 2 + PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + +*/ + +// led2_on_off(0); +// disable(); /* y TMS */ + + +// SCIb_RX_Int_enable(); +// SCIa_RX_Int_enable(); + + + +} +#endif + + +#if (TMSPWMGEN==1) +void init_eva_evb() +{ + +// unsigned int tload; + +// stop_pwm(); + + EALLOW; + +// EVA Configure T1PWM, T2PWM, PWM1-PWM6 +// Initalize the timers + // Initalize EVA Timer1 + + + PieVectTable.T1PINT=&PWM_Handler; + + + EvaRegs.EVAIMRA.bit.T1PINT = 1; + EvaRegs.EVAIFRA.bit.T1PINT = 1; + // Enable PIE group 2 interrupt 4 for T1PINT + PieCtrlRegs.PIEIER2.bit.INTx4 = 1; + + +// EvaRegs.EVAIFRA.bit.T1OFINT=1; +// PieVectTable.T1OFINT = &PWM_Handler2; +// EvaRegs.EVAIMRA.bit.T1OFINT = 1; +// EvaRegs.EVAIFRA.bit.T1OFINT = 1; + // Enable PIE group 2 interrupt 7 for T1PINT +// PieCtrlRegs.PIEIER2.bit.INTx7 = 1; + + +//#ifdef DOUBLE_UPDATE_PWM + +// PieVectTable.T1UFINT = &PWM_Handler2; +// EvaRegs.EVAIMRA.bit.T1UFINT = 1; +// EvaRegs.EVAIFRA.bit.T1UFINT = 1; + + // Enable PIE group 2 interrupt 7 for T1PINT +// PieCtrlRegs.PIEIER2.bit.INTx6 = 1; + +//#endif + + +// EvaRegs.EVAIFRA.bit.T1CINT=1; +// PieVectTable.T1CINT = &PWM_Handler2; +// EvaRegs.EVAIMRA.bit.T1CINT = 1; +// EvaRegs.EVAIFRA.bit.T1CINT = 1; + // Enable PIE group 2 interrupt 7 for T1PINT +// PieCtrlRegs.PIEIER2.bit.INTx5 = 1; + + + IER |= M_INT2; + + EDIS; +// start_pwm(); + + +} +#endif + + +#if (TMSPWMGEN==1) +void setup_tms_pwm_int(int pwm_freq, int one_two, int pwm_protect) +{ + + + float64 pwm_period; +// pwm_tick; + +// int prev_interrupt; + + // init_vector(); + +// f_disable(); /* y TMS */ +// *(int *)(VECT_TABLE + VECT_INT2) = (int)PWM_Handler; /* */ +// SET_IEMASK_INT2(); /* y */ + + pwm_period = (float64)HSPCLK/(float64)pwm_freq/2.0; + + Fpwm = (int)pwm_freq; + Dpwm = (int)pwm_period; + Dpwm2 = (int)(pwm_period/2); + Dpwm4 = (int)(pwm_period/4); + + // stop_pwm(); /* */ + // setup_pwm_out(); + + + + + init_eva_evb(); + + + + + EvbRegs.EVBIFRA.bit.PDPINTB=1; + EvaRegs.EVAIFRA.bit.PDPINTA=1; + +// EVBIFRB + // Initialize PWM module + pwmd.PeriodMax = Dpwm; // Perscaler X1 (T1), ISR period = T x 1 + pwmd.PeriodMin = DMIN; // Perscaler X1 (T1), ISR period = T x 1 + +// ARpwmd.PeriodMax = Dpwm; +// ARpwmd.PeriodMin = DMIN; +// + pwmd.ShiftPhaseA = 0;//Dpwm/6.0; + pwmd.ShiftPhaseB = 0; + + pwmd.init(&pwmd); + +// ARpwmd.init(&pwmd); + // m.m2.bit.WDog_pwm = 0; + + + +/* pwm1.PeriodMax = Dpwm; // Perscaler X1 (T1), ISR period = T x 1 + pwm1.init(&pwm1); + + pwm2.PeriodMax = Dpwm; // Perscaler X1 (T1), ISR period = T x 1 + pwm2.init(&pwm2); */ + + +// if(one_two < 1.5) one_two = 0; +// if(one_two > 1.5) one_two = 0x80000000; + + +// addr_xilinx(WG_COUNT) = pwm_divisor; /* */ +// addr_xilinx(WG_PERIOD) = Dpwm<<16; /* */ +// addr_xilinx(ADR_INT) = one_two; /* */ +// addr_xilinx(WG_PROTECT) = pwm_protect; /* */ + + + +//Invoking the computation function +//svgen_mf1. + +// Initialize the SVGEN_MF module +/* + svgen_mf1.FreqMax = _IQ(6*BASE_FREQ*T); + svgen_mf2.FreqMax = _IQ(6*BASE_FREQ*T); + + + svgen_mf2.Offset=_IQ(0); + svgen_mf1.Offset=_IQ(0); + + svgen_mf1.Alpha = _IQ(0); + svgen_mf2.Alpha = _IQ(0.52359877559829887307710723054658); + + + k=0.1; //0.9; + freq = 0.499; + +*/ +//svgen_mf1.calc(&svgen_mf1); +//svgen_mf2.calc(&svgen_mf2); + +// start_pwm_a(); +// start_pwm_b(); + + + i_WriteMemory(ADR_PWM_DRIVE_MODE, 0x0000); // TMS + +} +#endif + +/********************************************************************/ +/* */ +/********************************************************************/ +void start_tms_pwm_a() +{ + unsigned int mask_tk_lines; + mPWM_a = 1; + + + EALLOW; + EvaRegs.COMCONA.all = 0xa600;//0xA600; // Init COMCONA Register + + EvaRegs.ACTRA.all = 0x0999; + EDIS; + + +} + +void start_tms_pwm_b() +{ + unsigned int mask_tk_lines; + mPWM_b = 1; + + + EALLOW; + EvbRegs.COMCONB.all = 0xa600;//0xA600; // Init COMCONA Register + + EvbRegs.ACTRB.all = 0x0999; + EDIS; + + + +} + + + +void start_tms_pwm(void) +{ + mPWM_a = 1; + mPWM_b = 1; + + + m_PWM = 0; + // m.m1.bit.PWM=0; + // m.m1.bit.PWM_A=0; + // m.m1.bit.PWM_B=0; + + EALLOW; + // addr_xilinx(WG_OUT)=0x00; + + EvaRegs.COMCONA.all = 0xa600;//0xA600; // Init COMCONA Register + EvbRegs.COMCONB.all = 0xa600;//0xA600; // Init COMCONA Register + + EvaRegs.ACTRA.all = 0x0999; + EvbRegs.ACTRB.all = 0x0999; + +// EvaRegs.GPTCONA.bit.TCMPOE=0; +// EvbRegs.GPTCONB.bit.TCMPOE=0; +// EvaRegs.T1CON.bit.TECMPR=1; +// EvbRegs.T3CON.bit.TECMPR=1; + EDIS; + +} + +/********************************************************************/ +/* */ +/********************************************************************/ +void start_select_tms_pwm(unsigned int mask) +{ + unsigned int mask_pwm_a,mask_pwm_b; + unsigned char b,i; + + + EALLOW; + + + + EvaRegs.ACTRA.all = 0x0fff; + EvbRegs.ACTRB.all = 0x0fff; + + EvaRegs.COMCONA.all = 0xa600;//0xA600; // Init COMCONA Register + EvbRegs.COMCONB.all = 0xa600;//0xA600; // Init COMCONA Register + + + mask_pwm_a=0; + for (i=0;i<6;i++) + { + b=(mask >> i) & 1; + if (b==0) + mask_pwm_a |= (1 << (2*i) ); + else + mask_pwm_a |= (3 << (2*i) ); + + + } + + mask_pwm_b=0; + for (i=0;i<6;i++) + { + b=(mask >> (i+8)) & 1; + if (b==0) + mask_pwm_b |= (1 << (2*i) ); + else + mask_pwm_b |= (3 << (2*i) ); + + } + + EvaRegs.ACTRA.all = mask_pwm_a; + EvbRegs.ACTRB.all = mask_pwm_b; + + EDIS; +} + + +/********************************************************************/ +/* */ +/********************************************************************/ +//#pragma CODE_SECTION(stop_pwm,".fast_run"); +void stop_tms_pwm(void) +{ + mPWM_a = 0; + mPWM_b = 0; + + + m_PWM = 1; + // m.m1.bit.PWM=1; + // m.m1.bit.PWM_A=1; + // m.m1.bit.PWM_B=1; + + EALLOW; + // EvaRegs.GPTCONA.bit.TCMPOE=1; + // EvbRegs.GPTCONB.bit.TCMPOE=1; + // EvaRegs.T1CON.bit.TECMPR=0; + // EvbRegs.T3CON.bit.TECMPR=0; + + // addr_xilinx(WG_OUT)=0x0fff; // + EvaRegs.ACTRA.all = 0x0fff; + EvbRegs.ACTRB.all = 0x0fff; + + // EvaRegs.COMCONA.all = 0xa400;//0xA600; // Init COMCONA Register + // EvbRegs.COMCONB.all = 0xa400;//0xA600; // Init COMCONA Register + + // EvaRegs.COMCONA.bit.FCMP6OE=0; + + + + //EvbRegs.COMCONB.bit.FCOMPOE=0; + //EvaRegs.COMCONA.bit.CENABLE=0; + //EvbRegs.COMCONB.bit.CENABLE=0; + + + EDIS; + + +} + +void stop_tms_pwm_a() +{ + unsigned int mask_tk_lines; +// m_PWM = 1; + mPWM_a = 0; + + EALLOW; + EvaRegs.ACTRA.all = 0x0fff; + EDIS; + +} + + +void stop_tms_pwm_b() +{ + unsigned int mask_tk_lines; + m_PWM = 1; + mPWM_b = 0; + + + + EALLOW; + EvbRegs.ACTRB.all = 0x0fff; + EDIS; + +} + +void setup_tms_pwm_out(void) +{ +//int b; +#if (TMSPWMGEN==1) + EALLOW; + +// GpioMuxRegs.GPDMUX.bit.T3CTRIP_PDPB_GPIOD5=0; +// GpioMuxRegs.GPDDIR.bit.GPIOD5=0; +// GpioDataRegs.GPDSET.bit.GPIOD5=1; + + +// GpioDataRegs.GPDCLEAR.bit.GPIOD5=1; + + + + GpioMuxRegs.GPAMUX.bit.PWM1_GPIOA0=1; + GpioMuxRegs.GPAMUX.bit.PWM2_GPIOA1=1; + GpioMuxRegs.GPAMUX.bit.PWM3_GPIOA2=1; + GpioMuxRegs.GPAMUX.bit.PWM4_GPIOA3=1; + GpioMuxRegs.GPAMUX.bit.PWM5_GPIOA4=1; + GpioMuxRegs.GPAMUX.bit.PWM6_GPIOA5=1; + + GpioMuxRegs.GPBMUX.bit.PWM7_GPIOB0=1; + GpioMuxRegs.GPBMUX.bit.PWM8_GPIOB1=1; + GpioMuxRegs.GPBMUX.bit.PWM9_GPIOB2=1; + GpioMuxRegs.GPBMUX.bit.PWM10_GPIOB3=1; + GpioMuxRegs.GPBMUX.bit.PWM11_GPIOB4=1; + GpioMuxRegs.GPBMUX.bit.PWM12_GPIOB5=1; + + EDIS; + // +// write_memory(adr_oe_buf_v,0); +#endif +} + + + diff --git a/Inu/Src2/551/main/PWMTMSHandle.h b/Inu/Src2/551/main/PWMTMSHandle.h new file mode 100644 index 0000000..ab1675c --- /dev/null +++ b/Inu/Src2/551/main/PWMTMSHandle.h @@ -0,0 +1,25 @@ +#ifndef _PWMTMSHANDLE_H +#define _PWMTMSHANDLE_H + +void setup_tms_pwm_out(void); +void start_tms_pwm(void); +void stop_tms_pwm(void); + +void start_tms_pwm_b(); +void start_tms_pwm_a(); +void stop_tms_pwm_a(); +void stop_tms_pwm_b(); + + +void setup_tms_pwm_int(int pwm_freq, int one_two, int pwm_protect); + +void start_break_pwm(void); +void stop_break_pwm(void); + + + + + + +#endif + diff --git a/Inu/Src2/551/main/PWMTools.c b/Inu/Src2/551/main/PWMTools.c new file mode 100644 index 0000000..b62f7b3 --- /dev/null +++ b/Inu/Src2/551/main/PWMTools.c @@ -0,0 +1,2438 @@ +#include +#include +#include +#include +#include +#include //22.06 +#include +#include +#include +#include +//#include +#include +#include +#include //22.06 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "f281xpwm.h" + +//#include "SpaceVectorPWM.h" +#include "CAN_Setup.h" +#include "global_time.h" +#include "IQmathLib.h" +#include "mathlib.h" +#include "oscil_can.h" +#include "rmp_cntl_v1.h" +#include "uf_alg_ing.h" +#include "vhzprof.h" +#include "vector_control.h" +#include "MemoryFunctions.h" +#include "RS_Functions.h" +#include "TuneUpPlane.h" +#include "xp_write_xpwm_time.h" +#include "pwm_test_lines.h" +#include "detect_errors.h" +#include "modbus_table_v2.h" +#include "params_alg.h" +#include "v_rotor_22220.h" +#include "log_to_memory.h" +#include "log_params.h" +#include "limit_power.h" +#include "pwm_logs.h" +#include "optical_bus_tools.h" +#include "ramp_zadanie_tools.h" +#include "pll_tools.h" + + +///////////////////////////////////// +#if (_SIMULATE_AC==1) +#include "sim_model.h" +#endif + +//#pragma DATA_SECTION(freq1,".fast_vars1"); +//_iq freq1; + +//#pragma DATA_SECTION(k1,".fast_vars1"); +//_iq k1 = 0; + +#define ENABLE_LOG_INTERRUPTS 0 //1 + + +#if (ENABLE_LOG_INTERRUPTS) + +#pragma DATA_SECTION(log_interrupts,".slow_vars"); +#define MAX_COUNT_LOG_INTERRUPTS 100 +unsigned int log_interrupts[MAX_COUNT_LOG_INTERRUPTS+2] = {0}; + + + + +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + + +void add_log_interrupts(int cmd) +{ + static int count_log_interrupst = 0; + + if (count_log_interrupst>=MAX_COUNT_LOG_INTERRUPTS) + count_log_interrupst = 0; + + + log_interrupts[count_log_interrupst++] = cmd; + log_interrupts[count_log_interrupst++] = EvbRegs.T3CNT; + + +//#if (ENABLE_LOG_INTERRUPTS) +// add_log_interrupts(0); +//#endif + +} + +#endif //if (ENABLE_LOG_INTERRUPTS) + + + +#pragma DATA_SECTION(iq_U_1_save,".fast_vars1"); +_iq iq_U_1_save = 0; +#pragma DATA_SECTION(iq_U_2_save,".fast_vars1"); +_iq iq_U_2_save = 0; + + +unsigned int enable_calc_vector = 0; + + + +//WINDING winding1 = WINDING_DEFAULT; + +//#define COUNT_SAVE_LOG_OFF 50 // +#define COUNT_START_IMP 5 //10 + +#define CONST_005 838860 +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + + +#pragma CODE_SECTION(global_time_interrupt,".fast_run2"); +void global_time_interrupt(void) +{ + +// inc_RS_timeout_cicle(); +// inc_CAN_timeout_cicle(); + +#if(_ENABLE_PWM_LINES_FOR_TESTS) +// PWM_LINES_TK_18_ON; +#endif + + if (edrk.disable_interrupt_timer3) + return; + +//i_led1_on_off(1); + + + if (sync_data.latch_interrupt && sync_data.enabled_interrupt) + { + // ! + // + start_sync_interrupt(); + } + +#if (ENABLE_LOG_INTERRUPTS) + add_log_interrupts(1); +#endif + + global_time.calc(&global_time); + +#if (ENABLE_LOG_INTERRUPTS) + add_log_interrupts(101); +#endif + +/* +static unsigned int oldest_time = 0, time_pause = TIME_PAUSE_MODBUS_REMOUTE; +control_station_test_alive_all_control(); + if (detect_pause_milisec(time_pause,&oldest_time)) + modbusNetworkSharing(0); + + RS232_WorkingWith(0,1); +*/ + + +//i_led1_on_off(0); +#if(_ENABLE_PWM_LINES_FOR_TESTS) + // PWM_LINES_TK_18_OFF; +#endif +} + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +//#define get_tics_timer_pwm2(k) {time_buf2[k] = (EvbRegs.T3CNT-start_tics_4timer);k++;} +//unsigned int time_buf2[10] = {0}; + + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +#define PAUSE_INC_TIMEOUT_CICLE 10 // FREQPWM/10 +void pwm_inc_interrupt(void) +{ + static unsigned int t_inc = 0; + + if (t_inc>=PAUSE_INC_TIMEOUT_CICLE) + { + inc_RS_timeout_cicle(); + inc_CAN_timeout_cicle(); + t_inc = 0; + } + else + t_inc++; +} +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(pwm_analog_ext_interrupt,".fast_run2"); +void pwm_analog_ext_interrupt(void) +{ +// static int count_timer_buf2=0, start_tics_4timer = 0, c_rms = 0; +// static _iq prev_Iu=0, prev_Ua=0; + //static _iq iq_50hz_norma = _IQ(50.0/NORMA_FROTOR); + +// i_led2_on(); + + // +// start_tics_4timer = EvaRegs.T1CNT; + +// count_timer_buf2 = 0; +// get_tics_timer_pwm2(count_timer_buf2); + + if (edrk.SumSbor == 1) { +// detect_protect_adc(uf_alg.tetta_bs, uf_alg.tetta_bs); + } + + + + calc_pll_50hz(); + +// +// if (c_rms>=9) +// { +// edrk.test_rms_Iu = calc_rms(analog.iqIu,prev_Iu,edrk. f_stator); +// edrk.test_rms_Ua = calc_rms(analog.iqUin_A1B1,prev_Ua, iq_50hz_norma); +// +// prev_Iu = analog.iqIu; +// prev_Ua = analog.iqUin_A1B1; +// c_rms = 0; +// } +// else +// c_rms++; + +// fill_RMS_buff_interrupt(uf_alg.tetta_bs, uf_alg.tetta_bs); + + // get_tics_timer_pwm2(count_timer_buf2); +// i_led2_off(); + + +// global_time.calc(&global_time); + +} +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + +inline void init_regulators() +{ +// if(f.Mode != 0) +// { +//// pwm_vector_model_titov(0, 0, /*rotor.iqW*/0, 0); +// } +} + +#define select_working_channels(go_a, go_b) {go_a = !f.Obmotka1; \ + go_b = !f.Obmotka2;} + +#define MAX_COUNT_WAIT_GO_0 FREQ_PWM // 1 . + + +#define PAUSE_ERROR_DETECT_UPDATE_OPTBUS_DATA 900// ((unsigned int)(1*FREQ_PWM*2)) // ~1sec //50 +#define MAX_TIMER_WAIT_SET_TO_ZERO_ZADANIE 27000 //((unsigned int)(30*FREQ_PWM*2)) // 60 sec +//#define MAX_TIMER_WAIT_BOTH_READY2 108000 //(120*FREQ_PWM*2) // 120 sec +#define MAX_TIMER_WAIT_BOTH_READY2 216000 //(120*FREQ_PWM*2) // 240 sec +#define MAX_TIMER_WAIT_MASTER_SLAVE 4500 // 5 sec + +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +//#define _ENABLE_PWM_LED2_PROFILE 1 + + +#if (_ENABLE_PWM_LED2_PROFILE) +unsigned int profile_pwm[30]={0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0}; +unsigned int pos_profile_pwm = 0; +#endif + +/////////////////////////////////////////////////////////////////// +#define _ENABLE_LOG_TICS_PWM 0//1 +#define _ENABLE_SLOW_PWM 0//1 +#define _ENABLE_INTERRUPT_PWM_LED2 0//1 + +#if (_ENABLE_LOG_TICS_PWM==1) + +static int c_run=0; +static int c_run_start=0; +static int i_log; + + +#pragma DATA_SECTION(time_buf,".slow_vars"); +#define MAX_COUNT_TIME_BUF 50 +int time_buf[MAX_COUNT_TIME_BUF] = {0}; + +//#define get_tics_timer_pwm(flag,k) {if (flag) {time_buf[k] = (unsigned int)(EvbRegs.T3CNT-start_tics_4timer);k++;}else{time_buf[k] = -1; k++;}} + +#define set_tics_timer_pwm(flag,k) { time_buf[k] = flag;k++; } + +//#define get_tics_timer_pwm(flag,k) if (flag) ? {time_buf[k] = (EvbRegs.T3CNT-start_tics_4timer);k++;} : {time_buf[k] = -1; k++;}; +static int count_timer_buf=0; + +#else + +#define get_tics_timer_pwm(flag) asm(" NOP;") +#define set_tics_timer_pwm(flag,k) asm(" NOP;") +//static int count_timer_buf=0; + +#endif + + +#if(_ENABLE_SLOW_PWM) +static int slow_pwm_pause = 0; +#endif + +unsigned int count_time_buf = 0; +int stop_count_time_buf=0; +unsigned int log_wait; + +unsigned int end_tics_4timer, start_tics_4timer; +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////// +#if (_ENABLE_LOG_TICS_PWM==1) +//#pragma CODE_SECTION(get_tics_timer_pwm,".fast_run"); +void get_tics_timer_pwm(unsigned int flag) +{ + unsigned int delta; + + if (flag) + { + delta = (unsigned int)(EvbRegs.T3CNT-start_tics_4timer); + if (count_timer_buf>=3) + time_buf[count_timer_buf] = delta - time_buf[count_timer_buf-2]; + else + time_buf[count_timer_buf] = delta; + time_buf[count_timer_buf] = time_buf[count_timer_buf]*33/1000; + count_timer_buf++; + } + else + { + time_buf[count_timer_buf] = -1; + count_timer_buf++; + } +} +#else + +#endif + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////// +// +/////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(calc_rotors,".fast_run"); +void calc_rotors(int flag) +{ + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_17_ON; +#endif + + update_rot_sensors(); + + + + set_tics_timer_pwm(6,count_timer_buf); + get_tics_timer_pwm(flag); + + +#if(C_cds_in_number>=1) + project.cds_in[0].read_pbus(&project.cds_in[0]); + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_17_OFF; +#endif + +#if (_ENABLE_PWM_LED2_PROFILE) + if (profile_pwm[pos_profile_pwm++]) + i_led2_on_off(1); + else + i_led2_on_off(0); +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_19_ON; +#endif + +#if(SENSOR_ALG==SENSOR_ALG_23550) +// 23550 + RotorMeasureDetectDirection(); + RotorMeasure();// +#endif + +#if(SENSOR_ALG==SENSOR_ALG_22220) +// 22220 + Rotor_measure_22220(); + +#if (_ENABLE_PWM_LED2_PROFILE) + if (profile_pwm[pos_profile_pwm++]) + i_led2_on_off(1); + else + i_led2_on_off(0); +#endif + +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_19_OFF; +#endif + + set_tics_timer_pwm(7,count_timer_buf); + get_tics_timer_pwm(flag); + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_20_ON; +#endif + +// RotorMeasurePBus(); +#if(SENSOR_ALG==SENSOR_ALG_23550) +// 23550 + RotorDirectionFilter(WRotorPBus.RotorDirectionInstant, &WRotorPBus.RotorDirectionSlow, &WRotorPBus.RotorDirectionSlow2, &WRotorPBus.RotorDirectionCount); +#endif + +#if(SENSOR_ALG==SENSOR_ALG_22220) + // 22220 + // nothing +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_20_OFF; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_20_ON; +#endif + +#if(SENSOR_ALG==SENSOR_ALG_23550) +// 23550 + select_values_wrotor(); +#endif +#if(SENSOR_ALG==SENSOR_ALG_22220) +// 22220 + select_values_wrotor_22220(); + +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_20_OFF; +#endif + + set_tics_timer_pwm(8,count_timer_buf); + get_tics_timer_pwm(flag); + +#endif //(C_cds_in_number>=1) + + + edrk.rotor_direction = WRotor.RotorDirectionSlow; + +#if(SENSOR_ALG==SENSOR_ALG_23550) +// 23550 + edrk.iq_f_rotor_hz = WRotor.iqWRotorSumFilter; +#endif + +#if(SENSOR_ALG==SENSOR_ALG_22220) +// 22220 + edrk.iq_f_rotor_hz = WRotor.iqWRotorSum; +#endif + +} + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(calc_zadanie_rampa,".fast_run"); +void calc_zadanie_rampa(void) +{ +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_19_ON; +#endif + + + // + load_current_ramp_oborots_power(); + + if (edrk.StartGEDfromControl==0) + ramp_all_zadanie(2); // + else + if (edrk.flag_wait_set_to_zero_zadanie || edrk.flag_block_zadanie || edrk.Status_Ready.bits.ready_final==0 || /*edrk.StartGEDfromControl==0 ||*/ edrk.run_razbor_shema == 1) + ramp_all_zadanie(1); // , , edrk.StartGEDfromZadanie + else + ramp_all_zadanie(0); // + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_19_OFF; +#endif + +} + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(async_pwm_ext_interrupt,".fast_run2"); +void async_pwm_ext_interrupt(void) +{ + +#if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) + PWM_LINES_TK_19_ON; +#endif + if (edrk.run_to_pwm_async) + { + PWM_interrupt(); + edrk.run_to_pwm_async = 0; + } + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) + PWM_LINES_TK_19_OFF; +#endif + +} +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// +void run_detect_fast_error(void) +{ + + detect_error_u_zpt_fast(); + detect_error_u_in(); + +} +//////////////////////////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(PWM_interrupt_main,".fast_run"); +void PWM_interrupt_main(void) +{ + +#if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) + PWM_LINES_TK_16_ON; +#endif + + norma_adc_nc(0); + + edrk.run_to_pwm_async = 1; + +#if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) + PWM_LINES_TK_16_OFF; +#endif + +} +//////////////////////////////////////////////////////////////////////////////// + + +#define MAX_COUNT_COUNTSTARTGEDFROMZADANIE FREQ_PWM //3000 // edrk.StartGEDfromZadanie + + + +#pragma CODE_SECTION(PWM_interrupt,".fast_run"); +void PWM_interrupt(void) +{ + + static unsigned int pwm_run = 0; + static _iq Uzad1=0, Fzad=0, Uzad2=0, Izad_out = 0, Uzad_from_master = 0; + +// static int count_step_ram_off = 0; +// static int count_start_impuls = 0; + + static int prevGo = -1; + static volatile unsigned int go_a = 0; + static volatile unsigned int go_b = 0; + + static int prev_go_a = 0; + static int prev_go_b = 0; + + static _iq iq_U_1_prev = 0; + static _iq iq_U_2_prev = 0; + static unsigned int prev_timer = 0; + unsigned int cur_timer; + static unsigned int count_lost_interrupt=0; + static int en_rotor = 1;//1; + + static unsigned long timer_wait_set_to_zero_zadanie = 0; + static unsigned long timer_wait_both_ready2 = 0; + + static unsigned int prev_error_controller = 0,error_controller=0; + + static unsigned long time_delta = 0; + + static unsigned int run_calc_uf = 0, prev_run_calc_uf = 0, count_wait_go_0 = 0; + + int pwm_enable_calc_main = 0, pwm_up_down = 0, err_interr = 0, slow_error = 0; + + static unsigned int count_err_read_opt_bus = 0, prev_edrk_Kvitir = 0; + + static unsigned int count_wait_read_opt_bus = 0, old_count_ok = 0, data_ready_optbus = 0, count_ok_read_opt_bus = 0; + +// static T_cds_optical_bus_data_in buff[25]={0}; + static unsigned int flag_last_error_read_opt_bus = 0, sum_count_err_read_opt_bus1=0; + + static unsigned int count_read_slave = 0, flag1_change_moment_read_optbus = 0, flag2_change_moment_read_optbus = 0; + + static unsigned int count_updated_sbus = 0, prev_ManualDischarge = 0; + + static unsigned int prev_flag_detect_update_optbus_data=0, flag_detect_update_optbus_data = 0, pause_error_detect_update_optbus_data = 0; + static unsigned int timer_wait_to_master_slave = 0; + static unsigned int prev_master = 0; + + static int pwm_enable_calc_main_log = 1; + + static int what_pwm = 0; + + int localStartGEDfromZadanie; + static unsigned int countStartGEDfromZadanie = 0; + + +// OPTICAL_BUS_CODE_STATUS optbus_status = {0}; + static STATUS_DATA_READ_OPT_BUS optbus_status; + _iq wd; + +// if (edrk.disable_interrupt_sync==0) +// start_sync_interrupt(); + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_16_ON; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_16_ON; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS) +// PWM_LINES_TK_16_ON; +#endif + + + +#if (_ENABLE_INTERRUPT_PWM_LED2) +i_led2_on_off(1); +#endif + + if (edrk.disable_interrupt_pwm) + { + pwm_inc_interrupt(); + return; + } + + if (flag_special_mode_rs==1) + { + calc_norm_ADC_0(1); + calc_norm_ADC_1(1); + pwm_inc_interrupt(); + + return; + } + +#if (_ENABLE_PWM_LED2_PROFILE) + pos_profile_pwm = 0; +#endif + + + +#if (_ENABLE_PWM_LED2_PROFILE) + if (profile_pwm[pos_profile_pwm++]) + i_led2_on_off(1); + else + i_led2_on_off(0); +#endif + + +// if (xpwm_time.what_next_interrupt==PWM_LOW_LEVEL_INTERRUPT) +// { +//#if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) +// PWM_LINES_TK_17_ON; +//#endif +// +// i_sync_pin_on(); +// +// } +// else +// { +//#if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) +// PWM_LINES_TK_17_OFF; +//#endif +// +// i_sync_pin_off(); +// } + + + +//////////////// +//PWN_COUNT_RUN_PER_INTERRUPT PWM_TWICE_INTERRUPT_RUN + err_interr = detect_level_interrupt(edrk.flag_second_PCH); + + if (err_interr) + edrk.errors.e3.bits.ERR_INT_PWM_LONG |=1; + + if (xpwm_time.one_or_two_interrupts_run == PWM_ONE_INTERRUPT_RUN) + pwm_up_down = 2; + else + if (xpwm_time.where_interrupt == PWM_LOW_LEVEL_INTERRUPT) + { + pwm_up_down = 0; + } + else + pwm_up_down = 1; + + // sync line + if (pwm_up_down==2 || pwm_up_down==0) + { +// what_pwm = 0; + // i_sync_pin_on(); + calculate_sync_detected(); + } + +///////////////// +#if (ENABLE_LOG_INTERRUPTS) + add_log_interrupts(3); +#endif + + +#if (_ENABLE_LOG_TICS_PWM==1) + + count_timer_buf = 0; + // optical_read_data.timer=0; +#endif + + +#if (_FLOOR6==0) +// if (edrk.Stop==0) +// i_led1_on_off(1); +#else + // i_led1_on_off(1); +#endif + + + edrk.into_pwm_interrupt = 1; + + // + start_tics_4timer = EvbRegs.T3CNT; + cur_timer = global_time.pwm_tics; + if (prev_timer>cur_timer) + { + if ((prev_timer-cur_timer)<2) + { +// stop_pwm(); + edrk.count_lost_interrupt++; + } + } + else + { + if ((cur_timer==prev_timer) || (cur_timer-prev_timer)>2) + { +// stop_pwm(); + edrk.count_lost_interrupt++; + } + } + prev_timer = cur_timer; + // + + set_tics_timer_pwm(1,count_timer_buf); + get_tics_timer_pwm(1); + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_17_ON; +#endif + +#if (_SIMULATE_AC==1) + calc_norm_ADC_0_sim(0); +#else + calc_norm_ADC_0(0); // norma Pwm_main() +#endif + run_detect_fast_error(); // + + + + ///////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////// + if (edrk.Kvitir==0 && prev_edrk_Kvitir==1) + { + count_err_read_opt_bus = 0; + edrk.sum_count_err_read_opt_bus = 0; + } + + set_tics_timer_pwm(2,count_timer_buf); + get_tics_timer_pwm(1); + + ////////////////////////////// +// inc_RS_timeout_cicle(); + //////////////////////////////// + //////////////////////////////////////////// + //////////////////////////////////////////// +// inc_CAN_timeout_cicle(); + //////////////////////////////////////////// + + if (edrk.ms.another_bs_maybe_on==1 && + (edrk.auto_master_slave.local.bits.master || edrk.auto_master_slave.local.bits.slave) ) + { + + flag_detect_update_optbus_data = 1; + + if (prev_flag_detect_update_optbus_data == 0) + pause_error_detect_update_optbus_data = 0; + + + count_updated_sbus = optical_read_data.data_was_update_between_pwm_int; + + // PAUSE_ERROR_DETECT_UPDATE_OPTBUS_DATA OPT_BUS + // OPT_BUS + if (pause_error_detect_update_optbus_data=1) +// project.cds_in[0].read_pbus(&project.cds_in[0]); +//#endif + +#if(C_cds_in_number>=2) + project.cds_in[1].read_pbus(&project.cds_in[1]); +#endif + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_17_OFF; +#endif + + + + set_tics_timer_pwm(10,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + if (pwm_run == 1) + { + // - , ? + soft_stop_x24_pwm_all(); + edrk.errors.e9.bits.ERR_INT_PWM_VERY_LONG |=1; + } + else + { + pwm_run = 1; + +// detect_I_M_overload(); +// if (edrk.from_rs.bits.ACTIVE) +// edrk.Go = edrk.StartGEDRS; + +// project_read_errors_controller(); // ADR_ERRORS_TOTAL_INFO + + if ( (edrk.errors.e0.all) + || (edrk.errors.e1.all) + || (edrk.errors.e2.all) + || (edrk.errors.e3.all) + || (edrk.errors.e4.all) + || (edrk.errors.e5.all) + || (edrk.errors.e6.all) + || (edrk.errors.e7.all) + || (edrk.errors.e8.all) + || (edrk.errors.e9.all) + || (edrk.errors.e10.all) + || (edrk.errors.e11.all) + || (edrk.errors.e12.all) + ) + edrk.Stop |= 1; + else + edrk.Stop = 0; + + + + project.read_errors_controller(); + error_controller = (project.controller.read.errors.all | project.controller.read.errors_buses.bit.slave_addr_error | project.controller.read.errors_buses.bit.count_error_pbus); +// project.controller.read.errors.all = error_controller; + + + + if(error_controller && prev_error_controller==0) + { + edrk.errors.e11.bits.ERROR_CONTROLLER_BUS |= 1; + svgen_set_time_keys_closed(&svgen_pwm24_1); + svgen_set_time_keys_closed(&svgen_pwm24_2); + + write_swgen_pwm_times(PWM_MODE_RELOAD_FORCE); + +// xerror(main_er_ID(1),(void *)0); + } + prev_error_controller = error_controller;//project.controller.read.errors.all; + + + if (pwm_enable_calc_main==0)// - + { + + if (en_rotor) + { +#if (_SIMULATE_AC==1) +// calc_rotors_sim(); +#else + calc_rotors(pwm_enable_calc_main_log); // +#endif + + + + } + +#if (_ENABLE_PWM_LED2_PROFILE) + if (profile_pwm[pos_profile_pwm++]) + i_led2_on_off(1); + else + i_led2_on_off(0); +#endif + calc_zadanie_rampa(); + +#if (_ENABLE_PWM_LED2_PROFILE) + if (profile_pwm[pos_profile_pwm++]) + i_led2_on_off(1); + else + i_led2_on_off(0); +#endif + calc_norm_ADC_1(1); // + + calc_power_full(); + + calc_all_limit_koeffs(); + + } + + ///////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////// + + + if (pwm_enable_calc_main)// + { + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_18_ON; +#endif + + if (edrk.Obmotka1 == 0) + go_a = 1; + else + go_a = 0; + + if (edrk.Obmotka2 == 0) + go_b = 1; + else + go_b = 0; + + ////////////////////////// + + if (optical_read_data.data.cmd.bit.start_pwm && edrk.auto_master_slave.local.bits.slave ) + edrk.StartGEDfromSyncBus = 1; + else + edrk.StartGEDfromSyncBus = 0; + + edrk.master_Uzad = _IQ15toIQ( optical_read_data.data.pzad_or_wzad); + edrk.master_theta = _IQ12toIQ( optical_read_data.data.angle_pwm); + edrk.master_Izad = _IQ15toIQ( optical_read_data.data.iq_zad_i_zad); + edrk.master_Iq = _IQ15toIQ( optical_read_data.data.iq_zad_i_zad); + + set_tics_timer_pwm(11,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + ///////////////////////// + + if ((edrk.auto_master_slave.local.bits.slave==1 && edrk.auto_master_slave.local.bits.master==0) + || (edrk.auto_master_slave.local.bits.slave==0 && edrk.auto_master_slave.local.bits.master==1) ) + { + + if (edrk.auto_master_slave.local.bits.master != prev_master) + timer_wait_to_master_slave = 0; + + // . + if (timer_wait_to_master_slave>MAX_TIMER_WAIT_MASTER_SLAVE) + { + edrk.Status_Ready.bits.MasterSlaveActive = 1; + + if (edrk.auto_master_slave.local.bits.master) + edrk.MasterSlave = MODE_MASTER; + else + edrk.MasterSlave = MODE_SLAVE; + } + else + { + edrk.Status_Ready.bits.MasterSlaveActive = 0; + edrk.MasterSlave = MODE_DONTKNOW; + timer_wait_to_master_slave++; + } + prev_master = edrk.auto_master_slave.local.bits.master; + } + else + { + + edrk.Status_Ready.bits.MasterSlaveActive = 0; + edrk.MasterSlave = MODE_DONTKNOW; + + timer_wait_to_master_slave = 0; + } + + + set_tics_timer_pwm(12,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_OBOROTS || edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER) { + if (edrk.MasterSlave == MODE_MASTER) { + if (get_start_ged_from_zadanie()) { + edrk.prepare_stop_PWM = 0; + //edrk.StartGEDfromZadanie = 1; + localStartGEDfromZadanie = 1; + } else { + edrk.prepare_stop_PWM = 1; + if (edrk.k_stator1 < 41943) { //335544 ~ 2% + //edrk.StartGEDfromZadanie = 0; + localStartGEDfromZadanie = 0; + } + } + } else { + if (get_start_ged_from_zadanie()) { + //edrk.StartGEDfromZadanie = 1; + localStartGEDfromZadanie = 1; + } else { + if (edrk.k_stator1 < 41943) { //335544 ~ 2% + //edrk.StartGEDfromZadanie = 0; + localStartGEDfromZadanie = 0; + } + } + edrk.prepare_stop_PWM = optical_read_data.data.cmd.bit.prepare_stop_PWM; + } + } else { + //edrk.StartGEDfromZadanie = + localStartGEDfromZadanie = get_start_ged_from_zadanie(); + } + + // localStartGEDfromZadanie=1 edrk.StartGEDfromZadanie + if (localStartGEDfromZadanie && edrk.prevStartGEDfromZadanie==0) + { + if (countStartGEDfromZadanieMAX_TIMER_WAIT_BOTH_READY2) + edrk.errors.e1.bits.VERY_LONG_BOTH_READY2 |= 1; + else + timer_wait_both_ready2++; + + } + else + timer_wait_both_ready2 = 0; + + + if (optical_read_data.data.cmd.bit.rascepitel_cmd==CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_ON + && optical_read_data.data.cmd.bit.ready_cmd == CODE_READY_CMD_READY2) // + { + edrk.flag_block_zadanie = 0; + edrk.flag_wait_set_to_zero_zadanie = 0; + } + + if (optical_read_data.data.cmd.bit.rascepitel_cmd==CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_OFF + && optical_read_data.data.cmd.bit.ready_cmd == CODE_READY_CMD_READY1) // + { + edrk.flag_block_zadanie = 0; + edrk.flag_wait_set_to_zero_zadanie = 0; + } + + + if (edrk.StartGEDfromZadanie==0 && edrk.flag_block_zadanie + && (optical_read_data.data.cmd.bit.rascepitel_cmd==CODE_RASCEPITEL_CMD_REQUEST_AND_THIS_OFF)) + // + edrk.you_can_on_rascepitel = 1; + + + if (edrk.flag_wait_set_to_zero_zadanie) + { + if (timer_wait_set_to_zero_zadanie>MAX_TIMER_WAIT_SET_TO_ZERO_ZADANIE) + { + // , + // !!!! + edrk.errors.e1.bits.ANOTHER_BS_NOT_ON_RASCEPITEL |= 1; + + } + else + timer_wait_set_to_zero_zadanie++; + + } + else + timer_wait_set_to_zero_zadanie = 0; + + + // , . + if (edrk.errors.e1.bits.ANOTHER_BS_NOT_ON_RASCEPITEL) + edrk.flag_wait_set_to_zero_zadanie = 0; + + + edrk.StartGED = ((edrk.StartGEDfromControl==1) && (edrk.StartGEDfromZadanie==1) && (edrk.flag_block_zadanie==0)); + + + if (edrk.MasterSlave == MODE_MASTER) + { + edrk.GoWait = ( (edrk.StartGED ) && (edrk.Stop == 0) + && (project.controller.read.errors.all==0) && + (slow_error==0) && + (edrk.Status_Ready.bits.ready_final) + && edrk.Status_Ready.bits.MasterSlaveActive + && edrk.warnings.e9.bits.BREAKER_GED_ON==0 + ); + } + else + if (edrk.MasterSlave == MODE_SLAVE) + { + edrk.GoWait = ( (edrk.StartGED && edrk.StartGEDfromSyncBus) && (edrk.Stop == 0) + && (project.controller.read.errors.all==0) && + (slow_error==0) && + (edrk.Status_Ready.bits.ready_final) + && edrk.Status_Ready.bits.MasterSlaveActive + ); + } + else + edrk.GoWait = 0; + + // if (edrk.GoWait==0 && edrk.Go == 0 && + + + // edrk.Go + if (edrk.GoWait) + { + if (count_wait_go_0>=MAX_COUNT_WAIT_GO_0) + edrk.Go = edrk.GoWait; + else + { + edrk.Go = 0; + edrk.errors.e7.bits.VERY_FAST_GO_0to1 |=1; // ! edrk.Go!!! + } + } + else + { + if (edrk.Go) + count_wait_go_0 = 0; + + edrk.Go = 0; + if (count_wait_go_0=(MAX_COUNT_TIME_BUF-1)) + count_time_buf = 0; + + log_wait = 0; + if (edrk.MasterSlave == MODE_MASTER) + log_wait |= 0x1; + if (edrk.MasterSlave == MODE_SLAVE) + log_wait |= 0x2; + if (edrk.StartGED) + log_wait |= 0x4; + if (edrk.Stop) + log_wait |= 0x8; + if (edrk.Status_Ready.bits.ready_final) + log_wait |= 0x10; + if (edrk.Status_Ready.bits.MasterSlaveActive) + log_wait |= 0x20; + if (edrk.GoWait) + log_wait |= 0x40; + if (edrk.Go) + log_wait |= 0x80; + if (project.controller.read.errors.all==0) + log_wait |= 0x100; + if (slow_error) + log_wait |= 0x200; + if (edrk.StartGEDfromSyncBus) + log_wait |= 0x400; + + + time_buf[count_time_buf] = log_wait; + + if (edrk.errors.e7.bits.VERY_FAST_GO_0to1) + stop_count_time_buf = 1; + } +*/ +#endif + + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_GO) + if (edrk.StartGEDfromSyncBus) + { + PWM_LINES_TK_17_ON; + } + else + { + PWM_LINES_TK_17_OFF; + } + + if (edrk.StartGEDfromZadanie) + { + PWM_LINES_TK_18_ON; + } + else + { + PWM_LINES_TK_18_OFF; + } + if (edrk.flag_block_zadanie) + { + PWM_LINES_TK_19_ON; + } + else + { + PWM_LINES_TK_19_OFF; + } + + if (edrk.StartGEDfromControl) + { + PWM_LINES_TK_16_ON; + } + else + { + PWM_LINES_TK_16_OFF; + } + +#endif + + + + set_tics_timer_pwm(15,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + ////////////////////////////////// + ////////////////////////////////// + + if(edrk.Go == 1) + { + if (edrk.Go != prevGo) + { + edrk.count_run++; +// clear_mem(FAST_LOG); +// count_start_impuls = 0; +// count_step = 0; + f.count_step_ram_off = COUNT_SAVE_LOG_OFF; +// count_step_run = 0; + + // set_start_mem(FAST_LOG); + // set_start_mem(SLOW_LOG); + + // logpar.start_write_fast_log = 1; + + init_uf_const(); + init_simple_scalar(); + + Fzad = 0; + Uzad1 = 0; + Uzad2 = 0; + + clear_logpar(); + } + else + { + + if (f.count_start_impuls < COUNT_START_IMP) + { + f.count_start_impuls++; + } + else + { + f.count_start_impuls = COUNT_START_IMP; + + f.flag_record_log = 1; + enable_calc_vector = 1; + + } + + } + } + else // (edrk.Go == 0) + { + + if (f.count_step_ram_off > 0) + { + f.count_step_ram_off--; + f.flag_record_log = 1; + } else { + f.flag_record_log = 0; + } + + // + if (edrk.ManualDischarge && prev_ManualDischarge!=edrk.ManualDischarge) + edrk.Discharge = 1; + + prev_ManualDischarge =edrk.ManualDischarge; + + if (f.count_start_impuls == 0) + { + + if (edrk.Discharge || (edrk.ManualDischarge ) ) + { + break_resistor_managment_calc(); + soft_start_x24_break_1(); + } + else + { + + if (f.count_step_ram_off > 0) + { + break_resistor_recup_calc(edrk.zadanie.iq_set_break_level); + // soft_start_x24_break_1(); + } + else + { + // + soft_stop_x24_pwm_all(); + + } + } + + } + + set_tics_timer_pwm(16,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + if (f.count_start_impuls==COUNT_START_IMP) + { + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_OBOROTS || edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER) + { + if (edrk.flag_second_PCH == 0) { + wd = uf_alg.winding_displacement_bs1; + } else { + wd = uf_alg.winding_displacement_bs2; + } + + vectorControlConstId(edrk.zadanie.iq_power_zad_rmp, edrk.zadanie.iq_oborots_zad_hz_rmp, + WRotor.RotorDirectionSlow, WRotor.iqWRotorSumFilter, + edrk.Mode_ScalarVectorUFConst, + edrk.MasterSlave, edrk.zadanie.iq_Izad, wd, + edrk.master_theta, edrk.master_Iq, edrk.iq_power_kw_another_bs, + &edrk.tetta_to_slave, &edrk.Iq_to_slave, &edrk.P_to_master, + 0, 1); + + test_calc_vect_dq_pwm24_Ing(vect_control.iqTheta, vect_control.iqUdKm, vect_control.iqUqKm, + edrk.disable_alg_u_disbalance, + edrk.zadanie.iq_kplus_u_disbalance_rmp, edrk.zadanie.iq_k_u_disbalance_rmp, + filter.iqU_1_fast, filter.iqU_2_fast, + 0, + edrk.Uzad_max, + edrk.MasterSlave, + edrk.flag_second_PCH, + &edrk.Kplus, &edrk.Uzad_to_slave); + analog.PowerFOC = edrk.P_to_master; + Fzad = vect_control.iqFstator; + Izad_out = edrk.Iq_to_slave; + } else { + test_calc_simple_dq_pwm24_Ing(Fzad, 0, 0, + 0, 0, filter.iqU_1_fast, filter.iqU_2_fast, + 1, + edrk.Uzad_max, + edrk.master_theta, + edrk.master_Uzad, + edrk.MasterSlave, + edrk.flag_second_PCH, + &edrk.Kplus, &edrk.tetta_to_slave, + &edrk.Uzad_to_slave); + } + } + else + { + if (f.count_start_impuls==COUNT_START_IMP-1) + { + + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_OBOROTS || edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER) + { + if (edrk.flag_second_PCH == 0) { + wd = uf_alg.winding_displacement_bs1; + } else { + wd = uf_alg.winding_displacement_bs2; + } + + vectorControlConstId(edrk.zadanie.iq_power_zad_rmp, edrk.zadanie.iq_oborots_zad_hz_rmp, + WRotor.RotorDirectionSlow, WRotor.iqWRotorSumFilter, + edrk.Mode_ScalarVectorUFConst, + edrk.MasterSlave, edrk.zadanie.iq_Izad, wd, + edrk.master_theta, edrk.master_Iq, edrk.iq_power_kw_another_bs, + &edrk.tetta_to_slave, &edrk.Iq_to_slave, &edrk.P_to_master, + 0, 1); + + test_calc_vect_dq_pwm24_Ing(vect_control.iqTheta, vect_control.iqUdKm, vect_control.iqUqKm, + edrk.disable_alg_u_disbalance, + edrk.zadanie.iq_kplus_u_disbalance_rmp, edrk.zadanie.iq_k_u_disbalance_rmp, + filter.iqU_1_fast, filter.iqU_2_fast, + 0, + edrk.Uzad_max, + edrk.MasterSlave, + edrk.flag_second_PCH, + &edrk.Kplus, &edrk.Uzad_to_slave); + analog.PowerFOC = edrk.P_to_master; + Fzad = vect_control.iqFstator; + Izad_out = edrk.Iq_to_slave; + } else { + test_calc_simple_dq_pwm24_Ing(Fzad, 0, 0, + 0, 0, filter.iqU_1_fast, filter.iqU_2_fast, + 1, + edrk.Uzad_max, + edrk.master_theta, + edrk.master_Uzad, + edrk.MasterSlave, + edrk.flag_second_PCH, + &edrk.Kplus, &edrk.tetta_to_slave, + &edrk.Uzad_to_slave); + } + + } + else + { + if (f.count_start_impuls==COUNT_START_IMP-2) + { + // middle +// svgen_set_time_keys_closed(&svgen_pwm24_1); +// svgen_set_time_keys_closed(&svgen_pwm24_2); + svgen_set_time_middle_keys_open(&svgen_pwm24_1); + svgen_set_time_middle_keys_open(&svgen_pwm24_2); + } + else + // + { + svgen_set_time_keys_closed(&svgen_pwm24_1); + svgen_set_time_keys_closed(&svgen_pwm24_2); + } + + Fzad = 0; + + } + } + + + if (f.count_start_impuls > 0) { + f.count_start_impuls -= 1; + } else { + f.count_start_impuls = 0; + } + enable_calc_vector = 0; + + + + Uzad1 = 0; + Uzad2 = 0; + + } // end if Go==1 + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_18_OFF; +#endif + + + } // end pwm_enable_calc_main one interrupt one period only + +/* + * + // if ((m.m0.bit.EnableGoA == 1) && (f.Obmotka1 == 0)) + + + // if ((m.m0.bit.EnableGoB == 1) && (f.Obmotka2 == 0)) + if (f.Obmotka2 == 0) + { + go_b = 1; + } + else + { + go_b = 0; + } + + if (go_a == 0 && prev_go_a != go_a) + { + // 1 + soft_stop_x24_pwm_1(); + } + + if (go_a == 1 && prev_go_a != go_a) + { + // 1 + soft_start_x24_pwm_1(); + } + + if (go_b == 0 && prev_go_b != go_b) + { + // 2 + soft_stop_x24_pwm_2(); + } + + if (go_b == 1 && prev_go_b != go_b) + { + // 2 + soft_start_x24_pwm_2(); + } + + prev_go_a = go_a; + prev_go_b = go_b; + * + * + */ + + /////////////////////////////////////////// + /////////////////////////////////////////// + /////////////////////////////////////////// + /////////////////////////////////////////// + /////////////////////////////////////////// + /////////////////////////////////////////// + /////////////////////////////////////////// + /////////////////////////////////////////// + + if (pwm_enable_calc_main) // + { + + + if (f.count_start_impuls==1 && edrk.Go==1) + { + // + svgen_set_time_keys_closed(&svgen_pwm24_1); + svgen_set_time_keys_closed(&svgen_pwm24_2); + // soft_start_x24_pwm_1_2(); + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_OBOROTS || edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER) { + if (edrk.flag_second_PCH == 0) { + wd = uf_alg.winding_displacement_bs1; + } else { + wd = uf_alg.winding_displacement_bs2; + } + vectorControlConstId(edrk.zadanie.iq_power_zad_rmp, edrk.zadanie.iq_oborots_zad_hz_rmp, + WRotor.RotorDirectionSlow, WRotor.iqWRotorSumFilter, + edrk.Mode_ScalarVectorUFConst, + edrk.MasterSlave, edrk.zadanie.iq_Izad, wd, + edrk.master_theta, edrk.master_Iq, edrk.P_from_slave, + &edrk.tetta_to_slave, &edrk.Iq_to_slave, &edrk.P_to_master, 1, edrk.prepare_stop_PWM); + } + } + + if (f.count_start_impuls==2 && edrk.Go==1) + { + // + if (go_a == 1 && go_b == 1) { + // start_pwm(); edrk.Go + soft_start_x24_pwm_1_2(); + } else if (go_a == 1) { + soft_start_x24_pwm_1(); + } else if (go_b == 1) { + soft_start_x24_pwm_2(); + } + + // enable work break +#if (DISABLE_WORK_BREAK==1) + +#else +// if (edrk.disable_break_work==0) + { + soft_start_x24_break_1(); + } +#endif + + } // end if (count_start_impuls==5) + + + if (f.count_start_impuls==3 && edrk.Go==1) + { + // + svgen_set_time_middle_keys_open(&svgen_pwm24_1); + svgen_set_time_middle_keys_open(&svgen_pwm24_2); + } + + + + if (f.count_start_impuls==4 && edrk.Go==1) + { + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_OBOROTS || edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER) + { + +// void simple_scalar(int n_alg, int n_wind_pump, _iq Frot_pid, _iq Frot,_iq fzad,_iq mzz_zad, _iq bpsi_const, _iq fzad_provorot, +// _iq iqIm_1, _iq iqIm_2, _iq iqUin, _iq Iin, _iq powerzad, _iq power_pid, +// _iq *Fz, _iq *Uz1) + + if (edrk.flag_second_PCH == 0) { + wd = uf_alg.winding_displacement_bs1; + } else { + wd = uf_alg.winding_displacement_bs2; + } + + vectorControlConstId(0, 0, + WRotor.RotorDirectionSlow, WRotor.iqWRotorSumFilter, + edrk.Mode_ScalarVectorUFConst, + edrk.MasterSlave, edrk.zadanie.iq_Izad, wd, + edrk.master_theta, edrk.master_Iq, edrk.iq_power_kw_another_bs, + &edrk.tetta_to_slave, &edrk.Iq_to_slave, &edrk.P_to_master, + 0, edrk.prepare_stop_PWM); + + test_calc_vect_dq_pwm24_Ing(vect_control.iqTheta, vect_control.iqUdKm, vect_control.iqUqKm, + edrk.disable_alg_u_disbalance, + edrk.zadanie.iq_kplus_u_disbalance_rmp, edrk.zadanie.iq_k_u_disbalance_rmp, + filter.iqU_1_fast, filter.iqU_2_fast, + 0, + edrk.Uzad_max, + edrk.MasterSlave, + edrk.flag_second_PCH, + &edrk.Kplus, &edrk.Uzad_to_slave); + Fzad = vect_control.iqFstator; + Izad_out = edrk.Iq_to_slave; + } else { + test_calc_simple_dq_pwm24_Ing(Fzad, 0, 0, + 0, 0, filter.iqU_1_fast, filter.iqU_2_fast, + 0, + edrk.Uzad_max, + edrk.master_theta, + edrk.master_Uzad, + edrk.MasterSlave, + edrk.flag_second_PCH, + &edrk.Kplus, &edrk.tetta_to_slave, &edrk.Uzad_to_slave); + + + simple_scalar(1,0, WRotor.RotorDirectionSlow, + WRotor.iqWRotorSumFilter2, WRotor.iqWRotorSumFilter, + 0, + 0, + 0, edrk.iq_bpsi_normal, + 0, + // analog.iqU_1_long+analog.iqU_2_long, + edrk.zadanie.iq_ZadanieU_Charge_rmp+edrk.zadanie.iq_ZadanieU_Charge_rmp, + 0, + edrk.zadanie.iq_power_zad_rmp, 0, + edrk.zadanie.iq_limit_power_zad_rmp, edrk.Mode_ScalarVectorUFConst, + 0,0, edrk.count_bs_work+1, + &Fzad, &Uzad1, &Uzad2, &Izad_out); + } + + } + + if (f.count_start_impuls == COUNT_START_IMP && edrk.Go==1) + { + if (pwm_enable_calc_main) // + { +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_21_ON; +#endif + + + //break_resistor_recup_calc(edrk.zadanie.iq_ZadanieU_Charge); + break_resistor_recup_calc(edrk.zadanie.iq_set_break_level); + + set_tics_timer_pwm(17,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + run_calc_uf = 1; + + // , middle + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_UF_CONST) + { +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_ON; +#endif + uf_const(&Fzad,&Uzad1,&Uzad2); +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_OFF; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_ON; +#endif + + test_calc_simple_dq_pwm24_Ing(Fzad, + Uzad1, + edrk.disable_alg_u_disbalance, + edrk.zadanie.iq_kplus_u_disbalance, + edrk.zadanie.iq_k_u_disbalance, + filter.iqU_1_fast, + filter.iqU_2_fast, + 0, + edrk.Uzad_max, + edrk.master_theta, + edrk.master_Uzad, + edrk.MasterSlave, + edrk.flag_second_PCH, + &edrk.Kplus, + &edrk.tetta_to_slave, + &edrk.Uzad_to_slave); +// rmp_freq.DesiredInput = alg_pwm24.freq1; +// rmp_freq.calc(&rmp_freq); +// Fzad = rmp_freq.Out; +// +// vhz1.Freq = Fzad; +// vhz1.calc(&vhz1); +// +// +// Uzad1 = alg_pwm24.k1; +// Uzad2 = alg_pwm24.k1; + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_OFF; +#endif + + // test_calc_pwm24(Uzad1, Uzad2, Fzad); + // analog_dq_calc_const(); + + } // end ALG_MODE_UF_CONST + else + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_SCALAR_OBOROTS || edrk.Mode_ScalarVectorUFConst == ALG_MODE_SCALAR_POWER) + { +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_ON; +#endif + simple_scalar(1, + 0, + WRotor.RotorDirectionSlow, + WRotor.iqWRotorSumFilter, //rotor_22220.iqFlong * rotor_22220.direct_rotor; + WRotor.iqWRotorSumFilter, //rotor_22220.iqFout * rotor_22220.direct_rotor; + //0, 0, + edrk.zadanie.iq_oborots_zad_hz_rmp, + edrk.all_limit_koeffs.sum_limit, + edrk.zadanie.iq_Izad_rmp, + edrk.iq_bpsi_normal, + analog.iqIm, +// analog.iqU_1_long+analog.iqU_2_long, + edrk.zadanie.iq_ZadanieU_Charge_rmp+edrk.zadanie.iq_ZadanieU_Charge_rmp, + analog.iqIin_sum, + edrk.zadanie.iq_power_zad_rmp, + edrk.iq_power_kw_full_znak,//(filter.PowerScalar+edrk.iq_power_kw_another_bs), + edrk.zadanie.iq_limit_power_zad_rmp, edrk.Mode_ScalarVectorUFConst, + edrk.master_Izad, + edrk.MasterSlave, + edrk.count_bs_work+1, + &Fzad, + &Uzad1, + &Uzad2, + &Izad_out); + + set_tics_timer_pwm(18,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_OFF; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_ON; +#endif + + + + if (edrk.cmd_disable_calc_km_on_slave) + Uzad_from_master = edrk.master_Uzad; + else + { +#if (DISABLE_CALC_KM_ON_SLAVE==1) + Uzad_from_master = edrk.master_Uzad; +#else + Uzad_from_master = Uzad1; +#endif + + } + + test_calc_simple_dq_pwm24_Ing(Fzad, Uzad1, edrk.disable_alg_u_disbalance, + edrk.zadanie.iq_kplus_u_disbalance, edrk.zadanie.iq_k_u_disbalance, filter.iqU_1_fast, filter.iqU_2_fast, + 0, + edrk.Uzad_max, + edrk.master_theta, + Uzad_from_master, + edrk.MasterSlave, + edrk.flag_second_PCH, + &edrk.Kplus, &edrk.tetta_to_slave, &edrk.Uzad_to_slave); +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_OFF; +#endif + + set_tics_timer_pwm(19,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + if (edrk.flag_second_PCH == 0) { + wd = uf_alg.winding_displacement_bs1; + } else { + wd = uf_alg.winding_displacement_bs2; + } + + analog_dq_calc_external(wd, uf_alg.tetta); + + } // end ALG_MODE_SCALAR_OBOROTS + else + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_OBOROTS || edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER) + { + +// void simple_scalar(int n_alg, int n_wind_pump, _iq Frot_pid, _iq Frot,_iq fzad,_iq mzz_zad, _iq bpsi_const, _iq fzad_provorot, +// _iq iqIm_1, _iq iqIm_2, _iq iqUin, _iq Iin, _iq powerzad, _iq power_pid, +// _iq *Fz, _iq *Uz1) + + if (edrk.flag_second_PCH == 0) { + wd = uf_alg.winding_displacement_bs1; + } else { + wd = uf_alg.winding_displacement_bs2; + } +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_ON; +#endif + vectorControlConstId(edrk.zadanie.iq_power_zad_rmp, edrk.zadanie.iq_oborots_zad_hz_rmp, + WRotor.RotorDirectionSlow, WRotor.iqWRotorSumFilter, + edrk.Mode_ScalarVectorUFConst, + edrk.MasterSlave, edrk.zadanie.iq_Izad, wd, + edrk.master_theta, edrk.master_Iq, edrk.iq_power_kw_another_bs, + &edrk.tetta_to_slave, &edrk.Iq_to_slave, &edrk.P_to_master, + 0, edrk.prepare_stop_PWM); +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_OFF; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_ON; +#endif + + test_calc_vect_dq_pwm24_Ing(vect_control.iqTheta, vect_control.iqUdKm, vect_control.iqUqKm, + edrk.disable_alg_u_disbalance, + edrk.zadanie.iq_kplus_u_disbalance_rmp, edrk.zadanie.iq_k_u_disbalance_rmp, + filter.iqU_1_fast, filter.iqU_2_fast, + 0, + edrk.Uzad_max, + edrk.MasterSlave, + edrk.flag_second_PCH, + &edrk.Kplus, &edrk.Uzad_to_slave); + + analog.PowerFOC = edrk.P_to_master; + Fzad = vect_control.iqFstator; + Izad_out = edrk.Iq_to_slave; + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_20_OFF; +#endif + } // end ALG_MODE_FOC_OBOROTS + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_21_OFF; +#endif + + } // end pwm_enable_calc_main + + } // end (count_start_impuls == COUNT_START_IMP && edrk.Go==1) + else + { + run_calc_uf = 0; + if (pwm_enable_calc_main) // + { + + } + svgen_pwm24_1.Ta_imp = 0; + svgen_pwm24_1.Tb_imp = 0; + svgen_pwm24_1.Tc_imp = 0; + svgen_pwm24_2.Ta_imp = 0; + svgen_pwm24_2.Tb_imp = 0; + svgen_pwm24_2.Tc_imp = 0; + + } // end else (count_start_impuls == COUNT_START_IMP && edrk.Go==1) + + prevGo = edrk.Go; + + + + ////////////////////////////////// + optical_write_data.data.cmd.bit.start_pwm = edrk.Go; + optical_write_data.data.cmd.bit.prepare_stop_PWM = edrk.prepare_stop_PWM; + + optical_write_data.data.angle_pwm = _IQtoIQ12(edrk.tetta_to_slave + vect_control.add_tetta); + optical_write_data.data.pzad_or_wzad = _IQtoIQ15(edrk.Uzad_to_slave); + optical_write_data.data.iq_zad_i_zad = _IQtoIQ15(edrk.Izad_out); + + optical_bus_update_data_write(); + + set_tics_timer_pwm(20,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + + if (edrk.ms.another_bs_maybe_on==1 && edrk.auto_master_slave.local.bits.master) + { + // i_led2_on(); + } + + ////////////////////////////////// + ////////////////////////////////// + + edrk.Izad_out = Izad_out; + + if (edrk.MasterSlave==MODE_SLAVE) + { + edrk.f_stator = Fzad; + edrk.k_stator1 = edrk.Uzad_to_slave;//Uzad1; + edrk.k_stator2 = edrk.Uzad_to_slave;//Uzad2; + + } + else + if (edrk.MasterSlave==MODE_MASTER) + { + edrk.f_stator = Fzad; + edrk.k_stator1 = edrk.Uzad_to_slave;//Uzad1; + edrk.k_stator2 = edrk.Uzad_to_slave; + } + else + { + edrk.f_stator = 0; + edrk.k_stator1 = 0; + edrk.k_stator2 = 0; + } + + } // end pwm_enable_calc_main + + + + + /////////////////////////////////////////// + /////////////////////////////////////////// + /////////////////////////////////////////// + /////////////////////////////////////////// + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_22_ON; +#endif + + if (xpwm_time.one_or_two_interrupts_run == PWM_ONE_INTERRUPT_RUN) + write_swgen_pwm_times(PWM_MODE_RELOAD_FORCE); + else + { + if (edrk.Go==1) + { + if (f.count_start_impuls==COUNT_START_IMP-1) + { + if (pwm_enable_calc_main) + write_swgen_pwm_times(PWM_MODE_RELOAD_LEVEL_HIGH); + else + write_swgen_pwm_times(PWM_MODE_RELOAD_LEVEL_LOW); + } + else +// if (pwm_enable_calc_main) + write_swgen_pwm_times(PWM_MODE_RELOAD_FORCE); + } + else + { + if (f.count_start_impuls==COUNT_START_IMP-3) + { + if (pwm_enable_calc_main) + write_swgen_pwm_times(PWM_MODE_RELOAD_LEVEL_HIGH); + else + write_swgen_pwm_times(PWM_MODE_RELOAD_LEVEL_LOW); + + } + else + write_swgen_pwm_times(PWM_MODE_RELOAD_FORCE); + } + + + + // if (pwm_enable_calc_main) + // prev_run_calc_uf = run_calc_uf; + + + + } +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_22_OFF; +#endif + + + set_tics_timer_pwm(21,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + + // test write oscil buf + + if ( pwm_enable_calc_main==0) // + { + + run_write_logs(); + + } + + + // i_led2_on(); + // + if (edrk.SumSbor == 1) { + detect_protect_adc(uf_alg.tetta_bs, uf_alg.tetta_bs); + //// get_tics_timer_pwm(pwm_enable_calc_main,count_timer_buf); + } + + // fill_RMS_buff_interrupt(uf_alg.tetta_bs, uf_alg.tetta_bs); + + set_tics_timer_pwm(24,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + + // out_I_over_1_6.calc(&out_I_over_1_6); + // i_led2_off(); + + + pwm_run = 0; + + + } // end if pwm_run==1 + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_16_OFF; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_16_ON; +#endif + + if (pwm_enable_calc_main==0) // + { + + + // pwm_analog_ext_interrupt(); + +// inc_RS_timeout_cicle(); +// inc_CAN_timeout_cicle(); + +#if (_SIMULATE_AC==1) + sim_model_execute(); +#endif + + } + + pwm_analog_ext_interrupt(); + pwm_inc_interrupt(); + + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_16_OFF; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_16_ON; +#endif + + + + + set_tics_timer_pwm(25,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + + +#if (_ENABLE_SLOW_PWM) +// pause_1000(slow_pwm_pause); +#endif + + set_tics_timer_pwm(26,count_timer_buf); + get_tics_timer_pwm(pwm_enable_calc_main_log); + +///////////////////////////////////////////////// + // + end_tics_4timer = EvbRegs.T3CNT; + + if (end_tics_4timer>start_tics_4timer) + { + time_delta = (end_tics_4timer - start_tics_4timer); + time_delta = time_delta * 33/1000; + if (pwm_enable_calc_main) + edrk.period_calc_pwm_int1 = time_delta;//(end_tics_4timer - start_tics_4timer)*33/1000; + else + edrk.period_calc_pwm_int2 = time_delta;//(end_tics_4timer - start_tics_4timer)*33/1000; + } + // + ///////////////////////////////////////////////// + + // get_tics_timer_pwm(pwm_enable_calc_main,count_timer_buf); + + + + + +#if (_ENABLE_LOG_TICS_PWM==1) + + for (i_log=count_timer_buf;i_log=10000) + c_run=c_run_start; + else + c_run++; +#endif + +#if (ENABLE_LOG_INTERRUPTS) + add_log_interrupts(103); +#endif + + + +// i_sync_pin_off(); + edrk.into_pwm_interrupt = 0; + +#if (_ENABLE_INTERRUPT_PWM_LED2) +i_led2_on_off(0); +#endif + + + +#if(_ENABLE_PWM_LINES_FOR_TESTS) + // PWM_LINES_TK_16_OFF; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_16_OFF; +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_16_OFF; +#endif + + +#if (_ENABLE_PWM_LED2_PROFILE) + i_led2_on_off(0); + if (pwm_enable_calc_main==0) + profile_pwm[pos_profile_pwm] = 2; +#endif + + +} +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// + + + +#pragma CODE_SECTION(fix_pwm_freq_synchro_ain,".fast_run"); +void fix_pwm_freq_synchro_ain(void) +{ + unsigned int new_freq; + static unsigned int delta_freq = 1; +// if (f.Sync_input_or_output == SYNC_INPUT) + { + sync_inc_error(); + + if (sync_data.disable_sync || sync_data.timeout_sync_signal == 1 || sync_data.enable_do_sync == 0) + { + + new_freq = xpwm_time.pwm_tics; + i_WriteMemory(ADR_PWM_PERIOD, new_freq); + + return; + } + + if (sync_data.pwm_freq_plus_minus_zero==1) + { + + + //Increment xtics + new_freq = xpwm_time.pwm_tics + delta_freq; + i_WriteMemory(ADR_PWM_PERIOD, new_freq); // Saw period in tics. 1 tic = 16.67 nsec + + // change_freq_pwm(VAR_FREQ_PWM_XTICS); + + + } + + if (sync_data.pwm_freq_plus_minus_zero==-1) + { + //4464 + //Decrement xtics + new_freq = xpwm_time.pwm_tics - delta_freq; + i_WriteMemory(ADR_PWM_PERIOD, new_freq); // Saw period in tics. 1 tic = 16.67 nsec + + // change_freq_pwm(VAR_FREQ_PWM_XTICS); + + } + + if (sync_data.pwm_freq_plus_minus_zero==0) + { + new_freq = xpwm_time.pwm_tics; + i_WriteMemory(ADR_PWM_PERIOD, new_freq); + // change_freq_pwm(VAR_FREQ_PWM_XTICS); + } + + } + + + +} + +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// + +/* +void slow_vector_update() +{ + _iq iqKzad = 0; + + freq1 = _IQ (f.fzad/F_STATOR_MAX);//f.iqFRotorSetHz; + iqKzad = _IQ(f.kzad); + k1 = zad_intensiv_q(20000, 20000, k1, iqKzad); + +} +*/ + +void detect_work_revers(int direction, _iq fzad, _iq frot) +{ + static int prev_revers = 0; + int flag_revers; + // + if (direction == -1 && fzad > 0) + { + flag_revers = 1; + } + else + if (direction == 1 && fzad < 0) + { + flag_revers = 1; + } + else + { + flag_revers = 0; + } + + if (flag_revers && prev_revers==0) + edrk.count_revers++; + + prev_revers = flag_revers; + +} + + +void calc_power_full(void) +{ + _iq power_full_abs, power_one_abs, power_full_abs_f, power_one_abs_f; + + // + power_one_abs = _IQabs(filter.PowerScalar); + power_one_abs_f = _IQabs(filter.PowerScalarFilter2); + power_full_abs = power_one_abs + _IQabs(edrk.iq_power_kw_another_bs); + power_full_abs_f = power_one_abs_f + _IQabs(edrk.iq_power_kw_another_bs); + + if (edrk.oborots>=0) + { + edrk.iq_power_kw_full_znak = power_full_abs; + edrk.iq_power_kw_one_znak = power_one_abs; + edrk.iq_power_kw_full_filter_znak = power_full_abs_f; + edrk.iq_power_kw_one_filter_znak = power_one_abs_f; + } + else + { + edrk.iq_power_kw_full_znak = -power_full_abs; + edrk.iq_power_kw_one_znak = -power_one_abs; + edrk.iq_power_kw_full_filter_znak = -power_full_abs_f; + edrk.iq_power_kw_one_filter_znak = -power_one_abs_f; + } + + edrk.iq_power_kw_full_abs = power_full_abs; + edrk.iq_power_kw_one_abs = power_one_abs; + edrk.iq_power_kw_full_filter_abs = power_full_abs_f; + edrk.iq_power_kw_one_filter_abs = power_one_abs_f; + +} diff --git a/Inu/Src2/551/main/PWMTools.h b/Inu/Src2/551/main/PWMTools.h new file mode 100644 index 0000000..67f30b2 --- /dev/null +++ b/Inu/Src2/551/main/PWMTools.h @@ -0,0 +1,54 @@ +#ifndef PWMTOOLS_H +#define PWMTOOLS_H +#include +#include + + +////////////////////////////////////////////////// +////////////////////////////////////////////////// +////////////////////////////////////////////////// + + +void InitPWM(void); +void PWM_interrupt(void); +void PWM_interrupt_main(void); + + + +void stop_wdog(void); +void start_wdog(void); + + +void global_time_interrupt(void); +void optical_bus_read_write_interrupt(void); +void pwm_analog_ext_interrupt(void); +void pwm_inc_interrupt(void); + +void fix_pwm_freq_synchro_ain(void); +void async_pwm_ext_interrupt(void); + + + +void calc_rotors(int flag); + +void detect_work_revers(int direction, _iq fzad, _iq frot); + +void calc_power_full(void); + + + +////////////////////////////////////////////////// +////////////////////////////////////////////////// +////////////////////////////////////////////////// +////////////////////////////////////////////////// + +extern PWMGEND pwmd; + +//extern int var_freq_pwm_xtics; +//extern int var_period_max_xtics; +//extern int var_period_min_xtics; + + + +#endif //PWMTOOLS_H + diff --git a/Inu/Src2/551/main/adc_internal.h b/Inu/Src2/551/main/adc_internal.h new file mode 100644 index 0000000..c74a174 --- /dev/null +++ b/Inu/Src2/551/main/adc_internal.h @@ -0,0 +1,33 @@ + + +#define ADC_usDELAY 8000L +#define ADC_usDELAY2 20L + + + + + +// Determine when the shift to right justify the data takes place +// Only one of these should be defined as 1. +// The other two should be defined as 0. +#define POST_SHIFT 0 // Shift results after the entire sample table is full +#define INLINE_SHIFT 1 // Shift results as the data is taken from the results regsiter +#define NO_SHIFT 0 // Do not shift the results + +// ADC start parameters +#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25MHz +#define ADC_CKPS 0x0 // ADC module clock = HSPCLK/1 = 25MHz/(1) = 25MHz +#define ADC_SHCLK 0x1 // S/H width in ADC module periods = 2 ADC cycle +#define AVG 1000 // Average sample limit +#define ZOFFSET 0x00 // Average Zero offset +#define BUF_SIZE 100 // Sample buffer size + + + +#define FREQ_ADC 15000.0//26.08.2009//73000.0 + + +#define read_ADC(c) (*(&AdcRegs.ADCRESULT0+c)>>4) + +#define SDVIG_K_FILTER_S 2 //1//(27.08.2009) //3 + diff --git a/Inu/Src2/551/main/adc_tools.c b/Inu/Src2/551/main/adc_tools.c new file mode 100644 index 0000000..80b3b8d --- /dev/null +++ b/Inu/Src2/551/main/adc_tools.c @@ -0,0 +1,1412 @@ +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "IQmathLib.h" + +#include +#include +#include +#include +#include + +#include "mathlib.h" +#include "filter_v1.h" +#include "xp_project.h" + +//#include "spartan_tools.h" + + + +//#define LOG_ACP_TO_BUF 1 + +#ifdef LOG_ACP_TO_BUF + +#define SIZE_BUF_LOG_ACP 500 +#pragma DATA_SECTION(BUF_ADC,".slow_vars") +int BUF_ADC[SIZE_BUF_LOG_ACP]; +#pragma DATA_SECTION(BUF_ADC_2,".slow_vars") +int BUF_ADC_2[SIZE_BUF_LOG_ACP]; + +#endif + + + +#if (USE_INTERNAL_ADC==1) + +#if(C_adc_number==1) +unsigned int const R_ADC[COUNT_ARR_ADC_BUF][16] = { R_ADC_DEFAULT_0,R_ADC_DEFAULT_INTERNAL }; +unsigned int const K_LEM_ADC[COUNT_ARR_ADC_BUF][16] = { K_LEM_ADC_DEFAULT_0, K_LEM_ADC_DEFAULT_INTERNAL}; +float const K_NORMA_ADC[COUNT_ARR_ADC_BUF][16] = { NORMA_ADC_DEFAULT_0, NORMA_ADC_DEFAULT_INTERNAL}; +#endif +#if(C_adc_number==2) +unsigned int const R_ADC[COUNT_ARR_ADC_BUF][16] = { R_ADC_DEFAULT_0, R_ADC_DEFAULT_1,R_ADC_DEFAULT_INTERNAL }; +unsigned int const K_LEM_ADC[COUNT_ARR_ADC_BUF][16] = { K_LEM_ADC_DEFAULT_0, K_LEM_ADC_DEFAULT_1, K_LEM_ADC_DEFAULT_INTERNAL }; +float const K_NORMA_ADC[COUNT_ARR_ADC_BUF][16] = { NORMA_ADC_DEFAULT_0, NORMA_ADC_DEFAULT_1, NORMA_ADC_DEFAULT_INTERNAL }; +#endif +#if(C_adc_number==3) +unsigned int const R_ADC[COUNT_ARR_ADC_BUF][16] = { R_ADC_DEFAULT_0, R_ADC_DEFAULT_1, R_ADC_DEFAULT_2,R_ADC_DEFAULT_INTERNAL }; +unsigned int const K_LEM_ADC[COUNT_ARR_ADC_BUF][16] = { K_LEM_ADC_DEFAULT_0, K_LEM_ADC_DEFAULT_1, K_LEM_ADC_DEFAULT_2, K_LEM_ADC_DEFAULT_INTERNAL }; +float const K_NORMA_ADC[COUNT_ARR_ADC_BUF][16] = { NORMA_ADC_DEFAULT_0, NORMA_ADC_DEFAULT_1, NORMA_ADC_DEFAULT_2, NORMA_ADC_DEFAULT_INTERNAL }; +#endif + +#else + +#if(C_adc_number==1) +#pragma DATA_SECTION(R_ADC,".slow_vars") +unsigned int R_ADC[COUNT_ARR_ADC_BUF][16] = { R_ADC_DEFAULT_0 }; +#pragma DATA_SECTION(K_LEM_ADC,".slow_vars") +unsigned int K_LEM_ADC[COUNT_ARR_ADC_BUF][16] = { K_LEM_ADC_DEFAULT_0}; +#pragma DATA_SECTION(K_NORMA_ADC,".slow_vars") +float K_NORMA_ADC[COUNT_ARR_ADC_BUF][16] = { NORMA_ADC_DEFAULT_0}; +#endif +#if(C_adc_number==2) +#pragma DATA_SECTION(R_ADC,".slow_vars") +unsigned int R_ADC[COUNT_ARR_ADC_BUF][16] = { R_ADC_DEFAULT_0, R_ADC_DEFAULT_1 }; +#pragma DATA_SECTION(K_LEM_ADC,".slow_vars") +unsigned int K_LEM_ADC[COUNT_ARR_ADC_BUF][16] = { K_LEM_ADC_DEFAULT_0, K_LEM_ADC_DEFAULT_1 }; +#pragma DATA_SECTION(K_NORMA_ADC,".slow_vars") +float K_NORMA_ADC[COUNT_ARR_ADC_BUF][16] = { NORMA_ADC_DEFAULT_0, NORMA_ADC_DEFAULT_1 }; +#endif +#if(C_adc_number==3) +#pragma DATA_SECTION(R_ADC,".slow_vars") +unsigned int R_ADC[COUNT_ARR_ADC_BUF][16] = { R_ADC_DEFAULT_0, R_ADC_DEFAULT_1, R_ADC_DEFAULT_2 }; +#pragma DATA_SECTION(K_LEM_ADC,".slow_vars") +unsigned int K_LEM_ADC[COUNT_ARR_ADC_BUF][16] = { K_LEM_ADC_DEFAULT_0, K_LEM_ADC_DEFAULT_1, K_LEM_ADC_DEFAULT_2 }; +#pragma DATA_SECTION(K_NORMA_ADC,".slow_vars") +float K_NORMA_ADC[COUNT_ARR_ADC_BUF][16] = { NORMA_ADC_DEFAULT_0, NORMA_ADC_DEFAULT_1, NORMA_ADC_DEFAULT_2 }; +#endif + +#endif + +//unsigned int const R_ADC_1[16] = R_ADC_DEFAULT_1; +//unsigned int const K_LEM_ADC_1[16] = K_LEM_ADC_DEFAULT_1; + + + + +#if (USE_INTERNAL_ADC==1) +int error_ADC[COUNT_ARR_ADC_BUF][16] = { {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }; +#else + +#if(C_adc_number==1) +int error_ADC[COUNT_ARR_ADC_BUF][16] = { {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }; +#endif +#if(C_adc_number==2) +int error_ADC[COUNT_ARR_ADC_BUF][16] = { {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }; +#endif +#if(C_adc_number==3) +int error_ADC[COUNT_ARR_ADC_BUF][16] = { {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} }; +#endif + +#endif + + +#pragma DATA_SECTION(ADC_f,".fast_vars"); +int ADC_f[COUNT_ARR_ADC_BUF][16]; + +#pragma DATA_SECTION(ADC_fast,".fast_vars"); +int ADC_fast[COUNT_ARR_ADC_BUF][16][COUNT_ARR_ADC_BUF_FAST_POINT]; + + +#pragma DATA_SECTION(ADC_sf,".fast_vars"); +int ADC_sf[COUNT_ARR_ADC_BUF][16]; + +#pragma DATA_SECTION(analog,".fast_vars"); +ANALOG_VALUE analog = ANALOG_VALUE_DEFAULT; + +#pragma DATA_SECTION(filter,".fast_vars"); +ANALOG_VALUE filter = ANALOG_VALUE_DEFAULT; + +#pragma DATA_SECTION(analog_zero,".fast_vars"); +ANALOG_VALUE analog_zero = ANALOG_VALUE_DEFAULT; + + + +unsigned int const level_err_ADC_PLUS[16] = level_err_ADC_PLUS_default; +unsigned int const level_err_ADC_MINUS[16] = level_err_ADC_MINUS_default; + + +#pragma DATA_SECTION(err_adc_protect,".fast_vars"); +#pragma DATA_SECTION(mask_err_adc_protect,".fast_vars"); +ERR_ADC_PROTECT err_adc_protect[COUNT_ARR_ADC_BUF],mask_err_adc_protect[COUNT_ARR_ADC_BUF]; + + + +_iq koef_Im_filter=0; +_iq koef_Power_filter=0; +_iq koef_Power_filter2=0; + +#pragma DATA_SECTION(k_norm_ADC,".slow_vars") +_iq19 k_norm_ADC[COUNT_ARR_ADC_BUF][16]; + +#pragma DATA_SECTION(iq19_zero_ADC,".fast_vars"); +_iq19 iq19_zero_ADC[COUNT_ARR_ADC_BUF][16]; + + +#pragma DATA_SECTION(zero_ADC,".slow_vars") +int zero_ADC[COUNT_ARR_ADC_BUF][16]; + + +#pragma DATA_SECTION(iq19_k_norm_ADC,".fast_vars"); +_iq19 iq19_k_norm_ADC[COUNT_ARR_ADC_BUF][16]; + +#pragma DATA_SECTION(iq_norm_ADC,".fast_vars"); +_iq iq_norm_ADC[COUNT_ARR_ADC_BUF][16]; + +#pragma DATA_SECTION(iq_norm_ADC_sf,".fast_vars"); +_iq iq_norm_ADC_sf[COUNT_ARR_ADC_BUF][16]; + + +#pragma DATA_SECTION(koef_Uzpt_long_filter,".fast_vars"); +_iq koef_Uzpt_long_filter=0; + +#pragma DATA_SECTION(koef_Uzpt_fast_filter,".fast_vars"); +_iq koef_Uzpt_fast_filter=0; + +#pragma DATA_SECTION(koef_Uin_filter,".fast_vars"); +_iq koef_Uin_filter=0; + + +void fast_detect_protect_ACP(); +//void fast_read_all_adc_one(int cc); +//void fast_read_all_adc_more(void); + + +#if (USE_INTERNAL_ADC==1) +#pragma CODE_SECTION(adc_isr,".fast_run"); +interrupt void adc_isr(void) +{ +// unsigned char k; + static char l_ir=0; + static char step_acp=0; + +//i_led1_on_off(1); + +// i_led1_on_off(1); + + project.adc->read_pbus(&project.adc[0]); + + ADC_f[0][0] = project.adc[0].read.pbus.adc_value[0]; + ADC_f[0][1] = project.adc[0].read.pbus.adc_value[1]; + ADC_f[0][2] = project.adc[0].read.pbus.adc_value[2]; + ADC_f[0][3] = project.adc[0].read.pbus.adc_value[3]; + ADC_f[0][4] = project.adc[0].read.pbus.adc_value[4]; + ADC_f[0][5] = project.adc[0].read.pbus.adc_value[5]; + ADC_f[0][6] = project.adc[0].read.pbus.adc_value[6]; + ADC_f[0][7] = project.adc[0].read.pbus.adc_value[7]; + ADC_f[0][8] = project.adc[0].read.pbus.adc_value[8]; + ADC_f[0][9] = project.adc[0].read.pbus.adc_value[9]; + ADC_f[0][10] = project.adc[0].read.pbus.adc_value[10]; + ADC_f[0][11] = project.adc[0].read.pbus.adc_value[11]; + ADC_f[0][12] = project.adc[0].read.pbus.adc_value[12]; + ADC_f[0][13] = project.adc[0].read.pbus.adc_value[13]; + ADC_f[0][14] = project.adc[0].read.pbus.adc_value[14]; + ADC_f[0][15] = project.adc[0].read.pbus.adc_value[15]; + + + ADC_sf[0][0] += (ADC_f[0][0] - ADC_sf[0][0]) >> Shift_Filter; + ADC_sf[0][1] += (ADC_f[0][1] - ADC_sf[0][1]) >> Shift_Filter; + ADC_sf[0][2] += (ADC_f[0][2] - ADC_sf[0][2]) >> Shift_Filter; + ADC_sf[0][3] += (ADC_f[0][3] - ADC_sf[0][3]) >> Shift_Filter; + + +/* + + + if (ADC_sf[2][0]>ERR_LEVEL_ADC_PLUS || ADC_sf[2][0]ERR_LEVEL_ADC_PLUS || ADC_sf[2][1]ERR_LEVEL_ADC_PLUS || ADC_f[2]ERR_LEVEL_ADC_PLUS || ADC_sf[2][3]ERR_LEVEL_ADC_PLUS || ADC_f[8]ERR_LEVEL_ADC_PLUS || ADC_f[9]ERR_LEVEL_ADC_PLUS || ADC_f[10]ERR_LEVEL_ADC_PLUS_6 || ADC_f[2][11]maxU) maxU = buf_U1_3point[1]; +// if (buf_U1_3point[2]>maxU) maxU = buf_U1_3point[2]; +// +// if (buf_U1_3point[1]= component_Ready) + detect_zero_analog(i); + } + +// zero_ADC[1][2] = 2010;//1976; // uab +// zero_ADC[1][3] = 2010;//1989; // ubc +// zero_ADC[1][4] = 2010;//1994; // uca + + + zero_ADC[0][0]=zero_ADC[0][2];//2042;//1992;//1835; //uzpt + zero_ADC[0][1]=zero_ADC[0][2];//2042;//1992;//1835; //uzpt + + + +#if (COUNT_ARR_ADC_BUF>1) + zero_ADC[1][1]=zero_ADC[1][15]; + zero_ADC[1][2]=zero_ADC[1][15]; + zero_ADC[1][3]=zero_ADC[1][15]; + zero_ADC[1][4]=zero_ADC[1][15]; + zero_ADC[1][5]=zero_ADC[1][15]; + zero_ADC[1][6]=zero_ADC[1][15]; + zero_ADC[1][7]=zero_ADC[1][15]; + zero_ADC[1][8]=zero_ADC[1][15]; + zero_ADC[1][9]=zero_ADC[1][15]; + zero_ADC[1][10]=zero_ADC[1][15]; + zero_ADC[1][11]=zero_ADC[1][15]; + zero_ADC[1][12]=zero_ADC[1][15]; + zero_ADC[1][13]=zero_ADC[1][15]; + zero_ADC[1][14]=zero_ADC[1][15]; +#endif + + + for (k=0;k<16;k++) + { + for (i=0;i2200) || (zero_ADC[i][k]<1900)) + zero_ADC[i][k] = DEFAULT_ZERO_ADC; + } + } + + + + for (k=0;k<16;k++) + { + for (i=0;ierror_counts.adc_0) +// if (ADC_sf[i][k] >= ERR_LEVEL_ADC_PLUS) detect_protect_ACP_plus (i, k); + // if (ADC_sf[i][k] <= ERR_LEVEL_ADC_MINUS) detect_protect_ACP_minus(i, k); + } + } + + +} + +#if (USE_INTERNAL_ADC==1) +#pragma CODE_SECTION(fast_detect_protect_ACP_internal,".fast_run"); +void fast_detect_protect_ACP_internal(void) +{ + int k; + k=0; + if (ADC_sf[COUNT_ARR_ADC_BUF-1][k] >= ERR_LEVEL_ADC_PLUS) detect_protect_ACP_plus (2, k); + if (ADC_sf[COUNT_ARR_ADC_BUF-1][k] <= ERR_LEVEL_ADC_MINUS) detect_protect_ACP_minus(2, k); + k=1; + if (ADC_sf[COUNT_ARR_ADC_BUF-1][k] >= ERR_LEVEL_ADC_PLUS) detect_protect_ACP_plus (2, k); + if (ADC_sf[COUNT_ARR_ADC_BUF-1][k] <= ERR_LEVEL_ADC_MINUS) detect_protect_ACP_minus(2, k); + k=3; + if (ADC_sf[COUNT_ARR_ADC_BUF-1][k] >= ERR_LEVEL_ADC_PLUS) detect_protect_ACP_plus (2, k); + if (ADC_sf[COUNT_ARR_ADC_BUF-1][k] <= ERR_LEVEL_ADC_MINUS) detect_protect_ACP_minus(2, k); + + +} +#endif + + +#pragma CODE_SECTION(fast_detect_protect_ACP,".fast_run"); +void fast_detect_protect_ACP() +{ + int i,k; + +// for (i=0;i<2;i++) + { +// if (project.adc[i].status == component_Ready) +#if(C_adc_number>=1) + i = 0; + for (k=0;k<14;k++) + { + if (ADC_f[i][k] >= ERR_LEVEL_ADC_PLUS) detect_protect_ACP_plus (i, k); + if (ADC_f[i][k] <= ERR_LEVEL_ADC_MINUS) detect_protect_ACP_minus(i, k); + } +#endif +#if(C_adc_number>=2) + i = 1; + for (k=2;k<5;k++) + { + if (ADC_f[i][k] >= ERR_LEVEL_ADC_PLUS) detect_protect_ACP_plus (i, k); + if (ADC_f[i][k] <= ERR_LEVEL_ADC_MINUS) detect_protect_ACP_minus(i, k); + } +#endif +#if(C_adc_number>=3) + i = 2; + for (k=0;k<15;k++) + { + if (ADC_f[i][k] >= ERR_LEVEL_ADC_PLUS) detect_protect_ACP_plus (i, k); + if (ADC_f[i][k] <= ERR_LEVEL_ADC_MINUS) detect_protect_ACP_minus(i, k); + } +#endif + + } + +} + +#pragma CODE_SECTION(norma_adc,".fast_run"); +inline _iq norma_adc(int plane, int chan) +{ +// return _IQ19toIQ(_IQ19mpy((iq19_zero_ADC[n_norm] - ((long)ADC_sf[plane][chan]<<19) ),iq19_k_norm_ADC[n_norm])); + return _IQ19toIQ(_IQ19mpy((((long)ADC_f[plane][chan]<<19) - iq19_zero_ADC[plane][chan]),iq19_k_norm_ADC[plane][chan])); +} + + + +#if (USE_INTERNAL_ADC==1) +#pragma CODE_SECTION(norma_adc_internal_sf,".fast_run2"); +_iq norma_adc_internal_sf(int l) +{ + return _IQ19toIQ(_IQ19mpy((((long)ADC_sf[2][l]<<19) - iq19_zero_ADC[2][l]),iq19_k_norm_ADC[2][l])); +} +#endif + + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +// +//#pragma CODE_SECTION(fast_read_all_adc_one,".fast_run"); +//void fast_read_all_adc_one(int cc) +//{ +// int i,k; +// int t; +// +// i_led1_on_off(1); +// +// project.adc[0].read_pbus(&project.adc[0]); +// +// for (k=0;k<16;k++) +// { +// t = project.adc[0].read.pbus.adc_value[k]; +// ADC_fast[0][k][cc] = t; +// +// // save max values +// if (t>ADC_fast[0][k][1] || cc==3) +// ADC_fast[0][k][1] = t; +// // save min values +// if (tflags.bit.error==0 ) +// { +// +// +// +// fast_read_all_adc_one(3); +// pause_1000(p); +// fast_read_all_adc_one(4); +// pause_1000(p); +// fast_read_all_adc_one(5); +// pause_1000(p); +// fast_read_all_adc_one(6); +// pause_1000(p); +// fast_read_all_adc_one(7); +// pause_1000(p); +// fast_read_all_adc_one(8); +// +// +// +// for (k=0;k<16;k++) +// { +// ADC_fast[0][k][0] = (-ADC_fast[0][k][1] - ADC_fast[0][k][2] + ADC_fast[0][k][3] + ADC_fast[0][k][4] +// +ADC_fast[0][k][5] + ADC_fast[0][k][6] + ADC_fast[0][k][7] + ADC_fast[0][k][8]) >> 2; // 4 +// } +// +// } +// else +// { +// for (k=0;k<16;k++) +// { +// ADC_fast[0][k][0] = 5000; // error +// } +// } +// +// +// if (project.adc[1].status == component_Ready +// && project.controller.read.errors.bit.error_pbus == 0 +// && project.controller.read.errors_buses.bit.slave_addr_error==0 +// && project.x_parallel_bus->flags.bit.error==0 ) +// { +// +// fast_read_all_adc_two(); +// } +// else +// { +// for (k=0;k<16;k++) +// { +// ADC_fast[1][k][0] = 5000; // error +// } +// } +// +//} + +///////////////////////////////////////////////////////// +// +//#pragma CODE_SECTION(norma_fast_adc,".fast_run"); +//void norma_fast_adc(void) +//{ +// int i,k; +//// int bb; +// +//#ifdef LOG_ACP_TO_BUF +// static int c_log=0; +// static int n_log_acp_p=0; +// static int n_log_acp_c=2; +// static int n_log_acp_p_2=0; +// static int n_log_acp_c_2=2; +// +//#endif +// +// for (i=0;iflags.bit.error==0 ) +// { +// for (k=0;k<16;k++) +// { +// iq_norm_ADC[i][k] = _IQ19toIQ(_IQ19mpy((-iq19_zero_ADC[i][k] + ((long)ADC_fast[i][k][0]<<19) ),iq19_k_norm_ADC[i][k])); +// } +// } +// else +// { +// for (k=0;k<16;k++) +// { +// iq_norm_ADC[i][k] = 0; +// } +// +// } +// +// } +// +//#ifdef LOG_ACP_TO_BUF +// if (c_log>=SIZE_BUF_LOG_ACP) +// c_log=0; +// BUF_ADC[c_log]=ADC_fast[n_log_acp_p][n_log_acp_c][0]; +// BUF_ADC_2[c_log]=ADC_fast[n_log_acp_p_2][n_log_acp_c_2][3]; +// c_log++; +//#endif +// +////i_led2_off(); +//} + +///////////////////////////////////////////////////////// + +/* +#pragma CODE_SECTION(norma_all_adc,".fast_run"); +void norma_all_adc(void) +{ + int i,k; +// int bb; +#ifdef LOG_ACP_TO_BUF + static int c_log=0; + static int n_log_acp_p=0; + static int n_log_acp_c=2; + static int n_log_acp_p_2=0; + static int n_log_acp_c_2=5; + +#endif + + for (i=0;iread_pbus(&project.adc[i]); + + if ( project.adc[i].status == component_Ready + && project.controller.read.errors.bit.error_pbus == 0 + && project.controller.read.errors_buses.bit.slave_addr_error==0 + && project.x_parallel_bus->flags.bit.error==0 ) + { + for (k=0;k<16;k++) + { + +// ADC_f[i][k] = (int)pr->data.adc[i].acc_short[k]; + +#ifdef ADC_READ_FROM_PARALLEL_BUS + ADC_f[i][k] = project.adc[i].read.pbus.adc_value[k]; + ADC_sf[i][k] += (((int)(ADC_f[i][k] - ADC_sf[i][k]))>>SDVIG_K_FILTER_S); +#else +// ADC_f[i][k] = project.adc[i].fpga.read.channels[k].value.acc_short;//iq_norm_ADC[i][k] = _IQ19toIQ(_IQ19mpy((iq19_zero_ADC[i][k] - ((long)project.adc[i].fpga.read.channels[k].value.acc_short<<19) ),iq19_k_norm_ADC[i][k])); +#endif + iq_norm_ADC[i][k] = _IQ19toIQ(_IQ19mpy((-iq19_zero_ADC[i][k] + ((long)ADC_f[i][k]<<19) ),iq19_k_norm_ADC[i][k])); +// iq_norm_ADC_sf[i][k] = _IQ19toIQ(_IQ19mpy((iq19_zero_ADC[i][k] - ((long)ADC_sf[i][k]<<19) ),iq19_k_norm_ADC[i][k])); + } + } + else + { + for (k=0;k<16;k++) + { + ADC_f[i][k] = 5000;//DEFAULT_ZERO_ADC; + ADC_sf[i][k] = 5000;//DEFAULT_ZERO_ADC; + iq_norm_ADC[i][k] = 0; + } + + } + + } + +#ifdef LOG_ACP_TO_BUF + if (c_log>=SIZE_BUF_LOG_ACP) + c_log=0; + BUF_ADC[c_log]=ADC_f[n_log_acp_p][n_log_acp_c]; + BUF_ADC_2[c_log]=ADC_f[n_log_acp_p_2][n_log_acp_c_2]; + c_log++; +#endif + + +#if (USE_INTERNAL_ADC==1) + iq_norm_ADC[COUNT_ARR_ADC_BUF-1][0] = norma_adc_internal_sf(0); + iq_norm_ADC[COUNT_ARR_ADC_BUF-1][1] = norma_adc_internal_sf(1); + iq_norm_ADC[COUNT_ARR_ADC_BUF-1][3] = norma_adc_internal_sf(3); +#endif +//i_led2_off(); +} +*/ +//////////////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(norma_adc_nc,".fast_run"); +void norma_adc_nc(int nc) +{ + int k; +// int bb; + + project.read_errors_controller(); + project.adc[nc].read_pbus(&project.adc[nc]); + + if ( project.adc[nc].status == component_Ready + && project.controller.read.errors.bit.error_pbus == 0 + && project.controller.read.errors_buses.bit.slave_addr_error==0 + && project.x_parallel_bus->flags.bit.error==0 ) + { + for (k=0;k<16;k++) + { + + ADC_f[nc][k] = project.adc[nc].read.pbus.adc_value[k]; + ADC_sf[nc][k] += (((int)(ADC_f[nc][k] - ADC_sf[nc][k]))>>SDVIG_K_FILTER_S); + iq_norm_ADC[nc][k] = _IQ19toIQ(_IQ19mpy((-iq19_zero_ADC[nc][k] + ((long)ADC_f[nc][k]<<19) ),iq19_k_norm_ADC[nc][k])); + } + } + else + { + for (k=0;k<16;k++) + { + ADC_f[nc][k] = 5000;//DEFAULT_ZERO_ADC; + ADC_sf[nc][k] = 5000;//DEFAULT_ZERO_ADC; + iq_norm_ADC[nc][k] = 0; + } + + } +} + +//////////////////////////////////////////////////////////////////// + + +#pragma CODE_SECTION(calc_norm_ADC_1,".fast_run"); +void calc_norm_ADC_1(int run_norma) +{ + _iq a1,a2,a3; + +#if (USE_ADC_1) + + if (run_norma) + norma_adc_nc(1); + + +#if (_FLOOR6==1) + + analog.T_U01 = + analog.T_U02 = + analog.T_U03 = + analog.T_U04 = + analog.T_U05 = + analog.T_U06 = + analog.T_U07 = + analog.T_Water_external = + analog.T_Water_internal = + + analog.P_Water_internal = + + analog.T_Air_01 = + analog.T_Air_02 = + analog.T_Air_03 = + analog.T_Air_04 = 0; + +#else + analog.T_U01 = iq_norm_ADC[1][1]; + analog.T_U02 = iq_norm_ADC[1][2]; + analog.T_U03 = iq_norm_ADC[1][3]; + analog.T_U04 = iq_norm_ADC[1][4]; + analog.T_U05 = iq_norm_ADC[1][5]; + analog.T_U06 = iq_norm_ADC[1][6]; + analog.T_U07 = iq_norm_ADC[1][7]; + analog.T_Water_external = iq_norm_ADC[1][9]; + analog.T_Water_internal = iq_norm_ADC[1][8]; + + analog.P_Water_internal = iq_norm_ADC[1][14]; + + analog.T_Air_01 = iq_norm_ADC[1][10]; + analog.T_Air_02 = iq_norm_ADC[1][11]; + analog.T_Air_03 = iq_norm_ADC[1][12]; + analog.T_Air_04 = iq_norm_ADC[1][13]; + + +#endif +#else + + analog.T_U01 = + analog.T_U02 = + analog.T_U03 = + analog.T_U04 = + analog.T_U05 = + analog.T_U06 = + analog.T_U07 = + analog.T_Water_external = + analog.T_Water_internal = + + analog.P_Water_internal = + + analog.T_Air_01 = + analog.T_Air_02 = + analog.T_Air_03 = + analog.T_Air_04 = 0; + +#endif +// analog.iqI_vozbud = iq_norm_ADC[1][13]; + +} + +//////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(calc_norm_ADC_0,".fast_run"); +void calc_norm_ADC_0(int run_norma) +{ + _iq a1,a2,a3; + +#if (USE_ADC_0) + + if (run_norma) + norma_adc_nc(0); + +#if (_FLOOR6) + analog.iqU_1 = iq_norm_ADC[0][0] - analog_zero.iqU_1 + analog.iqU_1_imit; + analog.iqU_2 = iq_norm_ADC[0][1] - analog_zero.iqU_2 + analog.iqU_1_imit; +#else + analog.iqU_1 = iq_norm_ADC[0][0] - analog_zero.iqU_1; + analog.iqU_2 = iq_norm_ADC[0][1] - analog_zero.iqU_2; +#endif + analog.iqIu_1 = iq_norm_ADC[0][2]; + analog.iqIv_1 = iq_norm_ADC[0][3]; + analog.iqIw_1 = iq_norm_ADC[0][4]; + + analog.iqIu_2 = iq_norm_ADC[0][5]; + analog.iqIv_2 = iq_norm_ADC[0][6]; + analog.iqIw_2 = iq_norm_ADC[0][7]; + + analog.iqIin_1 = -iq_norm_ADC[0][9]; // + analog.iqIin_2 = -iq_norm_ADC[0][9]; // + + analog.iqUin_A1B1 = iq_norm_ADC[0][10]; + +// 23550.1 - +// 23550.1 + + analog.iqUin_B1C1 = iq_norm_ADC[0][11]; // 23550.1 + analog.iqUin_A2B2 = iq_norm_ADC[0][12]; // 23550.1 + +// 23550.3 bs1 bs2 + +// analog.iqUin_B1C1 = iq_norm_ADC[0][12]; // 23550.3 +// analog.iqUin_A2B2 = iq_norm_ADC[0][11]; // 23550.3 +// + analog.iqUin_B2C2 = iq_norm_ADC[0][13]; + + analog.iqIbreak_1 = iq_norm_ADC[0][14]; + analog.iqIbreak_2 = iq_norm_ADC[0][15]; + +#else + analog.iqU_1 = analog.iqIu_1 = analog.iqIu_2 = analog.iqIv_1 = analog.iqIv_2 = + analog.iqIw_1 = analog.iqIw_2 = analog.iqIin_1 = analog.iqIin_2 = analog.iqUin_A1B1 = + analog.iqUin_B1C1 = analog.iqUin_A2B2 = analog.iqUin_B2C2 = analog.iqIbreak_1 = analog.iqIbreak_2 + = 0; +#endif + + analog.iqUin_C1A1 = -(analog.iqUin_A1B1 + analog.iqUin_B1C1); + analog.iqUin_C2A2 = -(analog.iqUin_A2B2 + analog.iqUin_B2C2); + + + + filter.iqU_1_long = exp_regul_iq(koef_Uzpt_long_filter, filter.iqU_1_long, analog.iqU_1); + filter.iqU_2_long = exp_regul_iq(koef_Uzpt_long_filter, filter.iqU_2_long, analog.iqU_2); + + +// analog.iqU_1_fast = filter_U1_3point(analog.iqU_1_fast); + filter.iqU_1_fast = exp_regul_iq(koef_Uzpt_fast_filter, filter.iqU_1_fast, analog.iqU_1); + filter.iqU_2_fast = exp_regul_iq(koef_Uzpt_fast_filter, filter.iqU_2_fast, analog.iqU_2); + + +// filter.iqUzpt_2_2_fast = exp_regul_iq(koef_Uzpt_fast_filter, filter.iqUzpt_2_2_fast, analog.iqUzpt_2_2); + + + +//15 + + + analog.iqIm_1 = im_calc(analog.iqIu_1, analog.iqIv_1, analog.iqIw_1); + analog.iqIm_2 = im_calc(analog.iqIu_2, analog.iqIv_2, analog.iqIw_2); + + analog.iqIu = analog.iqIu_1+analog.iqIu_2; + analog.iqIv = analog.iqIv_1+analog.iqIv_2; + analog.iqIw = analog.iqIw_1+analog.iqIw_2; + + analog.iqIm = im_calc(analog.iqIu, analog.iqIv, analog.iqIw); + + + analog.iqIin_sum = analog.iqIin_1+analog.iqIin_2; + +// analog.iqIm_3 = im_calc(analog.iqIa1_1_fir_n+analog.iqIa2_1_fir_n, analog.iqIb1_1_fir_n+analog.iqIb2_1_fir_n, analog.iqIc1_1_fir_n+analog.iqIc2_1_fir_n); + + analog.iqUin_m1 = im_calc(analog.iqUin_A1B1, analog.iqUin_B1C1, analog.iqUin_C1A1); + analog.iqUin_m2 = im_calc(analog.iqUin_A2B2, analog.iqUin_B2C2, analog.iqUin_C2A2); + +// analog.iqUin_m2 = im_calc(analog.UinA2, analog.UinB2, analog.UinC2); + + filter.iqUin_m1 = exp_regul_iq(koef_Uin_filter, filter.iqUin_m1, analog.iqUin_m1); + filter.iqUin_m2 = exp_regul_iq(koef_Uin_filter, filter.iqUin_m2, analog.iqUin_m2); + + + +// i_led1_on_off(0); +// i_led1_on_off(1); + +//1 + + filter.iqIm_1 = exp_regul_iq(koef_Im_filter, filter.iqIm_1, analog.iqIm_1); + filter.iqIm_2 = exp_regul_iq(koef_Im_filter, filter.iqIm_2, analog.iqIm_2); + filter.iqIm = exp_regul_iq(koef_Im_filter, filter.iqIm, analog.iqIm); + + filter.iqIin_sum = exp_regul_iq(koef_Im_filter, filter.iqIin_sum, analog.iqIin_sum); + +//3 +// filter_batter2_Iin.InpVarCurr = (analog.iqIin_1)-ZERO_I_IN; + // filter_batter2_Iin.calc(&filter_batter2_Iin); + +// filter.iqIin = _IQmpy(filter_batter2_Iin.Out,_IQ_09); + + + filter.iqIin_1 = exp_regul_iq(koef_Im_filter, filter.iqIin_1, analog.iqIin_1); + filter.iqIin_2 = exp_regul_iq(koef_Im_filter, filter.iqIin_2, analog.iqIin_2); + + a1 = analog.iqU_1+analog.iqU_2; + a2 = analog.iqIin_1; + a3 = _IQmpy(a1,a2); + analog.PowerScalar = a3; +// filter.Power = analog.iqU_1+analog.iqU_2; + filter.PowerScalar = exp_regul_iq(koef_Power_filter, filter.PowerScalar, analog.PowerScalar); + filter.PowerScalarFilter2 = exp_regul_iq(koef_Power_filter2, filter.PowerScalarFilter2, filter.PowerScalar); + +} + + + +#pragma DATA_SECTION(acp_zero,".slow_vars") +_iq19 acp_zero[16]; +#pragma DATA_SECTION(acp_summ,".slow_vars") +long acp_summ[16]; +/********************************************************************/ +/* y */ +/********************************************************************/ +void detect_zero_analog(int nc) +{ + long i,k; + + + _iq koef_zero_ADC_filter = _IQ19(0.00002/0.0003185); + + + for (k=0;k<16;k++) + { + acp_zero[k] = 0; + acp_summ[k] = 0; + } + + + + for (i=0; i=1) +#define R_ADC_DEFAULT_0 { 271, 271, 876, 876, 876, 876, 876, 876, 249, 249, 301, 301, 301, 301, 301, 301 } +#define K_LEM_ADC_DEFAULT_0 { 7200, 7200, 5000, 5000, 5000, 5000, 5000, 5000, 5000, 5000, 8400, 8400, 8400, 8400, 5000, 5000 } +#define NORMA_ADC_DEFAULT_0 { NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP } +#endif + +#if(C_adc_number>=2) +#define R_ADC_DEFAULT_1 { 1, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190 } +#define K_LEM_ADC_DEFAULT_1 { 1, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1 } +#define NORMA_ADC_DEFAULT_1 { NORMA_ACP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_TEMPER_MILL_AMP, NORMA_ACP_P, NORMA_ACP } +#endif + +#if(C_adc_number>=3) +#define R_ADC_DEFAULT_2 { 271, 271, 887, 887, 887, 887, 887, 887, 250, 250, 3125, 3125, 3125, 3125, 309, 309 } +#define K_LEM_ADC_DEFAULT_2 { 7200, 7200, 5000, 5000, 5000, 5000, 5000, 5000, 5000, 5000, 60000, 60000, 60000, 60000, 5000, 5000 } +#define NORMA_ADC_DEFAULT_2 { NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP } +#endif + +// 23550.1 + +//#if(C_adc_number>=1) +//#define R_ADC_DEFAULT_0 { 271, 271, 887, 887, 887, 887, 887, 887, 250, 250, 312, 312, 312, 312, 309, 309 } +//#define K_LEM_ADC_DEFAULT_0 { 7200, 7200, 5000, 5000, 5000, 5000, 5000, 5000, 5000, 5000, 8400, 8400, 8400, 8400, 5000, 5000 } +//#define NORMA_ADC_DEFAULT_0 { NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP } +//#endif +// +//#if(C_adc_number>=2) +//#define R_ADC_DEFAULT_1 { 1, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190, 6190 } +//#define K_LEM_ADC_DEFAULT_1 { 1, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1000, 1 } +//#define NORMA_ADC_DEFAULT_1 { NORMA_ACP, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_TEMPER, NORMA_ACP_P, NORMA_ACP } +//#endif +// +//#if(C_adc_number>=3) +//#define R_ADC_DEFAULT_2 { 271, 271, 887, 887, 887, 887, 887, 887, 250, 250, 3125, 3125, 3125, 3125, 309, 309 } +//#define K_LEM_ADC_DEFAULT_2 { 7200, 7200, 5000, 5000, 5000, 5000, 5000, 5000, 5000, 5000, 60000, 60000, 60000, 60000, 5000, 5000 } +//#define NORMA_ADC_DEFAULT_2 { NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP } +//#endif + + + + +#if (USE_INTERNAL_ADC==1) +#define R_ADC_DEFAULT_INTERNAL { 100,100,100,100,100,100,100,100,1248,1248,1248,100,100,100,100,100 } +#define K_LEM_ADC_DEFAULT_INTERNAL { 30,30,30,30,10,10,10,10,621,621,621,100,10,10,10,10 } +#define NORMA_ADC_DEFAULT_INTERNAL { NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP, NORMA_ACP } +#endif + + + + + +/* + //awa3 + //14 out1 + 0 - 11 + //15 out2 + 0 - 11 + //8 + 0 - 20 | 0 - 200 / + 0V - 1.5V / 0 - 200 / + //9 + 0 - 20 | 0 - 200 / + 0V - 1.5V / 0 - 200 / + + //10 + 0 - 20 | 0 - 200 / + 0V - 1.5V / 0 - 200 / + + //11 + 0 - 20 | 0 - 200 / + 0V - 1.5V / 0 - 200 / + //12 + 4 - 20 | 0 - 10 / + 0.3V - 1.5V / 0 - 10 / + + //13 + 4 - 20 | 0 - 10 / + 0.3V - 1.5V / 0 - 10 / +*/ + + +typedef union +{ + + struct + { + unsigned int c0_plus :1; /* 0 + */ + unsigned int c1_plus :1; /* 0 + */ + unsigned int c2_plus :1; /* 0 + */ + unsigned int c3_plus :1; /* 0 + */ + unsigned int c4_plus :1; /* 0 + */ + unsigned int c5_plus :1; /* 0 + */ + unsigned int c6_plus :1; /* 0 + */ + unsigned int c7_plus :1; /* 0 + */ + unsigned int c8_plus :1; /* 0 + */ + unsigned int c9_plus :1; /* 0 + */ + unsigned int c10_plus :1; /* 0 + */ + unsigned int c11_plus :1; /* 0 + */ + unsigned int c12_plus :1; /* 0 + */ + unsigned int c13_plus :1; /* 0 + */ + unsigned int c14_plus :1; /* 0 + */ + unsigned int c15_plus :1; /* 0 + */ + } bit; /* */ + unsigned long all; /* */ + +} ERR_ADC_PLUS_PROTECT; + + +typedef union +{ + + struct + { + unsigned int c0_minus :1; /* 0 - */ + unsigned int c1_minus :1; /* 0 - */ + unsigned int c2_minus :1; /* 0 - */ + unsigned int c3_minus :1; /* 0 - */ + unsigned int c4_minus :1; /* 0 - */ + unsigned int c5_minus :1; /* 0 - */ + unsigned int c6_minus :1; /* 0 - */ + unsigned int c7_minus :1; /* 0 - */ + unsigned int c8_minus :1; /* 0 - */ + unsigned int c9_minus :1; /* 0 - */ + unsigned int c10_minus :1; /* 0 - */ + unsigned int c11_minus :1; /* 0 - */ + unsigned int c12_minus :1; /* 0 - */ + unsigned int c13_minus :1; /* 0 - */ + unsigned int c14_minus :1; /* 0 - */ + unsigned int c15_minus :1; /* 0 - */ + + } bit; /* */ + unsigned int all; /* */ + +} ERR_ADC_MINUS_PROTECT; + + +typedef struct +{ + ERR_ADC_PLUS_PROTECT plus; + ERR_ADC_MINUS_PROTECT minus; +} ERR_ADC_PROTECT; + + +/* y y */ +typedef struct +{ + _iq iqU_1; + _iq iqU_2; + + _iq iqU_1_fast; + _iq iqU_2_fast; + + _iq iqU_1_long; + _iq iqU_2_long; + + _iq iqIu_1; + _iq iqIv_1; + _iq iqIw_1; + + _iq iqIu_2; + _iq iqIv_2; + _iq iqIw_2; + + _iq iqIu_1_rms; + _iq iqIv_1_rms; + _iq iqIw_1_rms; + + _iq iqIu_2_rms; + _iq iqIv_2_rms; + _iq iqIw_2_rms; + + _iq iqIu; + _iq iqIv; + _iq iqIw; + + _iq iqIin_1; + _iq iqIin_2; + + _iq iqUin_A1B1; + _iq iqUin_B1C1; + _iq iqUin_C1A1; + + _iq iqUin_A2B2; + _iq iqUin_B2C2; + _iq iqUin_C2A2; + + _iq iqUin_A1B1_rms; + _iq iqUin_B1C1_rms; + _iq iqUin_C1A1_rms; + + _iq iqUin_A2B2_rms; + _iq iqUin_B2C2_rms; + _iq iqUin_C2A2_rms; + + _iq iqUin_m1; + _iq iqUin_m2; + + _iq iqIbreak_1; + _iq iqIbreak_2; //39 + + _iq T_U01; + _iq T_U02; + _iq T_U03; + _iq T_U04; + _iq T_U05; + _iq T_U06; + _iq T_U07; + + _iq T_Water_external; + _iq T_Water_internal; + + _iq T_Air_01; + _iq T_Air_02; + _iq T_Air_03; + _iq T_Air_04; + + _iq P_Water_internal; //53 + + + _iq iqI_vozbud; + + _iq iqIin_sum; + + _iq iqIm_1; + _iq iqIm_2; + + _iq iqIm; + + + _iq iqM; + + _iq PowerScalar; + _iq PowerScalarFilter2; + _iq PowerFOC; + + _iq iqU_1_imit; //63 + + + /* + _iq iqUzpt_1_2; //uzpt1 bs2 + _iq iqUzpt_2_2; //uzpt2 bs2 + _iq iqUzpt_1_2_fast; //uzpt1 bs2 + _iq iqUzpt_2_2_fast; //uzpt2 bs2 + _iq iqUzpt_1_2_long; //uzpt1 bs2 + _iq iqUzpt_2_2_long; //uzpt2 bs2 + _iq iqIin_1_1; //Iin AF1 BS1 + _iq iqIin_2_1; //Iin AF2 BS1 + _iq iqIin_3_1; //Iin AF3 BS1 + _iq iqIin_4_1; //Iin AF4 BS1 + _iq iqIin_5_1; //Iin AF5 BS1 + _iq iqIin_6_1; //Iin AF6 BS1 + _iq iqIin_1_2; //Iin AF1 BS2 + _iq iqIin_2_2; //Iin AF2 BS2 + _iq iqIin_3_2; //Iin AF3 BS2 + _iq iqIin_4_2; //Iin AF4 BS2 + _iq iqIin_5_2; //Iin AF5 BS2 + _iq iqIin_6_2; //Iin AF6 BS2 + _iq iqUin_AB; // AB + _iq iqUin_BC; // BC + _iq iqUin_CA; // CA + _iq iqUin_AB_sf; // AB + _iq iqUin_BC_sf; // BC + _iq iqUin_CA_sf; // CA + _iq iqT_WATER_in; // + _iq iqT_WATER_out; // + _iq iqT_AIR_in_up; // () + _iq iqT_AIR_in_down;// () + _iq iqP_WATER_in; // + _iq iqP_WATER_out; // + + _iq iqT_BK1_BK12; // BK1_BK12 + _iq iqT_BK13_BK24; // BK13_BK24 + + _iq iqUin_m1; // + + + _iq iqIu_1_1; //Iu AF1 BS1 + _iq iqIu_1_2; //Iu AF2 BS1 + _iq iqIv_1_1; //Iv AF3 BS1 + _iq iqIv_1_2; //Iv AF4 BS1 + _iq iqIw_1_1; //Iw AF5 BS1 + _iq iqIw_1_2; //Iw AF6 BS1 + + + + _iq iqIu_2_1; //Iu AF1 BS2 + _iq iqIu_2_2; //Iu AF2 BS2 + _iq iqIv_2_1; //Iv AF3 BS2 + _iq iqIv_2_2; //Iv AF4 BS2 + _iq iqIw_2_1; //Iw AF5 BS2 + _iq iqIw_2_2; //Iw AF6 BS2 + + _iq iqIm_1; + _iq iqIm_2; + + _iq iqWexp; + _iq iqWout; + + _iq iqM; +*/ +} ANALOG_VALUE; + + +#define ANALOG_VALUE_DEFAULT {0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0, 0} +/* y y */ + + +#define ERR_LEVEL_ADC_PLUS 3950 //+1270A //2950 // +650A //3467 // 3367 //3367 //3267 // 0xfff-0x29c +#define ERR_LEVEL_ADC_MINUS 150 //-1270A //1150 //-650A // 267 //367 + +#define ERR_LEVEL_ADC_PLUS_6 3800 //3783 //3623~1150 // 3462 ~ 1050 A // 3320 ~ 960A //3680 //3267 // 0xfff-0x29c +#define ERR_LEVEL_ADC_MINUS_6 1000 //267 //367 + +#define MIN_DETECT_UD_ZERO 2300 + + +#define level_err_ADC_PLUS_default {ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,\ + ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,\ + ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,\ + ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS,ERR_LEVEL_ADC_PLUS} + +#define level_err_ADC_MINUS_default {ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,\ + ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,\ + ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,\ + ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS,ERR_LEVEL_ADC_MINUS} + + +extern ANALOG_VALUE analog; +extern ANALOG_VALUE filter; +extern ANALOG_VALUE analog_zero; + +//void calc_norm_ADC(int fast); +void calc_norm_ADC_0(int run_norma); +void calc_norm_ADC_1(int run_norma); +void Init_Adc_Variables(void); +void norma_adc_nc(int nc); + + + +extern int ADC_f[COUNT_ARR_ADC_BUF][16]; +extern int zero_ADC[COUNT_ARR_ADC_BUF][16]; + +extern ERR_ADC_PROTECT err_adc_protect[COUNT_ARR_ADC_BUF],mask_err_adc_protect[COUNT_ARR_ADC_BUF]; + +extern unsigned int R_ADC[COUNT_ARR_ADC_BUF][16]; +extern unsigned int K_LEM_ADC[COUNT_ARR_ADC_BUF][16]; +extern float K_NORMA_ADC[COUNT_ARR_ADC_BUF][16]; + +//void norma_all_adc(void); +extern _iq koef_Uzpt_long_filter, koef_Uzpt_fast_filter, koef_Uin_filter, koef_Im_filter, koef_Power_filter, koef_Power_filter2; + +void detect_zero_analog(int nc); + + +#if (USE_INTERNAL_ADC==1) + +void Init_Internal_Adc(void); + +#endif + + +#endif // end _ADC_TOOLS diff --git a/Inu/Src2/551/main/alarm_log.c b/Inu/Src2/551/main/alarm_log.c new file mode 100644 index 0000000..7dd9e2e --- /dev/null +++ b/Inu/Src2/551/main/alarm_log.c @@ -0,0 +1,196 @@ +/* + * alarm_log.c + * + * Created on: 11 . 2024 . + * Author: yura + */ + +#include "edrk_main.h" +#include "alarm_log_can.h" +#include "alarm_log.h" +#include "log_params.h" +#include "logs_hmi.h" +#include "global_time.h" + + +#define PAUSE_AUTO_SAVE_ALARM_LOG_SECONDS 20 // 20 sec +#define PAUSE_AUTO_STOP_ALARM_LOG_SECONDS 5 // 5 sec + +void send_alarm_log_pult(void) +{ + static int prev_imit_send_alarm_log_pult = 0; + int to_store = 0; + + static int flag_wait_alarm = 0, prev_Ready2 = 0, flag_store_log = 0, flag_store_log_prepare = 0, flag_auto_logs = 0, flag_stop_alarm = 0; + + static unsigned int pause_store_logs = 0, pause_stop_logs = 0; + + + + // + if (edrk.imit_send_alarm_log_pult && prev_imit_send_alarm_log_pult == 0) + flag_store_log = 1; + prev_imit_send_alarm_log_pult = edrk.imit_send_alarm_log_pult; + + + // + + + // ? + if (prev_Ready2==0 && edrk.Status_Ready.bits.ready_final) + { + flag_wait_alarm = 1; + flag_stop_alarm = 0; + } + + if (prev_Ready2==1 && edrk.Status_Ready.bits.ready_final==0) + { + // , + init_timer_sec(&pause_stop_logs); + + flag_stop_alarm = 1; + } + prev_Ready2 = edrk.Status_Ready.bits.ready_final; + + + // + if (flag_wait_alarm && edrk.summ_errors) + { + // + flag_store_log_prepare = 1; + flag_wait_alarm = 0; + flag_stop_alarm = 0; + init_timer_sec(&pause_store_logs); + } + +// // , +// if (flag_stop_alarm) +// { +// +// +// } + + // , + if (flag_stop_alarm && detect_pause_sec(PAUSE_AUTO_STOP_ALARM_LOG_SECONDS, &pause_stop_logs)) + { + flag_stop_alarm = 0; + flag_wait_alarm = 0; + } + + + if (flag_store_log_prepare) + { + flag_auto_logs = detect_pause_sec(PAUSE_AUTO_SAVE_ALARM_LOG_SECONDS, &pause_store_logs); + } + + if (flag_auto_logs) + { + flag_store_log_prepare = 0; + flag_auto_logs = 0; + // + flag_store_log = 1; + + flag_wait_alarm = 0; + flag_stop_alarm = 0; + } + + + + + + + + // + if (flag_store_log) + { + + if (edrk.pult_cmd.log_what_memory >= 2) + to_store = 2; + else + if (edrk.pult_cmd.log_what_memory >= 1) + to_store = 1; + else + to_store = 0; + + log_to_HMI.sdusb = to_store; + + + // + if (log_to_HMI.sdusb) + { + log_to_HMI.send_log = 3; + } + + flag_store_log = 0; + + } + + + + +} + + +void test_send_alarm_log(int alarm_cmd) +{ + static unsigned int points_alarm_log = 1000; + // static unsigned int nchannel_alarm_log = 30; + static int prev_alarm_cmd = 0; + static int local_alarm_cmd = 0; + + + + if (alarm_cmd && prev_alarm_cmd==0 && alarm_log_can.stage==0) + { +// i_led2_on(); + + alarm_log_can.post_points = COUNT_SAVE_LOG_OFF;//100; // + alarm_log_can.oscills = log_params.BlockSizeErr;//nchannel_alarm_log; // + + alarm_log_can.global_enable = 1; + + alarm_log_can.start_adr_temp = (int *)0xc0000; // , . + + // alarm_log_can.finish_adr_temp = (int *)0xa0000; // , . + + alarm_log_can.start_adr_real_logs = (int *)log_params.start_address_log;//(int *)START_ADDRESS_LOG; // + alarm_log_can.finish_adr_real_log = (int *)log_params.end_address_log;//(int *)logpar.; // + + alarm_log_can.current_adr_real_log = (int *)log_params.addres_mem; + + + alarm_log_can.temp_points = points_alarm_log; // . + // alarm_log_can.real_points = 1000; // , . + + alarm_log_can.step = 450; // mks + local_alarm_cmd = alarm_cmd; +// alarm_log_can.status_alarm = alarm_cmd;//cmd_alarm_log; // + alarm_log_can.start = 0x1; + alarm_log_can.stop = 0x1; + alarm_log_can.copy2temp = 0x1; + + + alarm_log_can.clear(&alarm_log_can); +// alarm_log_can.send(&alarm_log_can); + +// i_led2_off(); + } + else + local_alarm_cmd = 0; + + alarm_log_can.status_alarm = local_alarm_cmd;//cmd_alarm_log; // + alarm_log_can.send(&alarm_log_can); + + if (alarm_log_can.stage) + { +// i_led2_on_off(1); + } + else + { +// i_led2_on_off(0); + } + + prev_alarm_cmd = alarm_cmd; + +} +//////////////////////////////////////////////////////////// diff --git a/Inu/Src2/551/main/alarm_log.h b/Inu/Src2/551/main/alarm_log.h new file mode 100644 index 0000000..c8fef58 --- /dev/null +++ b/Inu/Src2/551/main/alarm_log.h @@ -0,0 +1,16 @@ +/* + * alarm_log.h + * + * Created on: 11 . 2024 . + * Author: yura + */ + +#ifndef SRC_MAIN_ALARM_LOG_H_ +#define SRC_MAIN_ALARM_LOG_H_ + +void test_send_alarm_log(int alarm_cmd); +void send_alarm_log_pult(void); + + + +#endif /* SRC_MAIN_ALARM_LOG_H_ */ diff --git a/Inu/Src2/551/main/alg_simple_scalar.c b/Inu/Src2/551/main/alg_simple_scalar.c new file mode 100644 index 0000000..7fc3c8f --- /dev/null +++ b/Inu/Src2/551/main/alg_simple_scalar.c @@ -0,0 +1,976 @@ +/* + * alg_simple_scalar.c + * + * Created on: 26 . 2020 . + * Author: Yura + */ + + +#include +#include +//#include +#include +#include +#include +#include +#include +//#include "log_to_mem.h" +#include "IQmathLib.h" +#include "math_pi.h" +#include "mathlib.h" +#include "params_pwm24.h" +#include "filter_v1.h" +#include "log_to_memory.h" + + +#pragma DATA_SECTION(simple_scalar1,".slow_vars"); +ALG_SIMPLE_SCALAR simple_scalar1 = ALG_SIMPLE_SCALAR_DEFAULT; + +_iq koefBpsi = _IQ(0.05); //0.05 + +void init_simple_scalar(void) +{ + simple_scalar1.mzz_add_1 = _IQ(MZZ_ADD_1/NORMA_MZZ); + simple_scalar1.mzz_add_2 = _IQ(MZZ_ADD_2/NORMA_MZZ); + simple_scalar1.mzz_add_3 = _IQ(MZZ_ADD_3/NORMA_MZZ); + + simple_scalar1.poluses = _IQ(POLUS); + simple_scalar1.iq_mzz_max_for_fzad = _IQ(1000.0/NORMA_MZZ); + + simple_scalar1.powerzad_add = _IQ(POWERZAD_ADD_MAX); + simple_scalar1.powerzad_dec = _IQ(POWERZAD_DEC); + +// simple_scalar1.k_freq_for_pid = _IQ(1.0); + simple_scalar1.k_freq_for_pid = _IQ(450.0/FREQ_PWM); + + simple_scalar1.iq_add_kp_df = _IQ(ADD_KP_DF); + simple_scalar1.iq_add_ki_df = _IQ(ADD_KI_DF); + + simple_scalar1.min_mzz_for_df = _IQ(MIN_MZZ_FOR_DF/NORMA_MZZ); + + simple_scalar1.pidF_Kp = _IQ(PID_KP_F); + simple_scalar1.pidF_Ki = _IQ(PID_KI_F); + + + + simple_scalar1.pidIm1.Kp=_IQ(PID_KP_IM); + simple_scalar1.pidIm1.Ki=_IQ(PID_KI_IM); + + simple_scalar1.pidIm_Ki = simple_scalar1.pidIm1.Ki; + + simple_scalar1.pidIm1.Kc=_IQ(PID_KC_IM); + simple_scalar1.pidIm1.Kd=_IQ(PID_KD_IM); + + + simple_scalar1.pidIm1.OutMax=_IQ(K_STATOR_MAX); + simple_scalar1.pidIm1.OutMin=_IQ(K_STATOR_MIN); + +////////////// + + + simple_scalar1.pidF.Kp=_IQ(PID_KP_F); + simple_scalar1.pidF.Ki=_IQ(PID_KI_F); + simple_scalar1.pidF.Kc=_IQ(PID_KC_F); + simple_scalar1.pidF.Kd=_IQ(PID_KD_F); + + + simple_scalar1.pidF.OutMax=_IQ(500/NORMA_MZZ); + simple_scalar1.pidF.OutMin=_IQ(0); + // iq_MAX_DELTA_pidF = _IQ(MAX_DELTA_pidF/NORMA_WROTOR); +///////////////////////// +// simple_scalar1.pidPower_Kp = _IQ(PID_KP_POWER); +// simple_scalar1.pidPower_Ki = _IQ(PID_KI_POWER); + + + // iq_add_kp_dpower = _IQ(ADD_KP_DPOWER); + // iq_add_ki_dpower = _IQ(ADD_KI_DPOWER); + + simple_scalar1.pidPower.Kp=_IQ(PID_KP_POWER); + simple_scalar1.pidPower.Ki=_IQ(PID_KI_POWER); + simple_scalar1.pidPower.Ki = _IQmpy(simple_scalar1.pidPower.Ki, simple_scalar1.k_freq_for_pid); // Ki + + simple_scalar1.pidPower.Kc=_IQ(PID_KC_POWER); + simple_scalar1.pidPower.Kd=_IQ(PID_KD_POWER); + + simple_scalar1.pidPower.OutMax=_IQ(500/NORMA_MZZ); + simple_scalar1.pidPower.OutMin=_IQ(0); + + + simple_scalar1.iq_spad_k = _IQ(0.993); //0.993 ~ 0.4 sek 5% + + + // . + simple_scalar1.min_bpsi = _IQ(BPSI_MINIMAL/NORMA_FROTOR); + simple_scalar1.max_bpsi = _IQ(BPSI_MAXIMAL/NORMA_FROTOR); + +} + +/***************************************************************/ +/* / y 3 - + vector_moment(real Frot, - + real fzad, - + real mzz_zad, - - + real *Fz, - - yy + real *Uz1, - - . y 1 + real *Uz2) - - . y 2 + + + y y , y fzad + + y y = 0.5 + + yy 3- . + y y y */ +/****************************************************************/ + + +//#pragma CODE_SECTION(simple_scalar,".fast_run"); +void simple_scalar(int n_alg, + int n_wind_pump, + int direction, + _iq Frot_pid, + _iq Frot, + _iq fzad, + _iq iqKoefOgran, + _iq mzz_zad, + _iq bpsi_const, + _iq iqIm, + _iq iqUin, + _iq Iin, + _iq powerzad, + _iq power_pid, + _iq power_limit, + int mode_oborots_power, + _iq Izad_from_master, + int master, + int count_bs_work, + _iq *Fz, + _iq *Uz1, + _iq *Uz2, + _iq *Izad_out) +{ + + _iq mzz, dF, dI1, Izad, Uz_t1, Kpred_Ip, pred_Ip;//, znak_moment; + _iq dI2, Uz_t2; + + _iq pkk=0,ikk=0; + _iq Im_regul=0; + + + + static _iq bpsi=0; + // static _iq IQ_POLUS=0; + + + static _iq mzz_zad_int=0; + static _iq mzzi=0; + + static _iq I1_i=0; + static _iq I2_i=0; + + static _iq Im1=0; + static _iq Im2=0; + + static _iq Uze_t1=0; + static _iq Uze_t2=0; + + // static _iq fzad_ogr=0; + + + +// static _iq koef_Uz_t_filter=0; + static _iq dI1_prev=0; + static _iq Uz_t1_prev=0; + + static _iq dF_prev = 0; + static _iq mzz_prev = 0; + + // static _iq mzz_add_1, mzz_add_2; + + static _iq fzad_int=0;//, fzad_add_max;//,iq_mzz_max_for_fzad ; + static _iq fzad_add=0; //fzad_dec + _iq halfIm1, halfIm2; + + static _iq powerzad_int=0, powerzad_add_max=0, pidFOutMax = 0, pidFOutMin = 0 ; +//powerzad_dec powerzad_add +// static _iq koef_bpsi=0; + // static _iq min_bpsi=0; + static int flag_uz_t1=0; + + // static _iq correct_err=0; +// static _iq iq_dF_min1=0; +// static _iq iq_dF_min2=0; + _iq pred_dF,Kpred_dF; + static _iq dF_PREDEL_LEVEL2 = 0,dF_PREDEL_LEVEL1=0; + _iq Uze_ogr=0; + + // static _iq iq_spad_k=1; + static _iq myq_temp=0; + static _iq bpsi_filter=0; + static _iq _iq_koef_im_on_tormog = _IQ(KOEF_IM_ON_TORMOG); + static _iq _iq_koef_im_on_tormog_max_temper_break = _IQ(KOEF_IM_ON_TORMOG_WITH_MAX_TEMPER_BREAK); + static _iq n_iq_koef_im_on_tormog = CONST_IQ_1, t_iq_koef_im_on_tormog = CONST_IQ_1; + + static _iq _iq_koef_im_on_tormog_add =_IQ(0.0005), _iq_koef_im_on_tormog_dec = _IQ(0.01); + +// static _iq F_revers_level00= _IQ(70.0/60.0/NORMA_FROTOR); + static _iq F_revers_level0 = _IQ(90.0/60.0/NORMA_FROTOR); + static _iq F_revers_level1 = _IQ(100.0/60.0/NORMA_FROTOR); + static _iq F_revers_level2 = _IQ(110.0/60.0/NORMA_FROTOR); + static _iq F_revers_level3 = _IQ(120.0/60.0/NORMA_FROTOR); + static _iq F_revers_level4 = _IQ(130.0/60.0/NORMA_FROTOR); + static _iq F_revers_level5 = _IQ(140.0/60.0/NORMA_FROTOR); + static _iq F_revers_level6 = _IQ(150.0/60.0/NORMA_FROTOR); + static _iq F_revers_level7 = _IQ(160.0/60.0/NORMA_FROTOR); + static _iq F_revers_level8 = _IQ(170.0/60.0/NORMA_FROTOR); + static _iq F_revers_level9 = _IQ(180.0/60.0/NORMA_FROTOR); + static _iq F_revers_level10 = _IQ(190.0/60.0/NORMA_FROTOR); + static _iq F_revers_level11 = _IQ(200.0/60.0/NORMA_FROTOR); + static _iq F_revers_level12 = _IQ(210.0/60.0/NORMA_FROTOR); + static _iq F_revers_level13 = _IQ(220.0/60.0/NORMA_FROTOR); + + static _iq kF_revers_level00 = _IQ(0.65); + static _iq kF_revers_level0 = _IQ(0.70); + static _iq kF_revers_level1 = _IQ(0.75); + static _iq kF_revers_level2 = _IQ(0.78); + static _iq kF_revers_level3 = _IQ(0.80); + static _iq kF_revers_level4 = _IQ(0.82); + static _iq kF_revers_level5 = _IQ(0.84); + static _iq kF_revers_level6 = _IQ(0.86); + static _iq kF_revers_level7 = _IQ(0.88); + static _iq kF_revers_level8 = _IQ(0.90); + static _iq kF_revers_level9 = _IQ(0.91); + static _iq kF_revers_level10 = _IQ(0.92); + static _iq kF_revers_level11 = _IQ(0.93); + static _iq kF_revers_level12 = _IQ(0.94); + static _iq kF_revers_level13 = _IQ(0.96); + + + static _iq P_level0 = _IQ(70.0/60.0/NORMA_FROTOR); + static _iq P_level1 = _IQ(150.0/60.0/NORMA_FROTOR); + static _iq P_level2 = _IQ(160.0/60.0/NORMA_FROTOR); + static _iq P_level3 = _IQ(170.0/60.0/NORMA_FROTOR); + static _iq P_level4 = _IQ(180.0/60.0/NORMA_FROTOR); + static _iq P_level5 = _IQ(190.0/60.0/NORMA_FROTOR); + static _iq P_level6 = _IQ(200.0/60.0/NORMA_FROTOR); + static _iq P_level7 = _IQ(210.0/60.0/NORMA_FROTOR); + static _iq P_level8 = _IQ(220.0/60.0/NORMA_FROTOR); + static _iq P_level9 = _IQ(230.0/60.0/NORMA_FROTOR); +// static _iq P_level9 = _IQ(300.0/60.0/NORMA_FROTOR); + + static _iq kP_level0 = _IQ(0.9); + static _iq kP_level1 = _IQ(0.9); + static _iq kP_level2 = _IQ(0.9); + static _iq kP_level3 = _IQ(0.85); + static _iq kP_level4 = _IQ(0.8); + static _iq kP_level5 = _IQ(0.75); + static _iq kP_level6 = _IQ(0.7); + static _iq kP_level7 = _IQ(0.65); + static _iq kP_level8 = _IQ(0.6); + static _iq kP_level9 = _IQ(0.55); + + static _iq pid_kp_power = _IQ(PID_KP_POWER); + static _iq add_mzz_outmax_pidp = _IQ(100.0/NORMA_MZZ); + _iq new_pidP_OutMax = 0; + + _iq k_ogr_p_koef_1 = 0; + _iq k_ogr_p_koef_2 = 0; + + _iq k_ogr_n = 0; + + + _iq Frot_pid_abs; + + _iq d_m=0; + + _iq iq_decr_mzz_power; + + _iq level1_power_ain_decr_mzz, level2_power_ain_decr_mzz; + _iq new_power_limit = 0; + + static _iq koef_Power_filter2 = _IQ(1.0/(FREQ_PWM*EXP_FILTER_KOEF_OGRAN_POWER_LIMIT));//2.2 //30000;// 0,0012//16777;//0,001//13981; + + + + + + Frot_pid_abs = _IQabs(Frot_pid); + +// pidPower.Kp +// +// if (Frot_pid_abs>=P_level0) +// { +// k_ogr_p_koef_1 = CONST_IQ_1 - _IQdiv( (Frot_pid_abs-P_level0) , (P_level9-P_level0) ); +// if (k_ogr_p_koef_1<0) k_ogr_p_koef_1 = 0; +// } +// else +// k_ogr_p_koef_1 = CONST_IQ_1; +// +// //k_ogr_p_koef_1 1 0 +// +// k_ogr_p_koef_2 = CONST_IQ_01 + _IQmpy(CONST_IQ_09, k_ogr_p_koef_1); + +// simple_scalar1.pidPower.Kp = _IQmpy (pid_kp_power, k_ogr_p_koef_2);// _IQ(PID_KP_POWER) + + simple_scalar1.pidPower.Kp = pid_kp_power;//_IQmpy (pid_kp_power, k_ogr_p_koef_2);// _IQ(PID_KP_POWER) + + if (mode_oborots_power == ALG_MODE_SCALAR_OBOROTS) + { + if (simple_scalar1.cmd_new_calc_p_limit) + { + simple_scalar1.flag_decr_mzz_power = 0; + simple_scalar1.iq_decr_mzz_power_filter = CONST_IQ_1; + simple_scalar1.iq_decr_mzz_power = CONST_IQ_1; + new_power_limit = power_limit; + } + else + { + // , + // . + // simple_scalar1.iq_decr_mzz_power_filter 1.0 - , + // 1-MAX_KOEF_OGRAN_POWER_LIMIT - + new_power_limit = power_limit - simple_scalar1.sdvig_power_limit; + if (new_power_limit=(level2_power_ain_decr_mzz-level1_power_ain_decr_mzz)) + d_m = CONST_IQ_1; + else + d_m = _IQdiv(d_m,(level2_power_ain_decr_mzz - level1_power_ain_decr_mzz)); + } + + if (d_m<0) + d_m=0; // + + if (d_m>CONST_IQ_1) + d_m=CONST_IQ_1; // + + // 1.0 0.0 MAX_KOEF_OGRAN_POWER_LIMIT 0.0 + d_m = _IQmpy(d_m, MAX_KOEF_OGRAN_POWER_LIMIT); // + + simple_scalar1.iq_decr_mzz_power = CONST_IQ_1 - d_m;// 1.0 - . MAX_KOEF_OGRAN_POWER_LIMIT . . + + if (simple_scalar1.iq_decr_mzz_power<0) + simple_scalar1.iq_decr_mzz_power=0; + + + simple_scalar1.iq_decr_mzz_power_filter = exp_regul_iq(koef_Power_filter2, + simple_scalar1.iq_decr_mzz_power_filter, + simple_scalar1.iq_decr_mzz_power); + + if (simple_scalar1.iq_decr_mzz_power_filter<0) + simple_scalar1.iq_decr_mzz_power_filter = 0; + + + if (d_m>0) + simple_scalar1.flag_decr_mzz_power = 1; + else + simple_scalar1.flag_decr_mzz_power=0; + + } + } + else + { + simple_scalar1.flag_decr_mzz_power = 0; + simple_scalar1.iq_decr_mzz_power_filter = CONST_IQ_1; + simple_scalar1.iq_decr_mzz_power = CONST_IQ_1; + new_power_limit = power_limit; + } + +#if (ENABLE_DECR_MZZ_POWER_IZAD) + if (simple_scalar1.disable_KoefOgranIzad==0) + simple_scalar1.iqKoefOgranIzad = _IQmpy(iqKoefOgran,simple_scalar1.iq_decr_mzz_power_filter); + else + simple_scalar1.iqKoefOgranIzad = iqKoefOgran; +#else + simple_scalar1.iqKoefOgranIzad = iqKoefOgran; +#endif + //static _iq _iq_1 = _IQ(1.0); + + // static _iq mzz_int_level1_on_F=0; + + +// mzz = _IQsat(mzz,mzz_zad_int,0); + + + simple_scalar1.mzz_zad_in1 = mzz_zad; + simple_scalar1.Izad_from_master = Izad_from_master; + + iqKoefOgran = _IQsat(iqKoefOgran,CONST_IQ_1,0); + + /* y y */ + if ( (Frot==0) && (fzad==0) ) + { + mzzi = 0; + fzad_int = 0; + powerzad_int = 0; + bpsi_filter = 0; + pidFOutMax = pidFOutMin = 0; + n_iq_koef_im_on_tormog = CONST_IQ_1;//_IQ(1.0); + simple_scalar1.iq_decr_mzz_power_filter = CONST_IQ_1; + + } + + if (mzz_zad==0) + { + bpsi_filter = 0; + mzz=0; + I1_i=0; + mzzi=0; + mzz_zad_int = 0; + fzad_int = 0; + powerzad_int = 0; + + simple_scalar1.pidIm1.Up1 = 0; + simple_scalar1.pidIm1.Ui = 0; + + simple_scalar1.pidF.Up1 = 0; + simple_scalar1.pidF.Ui = 0; + + simple_scalar1.pidPower.Up1 = 0; + simple_scalar1.pidPower.Ui = 0; + + Uze_t1=0; + Uze_t2=0; + + dI1_prev = 0; + Uz_t1_prev = 0; + + dF_prev = 0; + mzz_prev = 0; + + + // fzad + fzad_add = _IQ(FZAD_ADD_MAX/NORMA_FROTOR); + // fzad + // fzad_dec = _IQ(FZAD_DEC/NORMA_FROTOR); +// +// + // mzz_max + // iq_mzz_max_for_fzad = _IQ(1000.0/NORMA_MZZ); + + + // . Uz_t_filter + // koef_Uz_t_filter = _IQ(0.001/0.5); //0.0333 + + + + // . mzz + // koef_bpsi = _IQ((0.6/NORMA_WROTOR)/(200.0/NORMA_MZZ)); + + flag_uz_t1=0; + + + // . . + // correct_err = _IQ(2.5/NORMA_WROTOR); + + // . . . + // iq_dF_min1 = _IQ(1.0/NORMA_WROTOR); + + // iq_dF_min2 = _IQ(1.5/NORMA_WROTOR); + + // . Km + // iq_spad_k = _IQ(0.993); //0.993 ~ 0.4 sek 5% + +// iq_spad_k = _IQ(0.9965); //0.993 ~ 0.4 sek 5% + + +// dF_PREDEL_LEVEL1 = _IQ(0.5/NORMA_WROTOR); +// dF_PREDEL_LEVEL2 = _IQ(1.5/NORMA_WROTOR); + + // mzz_int_level1_on_F = _IQ(1.0/NORMA_WROTOR); +// mzz_int_level2_on_F = _IQ(1.5/NORMA_WROTOR); + + + } + + + // + if (direction==0) + { + // + n_iq_koef_im_on_tormog = CONST_IQ_1;//_IQ(1.0); + } + else + if (direction==-1 && fzad <= 0) + { +// , + if (Frot_pid<-F_revers_level13) + n_iq_koef_im_on_tormog = kF_revers_level13; + else + if (Frot_pid<-F_revers_level12) + n_iq_koef_im_on_tormog = kF_revers_level12; + else + if (Frot_pid<-F_revers_level11) + n_iq_koef_im_on_tormog = kF_revers_level11; + else + if (Frot_pid<-F_revers_level10) + n_iq_koef_im_on_tormog = kF_revers_level10; + else + if (Frot_pid<-F_revers_level9) + n_iq_koef_im_on_tormog = kF_revers_level9; + else + if (Frot_pid<-F_revers_level8) + n_iq_koef_im_on_tormog = kF_revers_level8; + else + if (Frot_pid<-F_revers_level7) + n_iq_koef_im_on_tormog = kF_revers_level7; + else + if (Frot_pid<-F_revers_level6) + n_iq_koef_im_on_tormog = kF_revers_level6; + else + if (Frot_pid<-F_revers_level5) + n_iq_koef_im_on_tormog = kF_revers_level5; + else + if (Frot_pid<-F_revers_level4) + n_iq_koef_im_on_tormog = kF_revers_level4; + else + if (Frot_pid<-F_revers_level3) + n_iq_koef_im_on_tormog = kF_revers_level3; + else + if (Frot_pid<-F_revers_level2) + n_iq_koef_im_on_tormog = kF_revers_level2; + else + if (Frot_pid<-F_revers_level1) + n_iq_koef_im_on_tormog = kF_revers_level1; + if (Frot_pid<-F_revers_level0) + n_iq_koef_im_on_tormog = kF_revers_level0; + else + n_iq_koef_im_on_tormog = kF_revers_level00; + + } + else + if (direction==1 && fzad>=0) + { + // , + n_iq_koef_im_on_tormog = CONST_IQ_1;//_IQ(1.0); + } + else + { + // _iq_koef_im_on_tormog +// mzz_zad = _IQmpy(mzz_zad, _iq_koef_im_on_tormog); + + if (edrk.warnings.e9.bits.BREAK_TEMPER_ALARM == 1) + // , + n_iq_koef_im_on_tormog = _iq_koef_im_on_tormog_max_temper_break; + else + n_iq_koef_im_on_tormog = _iq_koef_im_on_tormog; + } + + t_iq_koef_im_on_tormog = zad_intensiv_q(_iq_koef_im_on_tormog_add, + _iq_koef_im_on_tormog_dec, + t_iq_koef_im_on_tormog, + n_iq_koef_im_on_tormog); + + + mzz_zad = _IQmpy(mzz_zad, t_iq_koef_im_on_tormog); + + simple_scalar1.mzz_zad_in2 = mzz_zad; + + /* */ + if (n_alg==1) + { + + mzz_zad_int = zad_intensiv_q(simple_scalar1.mzz_add_2, simple_scalar1.mzz_add_2, mzz_zad_int, mzz_zad); + +// if (Frot_pid>mzz_int_level1_on_F) +// mzz_zad_int = zad_intensiv_q(mzz_add_1, mzz_add_1, mzz_zad_int, mzz_zad); +// else +// mzz_zad_int = zad_intensiv_q(mzz_add_2, mzz_add_2, mzz_zad_int, mzz_zad); + + } + + + if (n_alg==2) + mzz_zad_int = zad_intensiv_q(simple_scalar1.mzz_add_2, simple_scalar1.mzz_add_2, mzz_zad_int, mzz_zad); + +// myq_temp = _IQdiv(mzz_zad, simple_scalar1.iq_mzz_max_for_fzad); +// myq_temp = _IQmpy( myq_temp, fzad_add_max); +// fzad_add = myq_temp; + + fzad_int = zad_intensiv_q(fzad_add, fzad_add, fzad_int, fzad ); + + + + + powerzad_int = zad_intensiv_q(simple_scalar1.powerzad_add, simple_scalar1.powerzad_add, powerzad_int, powerzad); + + if (n_alg==1) + { + /* y */ + if (mzz_zad_int>=0) + { + dF = fzad_int - Frot_pid;//*direction; + +////////// Power PI ////////////// + + + //if (_IQabs(simple_scalar1.pidF.Out)) + + k_ogr_n = (_IQabs(power_pid) - _IQabs(powerzad_int)); + // if (k_ogr_n<0) k_ogr_n = 0; + + k_ogr_n = CONST_IQ_1 - _IQdiv(k_ogr_n, _IQabs(powerzad_int)); + + simple_scalar1.k_ogr_n = _IQsat(k_ogr_n,CONST_IQ_1,-CONST_IQ_1); + + + // pidP OutMax + new_pidP_OutMax = _IQabs(simple_scalar1.pidF.Out)+add_mzz_outmax_pidp; + new_pidP_OutMax = _IQsat(new_pidP_OutMax, mzz_zad_int, add_mzz_outmax_pidp ); // 100 simple_scalar1.pidF.Out + + // +// new_pidP_OutMax = mzz_zad_int; + + simple_scalar1.pidPower.OutMax = new_pidP_OutMax; + simple_scalar1.pidPower.OutMin = 0; + + +// pidPower.Kp = _IQmpy( _IQdiv(iq_add_kp_dpower, _IQsat(mzz_zad,mzz_zad,MIN_MZZ_FOR_DPOWER)), pidPower_Kp); +// pidPower.Ki = _IQmpy( _IQdiv(iq_add_ki_dpower, _IQsat(mzz_zad,mzz_zad,MIN_MZZ_FOR_DPOWER)), pidPower_Ki); + +// simple_scalar1.pidPower.Ki = _IQmpy(simple_scalar1.pidPower.Ki, simple_scalar1.k_freq_for_pid); + + + simple_scalar1.pidPower.Ref = _IQabs(powerzad_int); // + + simple_scalar1.pidPower.Fdb = _IQabs(power_pid); + simple_scalar1.pidPower.calc(&simple_scalar1.pidPower); + + + // Saturate the integral output + + if (simple_scalar1.pidPower.Ui > simple_scalar1.pidPower.OutMax) + simple_scalar1.pidPower.Ui = simple_scalar1.pidPower.OutMax; + else if (simple_scalar1.pidPower.Ui < simple_scalar1.pidPower.OutMin) + simple_scalar1.pidPower.Ui = simple_scalar1.pidPower.OutMin; + + +////////////////////////////// +////////////////////////////// + + + // . + // pidF.OutMax=mzz_zad_int; + // + + pidFOutMax = zad_intensiv_q(simple_scalar1.mzz_add_3, simple_scalar1.mzz_add_1, pidFOutMax, simple_scalar1.pidPower.Out); + pidFOutMin = zad_intensiv_q(simple_scalar1.mzz_add_3, simple_scalar1.mzz_add_1, pidFOutMin, simple_scalar1.pidPower.Out); + + +// fzad + if (direction==-1 && fzad <= 0) + { + pidFOutMax = 0; + simple_scalar1.pidF.OutMax = 0;//simple_scalar1.pidPower.Out; + simple_scalar1.pidF.OutMin = -pidFOutMin;//-simple_scalar1.pidPower.Out; + + } + else + if (direction==1 && fzad>=0) + { + pidFOutMin = 0; + simple_scalar1.pidF.OutMax = pidFOutMax;//simple_scalar1.pidPower.Out; + simple_scalar1.pidF.OutMin = 0;//-simple_scalar1.pidPower.Out; + } + else + { + simple_scalar1.pidF.OutMax = pidFOutMax;//simple_scalar1.pidPower.Out; + simple_scalar1.pidF.OutMin = -pidFOutMin;//-simple_scalar1.pidPower.Out; + } + +/* +// pzad + if (direction==-1 && powerzad <= 0) + { + + + } + else + if (direction==1 && powerzad>=0) + { + + } + else + { + + } +*/ + +// pidF.OutMax = mzz_zad; + if (count_bs_work==2) + simple_scalar1.pidF.Kp = simple_scalar1.pidF_Kp;//_IQmpy( _IQdiv(simple_scalar1.iq_add_kp_df, _IQsat(mzz_zad,mzz_zad,simple_scalar1.min_mzz_for_df)), simple_scalar1.pidF_Kp); + else + simple_scalar1.pidF.Kp = _IQmpy2(simple_scalar1.pidF_Kp); + + simple_scalar1.pidF.Ki = simple_scalar1.pidF_Ki;//_IQmpy( _IQdiv(simple_scalar1.iq_add_ki_df, _IQsat(mzz_zad,mzz_zad,simple_scalar1.min_mzz_for_df)), simple_scalar1.pidF_Ki); + + simple_scalar1.pidF.Ki = _IQmpy(simple_scalar1.pidF.Ki,simple_scalar1.k_freq_for_pid); + +///////////////////////// + +// if (_IQabs(dF)iq_dF_min2) +// { +// m.m1.bit.w_rotor_ust = 0; +// } +////////////////////////////////// + + // dF + //fzad_int = + simple_scalar1.pidF.Ref = _IQmpy(fzad_int, iqKoefOgran); + + simple_scalar1.pidF.Fdb = Frot_pid;//*direction; + simple_scalar1.pidF.calc(&simple_scalar1.pidF); + + + // Saturate the integral output + + if (simple_scalar1.pidF.Ui > simple_scalar1.pidF.OutMax) + simple_scalar1.pidF.Ui = simple_scalar1.pidF.OutMax; + else if (simple_scalar1.pidF.Ui < simple_scalar1.pidF.OutMin) + simple_scalar1.pidF.Ui = simple_scalar1.pidF.OutMin; +///////////////////////////////////// + + mzz = _IQabs(simple_scalar1.pidF.Out); // !!! + +/////////////////////////////////////// + + + +// +// mzz = zad_intensiv_q(mzz_add_2, mzz_add_2, mzz, pidF.Out); + +// mzzi = zad_intensiv_q(mzz_add_2, mzz_add_2, mzzi, mzz); + + // mzz + mzz = _IQsat(mzz,mzz_zad_int,0); + + } + else + { + mzz = 0; + } + + } + + if (n_alg==2) + { + mzz = mzz_zad_int; + } + + + if (master == MODE_SLAVE) + { + mzz = Izad_from_master; + // mzz + mzz = _IQsat(mzz,mzz_zad_int,0); + } + + + *Izad_out = mzz; + /* y I_PREDEL_LEVEL1 + y */ + +/* + pred_Ip = (filter.I_3+filter.I_6)-I_PREDEL_LEVEL1; + + + if (pred_Ip<0) + Kpred_Ip=0.0; // + else + { + // + if (pred_Ip>=(I_PREDEL_LEVEL2-I_PREDEL_LEVEL1)) + Kpred_Ip=1; + else + Kpred_Ip = pred_Ip/(I_PREDEL_LEVEL2-I_PREDEL_LEVEL1); + + } + + // + Izad = mzz * (1-Kpred_Ip); + */ + + + + Izad = _IQmpy(mzz, simple_scalar1.iqKoefOgranIzad); + +// if ((n_alg==1) || (n_alg==2)) +// { +// +// Im1 = iqIm_1; +// Im2 = iqIm_2; +// +// if (n_wind_pump==0) // +// { +// +// halfIm1 = Im1 >> 1; +// halfIm2 = Im2 >> 1; +// +// if (Im1>halfIm2) //if (Im1>IQdiv(Im2,_IQ(2.0))) +// { +// Im_regul=Im1; +// simple_scalar1.UpravIm1=1; +// simple_scalar1.UpravIm2=0; +// } +// else +// { +// if (Im2>halfIm1) +// { +// Im_regul=Im2; +// simple_scalar1.UpravIm2=1; +// simple_scalar1.UpravIm1=0; +// } +// else +// { +// Im_regul=Im1; //Im1 +// simple_scalar1.UpravIm1=1;//1 +// simple_scalar1.UpravIm2=0;//0 +// } +// } +// } +// +// if (n_wind_pump==1) // 1 2- +// { +// Im_regul=Im2; +// simple_scalar1.UpravIm1=0; +// simple_scalar1.UpravIm2=1; +// } +// +// if (n_wind_pump==2) // 2 1- +// { +// Im_regul=Im1; +// simple_scalar1.UpravIm1=1; +// simple_scalar1.UpravIm2=0; +// } + + Im_regul = iqIm; + + simple_scalar1.Im_regul = Im_regul; + simple_scalar1.Izad = Izad; + + dI1 = (Izad - Im_regul ); + + simple_scalar1.pidIm1.Ki = simple_scalar1.pidIm_Ki; + simple_scalar1.pidIm1.Ki = _IQmpy(simple_scalar1.pidIm1.Ki,simple_scalar1.k_freq_for_pid); + + + simple_scalar1.pidIm1.Ref = _IQdiv(Izad,iqUin); + simple_scalar1.pidIm1.Fdb = _IQdiv(Im_regul,iqUin); + simple_scalar1.pidIm1.calc(&simple_scalar1.pidIm1); + + + Uz_t1 = simple_scalar1.pidIm1.Out; + + // Km + if (Uz_t1Uz_t1) Uze_t1 = Uze_ogr; + else + Uze_t1 = Uz_t1; + } + else + { + Uze_t1 = Uz_t1; + } + + Uze_t1 = _IQsat(Uze_t1,simple_scalar1.pidIm1.OutMax, simple_scalar1.pidIm1.OutMin); + +// } + + + /* */ + *Uz1 = Uze_t1; + *Uz2 = Uze_t1; + + + bpsi = bpsi_const + simple_scalar1.add_bpsi; + + // . ~ +// bpsi = _IQmpy(koef_bpsi,mzz); + + + bpsi = _IQsat(bpsi,simple_scalar1.max_bpsi, simple_scalar1.min_bpsi); + +#ifdef BAN_ROTOR_REVERS_DIRECT +// + if (analog.filter_direct_rotor==-1) + // , + *Fz = bpsi; + else + // , + *Fz = _IQmpy(Frot,IQ_POLUS) + bpsi; + +#else + + if (simple_scalar1.pidF.Out < 0) + { + bpsi_filter = exp_regul_iq(koefBpsi, bpsi_filter, -bpsi); + } + else + if (simple_scalar1.pidF.Out > 0) + { + bpsi_filter = exp_regul_iq(koefBpsi, bpsi_filter, bpsi); + } + else + bpsi_filter = exp_regul_iq(koefBpsi, bpsi_filter, 0); + + +// *Fz = _IQmpy(Frot*direction,simple_scalar1.poluses) + bpsi_filter; + *Fz = _IQmpy(Frot, simple_scalar1.poluses) + bpsi_filter; + + + simple_scalar1.bpsi_curent = bpsi_filter; + +#endif + + + simple_scalar1.mzz_zad_int = mzz_zad_int; + simple_scalar1.Uze_t1 = Uze_t1; + simple_scalar1.iqKoefOgran = iqKoefOgran; + simple_scalar1.Fz = *Fz; + simple_scalar1.direction = direction; + simple_scalar1.fzad_int = fzad_int; + + + +// if (n_alg==2) +// { +// +// *Fz = fzad_provorot; +// /* bpsi - , +// y y */ +// } + + +} + + + diff --git a/Inu/Src2/551/main/alg_simple_scalar.h b/Inu/Src2/551/main/alg_simple_scalar.h new file mode 100644 index 0000000..f05ca38 --- /dev/null +++ b/Inu/Src2/551/main/alg_simple_scalar.h @@ -0,0 +1,101 @@ +/* + * alg_simple_scalar.h + * + * Created on: 26 . 2020 . + * Author: Vladislav + */ + +#ifndef SRC_MAIN_ALG_SIMPLE_SCALAR_H_ +#define SRC_MAIN_ALG_SIMPLE_SCALAR_H_ + +#include "IQmathLib.h" +#include "pid_reg3.h" + +typedef struct { PIDREG3 pidIm1; + PIDREG3 pidF; + PIDREG3 pidPower; + + _iq mzz_add_1; + _iq mzz_add_2; + _iq poluses; + _iq fzad_add_max; + _iq fzad_dec; + + _iq powerzad_add; + _iq powerzad_dec; + _iq min_bpsi; + _iq koef_Uz_t_filter; + _iq iq_spad_k; + + _iq iq_mzz_max_for_fzad; + _iq k_freq_for_pid; + _iq iq_add_kp_df; + _iq iq_add_ki_df; + _iq min_mzz_for_df; + + _iq pidF_Kp; + _iq pidF_Ki; + int UpravIm1; + int UpravIm2; + _iq pidIm_Ki; + + _iq mzz_zad_in1; + _iq mzz_zad_in2; + + _iq mzz_zad_int; + _iq Im_regul; + _iq Izad; + _iq Izad_from_master; + _iq bpsi_curent; + _iq Uze_t1; + + _iq iqKoefOgran; + _iq Fz; + int direction; + _iq fzad_int; + + _iq add_bpsi; + _iq max_bpsi; + + _iq mzz_add_3; + + _iq k_ogr_n; + _iq iq_decr_mzz_power; + _iq iq_decr_mzz_power_filter; + int flag_decr_mzz_power; + + _iq iqKoefOgranIzad; + int disable_KoefOgranIzad; + _iq add_power_limit; + _iq sdvig_power_limit; + + int cmd_new_calc_p_limit; + + +} ALG_SIMPLE_SCALAR; + +#define ALG_SIMPLE_SCALAR_DEFAULT {PIDREG3_DEFAULTS,PIDREG3_DEFAULTS,PIDREG3_DEFAULTS,\ + 0,0,0,0,0,\ + 0,0,0,0,0,\ + 0,0,0,0,0,\ + 0,0,0,0,0,\ + 0,0,0,0,0,0,0, \ + 0,0, 0,0,0, 0,0, 0, 0, 0,0,0,0,0,0, 0,0 \ +} + + +extern ALG_SIMPLE_SCALAR simple_scalar1; + + + +void simple_scalar(int n_alg, int n_wind_pump, int direction, + _iq Frot_pid, _iq Frot,_iq fzad,_iq mzz_zad, _iq bpsi_const, + _iq iqKoefOgran, + _iq iqIm, _iq iqUin, _iq Iin, _iq powerzad, _iq power_pid, + _iq power_limit, int mode_oborots_power, + _iq Izad_from_master, int master, int count_bs_work, + _iq *Fz, _iq *Uz1, _iq *Uz2, _iq *Izad); + +void init_simple_scalar(void); + +#endif /* SRC_MAIN_ALG_SIMPLE_SCALAR_H_ */ diff --git a/Inu/Src2/551/main/alg_uf_const.c b/Inu/Src2/551/main/alg_uf_const.c new file mode 100644 index 0000000..3e5b8fa --- /dev/null +++ b/Inu/Src2/551/main/alg_uf_const.c @@ -0,0 +1,80 @@ +/* + * alg_uf_const.c + * + * Created on: 26 . 2020 . + * Author: Yura + */ +#include +#include +#include +#include +#include + +#include "mathlib.h" + + + + +#define T_NARAST 15 // . + +//VHZPROF vhz1 = VHZPROF_DEFAULTS; + + +ALG_UF_CONST uf_const1 = ALG_UF_CONST_DEFAULT; + +void init_uf_const(void) +{ + uf_const1.freq = 0; + uf_const1.km = 0; + + uf_const1.zad_plus_km = _IQ(1.0/(FREQ_PWM*T_NARAST)); + + + uf_const1.rmp_freq.RampLowLimit = _IQ(-4); //0 + uf_const1.rmp_freq.RampHighLimit = _IQ(4); + + uf_const1.rmp_freq.RampPlus = _IQ(0.0002); + + uf_const1.rmp_freq.RampMinus = _IQ(-0.0002); + uf_const1.rmp_freq.DesiredInput = 0; + uf_const1.rmp_freq.Out = 0; + + uf_const1.max_km = _IQ(K_STATOR_MAX); + +} + + +void uf_const(_iq *Fz, _iq *Uz1, _iq *Uz2) +{ + + +// vhz1.HighFreq = _IQ(f.fmax_uf/F_STATOR_MAX); +///////////// + + uf_const1.km = edrk.zadanie.iq_kzad_rmp; +// uf_const1.km = zad_intensiv_q(uf_const1.zad_plus_km, uf_const1.zad_plus_km, uf_const1.km, edrk.zadanie.iq_kzad); +// uf_const1.km = _IQsat(uf_const1.km,uf_const1.max_km,0); + *Uz1 = uf_const1.km; + *Uz2 = uf_const1.km; + + +///////////////// + uf_const1.freq = edrk.zadanie.iq_fzad_rmp; + +// uf_const1.rmp_freq.DesiredInput = uf_const1.freq; +// uf_const1.rmp_freq.calc(&uf_const1.rmp_freq); + *Fz = uf_const1.freq; + +/* + vhz1.Freq = Fzad; + vhz1.calc(&vhz1); + + + + *Fz = rmp_freq.Out; + */ + + +} + + diff --git a/Inu/Src2/551/main/alg_uf_const.h b/Inu/Src2/551/main/alg_uf_const.h new file mode 100644 index 0000000..50276f0 --- /dev/null +++ b/Inu/Src2/551/main/alg_uf_const.h @@ -0,0 +1,34 @@ +/* + * alg_uf_const.h + * + * Created on: 26 . 2020 . + * Author: Yura + */ + +#ifndef SRC_MAIN_ALG_UF_CONST_H_ +#define SRC_MAIN_ALG_UF_CONST_H_ + + +#include "IQmathLib.h" +#include "rmp_cntl_v1.h" + + +typedef struct { + RMP_V1 rmp_freq; + _iq freq; + _iq km; + _iq zad_plus_km; + _iq max_km; +} ALG_UF_CONST; + +extern ALG_UF_CONST uf_const1; + +#define ALG_UF_CONST_DEFAULT {RMP_V1_DEFAULTS, 0, 0, 0, 0 } + + + + +void init_uf_const(void); +void uf_const(_iq *Fz, _iq *Uz1, _iq *Uz2); + +#endif /* SRC_MAIN_ALG_UF_CONST_H_ */ diff --git a/Inu/Src2/551/main/another_bs.c b/Inu/Src2/551/main/another_bs.c new file mode 100644 index 0000000..542df74 --- /dev/null +++ b/Inu/Src2/551/main/another_bs.c @@ -0,0 +1,458 @@ +/* + * another_bs.c + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#include + +#include +#include +#include +#include +#include +#include +#include "IQmathLib.h" +#include "mathlib.h" +#include +#include "adc_tools.h" +#include "CAN_project.h" +#include "CAN_Setup.h" +#include "global_time.h" +#include "v_rotor.h" +#include "ukss_tools.h" +#include "another_bs.h" +#include "control_station_project.h" +#include "control_station.h" +#include "can_bs2bs.h" +#include "sync_tools.h" +#include "vector_control.h" +#include "master_slave.h" +#include "digital_filters.h" + + +////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////// +void read_data_from_bs(void) +{ + int g; + + if (control_station.alive_control_station[CONTROL_STATION_ANOTHER_BS]) + { + g = Unites[ANOTHER_BSU1_CAN_DEVICE][5]; + edrk.int_koef_ogran_power_another_bs = g; + edrk.iq_koef_ogran_power_another_bs = ((float)edrk.int_koef_ogran_power_another_bs); + + g = Unites[ANOTHER_BSU1_CAN_DEVICE][6]; + edrk.power_kw_another_bs = g; + edrk.iq_power_kw_another_bs = _IQ(((float)edrk.power_kw_another_bs * 1000.0)/NORMA_ACP/NORMA_ACP); + + g = Unites[ANOTHER_BSU1_CAN_DEVICE][7]; + edrk.active_post_upravl_another_bs = g; + + g = Unites[ANOTHER_BSU1_CAN_DEVICE][9]; + edrk.Ready1_another_bs = g; + + g = Unites[ANOTHER_BSU1_CAN_DEVICE][10]; + edrk.Ready2_another_bs = g; + + g = Unites[ANOTHER_BSU1_CAN_DEVICE][11]; + edrk.MasterSlave_another_bs = g; + + g = Unites[ANOTHER_BSU1_CAN_DEVICE][3] & 0x1; + edrk.ump_cmd_another_bs = g; + + g = (Unites[ANOTHER_BSU1_CAN_DEVICE][3] & 0x2) >> 1; + edrk.qtv_cmd_another_bs = g; + + g = Unites[ANOTHER_BSU1_CAN_DEVICE][13]; + edrk.errors_another_bs_from_can = g; + } + else + { + edrk.errors_another_bs_from_can = 0; + } + + +} + + +////////////////////////////////////////////////////////// +unsigned int read_cmd_sbor_from_bs(void) +{ + unsigned int g; + g = Unites[ANOTHER_BSU1_CAN_DEVICE][4]; + return g; + + +} + + + + +void UpdateTableSecondBS(void) +{ + int cmd; + int i,k; + + static unsigned int counter_sum_errors = 0; + + Unites2SecondBS[0]++; + + Unites2SecondBS[1] = global_time.miliseconds; + Unites2SecondBS[2] = edrk.flag_second_PCH; + Unites2SecondBS[3] = (edrk.to_shema.bits.QTV_ON_OFF << 1) | (edrk.to_shema.bits.UMP_ON_OFF); + Unites2SecondBS[4] = edrk.SumSbor; + Unites2SecondBS[5] = edrk.int_koef_ogran_power; + Unites2SecondBS[6] = (int)edrk.power_kw; + Unites2SecondBS[7] = (int)edrk.active_post_upravl; + Unites2SecondBS[8] = (int)edrk.power_kw; + Unites2SecondBS[9] = edrk.Status_Ready.bits.ready1; + Unites2SecondBS[10] = edrk.Status_Ready.bits.ready_final; + Unites2SecondBS[11] = edrk.MasterSlave; + + Unites2SecondBS[12] = _IQtoF(vect_control.iqId_min) * NORMA_ACP; + + Unites2SecondBS[13] = pause_detect_error(&counter_sum_errors, 10, edrk.summ_errors); + + + for (i=0;i +#include +#include +#include +#include + +#include "IQmathLib.h" +#include "pid_reg3.h" +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File + + +#pragma DATA_SECTION(break_result_1,".fast_vars"); +_iq break_result_1 = 0; + +#pragma DATA_SECTION(break_result_2,".fast_vars"); +_iq break_result_2 = 0; + +#pragma DATA_SECTION(break_result_3,".fast_vars"); +_iq break_result_3 = 0; + +#pragma DATA_SECTION(break_result_4,".fast_vars"); +_iq break_result_4 = 0; + +#pragma DATA_SECTION(koef_Krecup,".fast_vars"); +_iq koef_Krecup = 0; + +#pragma DATA_SECTION(koef_Min_recup,".fast_vars"); +_iq koef_Min_recup = 0; + +BREAK_REGUL break_reg = BREAK_REGUL_DEFAULTS; + +_iq calc_recup(_iq voltage, _iq recup_level, _iq max_recup_level); +//#pragma DATA_SECTION(pidF,".fast_vars"); +//PIDREG3 pidF=PIDREG3_DEFAULTS; + +void break_resistor_managment_init(unsigned int freq_pwm) +{ + volatile float percent;//, percent2; + _iq iq_percent1 = 0, iq_percent2 = 0;// iq_percent3 = 0, iq_percent4 = 0; + + break_reg.pwm_tics = (FREQ_INTERNAL_GENERATOR_XILINX_TMS / freq_pwm ); + break_reg.pwm_minimal_tics = (float)DEF_PERIOD_MIN_MKS*1000.0*FREQ_INTERNAL_GENERATOR_XILINX_TMS/1000000000.0; + break_reg.pwm_max_tics = break_reg.pwm_tics - break_reg.pwm_minimal_tics; + + + // - . IQ15. + percent = (break_reg.pwm_max_tics * RECUP_PERCENT_MIN/100.0) * 32768.0;// _IQ15 + iq_percent1 = percent; + + // - . IQ15. + percent = (break_reg.pwm_max_tics * RECUP_PERCENT_MAX/100.0) * 32768.0; + iq_percent2 = percent; + + // - + koef_Krecup = _IQdiv((iq_percent1 - iq_percent2),(IQ_RECUP_LEVEL_MIN - IQ_RECUP_LEVEL_MAX)); + koef_Min_recup = iq_percent1; // +} + + +//int break_resistor_managment_calc(int flag_on_off) +#pragma CODE_SECTION(break_resistor_managment_calc,".fast_run"); +void break_resistor_managment_calc() +{ + static unsigned int break_counter = 0;//MAX_BREAK_IMPULSE + 1; + + if(edrk.Discharge && edrk.from_shema_filter.bits.QTV_ON_OFF==0 + && edrk.from_shema_filter.bits.UMP_ON_OFF==0)// && edrk.to_shema.bits.QTV_ON == 0) + { + if (break_counter < MAX_BREAK_IMPULSE) + { + break_counter++; + + + if ((filter.iqU_1_fast > BREAK_INSENSITIVE_LEVEL_MIN) + || edrk.ManualDischarge || edrk.NoDetectUZeroDischarge) + { + if (edrk.Obmotka1 == 0) + break_result_1 = 300; + else + break_result_1 = 0; + } + else + { + break_result_1 = 0; + } + + if ((filter.iqU_2_fast > BREAK_INSENSITIVE_LEVEL_MIN) + || edrk.ManualDischarge || edrk.NoDetectUZeroDischarge ) + { + if (edrk.Obmotka2 == 0) + break_result_2 = 300; + else + break_result_2 = 0; + } + else + { + break_result_2 = 0; + } + +// if (filter.iqU_3_fast < BREAK_INSENSITIVE_LEVEL_MIN) +// { +// break_result_3 = 0; +// } +// else +// { +// break_result_3 = 300; +//// break_result_3 = calc_stop_run_recup(filter.iqU_3_fast); +// } +// +// if (filter.iqU_4_fast < BREAK_INSENSITIVE_LEVEL_MIN) +// { +// break_result_4 = 0; +// } +// else +// { +// break_result_4 = 300; +//// break_result_4 = calc_stop_run_recup(filter.iqU_4_fast); +// } + + if((!break_result_1 && !break_result_2 && !break_result_3 && !break_result_4) + || (break_counter >= (MAX_BREAK_IMPULSE - 1))) + { + edrk.Discharge = 0; + break_counter = 0; + } + } + else + { + break_result_1 = 0; + break_result_2 = 0; + break_result_3 = 0; + break_result_4 = 0; + break_counter = 0; + edrk.Discharge = 0; + } + } + +} + +#pragma CODE_SECTION(calc_recup,".fast_run"); +_iq calc_recup(_iq voltage, _iq recup_level, _iq max_recup_level) +{ + if (voltage <= recup_level) + { + return 0; + } + else + { + voltage = _IQsat(voltage,max_recup_level,recup_level); + voltage = _IQmpy(koef_Krecup,voltage - recup_level) + koef_Min_recup; + return voltage >> 15; + } +} + +#pragma CODE_SECTION(break_resistor_recup_calc,".fast_run"); +void break_resistor_recup_calc(_iq Uzpt_nominal) +{ + _iq Uzpt_start_recup = Uzpt_nominal + IQ_DELTA_U_START_RECUP; + _iq Uzpt_max_open_break_keys = Uzpt_nominal + IQ_DELTA_U_MAX_OPEN_BREAK_KEYS; + + if (/*edrk.Go &&*/ (edrk.SborFinishOk || edrk.Status_Ready.bits.ImitationReady2) ) + { + break_result_1 = calc_recup(filter.iqU_1_fast, Uzpt_start_recup, Uzpt_max_open_break_keys); + break_result_2 = calc_recup(filter.iqU_2_fast, Uzpt_start_recup, Uzpt_max_open_break_keys); + } +} + +#pragma CODE_SECTION(break_resistor_managment_update,".fast_run"); +void break_resistor_managment_update() +{ + if (break_result_1 < break_reg.pwm_minimal_tics) + break_result_1 = 0; + + if (break_result_2 < break_reg.pwm_minimal_tics) + break_result_2 = 0; + +// if (break_result_3 < break_reg.pwm_minimal_tics) +// break_result_3 = 0; +// +// if (break_result_4 < break_reg.pwm_minimal_tics) +// break_result_4 = 0; + + if (break_result_1 > break_reg.pwm_max_tics) + break_result_1 = break_reg.pwm_max_tics; + + if (break_result_2 > break_reg.pwm_max_tics) + break_result_2 = break_reg.pwm_max_tics; + +// if (break_result_3 > break_reg.pwm_max_tics) +// break_result_3 = break_reg.pwm_max_tics; +// +// if (break_result_4 > break_reg.pwm_max_tics) +// break_result_4 = break_reg.pwm_max_tics; +} + +//#pragma CODE_SECTION(break_resistor_set_closed,".fast_run"); +void break_resistor_set_closed() +{ + break_result_1 = 0; + break_result_2 = 0; + break_result_3 = 0; + break_result_4 = 0; +} diff --git a/Inu/Src2/551/main/break_regul.h b/Inu/Src2/551/main/break_regul.h new file mode 100644 index 0000000..1e79cdd --- /dev/null +++ b/Inu/Src2/551/main/break_regul.h @@ -0,0 +1,70 @@ +#ifndef _BREAK_REGUL_H +#define _BREAK_REGUL_H + +#ifdef __cplusplus + extern "C" { +#endif + +typedef struct { + unsigned int pwm_tics; + unsigned int pwm_minimal_tics; + unsigned int pwm_max_tics; +} BREAK_REGUL; + +#define BREAK_REGUL_DEFAULTS {0,0,0} + + +#define BREAK_INSENSITIVE_LEVEL_MIN 279620 //50V +#define BREAK_INSENSITIVE_LEVEL_MAX 4194304//500V//5872025//700 V//2516582//300 V//4194304//500 V//2516582 // 838860 //100 V +#define PERCENT_BREAK_MAX 13421772//80 percent +#define PERCENT_BREAK_MIN 838860//5 percent +#define MAX_RECUP_LEVEL 5872025 //700 V +#define K_RECUP_LEVEL 56 //5.6 /// 838860 / 4697620 //700 V +#define MAX_BREAK_IMPULSE 9000 + +#define RECUP_PERCENT_MIN 10.0 +#define RECUP_PERCENT_MAX 90.0 + +//#define IQ_RECUP_LEVEL_MIN_ACCUM 16777216 //3000V +//#define IQ_RECUP_LEVEL_MAX_ACCUM 17895697 //3200V + +#define IQ_RECUP_LEVEL_MIN 15658734L //2800V //15099494L //2700V //9507089L //1700V //8947848L //1600V // +#define IQ_RECUP_LEVEL_MAX 16777216L //3000V //16777216L //16217975L //2900V //11184810L //2000V //17895697 //3200V 10066329 //1800V // + +#define IQ_DELTA_U_START_RECUP 559240 //100V //279620LL //50V +#define IQ_DELTA_U_MAX_OPEN_BREAK_KEYS 1677721LL//300 V + + +#define IQ_MIN_VOLTAGE_STOP_RUN 279620L //50V +#define IQ_MAX_VOLTAGE_STOP_RUN 16777216L //3000V + +#define BRK_STOP_RUN_PERCENT_MIN 5 +#define BRK_STOP_RUN_PERCENT_MAX 50 + +//int break_resistor_managment_calc(int flag_on_off); +void break_resistor_managment_calc(void); +void break_resistor_managment_init(unsigned int freq_pwm); +void break_resistor_managment_update(void); +void break_resistor_recup_calc(_iq Uzpt_nominal); +void break_resistor_set_closed(void); +_iq calc_stop_run_recup(_iq voltage); + + +//extern PIDREG3 break_struct_1; +//extern PIDREG3 break_struct_2; + + + + +extern _iq break_result_1; +extern _iq break_result_2; +extern _iq break_result_3; +extern _iq break_result_4; + +extern _iq kp_break; + +#ifdef __cplusplus + } +#endif + +#endif /* _BREAK_REGUL_H */ diff --git a/Inu/Src2/551/main/calc_rms_vals.c b/Inu/Src2/551/main/calc_rms_vals.c new file mode 100644 index 0000000..7363ce2 --- /dev/null +++ b/Inu/Src2/551/main/calc_rms_vals.c @@ -0,0 +1,265 @@ +/* + * calc_rms_vals.c + * + * Created on: 14 . 2020 . + * Author: star + */ +#include +#include +#include +#include +#include + +#include "IQmathLib.h" +#include "mathlib.h" + +#define NUM_OF_CHANNELS 6 + +//#define USE_CALC_U_IN_RMS 1 +//#define USE_CALC_I_OUT_RMS 1 + + +#pragma DATA_SECTION(in_U_rms_calc_buffer,".slow_vars") +RMS_BUFFER in_U_rms_calc_buffer[NUM_OF_CHANNELS] = {RMS_BUFFER_DEFAULTS, RMS_BUFFER_DEFAULTS, \ + RMS_BUFFER_DEFAULTS, RMS_BUFFER_DEFAULTS, \ + RMS_BUFFER_DEFAULTS, RMS_BUFFER_DEFAULTS}; + +#pragma DATA_SECTION(out_I_rms_calc_buffer,".slow_vars") +RMS_BUFFER_WITH_THINNING out_I_rms_calc_buffer[6] = {RMS_BUFFER_WITH_THINNING_DEFAULTS, RMS_BUFFER_WITH_THINNING_DEFAULTS, \ + RMS_BUFFER_WITH_THINNING_DEFAULTS, RMS_BUFFER_WITH_THINNING_DEFAULTS, \ + RMS_BUFFER_WITH_THINNING_DEFAULTS, RMS_BUFFER_WITH_THINNING_DEFAULTS}; + +/////////////////////////////////////////////////// +void init_Uin_rms(void) +{ + int k,l; + // + for (k=0;kvalues[b->position++] = val; + if (b->position >= b->array_size) { b->position = 0;} +} + +#define add_to_buff_def(b, val) { (b)->values[(b)->position++] = (val); if ((b)->position >= (b)->array_size) { (b)->position = 0;}} + +static void calc_Uin_rms(void); +static void calc_Iout_rms(void); + +#define CONST_PI 52707178 + +//#pragma CODE_SECTION(fill_rms_array_IQ15,".fast_run1"); +void fill_rms_array_IQ15(RMS_BUFFER_WITH_THINNING *v) { + static _iq norma_f_rot = NORMA_FROTOR; + int period_by_teta = 0; +// int freq = _IQtoF(v->signal_freq) * NORMA_FROTOR; +// int freq = _IQtoF(v->signal_freq * norma_f_rot); //Max IQ24 = 127. + int freq = (v->signal_freq * norma_f_rot) / (1LL << GLOBAL_Q); // 10 , + int count_miss_writing = 100; + if (freq != 0) { + freq *= v->elements_in_period; //"" + count_miss_writing = (int)(v->freq_pwm / freq); + if (count_miss_writing > 100) {count_miss_writing = 100;} + } + + if (v->use_teta) { + v->internal.teta_period_counter += 1; + if ((v->teta < CONST_PI && v->internal.teta_prev > CONST_PI) || + (v->teta > CONST_PI && v->internal.teta_prev < CONST_PI)) { + v->internal.zero_teta_period = v->internal.teta_period_counter; + v->internal.teta_period_counter = 0; + } + v->internal.teta_prev = v->teta; + period_by_teta = v->internal.zero_teta_period / v->elements_in_period; + if (period_by_teta != 0) { + count_miss_writing = (count_miss_writing + period_by_teta) / 2; + } + } + + + if (v->internal.miss_write_counter++ < count_miss_writing) { + return; + } + + v->internal.miss_write_counter = 0; + v->values[v->position++] = _IQtoIQ15(v->val); + if (v->position >= v->array_size) { + v->position = 0; + } +} + +void fill_RMS_buff_interrupt(_iq teta_ch1, _iq teta_ch2) { +#ifdef USE_CALC_U_IN_RMS +// add_to_buff(&in_U_rms_calc_buffer[0], analog.iqUin_A1B1); +// add_to_buff(&in_U_rms_calc_buffer[1], analog.iqUin_B1C1); +// add_to_buff(&in_U_rms_calc_buffer[2], analog.iqUin_C1A1); +// add_to_buff(&in_U_rms_calc_buffer[3], analog.iqUin_A2B2); +// add_to_buff(&in_U_rms_calc_buffer[4], analog.iqUin_B2C2); +// add_to_buff(&in_U_rms_calc_buffer[5], analog.iqUin_C2A2); +// + add_to_buff_def(&in_U_rms_calc_buffer[0], analog.iqUin_A1B1); //define 10 + add_to_buff_def(&in_U_rms_calc_buffer[1], analog.iqUin_B1C1); + add_to_buff_def(&in_U_rms_calc_buffer[2], analog.iqUin_C1A1); + add_to_buff_def(&in_U_rms_calc_buffer[3], analog.iqUin_A2B2); + add_to_buff_def(&in_U_rms_calc_buffer[4], analog.iqUin_B2C2); + add_to_buff_def(&in_U_rms_calc_buffer[5], analog.iqUin_C2A2); +#endif //USE_CALC_U_IN_RMS +#ifdef USE_CALC_I_OUT_RMS + out_I_rms_calc_buffer[0].val = analog.iqIu_1; + out_I_rms_calc_buffer[0].teta = teta_ch1; + out_I_rms_calc_buffer[0].freq_pwm = FREQ_PWM * 2; + out_I_rms_calc_buffer[0].signal_freq = edrk.f_stator; + out_I_rms_calc_buffer[0].add_value(&out_I_rms_calc_buffer[0]); + out_I_rms_calc_buffer[1].val = analog.iqIv_1; + out_I_rms_calc_buffer[1].teta = teta_ch1; + out_I_rms_calc_buffer[1].freq_pwm = FREQ_PWM * 2; + out_I_rms_calc_buffer[1].signal_freq = edrk.f_stator; + out_I_rms_calc_buffer[1].add_value(&out_I_rms_calc_buffer[1]); + out_I_rms_calc_buffer[2].val = analog.iqIw_1; + out_I_rms_calc_buffer[2].teta = teta_ch1; + out_I_rms_calc_buffer[2].freq_pwm = FREQ_PWM * 2; + out_I_rms_calc_buffer[2].signal_freq = edrk.f_stator; + out_I_rms_calc_buffer[2].add_value(&out_I_rms_calc_buffer[2]); + + out_I_rms_calc_buffer[3].val = analog.iqIu_1; + out_I_rms_calc_buffer[3].teta = teta_ch2; + out_I_rms_calc_buffer[3].freq_pwm = FREQ_PWM * 2; + out_I_rms_calc_buffer[3].signal_freq = edrk.f_stator; + out_I_rms_calc_buffer[3].add_value(&out_I_rms_calc_buffer[3]); + out_I_rms_calc_buffer[4].val = analog.iqIu_1; + out_I_rms_calc_buffer[4].teta = teta_ch2; + out_I_rms_calc_buffer[4].freq_pwm = FREQ_PWM * 2; + out_I_rms_calc_buffer[4].signal_freq = edrk.f_stator; + out_I_rms_calc_buffer[4].add_value(&out_I_rms_calc_buffer[4]); + out_I_rms_calc_buffer[5].val = analog.iqIu_1; + out_I_rms_calc_buffer[5].teta = teta_ch2; + out_I_rms_calc_buffer[5].freq_pwm = FREQ_PWM * 2; + out_I_rms_calc_buffer[5].signal_freq = edrk.f_stator; + out_I_rms_calc_buffer[5].add_value(&out_I_rms_calc_buffer[5]); +#endif //USE_CALC_I_OUT_RMS +} + + +void calc_Uin_rms(void) { + + RMS_CALC_ARRAY rc = RMS_CALC_DEFAULTS; + + rc.size_array = in_U_rms_calc_buffer[0].array_size; + rc.data_array = in_U_rms_calc_buffer[0].values; + analog.iqUin_A1B1_rms = rc.calc(&rc); + rc.size_array = in_U_rms_calc_buffer[1].array_size; + rc.data_array = in_U_rms_calc_buffer[1].values; + analog.iqUin_B1C1_rms = rc.calc(&rc); + rc.size_array = in_U_rms_calc_buffer[2].array_size; + rc.data_array = in_U_rms_calc_buffer[2].values; + analog.iqUin_C1A1_rms = rc.calc(&rc); + + rc.size_array = in_U_rms_calc_buffer[3].array_size; + rc.data_array = in_U_rms_calc_buffer[3].values; + analog.iqUin_A2B2_rms = rc.calc(&rc); + rc.size_array = in_U_rms_calc_buffer[4].array_size; + rc.data_array = in_U_rms_calc_buffer[4].values; + analog.iqUin_B2C2_rms = rc.calc(&rc); + rc.size_array = in_U_rms_calc_buffer[5].array_size; + rc.data_array = in_U_rms_calc_buffer[5].values; + analog.iqUin_C2A2_rms = rc.calc(&rc); + +} + + +void calc_Iout_rms() { + int i = 0; + _iq results[NUM_OF_CHANNELS]; + RMS_CALC_ARRAY_THINNING rc_Iout = RMS_CALC_THINNING_DEFAULTS; + + //Calc rms + for (i = 0; i < NUM_OF_CHANNELS; i++) { + rc_Iout.data_array = out_I_rms_calc_buffer[i].values; + rc_Iout.last_elem_position = out_I_rms_calc_buffer[i].position; + rc_Iout.size_array = out_I_rms_calc_buffer[i].array_size; + rc_Iout.signal_period = out_I_rms_calc_buffer[i].elements_in_period; + results[i] = rc_Iout.calc(&rc_Iout); + } + analog.iqIu_1_rms = results[0]; + analog.iqIv_1_rms = results[1]; + analog.iqIw_1_rms = results[2]; + analog.iqIu_2_rms = results[3]; + analog.iqIv_2_rms = results[4]; + analog.iqIw_2_rms = results[5]; +} + +void calc_RMS_values_main() { +#ifdef USE_CALC_U_IN_RMS + calc_Uin_rms(); +#endif +// i_led2_off(); +// i_led2_on(); +#ifdef USE_CALC_I_OUT_RMS + calc_Iout_rms(); +#endif +} + +//float signal_amplitude = 141; +//_iq data_arr[RMS_BUFFER_SIZE]; +//_iq16 data_arr_IQ16[RMS_BUFFER_SIZE]; +//_iq position = 0; +//_iq result_simple = 0; +//_iq result_simple_t = 0; +// +//RMS_BUFFER_WITH_THINNING buffer_var_freq = RMS_BUFFER_WITH_THINNING_DEFAULTS; +//int freq_mian_signal = 1; +//int counter_wait_change_freq = 0; +//#define WAIT_CHANGE_FREQ_TICS 2000 +/* +void test_calc_rms (_iq teta) { + _iq amplitude = _IQ (signal_amplitude / NORMA_ACP); + _iq current_val = 0; + _iq add_var_freq = 0; + static _iq add_50hz = _IQ(6.28 * 50.0 / FREQ_PWM / 2.0); + static _iq teta_50hz = 0, teta_Low = 0; + RMS_CALC_ARRAY rc = RMS_CALC_DEFAULTS; + + RMS_CALC_ARRAY_THINNING rct = RMS_CALC_THINNING_DEFAULTS; + + current_val = _IQmpy(amplitude, _IQcos(teta_50hz)); + data_arr[position] = current_val; + data_arr_IQ16[position] = _IQtoIQ16(current_val); + position += 1; + if (position >= RMS_BUFFER_SIZE) position = 0; + teta_50hz += add_50hz; + rc.data_array = data_arr; + rc.size_array = RMS_BUFFER_SIZE; + result_simple = rc.calc(&rc); + + if (counter_wait_change_freq >= WAIT_CHANGE_FREQ_TICS) { + if (freq_mian_signal < 20) { freq_mian_signal +=1;} + counter_wait_change_freq = 0; + } else { + counter_wait_change_freq += 1; + } + + add_var_freq = _IQ(6.28 * freq_mian_signal / FREQ_PWM / 2.0); + teta_Low += add_var_freq; + current_val = _IQmpy(amplitude, _IQcos(teta_Low)); + buffer_var_freq.val = current_val; + buffer_var_freq.signal_freq = _IQ((float)freq_mian_signal / NORMA_FROTOR); + buffer_var_freq.teta = teta_Low; + buffer_var_freq.add_value(&buffer_var_freq); + + + + rct.data_array = buffer_var_freq.values; + rct.size_array = buffer_var_freq.array_size; + rct.last_elem_position = buffer_var_freq.position; + rct.signal_period = buffer_var_freq.array_size; + result_simple_t = rct.calc(&rct); +} +*/ diff --git a/Inu/Src2/551/main/calc_rms_vals.h b/Inu/Src2/551/main/calc_rms_vals.h new file mode 100644 index 0000000..a01b3da --- /dev/null +++ b/Inu/Src2/551/main/calc_rms_vals.h @@ -0,0 +1,66 @@ +/* + * calc_rms_vals.h + * + * Created on: 14 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_CALC_RMS_VALS_H_ +#define SRC_MAIN_CALC_RMS_VALS_H_ + + +#include + +#include "IQmathLib.h" + +#define RMS_BUFFER_SIZE (FREQ_PWM * 2 / 50) +//#define RMS_BUFFER_SIZE 18 //For FREQ_PWM 450 and signal frequency 50 Hz + + +typedef struct { + _iq values[RMS_BUFFER_SIZE]; + int array_size; + int position; +} RMS_BUFFER; + +#define RMS_BUFFER_DEFAULTS {{0}, RMS_BUFFER_SIZE, 0} + +#define RMS_THINNING_BUFFER_SIZE 40 // 30 +#define RMS_THINNING_PERIOD (RMS_THINNING_BUFFER_SIZE * 3 / 4) +typedef struct { + _iq val; //in + _iq16 values[RMS_THINNING_BUFFER_SIZE]; + int array_size; + int position; + int elements_in_period; // 1 + + int freq_pwm; //in + _iq signal_freq; //in + int use_teta; // teta + _iq teta; //in + + struct { + int miss_write_counter; + int teta_period_counter; + _iq teta_prev; + int zero_teta_period; +// int zero_teta_counter_prev; + } internal; + void (*add_value)(); +} RMS_BUFFER_WITH_THINNING; + + +#define RMS_BUFFER_WITH_THINNING_DEFAULTS {0, {0}, RMS_THINNING_BUFFER_SIZE,0, \ + RMS_THINNING_PERIOD,\ + (FREQ_PWM * 2),0,0,0, {0,0,0,0}, \ + fill_rms_array_IQ15} + +void fill_rms_array_IQ15(RMS_BUFFER_WITH_THINNING *v); +void fill_RMS_buff_interrupt(_iq teta_ch1, _iq teta_ch2); +void calc_RMS_values_main(); +void init_Uin_rms(void); + + +void test_calc_rms (_iq teta); + +#endif /* SRC_MAIN_CALC_RMS_VALS_H_ */ diff --git a/Inu/Src2/551/main/calc_tempers.c b/Inu/Src2/551/main/calc_tempers.c new file mode 100644 index 0000000..a5988cc --- /dev/null +++ b/Inu/Src2/551/main/calc_tempers.c @@ -0,0 +1,284 @@ +/* + * calc_tempers.c + * + * Created on: 4 . 2020 . + * Author: star + */ + +#include +#include +#include +#include +#include + +#include "CAN_Setup.h" +#include "IQmathLib.h" + +int calc_max_temper_acdrive_bear(void); +int calc_max_temper_acdrive_winding(void); +int calc_max_temper_edrk_u(void); +int calc_max_temper_edrk_water(void); +int calc_max_temper_edrk_air(void); +int calc_min_temper_edrk_air(void); + + + + +//////////////////////////////////////////////////////////////////// +int calc_max_temper_acdrive_bear(void) +{ + int i, max_t=0; + + for (i=0;imax_t) + max_t = edrk.temper_acdrive.winding.filter_real_int_temper[i]; + + return max_t; + +} +//////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////// +int calc_max_temper_acdrive_winding(void) +{ + int i, max_t=0; + + for (i=0;imax_t) + max_t = edrk.temper_acdrive.winding.filter_real_int_temper[i]; + + return max_t; + +} +//////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////// +int calc_max_temper_edrk_u(void) +{ + int i, max_t=0; + + for (i=0;i<7;i++) + if (edrk.temper_edrk.real_int_temper_u[i]>max_t) + max_t = edrk.temper_edrk.real_int_temper_u[i]; + + return max_t; + +} +//////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +int calc_max_temper_edrk_water(void) +{ + int i, max_t=0; + + for (i=0;i<2;i++) + if (edrk.temper_edrk.real_int_temper_water[i]>max_t) + max_t = edrk.temper_edrk.real_int_temper_water[i]; + + return max_t; + +} +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +int calc_max_temper_edrk_air(void) +{ + int i, max_t=0; + + for (i=0;i<4;i++) + if (edrk.temper_edrk.real_int_temper_air[i]>max_t) + max_t = edrk.temper_edrk.real_int_temper_air[i]; + + return max_t; + +} +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +int calc_min_temper_edrk_air(void) +{ + int i, min_t=1000; + + for (i=0;i<4;i++) + if (edrk.temper_edrk.real_int_temper_air[i] +#include +#include +#include +#include + +#include "control_station.h" +#include "CAN_Setup.h" +#include "global_time.h" +#include "IQmathLib.h" +#include "mathlib.h" +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "xp_project.h" +#include "another_bs.h" + + + + + + +#pragma DATA_SECTION(Unites2SecondBS, ".slow_vars") +int Unites2SecondBS[SIZE_ARR_CAN_UNITES_BS2BS]={0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0\ + }; + + + +int max_count_send_to_can2second_bs = SIZE_ARR_CAN_UNITES_BS2BS; + + + + + +void SendAll2SecondBS(unsigned int pause) +{ + static int time_tick_modbus_can=0; + static unsigned int old_PWM_ticks=0; + static int count_write_to_modbus_can=0; + static int time_send_to_can=0; + int real_mbox, n_box; + + + + +//send to another BS + if (detect_pause_milisec(pause, &old_PWM_ticks)) + { + // if (edrk.flag_second_PCH==0) + // n_box = ANOTHER_BSU2_CAN_DEVICE; + // else + n_box = ANOTHER_BSU1_CAN_DEVICE; + + time_tick_modbus_can=0; + time_send_to_can=0; + + UpdateTableSecondBS(); + + real_mbox = get_real_out_mbox (UNITS_TYPE_BOX, n_box); + + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_ON)) + { + CAN_cycle_send( UNITS_TYPE_BOX, n_box, 0, &Unites2SecondBS[0], max_count_send_to_can2second_bs, CAN_BOX_STANDART_ADR, CAN_BOX_PRIORITY_NORMAL);// 40 . + } + } + + + +} + + + diff --git a/Inu/Src2/551/main/can_bs2bs.h b/Inu/Src2/551/main/can_bs2bs.h new file mode 100644 index 0000000..b3d69cf --- /dev/null +++ b/Inu/Src2/551/main/can_bs2bs.h @@ -0,0 +1,21 @@ +/* + * can_bs2bs.h + * + * Created on: 27 . 2020 . + * Author: stud + */ + +#ifndef SRC_MAIN_CAN_BS2BS_H_ +#define SRC_MAIN_CAN_BS2BS_H_ + +#define SIZE_ARR_CAN_UNITES_BS2BS 50 //100 + + +extern int Unites2SecondBS[SIZE_ARR_CAN_UNITES_BS2BS]; + +void SendAll2SecondBS(unsigned int pause); + + + + +#endif /* SRC_MAIN_CAN_BS2BS_H_ */ diff --git a/Inu/Src2/551/main/can_protocol_ukss.h b/Inu/Src2/551/main/can_protocol_ukss.h new file mode 100644 index 0000000..18bf157 --- /dev/null +++ b/Inu/Src2/551/main/can_protocol_ukss.h @@ -0,0 +1,63 @@ +/* + * can_protocol_ukss.h + * + * Created on: 23 . 2024 . + * Author: yura + */ + +#ifndef SRC_MAIN_CAN_PROTOCOL_UKSS_H_ +#define SRC_MAIN_CAN_PROTOCOL_UKSS_H_ + + + +#define CAN_PROTOCOL_UKSS 2 // 2 + + +#ifndef CAN_PROTOCOL_UKSS +#define CAN_PROTOCOL_UKSS 1 +#endif + + + + +#if (CAN_PROTOCOL_UKSS == 2) + + +#define ADR_CYCLES_TIMER_MAIN 96 // . CAN, * 10 m +#define ADR_CYCLES_TIMER_ADD 97 // . CAN, * 10 m +#define ADR_CYCLES_PAUSE_MAIN 98 // . CAN, * 10 m +#define ADR_CYCLES_PAUSE_ADD 99 // . CAN, * 10 m +#define ADR_CYCLES_REPEATE_MAIN 100 // . CAN, * 10 m +#define ADR_CYCLES_REPEATE_ADD 101 // . CAN, * 10 m +#define ADR_CYCLES_REPEATE_DIGIO 102 // . , + +#define ADR_LIGHT_LED_1 104 // 1 +#define ADR_LIGHT_LED_2 105 // 2 +#define ADR_LIGHT_LED_3 106 // 3 +#define ADR_LIGHT_LED_4 107 // 4 +#define ADR_LIGHT_LED_5 108 // 5 +#define ADR_LIGHT_LED_6 109 // 6 +#define ADR_LIGHT_LED_7 110 // 7 + + + +#define ADR_COUNT_CYCLES_MAIN 120 // . CAN +#define ADR_COUNT_CYCLES_ADD 121 // . CAN +#define ADR_COUNT_FULL_CYCLES_MAIN 122 //- . CAN +#define ADR_COUNT_FULL_CYCLES_ADD 123 //- . CAN + +#define ADR_PROTOCOL_VERSION 125 // +#define ADR_UKSS_NUMBER 126 // + +#endif + + + + + + + + + + +#endif /* SRC_MAIN_CAN_PROTOCOL_UKSS_H_ */ diff --git a/Inu/Src2/551/main/control_station_project.c b/Inu/Src2/551/main/control_station_project.c new file mode 100644 index 0000000..877b4fb --- /dev/null +++ b/Inu/Src2/551/main/control_station_project.c @@ -0,0 +1,2493 @@ +/* + * control_station_project.c + * + * Created on: 1 . 2020 . + * Author: Yura + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "control_station.h" +#include "CAN_Setup.h" +#include "global_time.h" +#include "IQmathLib.h" +#include "mathlib.h" +#include "modbus_table_v2.h" +#include "vector_control.h" +#include "RS_Functions.h" +#include "adc_tools.h" +#include "RS_Function_terminal.h" +#include "alg_simple_scalar.h" + + + + + + +/*CONTROL_STATION_TERMINAL_RS232 + CONTROL_STATION_TERMINAL_CAN, + + CONTROL_STATION_INGETEAM_PULT_RS485, + CONTROL_STATION_MPU_SVU_CAN, + CONTROL_STATION_MPU_KEY_CAN, + CONTROL_STATION_MPU_SVU_RS485, + CONTROL_STATION_MPU_KEY_RS485, + CONTROL_STATION_ZADATCHIK_CAN, + + + + CONTROL_STATION_CMD_GO = 0,// cmd_go / + CONTROL_STATION_CMD_SET_IZAD,// + CONTROL_STATION_CMD_SET_ROTOR,// + CONTROL_STATION_CMD_CHARGE,// + CONTROL_STATION_CMD_UNCHARGE,// + CONTROL_STATION_CMD_CHECKBACK,// + CONTROL_STATION_CMD_TEST_LEDS + */ + + +#define DEC_ZAD_OBOROTS 1 +#define INC_ZAD_OBOROTS 1 + + + + + +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +void detect_active_from_all_signals(void) +{ + if (control_station.alive_control_station[CONTROL_STATION_TERMINAL_RS232]) + { + // control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_ACTIVE_CONTROL] = control_station + } + + +} +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +float plus_minus_oborots(int key_plus, int key_minus, float ff, int ufconst_vector, int flag) +{ + static float ff_add=0, ff_dec=0; + + float ff_add1=0, ff_dec1=0; + float ff_add2=0, ff_dec2=0; + float ff_add3=0, ff_dec3=0; + + static int prev_key_plus=0, prev_key_minus=0, count_press2 = 0, level_d1 = 2; + + static int direct_zad=0, direct_cur=0, only_plus=0, only_minus=0; + static unsigned int old_time_plus_minus=0, count_press = 0; + + if (flag==1) + { + count_press = 0; + + ff_dec = 0; + ff_add = 0; + + prev_key_plus = key_plus; + prev_key_minus = key_minus; + + return ff; + } + + if (ff>0) + { +// if (key_minus || key_plus) + only_plus = 1; + only_minus = 0; + } + else + if (ff<0) + { +// if (key_minus || key_plus) + only_minus = 1; + only_plus = 0; + } + else + { + if (key_minus==0 && key_plus==0) + { + only_plus = 0; + only_minus = 0; + } + + } + + +// +// +// if (key_plus) +// { +// if (ff>0) +// direct_zad = 1; +// if (ff<0) +// direct_zad = -1; +// if (ff==0) +// direct_zad = 0; +// +// } +// if (key_minus) +// { +// if (ff>0) +// direct_zad = -1; +// if (ff<0) +// direct_zad = 1; +// if (ff==0) +// direct_zad = 0; +// } + + + if (ufconst_vector==0) + { + ff_add1 = INC_ZAD_OBOROTS*10.0; + ff_dec1 = DEC_ZAD_OBOROTS*10.0; + + ff_add2 = INC_ZAD_OBOROTS*30.0; + ff_dec2 = DEC_ZAD_OBOROTS*30.0; + ff_add3 = INC_ZAD_OBOROTS*60.0; + ff_dec3 = DEC_ZAD_OBOROTS*60.0; + + } + else + { + ff_add1 = INC_ZAD_OBOROTS; + ff_dec1 = DEC_ZAD_OBOROTS; + + ff_add2 = INC_ZAD_OBOROTS*1.0; + ff_dec2 = DEC_ZAD_OBOROTS*1.0; + ff_add3 = INC_ZAD_OBOROTS*2.0; + ff_dec3 = DEC_ZAD_OBOROTS*2.0; + } + + + if (detect_pause_milisec(250,&old_time_plus_minus)) + { + if (key_minus || key_plus) + { + if (count_press<300) + count_press++; + + if (count_press2<10) + count_press2++; + + } + else + { + count_press = 0; + count_press2 = 0; + } + + if (count_press==1) + { +// ff_dec = 0; +// ff_add = 0; + ff_dec = ff_dec1; + ff_add = ff_add1; + level_d1 = 4; + } + + if (count_press==6) + { + ff_dec = ff_dec1; + ff_add = ff_add1; + level_d1 = 2; + } + + if (count_press==15) + { + ff_dec = ff_dec1; + ff_add = ff_add1; + level_d1 = 0; + } +// if (count_press==60) +// { +// ff_dec = ff_dec2; +// ff_add = ff_add2; +// level_d1 = 0; +// } + + if (count_press==30) + { + ff_dec = ff_dec3; + ff_add = ff_add3; + } + + + if (key_minus) + { + if ((count_press2>=level_d1) || (count_press==1)) + { + if (ff>ff_dec) + { + ff=ff-ff_dec; + if (ff0) + ff = 0; + } + else + if (ff<=ff_dec && ff>0) + ff=0; + else + if (ff<0 && only_plus==0) + ff=ff-ff_add; + else + if (ff==0 && only_plus==0) + ff=ff-DEAD_ZONE_ZADANIE_OBOROTS_ROTOR; + + count_press2 = 0; + } + } + else + if (key_plus) + { + if ((count_press2>=level_d1) || (count_press==1)) + { + if (ff==0 && only_minus==0) + ff=ff+DEAD_ZONE_ZADANIE_OBOROTS_ROTOR; + else + if (ff>=0 && only_minus==0) + ff=ff+ff_add; + else + if (ff>=-ff_dec && ff<0) + ff=0; + else + if (ff<-ff_dec) + { + ff=ff+ff_dec; + if (ff>-DEAD_ZONE_ZADANIE_OBOROTS_ROTOR && ff<0) + ff = 0; + } + + count_press2 = 0; + } + } + + } + + if (ufconst_vector==0) + ff = my_satur_float(ff,fast_round(MAX_ZADANIE_F*100.0),fast_round(-MAX_ZADANIE_F*100.0), 0); + else + ff = my_satur_float(ff, MAX_ZADANIE_OBOROTS_ROTOR, MIN_ZADANIE_OBOROTS_ROTOR, 0); + + + prev_key_plus = key_plus; + prev_key_minus = key_minus; + + + return ff; +} + +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +void parse_parameters_from_one_control_station_another_bs(int cc) +{ + int i;//, pos_numbercmd; + static int prev_checkback = 0; + static int flag_wait_revers_go = 0; + + _iq _iq_ff; + static unsigned int prev_charge=0, prev_uncharge=0, key_local_charge=0, key_local_uncharge=0; + static unsigned int old_time_pult_ing = 0; + float ff=0, ff_add=0, ff_dec=0; + int key_plus = 0, key_minus = 0; + + + + + if (edrk.ms.err_signals.alive_can_to_another_bs==0) + { + + // + // edrk.zadanie_from_another_bs.int_fzad = Unites[ANOTHER_BSU1_CAN_DEVICE][3]; + // edrk.zadanie_from_another_bs.int_kzad = Unites[ANOTHER_BSU1_CAN_DEVICE][4]; + // edrk.zadanie_from_another_bs.int_Izad = Unites[ANOTHER_BSU1_CAN_DEVICE][5]; + // edrk.zadanie_from_another_bs.int_oborots_zad = Unites[ANOTHER_BSU1_CAN_DEVICE][6]; + // edrk.zadanie_from_another_bs.int_power_zad = Unites[ANOTHER_BSU1_CAN_DEVICE][7]; + // // + // edrk.zadanie_from_another_bs.iq_fzad = _IQ15toIQ(edrk.zadanie_from_another_bs.int_fzad); + // edrk.zadanie_from_another_bs.iq_kzad = _IQ15toIQ(edrk.zadanie_from_another_bs.int_kzad); + // edrk.zadanie_from_another_bs.iq_Izad = _IQ15toIQ(edrk.zadanie_from_another_bs.int_Izad); + // edrk.zadanie_from_another_bs.oborots_zad = edrk.zadanie_from_another_bs.int_oborots_zad; + // edrk.zadanie_from_another_bs.iq_power_zad = _IQ15toIQ(edrk.zadanie_from_another_bs.int_power_zad); + + + } + else + { + + + + } + + + if (control_station.alive_control_station[cc]) + { + + } + else + { + for (i=0;i 0 && Unites[ANOTHER_BSU1_CAN_DEVICE][12] < 600) { + vect_control.iqId_min = _IQ((float)Unites[ANOTHER_BSU1_CAN_DEVICE][12] / NORMA_ACP); + } +/* + + control_station.array_cmd[cc][CONTROL_STATION_CMD_ACTIVE_CONTROL] = control_station.active_control_station[CONTROL_STATION_VPU_CAN]; + + +// scalar, vector, ufconst + control_station.array_cmd[cc][CONTROL_STATION_CMD_UFCONST_VECTOR] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_UFCONST_VECTOR]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_SCALAR_FOC] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_SCALAR_FOC]; + + + control_station.array_cmd[cc][CONTROL_STATION_CMD_ROTOR_POWER] = 0; + +// +// if + + if ((detect_pause_milisec(100,&old_time_pult_ing)) && control_station.array_cmd[cc][CONTROL_STATION_CMD_ACTIVE_CONTROL]) + { + +// control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = control_station.raw_array_data[cc][4].all; + ff = control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR]; + + key_plus = edrk.from_vpu.bits.PLUS; + key_minus = edrk.from_vpu.bits.MINUS; + + ff = plus_minus_oborots(key_plus, key_minus, ff, control_station.array_cmd[cc][CONTROL_STATION_CMD_UFCONST_VECTOR]); + + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR] = ff; + } + + +// +// pos_numbercmd = 15; // , + + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHECKBACK] = edrk.from_vpu.bits.KVITIR; + +// , + key_local_charge = 0;//edrk.from_shema.bits.SBOR_SHEMA; + key_local_uncharge = 0;//edrk.from_shema.bits.RAZBOR_SHEMA; + + if (key_local_charge && prev_charge==0) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + prev_charge = key_local_charge; + + + if (key_local_uncharge && prev_uncharge==0) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + prev_uncharge = key_local_uncharge; + + +/////////////////////////////////////////// +// + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_IZAD] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_SET_IZAD]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_KM] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_SET_KM]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_U_ZARYAD] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_SET_U_ZARYAD]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_K_U_DISBALANCE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_SET_K_U_DISBALANCE]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_K_PLUS_U_DISBALANCE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_SET_K_PLUS_U_DISBALANCE]; + + +// if (control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR]!=0) +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 1; +// else +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 0; + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_GO]; + +// +// control_station.array_cmd[cc][CONTROL_STATION_CMD_TEST_LEDS] = 0; +// +// prev_checkback = control_station.raw_array_data[cc][pos_numbercmd].bits.bit1; + + // rs232 + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_PUMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_ENABLE_ON_CHARGE]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_QTV]; + + // 0 - auto on - rand pump + // 1 - auto on 1 pump + // 2 - auto on 2 pump + // 3 - manual on 1 pump + // 4 - manual on 2 pump + + // + control_station.array_cmd[cc][CONTROL_STATION_CMD_MODE_PUMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MODE_PUMP]; + + + if (control_station.array_cmd[cc][CONTROL_STATION_CMD_ACTIVE_CONTROL]==0) + return; +*/ + +} +///////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +void parse_parameters_from_one_control_station_pult_vpu(int cc) +{ + int i;//, pos_numbercmd; + static int prev_checkback = 0, prev_key_oborots = 0; + static int flag_wait_revers_go = 0; + + _iq _iq_ff; + static unsigned int prev_charge=0, prev_uncharge=0, key_local_charge=0, key_local_uncharge=0; + static unsigned int old_time_pult_ing = 0, old_time_pult_ing2 = 0; + float ff=0, ff_add=0, ff_dec=0; + int key_plus = 0, key_minus = 0; + + + if (control_station.alive_control_station[cc]) + { + + } + else + { + for (i=0;i=0) + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = -control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + + + + + +// +// pos_numbercmd = 15; // , + + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHECKBACK] = edrk.from_vpu.bits.KVITIR; + +// , + key_local_charge = 0;//edrk.from_shema.bits.SBOR_SHEMA; + key_local_uncharge = 0;//edrk.from_shema.bits.RAZBOR_SHEMA; + + if (key_local_charge && prev_charge==0) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + prev_charge = key_local_charge; + + + if (key_local_uncharge) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + prev_uncharge = key_local_uncharge; + + + + +// if (control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR]!=0) +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 1; +// else +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 0; +// +// control_station.array_cmd[cc][CONTROL_STATION_CMD_TEST_LEDS] = 0; +// +// prev_checkback = control_station.raw_array_data[cc][pos_numbercmd].bits.bit1; + + + // rs232 + if (control_station.alive_control_station[CONTROL_STATION_TERMINAL_RS232]) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_GO]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_PUMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_ENABLE_ON_CHARGE]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_QTV]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_UMP] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_UMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_MANUAL_DISCHARGE]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_STOP_LOGS] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_STOP_LOGS]; + + } + else + if (control_station.alive_control_station[CONTROL_STATION_INGETEAM_PULT_RS485]) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_GO]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_PUMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_ENABLE_ON_CHARGE]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_QTV]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_UMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_UMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MANUAL_DISCHARGE]; + + edrk.Status_Ready.bits.ImitationReady2 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][181].all; + edrk.Obmotka1 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][194].all; + edrk.Obmotka2 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][195].all; + edrk.disable_alg_u_disbalance = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][193].all; + + + edrk.Run_Rascepitel_from_RS = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][182].all; + edrk.stop_logs_rs232 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][183].all; + edrk.stop_slow_log = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][184].all; + edrk.disable_limit_power_from_svu = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][185].all; + edrk.disable_uom = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][186].all; + + + + + } + + + // 0 - auto on - rand pump + // 1 - auto on 1 pump + // 2 - auto on 2 pump + // 3 - manual on 1 pump + // 4 - manual on 2 pump + + // + control_station.array_cmd[cc][CONTROL_STATION_CMD_MODE_PUMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MODE_PUMP]; + + + if (control_station.array_cmd[cc][CONTROL_STATION_CMD_ACTIVE_CONTROL]==0) + return; + + +} +///////////////////////////////////////////////////////////// + + + +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +void parse_parameters_from_one_control_station_pult_zadat4ik(int cc) +{ + int i;//, pos_numbercmd; + static int prev_checkback = 0, prev_key_oborots = 0; + static int flag_wait_revers_go = 0; + + float ff=0, ff_add=0, ff_dec=0; + int key_plus = 0, key_minus = 0; + + _iq _iq_ff; + static unsigned int prev_charge=0, prev_uncharge=0, key_local_charge=0, key_local_uncharge=0; + static unsigned int old_time_pult_ing = 0, old_time_pult_ing2 = 0; + + if (control_station.alive_control_station[cc]) + { + + } + else + { + for (i=0;i=0) + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = -control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + +// +// pos_numbercmd = 15; // , + + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHECKBACK] = edrk.from_zadat4ik.bits.KVITIR; + +// , + key_local_charge = edrk.from_shema_filter.bits.SBOR_SHEMA; + key_local_uncharge = edrk.from_shema_filter.bits.RAZBOR_SHEMA; + + + if (key_local_uncharge && key_local_charge) + { + key_local_uncharge = 0; + key_local_charge = 0; + //edrk.errors.e1.bits.BOTH_KEYS_CHARGE_DISCHARGE |=1; + } + + if (key_local_charge && prev_charge==0) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + prev_charge = key_local_charge; + + + if (key_local_uncharge) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + prev_uncharge = key_local_uncharge; + + +// if (control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR]!=0) +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 1; +// else +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 0; + +// +// control_station.array_cmd[cc][CONTROL_STATION_CMD_TEST_LEDS] = 0; +// +// prev_checkback = control_station.raw_array_data[cc][pos_numbercmd].bits.bit1; + + + // rs232 + if (control_station.alive_control_station[CONTROL_STATION_TERMINAL_RS232]) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_GO]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_PUMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_ENABLE_ON_CHARGE]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_QTV]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_UMP] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_UMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_MANUAL_DISCHARGE]; + } + else + if (control_station.alive_control_station[CONTROL_STATION_INGETEAM_PULT_RS485]) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_GO]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_PUMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_ENABLE_ON_CHARGE]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_QTV]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_UMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_UMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MANUAL_DISCHARGE]; + + edrk.Status_Ready.bits.ImitationReady2 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][181].all; + edrk.Obmotka1 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][194].all; + edrk.Obmotka2 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][195].all; + edrk.disable_alg_u_disbalance = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][193].all; + + edrk.Run_Rascepitel_from_RS = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][182].all; + edrk.stop_logs_rs232 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][183].all; + edrk.stop_slow_log = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][184].all; + edrk.disable_limit_power_from_svu = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][185].all; + edrk.disable_uom = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][186].all; + + } + + + // 0 - auto on - rand pump + // 1 - auto on 1 pump + // 2 - auto on 2 pump + // 3 - manual on 1 pump + // 4 - manual on 2 pump + + // + control_station.array_cmd[cc][CONTROL_STATION_CMD_MODE_PUMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MODE_PUMP]; + + + if (control_station.array_cmd[cc][CONTROL_STATION_CMD_ACTIVE_CONTROL]==0) + return; + + +} +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +void parse_parameters_from_one_control_station_pult_ingeteam(int cc) +{ + int i, zad_power; //pos_numbercmd + static int prev_checkback = 0; + static int flag_wait_revers_go = 0; + float ff=0, ff_add=0, ff_dec=0; + int key_plus = 0, key_minus = 0; + _iq _iq_ff=0; + static unsigned int prev_key_local_charge_key=0, prev_key_local_uncharge_key=0, + key_local_charge_key=0, key_local_uncharge_key=0; + static unsigned int prev_key_local_charge_display=0, prev_key_local_uncharge_display=0, + key_local_charge_display=0, key_local_uncharge_display=0; + + static unsigned int prev_charge=0, prev_uncharge=0, key_local_charge=0, key_local_uncharge=0; + + static unsigned int old_time_pult_ing = 0, old_time_pult_ing2 = 0; + static unsigned int prev_key_local_charge_uncharge_display=0, key_local_charge_uncharge_display=0; + + if (control_station.alive_control_station[cc]) + { + + } + else + { + for (i=0;i=0) + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = -control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + + } + + + + } + + +// +// pos_numbercmd = 15; // , + + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHECKBACK] = control_station.raw_array_data[cc][1].all; + + +// , + key_local_charge_key = edrk.from_ing2.bits.KEY_SBOR; + key_local_uncharge_key = edrk.from_ing2.bits.KEY_RAZBOR; + + + +// , + key_local_charge_uncharge_display = control_station.raw_array_data[cc][2].all; + + + prev_key_local_charge_key = key_local_charge_key; + prev_key_local_uncharge_key = key_local_uncharge_key; + + + if (prev_key_local_charge_uncharge_display != key_local_charge_uncharge_display) + { + if (key_local_charge_uncharge_display==1) + { + key_local_charge_display = 1; + key_local_uncharge_display = 0; + } + else + { + key_local_charge_display = 0; + key_local_uncharge_display =1; + } + } + else + { + key_local_charge_display = 0; + key_local_uncharge_display = 0; + } + + prev_key_local_charge_uncharge_display = key_local_charge_uncharge_display; + + + prev_key_local_charge_display = key_local_charge_display; + prev_key_local_uncharge_display = key_local_uncharge_display; + + key_local_charge = key_local_charge_key || key_local_charge_display; + key_local_uncharge = key_local_uncharge_key || key_local_uncharge_display; + + if (key_local_uncharge_key && key_local_charge_key) + { + key_local_uncharge_key = 0; + key_local_charge_key = 0; +// edrk.errors.e1.bits.BOTH_KEYS_CHARGE_DISCHARGE |=1; + } + + + + if (edrk.Status_Ready.bits.ImitationReady2==0) // , .. + { + if (key_local_charge && prev_charge==0) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + + + + if (key_local_uncharge) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + + } + else + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + } + + prev_charge = key_local_charge; + prev_uncharge = key_local_uncharge; + + + +// if (control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR]!=0) +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 1; +// else +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 0; +// + +// +// control_station.array_cmd[cc][CONTROL_STATION_CMD_TEST_LEDS] = 0; +// +// prev_checkback = control_station.raw_array_data[cc][pos_numbercmd].bits.bit1; + + + // rs232 + if (control_station.alive_control_station[CONTROL_STATION_TERMINAL_RS232]) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_PUMP] + || control_station.raw_array_data[cc][188].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] + || control_station.raw_array_data[cc][191].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_QTV] + || control_station.raw_array_data[cc][189].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_UMP] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_UMP] + || control_station.raw_array_data[cc][190].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_MANUAL_DISCHARGE] + || control_station.raw_array_data[cc][180].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_GO] + || !control_station.raw_array_data[cc][192].all; + } + else + { + + edrk.Status_Ready.bits.ImitationReady2 = control_station.raw_array_data[cc][181].all; + edrk.Run_Rascepitel_from_RS = control_station.raw_array_data[cc][182].all; + edrk.stop_logs_rs232 = control_station.raw_array_data[cc][183].all; + edrk.stop_slow_log = control_station.raw_array_data[cc][184].all; + edrk.disable_limit_power_from_svu = control_station.raw_array_data[cc][185].all; + edrk.disable_uom = control_station.raw_array_data[cc][186].all; + + + + edrk.Obmotka1 = control_station.raw_array_data[cc][194].all; + edrk.Obmotka2 = control_station.raw_array_data[cc][195].all; + edrk.disable_alg_u_disbalance = control_station.raw_array_data[cc][193].all; + + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.raw_array_data[cc][188].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.raw_array_data[cc][189].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_UMP] = control_station.raw_array_data[cc][190].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.raw_array_data[cc][191].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = control_station.raw_array_data[cc][180].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = !control_station.raw_array_data[cc][192].all; + + } + + + + //control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.raw_array_data[cc][188].all; +// control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.raw_array_data[cc][189].all; + //control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_UMP] = control_station.raw_array_data[cc][190].all; + //control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.raw_array_data[cc][191].all; +// control_station.array_cmd[cc][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = control_station.raw_array_data[cc][180].all; +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = !control_station.raw_array_data[cc][192].all; + + + + // 0 - auto on - rand pump + // 1 - auto on 1 pump + // 2 - auto on 2 pump + // 3 - manual on 1 pump + // 4 - manual on 2 pump + + if (control_station.raw_array_data[cc][9].all<=2) // _(0)_(1) + { + if (control_station.raw_array_data[cc][9].all==0) // (0) 1_2(1) + control_station.array_cmd[cc][CONTROL_STATION_CMD_MODE_PUMP] = 0; + if (control_station.raw_array_data[cc][9].all==1) // _1 + control_station.array_cmd[cc][CONTROL_STATION_CMD_MODE_PUMP] = 1; + if (control_station.raw_array_data[cc][9].all==2) // _2 + control_station.array_cmd[cc][CONTROL_STATION_CMD_MODE_PUMP] = 2; + } + else + { + if (control_station.raw_array_data[cc][9].all==3) // _1_2 + control_station.array_cmd[cc][CONTROL_STATION_CMD_MODE_PUMP] = 3; + if (control_station.raw_array_data[cc][9].all==4) // _1_2 + control_station.array_cmd[cc][CONTROL_STATION_CMD_MODE_PUMP] = 4; + } + + + if (control_station.array_cmd[cc][CONTROL_STATION_CMD_ACTIVE_CONTROL]==0) + return; + +} +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +void parse_parameters_from_one_control_station_MPU_SVU(int cc) +{ + int i, zad_power, limit_power; + _iq _iq_ff; + + static unsigned int old_time_MPU_SVU = 0; + + static int prev_checkback_3 = 0; + static int flag_wait_revers_go_3 = 0; + static unsigned int prev_charge_3 = 0, prev_uncharge_3 = 0, cmd_local_charge_3 = 0, cmd_local_uncharge_3 = 0; + static unsigned int old_time_MPU_SVU_3 = 0; + + static int prev_checkback_4 = 0; + static int flag_wait_revers_go_4 = 0; + static unsigned int prev_charge_4 = 0, prev_uncharge_4 = 0, cmd_local_charge_4 = 0, cmd_local_uncharge_4 = 0; + static unsigned int old_time_MPU_SVU_4 = 0; + + + + if (control_station.alive_control_station[cc]) + { + + } + else + { + for (i=0;i=0) + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = -control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + + } + } + // + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHECKBACK] = control_station.raw_array_data[cc][0].all; + + + if (cc==CONTROL_STATION_MPU_SVU_CAN) + { + // , + if (edrk.flag_second_PCH == 0) { + cmd_local_charge_3 = control_station.raw_array_data[cc][6].all; + cmd_local_uncharge_3 = control_station.raw_array_data[cc][9].all; + } else { + cmd_local_charge_3 = control_station.raw_array_data[cc][7].all;//modbus_table_can_in[129].all; //control_station.raw_array_data[cc][7].all; + cmd_local_uncharge_3 = control_station.raw_array_data[cc][10].all; + } + + + if (cmd_local_charge_3 && cmd_local_uncharge_3) + { + cmd_local_charge_3 = 0; + cmd_local_uncharge_3 = 0; + // edrk.errors.e1.bits.BOTH_KEYS_CHARGE_DISCHARGE |=1; + } + + + + if (cmd_local_charge_3 && prev_charge_3==0) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + prev_charge_3 = cmd_local_charge_3; + + + if (cmd_local_uncharge_3) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + + prev_uncharge_3 = cmd_local_uncharge_3; + } + + if (cc==CONTROL_STATION_MPU_KEY_CAN) + { + // , + if (edrk.flag_second_PCH == 0) { + cmd_local_charge_4 = control_station.raw_array_data[cc][6].all; + cmd_local_uncharge_4 = control_station.raw_array_data[cc][9].all; + } else { + cmd_local_charge_4 = control_station.raw_array_data[cc][7].all;//modbus_table_can_in[129].all; //control_station.raw_array_data[cc][7].all; + cmd_local_uncharge_4 = control_station.raw_array_data[cc][10].all; + } + + + if (cmd_local_charge_4 && cmd_local_uncharge_4) + { + cmd_local_charge_4 = 0; + cmd_local_uncharge_4 = 0; + // edrk.errors.e1.bits.BOTH_KEYS_CHARGE_DISCHARGE |=1; + } + + + + if (cmd_local_charge_4 && prev_charge_4==0) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + prev_charge_4 = cmd_local_charge_4; + + + if (cmd_local_uncharge_4) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 1; + control_station.array_cmd[cc][CONTROL_STATION_CMD_CHARGE] = 0; + } + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_UNCHARGE] = 0; + + prev_uncharge_4 = cmd_local_uncharge_4; + } + + control_station.array_cmd[cc][CONTROL_STATION_CMD_BLOCK_BS] = control_station.raw_array_data[cc][4].all; + +// if (control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR]!=0) +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 1; +// else +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 0; +// +// +// control_station.array_cmd[cc][CONTROL_STATION_CMD_TEST_LEDS] = 0; +// +// prev_checkback = control_station.raw_array_data[cc][pos_numbercmd].bits.bit1; + + + // rs232 + if (control_station.alive_control_station[CONTROL_STATION_TERMINAL_RS232]) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_GO]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_PUMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_ENABLE_ON_CHARGE]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_QTV]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_UMP] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_DISABLE_ON_UMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_MANUAL_DISCHARGE]; + } + else + if (control_station.alive_control_station[CONTROL_STATION_INGETEAM_PULT_RS485]) + { + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_GO]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_PUMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_ENABLE_ON_CHARGE]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_QTV] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_QTV]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_DISABLE_ON_UMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_UMP]; + control_station.array_cmd[cc][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MANUAL_DISCHARGE]; + + edrk.Status_Ready.bits.ImitationReady2 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][181].all; + edrk.Obmotka1 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][194].all; + edrk.Obmotka2 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][195].all; + edrk.disable_alg_u_disbalance = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][193].all; + + edrk.Run_Rascepitel_from_RS = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][182].all; + edrk.stop_logs_rs232 = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][183].all; + edrk.stop_slow_log = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][184].all; + edrk.disable_limit_power_from_svu = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][185].all; + edrk.disable_uom = control_station.raw_array_data[CONTROL_STATION_INGETEAM_PULT_RS485][186].all; + + + } + + + // 0 - auto on - rand pump + // 1 - auto on 1 pump + // 2 - auto on 2 pump + // 3 - manual on 1 pump + // 4 - manual on 2 pump + + // + control_station.array_cmd[cc][CONTROL_STATION_CMD_MODE_PUMP] = control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MODE_PUMP]; + + + edrk.breaker_on = control_station.raw_array_data[cc][17].all; + + edrk.break_tempers[0] = control_station.raw_array_data[cc][18].all; + edrk.break_tempers[1] = control_station.raw_array_data[cc][19].all; + edrk.break_tempers[2] = control_station.raw_array_data[cc][20].all; + edrk.break_tempers[3] = control_station.raw_array_data[cc][21].all; + + + if (control_station.array_cmd[cc][CONTROL_STATION_CMD_ACTIVE_CONTROL]==0) + return; + +} +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +void parse_parameters_from_one_control_station_terminal_rs232(int cc) +{ + static int pos_numbercmd = (sizeof(CMD_ANALOG_DATA_STRUCT) >> 1); + int i, fint; + static int prev_checkback = 0, lock_ImitationReady2 = 0; + static int flag_wait_revers_go = 0; + static unsigned int prev_charge=0, prev_uncharge=0, key_local_charge=0, key_local_uncharge=0; + float ff; + _iq _iq_ff; + int zad_power=0; + + if (control_station.alive_control_station[cc]) + { + + } + else + { + for (i=0;i=0) + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + else + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = -control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_LIMIT_POWER]; + } + + //control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR] = (int)control_station.raw_array_data[cc][0].all; + //control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER] = my_satur_int(control_station.raw_array_data[cc][2].all, MAX_ZADANIE_POWER, MIN_ZADANIE_POWER); + + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_KM] = control_station.raw_array_data[cc][1].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_IZAD] = my_satur_int(control_station.raw_array_data[cc][3].all, MAX_ZADANIE_I_M, 0, 0); + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_U_ZARYAD] = control_station.raw_array_data[cc][4].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_K_U_DISBALANCE] = control_station.raw_array_data[cc][5].all; + control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_K_PLUS_U_DISBALANCE] = control_station.raw_array_data[cc][6].all; + + + + if (control_station.raw_array_data[cc][8].all > 0 && control_station.raw_array_data[cc][8].all <= 600 && edrk.MasterSlave == MODE_MASTER) { + vect_control.iqId_min = _IQ((float)control_station.raw_array_data[cc][8].all / NORMA_ACP); + } + + fint = (int)control_station.raw_array_data[cc][9].all; + if (fint>=-360 && fint<=360 && edrk.MasterSlave == MODE_MASTER) + { + vect_control.add_tetta = _IQ(fint / 180.0 * PI); + } + else + vect_control.add_tetta = 0; + + fint = (int)control_station.raw_array_data[cc][10].all; + if (fint>=0) + { + edrk.t_slow_log = fint; + } + else + edrk.t_slow_log = 0; + + fint = (int)control_station.raw_array_data[cc][11].all; + if (fint) + { + simple_scalar1.add_bpsi = _IQ(fint/1000.0/NORMA_FROTOR);//_IQ(0.05/NORMA_FROTOR); + } + else + simple_scalar1.add_bpsi = 0; + + fint = (int)control_station.raw_array_data[cc][12].all; + if (fint) + { + simple_scalar1.add_power_limit = _IQ(fint*1000.0/(NORMA_MZZ*NORMA_MZZ));//_IQ(0.05/NORMA_FROTOR); + } + else + simple_scalar1.add_power_limit = 0; + + + fint = (int)control_station.raw_array_data[cc][13].all; + if (fint) + { + simple_scalar1.sdvig_power_limit = _IQ(fint*1000.0/(NORMA_MZZ*NORMA_MZZ));//_IQ(0.05/NORMA_FROTOR); + } + else + simple_scalar1.sdvig_power_limit = 0; + + +//#if (_FLOOR6) + fint = (int)control_station.raw_array_data[cc][14].all; + if (fint>=0 && fint<=3200) + { + analog.iqU_1_imit = _IQ(fint/NORMA_ACP); + } + else + analog.iqU_1_imit = 0; +//#else +// analog.iqU_1_imit = 0; +//#endif + + prev_checkback = control_station.array_cmd[cc][CONTROL_STATION_CMD_CHECKBACK];//control_station.raw_array_data[cc][pos_numbercmd].bits.bit1; + // edrk.KvitirRS = 1; + + control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.raw_array_data[cc][pos_numbercmd].bits.bit5; + +// if (control_station.array_cmd[cc][CONTROL_STATION_CMD_ROTOR_POWER]==0) +// { +// if (control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR]!=0) +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.raw_array_data[cc][pos_numbercmd].bits.bit5; +// else +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 0; +// } +// else +// { +// if (control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_POWER]!=0) +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = control_station.raw_array_data[cc][pos_numbercmd].bits.bit5; +// else +// control_station.array_cmd[cc][CONTROL_STATION_CMD_GO] = 0; +// } + + +/* + edrk.from_rs.bits.ACTIVE = control_station.array_cmd[cc][CONTROL_STATION_CMD_ACTIVE_CONTROL]; + + + if (edrk.from_rs.bits.ACTIVE==0) + return; + + edrk.from_can.bits.ACTIVE = 0; + +*/ + + + + if (control_station.array_cmd[cc][CONTROL_STATION_CMD_ACTIVE_CONTROL]==0) + return; + + // CAN RS232 + if (control_station.array_cmd[CONTROL_STATION_TERMINAL_RS232][CONTROL_STATION_CMD_ACTIVE_CONTROL] && cc==CONTROL_STATION_TERMINAL_CAN) + return; + + + + + +// edrk.DirectOUT = control_station.raw_array_data[cc][pos_numbercmd].bits.bit7; + +// edrk.DirectNagrevOff = control_station.raw_array_data[cc][pos_numbercmd].bits.bit8; +// edrk.DirectBlockKeyOff = control_station.raw_array_data[cc][pos_numbercmd].bits.bit9; +//// edrk.DirectPumpON = control_station.raw_array_data[cc][pos_numbercmd].bits.bit10; +// edrk.DirectZaryadOn = control_station.raw_array_data[cc][pos_numbercmd].bits.bit11; + + +// edrk.SetSpeed = control_station.raw_array_data[cc][pos_numbercmd].bits.bit14; + + + + + + //////////////////////////// + ///////////////////////// + + +} + +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +void parse_data_from_master_to_alg(void) +{ + + if (edrk.MasterSlave==MODE_SLAVE) + { + control_station.active_array_cmd[CONTROL_STATION_CMD_SET_ROTOR] = control_station.array_cmd[CONTROL_STATION_ANOTHER_BS][CONTROL_STATION_CMD_SET_ROTOR]; + control_station.active_array_cmd[CONTROL_STATION_CMD_SET_KM] = control_station.array_cmd[CONTROL_STATION_ANOTHER_BS][CONTROL_STATION_CMD_SET_KM]; + control_station.active_array_cmd[CONTROL_STATION_CMD_SET_IZAD] = control_station.array_cmd[CONTROL_STATION_ANOTHER_BS][CONTROL_STATION_CMD_SET_IZAD]; + control_station.active_array_cmd[CONTROL_STATION_CMD_SET_POWER] = control_station.array_cmd[CONTROL_STATION_ANOTHER_BS][CONTROL_STATION_CMD_SET_POWER]; + } + +} +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// + +void parse_analog_data_from_active_control_station_to_alg(void) +{ + float ff, ff1; + _iq _iq_ff; + int i; + +// edrk.disable_interrupt_sync = control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_INTERRUPT_SYNC]; +// edrk.disable_interrupt_timer2 = control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_INTERRUPT_TIMER2]; + + edrk.NoDetectUZeroDischarge = control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_QTV]; + + // if (current_active_control==CONTROL_STATION_TERMINAL_RS232) + edrk.StartGEDfromControl = control_station.active_array_cmd[CONTROL_STATION_CMD_GO]; + + + +////////////////// + if (control_station.active_array_cmd[CONTROL_STATION_CMD_UFCONST_VECTOR]==0) + edrk.Mode_ScalarVectorUFConst = ALG_MODE_UF_CONST; + else + if (control_station.active_array_cmd[CONTROL_STATION_CMD_SCALAR_FOC]==0) + { + if (control_station.active_array_cmd[CONTROL_STATION_CMD_ROTOR_POWER]==0) + edrk.Mode_ScalarVectorUFConst = ALG_MODE_SCALAR_OBOROTS; + else + edrk.Mode_ScalarVectorUFConst = ALG_MODE_SCALAR_POWER; + } + else + { + if (control_station.active_array_cmd[CONTROL_STATION_CMD_ROTOR_POWER]==0) + edrk.Mode_ScalarVectorUFConst = ALG_MODE_FOC_OBOROTS; + else + edrk.Mode_ScalarVectorUFConst = ALG_MODE_FOC_POWER; + } + + + ////////////////////////////////////////////////////// +// edrk.W_from_RS = control_station.array_cmd[cc][CONTROL_STATION_CMD_SET_ROTOR]; //DataAnalog1; +// ff = control_station.active_array_cmd[CONTROL_STATION_CMD_SET_I_VOZBUD];//0;//DataAnalog4; +// edrk.I_zad_vozb_add_from_RS = my_satur_float(ff,MAX_ZADANIE_I_VOZBUD,0); + + + ff = control_station.active_array_cmd[CONTROL_STATION_CMD_SET_U_ZARYAD]; + + edrk.zadanie.ZadanieU_Charge = my_satur_float(ff,MAX_ZADANIE_U_CHARGE,0,0); + edrk.zadanie.iq_ZadanieU_Charge = _IQ(edrk.zadanie.ZadanieU_Charge/NORMA_ACP); + + + if (edrk.Status_Ready.bits.ready_final==0) + { + // , + for (i=0;idigit_data.Byte01.bit_data.bit0 && flag_wait_revers_go) + edrk.StartGEDRS = 0; + if (pcommand->digit_data.Byte01.bit_data.bit0==0) + edrk.StartGEDRS = 0; + if (pcommand->digit_data.Byte01.bit_data.bit0==0 && flag_wait_revers_go) + flag_wait_revers_go = 0; + if (pcommand->digit_data.Byte01.bit_data.bit0==1 && flag_wait_revers_go==0) + edrk.StartGEDRS = 1; + +// edrk.StartGEDRS = pcommand->digit_data.Byte01.bit_data.bit0; +*/ +// end StartGED + + + + +//////////////// + + + + +// edrk.from_rs.bits.RAZBOR_SHEMA = pcommand->digit_data.Byte01.bit_data.bit5; + + + +// SBOR SHEMA +/* + if (edrk.summ_errors) + { + flag_wait_revers_sbor = 1; + } + + if (flag_wait_revers_sbor==1) + edrk.from_can.bits.SBOR_SHEMA = 0; + + if (pcommand->digit_data.Byte01.bit_data.bit4 && flag_wait_revers_sbor) + edrk.from_can.bits.SBOR_SHEMA = 0; + + if (pcommand->digit_data.Byte01.bit_data.bit4==0) + edrk.from_can.bits.SBOR_SHEMA = 0; + + if (pcommand->digit_data.Byte01.bit_data.bit4==0 && flag_wait_revers_sbor) + flag_wait_revers_sbor = 0; + + if (pcommand->digit_data.Byte01.bit_data.bit4==1 && flag_wait_revers_sbor==0) + edrk.from_can.bits.SBOR_SHEMA = pcommand->digit_data.Byte01.bit_data.bit4; + + prev_byte01_bit4 = pcommand->digit_data.Byte01.bit_data.bit4; +*/ +// end SBOR SHEMA + + + + + +// if (edrk.from_rs.bits.RAZBOR_SHEMA) + // edrk.from_rs.bits.SBOR_SHEMA = 0; + + //edrk.SborRS = pcommand->digit_data.Byte01.bit_data.bit4; + + +// edrk.to_shema.bits.QTV_ON = pcommand->digit_data.Byte02.bit_data.bit3; + + + + +// edrk.RemouteFromRS = pcommand->digit_data.Byte01.bit_data.bit3; + + + + +// edrk.VozbudOnOffFromRS = pcommand->digit_data.Byte01.bit_data.bit1; +// edrk.enable_set_vozbud = pcommand->digit_data.Byte01.bit_data.bit1; +// edrk.SborRS = pcommand->digit_data.Byte01.bit_data.bit2; +// edrk.RazborRS = pcommand->digit_data.Byte01.bit_data.bit3; +// edrk.DirectOUT = pcommand->digit_data.Byte01.bit_data.bit4; + +// edrk.StartGED = pcommand->digit_data.Byte01.bit_data.bit6; + + +// f.flag_distance = pcommand->digit_data.Byte01.bit_data.bit6; +// f.Set_power = pcommand->digit_data.Byte01.bit_data.bit7; + + + // f.Down50 = pcommand->digit_data.Byte02.bit_data.bit2; +// f.Up50 = pcommand->digit_data.Byte02.bit_data.bit3; +// f.Ciclelog = pcommand->digit_data.Byte02.bit_data.bit4; + + // if (SPEED_SELECT_ZADAT==1) +// f.Provorot = pcommand->digit_data.Byte02.bit_data.bit5; + + + + + + + + + + + + + +} + + + +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +void parse_parameters_from_all_control_station(void) +{ + + parse_parameters_from_one_control_station_terminal_rs232(CONTROL_STATION_TERMINAL_RS232); + parse_parameters_from_one_control_station_terminal_rs232(CONTROL_STATION_TERMINAL_CAN); + load_parameters_from_can_control_station_to_rs232(); + + if (edrk.get_new_data_from_hmi==1) // ? + { + func_unpack_answer_from_Ingeteam(CONTROL_STATION_INGETEAM_PULT_RS485); + parse_parameters_from_one_control_station_pult_ingeteam(CONTROL_STATION_INGETEAM_PULT_RS485); + edrk.get_new_data_from_hmi = 2; // modbus + } + parse_parameters_from_one_control_station_pult_zadat4ik(CONTROL_STATION_ZADATCHIK_CAN); + parse_parameters_from_one_control_station_pult_vpu(CONTROL_STATION_VPU_CAN); + parse_parameters_from_one_control_station_another_bs(CONTROL_STATION_ANOTHER_BS); +// unpack_answer_from_MPU_SVU_CAN(CONTROL_STATION_MPU_SVU_CAN); + unpack_answer_from_MPU_SVU_CAN(CONTROL_STATION_MPU_KEY_CAN); //4 + unpack_answer_from_MPU_SVU_CAN(CONTROL_STATION_MPU_SVU_CAN); //3 +// unpack_answer_from_MPU_SVU_RS(CONTROL_STATION_MPU_SVU_RS485); + parse_parameters_from_one_control_station_MPU_SVU(CONTROL_STATION_MPU_SVU_CAN); //3 + parse_parameters_from_one_control_station_MPU_SVU(CONTROL_STATION_MPU_KEY_CAN); //4 +// parse_parameters_from_one_control_station_MPU_SVU(CONTROL_STATION_MPU_SVU_RS485); + + +} + +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +void load_parameters_from_active_control_station(int current_control) +{ + int i; + + if (current_control>=CONTROL_STATION_LAST || current_control<0 ) + { + // - ! ! + for (i=0;i0 + CONTROL_STATION_CMD_SET_K_PLUS_U_DISBALANCE, //kplus_u_disbalance, =0, , . , <>0 . + CONTROL_STATION_CMD_MODE_PUMP, // // // 0 - auto on - rand pump + // 1 - auto on 1 pump + // 2 - auto on 2 pump + // 3 - manual on 1 pump + // 4 - manual on 2 pump + // 5- manual + CONTROL_STATION_CMD_DISABLE_ON_PUMP, + CONTROL_STATION_CMD_ENABLE_ON_CHARGE, + CONTROL_STATION_CMD_DISABLE_ON_QTV, + CONTROL_STATION_CMD_MANUAL_DISCHARGE, + CONTROL_STATION_CMD_DISABLE_ON_UMP, + CONTROL_STATION_CMD_WDOG_OFF, + CONTROL_STATION_CMD_SET_LIMIT_POWER,// + CONTROL_STATION_CMD_BLOCK_BS, // + CONTROL_STATION_CMD_DISABLE_INTERRUPT_SYNC, + CONTROL_STATION_CMD_DISABLE_INTERRUPT_TIMER2, + CONTROL_STATION_CMD_DISABLE_RASCEPITEL, // , + CONTROL_STATION_CMD_PWM_TEST_LINES, // 96 , !!! + CONTROL_STATION_CMD_STOP_LOGS, // + CONTROL_STATION_CMD_LAST // , , , . +}; + + +void control_station_test_alive_all_control(void); +int control_station_select_active(void); +int get_current_station_control(void); +void load_parameters_from_active_control_station(int current_control); +void parse_parameters_from_all_control_station(void); +void parse_parameters_from_one_control_station_terminal_rs232(int cc); +void parse_parameters_from_one_control_station_pult_ingeteam(int cc); +void parse_parameters_from_one_control_station_pult_zadat4ik(int cc); +void parse_parameters_from_one_control_station_pult_vpu(int cc); +void parse_parameters_from_one_control_station_another_bs(int cc); +void parse_parameters_from_one_control_station_MPU_SVU(int cc); + +void parse_analog_data_from_active_control_station_to_alg(void); +void parse_data_from_master_to_alg(void); + +void load_parameters_from_can_control_station_to_rs232(void); + + +#endif /* SRC_MAIN_CONTROL_STATION_PROJECT_H_ */ diff --git a/Inu/Src2/551/main/detect_error_3_phase.c b/Inu/Src2/551/main/detect_error_3_phase.c new file mode 100644 index 0000000..9b6fd87 --- /dev/null +++ b/Inu/Src2/551/main/detect_error_3_phase.c @@ -0,0 +1,167 @@ +/* + * detect_error_3_phase.c + * + * Created on: 7 . 2020 . + * Author: star + */ + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "IQmathLib.h" + + +#include +#include + +#include "global_time.h" + +static int detect_system_asymmetry(DETECT_PROTECT_3_PHASE *v); +static int detect_system_asymmetry_rms(DETECT_PROTECT_3_PHASE *v); + +int detect_error_3_phase(DETECT_PROTECT_3_PHASE *v) { + int err = 0; + int asymmetry = 0; + int break_channel = 0; + + v->errors.all = 0; + v->over_limit.all = 0; + if (v->setup.timers_inited == 0) { + v->setup.timers_inited = 1; + init_timer_milisec(&v->timer_low_minus_10); + init_timer_milisec(&v->timer_low_minus_20); + init_timer_milisec(&v->timer_high_plus_10); + init_timer_milisec(&v->timer_high_plus_20); + } + + if (v->setup.use.bits.phase_U != 0 && + v->iqVal_U > v->setup.levels.iqVal_U_max) { + v->errors.bits.phase_U_max = 1; + v->over_limit.bits.phase_U_max = 1; + err = 1; + } + if (v->setup.use.bits.phase_V != 0 && + v->iqVal_V > v->setup.levels.iqVal_V_max) { + v->errors.bits.phase_V_max = 1; + v->over_limit.bits.phase_V_max = 1; + err = 1; + } + if (v->setup.use.bits.phase_W != 0 && + v->iqVal_W > v->setup.levels.iqVal_W_max) { + v->errors.bits.phase_W_max = 1; + v->over_limit.bits.phase_W_max = 1; + err = 1; + } + //-------------------------------------------------------------------------// + if (v->setup.use.bits.module) { + if (v->iqVal_mod > v->setup.levels.iqVal_module_max) { + v->errors.bits.module_max = 1; + v->over_limit.bits.module_max = 1; + err = 1; + } + } + //-------------------------------------------------------------------------// + if (v->setup.use.bits.detect_minus_10 != 0) { + if (v->iqVal_mod < v->setup.levels.iqNominal_minus10) { + if (detect_pause_milisec(PAUSE_VAL_MINIS_10_S, &v->timer_low_minus_10)){ + v->errors.bits.module_10_percent_low = 1; + err = 1; + } + v->over_limit.bits.module_10_percent_low = 1; + } else { + init_timer_milisec(&v->timer_low_minus_10); + } + v->new_timer_low_minus_10 = v->timer_low_minus_10; + } + + if (v->setup.use.bits.detect_minus_20 != 0) { + if (v->iqVal_mod < v->setup.levels.iqNominal_minus20) { + if (detect_pause_milisec(PAUSE_VAL_MINIS_20_S, &v->timer_low_minus_20)) { + v->errors.bits.module_20_percent_low = 1; + err = 1; + } + v->over_limit.bits.module_20_percent_low = 1; + } else { + init_timer_milisec(&v->timer_low_minus_20); + } + v->new_timer_low_minus_20 = v->timer_low_minus_20; + } + + if (v->setup.use.bits.detect_plus_10 != 0) { + if (v->iqVal_mod > v->setup.levels.iqNominal_plus10) { + if (detect_pause_milisec(PAUSE_VAL_PLUS_10_S, &v->timer_high_plus_10)) { + v->errors.bits.module_10_percent_hi = 1; + err = 1; + } + v->over_limit.bits.module_10_percent_hi = 1; + } else { + init_timer_milisec(&v->timer_high_plus_10); + } + v->new_timer_high_plus_10 = v->timer_high_plus_10; + } + + if (v->setup.use.bits.detect_plus_20 != 0) { + if (v->iqVal_mod > v->setup.levels.iqNominal_plus20) { + if (detect_pause_milisec(PAUSE_VAL_PLUS_20_S, &v->timer_high_plus_20)) { + v->errors.bits.module_20_percent_hi = 1; + err = 1; + } + v->over_limit.bits.module_20_percent_hi = 1; + } else { + init_timer_milisec(&v->timer_high_plus_20); + } + v->new_timer_high_plus_20 = v->timer_high_plus_20; + } + // 3- . 3- 0 + if (v->setup.use.bits.system_asymmetry_by_summ != 0) { + asymmetry = detect_system_asymmetry(v); + if (asymmetry != 0) { + v->errors.bits.system_asymmetry = 1; + err = 1; + } + } + // 3- . 3- + if (v->setup.use.bits.system_asymmetry_by_delta != 0) { + asymmetry = detect_system_asymmetry_rms(v); + if (asymmetry != 0) { + v->errors.bits.system_asymmetry = 1; + err = 1; + } + } + // . , + if (v->setup.use.bits.break_phase != 0 && v->break_phase != 0) { + v->break_phase->iqIu = v->iqVal_U; + v->break_phase->iqIv = v->iqVal_V; + v->break_phase->iqIw = v->iqVal_W; + v->break_phase->iqImod = v->iqVal_mod; + v->break_phase->teta = v->iqTeta; + break_channel = v->break_phase->calc(v->break_phase); + if (break_channel) { + v->errors.bits.break_phase = 1; + err = 1; + switch (break_channel) { + case 1: v->errors.bits.break_phase_U = 1; break; + case 2: v->errors.bits.break_phase_V = 1; break; + case 3: v->errors.bits.break_phase_W = 1; break; + default: break; + } + } + } + + + return err; +} + +int detect_system_asymmetry(DETECT_PROTECT_3_PHASE *v) { + _iq sum = v->iqVal_U + v->iqVal_V + v->iqVal_W; + return _IQabs(sum) > v->setup.levels.iqAsymmetry_delta ? 1 : 0; +} + +int detect_system_asymmetry_rms(DETECT_PROTECT_3_PHASE *v) { + _iq d1 = _IQabs(v->iqVal_U - v->iqVal_V); + _iq d2 = _IQabs(v->iqVal_V - v->iqVal_W); + _iq d3 = _IQabs(v->iqVal_U - v->iqVal_W); + return d1 > v->setup.levels.iqAsymmetry_delta || + d2 > v->setup.levels.iqAsymmetry_delta || + d3 > v->setup.levels.iqAsymmetry_delta ? 1 : 0; +} + diff --git a/Inu/Src2/551/main/detect_error_3_phase.h b/Inu/Src2/551/main/detect_error_3_phase.h new file mode 100644 index 0000000..bdb7307 --- /dev/null +++ b/Inu/Src2/551/main/detect_error_3_phase.h @@ -0,0 +1,148 @@ +/* + * detect_error_3_phase.h + * + * Created on: 7 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_DETECT_ERROR_3_PHASE_H_ +#define SRC_MAIN_DETECT_ERROR_3_PHASE_H_ + +#include + +typedef struct { + _iq iqVal_module_max; + _iq iqVal_U_max; + _iq iqVal_V_max; + _iq iqVal_W_max; + _iq iqNominal_plus10; + _iq iqNominal_plus20; + _iq iqNominal_minus10; + + _iq iqNominal_minus20; + _iq iqAsymmetry_delta; +} PROTECT_LEVELS_3_PHASE; + +#define PROTECT_LEVELS_3_PHASE_DEFAULTS {0,0,0,0,0,0,0, 0,0} + +typedef struct { + PROTECT_LEVELS_3_PHASE levels; + union { + unsigned int all; + struct { + unsigned int phase_U :1; + unsigned int phase_V :1; + unsigned int phase_W :1; + unsigned int module :1; + + unsigned int detect_minus_10 :1; + unsigned int detect_minus_20 :1; + unsigned int detect_plus_10 :1; + unsigned int detect_plus_20 :1; + + unsigned int system_asymmetry_by_summ :1; // 3- 0 + unsigned int system_asymmetry_by_delta :1; // 3- + unsigned int break_phase :1; + unsigned int reserved :5; + } bits; + } use; + unsigned int timers_inited; +} SETUP_3_PHASE_PROTECT; + +#define SETUP_3_PHASE_PROTECT_DEFAULTS {PROTECT_LEVELS_3_PHASE_DEFAULTS, {0}, 0} + +typedef struct { + //In values + _iq iqVal_U; + _iq iqVal_V; + _iq iqVal_W; + _iq iqVal_mod; + _iq iqTeta; // + + unsigned int timer_low_minus_10; + unsigned int timer_low_minus_20; + unsigned int timer_high_plus_10; + unsigned int timer_high_plus_20; + + //Break phase I state values + BREAK_PHASE_I *break_phase; + + //Out values + union { + unsigned int all; + struct { + unsigned int phase_U_max :1; + unsigned int phase_V_max :1; + unsigned int phase_W_max :1; + unsigned int module_max :1; + unsigned int module_10_percent_hi :1; + unsigned int module_20_percent_hi :1; + unsigned int module_10_percent_low :1; + unsigned int module_20_percent_low :1; + + unsigned int system_asymmetry :1; + unsigned int break_phase :1; + unsigned int break_phase_U :1; + unsigned int break_phase_V :1; + unsigned int break_phase_W :1; + unsigned int reserved :3; + + } bits; + } errors; + union { + unsigned int all; + struct { + unsigned int phase_U_max :1; + unsigned int phase_V_max :1; + unsigned int phase_W_max :1; + unsigned int module_max :1; + unsigned int module_10_percent_hi :1; + unsigned int module_20_percent_hi :1; + unsigned int module_10_percent_low :1; + unsigned int module_20_percent_low :1; + + unsigned int system_asymmetry_by_summ :1; + unsigned int break_phase :1; + unsigned int break_phase_U :1; + unsigned int break_phase_V :1; + unsigned int break_phase_W :1; + unsigned int reserved :3; + + } bits; + } over_limit; + unsigned int new_timer_low_minus_10; + unsigned int new_timer_low_minus_20; + unsigned int new_timer_high_plus_10; + unsigned int new_timer_high_plus_20; + + //Setup + SETUP_3_PHASE_PROTECT setup; + + int (*calc_detect_error_3_phase)(); + +} DETECT_PROTECT_3_PHASE; + +#define DETECT_PROTECT_3_PHASE_DEFAULTS {0,0,0,0,0, 0,0,0,0, 0, {0},{0}, 0,0,0,0,\ + SETUP_3_PHASE_PROTECT_DEFAULTS, \ + detect_error_3_phase} + + +#define ADC_PROTECT_LEVELS_DEFAULT {0,0,0,0, 0,0,0,0, 0} + +#define PAUSE_VAL_MINIS_10_S 10000 +#define PAUSE_VAL_MINIS_20_S 1000 +#define PAUSE_VAL_PLUS_10_S 10000 +#define PAUSE_VAL_PLUS_20_S 1000 + +#define PLUS_10_PERCENT 1.1 +#define PLUS_20_PERCENT 1.2 +#define MINUS_10_PERCENT 0.9 +#define MINUS_20_PERCENT 0.8 +#define ASYMMETRY_DELTA_PERCENTS 0.2 + +int detect_error_3_phase(DETECT_PROTECT_3_PHASE *v); + + + + +#endif /* SRC_MAIN_DETECT_ERROR_3_PHASE_H_ */ diff --git a/Inu/Src2/551/main/detect_errors.c b/Inu/Src2/551/main/detect_errors.c new file mode 100644 index 0000000..07ff17c --- /dev/null +++ b/Inu/Src2/551/main/detect_errors.c @@ -0,0 +1,1606 @@ +/* + * detect_errors.c + * + * Created on: 4 . 2020 . + * Author: star + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "v_rotor.h" + + +#include "control_station.h" +#include "DSP281x_Device.h" +#include "master_slave.h" +#include "another_bs.h" +#include "digital_filters.h" + + +void detect_error_from_knopka_avaria(void); +void detect_error_ute4ka_water(void); +void detect_error_t_vipr(void); +void detect_error_power_upc(void); +void detect_error_op_pit(void); +void detect_error_p_water(void); +void detect_error_pump_2(void); +void detect_error_pump_1(void); +void detect_error_pre_ready_pump(void); +void detect_error_fan(void); +void detect_error_block_qtv_from_svu(void); + +void detect_error_predohr_vipr(void); +void detect_error_qtv(void); +void detect_error_pre_charge(void); +void detect_error_block_izol(void); +void detect_error_nagrev(void); +void detect_error_ground(void); +void detect_error_block_door(void); +void detect_error_optical_bus(void); +void detect_error_sync_bus(void); +int get_status_temper_acdrive_winding(int nc); +int get_status_temper_acdrive_winding_with_limits(int nc, int alarm, int abnormal); +int get_status_temper_acdrive_bear(int nc); +int get_status_temper_acdrive_bear_with_limits(int nc, int alarm, int abnormal); +int get_status_temper_air(int nc); +int get_status_temper_air_with_limits(int nc, int alarm, int abnormal); +int get_status_temper_u(int nc); +int get_status_temper_u_with_limits(int nc, int alarm, int abnormal); +int get_status_temper_water(int nc); +int get_status_p_water_max(void); +int get_status_p_water_min(int pump_on_off); +void detect_error_t_water(void); +void detect_error_t_air(void); +void detect_error_t_u(void); +void detect_error_acdrive_winding(void); + +int get_common_state_warning(void); +int get_common_state_overheat(void); +void detect_error_sensor_rotor(void); + + + + +#pragma DATA_SECTION(protect_levels,".slow_vars"); +PROTECT_LEVELS protect_levels = PROTECT_LEVELS_DEFAULTS; + + + + +/////////////////////////////////////////////// +int get_status_temper_acdrive_winding(int nc) +{ + if (edrk.temper_acdrive.winding.filter_real_int_temper[nc]>=ALARM_TEMPER_ACDRIVE_WINDING) + return 4; + if (edrk.temper_acdrive.winding.filter_real_int_temper[nc]>=ABNORMAL_TEMPER_ACDRIVE_WINDING) + return 2; + return 1; +} + +int get_status_temper_acdrive_winding_with_limits(int nc, int alarm, int abnormal) +{ + if (edrk.temper_acdrive.winding.filter_real_int_temper[nc]>=alarm) + return 4; + if (edrk.temper_acdrive.winding.filter_real_int_temper[nc]>=abnormal) + return 2; + return 1; +} +/////////////////////////////////////////////// +int get_status_temper_acdrive_bear(int nc) +{ + + if (edrk.temper_acdrive.bear.filter_real_int_temper[nc]>=ALARM_TEMPER_ACDRIVE_WINDING) + return 4; + if (edrk.temper_acdrive.bear.filter_real_int_temper[nc]>=ABNORMAL_TEMPER_ACDRIVE_WINDING) + return 2; + return 1; +} + +int get_status_temper_acdrive_bear_with_limits(int nc, int alarm, int abnormal) +{ + + if (edrk.temper_acdrive.bear.filter_real_int_temper[nc]>=alarm) + return 4; + if (edrk.temper_acdrive.bear.filter_real_int_temper[nc]>=abnormal) + return 2; + return 1; +} + +/////////////////////////////////////////////// +int get_status_temper_air(int nc) +{ + if (edrk.temper_edrk.real_int_temper_air[nc]>=ALARM_TEMPER_AIR_INT) + return 4; + if (edrk.temper_edrk.real_int_temper_air[nc]>=ABNORMAL_TEMPER_AIR_INT) + return 2; + return 1; +} + +int get_status_temper_air_with_limits(int nc, int alarm, int abnormal) +{ + if (edrk.temper_edrk.real_int_temper_air[nc]>=alarm) + return 4; + if (edrk.temper_edrk.real_int_temper_air[nc]>=abnormal) + return 2; + return 1; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +int get_status_temper_u(int nc) +{ + if (edrk.temper_edrk.real_int_temper_u[nc]>=ALARM_TEMPER_AF) + return 4; + if (edrk.temper_edrk.real_int_temper_u[nc]>=ABNORMAL_TEMPER_AF) + return 2; + return 1; +} + +int get_status_temper_u_with_limits(int nc, int alarm, int abnormal) +{ + if (edrk.temper_edrk.real_int_temper_u[nc]>=alarm) + return 4; + if (edrk.temper_edrk.real_int_temper_u[nc]>=abnormal) + return 2; + return 1; +} + +/////////////////////////////////////////////// +int get_status_temper_water(int nc) +{ + + if (nc==INDEX_T_WATER_EXT) // ext + { + if (edrk.temper_edrk.real_int_temper_water[nc]>=protect_levels.alarm_temper_water_ext) + return 4; + if (edrk.temper_edrk.real_int_temper_water[nc]>=protect_levels.abnormal_temper_water_ext) + return 2; + return 1; + } + + if (nc==INDEX_T_WATER_INT) // int + { + if (edrk.temper_edrk.real_int_temper_water[nc]>=protect_levels.alarm_temper_water_int) + return 4; + if (edrk.temper_edrk.real_int_temper_water[nc]>=protect_levels.abnormal_temper_water_int) + return 2; + return 1; + } + + return 0; +} + +/////////////////////////////////////////////// +int get_status_p_water_max(void) +{ + if (edrk.p_water_edrk.filter_real_int_p_water[0]>=protect_levels.alarm_p_water_max_int) + return 4; + if (edrk.p_water_edrk.filter_real_int_p_water[0]>=protect_levels.abnormal_p_water_max_int) + return 2; + return 1; +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// +int get_status_p_water_min(int pump_on_off) +{ + if (pump_on_off == 0) + { + if (edrk.p_water_edrk.filter_real_int_p_water[0]<=ALARM_P_WATER_MIN_INT_ON_OFF_PUMP) + return 4; + if (edrk.p_water_edrk.filter_real_int_p_water[0]<=ABNORMAL_P_WATER_MIN_INT_ON_OFF_PUMP) + return 2; + return 1; + } + + if (pump_on_off == 1) + { + if (edrk.p_water_edrk.filter_real_int_p_water[0]<=protect_levels.alarm_p_water_min_int) + return 4; + if (edrk.p_water_edrk.filter_real_int_p_water[0]<=protect_levels.abnormal_p_water_min_int) + return 2; + return 1; + } + return 0; +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void detect_error_sensor_rotor(void) +{ + static unsigned int count_err1 = 0, count_err2 = 0, count_err3 = 0, count_err4 = 0; + + + if (edrk.Go) + { + // ? + if (edrk.iq_f_rotor_hz==0) + { + // ! + if (pause_detect_error(&count_err3,TIME_WAIT_SENSOR_ROTOR_BREAK_ALL,1)) + { + edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 1; + edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 1; + //edrk.errors.e9.bits.SENSOR_ROTOR_1_2_BREAK |= 1; // ! + } + else + { +// edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 0; +// edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 0; + edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = pause_detect_error(&count_err1,TIME_WAIT_SENSOR_ROTOR_BREAK_ONE_SENSOR, + inc_sensor.break_sensor1); + edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = pause_detect_error(&count_err2,TIME_WAIT_SENSOR_ROTOR_BREAK_ONE_SENSOR, + inc_sensor.break_sensor2); + } + } + else + { + count_err3 = 0; +// edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 0; +// edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 0; + edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK |= pause_detect_error(&count_err1,TIME_WAIT_ERROR,inc_sensor.break_sensor1); + edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK |= pause_detect_error(&count_err2,TIME_WAIT_ERROR,inc_sensor.break_sensor2); + + } + } + else + { + + count_err1 = count_err2 = 0; + count_err3 = 0; + + edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 0; + edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 0; + } + +} +/////////////////////////////////////////////// +#define TIME_WAIT_T_WATER 30 +void detect_error_t_water(void) +{ + static unsigned int count_run = 0, count_run_static = 0; + int status; + + status = get_status_temper_water(INDEX_T_WATER_INT); + if (status==4) + edrk.errors.e2.bits.T_WATER_INT_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_WATER_INT_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_WATER_INT_MAX = 0; + + status = get_status_temper_water(INDEX_T_WATER_EXT); + if (status==4) + edrk.errors.e2.bits.T_WATER_EXT_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_WATER_EXT_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_WATER_EXT_MAX = 0; + +} +/////////////////////////////////////////////// + +void detect_error_t_air(void) +{ + static unsigned int count_run = 0, count_run_static = 0; + int status,i; + + + status = get_status_temper_air_with_limits(0, protect_levels.alarm_temper_air_int_01, + protect_levels.abnormal_temper_air_int_01); + if (status==4) + edrk.errors.e2.bits.T_AIR0_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_AIR0_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_AIR0_MAX = 0; + + + status = get_status_temper_air_with_limits(1, protect_levels.alarm_temper_air_int_02, + protect_levels.abnormal_temper_air_int_02); + if (status==4) + edrk.errors.e2.bits.T_AIR1_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_AIR1_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_AIR1_MAX = 0; + + + status = get_status_temper_air_with_limits(2, protect_levels.alarm_temper_air_int_03, + protect_levels.abnormal_temper_air_int_03); + if (status==4) + edrk.errors.e2.bits.T_AIR2_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_AIR2_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_AIR2_MAX = 0; + + + status = get_status_temper_air_with_limits(3, protect_levels.alarm_temper_air_int_04, + protect_levels.abnormal_temper_air_int_04); + if (status==4) + edrk.errors.e2.bits.T_AIR3_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_AIR3_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_AIR3_MAX = 0; +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +void detect_error_t_u(void) +{ + static unsigned int count_run = 0, count_run_static = 0; + int status,i; + + + status = get_status_temper_u_with_limits(0, protect_levels.alarm_temper_u_01, + protect_levels.abnormal_temper_u_01); + if (status == 4) + edrk.errors.e2.bits.T_UO1_MAX |= 1; + if (status == 2) + edrk.warnings.e2.bits.T_UO1_MAX = 1; + if (status == 1) + edrk.warnings.e2.bits.T_UO1_MAX = 0; + + status = get_status_temper_u_with_limits(1, protect_levels.alarm_temper_u_02, + protect_levels.abnormal_temper_u_02); + if (status==4) + edrk.errors.e2.bits.T_UO2_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_UO2_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_UO2_MAX = 0; + + status = get_status_temper_u_with_limits(2, protect_levels.alarm_temper_u_03, + protect_levels.abnormal_temper_u_03); + if (status==4) + edrk.errors.e2.bits.T_UO3_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_UO3_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_UO3_MAX = 0; + + status = get_status_temper_u_with_limits(3, protect_levels.alarm_temper_u_04, + protect_levels.abnormal_temper_u_04); + if (status==4) + edrk.errors.e2.bits.T_UO4_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_UO4_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_UO4_MAX = 0; + + status = get_status_temper_u_with_limits(4, protect_levels.alarm_temper_u_05, + protect_levels.abnormal_temper_u_05); + if (status==4) + edrk.errors.e2.bits.T_UO5_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_UO5_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_UO5_MAX = 0; + + status = get_status_temper_u_with_limits(5, protect_levels.alarm_temper_u_06, + protect_levels.abnormal_temper_u_06); + if (status==4) + edrk.errors.e2.bits.T_UO6_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_UO6_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_UO6_MAX = 0; + + status = get_status_temper_u_with_limits(6, protect_levels.alarm_temper_u_07, + protect_levels.abnormal_temper_u_07); + if (status==4) + edrk.errors.e2.bits.T_UO7_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.T_UO7_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.T_UO7_MAX = 0; + +} + +void detect_error_t_bsu(void) { + +} +/////////////////////////////////////////////// +void detect_error_acdrive_winding(void) +{ +// static unsigned int count_run = 0, count_run_static = 0; + int status, i; + + status = 0; + status |= get_status_temper_acdrive_winding_with_limits( + 0, protect_levels.alarm_temper_acdrive_winding_U1, + protect_levels.abnormal_temper_acdrive_winding_U1); + if (status == 4) { + edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1 = 1; + } + if (status == 2) { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1 = 1; + } else { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1 = 0; + } + + status = 0; + status |= get_status_temper_acdrive_winding_with_limits( + 1, protect_levels.alarm_temper_acdrive_winding_V1, + protect_levels.abnormal_temper_acdrive_winding_V1); + if (status == 4) { + edrk.errors.e10.bits.T_ACDRIVE_WINDING_V1 = 1; + } + if (status == 2) { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1 = 1; + } else { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1 = 0; + } + + status = 0; + status |= get_status_temper_acdrive_winding_with_limits( + 2, protect_levels.alarm_temper_acdrive_winding_W1, + protect_levels.abnormal_temper_acdrive_winding_W1); + if (status == 4) { + edrk.errors.e10.bits.T_ACDRIVE_WINDING_W1 = 1; + } + if (status == 2) { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1 = 1; + } else { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1 = 0; + } + + status = 0; + status |= get_status_temper_acdrive_winding_with_limits( + 3, protect_levels.alarm_temper_acdrive_winding_U2, + protect_levels.abnormal_temper_acdrive_winding_U2); + if (status == 4) { + edrk.errors.e10.bits.T_ACDRIVE_WINDING_U2 = 1; + } + if (status == 2) { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2 = 1; + } else { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2 = 0; + } + + status = 0; + status |= get_status_temper_acdrive_winding_with_limits( + 4, protect_levels.alarm_temper_acdrive_winding_V2, + protect_levels.abnormal_temper_acdrive_winding_V2); + if (status == 4) { + edrk.errors.e10.bits.T_ACDRIVE_WINDING_V2 = 1; + } + if (status == 2) { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2 = 1; + } else { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2 = 0; + } + + status = 0; + status |= get_status_temper_acdrive_winding_with_limits( + 5, protect_levels.alarm_temper_acdrive_winding_W2, + protect_levels.abnormal_temper_acdrive_winding_W2); + if (status == 4) { + edrk.errors.e10.bits.T_ACDRIVE_WINDING_W2 = 1; + } + if (status == 2) { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2 = 1; + } else { + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2 = 0; + } + + if (edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_V1 || + edrk.errors.e10.bits.T_ACDRIVE_WINDING_W1 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_U2 || + edrk.errors.e10.bits.T_ACDRIVE_WINDING_V2 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_W2) { + edrk.errors.e7.bits.T_ACDRIVE_WINDING_MAX |= 1; + } + if (edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1 || + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2 || + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2) { + edrk.warnings.e7.bits.T_ACDRIVE_WINDING_MAX = 1; + } + else + edrk.warnings.e7.bits.T_ACDRIVE_WINDING_MAX = 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void detect_error_acdrive_bear(void) +{ + static unsigned int count_run = 0, count_run_static = 0; + int status,i; + +// status = 0; + + status = get_status_temper_acdrive_bear_with_limits(0, protect_levels.alarm_temper_acdrive_bear_DNE, + protect_levels.abnormal_temper_acdrive_bear_DNE); + if (status & 4) + edrk.errors.e7.bits.T_ACDRIVE_BEAR_MAX_DNE |= 1; + if (status == 2) + edrk.warnings.e7.bits.T_ACDRIVE_BEAR_MAX_DNE = 1; + if (status == 1) + edrk.warnings.e7.bits.T_ACDRIVE_BEAR_MAX_DNE = 0; + + status = get_status_temper_acdrive_bear_with_limits(1, protect_levels.alarm_temper_acdrive_bear_NE, + protect_levels.abnormal_temper_acdrive_bear_NE); + if (status & 4) + edrk.errors.e9.bits.T_ACDRIVE_BEAR_MAX_NE |= 1; + if (status == 2) + edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE = 1; + if (status == 1) + edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE = 0; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +#define TIME_WAIT_RUN_PUMP 100 //50 +void detect_error_p_water(void) +{ + static unsigned int count_run = 0, count_run_static = 0; + int status,i; + + if (edrk.from_ing1.bits.NASOS_ON == 1) + { + if (pause_detect_error(&count_run,TIME_WAIT_RUN_PUMP,1)) + { + status = get_status_p_water_max(); + + if (status & 4) + edrk.errors.e2.bits.P_WATER_INT_MAX |= 1; + if (status==2) + edrk.warnings.e2.bits.P_WATER_INT_MAX = 1; + if (status==1) + edrk.warnings.e2.bits.P_WATER_INT_MAX = 0; + + status = get_status_p_water_min(1); + + if (status & 4) + edrk.errors.e2.bits.P_WATER_INT_MIN |= 1; + if (status==2) + edrk.warnings.e2.bits.P_WATER_INT_MIN = 1; + if (status==1) + edrk.warnings.e2.bits.P_WATER_INT_MIN = 0; + + } + } + else + count_run = 0; + + + // test if nasos off + status = get_status_p_water_min(0); + if (status>1) + { + if (pause_detect_error(&count_run_static,TIME_WAIT_RUN_PUMP,1)) + { + if (status==4) + { + if (control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_PUMP]==0) + edrk.errors.e2.bits.P_WATER_INT_MIN |= 1; + } + if (status==2) + edrk.warnings.e2.bits.P_WATER_INT_MIN = 1; + } + } + else + { + count_run_static = 0; + edrk.warnings.e2.bits.P_WATER_INT_MIN = 0; + } + +} + +/////////////////////////////////////////////// + +/////////////////////////////////////////////// + +void detect_error_ground(void) +{ + static unsigned int count_err = 0; + + + if (edrk.from_ing1.bits.ZAZEML_OFF == 0) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1)) + edrk.errors.e5.bits.ERROR_GROUND_NET |= 1; + } + + if (edrk.from_ing1.bits.ZAZEML_ON == 1) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1)) + edrk.errors.e5.bits.ERROR_GROUND_NET |= 1; + } + + if ((edrk.from_ing1.bits.ZAZEML_OFF == 1) && (edrk.from_ing1.bits.ZAZEML_ON == 0)) + count_err = 0; + +} + +/////////////////////////////////////////////// +void detect_error_nagrev(void) +{ + + static unsigned int count_err = 0; + + if (edrk.from_ing1.bits.NAGREV_ON == edrk.to_ing.bits.NAGREV_OFF) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1)) + edrk.errors.e5.bits.ERROR_HEAT |= 1; + } + else + count_err = 0; + + +} +/////////////////////////////////////////////// +#define TIME_WAIT_ERROR_BLOCK_DOOR 30 //20 +void detect_error_block_door(void) +{ + static unsigned int count_err = 0; + + if ((edrk.from_ing2.bits.SOST_ZAMKA == 1 && edrk.to_ing.bits.BLOCK_KEY_OFF==1) + || (edrk.from_ing2.bits.SOST_ZAMKA == 0 && edrk.to_ing.bits.BLOCK_KEY_OFF==0)) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_BLOCK_DOOR,1)) + edrk.errors.e1.bits.BLOCK_DOOR |= 1; + } + else + count_err = 0; + +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void detect_error_block_izol(void) +{ + static unsigned int count_err = 0; + + if (edrk.from_ing1.bits.BLOCK_IZOL_AVARIA == 1 ) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_IZOL,1)) + edrk.errors.e5.bits.ERROR_ISOLATE |= 1; + } + + if (edrk.from_ing1.bits.BLOCK_IZOL_AVARIA == 0 && edrk.from_ing1.bits.BLOCK_IZOL_NORMA == 0 ) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_IZOL,1)) + edrk.warnings.e5.bits.ERROR_ISOLATE |= 1; + } + else + edrk.warnings.e5.bits.ERROR_ISOLATE = 0; + + if (edrk.from_ing1.bits.BLOCK_IZOL_AVARIA == 0 && edrk.from_ing1.bits.BLOCK_IZOL_NORMA == 1 ) + { + count_err = 0; + } + + if (edrk.cmd_imit_low_isolation) + edrk.errors.e5.bits.ERROR_ISOLATE |= 1; + +} + +/////////////////////////////////////////////// +void detect_error_pre_charge(void) +{ + static unsigned int count_err = 0; + + if (edrk.from_ing1.bits.ZARYAD_ON == 1 && edrk.to_ing.bits.ZARYAD_ON == 0) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_CHARGE_ANSWER,1)) + edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER |= 1; + } + + if (edrk.from_ing1.bits.ZARYAD_ON == 0 && edrk.to_ing.bits.ZARYAD_ON == 1) + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_CHARGE_ANSWER,1)) + edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER |= 1; + + + if (edrk.from_ing1.bits.ZARYAD_ON == 0 && edrk.to_ing.bits.ZARYAD_ON == 0) + count_err = 0; + + +// edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER |= 1; +// edrk.errors.e6.bits.ERROR_PRE_CHARGE_U |= 1; +} + +/////////////////////////////////////////////// +void detect_error_qtv(void) +{ + static unsigned int count_err_off = 0; + static unsigned int count_err_on = 0; + + + // , + if (edrk.from_shema_filter.bits.QTV_ON_OFF == 1 && edrk.cmd_to_qtv == 0) + { + if (pause_detect_error(&count_err_off,TIME_WAIT_ERROR_QTV,1)) + edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER |= 1; + } + else + { + count_err_off = 0; + } + +// , + if (edrk.from_shema_filter.bits.QTV_ON_OFF == 0 && edrk.cmd_to_qtv == 1) + { + if (pause_detect_error(&count_err_on,TIME_WAIT_ERROR_QTV,1)) + edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER |= 1; + } + else + { + count_err_on = 0; + } + +// +// if (edrk.from_shema.bits.QTV_ON_OFF == 0 && edrk.cmd_to_qtv == 0) +// count_err = 0; + +// edrk.errors.e6.bits.QTV_ERROR_NOT_U |= 1; + +// edrk.errors.e6.bits.QTV_ERROR_NOT_U |= detect_error_u_zpt(); + edrk.errors.e6.bits.QTV_ERROR_NOT_U |= detect_error_u_in(); +// edrk.errors.e6.bits.QTV_ERROR_NOT_U |= detect_error_u_zpt_on_predzaryad(); +} + +/////////////////////////////////////////////// +void detect_error_predohr_vipr(void) +{ + static unsigned int count_err = 0; + + if (edrk.from_ing1.bits.VIPR_PREDOHR_NORMA == 0) + if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1)) + edrk.errors.e5.bits.ERROR_PRED_VIPR |= 1; + + if (edrk.from_ing1.bits.VIPR_PREDOHR_NORMA == 1) + count_err = 0; +} + +/////////////////////////////////////////////// +#define TIME_WAIT_ERROR_UMP_READY 1200 //120 //750 // 75 .. +#define TIME_WAIT_WARNING_UMP_READY 10 +void detect_error_ump(void) +{ + static unsigned int count_err = 0; + static unsigned int count_err2 = 0; + + static unsigned int prev_SumSbor = 0; + static unsigned int StageUMP = 0; + static unsigned int count_UMP_NOT_READY = 0; + int local_warning_ump = 0; + + if (edrk.SumSbor==1) + { + switch (StageUMP) { + case 0: if (edrk.from_shema_filter.bits.UMP_ON_OFF == 1) + StageUMP++; + break; + case 1: if (edrk.from_shema_filter.bits.UMP_ON_OFF == 0) + StageUMP++; + break; + case 2: + break; + case 3: + break; + + + default: break; + } + + if ((edrk.from_shema_filter.bits.READY_UMP == 0) && (StageUMP==0) && control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_UMP]==0) + { + + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_UMP_READY,1)) + edrk.errors.e7.bits.UMP_NOT_READY |= 1; + } + if (edrk.from_shema_filter.bits.READY_UMP == 1) + count_err = 0; + } + else + { + count_err= 0; + + // , ! + if (edrk.from_shema_filter.bits.UMP_ON_OFF==1) + if (pause_detect_error(&count_err2,TIME_WAIT_ERROR,1)) + edrk.errors.e11.bits.ERROR_UMP_NOT_OFF |= 1; + + if (edrk.from_shema_filter.bits.UMP_ON_OFF == 0) + count_err2 = 0; + + // + if (edrk.ump_cmd_another_bs==0) // + local_warning_ump = !edrk.from_shema_filter.bits.READY_UMP; + // edrk.warnings.e7.bits.UMP_NOT_READY = !edrk.from_shema_filter.bits.READY_UMP; + + + + StageUMP = 0; + } + + edrk.warnings.e7.bits.UMP_NOT_READY = filter_digital_input( edrk.warnings.e7.bits.UMP_NOT_READY, + &count_UMP_NOT_READY, + TIME_WAIT_WARNING_UMP_READY, + local_warning_ump); + + prev_SumSbor = edrk.SumSbor; +} + + +#define TIME_WAIT_BLOCK_QTV_FROM_SVU 20 +/////////////////////////////////////////////// +void detect_error_block_qtv_from_svu(void) +{ + static unsigned int count_err = 0; + + + if (edrk.from_shema.bits.SVU_BLOCK_QTV == 1 || control_station.active_array_cmd[CONTROL_STATION_CMD_BLOCK_BS]) + { + if (pause_detect_error(&count_err,TIME_WAIT_BLOCK_QTV_FROM_SVU,1)) + edrk.errors.e7.bits.SVU_BLOCK_ON_QTV |= 1; + } + else + { + count_err = 0; + } + +} + +/////////////////////////////////////////////// +void detect_error_fan(void) +{ + static unsigned int count_err = 0; + + if (edrk.from_ing1.bits.VENTIL_ON == 0 && (edrk.to_ing.bits.NASOS_1_ON || edrk.to_ing.bits.NASOS_2_ON)) + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_FAN,1)) + edrk.errors.e5.bits.FAN |= 1; + + if (edrk.from_ing1.bits.VENTIL_ON == 1 && (edrk.to_ing.bits.NASOS_1_ON == 0 && edrk.to_ing.bits.NASOS_2_ON == 0)) + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_FAN,1)) + edrk.errors.e5.bits.FAN |= 1; + + if (edrk.from_ing1.bits.VENTIL_ON == 0 && (edrk.to_ing.bits.NASOS_1_ON == 0 && edrk.to_ing.bits.NASOS_2_ON == 0)) + count_err = 0; + +} + + + +/////////////////////////////////////////////// +void detect_error_pre_ready_pump(void) +{ + static unsigned int count_err = 0; + + if (edrk.from_ing1.bits.NASOS_NORMA == 0) + if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1)) + { +// edrk.errors.e5.bits.PRE_READY_PUMP |= 1; + edrk.warnings.e5.bits.PRE_READY_PUMP = 1; + } + + if (edrk.from_ing1.bits.NASOS_NORMA == 1) + { + count_err = 0; + edrk.warnings.e5.bits.PRE_READY_PUMP = 0; + } +} +/////////////////////////////////////////////// +void detect_error_pump_1(void) +{ + static unsigned int count_err = 0; + + // , + if (edrk.from_ing1.bits.NASOS_ON == 0 && edrk.to_ing.bits.NASOS_1_ON) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_PUMP,1)) + { +// edrk.errors.e5.bits.PUMP_1 |= 1; + edrk.warnings.e5.bits.PUMP_1 = 1; + } + } + + + // , + if (edrk.from_ing1.bits.NASOS_ON == 1 && edrk.to_ing.bits.NASOS_1_ON==0 && edrk.SelectPump1_2==1) + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_PUMP,1)) + edrk.errors.e5.bits.PUMP_1 |= 1; + + + if (edrk.from_ing1.bits.NASOS_ON == 0 && edrk.to_ing.bits.NASOS_1_ON==0 && edrk.SelectPump1_2==1) + { + // + count_err = 0; + } + + if (edrk.from_ing1.bits.NASOS_ON == 1 && edrk.to_ing.bits.NASOS_1_ON==1 && edrk.SelectPump1_2==1) + { + // + count_err = 0; + edrk.warnings.e5.bits.PUMP_1 = 0; + } + + +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void detect_error_pump_2(void) +{ + static unsigned int count_err = 0; + + // , + if (edrk.from_ing1.bits.NASOS_ON == 0 && edrk.to_ing.bits.NASOS_2_ON) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_PUMP,1)) +// edrk.errors.e5.bits.PUMP_2 |= 1; + edrk.warnings.e5.bits.PUMP_2 = 1; + } + + if (edrk.from_ing1.bits.NASOS_ON == 1 && edrk.to_ing.bits.NASOS_2_ON==0 && edrk.SelectPump1_2==2) + { + if (pause_detect_error(&count_err,TIME_WAIT_ERROR_PUMP,1)) + edrk.errors.e5.bits.PUMP_2 |= 1; + } + + if (edrk.from_ing1.bits.NASOS_ON == 0 && edrk.to_ing.bits.NASOS_2_ON==0 && edrk.SelectPump1_2==2) + { + // + count_err = 0; + } + + if (edrk.from_ing1.bits.NASOS_ON == 1 && edrk.to_ing.bits.NASOS_2_ON==1 && edrk.SelectPump1_2==2) + { + // + count_err = 0; + edrk.warnings.e5.bits.PUMP_2 = 0; + } +} +/////////////////////////////////////////////// + +/////////////////////////////////////////////// +void detect_error_op_pit(void) +{ + static unsigned int count_err = 0; + + if (edrk.from_ing1.bits.OP_PIT_NORMA == 0 ) + if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1)) + edrk.errors.e5.bits.OP_PIT |= 1; + + if (edrk.from_ing1.bits.OP_PIT_NORMA == 1 ) + count_err = 0; +} +/////////////////////////////////////////////// +void detect_error_power_upc(void) +{ + static unsigned int count_err = 0; + + if (edrk.from_ing1.bits.UPC_24V_NORMA == 0 ) + if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1)) + edrk.errors.e5.bits.POWER_UPC |= 1; + + if (edrk.from_ing1.bits.UPC_24V_NORMA == 1 ) + count_err = 0; +} +/////////////////////////////////////////////// +void detect_error_t_vipr(void) +{ + static unsigned int count_err = 0; + +// if (edrk.from_ing.bits.VIPR_TEMPER_OK == 0 ) +// if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1)) +// edrk.errors.e5.bits.T_VIPR_MAX |= 1; +// +// if (edrk.from_ing.bits.VIPR_TEMPER_OK == 1 ) +// pause_detect_error(&count_err,TIME_WAIT_ERROR,0); +} +/////////////////////////////////////////////// +void detect_error_ute4ka_water(void) +{ + static unsigned int count_err = 0; + + if (edrk.from_ing1.bits.OHLAD_UTE4KA_WATER == 1 ) + if (pause_detect_error(&count_err,TIME_WAIT_ERROR,1)) + edrk.errors.e5.bits.UTE4KA_WATER |= 1; + + + if (edrk.from_ing1.bits.OHLAD_UTE4KA_WATER == 0 ) + count_err = 0; +} + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void detect_error_from_knopka_avaria(void) +{ + edrk.errors.e5.bits.KEY_AVARIA |= edrk.from_ing1.bits.ALL_KNOPKA_AVARIA; +} +/////////////////////////////////////////////// +void detect_error_optical_bus(void) +{ +// if () + + + +} + +#define TIME_WAIT_SYNC_SIGNAL 20 // 2 sec +/////////////////////////////////////////////// +void detect_error_sync_bus(void) +{ + static unsigned int count_err = 0; + +// if (sync_data.flag_sync_1_2==0) +// edrk.errors.e7.bits.MASTER_SLAVE_SYNC |= 1; + + if (!edrk.ms.ready1) + { + edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL = 0; + count_err = 0; + return; + } + + // , , + if (sync_data.timeout_sync_signal && optical_read_data.data.cmd.bit.sync_line_detect + && optical_read_data.status==1) + { + edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL = 1; + return; + } + else + edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL = 0; + + + // , , + if (sync_data.timeout_sync_signal && optical_read_data.data.cmd.bit.sync_line_detect==0 + && edrk.ms.another_bs_maybe_on && optical_read_data.status==1) + { + if (pause_detect_error(&count_err,TIME_WAIT_SYNC_SIGNAL,1)) + edrk.errors.e1.bits.NO_INPUT_SYNC_SIGNAL |= 1; + } + else + count_err = 0; + + +} +/////////////////////////////////////////////// +#pragma CODE_SECTION(detect_error_u_zpt_fast,".fast_run"); +int detect_error_u_zpt_fast(void) +{ + int err; + + err = 0; + + + if (analog.iqU_1>=edrk.iqMAX_U_ZPT_Global) + edrk.errors.e0.bits.U_1_MAX |= 1; + + if (analog.iqU_2>=edrk.iqMAX_U_ZPT_Global) + edrk.errors.e0.bits.U_2_MAX |= 1; + + + if (analog.iqU_1>=edrk.iqMAX_U_ZPT) + edrk.errors.e0.bits.U_1_MAX |= 1; + + + if (analog.iqU_2>=edrk.iqMAX_U_ZPT) + edrk.errors.e0.bits.U_2_MAX |= 1; + + + if (edrk.from_shema_filter.bits.QTV_ON_OFF == 1 + // && edrk.to_shema.bits.QTV_ON + ) + { + if (analog.iqU_1<=edrk.iqMIN_U_ZPT) + edrk.errors.e0.bits.U_1_MIN |= 1; + + if (analog.iqU_2<=edrk.iqMIN_U_ZPT) + edrk.errors.e0.bits.U_2_MIN |= 1; + } + + err = (edrk.errors.e0.bits.U_1_MAX || edrk.errors.e0.bits.U_2_MAX || edrk.errors.e0.bits.U_1_MIN || edrk.errors.e0.bits.U_2_MIN); + return err; + +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// +int detect_error_u_zpt(void) +{ + int err; + + err = 0; + + if (edrk.iqMAX_U_ZPT>MINIMAL_LEVEL_ZAD_U) + { + if (analog.iqU_1>=edrk.iqMAX_U_ZPT_Global) + edrk.errors.e0.bits.U_1_MAX |= 1; + + if (analog.iqU_2>=edrk.iqMAX_U_ZPT_Global) + edrk.errors.e0.bits.U_2_MAX |= 1; + } + + + if (edrk.iqMAX_U_ZPT>MINIMAL_LEVEL_ZAD_U && edrk.from_shema_filter.bits.QTV_ON_OFF == 1 + // && edrk.to_shema.bits.QTV_ON + ) + { + if (analog.iqU_1>=edrk.iqMAX_U_ZPT) + edrk.errors.e0.bits.U_1_MAX |= 1; + + + if (analog.iqU_2>=edrk.iqMAX_U_ZPT) + edrk.errors.e0.bits.U_2_MAX |= 1; + } + + if (edrk.from_shema_filter.bits.QTV_ON_OFF == 1 + //&& edrk.to_shema.bits.QTV_ON + ) + { + if (analog.iqU_1<=edrk.iqMIN_U_ZPT) + edrk.errors.e0.bits.U_1_MIN |= 1; + + if (analog.iqU_2<=edrk.iqMIN_U_ZPT) + edrk.errors.e0.bits.U_2_MIN |= 1; + } + + err = (edrk.errors.e0.bits.U_1_MAX || edrk.errors.e0.bits.U_2_MAX || edrk.errors.e0.bits.U_1_MIN || edrk.errors.e0.bits.U_2_MIN); + return err; + +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// +int detect_error_u_zpt_on_predzaryad(void) +{ + int err; + + err = 0; + + if (edrk.iqMAX_U_ZPT>MINIMAL_LEVEL_ZAD_U) + { + if (analog.iqU_1>=edrk.iqMAX_U_ZPT_Predzaryad) + edrk.errors.e0.bits.U_1_MAX |= 1; + + + if (analog.iqU_2>=edrk.iqMAX_U_ZPT_Predzaryad) + edrk.errors.e0.bits.U_2_MAX |= 1; + } + + err = (edrk.errors.e0.bits.U_1_MAX || edrk.errors.e0.bits.U_2_MAX || edrk.errors.e0.bits.U_1_MIN || edrk.errors.e0.bits.U_2_MIN); + return err; + +} + +/////////////////////////////////////////////// +#pragma CODE_SECTION(detect_error_u_in,".fast_run"); +int detect_error_u_in(void) +{ + int err; + static unsigned int count_err_on = 0; + + err = 0; + + if (edrk.iqMAX_U_ZPT>MINIMAL_LEVEL_ZAD_U) + { + if (filter.iqUin_m1>=edrk.iqMAX_U_IN) + edrk.errors.e0.bits.U_IN_MAX |= 1; + + + if (filter.iqUin_m2>=edrk.iqMAX_U_IN) + edrk.errors.e0.bits.U_IN_MAX |= 1; + } + + if (edrk.from_shema_filter.bits.QTV_ON_OFF == 1 && edrk.SumSbor + // && edrk.to_shema.bits.QTV_ON + ) + { + if (control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_QTV]==1) + { + err = 0; + } + else + { + if ((filter.iqUin_m1<=edrk.iqMIN_U_IN) || (filter.iqUin_m2<=edrk.iqMIN_U_IN)) + err = 1; + else + err = 0; + } + +#if (WORK_ON_STEND_D) + if (err) + { + if (pause_detect_error(&count_err_on,TIME_WAIT_ERROR_QTV,1)) + edrk.errors.e0.bits.U_IN_MIN |= 1; + } + else + count_err_on = 0; + + + +#else + + edrk.errors.e0.bits.U_IN_MIN |= err; +#endif + + } + + + + + + err = (edrk.errors.e0.bits.U_IN_MAX || edrk.errors.e0.bits.U_IN_MIN ); + return err; + +} +/////////////////////////////////////////////// +#define MAX_WAIT_AFTER_KVITIR 100//50 +void detect_error_all(void) +{ + unsigned int pause_after_kvitir=0; + + + if (f.count_wait_after_kvitir<=MAX_WAIT_AFTER_KVITIR) + { + f.count_wait_after_kvitir++; + pause_after_kvitir = 0; + } + else + pause_after_kvitir = 1; + + + + detect_error_ute4ka_water(); +// detect_error_t_vipr(); + detect_error_power_upc(); + detect_error_op_pit(); + + detect_error_pump_2(); + detect_error_pump_1(); + + if (edrk.warnings.e5.bits.PUMP_1 && edrk.warnings.e5.bits.PUMP_2) + { + edrk.errors.e5.bits.PUMP_1 |= 1; + edrk.errors.e5.bits.PUMP_2 |= 1; + } + + detect_error_pre_ready_pump(); + detect_error_fan(); + detect_error_qtv(); + detect_error_pre_charge(); + detect_error_block_izol(); + detect_error_nagrev(); + detect_error_ground(); + detect_error_ump(); + + + // , . ! + if (pause_after_kvitir) + { + detect_error_from_knopka_avaria(); + detect_error_from_another_bs(); + } + +#if (_FLOOR6==1) + +#else + detect_error_p_water(); +#endif + + detect_error_t_water(); + detect_error_t_air(); + detect_error_t_u(); + detect_error_acdrive_bear(); + detect_error_acdrive_winding(); + detect_error_block_qtv_from_svu(); + detect_error_block_door(); + + + detect_error_optical_bus(); + detect_error_sync_bus(); + detect_alive_another_bs(); + + edrk.warning = get_common_state_warning(); + edrk.overheat = get_common_state_overheat(); + + edrk.warnings.e10.bits.WARNING_I_OUT_OVER_1_6_NOMINAL = out_I_over_1_6.overload_detected; + +// edrk.errors.e7.bits.ANOTHER_BS_ALARM |= optical_read_data.data.cmd.bit.alarm; + detect_error_sensor_rotor(); + + +} +/////////////////////////////////////////////// +void clear_errors(void) +{ + + clear_errors_master_slave(); + clear_sync_error(); + + edrk.errors.e0.all = 0; + edrk.errors.e1.all = 0; + edrk.errors.e2.all = 0; + edrk.errors.e3.all = 0; + edrk.errors.e4.all = 0; + edrk.errors.e5.all = 0; + edrk.errors.e6.all = 0; + edrk.errors.e7.all = 0; + edrk.errors.e8.all = 0; + edrk.errors.e9.all = 0; + edrk.errors.e10.all = 0; + edrk.errors.e11.all = 0; + edrk.errors.e12.all = 0; + +// edrk.errors.e0.all = 0; +// edrk.errors.e0.all = 0; + edrk.Stop = 0; + + edrk.count_lost_interrupt = 0; + + f.count_wait_after_kvitir = 0; + + +} +/////////////////////////////////////////////// +void clear_warnings(void) +{ + + edrk.warnings.e0.all = 0; + edrk.warnings.e1.all = 0; + edrk.warnings.e2.all = 0; + edrk.warnings.e3.all = 0; + edrk.warnings.e4.all = 0; + edrk.warnings.e5.all = 0; + edrk.warnings.e6.all = 0; + edrk.warnings.e7.all = 0; + edrk.warnings.e8.all = 0; + edrk.warnings.e9.all = 0; + edrk.warnings.e10.all = 0; + edrk.warnings.e11.all = 0; + edrk.warnings.e12.all = 0; +} + +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +void read_plane_errors(void) +{ + if (project.controller.read.errors.bit.pwm_wdog) + edrk.errors.e9.bits.ERR_PWM_WDOG |= 1; + +#if USE_TK_0 +//af1 + if (project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_ack || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_current || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_ack || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_current || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_ack || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_current || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_ack || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_current || + project.cds_tk[0].read.sbus.time_err_tk_all.bit.tk_3210 || + project.cds_tk[0].read.sbus.lock_status_error.bit.line_err_keys_3210) + edrk.errors.e6.bits.UO2_KEYS |= 1; +//af2 + if (project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_ack || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_current || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_ack || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_current || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_ack || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_current || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_ack || + project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_current || + project.cds_tk[0].read.sbus.time_err_tk_all.bit.tk_7654 || + project.cds_tk[0].read.sbus.lock_status_error.bit.line_err_keys_7654) + edrk.errors.e6.bits.UO3_KEYS |= 1; +#endif + +#if USE_TK_1 +//af3 + if (project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_ack || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_current || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_ack || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_current || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_ack || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_current || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_ack || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_current || + project.cds_tk[1].read.sbus.time_err_tk_all.bit.tk_3210 || + project.cds_tk[1].read.sbus.lock_status_error.bit.line_err_keys_3210) + edrk.errors.e6.bits.UO4_KEYS |= 1; +//af4 + if (project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_ack || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_current || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_ack || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_current || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_ack || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_current || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_ack || + project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_current || + project.cds_tk[1].read.sbus.time_err_tk_all.bit.tk_7654 || + project.cds_tk[1].read.sbus.lock_status_error.bit.line_err_keys_7654) + edrk.errors.e6.bits.UO5_KEYS |= 1; +#endif + +#if USE_TK_2 +//af5 + if (project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_ack || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_current || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_ack || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_current || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_ack || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_current || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_ack || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_current || + project.cds_tk[2].read.sbus.time_err_tk_all.bit.tk_3210 || + project.cds_tk[2].read.sbus.lock_status_error.bit.line_err_keys_3210) + edrk.errors.e6.bits.UO6_KEYS |= 1; +//af6 + if (project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_ack || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_current || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_ack || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_current || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_ack || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_current || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_ack || + project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_current || + project.cds_tk[2].read.sbus.time_err_tk_all.bit.tk_7654 || + project.cds_tk[2].read.sbus.lock_status_error.bit.line_err_keys_7654) + edrk.errors.e6.bits.UO7_KEYS |= 1; + + +#endif + +#if USE_TK_3 + + if (project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_ack || + project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_current || + project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_ack || + project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_current || + project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk2_ack || + project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk2_current || + project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk3_ack || + project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk3_current || + project.cds_tk[3].read.sbus.time_err_tk_all.bit.tk_3210 || + project.cds_tk[3].read.sbus.lock_status_error.bit.line_err_keys_3210) + edrk.errors.e6.bits.UO1_KEYS |= 1; + +#endif + +//all errors local status + + +#if USE_TK_0 + if (project.cds_tk[0].read.sbus.lock_status_error.bit.err0_local) + edrk.errors.e4.bits.ERR_TK_0 |= 1; +#endif +#if USE_TK_1 + if (project.cds_tk[1].read.sbus.lock_status_error.bit.err0_local) + edrk.errors.e4.bits.ERR_TK_1 |= 1; +#endif +#if USE_TK_2 + if (project.cds_tk[2].read.sbus.lock_status_error.bit.err0_local) + edrk.errors.e4.bits.ERR_TK_2 |= 1; +#endif +#if USE_TK_3 + if (project.cds_tk[3].read.sbus.lock_status_error.bit.err0_local) + edrk.errors.e4.bits.ERR_TK_3 |= 1; +#endif + + +#if USE_IN_0 + if (project.cds_in[0].read.sbus.lock_status_error.bit.err0_local) + edrk.errors.e4.bits.ERR_IN_0 |= 1; +#endif +#if USE_IN_1 + if (project.cds_in[1].read.sbus.lock_status_error.bit.err0_local) + edrk.errors.e4.bits.ERR_IN_1 |= 1; +#endif + +#if USE_OUT_0 + if (project.cds_out[0].read.sbus.lock_status_error.bit.err0_local) + edrk.errors.e4.bits.ERR_OUT_0 |= 1; +#endif + +#if USE_ADC_0 + if (project.adc[0].read.sbus.lock_status_error.all) + edrk.errors.e4.bits.ERR_ADC_0 |= 1; +#endif +#if USE_ADC_1 + if (project.adc[1].read.sbus.lock_status_error.all) + edrk.errors.e4.bits.ERR_ADC_1 |= 1; +#endif +// + if (project.controller.read.errors.bit.status_er0) + edrk.errors.e5.bits.LINE_ERR0 |= 1; + if (project.controller.read.errors.bit.errHWP_trig) + edrk.errors.e5.bits.LINE_HWP |= 1; + + if (project.controller.read.errors.bit.error_pbus + || project.controller.read.errors_buses.bit.slave_addr_error + || project.controller.read.errors_buses.bit.count_error_pbus + || project.x_parallel_bus->flags.bit.error) + edrk.errors.e6.bits.ERR_PBUS |= 1; + + if (project.controller.read.errors_buses.bit.err_sbus) + edrk.errors.e6.bits.ERR_SBUS |= 1; + +/// + +#if USE_HWP_0 + if (project.hwp[0].read.comp_s.minus.all || project.hwp[0].read.comp_s.plus.all) + edrk.errors.e1.bits.HWP_ERROR |= 1; +#endif + + +#if USE_TK_0 + if (project.all_status_plates.tk0 != component_Ready) + edrk.errors.e3.bits.NOT_READY_TK_0 |= 1; +#endif +#if USE_TK_1 + if (project.all_status_plates.tk1 != component_Ready) + edrk.errors.e3.bits.NOT_READY_TK_1 |= 1; +#endif +#if USE_TK_2 + if (project.all_status_plates.tk2 != component_Ready) + edrk.errors.e3.bits.NOT_READY_TK_2 |= 1; +#endif +#if USE_TK_3 + if (project.all_status_plates.tk3 != component_Ready) + edrk.errors.e3.bits.NOT_READY_TK_3 |= 1; +#endif + +#if USE_ADC_0 + if (project.all_status_plates.adc0 != component_Ready) + edrk.errors.e3.bits.NOT_READY_ADC_0 |= 1; +#endif +#if USE_ADC_1 + if (project.all_status_plates.adc1 != component_Ready) + edrk.errors.e3.bits.NOT_READY_ADC_1 |= 1; +#endif + +#if USE_HWP_0 + if (project.all_status_plates.hwp0 != component_Ready) + edrk.errors.e3.bits.NOT_READY_HWP_0 |= 1; +#endif + +#if USE_IN_0 + if (project.all_status_plates.in0 != component_Ready) + edrk.errors.e3.bits.NOT_READY_IN_0 |= 1; +#endif +#if USE_IN_1 + if (project.all_status_plates.in1 != component_Ready) + edrk.errors.e3.bits.NOT_READY_IN_1 |= 1; +#endif + +#if USE_OUT_0 + if (project.all_status_plates.out0 != component_Ready) + edrk.errors.e3.bits.NOT_READY_OUT_0 |= 1; +#endif +} + +int get_common_state_warning() { + return edrk.warnings.e0.all != 0 || edrk.warnings.e1.all != 0 || + edrk.warnings.e2.all != 0 || edrk.warnings.e3.all != 0 || + edrk.warnings.e4.all != 0 || edrk.warnings.e5.all != 0 || + edrk.warnings.e6.all != 0 || edrk.warnings.e7.all != 0 || + edrk.warnings.e8.all != 0 || edrk.warnings.e9.all != 0 || + edrk.warnings.e10.all != 0 || edrk.warnings.e11.all != 0 || + edrk.warnings.e12.all != 0 ? 1 : 0; +} + +int get_common_state_overheat() { + return edrk.warnings.e2.bits.T_AIR0_MAX | edrk.warnings.e2.bits.T_AIR1_MAX | + edrk.warnings.e2.bits.T_AIR2_MAX | edrk.warnings.e2.bits.T_AIR3_MAX | + edrk.warnings.e2.bits.T_UO1_MAX | edrk.warnings.e2.bits.T_UO2_MAX | + edrk.warnings.e2.bits.T_UO3_MAX | edrk.warnings.e2.bits.T_UO4_MAX | + edrk.warnings.e2.bits.T_UO5_MAX | edrk.warnings.e2.bits.T_UO6_MAX | + edrk.warnings.e2.bits.T_UO7_MAX | edrk.warnings.e2.bits.T_WATER_EXT_MAX | + edrk.warnings.e2.bits.T_WATER_INT_MAX | + edrk.errors.e2.bits.T_AIR0_MAX | edrk.errors.e2.bits.T_AIR1_MAX | + edrk.errors.e2.bits.T_AIR2_MAX | edrk.errors.e2.bits.T_AIR3_MAX | + edrk.errors.e2.bits.T_UO1_MAX | edrk.errors.e2.bits.T_UO2_MAX | + edrk.errors.e2.bits.T_UO3_MAX | edrk.errors.e2.bits.T_UO4_MAX | + edrk.errors.e2.bits.T_UO5_MAX | edrk.errors.e2.bits.T_UO6_MAX | + edrk.errors.e2.bits.T_UO7_MAX | edrk.errors.e2.bits.T_WATER_EXT_MAX | + edrk.errors.e2.bits.T_WATER_INT_MAX; +} + diff --git a/Inu/Src2/551/main/detect_errors.h b/Inu/Src2/551/main/detect_errors.h new file mode 100644 index 0000000..48e3126 --- /dev/null +++ b/Inu/Src2/551/main/detect_errors.h @@ -0,0 +1,80 @@ +/* + * detect_errors.h + * + * Created on: 4 . 2020 . + * Author: star + */ + +#ifndef SRC_MYLIBS_DETECT_ERRORS_H_ +#define SRC_MYLIBS_DETECT_ERRORS_H_ + + + +#define TIME_WAIT_ERROR 20 // 2 sec +#define TIME_WAIT_ERROR_QTV 100 // 10 sec +#define TIME_WAIT_ERROR_CHARGE_ANSWER 60 // 6 sec +#define TIME_WAIT_ERROR_IZOL 50 //5 sec //200 // 20 sec +#define TIME_WAIT_ERROR_PUMP 100 // 10 sec +#define TIME_WAIT_ERROR_FAN 300 // 30 sec +#define TIME_WAIT_SENSOR_ROTOR_BREAK_ALL 200 // 20 sec +#define TIME_WAIT_SENSOR_ROTOR_BREAK_DIRECTION 10 // 1 sec +#define TIME_WAIT_SENSOR_ROTOR_BREAK_ONE_SENSOR 20 // 2 sec + + + + +#define MINIMAL_LEVEL_ZAD_U 27962 // 10 V + +void clear_errors(void); +void clear_warnings(void); +void detect_error_all(void); +void read_plane_errors(void); +int detect_error_u_zpt_on_predzaryad(void); +int detect_error_u_in(void); +int detect_error_u_zpt_fast(void); + + +void detect_error_from_knopka_avaria(void); +void detect_error_ute4ka_water(void); +void detect_error_t_vipr(void); +void detect_error_power_upc(void); +void detect_error_op_pit(void); +void detect_error_p_water(void); +void detect_error_pump_2(void); +void detect_error_pump_1(void); +void detect_error_pre_ready_pump(void); +void detect_error_fan(void); +void detect_error_block_qtv_from_svu(void); + +void detect_error_predohr_vipr(void); +void detect_error_qtv(void); +void detect_error_pre_charge(void); +void detect_error_block_izol(void); +void detect_error_nagrev(void); +void detect_error_ground(void); +void detect_error_block_door(void); +void detect_error_optical_bus(void); +void detect_error_sync_bus(void); +int get_status_temper_acdrive_winding(int nc); +int get_status_temper_acdrive_winding_with_limits(int nc, int alarm, int abnormal); +int get_status_temper_acdrive_bear(int nc); +int get_status_temper_acdrive_bear_with_limits(int nc, int alarm, int abnormal); +int get_status_temper_air(int nc); +int get_status_temper_air_with_limits(int nc, int alarm, int abnormal); +int get_status_temper_u(int nc); +int get_status_temper_u_with_limits(int nc, int alarm, int abnormal); +int get_status_temper_water(int nc); +int get_status_p_water_max(void); +int get_status_p_water_min(int pump_on_off); +void detect_error_t_water(void); +void detect_error_t_air(void); +void detect_error_t_u(void); +void detect_error_acdrive_winding(void); + +int get_common_state_warning(void); +int get_common_state_overheat(void); +void detect_error_sensor_rotor(void); + + + +#endif /* SRC_MYLIBS_DETECT_ERRORS_H_ */ diff --git a/Inu/Src2/551/main/detect_errors_adc.c b/Inu/Src2/551/main/detect_errors_adc.c new file mode 100644 index 0000000..634ea2f --- /dev/null +++ b/Inu/Src2/551/main/detect_errors_adc.c @@ -0,0 +1,310 @@ +/* + * detect_errors_adc.c + * + * Created on: 7 . 2020 . + * Author: star + */ +#include +#include +#include +#include +#include +#include +#include +#include "digital_filters.h" + +#include "IQmathLib.h" + +//ANALOG_PROTECT_LEVELS analog_protect_levels = ANALOG_PROTECT_LEVELS_DEFAULTS; + +//#pragma DATA_SECTION(analog_protect,".fast_vars"); +#pragma DATA_SECTION(analog_protect,".slow_vars"); +ANALOG_ADC_PROTECT analog_protect = ANALOG_ADC_PROTECT_DEFAULTS; + +//#pragma DATA_SECTION(break_Iout_1_state,".fast_vars"); +#pragma DATA_SECTION(break_Iout_1_state,".slow_vars"); +BREAK_PHASE_I break_Iout_1_state = BREAK_PHASE_I_DEFAULTS; + +//#pragma DATA_SECTION(break_Iout_2_state,".fast_vars"); +#pragma DATA_SECTION(break_Iout_2_state,".slow_vars"); +BREAK_PHASE_I break_Iout_2_state = BREAK_PHASE_I_DEFAULTS; + +int detect_error_Izpt(); +int detect_error_Ibreak(int res_num); +void init_protect_3_phase(void); + +void init_analog_protect_levels(void) { + init_protect_3_phase(); +} + +#define AMPL_TO_RMS 0.709 + +//#define LEVEL_I_1_2_DIBALANCE 1118481 // 200 A +#define LEVEL_I_1_2_DIBALANCE 1677721 // 300 A + +void init_protect_3_phase(void) { + analog_protect.in_voltage[0].setup.levels.iqVal_module_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[0].setup.levels.iqVal_U_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[0].setup.levels.iqVal_V_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[0].setup.levels.iqVal_W_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[0].setup.levels.iqNominal_plus10 = _IQ(edrk.zadanie.ZadanieU_Charge*PLUS_10_PERCENT/NORMA_ACP); + analog_protect.in_voltage[0].setup.levels.iqNominal_plus20 = _IQ(edrk.zadanie.ZadanieU_Charge*PLUS_20_PERCENT/NORMA_ACP); + analog_protect.in_voltage[0].setup.levels.iqNominal_minus10 = _IQ(edrk.zadanie.ZadanieU_Charge*MINUS_10_PERCENT/NORMA_ACP); + analog_protect.in_voltage[0].setup.levels.iqNominal_minus20 = _IQ(edrk.zadanie.ZadanieU_Charge*MINUS_20_PERCENT/NORMA_ACP); + analog_protect.in_voltage[0].setup.levels.iqAsymmetry_delta = _IQ(edrk.zadanie.ZadanieU_Charge*ASYMMETRY_DELTA_PERCENTS/NORMA_ACP); + analog_protect.in_voltage[0].setup.use.all = 0; + analog_protect.in_voltage[0].setup.use.bits.phase_U = 0; + analog_protect.in_voltage[0].setup.use.bits.phase_V = 0; + analog_protect.in_voltage[0].setup.use.bits.phase_W = 0; + analog_protect.in_voltage[0].setup.use.bits.module = 0; + analog_protect.in_voltage[0].setup.use.bits.detect_minus_10 = 1; + analog_protect.in_voltage[0].setup.use.bits.detect_minus_20 = 1; + analog_protect.in_voltage[0].setup.use.bits.detect_plus_10 = 0; + analog_protect.in_voltage[0].setup.use.bits.detect_plus_20 = 1; + analog_protect.in_voltage[0].setup.use.bits.system_asymmetry_by_delta = 1; + + analog_protect.in_voltage[1].setup.levels.iqVal_module_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[1].setup.levels.iqVal_U_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[1].setup.levels.iqVal_V_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[1].setup.levels.iqNominal_plus10 = _IQ(edrk.zadanie.ZadanieU_Charge*PLUS_10_PERCENT/NORMA_ACP); + analog_protect.in_voltage[1].setup.levels.iqNominal_plus20 = _IQ(edrk.zadanie.ZadanieU_Charge*PLUS_20_PERCENT/NORMA_ACP); + analog_protect.in_voltage[1].setup.levels.iqNominal_minus10 = _IQ(edrk.zadanie.ZadanieU_Charge*MINUS_10_PERCENT/NORMA_ACP); + analog_protect.in_voltage[1].setup.levels.iqNominal_minus20 = _IQ(edrk.zadanie.ZadanieU_Charge*MINUS_20_PERCENT/NORMA_ACP); + analog_protect.in_voltage[1].setup.levels.iqAsymmetry_delta = _IQ(edrk.zadanie.ZadanieU_Charge*ASYMMETRY_DELTA_PERCENTS/NORMA_ACP); + analog_protect.in_voltage[1].setup.use.all = 0; + analog_protect.in_voltage[1].setup.use.bits.phase_U = 0; + analog_protect.in_voltage[1].setup.use.bits.phase_V = 0; + analog_protect.in_voltage[1].setup.use.bits.phase_W = 0; + analog_protect.in_voltage[1].setup.use.bits.module = 0; + analog_protect.in_voltage[1].setup.use.bits.detect_minus_10 = 1; + analog_protect.in_voltage[1].setup.use.bits.detect_minus_20 = 1; + analog_protect.in_voltage[1].setup.use.bits.detect_plus_10 = 0; + analog_protect.in_voltage[1].setup.use.bits.detect_plus_20 = 1; + analog_protect.in_voltage[1].setup.use.bits.system_asymmetry_by_delta = 1; + + ///////////////// + analog_protect.out_I[0].setup.levels.iqVal_module_max = _IQ(LEVEL_ADC_I_AF / NORMA_ACP); + analog_protect.out_I[0].setup.levels.iqVal_U_max = _IQ(LEVEL_ADC_I_AF / NORMA_ACP); + analog_protect.out_I[0].setup.levels.iqVal_V_max = _IQ(LEVEL_ADC_I_AF / NORMA_ACP); + analog_protect.out_I[0].setup.levels.iqVal_W_max = _IQ(LEVEL_ADC_I_AF / NORMA_ACP); + analog_protect.out_I[0].setup.use.all = 0; + analog_protect.out_I[0].setup.use.bits.phase_U = 1; + analog_protect.out_I[0].setup.use.bits.phase_V = 1; + analog_protect.out_I[0].setup.use.bits.phase_W = 1; + analog_protect.out_I[0].setup.use.bits.break_phase = 1; + + analog_protect.out_I[1].setup.levels.iqVal_module_max = _IQ(LEVEL_ADC_I_AF / NORMA_ACP); + analog_protect.out_I[1].setup.levels.iqVal_U_max = _IQ(LEVEL_ADC_I_AF / NORMA_ACP); + analog_protect.out_I[1].setup.levels.iqVal_V_max = _IQ(LEVEL_ADC_I_AF / NORMA_ACP); + analog_protect.out_I[1].setup.levels.iqVal_W_max = _IQ(LEVEL_ADC_I_AF / NORMA_ACP); + analog_protect.out_I[1].setup.use.all = 0; + analog_protect.out_I[1].setup.use.bits.phase_U = 1; + analog_protect.out_I[1].setup.use.bits.phase_V = 1; + analog_protect.out_I[1].setup.use.bits.phase_W = 1; + analog_protect.out_I[1].setup.use.bits.break_phase = 1; + + analog_protect.iqI_zpt_level = _IQ(LEVEL_ADC_I_ZPT / NORMA_ACP); + analog_protect.iqI_break_level = _IQ(LEVEL_ADC_I_BREAK / NORMA_ACP); +} + +#define min(x,y) (x) < (y) ? (x) : (y) +#define max(x,y) (x) > (y) ? (x) : (y) + +void reinit_protect_I_and_U_settings(void) { + int max_I = 0; + analog_protect.in_voltage[0].setup.levels.iqVal_module_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[0].setup.levels.iqVal_U_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[0].setup.levels.iqVal_V_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[0].setup.levels.iqVal_W_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[0].setup.levels.iqNominal_plus10 = _IQ(edrk.zadanie.ZadanieU_Charge*PLUS_10_PERCENT/NORMA_ACP); + analog_protect.in_voltage[0].setup.levels.iqNominal_plus20 = _IQ(edrk.zadanie.ZadanieU_Charge*PLUS_20_PERCENT/NORMA_ACP); + analog_protect.in_voltage[0].setup.levels.iqNominal_minus10 = _IQ(edrk.zadanie.ZadanieU_Charge*MINUS_10_PERCENT/NORMA_ACP); + analog_protect.in_voltage[0].setup.levels.iqNominal_minus20 = _IQ(edrk.zadanie.ZadanieU_Charge*MINUS_20_PERCENT/NORMA_ACP); + analog_protect.in_voltage[0].setup.levels.iqAsymmetry_delta = _IQ(edrk.zadanie.ZadanieU_Charge*ASYMMETRY_DELTA_PERCENTS/NORMA_ACP); + + analog_protect.in_voltage[1].setup.levels.iqVal_module_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[1].setup.levels.iqVal_U_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[1].setup.levels.iqVal_V_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[1].setup.levels.iqVal_W_max = edrk.iqMAX_U_IN; + analog_protect.in_voltage[1].setup.levels.iqNominal_plus10 = _IQ(edrk.zadanie.ZadanieU_Charge*PLUS_10_PERCENT/NORMA_ACP); + analog_protect.in_voltage[1].setup.levels.iqNominal_plus20 = _IQ(edrk.zadanie.ZadanieU_Charge*PLUS_20_PERCENT/NORMA_ACP); + analog_protect.in_voltage[1].setup.levels.iqNominal_minus10 = _IQ(edrk.zadanie.ZadanieU_Charge*MINUS_10_PERCENT/NORMA_ACP); + analog_protect.in_voltage[1].setup.levels.iqNominal_minus20 = _IQ(edrk.zadanie.ZadanieU_Charge*MINUS_20_PERCENT/NORMA_ACP); + analog_protect.in_voltage[1].setup.levels.iqAsymmetry_delta = _IQ(edrk.zadanie.ZadanieU_Charge*ASYMMETRY_DELTA_PERCENTS/NORMA_ACP); + + max_I = max(protect_levels.alarm_Imax_U02, protect_levels.alarm_Imax_U03); + max_I = max(max_I, protect_levels.alarm_Imax_U04); + analog_protect.out_I[0].setup.levels.iqVal_module_max = _IQ(((float)max_I) / NORMA_ACP); + analog_protect.out_I[0].setup.levels.iqVal_U_max = _IQ(((float)protect_levels.alarm_Imax_U02) / NORMA_ACP); + analog_protect.out_I[0].setup.levels.iqVal_V_max = _IQ(((float)protect_levels.alarm_Imax_U03) / NORMA_ACP); + analog_protect.out_I[0].setup.levels.iqVal_W_max = _IQ(((float)protect_levels.alarm_Imax_U04) / NORMA_ACP); + + max_I = max(protect_levels.alarm_Imax_U05, protect_levels.alarm_Imax_U06); + max_I = max(max_I, protect_levels.alarm_Imax_U07); + analog_protect.out_I[1].setup.levels.iqVal_module_max = _IQ(((float)max_I) / NORMA_ACP); + analog_protect.out_I[1].setup.levels.iqVal_U_max = _IQ(((float)protect_levels.alarm_Imax_U05) / NORMA_ACP); + analog_protect.out_I[1].setup.levels.iqVal_V_max = _IQ(((float)protect_levels.alarm_Imax_U06) / NORMA_ACP); + analog_protect.out_I[1].setup.levels.iqVal_W_max = _IQ(((float)protect_levels.alarm_Imax_U07) / NORMA_ACP); + + analog_protect.iqI_zpt_level = _IQ(protect_levels.alarm_Izpt_max / NORMA_ACP); + analog_protect.iqI_break_level = _IQ(protect_levels.alarm_Imax_U01 / NORMA_ACP); + + if (edrk.SumSbor == 0) { + analog_protect.in_voltage[0].setup.timers_inited = 0; + analog_protect.in_voltage[1].setup.timers_inited = 0; + analog_protect.out_I[0].setup.timers_inited = 0; + analog_protect.out_I[1].setup.timers_inited = 0; + } +} + +#define TIME_DETECT_WARNING_U_PREDELS 100 + +void detect_protect_adc(_iq teta_ch1, _iq teta_ch2) { + static unsigned int timer_U_in1_minus10 = 0; + static unsigned int timer_U_in1_minus20 = 0; + static unsigned int timer_U_in1_plus20 = 0; + + static unsigned int timer_U_in2_minus10 = 0; + static unsigned int timer_U_in2_minus20 = 0; + static unsigned int timer_U_in2_plus20 = 0; + + static unsigned int counter_in1_minus10 = 0; + static unsigned int counter_in2_minus10 = 0; + static unsigned int counter_in1_minus20 = 0; + static unsigned int counter_in2_minus20 = 0; + + + // + //0 + analog_protect.in_voltage[0].errors.all = 0; + analog_protect.in_voltage[0].iqVal_U = analog.iqUin_A1B1_rms; + analog_protect.in_voltage[0].iqVal_V = analog.iqUin_B1C1_rms; + analog_protect.in_voltage[0].iqVal_W = analog.iqUin_C1A1_rms; + analog_protect.in_voltage[0].iqVal_mod = filter.iqUin_m1; + +// analog_protect.in_voltage[0].calc(&analog_protect.in_voltage[0]); + + //1 + analog_protect.in_voltage[1].errors.all = 0; + analog_protect.in_voltage[1].iqVal_U = analog.iqUin_A2B2_rms; + analog_protect.in_voltage[1].iqVal_V = analog.iqUin_B2C2_rms; + analog_protect.in_voltage[1].iqVal_W = analog.iqUin_C2A2_rms; + analog_protect.in_voltage[1].iqVal_mod = filter.iqUin_m2; + +// analog_protect.in_voltage[1].calc(&analog_protect.in_voltage[1]); + + // + edrk.errors.e0.bits.U_A1B1_MAX |= analog_protect.in_voltage[0].errors.bits.phase_U_max; + edrk.errors.e0.bits.U_B1C1_MAX |= analog_protect.in_voltage[0].errors.bits.phase_V_max; + edrk.errors.e0.bits.U_IN_MAX |= analog_protect.in_voltage[0].errors.bits.module_max; + // + edrk.errors.e0.bits.U_A2B2_MAX |= analog_protect.in_voltage[1].errors.bits.phase_U_max; + edrk.errors.e0.bits.U_B2C2_MAX |= analog_protect.in_voltage[1].errors.bits.phase_V_max; + edrk.errors.e0.bits.U_IN_MAX |= analog_protect.in_voltage[1].errors.bits.module_max; + + edrk.warnings.e8.bits.U_IN_20_PROCENTS_HIGH = analog_protect.in_voltage[0].over_limit.bits.module_20_percent_hi || analog_protect.in_voltage[1].over_limit.bits.module_20_percent_hi; + edrk.errors.e8.bits.U_IN_20_PROCENTS_HIGH |= analog_protect.in_voltage[0].errors.bits.module_20_percent_hi; + edrk.errors.e8.bits.U_IN_20_PROCENTS_HIGH |= analog_protect.in_voltage[1].errors.bits.module_20_percent_hi; + + if (edrk.from_shema_filter.bits.QTV_ON_OFF == 1 + // && edrk.to_shema.bits.QTV_ON + ) + { + + // + edrk.errors.e8.bits.U_IN_10_PROCENTS_LOW |= analog_protect.in_voltage[0].errors.bits.module_10_percent_low; + edrk.errors.e8.bits.U_IN_20_PROCENTS_LOW |= analog_protect.in_voltage[0].errors.bits.module_20_percent_low; + + edrk.errors.e8.bits.U_IN_10_PROCENTS_LOW |= analog_protect.in_voltage[1].errors.bits.module_10_percent_low; + edrk.errors.e8.bits.U_IN_20_PROCENTS_LOW |= analog_protect.in_voltage[1].errors.bits.module_20_percent_low; + + edrk.warnings.e8.bits.U_IN_10_PROCENTS_LOW = pause_detect_error(&counter_in1_minus10, + TIME_DETECT_WARNING_U_PREDELS, + analog_protect.in_voltage[0].over_limit.bits.module_10_percent_low); + + edrk.warnings.e8.bits.U_IN_10_PROCENTS_LOW = pause_detect_error(&counter_in2_minus10, + TIME_DETECT_WARNING_U_PREDELS, + analog_protect.in_voltage[1].over_limit.bits.module_10_percent_low); + + edrk.warnings.e8.bits.U_IN_20_PROCENTS_LOW = pause_detect_error(&counter_in1_minus20, + TIME_DETECT_WARNING_U_PREDELS, + analog_protect.in_voltage[0].over_limit.bits.module_20_percent_low); + + edrk.warnings.e8.bits.U_IN_20_PROCENTS_LOW = pause_detect_error(&counter_in2_minus20, + TIME_DETECT_WARNING_U_PREDELS, + analog_protect.in_voltage[1].over_limit.bits.module_20_percent_low); + + edrk.errors.e9.bits.DISBALANCE_Uin_1 |= analog_protect.in_voltage[0].errors.bits.system_asymmetry; + edrk.errors.e9.bits.DISBALANCE_Uin_2 |= analog_protect.in_voltage[1].errors.bits.system_asymmetry; + + } + else + { + edrk.warnings.e8.bits.U_IN_10_PROCENTS_LOW = 0; + edrk.warnings.e8.bits.U_IN_20_PROCENTS_LOW = 0; + } + + // + analog_protect.out_I[0].errors.all = 0; + analog_protect.out_I[0].iqVal_U = analog.iqIu_1; + analog_protect.out_I[0].iqVal_V = analog.iqIv_1; + analog_protect.out_I[0].iqVal_W = analog.iqIw_1; + analog_protect.out_I[0].iqVal_mod = analog.iqIm_1; + analog_protect.out_I[0].break_phase = &break_Iout_1_state; + analog_protect.out_I[0].iqTeta = teta_ch1; + +// analog_protect.out_I[0].calc(&analog_protect.out_I[0]); + + edrk.errors.e1.bits.I_UO2_MAX = analog_protect.out_I[0].errors.bits.phase_U_max; + edrk.errors.e1.bits.I_UO3_MAX = analog_protect.out_I[0].errors.bits.phase_V_max; + edrk.errors.e1.bits.I_UO4_MAX = analog_protect.out_I[0].errors.bits.phase_W_max; + + if (analog_protect.out_I[0].errors.bits.break_phase) { + edrk.errors.e8.bits.LOSS_OUTPUT_U1 = analog_protect.out_I[0].errors.bits.break_phase_U; + edrk.errors.e8.bits.LOSS_OUTPUT_V1 = analog_protect.out_I[0].errors.bits.break_phase_V; + edrk.errors.e8.bits.LOSS_OUTPUT_W1 = analog_protect.out_I[0].errors.bits.break_phase_W; + } + + analog_protect.out_I[1].errors.all = 0; + analog_protect.out_I[1].iqVal_U = analog.iqIu_2; + analog_protect.out_I[1].iqVal_V = analog.iqIv_2; + analog_protect.out_I[1].iqVal_W = analog.iqIw_2; + analog_protect.out_I[1].iqVal_mod = analog.iqIm_2; + analog_protect.out_I[1].break_phase = &break_Iout_2_state; + analog_protect.out_I[1].iqTeta = teta_ch2; + +// analog_protect.out_I[1].calc(&analog_protect.out_I[1]); + + edrk.errors.e1.bits.I_UO5_MAX = analog_protect.out_I[1].errors.bits.phase_U_max; + edrk.errors.e1.bits.I_UO6_MAX = analog_protect.out_I[1].errors.bits.phase_V_max; + edrk.errors.e1.bits.I_UO7_MAX = analog_protect.out_I[1].errors.bits.phase_W_max; + if (analog_protect.out_I[1].errors.bits.break_phase) { + edrk.errors.e8.bits.LOSS_OUTPUT_U2 = analog_protect.out_I[1].errors.bits.break_phase_U; + edrk.errors.e8.bits.LOSS_OUTPUT_V2 = analog_protect.out_I[1].errors.bits.break_phase_V; + edrk.errors.e8.bits.LOSS_OUTPUT_W2 = analog_protect.out_I[1].errors.bits.break_phase_W; + } + + edrk.errors.e8.bits.DISBALANCE_IM1_IM2 |= _IQabs(analog.iqIm_1 - analog.iqIm_2) > LEVEL_I_1_2_DIBALANCE ? 1 : 0; + + //I zpt + edrk.errors.e0.bits.I_1_MAX |= detect_error_Izpt(); + // + edrk.errors.e1.bits.I_BREAK_1_MAX |= detect_error_Ibreak(1); + edrk.errors.e1.bits.I_BREAK_2_MAX |= detect_error_Ibreak(2); +} + +int detect_error_Izpt() { + return analog.iqIin_1 > analog_protect.iqI_zpt_level ? 1 : 0; +} + +int detect_error_Ibreak(int res_num) { + if (res_num == 1) { + return analog.iqIbreak_1 > analog_protect.iqI_break_level || + analog.iqIbreak_1 < -analog_protect.iqI_break_level ? 1 : 0; + } else if (res_num == 2) { + return analog.iqIbreak_2 > analog_protect.iqI_break_level || + analog.iqIbreak_2 < -analog_protect.iqI_break_level ? 1 : 0; + } else { + return 0; + } +} diff --git a/Inu/Src2/551/main/detect_errors_adc.h b/Inu/Src2/551/main/detect_errors_adc.h new file mode 100644 index 0000000..6aa850d --- /dev/null +++ b/Inu/Src2/551/main/detect_errors_adc.h @@ -0,0 +1,45 @@ +/* + * detect_errors_adc.h + * + * Created on: 7 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_DETECT_ERRORS_ADC_H_ +#define SRC_MAIN_DETECT_ERRORS_ADC_H_ + +#include + +typedef struct { + SETUP_3_PHASE_PROTECT U_in; + SETUP_3_PHASE_PROTECT I_out; + + _iq iqI_zpt; + _iq iqI_break; + +} ANALOG_PROTECT_LEVELS; + +#define ANALOG_PROTECT_LEVELS_DEFAULTS { SETUP_3_PHASE_PROTECT_DEFAULTS, \ + SETUP_3_PHASE_PROTECT_DEFAULTS, \ + 0,0} + +typedef struct { + DETECT_PROTECT_3_PHASE in_voltage[2]; + DETECT_PROTECT_3_PHASE out_I[2]; + + _iq iqI_zpt_level; + _iq iqI_break_level; +} ANALOG_ADC_PROTECT; + +#define ANALOG_ADC_PROTECT_DEFAULTS { \ + {DETECT_PROTECT_3_PHASE_DEFAULTS,DETECT_PROTECT_3_PHASE_DEFAULTS},\ + {DETECT_PROTECT_3_PHASE_DEFAULTS,DETECT_PROTECT_3_PHASE_DEFAULTS},\ + 0,0 } + +void init_analog_protect_levels(void); +void detect_protect_adc (_iq teta_ch1, _iq teta_ch2); +void reinit_protect_I_and_U_settings(void); + + +extern ANALOG_ADC_PROTECT analog_protect; +#endif /* SRC_MAIN_DETECT_ERRORS_ADC_H_ */ diff --git a/Inu/Src2/551/main/detect_overload.c b/Inu/Src2/551/main/detect_overload.c new file mode 100644 index 0000000..fce38dd --- /dev/null +++ b/Inu/Src2/551/main/detect_overload.c @@ -0,0 +1,92 @@ +/* + * detect_overload.c + * + * Created on: 15 . 2020 . + * Author: star + */ +#include +#include +#include +#include +#include +#include "alg_simple_scalar.h" + +#include "IQmathLib.h" + +DETECT_OVERLOAD out_I_over_1_6 = DETECT_OVERLOAD_DEFAULTS; + +#define CALLS_IN_PWM_INT 2 // (1 2) + +void init_detect_overloads(void) { + out_I_over_1_6.level_overload = _IQmpy(I_OUT_NOMINAL_IQ, _IQ(1.6)); + out_I_over_1_6.time_over_tics = (long) 15 * FREQ_PWM * CALLS_IN_PWM_INT; + out_I_over_1_6.time_latch_tics = (long) 45 * FREQ_PWM * CALLS_IN_PWM_INT; + out_I_over_1_6.tics_counter = 0; + out_I_over_1_6.overload_detected = 0; + +} + +int calc_detect_overload(DETECT_OVERLOAD *v) { + if (v->val > v->level_overload) { + v->tics_counter += 1; + if (v->tics_counter > v->time_over_tics) { v->tics_counter = v->time_over_tics;} + } else { + if (v->tics_counter > 0) { v->tics_counter -= 1; } + else {v->tics_counter = 0;} + if (v->overload_detected && v->tics_counter == 0) { + v->overload_detected = 0; + } + } + if (v->tics_counter >= v->time_over_tics) { + v->overload_detected = 1; + v->tics_counter = v->time_latch_tics; + } + return v->overload_detected; +} + +#define LIMIT_DETECT_LEVEL 16273899 // 0.97 //15938355 //95% + +void check_all_power_limits() { + _iq level_I_nominal = 0; + + //edrk.power_limit.bits.limit_by_temper = edrk.temper_limit_koeffs.code_status; + + if (edrk.Go) + { + + level_I_nominal = _IQmpy(LIMIT_DETECT_LEVEL, edrk.zadanie.iq_Izad_rmp); + + if ((filter.iqIm > level_I_nominal) || + out_I_over_1_6.overload_detected) + { + edrk.power_limit.bits.limit_Iout = 1; + } else + { + edrk.power_limit.bits.limit_Iout = 0; + } + } + else + edrk.power_limit.bits.limit_Iout = 0; + +// if (edrk.from_uom.code>1) +// edrk.power_limit.bits.limit_UOM = 1; +// else +// edrk.power_limit.bits.limit_UOM = 0; + +//filter.PowerScalar + edrk.iq_power_kw_another_bs + if ( (edrk.iq_power_kw_full_filter_abs > _IQmpy(LIMIT_DETECT_LEVEL, edrk.zadanie.iq_limit_power_zad_rmp)) + || simple_scalar1.flag_decr_mzz_power + // , FOC, , . + ) + { + edrk.power_limit.bits.limit_from_SVU = 1; + } + else + { + edrk.power_limit.bits.limit_from_SVU = 0; + } + + +} + + diff --git a/Inu/Src2/551/main/detect_overload.h b/Inu/Src2/551/main/detect_overload.h new file mode 100644 index 0000000..897e24a --- /dev/null +++ b/Inu/Src2/551/main/detect_overload.h @@ -0,0 +1,32 @@ +/* + * detect_overload.h + * + * Created on: 15 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_DETECT_OVERLOAD_H_ +#define SRC_MAIN_DETECT_OVERLOAD_H_ + +typedef struct { + _iq val; // + _iq level_overload; // + int overload_detected; // + + unsigned long time_over_tics; + unsigned long time_latch_tics; + unsigned long tics_counter; + + int (*calc)(); +} DETECT_OVERLOAD; + +#define DETECT_OVERLOAD_DEFAULTS {0,0,0, 0,0,0, \ + calc_detect_overload } + +void init_detect_overloads(void); +int calc_detect_overload(DETECT_OVERLOAD *v); +void check_all_power_limits(); + +extern DETECT_OVERLOAD out_I_over_1_6; + +#endif /* SRC_MAIN_DETECT_OVERLOAD_H_ */ diff --git a/Inu/Src2/551/main/detect_phase_break.c b/Inu/Src2/551/main/detect_phase_break.c new file mode 100644 index 0000000..69f0b55 --- /dev/null +++ b/Inu/Src2/551/main/detect_phase_break.c @@ -0,0 +1,112 @@ +/* + * detect_phase_break.c + * + * Created on: 10 . 2020 . + * Author: star + */ + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "IQmathLib.h" + +#include + + +#define CONST_IQ_2PI 105414357 // 360 +#define CONST_IQ_PI2 26353589 // 90 + + +static void clear_alg_vars(BREAK_PHASE_I *v); +static int calc_direction(BREAK_PHASE_I *v); +static int calc_error_if_break(BREAK_PHASE_I *v, int num, int field_direction); + +// , +// 0 - +// 1- U +// 2- V +// 3- W +int calc_break_I_phase(BREAK_PHASE_I *v) { + + int field_direction = 1; //1 - forward, 0 - reverse + int err = 0; + + if (v->teta > CONST_IQ_2PI) { + v->teta = CONST_IQ_2PI; + } + if(v->teta < 0) { + v->teta = 0; + } + field_direction = calc_direction(v); + if (v->iqImod < v->config.iqLevelZero) { + clear_alg_vars(v); + return 0; + } + + if (_IQabs(v->iqIu) < v->config.iqLevelZero && + _IQabs(v->iqIv + v->iqIw) < v->config.iqLevelZero && + _IQabs(v->iqIv) > v->config.iqLevelZero && _IQabs(v->iqIw) > v->config.iqLevelZero) { + err = calc_error_if_break(v, 0, field_direction); + } else { + v->latch_break_start[0] = 0; + } + if (_IQabs(v->iqIv) < v->config.iqLevelZero && + _IQabs(v->iqIu + v->iqIw) < v->config.iqLevelZero && + _IQabs(v->iqIu) > v->config.iqLevelZero && _IQabs(v->iqIw) > v->config.iqLevelZero) { + err = calc_error_if_break(v, 1, field_direction); + } else { + v->latch_break_start[1] = 0; + } + if (_IQabs(v->iqIw) < v->config.iqLevelZero && + _IQabs(v->iqIv + v->iqIu) < v->config.iqLevelZero && + _IQabs(v->iqIv) > v->config.iqLevelZero && _IQabs(v->iqIu) > v->config.iqLevelZero) { + err = calc_error_if_break(v, 2, field_direction); + } else { + v->latch_break_start[2] = 0; + } + + return err; +} + +void clear_alg_vars(BREAK_PHASE_I *v) { + int i = 0; + for (i = 0; i < 3; i++) { + v->latch_break_start[i] = 0; + v->latched_teta[i] = 0; + } +} + +int calc_direction(BREAK_PHASE_I *v) { + int direction = 1; + if (v->teta > v->prev_teta) { + if (v->teta - v->prev_teta < CONST_IQ_PI2) { direction = 1;} + else { direction = 0;} + } else { + if (v->prev_teta - v->teta < CONST_IQ_2PI) { direction = 0;} + else { direction = 1;} + } + v->prev_teta = v->teta; + return direction; +} + +int calc_error_if_break(BREAK_PHASE_I *v, int num, int field_direction) { + int err = 0; + if (v->latch_break_start[num] == 0) { + v->latch_break_start[num] = 1; + v->latched_teta[num] = v->teta; + } else { + if (field_direction == 0) { + if (v->latched_teta[num] > v->teta) { + err = v->latched_teta[num] - v->teta > CONST_IQ_PI2 ? num + 1 : 0; + } else { + err = v->teta - v->latched_teta[num] < CONST_IQ_PI2 - CONST_IQ_2PI ? num + 1 : 0; + } + } else { + if (v->latched_teta[num] < v->teta) { + err = v->teta - v->latched_teta[num] > CONST_IQ_PI2 ? num + 1 : 0; + } else { + err = v->latched_teta[num] - v->teta < CONST_IQ_PI2 - CONST_IQ_2PI ? num + 1 : 0; + } + } + } + return err; +} diff --git a/Inu/Src2/551/main/detect_phase_break.h b/Inu/Src2/551/main/detect_phase_break.h new file mode 100644 index 0000000..66104d8 --- /dev/null +++ b/Inu/Src2/551/main/detect_phase_break.h @@ -0,0 +1,36 @@ +/* + * detect_phase_break.h + * + * Created on: 10 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_DETECT_PHASE_BREAK_H_ +#define SRC_MAIN_DETECT_PHASE_BREAK_H_ + +typedef struct { + _iq iqIu; + _iq iqIv; + _iq iqIw; + _iq iqImod; + _iq teta; + _iq prev_teta; + + _iq latched_teta[3]; + int latch_break_start[3]; + + struct { + _iq iqLevelZero; + + } config; + + int (*calc)(); +} BREAK_PHASE_I; + +#define BREAK_PHASE_I_DEFAULTS {0,0,0,0,0,0, \ + {0,0,0}, {0,0,0}, {0}, \ + calc_break_I_phase } + +int calc_break_I_phase(BREAK_PHASE_I *v); + +#endif /* SRC_MAIN_DETECT_PHASE_BREAK_H_ */ diff --git a/Inu/Src2/551/main/detect_phase_break2.c b/Inu/Src2/551/main/detect_phase_break2.c new file mode 100644 index 0000000..4cfb921 --- /dev/null +++ b/Inu/Src2/551/main/detect_phase_break2.c @@ -0,0 +1,203 @@ +/* + * detect_phase_break.c + * + * Created on: 10 . 2020 . + * Author: star + */ + +#include "IQmathLib.h" + +//#include "DSP281x_Examples.h" // DSP281x Examples Include File +//#include "DSP281x_Device.h" // DSP281x Headerfile Include File + +#include "detect_phase_break2.h" + + +#define CONST_IQ_2PI 105414357 // 2*pi 360 +#define CONST_IQ_3_2PI 79060767 // 4/3 pi 270 +#define CONST_IQ_PI2 26353589 // 90 + + + +void check_brocken_phase(BREAK2_PHASE *v) +{ + int i; + int ph_a=0, ph_b=0, ph_c=0; + _iq plus_a, max_a; + + if ( (v->iqCh[0] >= v->iqCh[1] && v->iqCh[0] < v->iqCh[2]) + || (v->iqCh[0] >= v->iqCh[2] && v->iqCh[0] < v->iqCh[1]) ) + ph_a = 1; + else + ph_a = -1; + + if ( (v->iqCh[1] >= v->iqCh[0] && v->iqCh[1] < v->iqCh[2]) + || (v->iqCh[1] >= v->iqCh[2] && v->iqCh[1] < v->iqCh[0]) ) + ph_b = 1; + else + ph_b = -1; + + if ( (v->iqCh[2] >= v->iqCh[0] && v->iqCh[2] < v->iqCh[1]) + || (v->iqCh[2] >= v->iqCh[1] && v->iqCh[2] < v->iqCh[0]) ) + ph_c = 1; + else + ph_c = -1; + + + // plus_a = _IQ(360.0/v->config.freq_pwm * v->freq_signal); + plus_a = _IQmpy(v->config.calc_const, v->freq_signal); + + + v->sum_brocken_out[0] += plus_a*ph_a; + v->sum_brocken_out[1] += plus_a*ph_b; + v->sum_brocken_out[2] += plus_a*ph_c; + + v->plus_a = plus_a; + + for (i=0;i<3;i++) + { + if (v->sum_brocken_out[i]>=CONST_IQ_2PI) v->sum_brocken_out[i] = CONST_IQ_2PI; + if (v->sum_brocken_out[i]<=0) v->sum_brocken_out[i] = 0; + + if (v->sum_brocken_out[i]>CONST_IQ_3_2PI) + v->return_brocken_code |= (1<sum_brocken_out[0]>=max_a) max_a = v->sum_brocken_out[0]; + if (v->sum_brocken_out[1]>=max_a) max_a = v->sum_brocken_out[1]; + if (v->sum_brocken_out[2]>=max_a) max_a = v->sum_brocken_out[2]; + v->sum_brocken_out[3] = max_a; // + +} + + + +void check_i_out_brocken(float freq) +{ + + + +} + + + + + +// , +// 0 - +// 1- U +// 2- V +// 3- W +int calc_break2_phase(BREAK2_PHASE *v) { + +// int field_direction = 1; //1 - forward, 0 - reverse + int err = 0; + + if (v->freq_signal==0) + { + v->sum_brocken_out[0] = 0; + v->sum_brocken_out[1] = 0; + v->sum_brocken_out[2] = 0; + v->sum_brocken_out[3] = 0; + v->brocken_i_out = 0; + } + else + { + if (_IQabs(v->iqCh[0])>v->config.minimal_level + || _IQabs(v->iqCh[1])>v->config.minimal_level + || _IQabs(v->iqCh[2])>v->config.minimal_level ) + { + check_brocken_phase(v); + } + else + { + + v->iqCh[0] = 0; + v->iqCh[1] = 0; + v->iqCh[2] = 0; + + check_brocken_phase(v); + + } + } + +// if (brocken_i_out & 0x1) +// error.power_errors.bit.phase_a_brocken |= 1; +// if (brocken_i_out & 0x2) +// error.power_errors.bit.phase_b_brocken |= 1; +// if (brocken_i_out & 0x4) +// error.power_errors.bit.phase_c_brocken |= 1; +// +// if(is_errors()) set_err_state(); + + +// +// if (v->teta > CONST_IQ_2PI) { +// v->teta = CONST_IQ_2PI; +// } +// if(v->teta < 0) { +// v->teta = 0; +// } +// field_direction = calc_direction(v); +// if (v->iqImod < v->config.iqLevelZero) { +// clear_alg_vars(v); +// return 0; +// } +// +// if (_IQabs(v->iqIu) < v->config.iqLevelZero && +// _IQabs(v->iqIv + v->iqIw) < v->config.iqLevelZero && +// _IQabs(v->iqIv) > v->config.iqLevelZero && _IQabs(v->iqIw) > v->config.iqLevelZero) { +// err = calc_error_if_break(v, 0, field_direction); +// } else { +// v->latch_break_start[0] = 0; +// } +// if (_IQabs(v->iqIv) < v->config.iqLevelZero && +// _IQabs(v->iqIu + v->iqIw) < v->config.iqLevelZero && +// _IQabs(v->iqIu) > v->config.iqLevelZero && _IQabs(v->iqIw) > v->config.iqLevelZero) { +// err = calc_error_if_break(v, 1, field_direction); +// } else { +// v->latch_break_start[1] = 0; +// } +// if (_IQabs(v->iqIw) < v->config.iqLevelZero && +// _IQabs(v->iqIv + v->iqIu) < v->config.iqLevelZero && +// _IQabs(v->iqIv) > v->config.iqLevelZero && _IQabs(v->iqIu) > v->config.iqLevelZero) { +// err = calc_error_if_break(v, 2, field_direction); +// } else { +// v->latch_break_start[2] = 0; +// } + + return err; +} + + + + +void init_break2_phase(BREAK2_PHASE *v) +{ + v->config.iq_freq = _IQ(v->config.freq_pwm / v->config.norma_freq); + v->config.calc_const = _IQdiv(CONST_IQ_2PI, v->config.iq_freq); + v->return_brocken_code = 0; + + +} + +void clear_break2_phase(BREAK2_PHASE *v) +{ + + v->iqCh[0] = 0; + v->iqCh[1] = 0; + v->iqCh[2] = 0; + v->sum_brocken_out[0] = 0; + v->sum_brocken_out[1] = 0; + v->sum_brocken_out[2] = 0; + v->sum_brocken_out[3] = 0; + v->brocken_i_out = 0; + + v->return_brocken_code = 0; +} + + + + + diff --git a/Inu/Src2/551/main/detect_phase_break2.h b/Inu/Src2/551/main/detect_phase_break2.h new file mode 100644 index 0000000..c32608e --- /dev/null +++ b/Inu/Src2/551/main/detect_phase_break2.h @@ -0,0 +1,50 @@ +/* + * detect_phase_break2.h + * + * Created on: 10 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_DETECT_PHASE_BREAK2_H_ +#define SRC_MAIN_DETECT_PHASE_BREAK2_H_ + +#include "IQmathLib.h" + + +typedef struct { + _iq iqCh[3]; + _iq sum_brocken_out[4]; // 4 - . + _iq freq_signal; + + int brocken_i_out; + int return_brocken_code; + _iq plus_a; + + + struct { + unsigned int freq_pwm; + unsigned int norma_freq; + + _iq minimal_level; + _iq calc_const; + _iq iq_freq; + } config; + + int (*calc)(); + void (*init)(); + void (*clear_error)(); + +} BREAK2_PHASE; + +#define BREAK2_PHASE_DEFAULTS {{0,0,0},\ + {0,0,0,0},\ + 0,0,0,0,\ + 0,0,0,0,0, \ + calc_break2_phase, init_break2_phase, clear_break2_phase } + +void check_brocken_phase(BREAK2_PHASE *v); +int calc_break2_phase(BREAK2_PHASE *v); +void init_break2_phase(BREAK2_PHASE *v); +void clear_break2_phase(BREAK2_PHASE *v); + +#endif /* SRC_MAIN_DETECT_PHASE_BREAK2_H_ */ diff --git a/Inu/Src2/551/main/digital_filters.c b/Inu/Src2/551/main/digital_filters.c new file mode 100644 index 0000000..a94d46b --- /dev/null +++ b/Inu/Src2/551/main/digital_filters.c @@ -0,0 +1,103 @@ +/* + * digital_filters.c + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + + + +//////////////////////////////////////////////////////////////////// +unsigned int filter_digital_input(unsigned int prev_valus, unsigned int *c_plus, unsigned int max_wait, unsigned int flag) +{ + + if (flag) + { + if ((*c_plus)>=max_wait) + { + return 1; + } + else + { + (*c_plus)++; + return (prev_valus); + } + } + else + { + if ((*c_plus)==0) + { + return 0; + } + else + { + (*c_plus)--; + return (prev_valus); + } + } +} +/////////////////////////////////////////////////////////////////// +//TODO: may be move to detect_errors.c +unsigned int pause_detect_error(unsigned int *c_err, unsigned int max_wait,unsigned int flag) +{ + if (flag) + { + if ((*c_err)>=max_wait) + { + return 1; + } + else + { + (*c_err)++; + return 0; + } + } + else + { + (*c_err) = 0; + return 0; + + } + + + +} + + + +////////////////////////////////////////////////////////// + + + +unsigned int filter_err_count(unsigned int *counter, unsigned int max_errors, unsigned int err, unsigned int cmd) +{ + if (cmd==1) + { + (*counter) = 0; + return 0; + } + + if (err) + { + if ((*counter)>=max_errors) + return 1; + else + (*counter)++; + + return 0; + } + + if (err==0) + { + if ((*counter)==0) + return 0; + else + (*counter)--; + + return 0; + } + return 0; +} + + + diff --git a/Inu/Src2/551/main/digital_filters.h b/Inu/Src2/551/main/digital_filters.h new file mode 100644 index 0000000..bc24cac --- /dev/null +++ b/Inu/Src2/551/main/digital_filters.h @@ -0,0 +1,19 @@ +/* + * digital_filters.h + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef SRC_MAIN_DIGITAL_FILTERS_H_ +#define SRC_MAIN_DIGITAL_FILTERS_H_ + +unsigned int filter_digital_input(unsigned int prev_valus, unsigned int *c_plus, unsigned int max_wait, unsigned int flag); + +unsigned int pause_detect_error(unsigned int *c_err, unsigned int max_wait,unsigned int flag); + + +unsigned int filter_err_count(unsigned int *counter, unsigned int max_errors, unsigned int err, unsigned int cmd); + + +#endif /* SRC_MAIN_DIGITAL_FILTERS_H_ */ diff --git a/Inu/Src2/551/main/edrk_main.c b/Inu/Src2/551/main/edrk_main.c new file mode 100644 index 0000000..c89a473 --- /dev/null +++ b/Inu/Src2/551/main/edrk_main.c @@ -0,0 +1,2736 @@ +#include <281xEvTimersInit.h> +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mathlib.h" +#include "params_hwp.h" + +//#include "modbus_fill_table.h" + +#include "big_dsp_module.h" +#include "control_station.h" +#include "CAN_Setup.h" + +#include "global_time.h" +#include "IQmathLib.h" +#include "mathlib.h" + +#include "modbus_table_v2.h" +#include "oscil_can.h" +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "alg_pll.h" +#include "vector_control.h" +#include "CRC_Functions.h" +#include "RS_Functions.h" +#include "xp_project.h" +#include "sbor_shema.h" +#include "alarm_log_can.h" +#include "pwm_test_lines.h" +#include "master_slave.h" +#include "xp_write_xpwm_time.h" +#include "v_rotor_22220.h" +#include "log_to_memory.h" +#include "log_params.h" +#include "build_version.h" +#include "profile_interrupt.h" +#include "limit_power.h" +#include "pwm_logs.h" +#include "logs_hmi.h" +#include "alarm_log.h" +#include "can_protocol_ukss.h" + +#include "ukss_tools.h" +#include "another_bs.h" +#include "temper_p_tools.h" +#include "digital_filters.h" +#include "pll_tools.h" +#include "ramp_zadanie_tools.h" +#include "uom_tools.h" +#include "synhro_tools.h" + +#if (_SIMULATE_AC==1) +#include "sim_model.h" +#endif +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +//#pragma DATA_SECTION(ccc, ".slow_vars") +//int ccc[40] = {0,1,1,1,1,1,1,1,1,1, 1,1,1,1,1,1,1,1,1,1, 1,1,1,1,1,1,1,1,1,1, 1,1,1,1,1,1,1,1,1,1}; + + + +#pragma DATA_SECTION(f, ".slow_vars") +FLAG f = FLAG_DEFAULTS; + +int cur1=0; +int cur2=0; + +unsigned int old_time_edrk1 = 0, old_time_edrk2 = 0, prev_flag_special_mode_rs = 0; + +#pragma DATA_SECTION(edrk, ".slow_vars") +EDRK edrk = EDRK_DEFAULT; + + + + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +// PLUS, MINUS +// +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +void set_oborots_from_zadat4ik(void) +{ +static unsigned int old_time_edrk3 = 0, prev_PROVOROT; + + + if (!(detect_pause_milisec(100,&old_time_edrk3))) + return; + +} + + +////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +#define RASCEPITEL_MANUAL_ALWAYS_ON_2 1 // 1 +#define TIME_ON_OFF_FOR_IMITATION_RASCEPITEL 50 // 5 . +#define TIME_FILTER_UMP_SIGNALS 5 // 0.5 +#define TIME_FILTER_ALL_SIGNALS 5 // 0.5 + + +#pragma DATA_SECTION(count_wait_filter, ".slow_vars") +unsigned int count_wait_filter[16] = {0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0}; +unsigned int counter_imit_rascepitel = 0; + +void update_input_edrk(void) +{ + static unsigned int flag_imit_rascepitel = 0; + static int st1=0; + +// ANOTHER PCH + edrk.from_second_pch.bits.RASCEPITEL = !FROM_ING_ANOTHER_RASCEPITEL; + edrk.from_second_pch.bits.MASTER = FROM_ING_ANOTHER_MASTER_PCH; + + +// ING +#if (_FLOOR6==1) + + if (st1==0) + { + edrk.from_zadat4ik.all = 0; + edrk.from_vpu.all = 0; + + edrk.from_ing1.bits.ALL_KNOPKA_AVARIA = 0;//!FROM_ALL_KNOPKA_AVARIA; + edrk.from_ing1.bits.BLOCK_IZOL_AVARIA = 0;//!FROM_ING_BLOCK_IZOL_AVARIA; + edrk.from_ing1.bits.BLOCK_IZOL_NORMA = 1;//!FROM_ING_BLOCK_IZOL_NORMA; + edrk.from_ing1.bits.LOCAL_REMOUTE = 1;//0;//!FROM_ING_LOCAL_REMOUTE; + edrk.from_ing1.bits.NAGREV_ON = 1;//!FROM_ING_NAGREV_ON; + edrk.from_ing1.bits.NASOS_NORMA = 1;//!FROM_ING_NASOS_NORMA; + edrk.from_ing1.bits.NASOS_ON = 0;//!FROM_ING_NASOS_ON; + edrk.from_ing1.bits.OHLAD_UTE4KA_WATER = 0;//!FROM_ING_OHLAD_UTE4KA_WATER; + edrk.from_ing1.bits.UPC_24V_NORMA = 1;//!FROM_ING_UPC_24V_NORMA; + edrk.from_ing1.bits.OP_PIT_NORMA = 1;//!FROM_ING_OP_PIT_NORMA; + edrk.from_ing1.bits.VENTIL_ON = 0;//!FROM_ING_VENTIL_ON; + edrk.from_ing1.bits.VIPR_PREDOHR_NORMA = 1;//!FROM_ING_VIPR_PREDOHR_NORMA; + + edrk.from_ing1.bits.ZARYAD_ON = 0;//!FROM_ING_ZARYAD_ON; + edrk.from_ing1.bits.ZAZEML_OFF = 1;//!FROM_ING_ZAZEML_OFF; + edrk.from_ing1.bits.ZAZEML_ON = 0;//!FROM_ING_ZAZEML_ON; + + edrk.from_ing2.bits.KEY_MINUS = 0;//FROM_ING_OBOROTS_MINUS; + edrk.from_ing2.bits.KEY_PLUS = 0;//!FROM_ING_OBOROTS_PLUS; + edrk.from_ing2.bits.KEY_KVITIR = 0;//FROM_ING_LOCAL_KVITIR; + + edrk.from_ing2.bits.KEY_SBOR = 0;//FROM_ING_SBOR_SHEMA; + edrk.from_ing2.bits.KEY_RAZBOR = 0;//FROM_ING_RAZBOR_SHEMA; + + // edrk.from_ing1.bits.RASCEPITEL_ON = 0;//FROM_ING_RASCEPITEL_ON_OFF; + + // edrk.from_ing2.bits.SOST_ZAMKA = !edrk.to_ing.bits.BLOCK_KEY_OFF;//1;//!FROM_ING_SOST_ZAMKA; + + + // SHEMA + edrk.from_shema.bits.RAZBOR_SHEMA = 0;//FROM_BSU_RAZBOR_SHEMA; + edrk.from_shema.bits.SBOR_SHEMA = 0;//FROM_BSU_SBOR_SHEMA; + + edrk.from_shema.bits.ZADA_DISPLAY = 0;//!FROM_BSU_ZADA_DISPLAY; + edrk.from_shema.bits.SVU = 0;//!FROM_BSU_SVU; + // edrk.from_shema.bits.KNOPKA_AVARIA = FROM_ALL_KNOPKA_AVARIA; + edrk.from_shema.bits.QTV_ON_OFF = 0;//!FROM_SHEMA_QTV_ON_OFF; + edrk.from_shema.bits.UMP_ON_OFF = 0;//!FROM_SHEMA_UMP_ON_OFF; + edrk.from_shema.bits.READY_UMP = 1;//!FROM_SHEMA_READY_UMP; + edrk.from_shema.bits.SVU_BLOCK_QTV = 0;//!FROM_SVU_BLOCK_QTV; + st1 = 1; + } + + // + if (edrk.to_ing.bits.RASCEPITEL_ON) + flag_imit_rascepitel = 1; + if (edrk.to_ing.bits.RASCEPITEL_OFF) + flag_imit_rascepitel = 0; + + edrk.from_ing1.bits.RASCEPITEL_ON = imit_signals_rascepitel(&counter_imit_rascepitel, TIME_ON_OFF_FOR_IMITATION_RASCEPITEL, flag_imit_rascepitel, 0); + ///// + + + edrk.from_ing2.bits.SOST_ZAMKA = !edrk.to_ing.bits.BLOCK_KEY_OFF; + if (edrk.to_ing.bits.NASOS_2_ON || edrk.to_ing.bits.NASOS_1_ON) + { + edrk.from_ing1.bits.VENTIL_ON = 1; + edrk.from_ing1.bits.NASOS_ON = 1; + } + else + { + edrk.from_ing1.bits.VENTIL_ON = 0; + edrk.from_ing1.bits.NASOS_ON = 0; + } +#else + + + // ZADAT4IK + if (control_station.alive_control_station[CONTROL_STATION_ZADATCHIK_CAN]) + edrk.from_zadat4ik.all = Unites[ZADATCHIK_CAN][16]; + else + edrk.from_zadat4ik.all = 0; + + if (control_station.alive_control_station[CONTROL_STATION_VPU_CAN]) + edrk.from_vpu.all = Unites[VPU_CAN][16]; + else + edrk.from_vpu.all = 0; + + + + edrk.from_ing1.bits.ALL_KNOPKA_AVARIA = !FROM_ALL_KNOPKA_AVARIA; + edrk.from_ing1.bits.BLOCK_IZOL_AVARIA = !FROM_ING_BLOCK_IZOL_AVARIA; + edrk.from_ing1.bits.BLOCK_IZOL_NORMA = !FROM_ING_BLOCK_IZOL_NORMA; + edrk.from_ing1.bits.LOCAL_REMOUTE = !FROM_ING_LOCAL_REMOUTE; + edrk.from_ing1.bits.NAGREV_ON = !FROM_ING_NAGREV_ON; + edrk.from_ing1.bits.NASOS_NORMA = !FROM_ING_NASOS_NORMA; + edrk.from_ing1.bits.NASOS_ON = !FROM_ING_NASOS_ON; + edrk.from_ing1.bits.OHLAD_UTE4KA_WATER = !FROM_ING_OHLAD_UTE4KA_WATER; + edrk.from_ing1.bits.UPC_24V_NORMA = !FROM_ING_UPC_24V_NORMA; + edrk.from_ing1.bits.OP_PIT_NORMA = !FROM_ING_OP_PIT_NORMA; + edrk.from_ing1.bits.VENTIL_ON = !FROM_ING_VENTIL_ON; + edrk.from_ing1.bits.VIPR_PREDOHR_NORMA = !FROM_ING_VIPR_PREDOHR_NORMA; + + edrk.from_ing1.bits.ZARYAD_ON = !FROM_ING_ZARYAD_ON; + edrk.from_ing1.bits.ZAZEML_OFF = !FROM_ING_ZAZEML_OFF; + edrk.from_ing1.bits.ZAZEML_ON = !FROM_ING_ZAZEML_ON; + + edrk.from_ing2.bits.KEY_MINUS = FROM_ING_OBOROTS_MINUS; + edrk.from_ing2.bits.KEY_PLUS = !FROM_ING_OBOROTS_PLUS; + edrk.from_ing2.bits.KEY_KVITIR = FROM_ING_LOCAL_KVITIR; + + edrk.from_ing2.bits.KEY_SBOR = FROM_ING_SBOR_SHEMA; + edrk.from_ing2.bits.KEY_RAZBOR = FROM_ING_RAZBOR_SHEMA; + +#if(RASCEPITEL_MANUAL_ALWAYS_ON_2) + + // + if (edrk.to_ing.bits.RASCEPITEL_ON) + flag_imit_rascepitel = 1; + if (edrk.to_ing.bits.RASCEPITEL_OFF) + flag_imit_rascepitel = 0; + + edrk.from_ing1.bits.RASCEPITEL_ON = imit_signals_rascepitel(&counter_imit_rascepitel, TIME_ON_OFF_FOR_IMITATION_RASCEPITEL, flag_imit_rascepitel, 0); + +#else + edrk.from_ing1.bits.RASCEPITEL_ON = FROM_ING_RASCEPITEL_ON_OFF; +#endif + edrk.from_ing2.bits.SOST_ZAMKA = !FROM_ING_SOST_ZAMKA; + + +// SHEMA + edrk.from_shema.bits.RAZBOR_SHEMA = FROM_BSU_RAZBOR_SHEMA; + edrk.from_shema.bits.SBOR_SHEMA = FROM_BSU_SBOR_SHEMA; + + if (edrk.from_shema.bits.RAZBOR_SHEMA==1 && edrk.from_shema.bits.SBOR_SHEMA) + { + // + edrk.from_shema.bits.RAZBOR_SHEMA = 0; + edrk.from_shema.bits.SBOR_SHEMA = 0; + } + edrk.from_shema_filter.bits.RAZBOR_SHEMA = filter_digital_input( edrk.from_shema_filter.bits.RAZBOR_SHEMA, + &count_wait_filter[0], + TIME_FILTER_ALL_SIGNALS, + edrk.from_shema.bits.RAZBOR_SHEMA); + + + edrk.from_shema_filter.bits.SBOR_SHEMA = filter_digital_input( edrk.from_shema_filter.bits.SBOR_SHEMA, + &count_wait_filter[1], + TIME_FILTER_ALL_SIGNALS, + edrk.from_shema.bits.SBOR_SHEMA); + + edrk.from_shema.bits.ZADA_DISPLAY = !FROM_BSU_ZADA_DISPLAY; + edrk.from_shema_filter.bits.ZADA_DISPLAY = filter_digital_input( edrk.from_shema_filter.bits.ZADA_DISPLAY, + &count_wait_filter[2], + TIME_FILTER_ALL_SIGNALS, + edrk.from_shema.bits.ZADA_DISPLAY); + + edrk.from_shema.bits.SVU = !FROM_BSU_SVU; + edrk.from_shema_filter.bits.SVU = filter_digital_input( edrk.from_shema_filter.bits.SVU, + &count_wait_filter[3], + TIME_FILTER_ALL_SIGNALS, + edrk.from_shema.bits.SVU); + + +// edrk.from_shema.bits.KNOPKA_AVARIA = FROM_ALL_KNOPKA_AVARIA; + edrk.from_shema.bits.QTV_ON_OFF = !FROM_SHEMA_QTV_ON_OFF; + edrk.from_shema_filter.bits.QTV_ON_OFF = filter_digital_input( edrk.from_shema_filter.bits.QTV_ON_OFF, + &count_wait_filter[4], + TIME_FILTER_ALL_SIGNALS, + edrk.from_shema.bits.QTV_ON_OFF); + + + + /// FROM_SHEMA_UMP_ON_OFF +// edrk.local_ump_on_off = !FROM_SHEMA_UMP_ON_OFF; +// +// if (edrk.local_ump_on_off) +// { +// if (edrk.local_ump_on_off_count>=TIME_FILTER_UMP_SIGNALS) +// edrk.from_shema.bits.UMP_ON_OFF = 1; +// else +// edrk.local_ump_on_off_count++; +// } +// else +// { +// if (edrk.local_ump_on_off_count==0) +// edrk.from_shema.bits.UMP_ON_OFF = 0; +// else +// edrk.local_ump_on_off_count--; +// } +// +// + edrk.from_shema.bits.UMP_ON_OFF = !FROM_SHEMA_UMP_ON_OFF; + edrk.from_shema_filter.bits.UMP_ON_OFF = filter_digital_input( edrk.from_shema_filter.bits.UMP_ON_OFF, + &count_wait_filter[5], + TIME_FILTER_UMP_SIGNALS, + edrk.from_shema.bits.UMP_ON_OFF); + + + + + + + /// FROM_SHEMA_READY_UMP +// edrk.local_ready_ump = !FROM_SHEMA_READY_UMP; +// +// if (edrk.local_ready_ump) +// { +// if (edrk.local_ready_ump_count>=TIME_FILTER_UMP_SIGNALS) +// edrk.from_shema.bits.READY_UMP = 1; +// else +// edrk.local_ready_ump_count++; +// } +// else +// { +// if (edrk.local_ready_ump_count==0) +// edrk.from_shema.bits.READY_UMP = 0; +// else +// edrk.local_ready_ump_count--; +// } +// + + edrk.from_shema.bits.READY_UMP = !FROM_SHEMA_READY_UMP; + edrk.from_shema_filter.bits.READY_UMP = filter_digital_input( edrk.from_shema_filter.bits.READY_UMP, + &count_wait_filter[6], + TIME_FILTER_UMP_SIGNALS, + edrk.from_shema.bits.READY_UMP); + + + + edrk.from_shema.bits.SVU_BLOCK_QTV = !FROM_SVU_BLOCK_QTV; + edrk.from_shema_filter.bits.SVU_BLOCK_QTV = filter_digital_input( edrk.from_shema_filter.bits.SVU_BLOCK_QTV, + &count_wait_filter[7], + TIME_FILTER_ALL_SIGNALS, + edrk.from_shema.bits.SVU_BLOCK_QTV); + +#endif +} + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +void get_where_oborots(void) +{ + +//// if (CAN_timeout[get_real_out_mbox(MPU_TYPE_BOX,0)-1]==0) +// if (CAN_timeout[get_real_in_mbox(MPU_TYPE_BOX,0)]==0) +// { +// edrk.W_from_SVU = modbus_table_can_in[14].all; +// edrk.W_from_DISPLAY = modbus_table_can_in[16].all; +// } +// else +// { +// edrk.W_from_SVU = 0; +// edrk.W_from_DISPLAY = 0; +// } +// +// +// +// +// if (edrk.from_shema.bits.SVU) +// { +// edrk.W_from_all = edrk.W_from_SVU; +// edrk.W_from_ZADAT4IK = edrk.W_from_all; +// } +// else +// { +// if (edrk.from_shema.bits.ZADA_DISPLAY) +// { +// edrk.W_from_all = edrk.W_from_DISPLAY; +// edrk.W_from_ZADAT4IK = edrk.W_from_all; +// } +// else +// edrk.W_from_all = edrk.W_from_ZADAT4IK; +// } + +} + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// + +unsigned int toggle_status_lamp(unsigned int bb1, unsigned int flag) +{ + + if (bb1==1 && flag==0) + { + return 0; + } + + if (bb1==0 && flag==0) + { + return 0; + } + + if (bb1==1 && flag==1) + { + return 0; + } + + if (bb1==0 && flag==1) + { + return 1; + } + return 0; +} + +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +// +//////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////// +void update_output_edrk(void) +{ + unsigned int b; + static unsigned int time_toggle1=0,time_toggle2=0; + +//to ingetim + + TO_ING_NAGREV_OFF = !edrk.to_ing.bits.NAGREV_OFF; + TO_ING_NASOS_1_ON = !edrk.to_ing.bits.NASOS_1_ON; + TO_ING_NASOS_2_ON = !edrk.to_ing.bits.NASOS_2_ON; + // TO_ING_RESET_BLOCK_IZOL = !edrk.to_ing.bits.RESET_BLOCK_IZOL; + TO_ING_SMALL_LAMPA_AVARIA = edrk.to_ing.bits.SMALL_LAMPA_AVARIA; + + if (edrk.disable_rascepitel_work) + { + + } + else + { + TO_ING_RASCEPITEL_OFF = !edrk.to_ing.bits.RASCEPITEL_OFF; + TO_ING_RASCEPITEL_ON = !edrk.to_ing.bits.RASCEPITEL_ON; + } + +// ANOTHER PCH + TO_SECOND_PCH_MASTER = edrk.to_second_pch.bits.MASTER; + TO_SECOND_PCH_ALARM = !edrk.to_second_pch.bits.ALARM; + + + +//to_shema +// +//#if (ENABLE_USE_QTV==1) +// TO_STEND_QM_ON_INVERS = !edrk.to_shema.bits.QTV_ON; +//#endif + + + TO_ING_LAMPA_ZARYAD = !edrk.Status_Ready.bits.Batt; + TO_ING_ZARYAD_ON = !edrk.to_ing.bits.ZARYAD_ON; + TO_ING_BLOCK_KEY_OFF = !edrk.to_ing.bits.BLOCK_KEY_OFF; + +#if (MODE_QTV_UPRAVLENIE==1) + TO_SHEMA_QTV_ON_OFF = !edrk.to_shema.bits.QTV_ON_OFF; +#endif + + +#if (MODE_QTV_UPRAVLENIE==2) + TO_SHEMA_QTV_OFF = !edrk.to_shema.bits.QTV_OFF; + TO_SHEMA_QTV_ON = !edrk.to_shema.bits.QTV_ON; +#endif + + TO_SHEMA_ENABLE_QTV = !edrk.to_shema.bits.ENABLE_QTV; + TO_SHEMA_UMP_ON_OFF = !edrk.to_shema.bits.UMP_ON_OFF; + + + + + + + +//lamps APL +// if (edrk.Sbor)// && edrk.from_ing.bits2.GED_NAMAGNI4EN==0) +// { +// if (edrk.Status_Ready.bits.ready5==0) +// edrk.to_zadat4ik.APL_LAMS0.bits.SBOR_SIL_SHEMA = 1; +// else +// edrk.to_zadat4ik.APL_LAMS0.bits.SBOR_SIL_SHEMA = 0; +// } +// else +// { +// edrk.to_zadat4ik.APL_LAMS0.bits.SBOR_SIL_SHEMA = 0; +// } + + + + edrk.to_vpu.BIG_LAMS.bits.GOTOV2 = edrk.Status_Ready.bits.ready_final; + edrk.to_vpu.BIG_LAMS.bits.PEREGRUZKA = edrk.to_zadat4ik.BIG_LAMS.bits.OGRAN_POWER; + edrk.to_vpu.BIG_LAMS.bits.PODDERG_OBOROTS = 0;// + edrk.to_vpu.BIG_LAMS.bits.VPU = edrk.to_zadat4ik.APL_LAMS0.bits.OBOROT_VPU; + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +/////////////////////////////////////////////// +void update_lamp_alarm(void) +{ + if ((edrk.errors.e0.all) + || (edrk.errors.e1.all) + || (edrk.errors.e2.all) + || (edrk.errors.e3.all) + || (edrk.errors.e4.all) + || (edrk.errors.e5.all) + || (edrk.errors.e6.all) + || (edrk.errors.e7.all) + || (edrk.errors.e8.all) + || (edrk.errors.e9.all) + || (edrk.errors.e10.all) + || (edrk.errors.e11.all) + || (edrk.errors.e12.all) + ) + { + edrk.to_ing.bits.SMALL_LAMPA_AVARIA = 1; + // edrk.to_second_pch.bits.ALARM = 1; + edrk.summ_errors = 1; + edrk.Stop |= 1; + } + else + { + edrk.to_ing.bits.SMALL_LAMPA_AVARIA = 0; + edrk.to_second_pch.bits.ALARM = 0; + edrk.summ_errors = 0; + } + +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +#define TIME_WAIT_RELE_QTV_ON 30 //2 sec +#define TIME_WAIT_RELE_QTV_OFF 30 //2 sec + +#define TIME_WAIT_ANSWER_QTV_ON TIME_WAIT_ERROR_QTV //150 //15 sec +#define TIME_WAIT_ANSWER_QTV_OFF 50 //4 sec + +/////////////////////////////////////////////// +int qtv_on_off(unsigned int flag) +{ +static unsigned int time_wait_rele_on_qtv=0; +static unsigned int time_wait_rele_off_qtv=0; +static unsigned int time_wait_answer_on_qtv=0; +static unsigned int time_wait_answer_off_qtv=0; +static unsigned int count_err_on = 0; + + +int cmd_qtv=0;//,cmd_p2=0; +static int QTV_Ok = 0; +static int prev_error = 0; + + + cmd_qtv = 0; +// cmd_p2 = 0; + + if ( flag==1 && edrk.summ_errors==0) + { + cmd_qtv = 1; + } + else + { + cmd_qtv = 0; + } + + + + edrk.cmd_to_qtv = cmd_qtv; + + if (cmd_qtv) + { + edrk.to_shema.bits.ENABLE_QTV = 1; + edrk.to_shema.bits.QTV_OFF = 1; + + if ((pause_detect_error(&time_wait_rele_on_qtv,TIME_WAIT_RELE_QTV_ON,1)==0) && edrk.from_shema_filter.bits.QTV_ON_OFF==0) + { +#if (MODE_QTV_UPRAVLENIE==2) + edrk.to_shema.bits.QTV_ON = 1; +#endif +#if (MODE_QTV_UPRAVLENIE==1) + edrk.to_shema.bits.QTV_ON_OFF = 1; +#endif + } + else + edrk.to_shema.bits.QTV_ON = 0; + + + if (pause_detect_error(&time_wait_answer_on_qtv,TIME_WAIT_ANSWER_QTV_ON,1)==0) + { + + if (edrk.from_shema_filter.bits.QTV_ON_OFF==1) + QTV_Ok = 1; + + } + else + { + + // , + if (edrk.from_shema_filter.bits.QTV_ON_OFF==0) + { +#if (WORK_ON_STEND_D) + if (pause_detect_error(&count_err_on,TIME_WAIT_ANSWER_QTV_ON,1)) + { + edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER |= 1; + QTV_Ok = 0; + } +#else + edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER |= 1; + QTV_Ok = 0; +#endif + } + else + count_err_on = 0; + + } + + time_wait_rele_off_qtv = 0; + time_wait_answer_off_qtv = 0; + } + else + { + QTV_Ok = 0; + edrk.to_shema.bits.ENABLE_QTV = 0; + time_wait_rele_on_qtv = 0; + time_wait_answer_on_qtv = 0; + + edrk.to_shema.bits.QTV_ON = 0; + + edrk.to_shema.bits.QTV_ON_OFF = 0; + +// if (pause_detect_error(&time_wait_rele_off_qtv,TIME_WAIT_RELE_QTV_OFF,1)==0) +// edrk.to_shema.bits.QTV_OFF = 1; +// else + edrk.to_shema.bits.QTV_OFF = 0; + + + if (pause_detect_error(&time_wait_answer_off_qtv,TIME_WAIT_ANSWER_QTV_OFF,1)==0) + { + + } + else + { + if (edrk.from_shema_filter.bits.QTV_ON_OFF==1) + edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER |= 1; + } + + + if (prev_error!=edrk.summ_errors && edrk.summ_errors) + { + if (pause_detect_error(&time_wait_rele_off_qtv,TIME_WAIT_RELE_QTV_OFF,1)==1) + time_wait_rele_off_qtv = 0; + } + + + } + + prev_error = edrk.summ_errors; + return (QTV_Ok); + + +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +/////////////////////////////////////////////// +void detect_kvitir_from_all(void) +{ + + static int prev_kvitir=0; + + edrk.Kvitir = control_station.active_array_cmd[CONTROL_STATION_CMD_CHECKBACK] + || edrk.from_ing2.bits.KEY_KVITIR + || edrk.from_zadat4ik.bits.KVITIR; + + /* + if (edrk.RemouteFromRS) + edrk.Kvitir = edrk.KvitirRS; + + if (edrk.RemouteFromVPU) + edrk.Kvitir = edrk.KvitirVPU; + + if (edrk.RemouteFromDISPLAY) + edrk.Kvitir = edrk.from_display.bits.KVITIR;//edrk.KvitirDISPLAY; + + if (edrk.RemouteFromMPU) + edrk.Kvitir = edrk.KvitirMPU; +*/ + + if (edrk.Kvitir==1 && prev_kvitir==0) + { + + if (edrk.Status_Ready.bits.ready_final==0 && edrk.Go==0 && edrk.Stop == 1) + { + edrk.KvitirProcess = 1; + project.clear_errors_all_plates(); + clear_errors(); + edrk.KvitirProcess = 0; + } + clear_warnings(); + /* edrk.KvitirDISPLAY = 0; + edrk.KvitirVPU = 0; + edrk.KvitirMPU = 0; + edrk.KvitirSVU = 0; + edrk.KvitirRS = 0; + */ + } + + prev_kvitir = edrk.Kvitir; +} + +/////////////////////////////////////////////// +unsigned int get_ready_1(void) +{ + unsigned int r1, r2; + + + + if (project.cds_in[0].status == component_Ready + && project.cds_in[1].status == component_Ready + && project.cds_out[0].status == component_Ready + && project.cds_tk[0].status == component_Ready + && project.cds_tk[1].status == component_Ready + && project.cds_tk[2].status == component_Ready + && project.cds_tk[3].status == component_Ready + && project.adc[0].status == component_Ready + && project.adc[1].status == component_Ready + && project.hwp[0].status == component_Ready + ) + r2 = 1; + else + r2 = 0; + + + r1 = (edrk.ms.ready1 && edrk.from_ing1.bits.NASOS_NORMA + && edrk.from_ing1.bits.ZAZEML_ON==0 && edrk.from_ing1.bits.ZAZEML_OFF==1 + && edrk.from_ing1.bits.VIPR_PREDOHR_NORMA + && edrk.from_ing1.bits.BLOCK_IZOL_NORMA + && edrk.from_ing1.bits.OP_PIT_NORMA + && edrk.from_ing1.bits.UPC_24V_NORMA + && r2); + + return r1; + + +} +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + + + +void set_zadanie_u_charge(void) +{ + +// edrk.ZadanieU_Charge = edrk.ZadanieU_Charge_RS; + +// edrk.iq_ZadanieU_Charge = _IQ(edrk.ZadanieU_Charge/NORMA_ACP); + + if (edrk.zadanie.ZadanieU_Charge<=100) + { + edrk.iqMIN_U_ZPT = _IQ(-50.0/NORMA_ACP); + edrk.iqMIN_U_IN = _IQ(-50.0/NORMA_ACP); + } + else + { + + edrk.iqMIN_U_ZPT = _IQ(edrk.zadanie.ZadanieU_Charge*MIN_U_PROC/NORMA_ACP); + edrk.iqMIN_U_IN = _IQ(edrk.zadanie.ZadanieU_Charge*MIN_U_PROC/NORMA_ACP); + + } + + if (edrk.zadanie.ZadanieU_ChargeU_D_MAX_ERROR_GLOBAL) + edrk.iqMAX_U_ZPT_Global = U_D_MAX_ERROR_GLOBAL; + } + + edrk.iqMAX_U_ZPT = edrk.iqMAX_U_ZPT_Global;//_IQ(edrk.zadanie.ZadanieU_Charge*MAX_U_PROC/NORMA_ACP); + edrk.iqMAX_U_IN = _IQ(edrk.zadanie.ZadanieU_Charge*MAX_U_PROC/NORMA_ACP); + + edrk.zadanie.iq_set_break_level = _IQ(NOMINAL_U_BREAK_LEVEL/NORMA_ACP); + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +//////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +#define TIME_WAIT_SBOR_1 1 +#define TIME_WAIT_SBOR_2 3 + +void get_sumsbor_command(void) +{ + static unsigned int prev_SBOR_SHEMA = 0; + static unsigned int prev_SBOR_SHEMA_ANOTHER_BS = 0; + unsigned int SBOR_SHEMA_ANOTHER_BS = 0; + static unsigned int Sbor, first=1, w_sbor = 0, Sbor_f = 0; + + Sbor = edrk.SumSbor; + + if (Sbor == 0) + edrk.run_razbor_shema = 0; + + SBOR_SHEMA_ANOTHER_BS = read_cmd_sbor_from_bs(); + + // + if (edrk.Status_Ready.bits.ImitationReady2==0 && + control_station.active_array_cmd[CONTROL_STATION_CMD_CHARGE]==1 && (prev_SBOR_SHEMA==0) + && edrk.from_ing1.bits.ALL_KNOPKA_AVARIA==0 && edrk.summ_errors==0 + && control_station.active_array_cmd[CONTROL_STATION_CMD_UNCHARGE]==0 + ) + { + Sbor = 1; + } + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_UNCHARGE]==1 + // || edrk.from_shema_filter.bits.RAZBOR_SHEMA // + ) + { + edrk.run_razbor_shema = 1; + // Sbor = 0; + } + + + if (edrk.StartGEDfromZadanie==0 && edrk.run_razbor_shema) + Sbor = 0; + + +// ? + if (SBOR_SHEMA_ANOTHER_BS==0 && prev_SBOR_SHEMA_ANOTHER_BS==1) + { + Sbor = 0; + } + + prev_SBOR_SHEMA = control_station.active_array_cmd[CONTROL_STATION_CMD_CHARGE]; + + prev_SBOR_SHEMA_ANOTHER_BS = SBOR_SHEMA_ANOTHER_BS; + + + // ! + if (edrk.from_ing1.bits.ALL_KNOPKA_AVARIA || edrk.summ_errors) + { + Sbor = 0; + } + + if (Sbor) + { +// if (edrk.flag_second_PCH == 0) +// { +// if (w_sbor=40) + level_go_main = 0; + + +} +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +//#pragma CODE_SECTION(get_start_ged_from_zadanie,".fast_run"); +int get_start_ged_from_zadanie(void) +{ + + // uf const + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_UF_CONST) + { + if (edrk.zadanie.iq_fzad_rmp!=0 && edrk.zadanie.iq_kzad_rmp!=0) + return 1; + else + return 0; + } + else + // scalar oborots + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_SCALAR_OBOROTS) + { + if (edrk.MasterSlave==MODE_SLAVE) + { + if (edrk.zadanie.iq_Izad_rmp!=0 + && edrk.zadanie.iq_limit_power_zad_rmp!=0) + return 1; + else + return 0; + } + else + { + if (edrk.zadanie.iq_oborots_zad_hz_rmp!=0 && edrk.zadanie.iq_Izad_rmp!=0 + && edrk.zadanie.iq_power_zad_rmp!=0 && edrk.zadanie.iq_limit_power_zad_rmp!=0) + return 1; + else + return 0; + } + } + else + // scalar power + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_SCALAR_POWER) + { + if (edrk.zadanie.iq_oborots_zad_hz_rmp!=0 && edrk.zadanie.iq_Izad_rmp!=0 + && edrk.zadanie.iq_power_zad_rmp!=0 && edrk.zadanie.iq_limit_power_zad_rmp!=0) + return 1; + else + return 0; + } + else + // foc oborots + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_OBOROTS) + { + if (edrk.zadanie.iq_oborots_zad_hz_rmp!=0 && edrk.zadanie.iq_Izad_rmp!=0 + && edrk.zadanie.iq_power_zad_rmp!=0 && edrk.zadanie.iq_limit_power_zad_rmp!=0) + return 1; + else + return 0; + } + else + // foc power + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER) + { + if (edrk.zadanie.iq_oborots_zad_hz_rmp!=0 && edrk.zadanie.iq_Izad_rmp!=0 + && edrk.zadanie.iq_power_zad_rmp!=0 && edrk.zadanie.iq_limit_power_zad_rmp!=0) + return 1; + else + return 0; + } + else + { + return 0; + } + +} +////////////////////////////////////////////////////////// + + +void cross_stend_automats(void) +{ + unsigned int g; + + edrk.to_shema.bits.CROSS_UMP_ON_OFF = 0; + edrk.to_shema.bits.CROSS_QTV_ON_OFF = 0; + +} + + + + +#define MAX_ERRORS_DETECT_CHANGE_ACTIVE_CONTROL 50 +void check_change_post_upravl(void) +{ + static int prev_active_post_upravl = -1, prev_active_post_upravl_another_bs = -1; + int active_post_upravl = -1, active_post_upravl_another_bs = -1; + static unsigned int count_err = 0; + + + active_post_upravl = get_code_active_post_upravl(); + active_post_upravl_another_bs = edrk.active_post_upravl_another_bs; + + + if (edrk.Status_Ready.bits.ready_final && edrk.Ready2_another_bs) + { + if ((active_post_upravl_another_bs==0 || active_post_upravl==0) && (active_post_upravl==2 || active_post_upravl_another_bs==2)) + { + // - + edrk.errors.e9.bits.CHANGE_ACTIVE_CONTROL_TO_LOCAL_FROM_SVU |= + filter_err_count(&count_err, + MAX_ERRORS_DETECT_CHANGE_ACTIVE_CONTROL, + 1, + 0); + } + else + count_err = 0; + } + + + prev_active_post_upravl = active_post_upravl; + prev_active_post_upravl_another_bs = active_post_upravl_another_bs; + + edrk.active_post_upravl = active_post_upravl; +} + + +int get_code_active_post_upravl(void) +{ + + if (control_station.active_control_station[CONTROL_STATION_TERMINAL_RS232]) + return 3; + else + if (control_station.active_control_station[CONTROL_STATION_TERMINAL_CAN]) + return 4; + else + if (control_station.active_control_station[CONTROL_STATION_INGETEAM_PULT_RS485])//(edrk.RemouteFromDISPLAY) + return 0; + else + if (control_station.active_control_station[CONTROL_STATION_MPU_KEY_CAN]) + return 5; + else + if (control_station.active_control_station[CONTROL_STATION_ZADATCHIK_CAN]) + return 6; + else + if (control_station.active_control_station[CONTROL_STATION_VPU_CAN]) + return 1; + else + if (control_station.active_control_station[CONTROL_STATION_MPU_SVU_CAN]) + return 2; + else + return 10; //error +} + + + + +#define MAX_COUNT_DETECTS_ZERO_U_ZPT 5 + +void auto_detect_zero_u_zpt(void) +{ + static unsigned int old_time_u_zpt1=0, count_detects = 0, flag_detect_zero_u_zpt = 0; + + static _iq prev_uzpt1=0; + static _iq prev_uzpt2=0; + static _iq delta_u = _IQ(3.0/NORMA_ACP); + static _iq minimal_detect_u = _IQ(40.0/NORMA_ACP); + + + + if (edrk.SumSbor==0 && flag_detect_zero_u_zpt==0) + { + // , Uzpt + if (detect_pause_sec(5,&old_time_u_zpt1)) + { + if ( filter.iqU_1_long>=minimal_detect_u || + filter.iqU_2_long>=minimal_detect_u || + (prev_uzpt1-filter.iqU_1_long)>=delta_u || + (prev_uzpt2-filter.iqU_2_long)>=delta_u ) + { + // + count_detects = 0; + } + else + { + if (count_detects=0) + { + if (local_oborots>max_oborots) + local_oborots = max_oborots; + } + else + { + if (local_oborots<-max_oborots) + local_oborots = -max_oborots; + } + + float_oborots = zad_intensiv(1.0, 1.0, float_oborots, local_oborots); + + edrk.oborots = float_oborots; + edrk.power_kw = edrk.oborots * koef_p3/(edrk.count_bs_work+1); + + + + +// +// max_oborots = edrk.zadanie.limit_power_zad/koef_p2; +// max_oborots = my_satur_float(max_oborots,MAX_ZADANIE_OBOROTS_ROTOR,MIN_ZADANIE_OBOROTS_ROTOR, 0); +// +// local_oborots = fast_round(_IQtoF(edrk.zadanie.rmp_oborots_imitation_rmp)*60.0*NORMA_FROTOR); +// if (local_oborots>=0) +// { +// if (local_oborots>max_oborots) +// local_oborots = max_oborots; +// } +// else +// { +// if (local_oborots<-max_oborots) +// local_oborots = -max_oborots; +// } + + } + else + { + + local_power = fast_round(_IQtoF(edrk.zadanie.iq_power_zad_rmp) * NORMA_ACP * NORMA_ACP / 1000.0); + if (edrk.count_bs_work==0) + local_power = my_satur_float(local_power, MAX_ZADANIE_POWER/2, MIN_ZADANIE_POWER/2, 0); + else + local_power = my_satur_float(local_power, MAX_ZADANIE_POWER, MIN_ZADANIE_POWER, 0); + + local_oborots = local_power/koef_p3; + float_oborots = zad_intensiv(1.0, 1.0, float_oborots, local_oborots); + edrk.oborots = float_oborots; + edrk.power_kw = local_power/(edrk.count_bs_work+1);//edrk.oborots * koef_p3; + +// local_power = fast_round(_IQtoF(edrk.zadanie.iq_power_zad_rmp) * NORMA_ACP * NORMA_ACP / 1000.0); +// local_oborots = local_power/koef_p1; + } + + +// float_oborots = zad_intensiv(0.5, 0.5, float_oborots, local_oborots); +// edrk.oborots = float_oborots; +// +// if (edrk.oborots>=0) +// edrk.power_kw = edrk.oborots * koef_p2; +// else +// edrk.power_kw = edrk.oborots * koef_p2; + +// +// +// +// if (edrk.oborots>=0) +// edrk.power_kw = edrk.oborots * koef_p; +// else +// edrk.power_kw = edrk.oborots * (+koef_p); + } + else + { + edrk.oborots = fast_round(_IQtoF(WRotor.iqWRotorSumFilter3)*60.0*NORMA_FROTOR); +// local_power = fast_round(_IQtoF(filter.PowerScalarFilter2) * NORMA_ACP * NORMA_ACP / 1000.0); +// +// if (edrk.oborots>=0) +// edrk.power_kw = local_power; +// else +// edrk.power_kw = -local_power; + + edrk.power_kw = fast_round(_IQtoF(edrk.iq_power_kw_one_filter_znak) * NORMA_ACP * NORMA_ACP / 1000.0); + } + + power_kw_full = edrk.power_kw + edrk.power_kw_another_bs; + +// if (power_kw_full < MINIMAL_POWER_TO_DISPLAY) +// edrk.power_kw_full = 0; +// else + edrk.power_kw_full = power_kw_full; + /////////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////////// + + + + edrk.Status_Ready.bits.ready1 = get_ready_1(); + + pump_control(); + + + if (control_station_select_active()) + { + + if (filter_count_error_control_station_select_active<30) + filter_count_error_control_station_select_active++; + else + edrk.errors.e7.bits.NOT_VALID_CONTROL_STATION |= 1; + } + else + filter_count_error_control_station_select_active = 0; + + edrk.current_active_control = get_current_station_control(); + + if (edrk.current_active_controlLEVEL_HWP_I_AF) level = LEVEL_HWP_I_AF; + if (level<0) level = 0; + + if (n_af == 0) + { + if (level != prev_level_all) + { + i_af_protect_d = convert_real_to_mv_hwp(2,level); + if (i_af_protect_d>1500) i_af_protect_d = 1500; // max 1500 mV + + update_maz_level_i_af(n_af, i_af_protect_d); + project.write_all_hwp(); + } + prev_level_all = level; + } +// else +// { +// if (level != prev_level_2) +// { +// i_af_protect_d = convert_real_to_mv_hwp(4,level); +// if (i_af_protect_d>1500) i_af_protect_d = 1500; // max 1500 mV +// +// update_maz_level_i_af(n_af, i_af_protect_d); +// project.write_all_hwp(); +// } +// prev_level_2 = level; +// +// } +} + + +void calc_count_build_revers(void) +{ + static unsigned int prev_b = 0, prev_r = 0; + + if (edrk.Status_Ready.bits.ImitationReady2) + { + detect_work_revers(((edrk.oborots>=0) ? 1 : -1), edrk.zadanie.iq_oborots_zad_hz_rmp, edrk.oborots); + } + else + detect_work_revers(WRotor.RotorDirectionSlow, edrk.zadanie.iq_oborots_zad_hz_rmp, WRotor.iqWRotorSumFilter2); + + if (edrk.count_revers != prev_r) + inc_count_revers(); + + if (edrk.count_sbor != prev_b) + inc_count_build(); + + prev_r = edrk.count_revers; + prev_b = edrk.count_sbor; + +} + + +void prepare_logger_pult(void) +{ + + edrk.pult_data.logger_params[0] = fast_round(_IQtoF(simple_scalar1.iq_decr_mzz_power_filter)*1000.0);//edrk.zadanie.oborots_zad; + edrk.pult_data.logger_params[1] = fast_round(_IQtoF(edrk.Kplus)*1000.0); + edrk.pult_data.logger_params[2] = fast_round(_IQtoF(pll1.vars.pll_Ud)*NORMA_ACP); + edrk.pult_data.logger_params[3] = fast_round(_IQtoF(edrk.f_stator)*NORMA_FROTOR*100.0); + edrk.pult_data.logger_params[4] = fast_round(_IQtoF(edrk.k_stator1)*10000.0); + edrk.pult_data.logger_params[5] = fast_round(_IQtoF(pll1.vars.pll_Uq)*NORMA_ACP); + edrk.pult_data.logger_params[6] = edrk.period_calc_pwm_int2; + edrk.pult_data.logger_params[7] = fast_round(_IQtoF(simple_scalar1.pidF.OutMax)*NORMA_ACP);//edrk.power_kw_full; + edrk.pult_data.logger_params[8] = edrk.Sbor_Mode; + edrk.pult_data.logger_params[9] = edrk.Stage_Sbor; + edrk.pult_data.logger_params[10] = fast_round(_IQtoF(edrk.Izad_out)*NORMA_ACP); + edrk.pult_data.logger_params[11] = edrk.period_calc_pwm_int1; + edrk.pult_data.logger_params[12] = fast_round(_IQtoF(simple_scalar1.pidF.Out)*NORMA_ACP); + edrk.pult_data.logger_params[13] = fast_round(_IQtoF(simple_scalar1.pidF.OutMin)*NORMA_ACP); + edrk.pult_data.logger_params[14] = fast_round(_IQtoF(simple_scalar1.pidPower.Out)*NORMA_ACP); + edrk.pult_data.logger_params[15] = fast_round(_IQtoF(simple_scalar1.pidPower.OutMax)*NORMA_ACP); + edrk.pult_data.logger_params[16] = fast_round(_IQtoF(simple_scalar1.pidF.Ref)*NORMA_FROTOR*1000.0);// //modbus_table_can_in[123].all;// ( , ) + edrk.pult_data.logger_params[17] = modbus_table_can_in[124].all;// () + edrk.pult_data.logger_params[18] = modbus_table_can_in[125].all;// () + edrk.pult_data.logger_params[19] = modbus_table_can_in[134].all;// + edrk.pult_data.logger_params[20] = fast_round(_IQtoF(simple_scalar1.bpsi_curent)*NORMA_FROTOR*1000.0); + edrk.pult_data.logger_params[21] = fast_round(_IQtoF(edrk.from_uom.iq_level_value_kwt)*NORMA_ACP*NORMA_ACP/1000.0); + edrk.pult_data.logger_params[22] = fast_round(_IQtoF(simple_scalar1.iqKoefOgran)*1000.0);//fast_round(_IQtoF(rotor_22220.iqFout)*NORMA_FROTOR*1000.0); + edrk.pult_data.logger_params[23] = fast_round(_IQtoF(simple_scalar1.iqKoefOgranIzad)*1000.0); //fast_round(_IQtoF(edrk.zadanie.iq_limit_power_zad)*NORMA_ACP*NORMA_ACP/1000.0); + edrk.pult_data.logger_params[24] = fast_round(_IQtoF(edrk.all_limit_koeffs.sum_limit)*1000.0); + edrk.pult_data.logger_params[25] = fast_round(_IQtoF(edrk.all_limit_koeffs.uom_limit)*1000.0); + edrk.pult_data.logger_params[26] = fast_round(_IQtoF(edrk.all_limit_koeffs.uin_freq_limit)*1000.0); + edrk.pult_data.logger_params[27] = fast_round(_IQtoF(simple_scalar1.pidF.Fdb)*NORMA_FROTOR*1000.0); // + + +} + + +int calc_auto_moto_pump(void) +{ + volatile long sum_minutes_pump1, sum_minutes_pump2, set_delta_minutes, cur_delta_minutes; + + + sum_minutes_pump1 = 0; + if (edrk.pult_data.data_from_pult.moto[12]>=0) + sum_minutes_pump1 += edrk.pult_data.data_from_pult.moto[12] * 1440; + if (edrk.pult_data.data_from_pult.moto[3]>=0) + sum_minutes_pump1 += edrk.pult_data.data_from_pult.moto[3]; + + sum_minutes_pump2 = 0; + if (edrk.pult_data.data_from_pult.moto[13]>=0) + sum_minutes_pump2 += edrk.pult_data.data_from_pult.moto[13] * 1440; + if (edrk.pult_data.data_from_pult.moto[4]>=0) + sum_minutes_pump2 += edrk.pult_data.data_from_pult.moto[4]; + + cur_delta_minutes = sum_minutes_pump1 - sum_minutes_pump2; + + set_delta_minutes = edrk.pult_data.data_to_pult.TimeToChangePump; + + if (set_delta_minutes==0) + { + return 0; + } + + + if (cur_delta_minutes>set_delta_minutes) + { + return 2; + } + else + if (cur_delta_minutes<-set_delta_minutes) + { + return 1; + } + else + if (edrk.pult_data.data_from_pult.LastWorkPump==0) + { + if (cur_delta_minutes>0) + { + return 1; + } + else + if (cur_delta_minutes<=0) + { + return 2; + } + else + return 0; + } + else + { + if (edrk.pult_data.data_from_pult.LastWorkPump == 1) + return 1; + else + if (edrk.pult_data.data_from_pult.LastWorkPump == 2) + return 2; + else + return 0; + } +// +// +// if (cur_delta_minutes>0) +// { +// //T1>T2 +// if (_IQabs(cur_delta_minutes) >= set_delta_minutes) +// { +// // T1+delta>T2 +// return 2; +// } +// else +// return 1; +// } +// else +// { +// //T2>T1 +// if (_IQabs(cur_delta_minutes) >= set_delta_minutes) +// { +// //T2+delta>T1 +// return 1; +// } +// else +// return 2; +// } + +// if (_IQabs(cur_delta_minutes) > set_delta_minutes) +// { +// if (cur_delta_minutes>) +// return 2; +// else +// return 1; +// +// +// } +// if (cur_delta_minutes>=0) +// { +// if (_IQabs(cur_delta_minutes) > set_delta_minutes) +// return 2; +// else +// return 1; +// } +// else +// { +// if (_IQabs(cur_delta_minutes) > set_delta_minutes) +// return 1; +// else +// return 2; +// } + + + +} + + + +void read_can_error(void) +{ + EALLOW; + edrk.canes_reg = ECanaRegs.CANES.all; + edrk.canrec_reg = ECanaRegs.CANREC.all; + edrk.cantec_reg = ECanaRegs.CANTEC.all; + EDIS; + + cmd_clear_can_error(); + +} + + +void clear_can_error(void) +{ + // EALLOW; + + // ECanaRegs.CANES.all=0xffffffff; + InitCanSoft(); + + //EDIS; + +} + +void cmd_clear_can_error(void) +{ + static int prev_cmd_clear_can_error = 0; + + if (edrk.cmd_clear_can_error && prev_cmd_clear_can_error==0) + { + clear_can_error(); + } + prev_cmd_clear_can_error = edrk.cmd_clear_can_error; + +} + + +void check_temper_break(void) +{ + + if ( (edrk.break_tempers[0] > ABNORMAL_TEMPER_BREAK_INT) + || (edrk.break_tempers[1] > ABNORMAL_TEMPER_BREAK_INT) + || (edrk.break_tempers[2] > ABNORMAL_TEMPER_BREAK_INT) + || (edrk.break_tempers[3] > ABNORMAL_TEMPER_BREAK_INT) + ) + edrk.warnings.e9.bits.BREAK_TEMPER_WARNING = 1; + else + { + if ( (edrk.break_tempers[0] < ABNORMAL_TEMPER_BREAK_INT-DELTA_TEMPER_BREAK_INT) + && (edrk.break_tempers[1] < ABNORMAL_TEMPER_BREAK_INT-DELTA_TEMPER_BREAK_INT) + && (edrk.break_tempers[2] < ABNORMAL_TEMPER_BREAK_INT-DELTA_TEMPER_BREAK_INT) + && (edrk.break_tempers[3] < ABNORMAL_TEMPER_BREAK_INT-DELTA_TEMPER_BREAK_INT) + ) + edrk.warnings.e9.bits.BREAK_TEMPER_WARNING = 0; + } + + + if ( (edrk.break_tempers[0] > ALARM_TEMPER_BREAK_INT) + || (edrk.break_tempers[1] > ALARM_TEMPER_BREAK_INT) + || (edrk.break_tempers[2] > ALARM_TEMPER_BREAK_INT) + || (edrk.break_tempers[3] > ALARM_TEMPER_BREAK_INT) + ) + edrk.warnings.e9.bits.BREAK_TEMPER_ALARM = 1; + else + { + //DELTA_TEMPER_BREAK_INT + if ( (edrk.break_tempers[0] < ALARM_TEMPER_BREAK_INT-DELTA_TEMPER_BREAK_INT) + && (edrk.break_tempers[1] < ALARM_TEMPER_BREAK_INT-DELTA_TEMPER_BREAK_INT) + && (edrk.break_tempers[2] < ALARM_TEMPER_BREAK_INT-DELTA_TEMPER_BREAK_INT) + && (edrk.break_tempers[3] < ALARM_TEMPER_BREAK_INT-DELTA_TEMPER_BREAK_INT) + ) + edrk.warnings.e9.bits.BREAK_TEMPER_ALARM = 0; + } + +} + +#define TIME_FILTER_BREAKER_SIGNALS 10 + +void check_breaker_ged(void) +{ + static unsigned int count_wait_breaker = 0; + + edrk.warnings.e9.bits.BREAKER_GED_ON = filter_digital_input( edrk.warnings.e9.bits.BREAKER_GED_ON, + &count_wait_breaker, + TIME_FILTER_BREAKER_SIGNALS, + edrk.breaker_on); + +// if (edrk.breaker_on) +// edrk.warnings.e9.bits.BREAKER_GED_ON = 1; +// else +// edrk.warnings.e9.bits.BREAKER_GED_ON = 0; + +} diff --git a/Inu/Src2/551/main/edrk_main.h b/Inu/Src2/551/main/edrk_main.h new file mode 100644 index 0000000..435baca --- /dev/null +++ b/Inu/Src2/551/main/edrk_main.h @@ -0,0 +1,1838 @@ + +#ifndef _EDRK_MAIN_H__ +#define _EDRK_MAIN_H__ + + +#include "IQmathLib.h" +#include "rmp_cntl_v1.h" +#include "rmp_cntl_v2.h" + +#include "alg_pll.h" + + +#define TIME_PAUSE_MODBUS_CAN_BS2BS 500 //900 //500 +#define TIME_PAUSE_MODBUS_CAN_ZADATCHIK_VPU 250 //100//100 +#define TIME_PAUSE_MODBUS_CAN_UKSS_SETUP 2500 // +#define TIME_PAUSE_MODBUS_CAN_MPU 1100 //500 +#define TIME_PAUSE_MODBUS_CAN_TERMINALS 2000 //1000 +#define TIME_PAUSE_MODBUS_CAN_OSCIL 5000 + +//#define TIME_PAUSE_MODBUS_CAN_BS2BS 100//20//500 +//#define TIME_PAUSE_MODBUS_CAN_ZADATCHIK_VPU 250//20//100 +//#define TIME_PAUSE_MODBUS_CAN_UKSS_SETUP 5000 +//#define TIME_PAUSE_MODBUS_CAN_MPU 500//20//500 +//#define TIME_PAUSE_MODBUS_CAN_TERMINALS 1000 +//#define TIME_PAUSE_MODBUS_CAN_OSCIL 5000 + + +//#define TIME_PAUSE_MODBUS_CAN_TMS2TMS_VIPR 75 //500 + + + +//#define FROM_OPENDOOR project.cds_in[1].read.pbus.data_in.bit.in15 + + +// IN0 +#define SENSOR_ROTOR_1 project.cds_in[0].read.pbus.data_in.bit.in0 // 1 +#define SENSOR_ROTOR_2 project.cds_in[0].read.pbus.data_in.bit.in1 // 2 +#define SENSOR_ROTOR_3 project.cds_in[0].read.pbus.data_in.bit.in2 // 3 + +#define FROM_ING_LOCAL_REMOUTE project.cds_in[0].read.pbus.data_in.bit.in3 // LOCAL=0/REMOUTE=1 +#define FROM_ING_LOCAL_KVITIR project.cds_in[0].read.pbus.data_in.bit.in4 // + +#define FROM_BSU_RAZBOR_SHEMA project.cds_in[0].read.pbus.data_in.bit.in5 // =0 +#define FROM_BSU_SBOR_SHEMA project.cds_in[0].read.pbus.data_in.bit.in6 // =0 + +#define FROM_ING_RAZBOR_SHEMA project.cds_in[0].read.pbus.data_in.bit.in5 // =0 +#define FROM_ING_SBOR_SHEMA project.cds_in[0].read.pbus.data_in.bit.in6 // =0 + +#define FROM_ING_OBOROTS_MINUS project.cds_in[0].read.pbus.data_in.bit.in7 // +#define FROM_ING_OBOROTS_PLUS project.cds_in[0].read.pbus.data_in.bit.in8 // + + +#define FROM_BSU_ZADA_DISPLAY project.cds_in[0].read.pbus.data_in.bit.in9 // =1/=0 +#define FROM_BSU_SVU project.cds_in[0].read.pbus.data_in.bit.in10 // =0/=1 +#define FROM_SHEMA_QTV_ON_OFF ((project.cds_in[0].read.pbus.data_in.bit.in12)) + +// , . +#define FROM_SVU_BLOCK_QTV project.cds_in[0].read.pbus.data_in.bit.in11 // QTV + +#define FROM_ING_ANOTHER_RASCEPITEL 1//project.cds_in[0].read.pbus.data_in.bit.in12 // +#define FROM_SHEMA_UMP_ON_OFF project.cds_in[0].read.pbus.data_in.bit.in13 // + +#define FROM_SHEMA_READY_UMP project.cds_in[0].read.pbus.data_in.bit.in14 // +#define FROM_ING_RASCEPITEL_ON_OFF ((project.cds_in[0].read.pbus.data_in.bit.in15)) // + + + +///////////////// + +#define FROM_ING_OP_PIT_NORMA project.cds_in[1].read.pbus.data_in.bit.in0 // 0- +#define FROM_ING_OHLAD_UTE4KA_WATER !(project.cds_in[1].read.pbus.data_in.bit.in1) // // 1 - , 0 - +#define FROM_ING_SOST_ZAMKA project.cds_in[1].read.pbus.data_in.bit.in2 // +#define FROM_ING_ZARYAD_ON project.cds_in[1].read.pbus.data_in.bit.in3 // 1- + +#define FROM_ING_VENTIL_ON project.cds_in[1].read.pbus.data_in.bit.in4 // 0- +#define FROM_ING_NASOS_ON project.cds_in[1].read.pbus.data_in.bit.in5 // 0 - +#define FROM_ING_NASOS_NORMA project.cds_in[1].read.pbus.data_in.bit.in6 // 0? 0. +#define FROM_ING_ZAZEML_OFF project.cds_in[1].read.pbus.data_in.bit.in7 // 1-. +#define FROM_ING_NAGREV_ON project.cds_in[1].read.pbus.data_in.bit.in8 // 1- +#define FROM_ING_BLOCK_IZOL_NORMA project.cds_in[1].read.pbus.data_in.bit.in9 // . 1-. +#define FROM_ING_VIPR_PREDOHR_NORMA project.cds_in[1].read.pbus.data_in.bit.in10 // 0 - . +#define FROM_ING_BLOCK_IZOL_AVARIA project.cds_in[1].read.pbus.data_in.bit.in11 // . 0- +#define FROM_ALL_KNOPKA_AVARIA project.cds_in[1].read.pbus.data_in.bit.in12 // 1 - . +#define FROM_ING_ZAZEML_ON project.cds_in[1].read.pbus.data_in.bit.in13 // 0-. + +#define FROM_ING_ANOTHER_MASTER_PCH project.cds_in[1].read.pbus.data_in.bit.in14 // . + +#define FROM_ING_UPC_24V_NORMA project.cds_in[1].read.pbus.data_in.bit.in15 // 24 UPC 0-. + +//#define FROM_REZERV_12 project.cds_in[1].read.pbus.data_in.bit.in12 // + + + + +#define TO_ING_ZARYAD_ON project.cds_out[0].write.sbus.data_out.bit.dout0 // +#define TO_ING_NAGREV_OFF project.cds_out[0].write.sbus.data_out.bit.dout1 // +#define TO_ING_NASOS_1_ON project.cds_out[0].write.sbus.data_out.bit.dout2 // 1 +#define TO_ING_NASOS_2_ON project.cds_out[0].write.sbus.data_out.bit.dout3 // 2 +#define TO_ING_BLOCK_KEY_OFF project.cds_out[0].write.sbus.data_out.bit.dout4 // , + +#define TO_ING_RELOAD_UPC project.cds_out[0].write.sbus.data_out.bit.dout5 //5- + +#define TO_SHEMA_ENABLE_QTV project.cds_out[0].write.sbus.data_out.bit.dout6 // 6 - QTV +#define TO_ING_LAMPA_ZARYAD project.cds_out[0].write.sbus.data_out.bit.dout7 //7- 80 . + + + +#define MODE_QTV_UPRAVLENIE 2 // 1 - , 2 - + + +#if (MODE_QTV_UPRAVLENIE==1) +////////////////////////////////////////////////////////// +// QTV +#define TO_SHEMA_QTV_ON_OFF project.cds_out[0].write.sbus.data_out.bit.dout8 // 8 - QTV +#endif + + +#if (MODE_QTV_UPRAVLENIE==2) +// QTV +#define TO_SHEMA_QTV_ON project.cds_out[0].write.sbus.data_out.bit.dout8 // 8 - QTV +#define TO_SHEMA_QTV_OFF project.cds_out[0].write.sbus.data_out.bit.dout9 // 9 - QTV +/////////////////////////////////////////////////////////// +#endif + +#define TO_ING_SMALL_LAMPA_AVARIA project.cds_out[0].write.sbus.data_out.bit.dout10 // + +#define TO_SECOND_PCH_ALARM project.cds_out[0].write.sbus.data_out.bit.dout11 // 11 - . +#define TO_SECOND_PCH_MASTER project.cds_out[0].write.sbus.data_out.bit.dout12 // 12 - - . + +#define TO_SHEMA_UMP_ON_OFF project.cds_out[0].write.sbus.data_out.bit.dout13 // 13 - +#define TO_ING_RASCEPITEL_OFF project.cds_out[0].write.sbus.data_out.bit.dout14// 14- +#define TO_ING_RASCEPITEL_ON project.cds_out[0].write.sbus.data_out.bit.dout15// 15 - + + + +enum +{ + ALG_MODE_UF_CONST = 1, + ALG_MODE_SCALAR_OBOROTS, + ALG_MODE_SCALAR_POWER, + ALG_MODE_FOC_OBOROTS, + ALG_MODE_FOC_POWER +}; + + +enum +{ + STAGE_SBOR_STATUS_NO_STATUS = 0, + STAGE_SBOR_STATUS_FIRST, + STAGE_SBOR_STATUS_PUMP, + STAGE_SBOR_STATUS_ZARYAD, + STAGE_SBOR_STATUS_UMP_ON, + STAGE_SBOR_STATUS_QTV, + STAGE_SBOR_STATUS_UMP_OFF, + STAGE_SBOR_STATUS_RASCEPITEL_1, + STAGE_SBOR_STATUS_RASCEPITEL_2, + STAGE_SBOR_STATUS_RASCEPITEL_3, + STAGE_SBOR_STATUS_RASCEPITEL_4, + STAGE_SBOR_STATUS_WAIT_READY_ANOTHER, + STAGE_SBOR_STATUS_FINISH +}; + +/* + + + + + +#define TO_ING_KVITIR project.cds_out[0].write.sbus.data_out.bit.dout3 +#define TO_QTV_OFF project.cds_out[0].write.sbus.data_out.bit.dout4 + +#define TO_ING_VOZB_PODKLU4EN project.cds_out[0].write.sbus.data_out.bit.dout5 +#define TO_ING_VOZB_NEPODKLU4EN project.cds_out[0].write.sbus.data_out.bit.dout6 +#define TO_ING_VOZB_READY project.cds_out[0].write.sbus.data_out.bit.dout7 + + + +#define TO_ING_QTV_VLU4EN project.cds_out[0].write.sbus.data_out.bit.dout9 +#define TO_ING_QTV_READY project.cds_out[0].write.sbus.data_out.bit.dout10 +#define TO_ING_START_GED project.cds_out[0].write.sbus.data_out.bit.dout11 +#define TO_ING_SIL_BLOK_OTKL project.cds_out[0].write.sbus.data_out.bit.dout12 +#define TO_ING_SIL_BLOK_VKL project.cds_out[0].write.sbus.data_out.bit.dout13 +#define TO_ING_BLOK_VOZB_WORK project.cds_out[0].write.sbus.data_out.bit.dout15 +#define TO_ING_OSTANOV_GED project.cds_out[0].write.sbus.data_out.bit.dout14 + + + +#define FROM_ING_SIL_BLOK_VKL project.cds_in[1].read.pbus.data_in.bit.in0 +#define FROM_ING_SIL_BLOK_OTKL project.cds_in[1].read.pbus.data_in.bit.in1 +#define FROM_ING_GED_NAMAGNI4EN project.cds_in[1].read.pbus.data_in.bit.in2 +#define FROM_ING_GED_OSTANOVLEN project.cds_in[1].read.pbus.data_in.bit.in3 +#define FROM_ING_QTV_ON project.cds_in[1].read.pbus.data_in.bit.in4 +#define FROM_ING_QTV_OFF project.cds_in[1].read.pbus.data_in.bit.in5 +#define FROM_ING_VOZB_PODKLU4IT project.cds_in[1].read.pbus.data_in.bit.in6 +#define FROM_ING_VOZB_OTKLU4IT project.cds_in[1].read.pbus.data_in.bit.in7 +#define FROM_ING_VOZB_PUSK project.cds_in[1].read.pbus.data_in.bit.in8 + +*/ + +typedef struct +{ + int adc_temper_u[7]; + float real_temper_u[7]; + int real_int_temper_u[7]; + int max_real_int_temper_u; + + int adc_temper_water[2]; + float real_temper_water[2]; + int real_int_temper_water[2]; //0 - internal; 1 - external + int max_real_int_temper_water; + + int adc_temper_air[4]; + float real_temper_air[4]; + int real_int_temper_air[4]; + int max_real_int_temper_air; + int min_real_int_temper_air; + + + + +} TEMPER_EDRK; +#define TEMPER_EDRK_DEFAULT {{0,0,0,0,0,0,0},{0,0,0,0,0,0,0},{0,0,0,0,0,0,0},0,\ + {0,0},{0,0},{0,0},0,\ + {0,0,0,0},{0,0,0,0},{0,0,0,0},0,0\ + } + + +typedef struct +{ + int adc_p_water[1]; + float real_p_water[1]; + int real_int_p_water[1]; + float filter_real_p_water[1]; + int filter_real_int_p_water[1]; + int flag_init_filter_temp[1]; + +} P_WATER_EDRK; +#define P_WATER_EDRK_DEFAULT {{0},{0},{0},{0},{0},{0}} + + + +typedef struct +{ + + struct + { + int adc_temper[6]; + float real_temper[6]; + int real_int_temper[6]; + float filter_real_temper[6]; + int filter_real_int_temper[6]; + int flag_init_filter_temp[6]; + int max_size; + int max_real_int_temper; + } winding; + + struct + { + int adc_temper[2]; + float real_temper[2]; + int real_int_temper[2]; + float filter_real_temper[2]; + int filter_real_int_temper[2]; + int flag_init_filter_temp[2]; + int max_size; + int max_real_int_temper; + } bear; + +} TEMPER_ACDRIVE; + +#define TEMPER_ACDRIVE_DEFAULT {{{0,0,0,0,0,0},{0,0,0,0,0,0},{0,0,0,0,0,0},{0,0,0,0,0,0},{0,0,0,0,0,0},{0,0,0,0,0,0},6,0},\ + {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},2,0} } +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// + +typedef struct +{ + union { + unsigned int all; + struct { + unsigned int U_1_MAX: 1; + unsigned int U_2_MAX: 1; + unsigned int U_1_MIN: 1; + unsigned int U_2_MIN : 1; + + unsigned int U_A1B1_MAX: 1; + unsigned int U_A2B2_MAX: 1; + unsigned int U_B1C1_MAX:1; + unsigned int U_B2C2_MAX :1; + + unsigned int U_A1B1_MIN :1; + unsigned int U_A2B2_MIN: 1; + unsigned int U_B1C1_MIN:1; + unsigned int U_B2C2_MIN :1; + + unsigned int U_IN_MAX:1; + unsigned int U_IN_MIN:1; + unsigned int I_1_MAX:1; + unsigned int I_2_MAX:1; + + } bits; + } e0; + + union { + unsigned int all; + struct { + unsigned int I_UO2_MAX: 1; + unsigned int I_UO3_MAX: 1; + unsigned int I_UO4_MAX: 1; + unsigned int I_UO5_MAX : 1; + + unsigned int I_UO6_MAX: 1; + unsigned int I_UO7_MAX: 1; + unsigned int I_BREAK_1_MAX:1; + unsigned int I_BREAK_2_MAX :1; + + unsigned int HWP_ERROR :1; + + unsigned int BLOCK_DOOR: 1; + unsigned int NO_INPUT_SYNC_SIGNAL: 1; + unsigned int NO_CONFIRM_ON_RASCEPITEL: 1; + + unsigned int ANOTHER_BS_NOT_ON_RASCEPITEL: 1; + unsigned int ANOTHER_BS_VERY_LONG_WAIT: 1; + unsigned int VERY_LONG_BOTH_READY2: 1; + unsigned int BOTH_KEYS_CHARGE_DISCHARGE: 1; + + + } bits; + } e1; + + + union { + unsigned int all; + struct { + unsigned int T_UO1_MAX:1; + unsigned int T_UO2_MAX :1; + unsigned int T_UO3_MAX :1; + unsigned int T_UO4_MAX :1; + + unsigned int T_UO5_MAX :1; + unsigned int T_UO6_MAX:1; + unsigned int T_UO7_MAX:1; + unsigned int T_WATER_EXT_MAX:1; + + unsigned int T_WATER_INT_MAX:1; + unsigned int P_WATER_INT_MAX: 1; + unsigned int P_WATER_INT_MIN: 1; + unsigned int T_AIR0_MAX :1; + + unsigned int T_AIR1_MAX :1; + unsigned int T_AIR2_MAX :1; + unsigned int T_AIR3_MAX :1; + unsigned int ERROR_RAZBOR_SHEMA :1; + + + } bits; + } e2; + + + union { + unsigned int all; + struct { + unsigned int NOT_READY_TK_0: 1; + unsigned int NOT_READY_TK_1 : 1; + unsigned int NOT_READY_TK_2: 1; + unsigned int NOT_READY_TK_3: 1; + + unsigned int NOT_READY_OUT_0:1; + unsigned int NOT_READY_OUT_1:1; + unsigned int NOT_READY_OUT_2:1; + unsigned int NOT_READY_IN_0 :1; + + unsigned int NOT_READY_IN_1 :1; + unsigned int NOT_READY_IN_2 :1; + unsigned int NOT_READY_ADC_0: 1; + unsigned int NOT_READY_ADC_1: 1; + + unsigned int NOT_READY_HWP_0: 1; + unsigned int NOT_READY_HWP_1: 1; + unsigned int NOT_READY_CONTR: 1; + unsigned int ERR_INT_PWM_LONG:1; + + + } bits; + } e3; + + + union { + unsigned int all; + struct { + + unsigned int ERR_TK_0: 1; + unsigned int ERR_TK_1: 1; + unsigned int ERR_TK_2: 1; + unsigned int ERR_TK_3: 1; + + unsigned int ERR_OUT_0:1; + unsigned int ERR_OUT_1:1; + unsigned int ERR_OUT_2:1; + unsigned int ERR_IN_0 :1; + + unsigned int ERR_IN_1 :1; + unsigned int ERR_IN_2 :1; + unsigned int ERR_ADC_0:1; + unsigned int ERR_ADC_1:1; + + unsigned int ERR_HWP_0:1; + unsigned int ERR_HWP_1:1; + unsigned int ANOTHER_BS_POWER_OFF:1; + unsigned int FAST_OPTICAL_ALARM:1; + } bits; + } e4; + + union { + unsigned int all; + struct { + + unsigned int LINE_ERR0: 1; + unsigned int LINE_HWP : 1; + unsigned int KEY_AVARIA: 1; + unsigned int PUMP_1: 1; + + unsigned int PUMP_2 : 1; + unsigned int FAN : 1; + unsigned int OP_PIT : 1; + unsigned int POWER_UPC :1; + + unsigned int UTE4KA_WATER :1; + unsigned int T_VIPR_MAX :1; + unsigned int ERROR_PRE_CHARGE_ON: 1; + unsigned int PRE_READY_PUMP: 1; + + unsigned int ERROR_GROUND_NET: 1; + unsigned int ERROR_HEAT: 1; + unsigned int ERROR_ISOLATE: 1; + unsigned int ERROR_PRED_VIPR: 1; + + + } bits; + } e5; + + union { + unsigned int all; + struct { + + unsigned int QTV_ERROR_NOT_ANSWER: 1; + unsigned int QTV_ERROR_NOT_U : 1; + unsigned int ERROR_PRE_CHARGE_U: 1; + unsigned int ERROR_PRE_CHARGE_ANSWER: 1; + + unsigned int UO2_KEYS :1; + unsigned int UO3_KEYS :1; + unsigned int UO4_KEYS :1; + unsigned int UO5_KEYS :1; + + unsigned int UO6_KEYS:1; + unsigned int UO7_KEYS:1; + unsigned int UO1_KEYS:1; + unsigned int ERR_PBUS:1; + + unsigned int ERR_SBUS:1; + unsigned int ER_DISBAL_BATT:1; + unsigned int ER_RAZBALANS_ALG:1; + unsigned int RASCEPITEL_ERROR_NOT_ANSWER:1; + + } bits; + } e6; + + union { + unsigned int all; + struct { + + unsigned int MASTER_SLAVE_SYNC: 1; + unsigned int WRITE_OPTBUS: 1; + unsigned int READ_OPTBUS: 1; + unsigned int ANOTHER_PCH_NOT_ANSWER: 1; + + unsigned int AUTO_SET_MASTER: 1; + unsigned int UMP_NOT_READY: 1; + unsigned int ERROR_SBOR_SHEMA: 1; + unsigned int NOT_VALID_CONTROL_STATION:1; + + unsigned int VERY_FAST_GO_0to1:1; + unsigned int T_ACDRIVE_WINDING_MAX:1; + unsigned int T_ACDRIVE_BEAR_MAX_DNE:1; + unsigned int SVU_BLOCK_ON_QTV:1; + + unsigned int UMP_NOT_ANSWER: 1; + unsigned int ANOTHER_RASCEPITEL_ON: 1; + unsigned int CAN2CAN_BS: 1; + unsigned int ANOTHER_BS_ALARM: 1; + + + + } bits; + } e7; + + union { + unsigned int all; + struct { + + unsigned int LOSS_OUTPUT_U1: 1; + unsigned int LOSS_OUTPUT_V1: 1; + unsigned int LOSS_OUTPUT_W1: 1; + unsigned int LOSS_OUTPUT_U2: 1; + + unsigned int LOSS_OUTPUT_V2: 1; + unsigned int LOSS_OUTPUT_W2: 1; + unsigned int LOSS_INPUT_A1B1: 1; + unsigned int LOSS_INPUT_B1C1: 1; + + unsigned int LOSS_INPUT_A2B2: 1; + unsigned int LOSS_INPUT_B2C2: 1; + unsigned int LOW_FREQ_50HZ: 1; + unsigned int U_IN_10_PROCENTS_LOW: 1; + + unsigned int U_IN_20_PROCENTS_LOW: 1; + unsigned int U_IN_20_PROCENTS_HIGH: 1; + unsigned int DISBALANCE_IM1_IM2: 1; + unsigned int WDOG_OPTICAL_BUS: 1; + + } bits; + } e8; + + union { + unsigned int all; + struct { + unsigned int T_ACDRIVE_BEAR_MAX_NE :1; + unsigned int I_GED_MAX :1; + unsigned int CHANGE_ACTIVE_CONTROL_TO_LOCAL_FROM_SVU :1; + unsigned int DISBALANCE_Uin_1 :1; + + unsigned int DISBALANCE_Uin_2 :1; + unsigned int U_IN_FREQ_NOT_NORMA :1; + unsigned int U_IN_FREQ_NOT_STABLE :1; + unsigned int ERR_PWM_WDOG :1; + + unsigned int ERR_INT_PWM_VERY_LONG : 1; + unsigned int SENSOR_ROTOR_1_BREAK : 1; + unsigned int SENSOR_ROTOR_2_BREAK : 1; + unsigned int SENSOR_ROTOR_1_2_BREAK : 1; + + unsigned int SENSOR_ROTOR_BREAK_DIRECTION : 1; + + unsigned int BREAK_TEMPER_WARNING : 1; + unsigned int BREAK_TEMPER_ALARM : 1; + unsigned int BREAKER_GED_ON : 1; + + } bits; + } e9; + union { + unsigned int all; + struct { + unsigned int WARNING_I_OUT_OVER_1_6_NOMINAL :1; + unsigned int T_BSU_Sensor_BK1 :1; + unsigned int T_BSU_Sensor_BK2 :1; + unsigned int T_ACDRIVE_WINDING_U1 :1; + unsigned int T_ACDRIVE_WINDING_V1 :1; + unsigned int T_ACDRIVE_WINDING_W1 :1; + unsigned int T_ACDRIVE_WINDING_U2 :1; + unsigned int T_ACDRIVE_WINDING_V2 :1; + unsigned int T_ACDRIVE_WINDING_W2 :1; + unsigned int res: 7; + + } bits; + } e10; + union { + unsigned int all; + struct { + unsigned int ERROR_PUMP_ON_SBOR:1; + unsigned int ERROR_RESTART_PUMP_1_ON_SBOR:1; + unsigned int ERROR_RESTART_PUMP_2_ON_SBOR:1; + unsigned int ERROR_RESTART_PUMP_ALL_ON_SBOR:1; + + unsigned int ERROR_PRED_ZARYAD:1; + unsigned int ERROR_PRED_ZARYAD_AFTER:1; + unsigned int ERROR_READY_UMP_BEFORE_QTV:1; + unsigned int ERROR_STATUS_QTV:1; + + unsigned int ERROR_UMP_ON_AFTER :1; + unsigned int ERROR_UMP_NOT_ON:1; + unsigned int ERROR_UMP_NOT_OFF :1; + unsigned int ERROR_RASCEPITEL_WAIT_CMD:1; + + unsigned int ERROR_RASCEPITEL_ON_AFTER:1; + unsigned int ERROR_DISABLE_SBOR:1; + unsigned int ERROR_VERY_LONG_SBOR:1; + unsigned int ERROR_CONTROLLER_BUS:1; +// unsigned int :1; + + } bits; + } e11; + union { + unsigned int all; + struct { + unsigned int res: 16; + + } bits; + } e12; + +} ERRORS_EDRK; + + +#define ERRORS_EDRK_DEFAULT {0,0,0,0,0,0,0,0,0,0,0,0} + +//////////////////////////////////////////////////////// + +typedef struct +{ + struct + { + unsigned int alive_can_to_another_bs; + unsigned int alive_sync_line; + unsigned int alive_sync_line_local; + unsigned int alive_opt_bus_read; + unsigned int alive_opt_bus_write; + unsigned int input_master_slave; + unsigned int input_alarm_another_bs; + unsigned int another_rascepitel; + unsigned int fast_optical_alarm; + } err_lock_signals; + struct + { + unsigned int alive_can_to_another_bs; + unsigned int alive_sync_line; + unsigned int alive_sync_line_local; + unsigned int alive_opt_bus_read; + unsigned int alive_opt_bus_write; + unsigned int input_master_slave; + unsigned int input_alarm_another_bs; + unsigned int another_rascepitel; + unsigned int fast_optical_alarm; + } err_signals; + struct + { + unsigned int alive_can_to_another_bs; + unsigned int alive_sync_line; + unsigned int alive_sync_line_local; + unsigned int alive_opt_bus_read; + unsigned int alive_opt_bus_write; + unsigned int input_master_slave; + unsigned int input_alarm_another_bs; + unsigned int another_rascepitel; + unsigned int fast_optical_alarm; + } warning_signals; + struct + { + unsigned int alive_can_to_another_bs; + unsigned int alive_sync_line; + unsigned int alive_sync_line_local; + unsigned int alive_opt_bus_read; + unsigned int alive_opt_bus_write; + unsigned int input_master_slave; + unsigned int input_alarm_another_bs; + unsigned int another_rascepitel; + unsigned int fast_optical_alarm; + } errors_count; + struct + { + unsigned int alive_can_to_another_bs; + unsigned int alive_sync_line; + unsigned int alive_sync_line_local; + unsigned int alive_opt_bus_read; + unsigned int alive_opt_bus_write; + unsigned int input_master_slave; + unsigned int input_alarm_another_bs; + unsigned int another_rascepitel; + unsigned int fast_optical_alarm; + } wait_count; + + + unsigned int sum_err; // + unsigned int sum_warning; // + unsigned int another_bs_maybe_on; // + unsigned int another_bs_maybe_off; // + unsigned int ready1; // 1 + unsigned int ready2; // 2 + unsigned int ready3; // master/slave + unsigned int count_time_wait_ready1; // + unsigned int count_time_wait_ready2; // + unsigned int status; // , : , , . + + + +} MASTER_SLAVE_COM; +#define MASTER_SLAVE_COM_DEFAULT {{0,0,0,0,0,0,0,0},\ + {0,0,0,0,0,0,0,0},\ + {0,0,0,0,0,0,0,0},\ + {0,0,0,0,0,0,0,0},\ + {0,0,0,0,0,0,0,0},\ + 0,0,0,0,0,0,0,0,0} + + + +//////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////// + +typedef union { + unsigned int all; + struct { + + unsigned int master: 1; + unsigned int slave: 1; + unsigned int try_master: 1; + unsigned int try_slave: 1; + + unsigned int nothing: 1; + unsigned int sync1_2: 1; + unsigned int bus_off: 1; + unsigned int in_err: 1; + unsigned int sync_line_detect:1; + unsigned int tick:1; + + + } bits; + + } AUTO_MASTER_SLAVE_DATA; +//////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + + unsigned int ready1: 1; + unsigned int ready2: 1; + unsigned int ready3: 1; + unsigned int ready4: 1; + + unsigned int ready5: 1; + unsigned int ready6: 1; + unsigned int ready7: 1; + unsigned int ready_final: 1; + + unsigned int Batt: 1; + unsigned int ImitationReady2: 1; + unsigned int MasterSlaveActive: 1; // master slave + unsigned int preImitationReady2: 1; + + unsigned int res:4; + } bits; + } STATUS_READY; +//////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + + unsigned int ZARYAD_ON: 1; + unsigned int NAGREV_OFF: 1; + unsigned int NASOS_1_ON: 1; + unsigned int NASOS_2_ON: 1; + + unsigned int BLOCK_KEY_OFF: 1; + unsigned int RESET_BLOCK_IZOL: 1; + unsigned int SMALL_LAMPA_AVARIA: 1; + unsigned int RASCEPITEL_OFF: 1; + + unsigned int RASCEPITEL_ON: 1; + + unsigned int res:7; + } bits; + } TO_ING; +//////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + unsigned int OP_PIT_NORMA : 1; + unsigned int OHLAD_UTE4KA_WATER: 1; + unsigned int RASCEPITEL_ON: 1; + unsigned int ZARYAD_ON: 1; + + unsigned int VENTIL_ON : 1; + unsigned int NASOS_ON: 1; + unsigned int NASOS_NORMA: 1; + unsigned int ZAZEML_OFF: 1; + + unsigned int NAGREV_ON: 1; + unsigned int BLOCK_IZOL_NORMA: 1; + unsigned int VIPR_PREDOHR_NORMA: 1; + unsigned int UPC_24V_NORMA: 1; + + unsigned int LOCAL_REMOUTE: 1; + unsigned int ZAZEML_ON: 1; + unsigned int ALL_KNOPKA_AVARIA: 1; + unsigned int BLOCK_IZOL_AVARIA: 1; + } bits; + } FROM_ING1; + //////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + unsigned int KEY_PLUS : 1; + unsigned int KEY_MINUS : 1; + unsigned int KEY_SBOR : 1; + unsigned int KEY_RAZBOR : 1; + + unsigned int KEY_KVITIR : 1; + unsigned int SOST_ZAMKA : 1; + + unsigned int res: 9; + + } bits; + } FROM_ING2; + //////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + unsigned int MASTER: 1; + unsigned int RASCEPITEL: 1; + unsigned int res:14; + } bits; + } FROM_SECOND_PCH; + //////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + unsigned int MASTER: 1; + unsigned int ALARM: 1; + + unsigned int res:14; + } bits; + } TO_SECOND_PCH; + //////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + unsigned int QTV_ON: 1; + unsigned int QTV_OFF: 1; + unsigned int UMP_ON_OFF: 1; + unsigned int ENABLE_QTV: 1; + unsigned int QTV_ON_OFF: 1; + unsigned int CROSS_UMP_ON_OFF: 1; + unsigned int CROSS_QTV_ON_OFF: 1; + + unsigned int res:9; + } bits; + } TO_SHEMA; + //////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + unsigned int QTV_ON_OFF: 1; + // unsigned int KNOPKA_AVARIA: 1; + unsigned int ZADA_DISPLAY : 1; + unsigned int RAZBOR_SHEMA :1 ; + unsigned int SBOR_SHEMA : 1; + // unsigned int OPENDOOR : 1; + unsigned int SVU : 1; + // unsigned int ACTIVE : 1; + unsigned int READY_UMP : 1; + unsigned int UMP_ON_OFF : 1; + unsigned int SVU_BLOCK_QTV : 1; + + // unsigned int res:10; + } bits; + } FROM_SHEMA; + //////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + unsigned int KVITIR: 1; + unsigned int PLUS: 1; + unsigned int MINUS : 1; + unsigned int PROVOROT :1 ; + + unsigned int UOM_READY_ACTIVE : 1; + unsigned int UOM_LIMIT_3 : 1; + unsigned int UOM_LIMIT_2 : 1; + unsigned int UOM_LIMIT_1 : 1; + + + unsigned int res:8; + } bits; + } FROM_ZADAT4IK; + //////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + unsigned int SBOR_SHEMA: 1; + unsigned int RAZBOR_SHEMA: 1; + unsigned int KVITIR: 1; + unsigned int ACTIVE : 1; + unsigned int res:12; + } bits; + } FROM_RS; + //////////////////////////////////////////////////////// + typedef union { + unsigned int all; + struct { + unsigned int SBOR_SHEMA: 1; + unsigned int RAZBOR_SHEMA: 1; + unsigned int KVITIR: 1; + unsigned int ACTIVE : 1; + unsigned int BLOCKED : 1; + unsigned int res:11; + } bits; + } FROM_DISPLAY; + //////////////////////////////////////////////////////// + typedef struct { + + union { + int all; + } OBOROTS1; + + + union { + int all; + } OBOROTS2; + + union { + unsigned int all; + struct { + unsigned int GOTOV1 : 1; + unsigned int GOTOV2 : 1; + unsigned int EMKOST : 1; //For 23550.3 and AVARIA moved up + unsigned int NEISPRAVNOST : 1; + unsigned int PEREGREV : 1; + unsigned int OGRAN_POWER : 1; + unsigned int AVARIA : 1; + unsigned int res:9; + } bits; + } BIG_LAMS; + + union { + unsigned int all; + struct { + unsigned int PCH1_READY1: 1; + unsigned int PCH1_SHEMA_SOBRANA: 1; + unsigned int PCH1_PODKLU4EN: 1; + unsigned int PCH1_MESTNOE: 1; + + unsigned int PCH2_READY1: 1; + unsigned int PCH2_SHEMA_SOBRANA: 1; + unsigned int PCH2_PODKLU4EN: 1; + unsigned int PCH2_MESTNOE: 1; + + unsigned int GED_PEREGREV: 1; + unsigned int PCH1_PCH2_SYNC: 1; + unsigned int GED_PEREGRUZ: 1; + unsigned int OBOROT_SVU: 1; + + unsigned int OBOROT_ZADAT: 1; + unsigned int OBOROT_MONITOR: 1; + unsigned int OBOROT_VPU: 1; + unsigned int HOD: 1; + } bits; + } APL_LAMS0; + + union { + unsigned int all; + struct { + unsigned int PCH_READY1: 1; + unsigned int PCH_SHEMA_SOBRANA: 1; + unsigned int PCH_PODKLU4EN: 1; + unsigned int PCH_MESTNOE: 1; + unsigned int reserv: 12; + } bits; + } APL_LAMS_PCH; + + } TO_ZADAT4IK; + +#define TO_ZADAT4IK_DEFAULT {0,0,0,0,0} + + + //////////////////////////////////////////////////////// + typedef struct { + + union { + int all; + } OBOROTS1; + + + union { + int all; + } OBOROTS2; + + union { + unsigned int all; + struct { + unsigned int VPU: 1; + unsigned int GOTOV2: 1; + unsigned int PODDERG_OBOROTS : 1; + unsigned int PEREGRUZKA :1 ; + unsigned int res:12; + } bits; + } BIG_LAMS; + + } TO_VPU; + +#define TO_VPU_DEFAULT {0,0,0} + + //////////////////////////////////////////////////////// + typedef struct { + + unsigned int level_value; + unsigned int ready; + unsigned int error; + unsigned int code; + _iq iq_level_value; + _iq iq_level_value_kwt; + + + + union { + unsigned int all; + struct { + unsigned int ready: 1; + unsigned int level0: 1; + unsigned int level1: 1; + unsigned int level2: 1; + unsigned int level3: 12; + } bits; + } digital_line; + + } FROM_UOM; + //////////////////////////////////////////////////////// + //////////////////////////////////////////////////////// + //////////////////////////////////////////////////////// + //////////////////////////////////////////////////////// + //////////////////////////////////////////////////////// + typedef struct { + + int int_ZadanieU_Charge; + float ZadanieU_Charge; + _iq iq_ZadanieU_Charge; + _iq iq_ZadanieU_Charge_rmp; + + int int_oborots_zad; + float oborots_zad; + float oborots_zad_hz; + _iq iq_oborots_zad_hz; + _iq iq_oborots_zad_hz_rmp; + + int int_fzad; + float fzad; + _iq iq_fzad; + _iq iq_fzad_rmp; + + int int_kzad; + float kzad; + _iq iq_kzad; + _iq iq_kzad_rmp; + + int int_Izad; + float Izad; + _iq iq_Izad; + _iq iq_Izad_rmp; + + int int_power_zad; + float power_zad; + _iq iq_power_zad; + _iq iq_power_zad_rmp; + + } ZADANIE_FROM_ANOTHER_BS; + +#define ZADANIE_FROM_ANOTHER_BS_DEFAULT {\ + 0,0,0,0, 0,0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0 } + + //////////////////////////////////////////////////////// + +typedef struct { + + RMP_V1 rmp_ZadanieU_Charge; + RMP_V1 rmp_fzad; + RMP_V1 rmp_k_u_disbalance; + RMP_V1 rmp_kplus_u_disbalance; + RMP_V1 rmp_Izad; + + RMP_V2 rmp_powers_zad; + + RMP_V2 rmp_limit_powers_zad; + RMP_V1 rmp_kzad; + + RMP_V2 rmp_oborots_zad_hz; + + RMP_V1 rmp_oborots_imitation; + + _iq rmp_oborots_imitation_rmp; + + + float ZadanieU_Charge; + _iq iq_ZadanieU_Charge; + _iq iq_ZadanieU_Charge_rmp; + + float oborots_zad; + + float oborots_zad_hz; + _iq iq_oborots_zad_hz; + _iq iq_oborots_zad_hz_rmp; + + float fzad; + _iq iq_fzad; + _iq iq_fzad_rmp; + + float kzad; + _iq iq_kzad; + _iq iq_kzad_rmp; + + float k_u_disbalance; + _iq iq_k_u_disbalance; + _iq iq_k_u_disbalance_rmp; + + float kplus_u_disbalance; + _iq iq_kplus_u_disbalance; + _iq iq_kplus_u_disbalance_rmp; + + float Izad; + _iq iq_Izad; + _iq iq_Izad_rmp; + + float power_zad; + _iq iq_power_zad; + _iq iq_power_zad_rmp; + + float limit_power_zad; + _iq iq_limit_power_zad; + _iq iq_limit_power_zad_rmp; + + _iq iq_set_break_level; + + float oborots_zad_no_dead_zone; + +} ZADANIE; + +#define ZADANIE_DEFAULT { RMP_V1_DEFAULTS, RMP_V1_DEFAULTS,RMP_V1_DEFAULTS,\ + RMP_V1_DEFAULTS,RMP_V1_DEFAULTS,\ + RMP_V2_DEFAULTS,\ + RMP_V2_DEFAULTS,RMP_V1_DEFAULTS,\ + RMP_V2_DEFAULTS,\ + RMP_V1_DEFAULTS,\ + 0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0 , 0,0,0, 0,0} + +typedef union { + struct { + unsigned int limit_by_temper:1; + unsigned int limit_Iout:1; + unsigned int limit_UOM:1; // + unsigned int limit_from_SVU:1; + unsigned int limit_from_freq:1; + unsigned int limit_from_uom_fast:1; + unsigned int limit_moment:1; + + unsigned int res:9; + } bits; + unsigned int all; +} POWER_LIMIT; + +#define POWER_LIMIT_DEFAULTS {0} + + +typedef struct { + + _iq temper_limit; + _iq power_limit; + _iq moment_limit; + _iq uin_freq_limit; + _iq uom_limit; + + _iq local_temper_limit; + _iq local_power_limit; + _iq local_moment_limit; + _iq local_uin_freq_limit; + _iq local_uom_limit; + + _iq sum_limit; + _iq local_sum_limit; + int code_status; + +} ALL_LIMIT_KOEFFS; + +#define ALL_LIMIT_KOEFFS_DEFAULTS {0,0,0,0,0, 0,0,0,0,0, 0,0,0} + +typedef struct { + _iq power_units; + _iq area; + _iq water_int; + _iq water_ext; + _iq acdrive_windings; + + _iq acdrive_bears; + _iq sum_limit; + int code_status; +} TEMPERATURE_LIMIT_KOEFFS; + +#define TEMPERATURE_LIMIT_KOEFFS_DEFAULTS {0,0,0,0,0, 0,CONST_IQ_1,0} + +#define COUNT_MOTO_PULT 18 + +typedef struct +{ + + int nPCH; + int TimeToChangePump; + + int count_revers; // - + int count_build; // - + + int LastWorkPump; // + + int moto[COUNT_MOTO_PULT]; + +} t_params_pult_ing_one; + +#define PARAMS_PULT_ING_ONE_DEFAULTS {-1,-1, -1,-1, 0, \ + {-1,-1,-1,-1,-1, -1,-1,-1,-1,-1, -1,-1,-1,-1,-1, -1,-1,-1 } } + +#define PARAMS_PULT_ING_TWO_DEFAULTS {0,0, 0,0, 0, \ + {0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0 } } + +typedef struct +{ + int flagSaveDataPCH; + int flagSaveDataMoto; + int flagSaveSlowLogs; + int flagSaveParamLogs; + + int logger_params[28]; + + t_params_pult_ing_one data; + t_params_pult_ing_one data_from_pult; + t_params_pult_ing_one data_to_pult; + +// int nPCH_from_pult; +// int nPCH_to_pult; +// int nPCH; +// +// int TimeToChangePump_from_pult; +// int TimeToChangePump_to_pult; +// int TimeToChangePump; +// +// int moto_from_pult[COUNT_MOTO_PULT]; +// int mot_to_pult[COUNT_MOTO_PULT]; +// int moto[COUNT_MOTO_PULT]; +// +// int count_revers_from_pult; +// int count_revers_to_pult; + +} t_params_pult_ing; + +#define PARAMS_PULT_ING_DEFAULTS {0,0,0,0, \ + {0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0}, \ + PARAMS_PULT_ING_TWO_DEFAULTS, \ + PARAMS_PULT_ING_ONE_DEFAULTS, \ + PARAMS_PULT_ING_ONE_DEFAULTS \ + } + + + + +typedef struct +{ + int log_what_memory; // 0 - , ; + // 1 - , ; + // 2 - , ; + // 3 - ; + int kvitir; // + int sbor; + int send_log; + int pump_mode; + int sdusb;// 0 - sd, 1 usb + +} t_pult_cmd_ing; + +#define PULT_CMD_ING_DEFAULTS 0,0,0,0,0,0 + + + +//////////////////////////////////////////////////////// +typedef struct +{ + ZADANIE zadanie; + ZADANIE_FROM_ANOTHER_BS zadanie_from_another_bs; + TEMPER_EDRK temper_edrk; + P_WATER_EDRK p_water_edrk; + ERRORS_EDRK errors; + ERRORS_EDRK warnings; + TEMPER_ACDRIVE temper_acdrive; + + POWER_LIMIT power_limit; + TEMPERATURE_LIMIT_KOEFFS temper_limit_koeffs; + ALL_LIMIT_KOEFFS all_limit_koeffs; + + MASTER_SLAVE_COM ms; + + //////// + + struct { + + AUTO_MASTER_SLAVE_DATA local; // 1 + AUTO_MASTER_SLAVE_DATA prev_local;//1 + AUTO_MASTER_SLAVE_DATA remoute;//1 + AUTO_MASTER_SLAVE_DATA prev_remoute;//1 + unsigned int status; + unsigned int prev_status; + } auto_master_slave; // 6 + + + + STATUS_READY Status_Ready; //1 + + TO_ING to_ing; //1 + + FROM_ING1 from_ing1;//1 + + FROM_ING2 from_ing2;//1 + + FROM_SECOND_PCH from_second_pch;//1 + + TO_SECOND_PCH to_second_pch;//1 + + TO_SHEMA to_shema;//1 + + FROM_SHEMA from_shema;//1 + FROM_SHEMA from_shema_filter;//1 + + FROM_ZADAT4IK from_zadat4ik;//1 + + FROM_ZADAT4IK from_vpu;//1 + + FROM_RS from_rs;//1 + + FROM_RS from_can;//1 + + FROM_DISPLAY from_display;//1 + + FROM_DISPLAY from_mpu;//1 + + FROM_DISPLAY from_svu;//1 + + TO_ZADAT4IK to_zadat4ik;//5 + + + + TO_VPU to_vpu;//3 + + FROM_UOM from_uom;//7 +/////////////////////////////////////////////// + + unsigned int Discharge; + unsigned int ManualDischarge; + unsigned int NoDetectUZeroDischarge; + + unsigned int TimeSbor; + unsigned int TimeRazbor; + + unsigned int AutoStartPump; + unsigned int SumStartPump; + unsigned int ManualStartPump; + + + + unsigned int SumSbor; + + int Kvitir; + int KvitirProcess;//10 + + unsigned int prevGo; + unsigned int Go; + unsigned int GoBreak; + + unsigned int GoWait; + + int flag_wait_set_to_zero_zadanie; + int flag_block_zadanie; + int StartGEDfromControl; + int StartGEDfromZadanie; + int prevStartGEDfromZadanie; + + int StartGED; + int test_mode; + int cmd_to_qtv;//20 + int cmd_to_ump;//20 + int prepare_stop_PWM; + + int StartGEDfromSyncBus; + + + int cmd_to_rascepitel; + + int Mode_ScalarVectorUFConst; + int Mode_OborotsOrPower; + + int SelectPump1_2;//25 + + int summ_errors; + int Status_Charge; + + unsigned int Sbor_Mode; + unsigned int Razbor_Mode; + unsigned int time_wait_sbor; + + int Status_Sbor; + int Stage_Sbor; + int StatusPumpFanAll; + + int StatusPump0; + int StatusPump1; + int StatusFunAll; + int StatusPumpAll;//35 + + + int Run_Pred_Zaryad; + int Zaryad_OK; + int Rascepitel_OK; + int Run_QTV; + int Run_Rascepitel; + int Run_Rascepitel_from_RS; + int Run_UMP; + int Zaryad_UMP_Ok; + int Status_UMP_Ok; + + + int Status_QTV_Ok; + int Status_Rascepitel_Ok; + int Status_Perehod_Rascepitel; + int Final_Status_Rascepitel; + int you_can_on_rascepitel; + int RunZahvatRascepitel; + int RunUnZahvatRascepitel; + + _iq iqMAX_U_ZPT; + _iq iqMAX_U_ZPT_Global; + _iq iqMAX_U_ZPT_Predzaryad; + _iq iqMIN_U_ZPT;//50 + + _iq iqMAX_U_IN; + _iq iqMIN_U_IN; + + int SborFinishOk; + int RazborNotFinish; + + int Obmotka1; + int Obmotka2; + + _iq f_stator; + + _iq k_stator1; + _iq k_stator2;//60 + + _iq iq_f_rotor_hz; + float f_rotor_hz; + int oborots; + int rotor_direction; + int power_kw; +// _iq iq_oborots; + + _iq Izad_out; + + unsigned int period_calc_pwm_int1; + unsigned int period_calc_pwm_int2; + + unsigned int count_lost_interrupt; + unsigned int into_pwm_interrupt; + + int disable_alg_u_disbalance; + + _iq Kplus; + _iq Kminus; + + unsigned int Revers; + + _iq Uzad_max; + + _iq iq_bpsi_normal; + + _iq iq_f_provorot;//70 + + int flag_second_PCH; + int test; + + int Stop; + + int warning; + int overheat; + + unsigned int MasterSlave; + + _iq master_theta; + _iq master_Uzad; + _iq master_Iq; + _iq master_Izad; + _iq tetta_to_slave; + _iq Uzad_to_slave; + _iq Iq_to_slave; + _iq P_from_slave; + _iq P_to_master;//82 + + int flag_wait_both_ready2; + + int number_can_box_terminal_cmd; + int number_can_box_terminal_oscil; + + int Provorot; + int int_koef_ogran_power; + _iq iq_koef_ogran_power; + + int int_koef_ogran_power_another_bs; + _iq iq_koef_ogran_power_another_bs; + + int power_kw_another_bs; + _iq iq_power_kw_another_bs; + + int run_razbor_shema; + + int Ready1_another_bs; + int Ready2_another_bs; + + int ump_cmd_another_bs; + int qtv_cmd_another_bs; + + int active_post_upravl; + int active_post_upravl_another_bs; + int MasterSlave_another_bs; + int freq_50hz_1; + int freq_50hz_2; + + _iq test_rms_Iu; + _iq test_rms_Ua; +// + int disable_interrupt_pwm; + + int disable_interrupt_timer1; + int disable_interrupt_timer2; + int disable_interrupt_timer3; + int disable_interrupt_timer4; + + int disable_interrupt_sync; + + int get_new_data_from_hmi; + int flag_enable_update_hmi; + + int flag_disable_pult_485; + + int disable_rascepitel_work; + + int enable_pwm_test_lines; + int count_bs_work; + + unsigned int run_to_pwm_async; + + int power_kw_full; + + int stop_logs_rs232; + int sbor_wait_ump1; + int sbor_wait_ump2; + int flag_enable_on_ump; + + int local_ump_on_off; + int local_ump_on_off_count; + int local_ready_ump; + int local_ready_ump_count; + + t_params_pult_ing pult_data; + + int logs_rotor; + + int stop_slow_log; + int t_slow_log; + int disable_limit_power_from_svu; + int disable_uom; + int disable_break_work; + + int flag_another_bs_first_ready12; + int flag_this_bs_first_ready12; + int enter_to_pump_stage; + + int buildYear; + int buildMonth; + int buildDay; + + int errors_another_bs_from_can; + + unsigned int count_sbor; + unsigned int count_revers; + unsigned int count_run; + + int flag_slow_in_main; + + t_pult_cmd_ing pult_cmd; + + int get_new_data_from_hmi2; + + _iq iq_freq_50hz; + + int imit_limit_freq; + int imit_limit_uom; + int set_limit_uom_50; + + _iq iq_power_kw_full_znak; + _iq iq_power_kw_one_znak; + + _iq iq_power_kw_full_filter_znak; + _iq iq_power_kw_one_filter_znak; + + _iq iq_power_kw_full_abs; + _iq iq_power_kw_one_abs; + + _iq iq_power_kw_full_filter_abs; + _iq iq_power_kw_one_filter_abs; + + unsigned int sum_count_err_read_opt_bus; + + int imit_save_slow_logs; + + int imit_send_alarm_log_pult; + + int current_active_control; + + // int data_to_message2[100]; +//101 + unsigned long canes_reg; + unsigned long cantec_reg; // Transmit Error Counter + unsigned long canrec_reg; // Receive Error Counter + + int cmd_clear_can_error; + + int cmd_very_slow_start; + + int cmd_imit_low_isolation; + + + int breaker_on; + int break_tempers[4]; + + int cmd_disable_calc_km_on_slave; + + +} EDRK; + + + +#define EDRK_DEFAULT { \ + ZADANIE_DEFAULT,\ + ZADANIE_FROM_ANOTHER_BS_DEFAULT,\ + TEMPER_EDRK_DEFAULT, \ + P_WATER_EDRK_DEFAULT, \ + ERRORS_EDRK_DEFAULT, \ + ERRORS_EDRK_DEFAULT, \ + TEMPER_ACDRIVE_DEFAULT, \ + POWER_LIMIT_DEFAULTS, \ + TEMPERATURE_LIMIT_KOEFFS_DEFAULTS, \ + ALL_LIMIT_KOEFFS_DEFAULTS, \ + MASTER_SLAVE_COM_DEFAULT, \ + 0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0, \ + 0,0,0,0, \ + 0,0,0, \ + 0,0,0,0,0,0,0, \ + \ + 0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0,0,0,0,0,0,0, 0,0, \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, \ + 0,0,0,0, \ + PARAMS_PULT_ING_DEFAULTS, \ + 0,0,0,0,0,0,0,0, \ + 0,0,0,\ + 0, 0,0,0, 0, \ + PULT_CMD_ING_DEFAULTS, 0,0, 0,0,0, 0,0,0,0, 0,0,0,0, \ + 0, 0,0, 0, 0, \ + 0,0,0, 0, 0, 0, \ + 0, {0,0,0,0}, \ + 0 \ + } + + +extern EDRK edrk; +extern PLL_REC pll1; + +//float get_sensor_ing(void); +//float get_i_vozbud(void); +//float get_zad_vozbud(void); + +//unsigned int convert_w_to_mA(float inp); + +void edrk_init(void); + + +void update_input_edrk(void); +void update_output_edrk(void); + + +//float get_amper_vozbud(void); + +//void set_amper_vozbud(float set_curr, float cur_curr); + + + +//void write_dac(int ndac, int Value); + +void run_edrk(void); + + + +void set_oborots_from_zadat4ik(void); +void get_where_oborots(void); + +//void update_errors(void); + + + + + + +//unsigned int zaryad_on_off(unsigned int flag); + + +void update_lamp_alarm(void); + + + + + + +//int get_status_temper_acdrive_winding(int nc); +//int get_status_temper_acdrive_bear(int nc); +//int get_status_temper_air(int nc); +//int get_status_temper_u(int nc); +//int get_status_temper_water(int nc); +//int get_status_p_water_max(void); +//int get_status_p_water_min(int pump_on_off); + +void detect_kvitir_from_all(void); +//void set_status_pump_fan(void); + + + +int qtv_on_off(unsigned int flag); + +///int detect_error_u_zpt(void); +//int detect_error_u_zpt_on_predzaryad(void); + +void set_zadanie_u_charge(void); + + + + + + + + + + + +void edrk_init_variables(void); + +void edrk_init_before_main(void); +void edrk_init_before_loop(void); +void edrk_go_main(void); + +int get_start_ged_from_zadanie(void); + + +//void UpdateTableSecondBS(void); + +unsigned int get_ready_1(void); + +//int detect_zaryad_ump(void); + +void cross_stend_automats(void); + + + +void get_sumsbor_command(void); + + +//unsigned int read_cmd_sbor_from_bs(void); + +//void read_data_from_bs(void); + + +void check_change_post_upravl(void); +int get_code_active_post_upravl(void); + + + +void auto_detect_zero_u_zpt(void); + +void run_can_from_mpu(void); +void set_new_level_i_protect(int n_af, int level); +void update_maz_level_i_af(int n_af, unsigned int new_maz_level); +void calc_count_build_revers(void); +int calc_auto_moto_pump(void); +void prepare_logger_pult(void); +void read_can_error(void); +void clear_can_error(void); +void cmd_clear_can_error(void); +void check_temper_break(void); +void check_breaker_ged(void); + + + + +//extern int ccc[40]; + +void reinit_before_sbor(void); +unsigned int toggle_status_lamp(unsigned int bb1, unsigned int flag); + + +#endif + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Inu/Src2/551/main/f281xbmsk.h b/Inu/Src2/551/main/f281xbmsk.h new file mode 100644 index 0000000..f9dd78f --- /dev/null +++ b/Inu/Src2/551/main/f281xbmsk.h @@ -0,0 +1,244 @@ +/* ================================================================================== +File name: F281XBMSK.H + +Originator: Digital Control Systems Group + Texas Instruments +Description: +Header file containing handy bitmasks for setting up register values. +This file defines the bitmasks for F281X. + +Target: TMS320F281x family + +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20: Using DSP281x v. 1.00 or higher +---------------------------------------------------------------------------------- */ + +#ifndef __F281X_BMSK_H__ +#define __F281X_BMSK_H__ + +/*------------------------------------------------------------------------------ + F281X Register TxCON +------------------------------------------------------------------------------*/ +#define FREE_RUN_FLAG 0x8000 +#define SOFT_STOP_FLAG 0x4000 + +#define TIMER_STOP 0x0000 +#define TIMER_CONT_UPDN 0x0800 +#define TIMER_CONT_UP 0x1000 +#define TIMER_DIR_UPDN 0x1800 + +#define TIMER_CLK_PRESCALE_X_1 0x0000 +#define TIMER_CLK_PRESCALE_X_2 0x0100 +#define TIMER_CLK_PRESCALE_X_4 0x0200 +#define TIMER_CLK_PRESCALE_X_8 0x0300 +#define TIMER_CLK_PRESCALE_X_16 0x0400 +#define TIMER_CLK_PRESCALE_X_32 0x0500 +#define TIMER_CLK_PRESCALE_X_64 0x0600 +#define TIMER_CLK_PRESCALE_X_128 0x0700 + +#define TIMER_ENABLE_BY_OWN 0x0000 +#define TIMER_ENABLE_BY_T1 0x0080 + +#define TIMER_ENABLE 0x0040 +#define TIMER_DISABLE 0x0000 + +#define TIMER_CLOCK_SRC_INTERNAL 0x0000 +#define TIMER_CLOCK_SRC_EXTERNAL 0x0010 +#define TIMER_CLOCK_SRC_QEP 0x0030 + +#define TIMER_COMPARE_LD_ON_ZERO 0x0000 +#define TIMER_COMPARE_LD_ON_ZERO_OR_PRD 0x0004 +#define TIMER_COMPARE_LD_IMMEDIATE 0x0008 + +#define TIMER_ENABLE_COMPARE 0x0002 +#define TIMER_SELECT_T1_PERIOD 0x0001 + +/*------------------------------------------------------------------------------ + F281X Register ACTR 0x7413 BIT FIELD MASKS +------------------------------------------------------------------------------*/ +/*------------------------------------------------------------------------------ +Space Vector Direction Commands +------------------------------------------------------------------------------*/ +#define SV_DIRECTION_CW 0x8000 +#define SV_DIRECTION_CCW 0x0000 + +/*------------------------------------------------------------------------------ +Space Vector Generation Vectors +------------------------------------------------------------------------------*/ + +//------------------------------------------------------------------------------ +#define SPACE_VECTOR_0 0x0000 +#define SPACE_VECTOR_1 0x1000 +#define SPACE_VECTOR_2 0x2000 +#define SPACE_VECTOR_3 0x3000 +#define SPACE_VECTOR_4 0x4000 +#define SPACE_VECTOR_5 0x5000 +#define SPACE_VECTOR_6 0x6000 +#define SPACE_VECTOR_7 0x7000 + +/*------------------------------------------------------------------------------ + Compare action definitions +------------------------------------------------------------------------------*/ +#define COMPARE6_FL 0x0000 +#define COMPARE6_AL 0x0400 +#define COMPARE6_AH 0x0800 +#define COMPARE6_FH 0x0C00 +//------------------------------------------------------------------------------ +#define COMPARE5_FL 0x0000 +#define COMPARE5_AL 0x0100 +#define COMPARE5_AH 0x0200 +#define COMPARE5_FH 0x0300 +//------------------------------------------------------------------------------ +#define COMPARE4_FL 0x0000 +#define COMPARE4_AL 0x0040 +#define COMPARE4_AH 0x0080 +#define COMPARE4_FH 0x00C0 +//------------------------------------------------------------------------------ +#define COMPARE3_FL 0x0000 +#define COMPARE3_AL 0x0010 +#define COMPARE3_AH 0x0020 +#define COMPARE3_FH 0x0030 +//------------------------------------------------------------------------------ +#define COMPARE2_FL 0x0000 +#define COMPARE2_AL 0x0004 +#define COMPARE2_AH 0x0008 +#define COMPARE2_FH 0x000C +//------------------------------------------------------------------------------ +#define COMPARE1_FL 0x0000 +#define COMPARE1_AL 0x0001 +#define COMPARE1_AH 0x0002 +#define COMPARE1_FH 0x0003 +//------------------------------------------------------------------------------ + +/*------------------------------------------------------------------------------ + F281X Register COMCONA/COMCONB +------------------------------------------------------------------------------*/ +#define CMPR_ENABLE 0x8000 +#define CMPR_LD_ON_ZERO 0x0000 +#define CMPR_LD_ON_ZERO_OR_PRD 0x2000 +#define CMPR_LD_IMMEDIATE 0x4000 +#define SVENABLE 0x1000 +#define SVDISABLE 0x0000 +#define ACTR_LD_ON_ZERO 0x0000 +#define ACTR_LD_ON_ZERO_OR_PRD 0x0400 +#define ACTR_LD_IMMEDIATE 0x0800 +#define FCOMPOE 0x0100 + +/*------------------------------------------------------------------------------ + F281X Register DBTCON +------------------------------------------------------------------------------*/ +#define DBT_VAL_0 0x0000 +#define DBT_VAL_1 0x0100 +#define DBT_VAL_2 0x0200 +#define DBT_VAL_3 0x0300 +#define DBT_VAL_4 0x0400 +#define DBT_VAL_5 0x0500 +#define DBT_VAL_6 0x0600 +#define DBT_VAL_7 0x0700 +#define DBT_VAL_8 0x0800 +#define DBT_VAL_9 0x0900 +#define DBT_VAL_10 0x0A00 +#define DBT_VAL_11 0x0B00 +#define DBT_VAL_12 0x0C00 +#define DBT_VAL_13 0x0D00 +#define DBT_VAL_14 0x0E00 +#define DBT_VAL_15 0x0F00 + +#define EDBT3_DIS 0x0000 +#define EDBT3_EN 0x0080 +#define EDBT2_DIS 0x0000 +#define EDBT2_EN 0x0040 +#define EDBT1_DIS 0x0000 +#define EDBT1_EN 0x0020 + +#define DBTPS_X32 0x0014 +#define DBTPS_X16 0x0010 +#define DBTPS_X8 0x000C +#define DBTPS_X4 0x0008 +#define DBTPS_X2 0x0004 +#define DBTPS_X1 0x0000 + +/*------------------------------------------------------------------------------ + F281X Register ADCTRL1 +------------------------------------------------------------------------------*/ +#define ADC_SUS_MODE0 0x0000 +#define ADC_SUS_MODE1 0X1000 +#define ADC_SUS_MODE2 0x2000 +#define ADC_SUS_MODE3 0X3000 +#define ADC_RESET_FLAG 0x4000 + +#define ADC_ACQ_PS_1 0x0000 +#define ADC_ACQ_PS_2 0x0100 +#define ADC_ACQ_PS_3 0x0200 +#define ADC_ACQ_PS_4 0x0300 +#define ADC_ACQ_PS_5 0x0400 +#define ADC_ACQ_PS_6 0x0500 +#define ADC_ACQ_PS_7 0x0600 +#define ADC_ACQ_PS_8 0x0700 +#define ADC_ACQ_PS_9 0x0800 +#define ADC_ACQ_PS_10 0x0900 +#define ADC_ACQ_PS_11 0x0A00 +#define ADC_ACQ_PS_12 0x0B00 +#define ADC_ACQ_PS_13 0x0C00 +#define ADC_ACQ_PS_14 0x0D00 +#define ADC_ACQ_PS_15 0x0E00 +#define ADC_ACQ_PS_16 0x0F00 + +#define ADC_CPS_1 0x0000 +#define ADC_CPS_2 0x0080 +#define ADC_CONT_RUN 0x0040 +#define ADC_SEQ_CASC 0x0010 +#define ADC_SEQ_DUAL 0x0000 + +/*------------------------------------------------------------------------------ + F281X Register ADCTRL2 +------------------------------------------------------------------------------*/ +#define ADC_EVB_SOC 0x8000 +#define ADC_RST_SEQ1 0x4000 +#define ADC_SOC_SEQ1 0x2000 + +#define ADC_INT_ENA_SEQ1 0x0800 +#define ADC_INT_MODE_SEQ1 0X0400 +#define ADC_EVA_SOC_SEQ1 0x0100 + +#define ADC_EXT_SOC_SEQ1 0x0080 +#define ADC_RST_SEQ2 0x0040 +#define ADC_SOC_SEQ2 0x0020 + +#define ADC_INT_ENA_SEQ2 0x0008 +#define ADC_INT_MODE_SEQ2 0x0004 +#define ADC_EVB_SOC_SEQ2 0x0001 + +/*------------------------------------------------------------------------------ + F281X Register ADCTRL3 +------------------------------------------------------------------------------*/ +#define ADC_RFDN 0x0080 +#define ADC_BGDN 0x0040 +#define ADC_PWDN 0x0020 + +#define ADC_CLKPS_X_1 0x0000 +#define ADC_CLKPS_X_2 0x0002 +#define ADC_CLKPS_X_4 0x0004 +#define ADC_CLKPS_X_6 0x0006 +#define ADC_CLKPS_X_8 0x0008 +#define ADC_CLKPS_X_10 0x000A +#define ADC_CLKPS_X_12 0x000C +#define ADC_CLKPS_X_14 0x000E +#define ADC_CLKPS_X_16 0x0010 +#define ADC_CLKPS_X_18 0x0012 +#define ADC_CLKPS_X_20 0x0014 +#define ADC_CLKPS_X_22 0x0016 +#define ADC_CLKPS_X_24 0x0018 +#define ADC_CLKPS_X_26 0x001A +#define ADC_CLKPS_X_28 0x001C +#define ADC_CLKPS_X_30 0x001E + +#define ADC_SMODE_SIMULTANEOUS 0x0001 +#define ADC_SMODE_SEQUENTIAL 0x0000 + +#endif // __F281X_BMSK_H__ +// EOF + + diff --git a/Inu/Src2/551/main/f281xpwm.c b/Inu/Src2/551/main/f281xpwm.c new file mode 100644 index 0000000..1103b7e --- /dev/null +++ b/Inu/Src2/551/main/f281xpwm.c @@ -0,0 +1,288 @@ +/* ================================================================================== +File name: F281XPWM.C + +Originator: Digital Control Systems Group + Texas Instruments + +Description: This file contains source for the Full Compare PWM drivers for the F281x + +Target: TMS320F281x family + +===================================================================================== +History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20: Using DSP281x v. 1.00 or higher +----------------------------------------------------------------------------------*/ + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "IQmathLib.h" + +#include + +#include "DSP281x_Ev.h" +//#include "params.h" + + +void F281X_EV1_PWM_Init(PWMGEN *p) +{ + EvaRegs.T1PR = p->PeriodMax; // Init Timer 1 period Register + EvaRegs.T1CON.all = PWM_INIT_STATE; // Symmetrical Operation + EvaRegs.DBTCONA.all = DBTCON_INIT_STATE; // Init DBTCONA Register + EvaRegs.ACTRA.all = ACTR_INIT_STATE; // Init ACTRA Register + + EvaRegs.COMCONA.all = 0xA600; // Init COMCONA Register + + EvaRegs.CMPR1 = p->PeriodMax; // Init CMPR1 Register + EvaRegs.CMPR2 = p->PeriodMax; // Init CMPR2 Register + EvaRegs.CMPR3 = p->PeriodMax; // Init CMPR3 Register + EALLOW; // Enable EALLOW + GpioMuxRegs.GPAMUX.all |= 0x003F; // Setting PWM1-6 as primary output pins + EDIS; // Disable EALLOW +} + + +void F281X_EV1_PWM_Update(PWMGEN *p) +{ + int16 MPeriod; + int32 Tmp; + +// Compute the timer period (Q0) from the period modulation input (Q15) + Tmp = (int32)p->PeriodMax*(int32)p->MfuncPeriod; // Q15 = Q0*Q15 + MPeriod = (int16)(Tmp>>16) + (int16)(p->PeriodMax>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvaRegs.T1PR = MPeriod; + +// Compute the compare 1 (Q0) from the PWM 1&2 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC1; // Q15 = Q0*Q15 + EvaRegs.CMPR1 = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + +// Compute the compare 2 (Q0) from the PWM 3&4 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC2; // Q15 = Q0*Q15 + EvaRegs.CMPR2 = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + +// Compute the compare 3 (Q0) from the PWM 5&6 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC3; // Q15 = Q0*Q15 + EvaRegs.CMPR3 = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) +} + + +void F281X_EV2_PWM_Init(PWMGEN *p) +{ + EvbRegs.T3PR = p->PeriodMax; // Init Timer 1 period Register + EvbRegs.T3CON.all = PWM_INIT_STATE; // Symmetrical Operation + EvbRegs.DBTCONB.all = DBTCON_INIT_STATE; // Init DBTCONA Register + EvbRegs.ACTRB.all = ACTR_INIT_STATE; // Init ACTRA Register + + EvbRegs.COMCONB.all = 0xA600; // Init COMCONA Register + + EvbRegs.CMPR4 = p->PeriodMax; // Init CMPR1 Register + EvbRegs.CMPR5 = p->PeriodMax; // Init CMPR2 Register + EvbRegs.CMPR6 = p->PeriodMax; // Init CMPR3 Register + EALLOW; // Enable EALLOW + GpioMuxRegs.GPBMUX.all |= 0x003F; // Setting PWM1-6 as primary output pins + EDIS; // Disable EALLOW +} + + +void F281X_EV2_PWM_Update(PWMGEN *p) +{ + int16 MPeriod; + int32 Tmp; + +// Compute the timer period (Q0) from the period modulation input (Q15) + Tmp = (int32)p->PeriodMax*(int32)p->MfuncPeriod; // Q15 = Q0*Q15 + MPeriod = (int16)(Tmp>>16) + (int16)(p->PeriodMax>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvbRegs.T3PR = MPeriod; + +// Compute the compare 1 (Q0) from the PWM 1&2 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC1; // Q15 = Q0*Q15 + EvbRegs.CMPR4 = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + +// Compute the compare 2 (Q0) from the PWM 3&4 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC2; // Q15 = Q0*Q15 + EvbRegs.CMPR5 = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + +// Compute the compare 3 (Q0) from the PWM 5&6 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC3; // Q15 = Q0*Q15 + EvbRegs.CMPR6 = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + +} + + + +void F281X_EVD_PWM_Init(PWMGEND *p) +{ +//unsigned int pna=0,pnb=0; + + EvaRegs.T1PR = p->PeriodMax; // Init Timer 1 period Register + +#ifdef DOUBLE_UPDATE_PWM + EvaRegs.T1CON.all = PWM_INIT_STATE_DOUBLE_UPADTE; // Symmetrical Operation + DOUBLE UPDATE +#else + EvaRegs.T1CON.all = PWM_INIT_STATE; // Symmetrical Operation +#endif + + EvaRegs.DBTCONA.all = DBTCON_INIT_STATE; // Init DBTCONA Register + EvaRegs.ACTRA.all = ACTR_INIT_STATE; // Init ACTRA Register + + EvaRegs.COMCONA.all = 0xa600;//0xA600; // Init COMCONA Register + + EvaRegs.CMPR1 = p->PeriodMax; // Init CMPR1 Register + EvaRegs.CMPR2 = p->PeriodMax; // Init CMPR2 Register + EvaRegs.CMPR3 = p->PeriodMax; // Init CMPR3 Register + EALLOW; // Enable EALLOW + GpioMuxRegs.GPAMUX.all |= 0x003F; // Setting PWM1-6 as primary output pins + EDIS; // Disable EALLOW + + + EvbRegs.T3PR = p->PeriodMax; // Init Timer 1 period Register + +#ifdef DOUBLE_UPDATE_PWM + EvbRegs.T3CON.all = PWM_INIT_STATE_DOUBLE_UPADTE; // Symmetrical Operation + DOUBLE UPDATE +#else + EvbRegs.T3CON.all = PWM_INIT_STATE; // Symmetrical Operation +#endif + + EvbRegs.DBTCONB.all = DBTCON_INIT_STATE; // Init DBTCONA Register + EvbRegs.ACTRB.all = ACTR_INIT_STATE; // Init ACTRA Register + + EvbRegs.COMCONB.all = 0xa600;//0xA600; // Init COMCONA Register + + EvbRegs.CMPR4 = p->PeriodMax; // Init CMPR1 Register + EvbRegs.CMPR5 = p->PeriodMax; // Init CMPR2 Register + EvbRegs.CMPR6 = p->PeriodMax; // Init CMPR3 Register + EALLOW; // Enable EALLOW + GpioMuxRegs.GPBMUX.all |= 0x003F; // Setting PWM1-6 as primary output pins + EDIS; // Disable EALLOW +// pna = p->ShiftPhaseA;//(p->PeriodMax); +// pnb = p->ShiftPhaseB; + + + EvaRegs.T1CNT = 0x0000; + EvbRegs.T3CNT = 0x0000; + +} + +#pragma CODE_SECTION(set_predel_dshim,".fast_run"); +int16 set_predel_dshim(int16 dshim,int16 dmin,int16 dpwm) +{ + if (dshim < dmin) + { + dshim = dmin; + } + + if (dshim > (dpwm - dmin) ) + { + dshim = (dpwm - dmin); + } + return dshim; +} + +#pragma CODE_SECTION(set_predel_dshim_max,".fast_run"); +int16 set_predel_dshim_max(int16 dshim,int16 dmin,int16 dpwm) +{ + int d2; + +/* + if (dshim < dmin) + { + return 0; + } + else + { + if (dshim > (dpwm - dmin) ) + { +// dshim = (dpwm + 1); + return (dpwm + 10); + } + else + return dshim; + + } +*/ + + + d2 = dmin/2; + + if (dshim < d2) + { + dshim = 0; + return dshim; + } + + if (dshim < dmin) + { + dshim = dmin; + return dshim; + } + + + if (dshim > (dpwm - d2) ) + { + dshim = dpwm+dmin; + return dshim; + } + + + if (dshim > (dpwm - dmin) ) + { + dshim = (dpwm - dmin); + return dshim; + } + + return dshim; + + +} + + +//#pragma CODE_SECTION(F281X_EVD_PWM_Update,".fast_run"); +void F281X_EVD_PWM_Update(PWMGEND *p) +{ + int16 MPeriod, Dshim; + int32 Tmp; + + +// Compute the timer period (Q0) from the period modulation input (Q15) + Tmp = (int32)p->PeriodMax*(int32)p->MfuncPeriod; // Q15 = Q0*Q15 + MPeriod = (int16)(Tmp>>16) + (int16)(p->PeriodMax>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvaRegs.T1PR = MPeriod; + +// Compute the compare 1 (Q0) from the PWM 1&2 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC1; // Q15 = Q0*Q15 + Dshim = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvaRegs.CMPR1 = set_predel_dshim(Dshim,(int16)p->PeriodMin,(int16)MPeriod); + +// Compute the compare 2 (Q0) from the PWM 3&4 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC2; // Q15 = Q0*Q15 + Dshim = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvaRegs.CMPR2 = set_predel_dshim(Dshim,(int16)p->PeriodMin,(int16)MPeriod); + +// Compute the compare 3 (Q0) from the PWM 5&6 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC3; // Q15 = Q0*Q15 + Dshim = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvaRegs.CMPR3 = set_predel_dshim(Dshim,(int16)p->PeriodMin,(int16)MPeriod); + + +// Compute the timer period (Q0) from the period modulation input (Q15) +// Tmp = (int32)p->PeriodMax*(int32)p->MfuncPeriod; // Q15 = Q0*Q15 +// MPeriod = (int16)(Tmp>>16) + (int16)(p->PeriodMax>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvbRegs.T3PR = MPeriod; + +// Compute the compare 1 (Q0) from the PWM 1&2 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC4; // Q15 = Q0*Q15 + Dshim = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvbRegs.CMPR4 = set_predel_dshim(Dshim,(int16)p->PeriodMin,(int16)MPeriod); + +// Compute the compare 2 (Q0) from the PWM 3&4 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC5; // Q15 = Q0*Q15 + Dshim = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvbRegs.CMPR5 = set_predel_dshim(Dshim,(int16)p->PeriodMin,(int16)MPeriod); + +// Compute the compare 3 (Q0) from the PWM 5&6 duty cycle ratio (Q15) + Tmp = (int32)MPeriod*(int32)p->MfuncC6; // Q15 = Q0*Q15 + Dshim = (int16)(Tmp>>16) + (int16)(MPeriod>>1); // Q0 = (Q15->Q0)/2 + (Q0/2) + EvbRegs.CMPR6 = set_predel_dshim(Dshim,(int16)p->PeriodMin,(int16)MPeriod); + +} + diff --git a/Inu/Src2/551/main/f281xpwm.h b/Inu/Src2/551/main/f281xpwm.h new file mode 100644 index 0000000..bf9499f --- /dev/null +++ b/Inu/Src2/551/main/f281xpwm.h @@ -0,0 +1,163 @@ +/* ================================================================================== +File name: F281XPWM.H + +Originator: Digital Control Systems Group + Texas Instruments +Description: +Header file containing data type and object definitions and +initializers. Also contains prototypes for the functions in F281XPWM.C. + +Target: TMS320F281x family + +===================================================================================== + History: +------------------------------------------------------------------------------------- + 04-15-2005 Version 3.20: Using DSP281x v. 1.00 or higher +---------------------------------------------------------------------------------- */ + +#ifndef __F281X_PWM_H__ +#define __F281X_PWM_H__ + +#include +//#include "DSP281x_Device.h" +/*---------------------------------------------------------------------------- +Initialization constant for the F281X Timer TxCON for PWM Generation. +Sets up the timer to run free upon emulation suspend, continuous up-down mode +prescaler 1, timer enabled. +----------------------------------------------------------------------------*/ //FREE_RUN_FLAG +#define PWM_INIT_STATE (FREE_RUN_FLAG + \ + TIMER_CONT_UPDN + \ + TIMER_CLK_PRESCALE_X_1 + \ + TIMER_ENABLE_BY_OWN + \ + TIMER_ENABLE) + +#define PWM_INIT_STATE_DOUBLE_UPADTE (FREE_RUN_FLAG + \ + TIMER_COMPARE_LD_ON_ZERO_OR_PRD + \ + TIMER_CONT_UPDN + \ + TIMER_CLK_PRESCALE_X_1 + \ + TIMER_ENABLE_BY_OWN + \ + TIMER_ENABLE) + +/*---------------------------------------------------------------------------- +Initialization constant for the F281X ACTRx register for PWM Generation. +Sets up PWM polarities. +----------------------------------------------------------------------------*/ +#define ACTR_INIT_STATE ( COMPARE1_FH + \ + COMPARE2_FH + \ + COMPARE3_FH + \ + COMPARE4_FH + \ + COMPARE5_FH + \ + COMPARE6_FH ) + +#define ACTR_ON_STATE ( COMPARE1_AL + \ + COMPARE2_AH + \ + COMPARE3_AL + \ + COMPARE4_AH + \ + COMPARE5_AL + \ + COMPARE6_AH ) + +/*---------------------------------------------------------------------------- +Initialization constant for the F281X DBTCONx register for PWM Generation. +Sets up the dead band for PWM and sets up dead band values. +----------------------------------------------------------------------------*/ +#define DBTCON_INIT_STATE ( DBT_VAL_10 + \ + EDBT3_EN + \ + EDBT2_EN + \ + EDBT1_EN + \ + DBTPS_X32 ) + + +/*----------------------------------------------------------------------------- +Define the structure of the PWM Driver Object +-----------------------------------------------------------------------------*/ +typedef struct { + Uint16 PeriodMax; // Parameter: PWM Half-Period in CPU clock cycles (Q0) + int16 MfuncPeriod; // Input: Period scaler (Q15) + int16 MfuncC1; // Input: PWM 1&2 Duty cycle ratio (Q15) + int16 MfuncC2; // Input: PWM 3&4 Duty cycle ratio (Q15) + int16 MfuncC3; // Input: PWM 5&6 Duty cycle ratio (Q15) + void (*init)(); // Pointer to the init function + void (*update)(); // Pointer to the update function + } PWMGEN ; + + +typedef struct { + Uint16 PeriodMax; // Parameter: PWM Half-Period in CPU clock cycles (Q0) + Uint16 PeriodMin; // Parameter: PWM Half-Period in CPU clock cycles (Q0) + int16 MfuncPeriod; // Input: Period scaler (Q15) + int16 MfuncC1; // Input: PWM 1&2 Duty cycle ratio (Q15) + int16 MfuncC2; // Input: PWM 3&4 Duty cycle ratio (Q15) + int16 MfuncC3; // Input: PWM 5&6 Duty cycle ratio (Q15) + int16 MfuncC4; // Input: PWM 1&2 Duty cycle ratio (Q15) + int16 MfuncC5; // Input: PWM 3&4 Duty cycle ratio (Q15) + int16 MfuncC6; // Input: PWM 5&6 Duty cycle ratio (Q15) + Uint16 ShiftPhaseA; // Parameter: PWM Half-Period in CPU clock cycles (Q0) + Uint16 ShiftPhaseB; // Parameter: PWM Half-Period in CPU clock cycles (Q0) + void (*init)(); // Pointer to the init function + void (*update)(); // Pointer to the update function + } PWMGEND ; + +/*----------------------------------------------------------------------------- +Define a PWMGEN_handle +-----------------------------------------------------------------------------*/ +typedef PWMGEN *PWMGEN_handle; +typedef PWMGEND *PWMGEND_handle; + +/*------------------------------------------------------------------------------ +Default Initializers for the F281X PWMGEN Object +------------------------------------------------------------------------------*/ +#define F281X_EV1_FC_PWM_GEN {1000, \ + 0x7FFF, \ + 0x4000, \ + 0x4000, \ + 0x4000, \ + (void (*)(Uint32))F281X_EV1_PWM_Init, \ + (void (*)(Uint32))F281X_EV1_PWM_Update \ + } + +#define F281X_EV2_FC_PWM_GEN {1000, \ + 0x7FFF, \ + 0x4000, \ + 0x4000, \ + 0x4000, \ + (void (*)(Uint32))F281X_EV2_PWM_Init, \ + (void (*)(Uint32))F281X_EV2_PWM_Update \ + } + + +#define F281X_EVD_FC_PWM_GEN {1000, \ + 0, \ + 0x7FFF, \ + 0x4000, \ + 0x4000, \ + 0x4000, \ + 0x4000, \ + 0x4000, \ + 0x4000, \ + 0x000, \ + 0x000, \ + (void (*)(Uint32))F281X_EVD_PWM_Init, \ + (void (*)(Uint32))F281X_EVD_PWM_Update \ + } + +#define PWMGEN1_DEFAULTS F281X_EV1_FC_PWM_GEN +#define PWMGEN2_DEFAULTS F281X_EV2_FC_PWM_GEN +#define PWMGEND_DEFAULTS F281X_EVD_FC_PWM_GEN + +/*------------------------------------------------------------------------------ + Prototypes for the functions in F281XPWM.C +------------------------------------------------------------------------------*/ +void F281X_EV1_PWM_Init(PWMGEN_handle); +void F281X_EV1_PWM_Update(PWMGEN_handle); +void F281X_EV2_PWM_Init(PWMGEN_handle); +void F281X_EV2_PWM_Update(PWMGEN_handle); + +void F281X_EVD_PWM_Init(PWMGEND_handle); +void F281X_EVD_PWM_Update(PWMGEND_handle); + +int16 set_predel_dshim_max(int16 dshim,int16 dmin,int16 dpwm); +int16 set_predel_dshim(int16 dshim,int16 dmin,int16 dpwm); + + +#endif // __F281X_PWM_H__ + diff --git a/Inu/Src2/551/main/limit_lib.c b/Inu/Src2/551/main/limit_lib.c new file mode 100644 index 0000000..859b644 --- /dev/null +++ b/Inu/Src2/551/main/limit_lib.c @@ -0,0 +1,50 @@ +/* + * limit_lib.c + * + * Created on: 15 . 2024 . + * Author: yura + */ + + +#include "IQmathLib.h" +#include "math_pi.h" + + + +_iq linear_decrease(float current, int alarm_level, int warnig_level) { + float delta = current - warnig_level; + float max_delta = alarm_level - warnig_level; + if (delta <= 0 || max_delta <= 0) { + return CONST_IQ_1; + } else { + if (delta>max_delta) + return 0; + else + return CONST_IQ_1 - _IQ(delta / max_delta); + } +} + + + + + + + +_iq linear_decrease_iq(_iq current, _iq alarm_level, _iq warnig_level) +{ + _iq delta = current - warnig_level; + + _iq max_delta = alarm_level - warnig_level; + + if (delta <= 0 || max_delta <= 0) { + return CONST_IQ_1; + } else { + if (delta>=max_delta) + return 0; + else + return CONST_IQ_1 - _IQdiv(delta, max_delta); + } +} + + + diff --git a/Inu/Src2/551/main/limit_lib.h b/Inu/Src2/551/main/limit_lib.h new file mode 100644 index 0000000..3b1e6aa --- /dev/null +++ b/Inu/Src2/551/main/limit_lib.h @@ -0,0 +1,15 @@ +/* + * limit_lib.h + * + * Created on: 15 . 2024 . + * Author: yura + */ + +#ifndef SRC_MAIN_LIMIT_LIB_H_ +#define SRC_MAIN_LIMIT_LIB_H_ + +_iq linear_decrease(float current, int alarm_level, int warnig_level); + +_iq linear_decrease_iq(_iq current, _iq alarm_level, _iq warnig_level); + +#endif /* SRC_MAIN_LIMIT_LIB_H_ */ diff --git a/Inu/Src2/551/main/limit_power.c b/Inu/Src2/551/main/limit_power.c new file mode 100644 index 0000000..840019f --- /dev/null +++ b/Inu/Src2/551/main/limit_power.c @@ -0,0 +1,237 @@ +/* + * limit_power.c + * + * Created on: 15 . 2024 . + * Author: yura + */ + +#include "IQmathLib.h" + +#include +#include +#include +#include +#include +#include "mathlib.h" +#include "math_pi.h" + + +#include "limit_power.h" +#include "limit_lib.h" + +#include "pll_tools.h" + +#include "uom_tools.h" + + + + +#define KOEF_50HZ (FREQ_PWM*2.0*50.0/PI) +#define LEVEL_01HZ_IQ _IQ(10.0/KOEF_50HZ) // 0.1 HZ + +_iq level_50hz = _IQmpyI32(LEVEL_01HZ_IQ, 500); +_iq level_minimal_level_work_hz = _IQmpyI32(LEVEL_01HZ_IQ, 350); + +_iq delta_freq_test = 0; + + +//_iq level_01hz = _IQ(LEVEL_01HZ); + + +//#define LEVEL_50HZ (5000.0/KOEF_50HZ) // 50 HZ +//#define LEVEL_05HZ (50.0/KOEF_50HZ) // 50 HZ +// +//#define LEVEL_3HZ (300.0/KOEF_50HZ) // 50 HZ +//#define LEVEL_2HZ (200.0/KOEF_50HZ) // 50 HZ +//#define LEVEL_1HZ (100.0/KOEF_50HZ) // 50 HZ + + + +#define LEVEL1_FREQ_DECR 10 // 1.5 Hz 49.0 +#define LEVEL2_FREQ_DECR 100 // 10 Hz 40 +//#define LEVEL1_FREQ_DECR 15 // 1.5 Hz 48.5 +//#define LEVEL2_FREQ_DECR 100 // 10 Hz 40 + +#define PLUS_LIMIT_KOEFFS 0.0001 +#define MINUS_LIMIT_KOEFFS 0.05 + +#define MAX_COUNT_GO_UOM (FREQ_PWM*5) // 5 sec +#define SET_LIMIT_UOM 0.5 + +void calc_all_limit_koeffs(void) +{ + _iq sum_limit, delta_freq; + + static unsigned int prev_uom = 0; + static int flag_enable_go_uom = 0; + + + static _iq level1_freq_decr = _IQmpyI32(LEVEL_01HZ_IQ, LEVEL1_FREQ_DECR); + static _iq level2_freq_decr = _IQmpyI32(LEVEL_01HZ_IQ, LEVEL2_FREQ_DECR); + + static _iq iq_set_limit_uom = _IQ(SET_LIMIT_UOM); + static unsigned int count_go_uom = 0; + + static _iq iq_plus_limit_koeffs = _IQ(PLUS_LIMIT_KOEFFS); + static _iq iq_minus_limit_koeffs = _IQ(MINUS_LIMIT_KOEFFS); + + static long freq_test = 30; + //*LEVEL_01HZ_IQ; + static _iq minus_delta_freq_test = _IQdiv32(LEVEL_01HZ_IQ); // 0.1/32 + + + static int uom_test = 50; + static int prev_imit_limit_freq = 0, prev_imit_limit_uom = 0; + + static _iq iq_new_uom_level_kwt = 0; + + + update_uom(); + + // temper + edrk.all_limit_koeffs.local_temper_limit = edrk.temper_limit_koeffs.sum_limit; + + + // uin_freq + if (edrk.Status_Ready.bits.ready_final) //|| edrk.imit_limit_freq + { + + get_freq_50hz_iq(); + + // freq = LEVEL_50HZ - edrk.iq_freq_50hz; + + if (edrk.imit_limit_freq && prev_imit_limit_freq == 0) + delta_freq_test = _IQmpyI32(LEVEL_01HZ_IQ, freq_test); + + if (delta_freq_test>0) + { + if (delta_freq_test>0) + delta_freq_test -= minus_delta_freq_test; + if (delta_freq_test<0) + delta_freq_test = 0; + } + + if (edrk.iq_freq_50hz>level_minimal_level_work_hz) + { + edrk.all_limit_koeffs.local_uin_freq_limit = linear_decrease_iq( (level_50hz - edrk.iq_freq_50hz), + level2_freq_decr, level1_freq_decr); + } + else + edrk.all_limit_koeffs.local_uin_freq_limit = CONST_IQ_1; + } + else + { + edrk.all_limit_koeffs.local_uin_freq_limit = CONST_IQ_1; + } + prev_imit_limit_freq = edrk.imit_limit_freq; + + // + /// UOM + // + if (edrk.from_uom.ready || edrk.set_limit_uom_50) + { + if (edrk.set_limit_uom_50) + { + edrk.from_uom.level_value = uom_test; + } + + if (edrk.imit_limit_uom && prev_imit_limit_uom == 0) + edrk.from_uom.level_value++; + + + if (prev_uom!=edrk.from_uom.level_value && edrk.from_uom.level_value > prev_uom) + { + if (edrk.iq_power_kw_full_filter_abs > edrk.from_uom.iq_level_value_kwt) + flag_enable_go_uom = 1; + } + else + flag_enable_go_uom = 0; + + if (flag_enable_go_uom) + { + count_go_uom = MAX_COUNT_GO_UOM; + edrk.all_limit_koeffs.local_uom_limit = iq_set_limit_uom; // + } + + if (count_go_uom) + { + // + count_go_uom--; + } + else + edrk.all_limit_koeffs.local_uom_limit = CONST_IQ_1; // + + prev_uom = edrk.from_uom.level_value; + + } + else + { + + edrk.power_limit.bits.limit_from_uom_fast = 0; + edrk.all_limit_koeffs.uom_limit = CONST_IQ_1; + prev_uom = 0; + } + prev_imit_limit_uom = edrk.imit_limit_uom; + // if () + + + //// temper + edrk.all_limit_koeffs.temper_limit = zad_intensiv_q(iq_plus_limit_koeffs, iq_minus_limit_koeffs, + edrk.all_limit_koeffs.temper_limit, + edrk.all_limit_koeffs.local_temper_limit); + + edrk.power_limit.bits.limit_by_temper = (edrk.all_limit_koeffs.temper_limit +#include +#include +#include + +#include "control_station.h" +#include "global_time.h" +#include "modbus_table_v2.h" +#include "RS_modbus_pult.h" +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "RS_modbus_svu.h" +#include "log_params.h" +#include "logs_hmi.h" +#include "edrk_main.h" + + +#pragma DATA_SECTION(log_to_HMI, ".logs"); +t_Logs_with_modbus log_to_HMI = LOGS_WITH_MODBUS_DEFAULTS; + + +#define COUNT_FAST_DATA 300//150 +#define COUNT_SLOW_DATA 300 + + + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +#define MAX_SIZE_LOGS_HMI_FULL (END_ADDRESS_LOGS - START_ADDRESS_LOG + 1) //262144 // 0x80000/2 +#define MAX_SIZE_LOGS_HMI_SMALL 10000 + +#define START_ARRAY_LOG_SEND 300 +#define END_ARRAY_LOG_SEND 899 +#define SIZE_ARRAY_LOG_SEND (END_ARRAY_LOG_SEND - START_ARRAY_LOG_SEND + 1) +#define SIZE_BUF_WRITE_LOGS_TO_MODBUS16_REMOUTE 120 + +int writeLogsArray(int flag_next) +{ + int succed = 0; + static unsigned int old_time = 0; + + static int count_write_to_modbus = 0; + static int cur_position_buf_modbus16 = 0; + + + + + + if (!rs_b.flag_LEADING) + { + + ModbusRTUsetDataArrays(modbus_table_analog_in, modbus_table_analog_out); + + if (control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] == 0) + { + if (log_to_HMI.flag_start_log_array_sent) + { + cur_position_buf_modbus16 = START_ARRAY_LOG_SEND; + log_to_HMI.flag_log_array_sended = 0; + } + else + { + if (flag_next) + cur_position_buf_modbus16 = cur_position_buf_modbus16 + SIZE_BUF_WRITE_LOGS_TO_MODBUS16_REMOUTE; + } + + log_to_HMI.flag_start_log_array_sent = 0; + } + + if (cur_position_buf_modbus16 >= END_ARRAY_LOG_SEND) + { + // ? + cur_position_buf_modbus16 = START_ARRAY_LOG_SEND; + log_to_HMI.flag_log_array_sended = 1; + // log_to_HMI.flag_log_array_sent_process = 0; +// succed = 1; + return succed; + } + +// // . . +// if ((cur_position_buf_modbus16 > ADRESS_END_FIRST_BLOCK) && +// (cur_position_buf_modbus16 < ADRESS_START_PROTECTION_LEVELS)) { +// cur_position_buf_modbus16 = ADRESS_START_PROTECTION_LEVELS; +// } + + if ((cur_position_buf_modbus16 + SIZE_BUF_WRITE_LOGS_TO_MODBUS16_REMOUTE) > (END_ARRAY_LOG_SEND+1)) + count_write_to_modbus = END_ARRAY_LOG_SEND - cur_position_buf_modbus16 + 1; + else + count_write_to_modbus = SIZE_BUF_WRITE_LOGS_TO_MODBUS16_REMOUTE; + + log_to_HMI.n_log_array_sended = (cur_position_buf_modbus16 - START_ARRAY_LOG_SEND)/100 + 1; + log_to_HMI.flag_log_array_sent_process++;// = 1; + + ModbusRTUsend16(&rs_b, 2, + ADR_MODBUS_TABLE_REMOUTE + cur_position_buf_modbus16, + count_write_to_modbus); + + + + // control_station.count_error_modbus_16[CONTROL_STATION_INGETEAM_PULT_RS485]++; + + // control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] = 1; + succed = count_write_to_modbus; + } + return succed; + + + +/* + + unsigned long i = 0; + int succed = 0; + +// int *p_log_data = (int*)LOG_START_ADRES; + + ModbusRTUsetDataArrays(modbus_table_analog_in, modbus_table_analog_out); + if (!rs_b.flag_LEADING) + { + ModbusRTUsend16(&rs_b, 2, + log_to_HMI.current_address, + log_to_HMI.count_write_to_modbus + 1); + + if (err_send_log_16 == 0) { //prev message without errors + log_to_HMI.current_address = log_to_HMI.current_address + SIZE_BUF_WRITE_LOG_TO_MODBUS16; + } + if (log_to_HMI.current_address > END_ARRAY_LOG_SEND) { + log_to_HMI.current_address = START_ARRAY_LOG_SEND; +// log_to_HMI.flag_end_of_log = 1; + log_to_HMI.flag_log_array_sent = 1; + } + if ((log_to_HMI.current_address + SIZE_BUF_WRITE_LOG_TO_MODBUS16) > END_ARRAY_LOG_SEND) { + log_to_HMI.count_write_to_modbus = END_ARRAY_LOG_SEND - log_to_HMI.current_address; + } else { + log_to_HMI.count_write_to_modbus = SIZE_BUF_WRITE_LOG_TO_MODBUS16; + } + + err_send_log_16 += 1; + succed = 1; + + } + return succed; +*/ +} + +void prepareWriteLogsArray(void) { +// log_to_HMI.start_log_address = logpar.addres_mem - logpar.count_log_params_fast_log * SIZE_ARRAY_LOG_SEND; +// log_to_HMI.start_log_address = log_params.addres_mem - log_params.BlockSizeErr * SIZE_ARRAY_LOG_SEND; + + if (log_to_HMI.send_log == 1) + log_to_HMI.start_log_address = log_params.start_address_log_slow; + if (log_to_HMI.send_log == 2) + log_to_HMI.start_log_address = log_params.start_address_log; + if (log_to_HMI.send_log == 3) + log_to_HMI.start_log_address = 0;//log_params.start_address_log; + + // - log_to_HMI.max_size_logs_hmi; + +// if (log_to_HMI.start_log_address < log_params.start_address_log) { +// log_to_HMI.start_log_address = log_params.end_address_log - (log_params.start_address_log - log_to_HMI.start_log_address); +// } +// log_to_HMI.log_address_step = SIZE_ARRAY_LOG_SEND;//log_params.BlockSizeErr; +} + + +int fillAnalogDataArrayForLogSend(void) +{ + int i, k, n;// = START_ARRAY_LOG_SEND; + int c_data = 0, lb = 0, type_log; + volatile unsigned long local_pos = 0; + +// unsigned long current_address = log_to_HMI.start_log_address;// + num_of_log; + + k = 0; + n = 0; + for (i = START_ARRAY_LOG_SEND; i <= END_ARRAY_LOG_SEND; i++) { + +// if (log_to_HMI.count_write_to_modbus > log_to_HMI.max_size_logs_hmi) +// break; + + n = log_to_HMI.count_write_to_modbus/SIZE_BUF_WRITE_LOGS_TO_MODBUS16_REMOUTE; + + if (k>=SIZE_BUF_WRITE_LOGS_TO_MODBUS16_REMOUTE) + k = 0; + + if (k==0) + modbus_table_analog_out[i].all = LOWORD(log_to_HMI.count_write_to_modbus); + else + if (k==1) + modbus_table_analog_out[i].all = LOWORD(global_time.miliseconds); + else + if (k==2) + modbus_table_analog_out[i].all = HIWORD(log_to_HMI.start_log_address); + else + if (k==3) + modbus_table_analog_out[i].all = LOWORD(log_to_HMI.start_log_address); + else + if (k==SIZE_BUF_WRITE_LOGS_TO_MODBUS16_REMOUTE-1) + modbus_table_analog_out[i].all = log_to_HMI.tick_step; + else + { + if (log_to_HMI.count_write_to_modbus > log_to_HMI.max_size_logs_hmi) + modbus_table_analog_out[i].all = 0; + else + { +// modbus_table_analog_out[i].all = LOWORD(log_to_HMI.start_log_address); // + if (log_to_HMI.send_log==3) + { + if (log_to_HMI.start_log_address>=(COUNT_FAST_DATA*log_params.BlockSizeErr) ) + { + local_pos = log_to_HMI.max_size_logs_hmi - log_to_HMI.start_log_address;// - (COUNT_FAST_DATA*log_params.BlockSizeErr); + type_log = SLOW_LOG; + } + else + { + local_pos = log_to_HMI.max_size_logs_hmi - log_to_HMI.start_log_address - (COUNT_SLOW_DATA*log_params.BlockSizeErr); + type_log = FAST_LOG; + } + + modbus_table_analog_out[i].all = alarm_log_get_data(local_pos, type_log); + } + else + modbus_table_analog_out[i].all = ReadMemory(log_to_HMI.start_log_address); + + + + log_to_HMI.start_log_address += 1;//log_to_HMI.log_address_step; + log_to_HMI.count_write_to_modbus += 1; + + } + } + +// modbus_table_analog_out[i+1].all = HIWORD(log_to_HMI.start_log_address);//log_to_HMI.count_write_to_modbus;//ReadMemory(log_to_HMI.start_log_address); +// modbus_table_analog_out[i].all = LOWORD(global_time.miliseconds);//ReadMemory(log_to_HMI.start_log_address); +// modbus_table_analog_out[i+1].all = HIWORD(global_time.miliseconds);//log_to_HMI.count_write_to_modbus;//ReadMemory(log_to_HMI.start_log_address); + +// if (k>1 && k 0) { + *(p_memory++) = value; + value += 1; +// if (log_size % 8 == 0) { +// value += 1; +// } + } +} + + + + + + +int alarm_log_get_data(unsigned long pos, int type_log) +{ + //unsigned int i,k; + static volatile unsigned long cur_adr_log, end_log, start_log, addres_mem, temp_length, delta_adr;//clog //real_length + //int *adr_finish_temp, *adr_current; + + +// real_length = al->real_points * al->oscills; + // real_adr = al->start_adr_real_logs; + + if (type_log==FAST_LOG) + { + temp_length = log_params.BlockSizeErr; + cur_adr_log = log_params.addres_mem; + end_log = log_params.end_address_log; + start_log = log_params.start_address_log; + + } + + if (type_log==SLOW_LOG) + { + temp_length = log_params.BlockSizeSlow; + cur_adr_log = log_params.addres_mem_slow; + end_log = log_params.end_address_log_slow; + start_log = log_params.start_address_log_slow; + } + + // + + + addres_mem = cur_adr_log - pos;//temp_length + + // ? + if (addres_memtemp_points * al->oscills; // + al->temp_log_ready = 0; + + + if (al->current_adr_real_log == al->start_adr_real_logs) // , ? + return; + + adr_current = al->current_adr_real_log; // + adr_finish_temp = al->start_adr_temp + temp_length; // temp + // adr_finish temp_log + // , + for (clog=0; clog= al->start_adr_real_logs) ) + { + *adr_finish_temp = *adr_current; // + // + adr_current--; + } + else + *adr_finish_temp = 0; // ! + + // + adr_finish_temp--; + + // ? + if (adr_current < al->start_adr_real_logs) + { + if (al->finish_adr_real_log) // ? + adr_current = al->finish_adr_real_log; // . + else + adr_current = al->start_adr_real_logs - 1; + } + } + + al->temp_log_ready = 1; +*/ + +} + + + + diff --git a/Inu/Src2/551/main/logs_hmi.h b/Inu/Src2/551/main/logs_hmi.h new file mode 100644 index 0000000..e7637f5 --- /dev/null +++ b/Inu/Src2/551/main/logs_hmi.h @@ -0,0 +1,86 @@ +/* + * logs_hmi.h + * + * Created on: 28 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef SRC_MAIN_LOGS_HMI_H_ +#define SRC_MAIN_LOGS_HMI_H_ + +#define _LOG_HMI_SMALL_TEST 0//1 + +#define PLACE_STORE_LOG_PULT_SD 1 //SD +#define PLACE_STORE_LOG_PULT_USB 2 //USB Flash + +typedef struct { + + int send_log; + +// int new_send_log_checked; + unsigned long log_size_sent; +// int flag_data_received; + + + +// unsigned int number_of_log; + unsigned long count_write_to_modbus; + +// unsigned long current_address; + unsigned long start_log_address; +// int log_address_step; + + int step; + int progress_bar; + int enable_progress_bar; + + int cleanLogs; + int tick_step; +// int tick_finish; + + int flag_log_array_sended; + int flag_start_log_array_sent; + + int flag_log_array_sent_process; + int count_data_in_buf; + unsigned long count_sended_to_pult; + + unsigned long max_size_logs_hmi; + + int tick_step2; + int tick_step3; + int tick_step4; + int tick_step5; + int n_log_array_sended; + + unsigned long max_size_logs_hmi_small; + unsigned long max_size_logs_hmi_full; + + int saveLogsToSDCard; + int ReportLogOut; + int sdusb; + +} t_Logs_with_modbus; + +#define LOGS_WITH_MODBUS_DEFAULTS {0,0,0,0,0, 0,0,0,0, 0,0,0,0,0, 0, 0,0,0,0,0, 0,0, 0,0,0} +extern t_Logs_with_modbus log_to_HMI; + + + + +#define LOG_START_ADRES 0xA0000UL +#define LOG_END_ADRES 0xF0000UL +#define LOG_BUFFER_SIZE 0x50000UL //0x100UL + +void fillLogArea(); //TODO for testing only + +int alarm_log_get_data(unsigned long pos, int type_log); + +int writeLogsArray(int flag_next); +static void prepareWriteLogsArray(void); +static int fillAnalogDataArrayForLogSend(void); +int sendLogToHMI(int status_ok); +void run_store_slow_logs(void); + + +#endif /* SRC_MAIN_LOGS_HMI_H_ */ diff --git a/Inu/Src2/551/main/manch.h b/Inu/Src2/551/main/manch.h new file mode 100644 index 0000000..d634beb --- /dev/null +++ b/Inu/Src2/551/main/manch.h @@ -0,0 +1,182 @@ +#ifndef MANCH_H +#define MANCH_H + +#ifdef __cplusplus +extern "C" { +#endif + + + + +struct MANCH_READ_BITS { // bits description + Uint16 but_0:1; // 1 + Uint16 but_1:1; // 1 + Uint16 but_2:1; // 1 + Uint16 but_3:1; // 1 + Uint16 but_4:1; // 1 + Uint16 but_5:1; // 1 + Uint16 but_6:1; // 1 + Uint16 but_7:1; // 1 + Uint16 press_any_key:1; // 0 +}; + + +union MANCH_READ_REG { + Uint16 all; + struct MANCH_READ_BITS bit; +}; + + +struct MANCH_WRITE_BITS { // bits description + int number0:14; // 1 + int number1:14; // 1 + Uint16 data_control:1; // 1 + Uint16 case_line_recive2:1; // 1 + Uint16 res0:1; // 1 + Uint16 res1:1; // 1 + Uint16 set_ratio_indicator:4; // 1 + union { + Uint16 all; + struct + { + Uint16 lamp_0:1; // 1 + Uint16 lamp_1:1; // 1 + Uint16 lamp_2:1; // 1 + Uint16 lamp_3:1; // 1 + Uint16 lamp_4:1; // 1 + Uint16 lamp_5:1; // 1 + Uint16 lamp_6:1; // 1 + Uint16 lamp_7:1; // 1 + Uint16 lamp_8:1; // 1 + Uint16 lamp_9:1; // 1 + Uint16 lamp_10:1; // 1 + Uint16 lamp_11:1; // 1 + Uint16 lamp_12:1; // 1 + Uint16 lamp_13:1; // 1 + Uint16 lamp_14:1; // 1 + Uint16 lamp_15:1; // 1 + } bit; + } lamps; + union { + Uint16 all; + struct + { + Uint16 lamp_0:1; // 1 + Uint16 lamp_1:1; // 1 + Uint16 lamp_2:1; // 1 + Uint16 lamp_3:1; // 1 + Uint16 lamp_4:1; // 1 + Uint16 lamp_5:1; // 1 + Uint16 lamp_6:1; // 1 + Uint16 lamp_7:1; // 1 + Uint16 lamp_8:1; // 1 + Uint16 lamp_9:1; // 1 + Uint16 lamp_10:1; // 1 + Uint16 lamp_11:1; // 1 + Uint16 lamp_12:1; // 1 + Uint16 lamp_13:1; // 1 + Uint16 lamp_14:1; // 1 + Uint16 lamp_15:1; // 1 + } bit; + } lamps_2; + Uint16 res2:1; // 1 + Uint16 res3:1; // 1 + Uint16 set_ratio_lamp:4; // 1 + Uint16 case_line_receive1:1; +}; + +/* + +struct MANCH_WRITE1_BITS { // bits description + Uint16 number0:16; // 1 +}; + + + +struct MANCH_WRITE2_BITS { // bits description + Uint16 number1:8; // 1 + Uint16 data_control:1; // 1 + Uint16 case_line_recive2:1; // 1 + Uint16 res10:1; // 1 + Uint16 res11:1; // 1 + + Uint16 res1:6; // 1 +}; + +struct MANCH_WRITE3_BITS { // bits description + Uint16 lamp_0:1; // 1 + Uint16 lamp_1:1; // 1 + Uint16 lamp_2:1; // 1 + Uint16 lamp_3:1; // 1 + Uint16 lamp_4:1; // 1 + Uint16 lamp_5:1; // 1 + Uint16 lamp_6:1; // 1 + Uint16 lamp_7:1; // 1 + Uint16 lamp_8:1; // 1 + Uint16 lamp_9:1; // 1 + Uint16 lamp_10:1; // 1 + Uint16 lamp_11:1; // 1 + Uint16 lamp_12:1; // 1 + Uint16 lamp_13:1; // 1 + Uint16 lamp_14:1; // 1 + Uint16 lamp_15:1; // 1 +}; + + +union MANCH_WRITE1_REG { + Uint16 all; + struct MANCH_WRITE1_BITS bit; +}; + +union MANCH_WRITE2_REG { + Uint16 all; + struct MANCH_WRITE2_BITS bit; +}; + +union MANCH_WRITE3_REG { + Uint16 all; + struct MANCH_WRITE3_BITS bit; +}; + +*/ + +typedef volatile struct { // bits description + union MANCH_READ_REG reg1; +} MANCH_READ_REGS; + +/* +typedef volatile struct { // bits description + union MANCH_WRITE1_REG reg1; + union MANCH_WRITE2_REG reg2; + union MANCH_WRITE3_REG reg3; +} MANCH_WRITE_REGS; +*/ + +typedef volatile struct MANCH_WRITE_BITS MANCH_WRITE_REGS; + + + + + +extern MANCH_READ_REGS ManchReadRegs_00; +extern MANCH_READ_REGS ManchReadRegs_01; +extern MANCH_READ_REGS ManchReadRegs_02; +extern MANCH_READ_REGS ManchReadRegs_03; + +extern MANCH_WRITE_REGS ManchWriteRegs_00; +extern MANCH_WRITE_REGS ManchWriteRegs_01; + + + +void read_manch(); +int write_manch(); +void tune_manch_lines_v1(); + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of MANCH_H definition + diff --git a/Inu/Src2/551/main/master_slave.c b/Inu/Src2/551/main/master_slave.c new file mode 100644 index 0000000..4aa4297 --- /dev/null +++ b/Inu/Src2/551/main/master_slave.c @@ -0,0 +1,586 @@ +/* + * master_slave.c + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#include + +#include +#include +#include +#include +#include +#include +#include "IQmathLib.h" +#include "mathlib.h" +#include +#include "synhro_tools.h" +#include "master_slave.h" + +////////////////////////////////////////////////////////// + +#pragma DATA_SECTION(buf_log_master_slave_status,".slow_vars"); +unsigned int buf_log_master_slave_status[SIZE_LOG_MASTER_SLAVE_STATUS] = {0}; +//AUTO_MASTER_SLAVE_DATA buf2[SIZE_BUF1] = {0}; +//AUTO_MASTER_SLAVE_DATA buf3[SIZE_BUF1] = {0}; +//OPTICAL_BUS_DATA_LOW_CMD buf4[SIZE_BUF1] = {0}; +//OPTICAL_BUS_DATA_LOW_CMD buf5[SIZE_BUF1] = {0}; + + +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// + +void auto_select_master_slave(void) +{ + static unsigned int count_try_master = 0; + static unsigned int count_wait_answer_confirm_mode = 0; + static unsigned int count_wait_slave_try_master = 0; + unsigned int err_confirm_mode = 0; // + static unsigned int c_buf_log_master_slave_status = 0, prev_status = 0; + + + +// logs master_slave_status + if (edrk.auto_master_slave.status != prev_status) + { + c_buf_log_master_slave_status++; + if (c_buf_log_master_slave_status>=SIZE_LOG_MASTER_SLAVE_STATUS) + c_buf_log_master_slave_status = 0; + buf_log_master_slave_status[c_buf_log_master_slave_status] = edrk.auto_master_slave.status; + } + prev_status = edrk.auto_master_slave.status; +//end logs master_slave_status + + if (edrk.ms.ready2==0 && edrk.errors.e7.bits.AUTO_SET_MASTER==0) + { + edrk.auto_master_slave.remoute.all = 0; + edrk.auto_master_slave.local.all = 0; + edrk.auto_master_slave.prev_remoute.all = edrk.auto_master_slave.remoute.all; + edrk.auto_master_slave.prev_local.all = edrk.auto_master_slave.local.all; + + edrk.auto_master_slave.status = 1; + +// if (prev_ready!=edrk.ms.ready2) +// for (c_buf=0;c_buf=SIZE_BUF1) +// c_buf = 0; +// +// buf1[c_buf] = edrk.auto_master_slave.status; +// buf2[c_buf].all = edrk.auto_master_slave.local.all; +// buf3[c_buf].all = edrk.auto_master_slave.remoute.all; +// buf4[c_buf].all = optical_read_data.data.cmd.all; +// buf5[c_buf].all = optical_write_data.data.cmd.all; +// + + // + if (edrk.auto_master_slave.local.bits.try_master==0 || + (edrk.auto_master_slave.prev_local.bits.try_master != edrk.auto_master_slave.local.bits.try_master && edrk.auto_master_slave.local.bits.try_master==1)) + count_try_master = 0; + + // OPTICAL_BUS , + if (edrk.errors.e7.bits.WRITE_OPTBUS==1 || edrk.errors.e7.bits.READ_OPTBUS==1 || + edrk.warnings.e7.bits.WRITE_OPTBUS==1 || edrk.warnings.e7.bits.READ_OPTBUS==1) + { + + if (edrk.errors.e7.bits.WRITE_OPTBUS==1 || edrk.errors.e7.bits.READ_OPTBUS==1) + { + // , + // - - + + edrk.errors.e7.bits.AUTO_SET_MASTER |= 1; + + edrk.auto_master_slave.remoute.bits.nothing = 1; + edrk.auto_master_slave.remoute.bits.master = 0; + edrk.auto_master_slave.remoute.bits.slave = 0; + edrk.auto_master_slave.remoute.bits.try_master = 0; + edrk.auto_master_slave.remoute.bits.try_slave = 0; + + + edrk.auto_master_slave.local.bits.master = 0; + edrk.auto_master_slave.local.bits.slave = 0; + edrk.auto_master_slave.local.bits.try_master = 0; + edrk.auto_master_slave.local.bits.try_slave = 0; + edrk.auto_master_slave.local.bits.nothing = 1; + + edrk.auto_master_slave.status = 10; + } + else + { + // , + // + edrk.warnings.e7.bits.AUTO_SET_MASTER = 1; + + edrk.auto_master_slave.remoute.bits.nothing = 1; + edrk.auto_master_slave.remoute.bits.master = 0; + edrk.auto_master_slave.remoute.bits.slave = 0; + edrk.auto_master_slave.remoute.bits.try_master = 0; + edrk.auto_master_slave.remoute.bits.try_slave = 0; + + + + edrk.auto_master_slave.local.bits.master = 1; + edrk.auto_master_slave.local.bits.slave = 0; + edrk.auto_master_slave.local.bits.try_master = 0; + edrk.auto_master_slave.local.bits.try_slave = 0; + edrk.auto_master_slave.local.bits.nothing = 1; + + edrk.auto_master_slave.status = 2; + } + + edrk.auto_master_slave.remoute.bits.sync_line_detect = 0; + edrk.auto_master_slave.remoute.bits.bus_off = 1; + edrk.auto_master_slave.remoute.bits.sync1_2 = 0; + + } + else + { + edrk.warnings.e7.bits.AUTO_SET_MASTER = 0; + + edrk.auto_master_slave.remoute.bits.bus_off = 0; + + // OPTICAL_BUS + + if (wait_synhro_optical_bus()==1) + { + + edrk.auto_master_slave.status = 50; // wait synhro + + + } + else + { + + + edrk.auto_master_slave.remoute.bits.master = optical_read_data.data.cmd.bit.master; + edrk.auto_master_slave.remoute.bits.slave = optical_read_data.data.cmd.bit.slave; + edrk.auto_master_slave.remoute.bits.try_master = optical_read_data.data.cmd.bit.maybe_master; + edrk.auto_master_slave.remoute.bits.sync1_2 = optical_read_data.data.cmd.bit.sync_1_2; + edrk.auto_master_slave.remoute.bits.sync_line_detect = optical_read_data.data.cmd.bit.sync_line_detect; + edrk.auto_master_slave.remoute.bits.tick = optical_read_data.data.cmd.bit.wdog_tick; + + if (optical_read_data.data.cmd.bit.master==0 && optical_read_data.data.cmd.bit.slave==0) + edrk.auto_master_slave.remoute.bits.nothing = 1; + + + ////////////////////////////////////////////////// + ////////////////////////////////////////////////// + // 1 + + // + if (edrk.auto_master_slave.remoute.bits.master) + { + + // -? + if (edrk.auto_master_slave.local.bits.master) + { + edrk.errors.e7.bits.AUTO_SET_MASTER |= 1; + edrk.auto_master_slave.status = 3; + } + else + { + // , slave + if (edrk.auto_master_slave.local.bits.master==0 && edrk.auto_master_slave.local.bits.slave==0) + { + // edrk.auto_master_slave.local.bits.try_slave = 1; + // slave + edrk.auto_master_slave.local.bits.slave = 1; + // + edrk.auto_master_slave.local.bits.try_master = 0; + edrk.auto_master_slave.status = 4; + } + else + { + edrk.auto_master_slave.status = 21; + } + } + } + else + ////////////////////////////////////////////////// + ////////////////////////////////////////////////// + // 2 + // slave + + if (edrk.auto_master_slave.remoute.bits.slave) + { + + // slave -? + if (edrk.auto_master_slave.local.bits.slave) + { + + // slave + if (edrk.auto_master_slave.prev_remoute.bits.slave==0) + { + if (edrk.Go) + { + // + edrk.errors.e7.bits.AUTO_SET_MASTER |= 1; + edrk.auto_master_slave.status = 5; + } + else + { + // master + edrk.auto_master_slave.local.bits.try_master = 1; + edrk.auto_master_slave.status = 6; + } + } + else + { + edrk.errors.e7.bits.AUTO_SET_MASTER |= 1; + edrk.auto_master_slave.status = 7; + } + + } + else + { + + // , master + if (edrk.auto_master_slave.local.bits.master==0 && edrk.auto_master_slave.local.bits.slave==0 && edrk.auto_master_slave.local.bits.try_master==0) + { + if (edrk.flag_second_PCH==0) + edrk.auto_master_slave.local.bits.try_master = 1; + if (edrk.flag_second_PCH==1) + edrk.auto_master_slave.local.bits.try_master = 1; + + edrk.auto_master_slave.status = 8; + // edrk.auto_master_slave.local.bits.slave = 1; + } + else + // , slave . + if (edrk.auto_master_slave.local.bits.master==0 && edrk.auto_master_slave.local.bits.slave==0 && edrk.auto_master_slave.local.bits.try_master==1) + { + // + edrk.auto_master_slave.local.bits.master = 1; + edrk.auto_master_slave.local.bits.try_master = 0; + edrk.auto_master_slave.status = 9; + // edrk.auto_master_slave.local.bits.slave = 1; + } + else + { + edrk.auto_master_slave.status = 22; + } + + } + } + else + ////////////////////////////////////////////////// + ////////////////////////////////////////////////// + // 3 + // + + if (edrk.auto_master_slave.remoute.bits.master==0 + && edrk.auto_master_slave.remoute.bits.slave==0 + && edrk.auto_master_slave.remoute.bits.try_master) + { + // slave + if (edrk.auto_master_slave.local.bits.slave) + { + // , slave + // , try_master + if (count_wait_slave_try_master +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "control_station.h" +#include "global_time.h" +#include "vector_control.h" +#include "x_basic_types.h" +#include "xp_cds_in.h" +#include "xp_hwp.h" +#include "xp_project.h" +#include "modbus_table_v2.h" +#include "filter_v1.h" +#include "v_rotor_22220.h" +#include "log_params.h" +#include "break_regul.h" +#include "logs_hmi.h" +#include "CAN_Setup.h" +#include "params_temper_p.h" + + +void func_unpack_answer_from_TMS_RS232(CMD_TO_TMS_STRUCT *pcommand) +{ + // y + unsigned int DataOut; + int Data, Data1, Data2, DataAnalog1, DataAnalog2, DataAnalog3, DataAnalog4, i; + unsigned int h; + volatile unsigned char *pByte; + // static int vs11,vs12,vs1; + // static int DataCnt=0; + // int GoT,Assemble_scheme; + // static int prev_temp_Rele1=0, temp_Rele1=0, prev_temp_Rele2=0, temp_Rele2=0; + + static int flag_prev_turn_on = 0; + static int flag_prev_turn_off = 0; + static int prev_byte01_bit4 = 0; + static int prev_byte01_bit1 = 0; + static int flag_wait_revers_sbor = 1; + static int flag_wait_revers_go = 1; + + static unsigned int count_transmited = 0; + + + // y + // + + if ((sizeof(CMD_TO_TMS_STRUCT)-5)>CONTROL_STATION_MAX_RAW_DATA) + xerror(main_er_ID(2),(void *)0); + + + + // , .. RS232 + pByte = (unsigned char *)(pcommand);//->analog_data.analog1_lo; + + + pByte++; + pByte++; + + for (h=0;h>1].all |= ( (*pByte) << 8) & 0xff00; + } + else + control_station.raw_array_data[CONTROL_STATION_TERMINAL_RS232][h>>1].all = ( (*pByte) ) & 0x00ff; + + pByte++; + } + +} + + + +void func_pack_answer_to_TMS(TMS_TO_TERMINAL_STRUCT *reply_a) +{ + // y + unsigned int DataOut; + int Data1, Data2, DataAnalog1, DataAnalog2, DataAnalog3, DataAnalog4, i; + float Data; + unsigned char *pByte; + // static int vs11,vs12,vs1; + // static int DataCnt=0; + // int GoT,Assemble_scheme; + // static int prev_temp_Rele1=0, temp_Rele1=0, prev_temp_Rele2=0, temp_Rele2=0; + + static int flag_prev_turn_on = 0; + static int flag_prev_turn_off = 0; + static int prev_byte01_bit4 = 0; + static int prev_byte01_bit1 = 0; + static int flag_wait_revers_sbor = 1; + static int flag_wait_revers_go = 1; + + static unsigned int count_transmited = 0; + /* const + */ + +// edrk.data_to_message2[1] = _IQtoF(filter.iqU_1_long)*NORMA_ACP; +// edrk.data_to_message2[2] = _IQtoF(filter.iqU_2_long)*NORMA_ACP; + + + //For instance + //reply->digit_data.byte01.byte_data = 0x43; + + + //1 + Data = _IQtoF(filter.iqU_1_long)*NORMA_ACP; + reply_a->analog_data.analog1_lo = LOBYTE(Data); + reply_a->analog_data.analog1_hi = HIBYTE(Data); + //2 + Data = _IQtoF(filter.iqU_2_long)*NORMA_ACP;//(project.adc[0].read.pbus.adc_value[1] - 2330)/4096*3.0/62.2*1000.0; + reply_a->analog_data.analog2_lo = LOBYTE(Data); + reply_a->analog_data.analog2_hi = HIBYTE(Data); + + //3 + Data = _IQtoF(filter.iqUin_m1)*NORMA_ACP;//(project.adc[0].read.pbus.adc_value[2] - 2330)/4096*3.0/62.2*1000.0; + reply_a->analog_data.analog3_lo = LOBYTE(Data); + reply_a->analog_data.analog3_hi = HIBYTE(Data); + +//4 +// Data = edrk.Status_Sbor;//_IQtoF(filter.iqUin_m2)*NORMA_ACP;//(project.adc[0].read.pbus.adc_value[3] - 2330)/4096*3.0/62.2*1000.0; + Data = _IQtoF(filter.iqUin_m2)*NORMA_ACP;//(project.adc[0].read.pbus.adc_value[3] - 2330)/4096*3.0/62.2*1000.0; +// Data = (_IQtoF((filter.Power) * 9000.0)); // + reply_a->analog_data.analog4_lo = LOBYTE(Data); + reply_a->analog_data.analog4_hi = HIBYTE(Data); + +//5 + Data = edrk.power_kw; // +// Data = (_IQtoF((analog.Power) * 9000.0)); // + //_IQtoF(analog.iqIin_1)*NORMA_ACP;//project.adc[0].read.pbus.adc_value[0]; + reply_a->analog_data.analog5_lo = LOBYTE(Data); + reply_a->analog_data.analog5_hi = HIBYTE(Data); + + Data = _IQtoF(analog.iqIin_sum)*NORMA_ACP;//project.adc[0].read.pbus.adc_value[1]; + reply_a->analog_data.analog6_lo = LOBYTE(Data); + reply_a->analog_data.analog6_hi = HIBYTE(Data); + + + Data = _IQtoF(filter.iqIm_1)*NORMA_ACP;//project.adc[0].read.pbus.adc_value[2]; + reply_a->analog_data.analog7_lo = LOBYTE(Data); + reply_a->analog_data.analog7_hi = HIBYTE(Data); + + Data = _IQtoF(filter.iqIm_2)*NORMA_ACP;//project.adc[0].read.pbus.adc_value[3]; + reply_a->analog_data.analog8_lo = LOBYTE(Data); + reply_a->analog_data.analog8_hi = HIBYTE(Data); + + Data = (int)(edrk.temper_edrk.max_real_int_temper_u); + reply_a->analog_data.analog9_lo = LOBYTE(Data); + reply_a->analog_data.analog9_hi = HIBYTE(Data); + + Data = (int) (edrk.temper_edrk.max_real_int_temper_water); + reply_a->analog_data.analog10_lo = LOBYTE(Data); + reply_a->analog_data.analog10_hi = HIBYTE(Data); + + Data = (int) (edrk.p_water_edrk.filter_real_int_p_water[0]); + reply_a->analog_data.analog11_lo = LOBYTE(Data); + reply_a->analog_data.analog11_hi = HIBYTE(Data); + + Data = (int) (edrk.temper_edrk.max_real_int_temper_air);//_IQtoF(edrk.f_stator)*F_STATOR_MAX;// + reply_a->analog_data.analog12_lo = LOBYTE(Data); + reply_a->analog_data.analog12_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(edrk.zadanie.iq_ZadanieU_Charge_rmp)*NORMA_ACP);//edrk.I_zad_vozbud;// + reply_a->analog_data.analog13_lo = LOBYTE(Data); + reply_a->analog_data.analog13_hi = HIBYTE(Data); + + Data = edrk.zadanie.oborots_zad;//edrk.I_zad_vozbud_exp;// + reply_a->analog_data.analog14_lo = LOBYTE(Data); + reply_a->analog_data.analog14_hi = HIBYTE(Data); + + Data = edrk.zadanie.power_zad;//edrk.I_cur_vozbud;// + reply_a->analog_data.analog15_lo = LOBYTE(Data); + reply_a->analog_data.analog15_hi = HIBYTE(Data); + + Data = edrk.zadanie.Izad;//edrk.I_cur_vozbud_exp;// + reply_a->analog_data.analog16_lo = LOBYTE(Data); + reply_a->analog_data.analog16_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(edrk.Kplus)*1000.0);//edrk.W_zad_mA;// + reply_a->analog_data.analog17_lo = LOBYTE(Data); + reply_a->analog_data.analog17_hi = HIBYTE(Data); + +Data = fast_round(edrk.freq_50hz_1/10.0);//edrk.Zadanie2VozbudING;// + reply_a->analog_data.analog18_lo = LOBYTE(Data); + reply_a->analog_data.analog18_hi = HIBYTE(Data); + +Data =fast_round(_IQtoF(edrk.f_stator)*NORMA_FROTOR*100.0);// 0;//edrk.Zadanie2VozbudMY;// + reply_a->analog_data.analog19_lo = LOBYTE(Data); + reply_a->analog_data.analog19_hi = HIBYTE(Data); + +Data = fast_round(_IQtoF(edrk.k_stator1)*10000.0);// edrk.W_from_all; + reply_a->analog_data.analog20_lo = LOBYTE(Data); + reply_a->analog_data.analog20_hi = HIBYTE(Data); + +Data = _IQtoF(vect_control.iqId1)*NORMA_ACP;//0;//_IQtoF(edrk.test_rms_Iu)*NORMA_ACP; //fast_round(_IQtoF(WRotor.iqWRotorImpulses1)*NORMA_FROTOR*1000.0);// edrk.W_from_DISPLAY; + reply_a->analog_data.analog21_lo = LOBYTE(Data); + reply_a->analog_data.analog21_hi = HIBYTE(Data); + +Data = _IQtoF(vect_control.iqIq1)*NORMA_ACP;// 0;//_IQtoF(edrk.test_rms_Ua)*NORMA_ACP;// fast_round(_IQtoF(WRotor.iqWRotorImpulses2)*NORMA_FROTOR*1000.0);//600.0*1000000000.0/WRotor.iqWRotorImpulses1;//edrk.W_from_SVU; + reply_a->analog_data.analog22_lo = LOBYTE(Data); + reply_a->analog_data.analog22_hi = HIBYTE(Data); + +//Data = fast_round(_IQtoF(WRotor.iqWRotorSumFilter3)*NORMA_FROTOR*100.0*60.0);//edrk.oborots;//fast_round(_IQtoF(WRotorPBus.iqAngle1F)*360.0);//600.0*1000000000.0/WRotor.iqWRotorImpulses2;//edrk.W_from_ZADAT4IK; +Data = _IQtoF(WRotor.iqWRotorSumFilter) * NORMA_FROTOR*600.0;//edrk.oborots; + reply_a->analog_data.analog23_lo = LOBYTE(Data); + reply_a->analog_data.analog23_hi = HIBYTE(Data); + +Data = fast_round(edrk.f_rotor_hz*100.0);//fast_round(_IQtoF(WRotorPBus.iqAngle2F)*360.0);//; + reply_a->analog_data.analog24_lo = LOBYTE(Data); + reply_a->analog_data.analog24_hi = HIBYTE(Data); + +//Data = _IQtoF(edrk.k_stator1)*10000;//; +Data = edrk.period_calc_pwm_int2;//fast_round(_IQtoF(rotor_22220.iqFdirty)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog25_lo = LOBYTE(Data); + reply_a->analog_data.analog25_hi = HIBYTE(Data); + +Data = edrk.power_kw_full; // +//fast_round(_IQtoF(WRotor.iqWRotorCalcBeforeRegul2)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog26_lo = LOBYTE(Data); + reply_a->analog_data.analog26_hi = HIBYTE(Data); + +Data = edrk.Sbor_Mode;//fast_round(_IQtoF(WRotorPBus.iqWRotorCalcBeforeRegul1)*NORMA_FROTOR*1000.0);//edrk.count_lost_interrupt; + reply_a->analog_data.analog27_lo = LOBYTE(Data); + reply_a->analog_data.analog27_hi = HIBYTE(Data); + +Data = edrk.Stage_Sbor;// fast_round(_IQtoF(WRotorPBus.iqWRotorCalcBeforeRegul2)*NORMA_FROTOR*1000.0);; + reply_a->analog_data.analog28_lo = LOBYTE(Data); + reply_a->analog_data.analog28_hi = HIBYTE(Data); + +Data = fast_round(_IQtoF(edrk.Izad_out)*NORMA_ACP);//edrk.I_zad_vozbud;//; + reply_a->analog_data.analog29_lo = LOBYTE(Data); + reply_a->analog_data.analog29_hi = HIBYTE(Data); + +Data = edrk.period_calc_pwm_int1; + reply_a->analog_data.analog30_lo = LOBYTE(Data); + reply_a->analog_data.analog30_hi = HIBYTE(Data); + + Data = (int)edrk.temper_acdrive.winding.max_real_int_temper; + reply_a->analog_data.analog31_lo = LOBYTE(Data); + reply_a->analog_data.analog31_hi = HIBYTE(Data); + Data = (int)edrk.temper_acdrive.bear.max_real_int_temper; + reply_a->analog_data.analog32_lo = LOBYTE(Data); + reply_a->analog_data.analog32_hi = HIBYTE(Data); + + + + Data = (int)(edrk.temper_edrk.real_int_temper_u[0]); + reply_a->analog_data.analog33_lo = LOBYTE(Data); + reply_a->analog_data.analog33_hi = HIBYTE(Data); + + Data = (int)(edrk.temper_edrk.real_int_temper_u[1]); + reply_a->analog_data.analog34_lo = LOBYTE(Data); + reply_a->analog_data.analog34_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_u[2]); + reply_a->analog_data.analog35_lo = LOBYTE(Data); + reply_a->analog_data.analog35_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_u[3]); + reply_a->analog_data.analog36_lo = LOBYTE(Data); + reply_a->analog_data.analog36_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_u[4]); + reply_a->analog_data.analog37_lo = LOBYTE(Data); + reply_a->analog_data.analog37_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_u[5]); + reply_a->analog_data.analog38_lo = LOBYTE(Data); + reply_a->analog_data.analog38_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_u[6]); + reply_a->analog_data.analog39_lo = LOBYTE(Data); + reply_a->analog_data.analog39_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_air[0]); + reply_a->analog_data.analog40_lo = LOBYTE(Data); + reply_a->analog_data.analog40_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_air[1]); + reply_a->analog_data.analog41_lo = LOBYTE(Data); + reply_a->analog_data.analog41_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_air[2]); + reply_a->analog_data.analog42_lo = LOBYTE(Data); + reply_a->analog_data.analog42_hi = HIBYTE(Data); + + Data = (int)(edrk.temper_edrk.real_int_temper_air[3]); + reply_a->analog_data.analog43_lo = LOBYTE(Data); + reply_a->analog_data.analog43_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_water[0]); // external + reply_a->analog_data.analog44_lo = LOBYTE(Data); + reply_a->analog_data.analog44_hi = HIBYTE(Data); + Data = (int)(edrk.temper_edrk.real_int_temper_water[1]); // internal + reply_a->analog_data.analog45_lo = LOBYTE(Data); + reply_a->analog_data.analog45_hi = HIBYTE(Data); + + + Data = fast_round(_IQtoF(simple_scalar1.pidF.OutMax)*NORMA_ACP);//edrk.auto_master_slave.prev_status;//fast_round(_IQtoF(edrk.zadanie.iq_ZadanieU_Charge_rmp)*NORMA_ACP); + reply_a->analog_data.analog46_lo = LOBYTE(Data); + reply_a->analog_data.analog46_hi = HIBYTE(Data); + + + Data = fast_round(_IQtoF(edrk.zadanie.iq_Izad_rmp)*NORMA_ACP); + reply_a->analog_data.analog47_lo = LOBYTE(Data); + reply_a->analog_data.analog47_hi = HIBYTE(Data); + Data = fast_round(_IQtoF(edrk.zadanie.iq_fzad_rmp)*NORMA_FROTOR*100.0); + reply_a->analog_data.analog48_lo = LOBYTE(Data); + reply_a->analog_data.analog48_hi = HIBYTE(Data); + Data = fast_round(_IQtoF(edrk.zadanie.iq_kzad_rmp)*10000.0); + reply_a->analog_data.analog49_lo = LOBYTE(Data); + reply_a->analog_data.analog49_hi = HIBYTE(Data); + Data = fast_round(_IQtoF(edrk.zadanie.iq_oborots_zad_hz_rmp)*NORMA_FROTOR*60.0); + reply_a->analog_data.analog50_lo = LOBYTE(Data); + reply_a->analog_data.analog50_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(edrk.zadanie.iq_power_zad_rmp)*NORMA_ACP*NORMA_ACP/1000.0); + reply_a->analog_data.analog51_lo = LOBYTE(Data); + reply_a->analog_data.analog51_hi = HIBYTE(Data); + + Data = _IQtoF(vect_control.iqId2)*NORMA_ACP;//0;//fast_round( _IQtoF(edrk.zadanie.iq_k_u_disbalance_rmp)*100.0); + reply_a->analog_data.analog52_lo = LOBYTE(Data); + reply_a->analog_data.analog52_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(edrk.zadanie.iq_limit_power_zad_rmp)*NORMA_ACP*NORMA_ACP/1000.0); + reply_a->analog_data.analog53_lo = LOBYTE(Data); + reply_a->analog_data.analog53_hi = HIBYTE(Data); + + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_OBOROTS || edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER) { + Data = fast_round(_IQtoF(turns.pidFvect.Out)*NORMA_ACP); + reply_a->analog_data.analog54_lo = LOBYTE(Data); + reply_a->analog_data.analog54_hi = HIBYTE(Data); + Data = fast_round(_IQtoF(turns.pidFvect.OutMax)*NORMA_ACP); + reply_a->analog_data.analog55_lo = LOBYTE(Data); + reply_a->analog_data.analog55_hi = HIBYTE(Data); + Data =fast_round(_IQtoF(power.pidP.Out)*NORMA_ACP); + reply_a->analog_data.analog56_lo = LOBYTE(Data); + reply_a->analog_data.analog56_hi = HIBYTE(Data); + Data = fast_round(_IQtoF(power.pidP.OutMax)*NORMA_ACP); + } else { + Data = fast_round(_IQtoF(simple_scalar1.pidF.Out)*NORMA_ACP); + reply_a->analog_data.analog54_lo = LOBYTE(Data); + reply_a->analog_data.analog54_hi = HIBYTE(Data); + Data = fast_round(_IQtoF(simple_scalar1.pidF.OutMin)*NORMA_ACP); + reply_a->analog_data.analog55_lo = LOBYTE(Data); + reply_a->analog_data.analog55_hi = HIBYTE(Data); + Data =fast_round(_IQtoF(simple_scalar1.pidPower.Out)*NORMA_ACP); + reply_a->analog_data.analog56_lo = LOBYTE(Data); + reply_a->analog_data.analog56_hi = HIBYTE(Data); + Data = fast_round(_IQtoF(simple_scalar1.pidPower.OutMax)*NORMA_ACP); + } + + reply_a->analog_data.analog57_lo = LOBYTE(Data); + reply_a->analog_data.analog57_hi = HIBYTE(Data); + + + + Data = fast_round(_IQtoF(simple_scalar1.Izad)*NORMA_ACP); + reply_a->analog_data.analog58_lo = LOBYTE(Data); + reply_a->analog_data.analog58_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(edrk.master_Iq)*NORMA_ACP); + reply_a->analog_data.analog59_lo = LOBYTE(Data); + reply_a->analog_data.analog59_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.mzz_zad_in2)*NORMA_ACP);//count_transmited++; + reply_a->analog_data.analog60_lo = LOBYTE(Data); + reply_a->analog_data.analog60_hi = HIBYTE(Data); +// + Data = modbus_table_can_in[123].all;// ( , ) + reply_a->analog_data.analog61_lo = LOBYTE(Data); + reply_a->analog_data.analog61_hi = HIBYTE(Data); + + Data = modbus_table_can_in[124].all;// () + reply_a->analog_data.analog62_lo = LOBYTE(Data); + reply_a->analog_data.analog62_hi = HIBYTE(Data); + + Data = modbus_table_can_in[125].all;// () + reply_a->analog_data.analog63_lo = LOBYTE(Data); + reply_a->analog_data.analog63_hi = HIBYTE(Data); + + Data = modbus_table_can_in[134].all;// + reply_a->analog_data.analog64_lo = LOBYTE(Data); + reply_a->analog_data.analog64_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.pidPower.SatErr)*NORMA_ACP);//project.cds_tk[3].optical_data_in.local_count_error; + reply_a->analog_data.analog65_lo = LOBYTE(Data); + reply_a->analog_data.analog65_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.pidPower.Fdb)*NORMA_ACP*NORMA_ACP/1000.0);//project.cds_tk[3].optical_data_out.local_count_error; + reply_a->analog_data.analog66_lo = LOBYTE(Data); + reply_a->analog_data.analog66_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.pidPower.Ref)*NORMA_ACP*NORMA_ACP/1000.0);//////optical_read_data.count_error_wdog; + reply_a->analog_data.analog67_lo = LOBYTE(Data); + reply_a->analog_data.analog67_hi = HIBYTE(Data); + + + Data = fast_round(_IQtoF(simple_scalar1.pidPower.Up)*NORMA_ACP);//edrk.auto_master_slave.status;//fast_round(_IQtoF(edrk.zadanie.iq_kplus_u_disbalance_rmp)*1000.0); + reply_a->analog_data.analog68_lo = LOBYTE(Data); + reply_a->analog_data.analog68_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(pll1.vars.pll_Uq)*NORMA_ACP); + reply_a->analog_data.analog69_lo = LOBYTE(Data); + reply_a->analog_data.analog69_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(pll1.vars.pll_Ud)*NORMA_ACP); + reply_a->analog_data.analog70_lo = LOBYTE(Data); + reply_a->analog_data.analog70_hi = HIBYTE(Data); + +Data = fast_round(_IQtoF(simple_scalar1.bpsi_curent)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog71_lo = LOBYTE(Data); + reply_a->analog_data.analog71_hi = HIBYTE(Data); + +Data = fast_round(_IQtoF(WRotor.iqWRotorSumFilter2)*NORMA_FROTOR*1000.0); //iqFlong + reply_a->analog_data.analog72_lo = LOBYTE(Data); + reply_a->analog_data.analog72_hi = HIBYTE(Data); + +//Data = fast_round(_IQtoF(WRotor.iqWRotorCalc1)*NORMA_FROTOR*1000.0); +Data = fast_round(_IQtoF(edrk.from_uom.iq_level_value_kwt)*NORMA_ACP*NORMA_ACP/1000.0);// ;//edrk.from_uom.level_value;//fast_round(_IQtoF(rotor_22220.iqFdirty)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog73_lo = LOBYTE(Data); + reply_a->analog_data.analog73_hi = HIBYTE(Data); + +//Data = fast_round(_IQtoF(WRotor.iqWRotorCalc2)*NORMA_FROTOR*1000.0); +Data = _IQtoF(vect_control.iqIq2)*NORMA_ACP;//0;//fast_round(_IQtoF(rotor_22220.iqF)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog74_lo = LOBYTE(Data); + reply_a->analog_data.analog74_hi = HIBYTE(Data); + +//Data = fast_round(_IQtoF(WRotor.iqWRotorImpulsesBeforeRegul1)*NORMA_FROTOR*1000.0);// edrk.W_from_DISPLAY; +Data = fast_round(_IQtoF(WRotor.iqWRotorSumFilter)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog75_lo = LOBYTE(Data); + reply_a->analog_data.analog75_hi = HIBYTE(Data); + +//Data = fast_round(_IQtoF(WRotor.iqWRotorImpulsesBeforeRegul2)*NORMA_FROTOR*1000.0);//600.0*1000000000.0/WRotor.iqWRotorImpulses1;//edrk.W_from_SVU; +Data = fast_round(_IQtoF(simple_scalar1.mzz_zad_int)*NORMA_ACP);//;//0;//fast_round(_IQtoF(rotor_22220.iqFlong)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog76_lo = LOBYTE(Data); + reply_a->analog_data.analog76_hi = HIBYTE(Data); + +//Data = fast_round(_IQtoF(WRotor.iqWRotorImpulses1)*NORMA_FROTOR*1000.0);// edrk.W_from_DISPLAY; + Data = _IQtoF(simple_scalar1.Izad)*NORMA_ACP_RMS;// 0;//fast_round(_IQtoF(WRotor.iqWRotorSumRamp)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog77_lo = LOBYTE(Data); + reply_a->analog_data.analog77_hi = HIBYTE(Data); + +//Data = fast_round(_IQtoF(WRotor.iqWRotorImpulses2)*NORMA_FROTOR*1000.0);//600.0*1000000000.0/WRotor.iqWRotorImpulses1;//edrk.W_from_SVU; + Data = WRotor.RotorDirectionSlow; + reply_a->analog_data.analog78_lo = LOBYTE(Data); + reply_a->analog_data.analog78_hi = HIBYTE(Data); + +Data = fast_round(_IQtoF(simple_scalar1.iqKoefOgran)*1000.0);//0;//fast_round(_IQtoF(WRotor.iqWRotorSum)*NORMA_FROTOR*1000.0);// edrk.W_from_DISPLAY; + reply_a->analog_data.analog79_lo = LOBYTE(Data); + reply_a->analog_data.analog79_hi = HIBYTE(Data); + +Data = fast_round(_IQtoF(simple_scalar1.iqKoefOgranIzad)*1000.0);//0;//fast_round(_IQtoF(WRotor.iqWRotorSumFilter)*NORMA_FROTOR*1000.0);//600.0*1000000000.0/WRotor.iqWRotorImpulses1;//edrk.W_from_SVU; + reply_a->analog_data.analog80_lo = LOBYTE(Data); + reply_a->analog_data.analog80_hi = HIBYTE(Data); + + Data = log_params.cur_volume_of_slow_log;//edrk.power_kw_full; // +// Data = (_IQtoF((analog.Power) * 9000.0)); // + //_IQtoF(analog.iqIin_1)*NORMA_ACP;//project.adc[0].read.pbus.adc_value[0]; + reply_a->analog_data.analog81_lo = LOBYTE(Data); + reply_a->analog_data.analog81_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(edrk.zadanie.iq_limit_power_zad)*NORMA_ACP*NORMA_ACP/1000.0); + reply_a->analog_data.analog82_lo = LOBYTE(Data); + reply_a->analog_data.analog82_hi = HIBYTE(Data); + + Data = break_result_1;//fast_round(_IQtoF(WRotor.iqWRotorSumFilter3)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog83_lo = LOBYTE(Data); + reply_a->analog_data.analog83_hi = HIBYTE(Data); + + Data = break_result_2;//WRotorPBus.RotorDirectionInstant; + reply_a->analog_data.analog84_lo = LOBYTE(Data); + reply_a->analog_data.analog84_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(edrk.all_limit_koeffs.sum_limit)*1000.0);//WRotorPBus.RotorDirectionCount; + reply_a->analog_data.analog85_lo = LOBYTE(Data); + reply_a->analog_data.analog85_hi = HIBYTE(Data); + + + Data = fast_round(_IQtoF(edrk.all_limit_koeffs.uom_limit)*1000.0);//WRotorPBus.RotorDirectionSlow2; + reply_a->analog_data.analog86_lo = LOBYTE(Data); + reply_a->analog_data.analog86_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(edrk.all_limit_koeffs.uin_freq_limit)*1000.0);//fast_round(_IQtoF(WRotor.iqWRotorSumRamp)*NORMA_FROTOR*1000.0); + reply_a->analog_data.analog87_lo = LOBYTE(Data); + reply_a->analog_data.analog87_hi = HIBYTE(Data); + + Data = _IQtoF(simple_scalar1.Im_regul)*NORMA_ACP_RMS;//(edrk.cantec_reg & 0xff);//edrk.pult_data.TimeToChangePump_from_pult;//0;//fast_round(_IQtoF(WRotor.iqWRotorCalc1Ramp)*NORMA_FROTOR*1000.0);;//WRotor.iqWRotorCalc1Ramp + reply_a->analog_data.analog88_lo = LOBYTE(Data); + reply_a->analog_data.analog88_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.pidPower.Ui)*NORMA_ACP);//(edrk.canrec_reg & 0xff);;//edrk.pult_data.nPCH_from_pult;//0;//fast_round(_IQtoF(WRotor.iqWRotorCalc2Ramp)*NORMA_FROTOR*1000.0);; + reply_a->analog_data.analog89_lo = LOBYTE(Data); + reply_a->analog_data.analog89_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.pidF.Fdb)*NORMA_FROTOR*1000.0);//(((unsigned long)edrk.canes_reg>>16) & 0x01ff); + reply_a->analog_data.analog90_lo = LOBYTE(Data); + reply_a->analog_data.analog90_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.pidF.Ref)*NORMA_FROTOR*1000.0);//(((unsigned long)edrk.canes_reg) & 0x3f); + reply_a->analog_data.analog91_lo = LOBYTE(Data); + reply_a->analog_data.analog91_hi = HIBYTE(Data); + + + Data = fast_round(_IQtoF(simple_scalar1.pidF.SatErr)*NORMA_ACP);//CanBusOffError;//0; + reply_a->analog_data.analog92_lo = LOBYTE(Data); + reply_a->analog_data.analog92_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.pidF.Ui)*NORMA_ACP);//CanTimeOutErrorTR;//0; + reply_a->analog_data.analog93_lo = LOBYTE(Data); + reply_a->analog_data.analog93_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.pidF.Up)*NORMA_ACP);//0; + reply_a->analog_data.analog94_lo = LOBYTE(Data); + reply_a->analog_data.analog94_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.iq_decr_mzz_power)*1000.0);//0;//simple_scalar1.k_ogr_n + reply_a->analog_data.analog95_lo = LOBYTE(Data); + reply_a->analog_data.analog95_hi = HIBYTE(Data); + + Data = fast_round(_IQtoF(simple_scalar1.iq_decr_mzz_power_filter)*1000.0);//fast_round(_IQtoF(edrk.zadanie.rmp_oborots_zad_hz.PosRampPlus1)*NORMA_FROTOR*60.0*450.0*1000.0); + reply_a->analog_data.analog96_lo = LOBYTE(Data); + reply_a->analog_data.analog96_hi = HIBYTE(Data); + +// Data = 0; +// reply_a->analog_data.analog97_lo = LOBYTE(Data); +// reply_a->analog_data.analog97_hi = HIBYTE(Data); + + + + pByte = &reply_a->digit_data.byte01.byte_data; + for (i = 0; i < 59; i++) //zero all dig data + { + *(pByte + i) = 0; + } + + +// reply->digit_data.byte01.byte_data = project.cds_in[1].read.pbus.data_in.all & 0xff; +// reply->digit_data.byte02.byte_data = (project.cds_in[1].read.pbus.data_in.all >> 8) & 0xff; + + reply_a->digit_data.byte01.byte_data = edrk.errors.e0.all & 0xff; + reply_a->digit_data.byte02.byte_data = (edrk.errors.e0.all >> 8) & 0xff; + + reply_a->digit_data.byte03.byte_data = edrk.errors.e1.all & 0xff; + reply_a->digit_data.byte04.byte_data = (edrk.errors.e1.all >> 8) & 0xff; + + reply_a->digit_data.byte05.byte_data = edrk.errors.e2.all & 0xff; + reply_a->digit_data.byte06.byte_data = (edrk.errors.e2.all >> 8) & 0xff; + + reply_a->digit_data.byte07.byte_data = edrk.errors.e3.all & 0xff; + reply_a->digit_data.byte08.byte_data = (edrk.errors.e3.all >> 8) & 0xff; + + reply_a->digit_data.byte09.byte_data = edrk.errors.e4.all & 0xff; + reply_a->digit_data.byte10.byte_data = (edrk.errors.e4.all >> 8) & 0xff; + + reply_a->digit_data.byte11.byte_data = edrk.errors.e5.all & 0xff; + reply_a->digit_data.byte12.byte_data = (edrk.errors.e5.all >> 8) & 0xff; + +//13 + if (edrk.Status_Perehod_Rascepitel) + reply_a->digit_data.byte13.bit_data.bit1 = 1; + else + reply_a->digit_data.byte13.bit_data.bit1 = 0; + + if (edrk.Status_Rascepitel_Ok) + reply_a->digit_data.byte13.bit_data.bit0 = 1; + else + reply_a->digit_data.byte13.bit_data.bit0 = 0; + + reply_a->digit_data.byte13.bit_data.bit2 = edrk.from_second_pch.bits.MASTER; + reply_a->digit_data.byte13.bit_data.bit3 = edrk.from_second_pch.bits.RASCEPITEL; + + reply_a->digit_data.byte13.bit_data.bit4 = edrk.warning; + reply_a->digit_data.byte13.bit_data.bit5 = edrk.overheat; + reply_a->digit_data.byte13.bit_data.bit6 = edrk.summ_errors; + reply_a->digit_data.byte13.bit_data.bit7 = edrk.Status_Ready.bits.ready_final; + + +// reply_a->digit_data.byte13.byte_data = edrk.errors.e6.all & 0xff; +// reply->digit_data.byte14.byte_data = (edrk.errors.e6.all >> 8) & 0xff; +/* + reply->digit_data.byte15.byte_data = edrk.errors.e7.all & 0xff; + reply->digit_data.byte16.byte_data = (edrk.errors.e7.all >> 8) & 0xff; + + reply->digit_data.byte17.byte_data = edrk.errors.e8.all & 0xff; + reply->digit_data.byte18.byte_data = (edrk.errors.e8.all >> 8) & 0xff; +*/ +//IN2 + reply_a->digit_data.byte14.byte_data = edrk.from_ing1.all & 0xff;// project.cds_in[1].read.pbus.data_in.all & 0xFF; + reply_a->digit_data.byte15.byte_data = (edrk.from_ing1.all >> 8) & 0xFF;//(project.cds_in[1].read.pbus.data_in.all >> 8) & 0xFF; + +// status plates + reply_a->digit_data.byte16.bit_data.bit0 = !(project.hwp[0].status == component_Ready);//XProject_balzam.IsReady_reg.bit.XPlaneHWP_Chanals_IsReady; + reply_a->digit_data.byte16.bit_data.bit1 = !(project.adc[0].status == component_Ready);//XProject_balzam.IsReady_reg.bit.XPlaneHWP_Chanals_IsReady; + reply_a->digit_data.byte16.bit_data.bit2 = !(project.adc[1].status == component_Ready); + reply_a->digit_data.byte16.bit_data.bit3 = !(project.cds_in[0].status == component_Ready);//XProject_balzam.IsReady_reg.bit.XPlaneIN0_IsReady; + reply_a->digit_data.byte16.bit_data.bit4 = !(project.cds_in[1].status == component_Ready);//XProject_balzam.IsReady_reg.bit.XPlaneIN1_IsReady; +// reply_ans->digit_data.byte21.bit_data.bit5 = !project.cds_in[2].status;//XProject_balzam.IsReady_reg.bit.XPlaneIN2_IsReady; + reply_a->digit_data.byte16.bit_data.bit5 = !(project.cds_out[0].status == component_Ready);//XProject_balzam.IsReady_reg.bit.XPlaneOUT0_IsReady; +// reply_ans->digit_data.byte21.bit_data.bit7 = !project.cds_out[1].status;//XProject_balzam.IsReady_reg.bit.XPlaneOUT1_IsReady; +// reply_ans->digit_data.byte22.bit_data.bit0 = !project.cds_out[2].status;//XProject_balzam.IsReady_reg.bit.XPlaneOUT2_IsReady; + reply_a->digit_data.byte16.bit_data.bit6 = !(project.cds_tk[0].status == component_Ready);//XProject_balzam.IsReady_reg.bit.XPlaneTK0_IsReady; + reply_a->digit_data.byte16.bit_data.bit7 = !(project.cds_tk[1].status == component_Ready);//XProject_balzam.IsReady_reg.bit.XPlaneTK1_IsReady; + reply_a->digit_data.byte17.bit_data.bit0 = !(project.cds_tk[2].status == component_Ready);//XProject_balzam.IsReady_reg.bit.XPlaneTK2_IsReady; + reply_a->digit_data.byte17.bit_data.bit1 = !(project.cds_tk[3].status == component_Ready);//!XProject_balzam.IsReady_reg.bit.XPlaneTK3_IsReady; +// reply_ans->digit_data.byte22.bit_data.bit5 = !project.adc[1].status;//XProject_balzam.IsReady_reg.bit.XPlaneHWP_Chanals_IsReady; + + +//IN1 + reply_a->digit_data.byte17.bit_data.bit2 = project.cds_in[0].read.pbus.data_in.bit.in0; + reply_a->digit_data.byte17.bit_data.bit3 = project.cds_in[0].read.pbus.data_in.bit.in1; + reply_a->digit_data.byte17.bit_data.bit4 = project.cds_in[0].read.pbus.data_in.bit.in2; + reply_a->digit_data.byte17.bit_data.bit5 = project.cds_in[0].read.pbus.data_in.bit.in3; + reply_a->digit_data.byte17.bit_data.bit6 = project.cds_in[0].read.pbus.data_in.bit.in4; + + reply_a->digit_data.byte17.bit_data.bit7 = project.cds_in[0].read.pbus.data_in.bit.in8; + + reply_a->digit_data.byte18.bit_data.bit0 = project.cds_in[0].read.pbus.data_in.bit.in9; + reply_a->digit_data.byte18.bit_data.bit1 = project.cds_in[0].read.pbus.data_in.bit.in10; + reply_a->digit_data.byte18.bit_data.bit2 = project.cds_in[0].read.pbus.data_in.bit.in11; + + +//out + reply_a->digit_data.byte18.bit_data.bit3 = edrk.to_ing.bits.ZARYAD_ON;// project.cds_out[0].write.sbus.data_out.bit.dout0; + + reply_a->digit_data.byte18.bit_data.bit4 = edrk.to_ing.bits.NAGREV_OFF;//project.cds_out[0].write.sbus.data_out.bit.dout1; + reply_a->digit_data.byte18.bit_data.bit5 = edrk.to_ing.bits.NASOS_1_ON;//project.cds_out[0].write.sbus.data_out.bit.dout2; + reply_a->digit_data.byte18.bit_data.bit6 = edrk.to_ing.bits.NASOS_2_ON;//project.cds_out[0].write.sbus.data_out.bit.dout3; + reply_a->digit_data.byte18.bit_data.bit7 = edrk.to_ing.bits.BLOCK_KEY_OFF;//project.cds _out[0].write.sbus.data_out.bit.dout4; + reply_a->digit_data.byte19.bit_data.bit0 = (edrk.to_shema.bits.UMP_ON_OFF || edrk.to_shema.bits.CROSS_UMP_ON_OFF);//project.cds_out[0].write.sbus.data_out.bit.dout5; + reply_a->digit_data.byte19.bit_data.bit1 = edrk.to_shema.bits.QTV_ON || edrk.to_shema.bits.QTV_ON_OFF || edrk.to_shema.bits.CROSS_QTV_ON_OFF;//project.cds_out[0].write.sbus.data_out.bit.dout6; + reply_a->digit_data.byte19.bit_data.bit2 = edrk.to_shema.bits.QTV_OFF;//project.cds_out[0].write.sbus.data_out.bit.dout7; + + reply_a->digit_data.byte19.bit_data.bit3 = edrk.to_ing.bits.RASCEPITEL_OFF; + reply_a->digit_data.byte19.bit_data.bit4 = edrk.to_ing.bits.RASCEPITEL_ON; + reply_a->digit_data.byte19.bit_data.bit5 = sync_data.local_flag_sync_1_2;// + reply_a->digit_data.byte19.bit_data.bit6 = edrk.flag_second_PCH;// + reply_a->digit_data.byte19.bit_data.bit7 = edrk.to_ing.bits.SMALL_LAMPA_AVARIA; //project.cds_out[0].write.sbus.data_out.bit.dout15; + +//20 + reply_a->digit_data.byte20.bit_data.bit0 = edrk.SumSbor; + + reply_a->digit_data.byte20.bit_data.bit1 = edrk.Status_Ready.bits.ready1; + reply_a->digit_data.byte20.bit_data.bit2 = edrk.Status_Ready.bits.ready2; + reply_a->digit_data.byte20.bit_data.bit3 = edrk.Status_Ready.bits.ready3; + reply_a->digit_data.byte20.bit_data.bit4 = edrk.Status_Ready.bits.ready4; + reply_a->digit_data.byte20.bit_data.bit5 = edrk.Status_Ready.bits.ready5; + reply_a->digit_data.byte20.bit_data.bit6 = edrk.Status_Charge; + reply_a->digit_data.byte20.bit_data.bit7 = edrk.Zaryad_OK; + + reply_a->digit_data.byte21.byte_data = edrk.errors.e6.all & 0xff; + reply_a->digit_data.byte22.byte_data = (edrk.errors.e6.all >> 8) & 0xff; + +// reply_a->digit_data.byte21.bit_data.bit0 = edrk.errors.e6.bits.UO6_KEYS; +// reply_a->digit_data.byte21.bit_data.bit1 = edrk.errors.e6.bits.UO7_KEYS; +// reply_a->digit_data.byte21.bit_data.bit2 = edrk.errors.e6.bits.UO1_KEYS; +// reply_a->digit_data.byte21.bit_data.bit3 = edrk.errors.e6.bits.ERR_PBUS; +// reply_a->digit_data.byte21.bit_data.bit4 = edrk.errors.e6.bits.ERR_SBUS; +// reply_a->digit_data.byte21.bit_data.bit5 = edrk.errors.e6.bits.ER_DISBAL_BATT; +// reply_a->digit_data.byte21.bit_data.bit6 = edrk.errors.e6.bits.ER_RAZBALANS_ALG; +// reply_a->digit_data.byte21.bit_data.bit7 = edrk.errors.e6.bits.RASCEPITEL_ERROR_NOT_ANSWER; + + + reply_a->digit_data.byte23.byte_data = edrk.errors.e7.all & 0xff; + reply_a->digit_data.byte24.byte_data = (edrk.errors.e7.all >> 8) & 0xff; + + + + // hwp + reply_a->digit_data.byte25.byte_data = project.hwp[0].read.comp_s.plus.all & 0xff; + reply_a->digit_data.byte26.byte_data = (project.hwp[0].read.comp_s.plus.all >> 8) & 0xff; + + reply_a->digit_data.byte27.byte_data = project.hwp[0].read.comp_s.minus.all & 0xff; + reply_a->digit_data.byte28.byte_data = (project.hwp[0].read.comp_s.minus.all >> 8) & 0xff; + + + reply_a->digit_data.byte29.bit_data.bit0 = control_station.active_control_station[CONTROL_STATION_TERMINAL_RS232]; + reply_a->digit_data.byte29.bit_data.bit1 = control_station.active_control_station[CONTROL_STATION_TERMINAL_CAN]; + reply_a->digit_data.byte29.bit_data.bit2 = control_station.active_control_station[CONTROL_STATION_INGETEAM_PULT_RS485]; + reply_a->digit_data.byte29.bit_data.bit3 = control_station.active_control_station[CONTROL_STATION_MPU_SVU_CAN]; + reply_a->digit_data.byte29.bit_data.bit4 = control_station.active_control_station[CONTROL_STATION_MPU_KEY_CAN]; + reply_a->digit_data.byte29.bit_data.bit5 = control_station.active_control_station[CONTROL_STATION_MPU_SVU_RS485]; + reply_a->digit_data.byte29.bit_data.bit6 = control_station.active_control_station[CONTROL_STATION_MPU_KEY_RS485]; + reply_a->digit_data.byte29.bit_data.bit7 = control_station.active_control_station[CONTROL_STATION_ZADATCHIK_CAN]; + + reply_a->digit_data.byte30.bit_data.bit0 = control_station.alive_control_station[CONTROL_STATION_TERMINAL_RS232]; + reply_a->digit_data.byte30.bit_data.bit1 = control_station.alive_control_station[CONTROL_STATION_TERMINAL_CAN]; + reply_a->digit_data.byte30.bit_data.bit2 = control_station.alive_control_station[CONTROL_STATION_INGETEAM_PULT_RS485]; + reply_a->digit_data.byte30.bit_data.bit3 = control_station.alive_control_station[CONTROL_STATION_MPU_SVU_CAN]; + reply_a->digit_data.byte30.bit_data.bit4 = control_station.alive_control_station[CONTROL_STATION_MPU_KEY_CAN]; + reply_a->digit_data.byte30.bit_data.bit5 = control_station.alive_control_station[CONTROL_STATION_MPU_SVU_RS485]; + reply_a->digit_data.byte30.bit_data.bit6 = control_station.alive_control_station[CONTROL_STATION_MPU_KEY_RS485]; + reply_a->digit_data.byte30.bit_data.bit7 = control_station.alive_control_station[CONTROL_STATION_ZADATCHIK_CAN]; + + + reply_a->digit_data.byte31.byte_data = optical_read_data.data.cmd.all & 0xff; + reply_a->digit_data.byte32.byte_data = (optical_read_data.data.cmd.all >> 8) & 0xff; + + reply_a->digit_data.byte33.byte_data = optical_write_data.data.cmd.all & 0xff; + reply_a->digit_data.byte34.byte_data = (optical_write_data.data.cmd.all >> 8) & 0xff; + + reply_a->digit_data.byte35.bit_data.bit0 = control_station.alive_control_station[CONTROL_STATION_VPU_CAN]; + reply_a->digit_data.byte35.bit_data.bit1 = control_station.active_control_station[CONTROL_STATION_VPU_CAN]; + + reply_a->digit_data.byte35.bit_data.bit2 = edrk.auto_master_slave.local.bits.master; + reply_a->digit_data.byte35.bit_data.bit3 = edrk.auto_master_slave.local.bits.slave; + reply_a->digit_data.byte35.bit_data.bit4 = edrk.auto_master_slave.local.bits.try_master; + + reply_a->digit_data.byte35.bit_data.bit5 = edrk.auto_master_slave.remoute.bits.master; + reply_a->digit_data.byte35.bit_data.bit6 = edrk.auto_master_slave.remoute.bits.slave; + reply_a->digit_data.byte35.bit_data.bit7 = edrk.auto_master_slave.remoute.bits.try_master; + + reply_a->digit_data.byte36.bit_data.bit0 = edrk.Status_Ready.bits.MasterSlaveActive; + reply_a->digit_data.byte36.bit_data.bit1 = edrk.ms.ready1; + reply_a->digit_data.byte36.bit_data.bit2 = edrk.ms.ready2; + reply_a->digit_data.byte36.bit_data.bit3 = edrk.flag_wait_both_ready2; + reply_a->digit_data.byte36.bit_data.bit4 = edrk.Ready1_another_bs; + reply_a->digit_data.byte36.bit_data.bit5 = edrk.Ready2_another_bs; + reply_a->digit_data.byte36.bit_data.bit6 = edrk.flag_another_bs_first_ready12; + reply_a->digit_data.byte36.bit_data.bit7 = edrk.flag_this_bs_first_ready12; + + + + + reply_a->digit_data.byte37.byte_data = edrk.errors.e8.all & 0xff; + reply_a->digit_data.byte38.byte_data = (edrk.errors.e8.all >> 8) & 0xff; + + reply_a->digit_data.byte39.bit_data.bit0 = edrk.RazborNotFinish; + reply_a->digit_data.byte39.bit_data.bit1 = edrk.RunZahvatRascepitel; + reply_a->digit_data.byte39.bit_data.bit2 = edrk.RunUnZahvatRascepitel; + reply_a->digit_data.byte39.bit_data.bit3 = edrk.Run_Rascepitel; + reply_a->digit_data.byte39.bit_data.bit4 = edrk.ms.ready3; + + reply_a->digit_data.byte39.bit_data.bit5 = edrk.StartGEDfromZadanie; + reply_a->digit_data.byte39.bit_data.bit6 = edrk.flag_wait_set_to_zero_zadanie; + reply_a->digit_data.byte39.bit_data.bit7 = edrk.flag_block_zadanie; + reply_a->digit_data.byte40.bit_data.bit0 = edrk.you_can_on_rascepitel; + reply_a->digit_data.byte40.bit_data.bit1 = edrk.StartGEDfromControl; + reply_a->digit_data.byte40.bit_data.bit2 = edrk.StartGED; + reply_a->digit_data.byte40.bit_data.bit3 = edrk.GoWait; + + reply_a->digit_data.byte40.bit_data.bit4 = edrk.stop_logs_rs232; + reply_a->digit_data.byte40.bit_data.bit5 = edrk.stop_slow_log; + + reply_a->digit_data.byte40.bit_data.bit6 = edrk.disable_limit_power_from_svu; + reply_a->digit_data.byte40.bit_data.bit7 = edrk.disable_uom; + + reply_a->digit_data.byte41.byte_data = edrk.errors.e9.all & 0xff; + reply_a->digit_data.byte42.byte_data = (edrk.errors.e9.all >> 8) & 0xff; + + reply_a->digit_data.byte43.byte_data = edrk.errors.e10.all & 0xff; + reply_a->digit_data.byte44.byte_data = (edrk.errors.e10.all >> 8) & 0xff; + + reply_a->digit_data.byte45.byte_data = edrk.errors.e11.all & 0xff; + reply_a->digit_data.byte46.byte_data = (edrk.errors.e11.all >> 8) & 0xff; + + reply_a->digit_data.byte47.byte_data = edrk.errors.e12.all & 0xff; + reply_a->digit_data.byte48.byte_data = (edrk.errors.e12.all >> 8) & 0xff; + + +// reply_a->digit_data.byte49.byte_data = 0; +// reply_a->digit_data.byte50.byte_data = 0; + // reply_a->digit_data.byte49.byte_data = 0; + + // reply_a->digit_data.byte49.bit_data.bit0 = edrk.from_ing1.bits.ALL_KNOPKA_AVARIA; + // reply_a->digit_data.byte49.bit_data.bit0 = edrk.from_ing1.bits.BLOCK_IZOL_AVARIA; + // reply_a->digit_data.byte49.bit_data.bit0 = edrk.from_ing1.bits.BLOCK_IZOL_NORMA; + reply_a->digit_data.byte49.bit_data.bit0 = edrk.from_ing1.bits.LOCAL_REMOUTE; + // reply_a->digit_data.byte49.bit_data.bit0 = edrk.from_ing1.bits.NAGREV_ON = !FROM_ING_NAGREV_ON; + // reply_a->digit_data.byte49.bit_data.bit0 = edrk.from_ing1.bits.NASOS_NORMA = !FROM_ING_NASOS_NORMA; + // reply_a->digit_data.byte49.bit_data.bit0 = edrk.from_ing1.bits.NASOS_ON = !FROM_ING_NASOS_ON; + // reply_a->digit_data.byte49.bit_data.bit0 = edrk.from_ing1.bits.OHLAD_UTE4KA_WATER = !FROM_ING_OHLAD_UTE4KA_WATER; + // edrk.from_ing1.bits.UPC_24V_NORMA = !FROM_ING_UPC_24V_NORMA; + //edrk.from_ing1.bits.OP_PIT_NORMA = !FROM_ING_OP_PIT_NORMA; + //edrk.from_ing1.bits.VENTIL_ON = !FROM_ING_VENTIL_ON; + // edrk.from_ing1.bits.VIPR_PREDOHR_NORMA = !FROM_ING_VIPR_PREDOHR_NORMA; + + // edrk.from_ing1.bits.ZARYAD_ON = !FROM_ING_ZARYAD_ON; + // edrk.from_ing1.bits.ZAZEML_OFF = !FROM_ING_ZAZEML_OFF; + // edrk.from_ing1.bits.ZAZEML_ON = !FROM_ING_ZAZEML_ON; + + reply_a->digit_data.byte49.bit_data.bit1 = edrk.from_ing2.bits.KEY_MINUS; + reply_a->digit_data.byte49.bit_data.bit2 = edrk.from_ing2.bits.KEY_PLUS; + reply_a->digit_data.byte49.bit_data.bit3 = edrk.from_ing2.bits.KEY_KVITIR; + + reply_a->digit_data.byte49.bit_data.bit4 = edrk.from_ing2.bits.KEY_SBOR; + reply_a->digit_data.byte49.bit_data.bit5 = edrk.from_ing2.bits.KEY_RAZBOR; + + // edrk.from_ing1.bits.RASCEPITEL_ON = FROM_ING_RASCEPITEL_ON_OFF; + + reply_a->digit_data.byte49.bit_data.bit6 = edrk.from_ing2.bits.SOST_ZAMKA; + reply_a->digit_data.byte49.bit_data.bit7 = edrk.from_shema_filter.bits.RAZBOR_SHEMA; + // + reply_a->digit_data.byte50.bit_data.bit0 = edrk.from_shema_filter.bits.SBOR_SHEMA; + + reply_a->digit_data.byte50.bit_data.bit1 = edrk.from_shema_filter.bits.ZADA_DISPLAY; + reply_a->digit_data.byte50.bit_data.bit2 = edrk.from_shema_filter.bits.SVU; + // edrk.from_shema.bits.KNOPKA_AVARIA = FROM_ALL_KNOPKA_AVARIA; + reply_a->digit_data.byte50.bit_data.bit3 = edrk.from_shema.bits.QTV_ON_OFF; + reply_a->digit_data.byte50.bit_data.bit4 = edrk.from_shema_filter.bits.UMP_ON_OFF; + reply_a->digit_data.byte50.bit_data.bit5 = edrk.from_shema_filter.bits.READY_UMP; + reply_a->digit_data.byte50.bit_data.bit6 = edrk.from_shema.bits.SVU_BLOCK_QTV; + reply_a->digit_data.byte50.bit_data.bit7 = edrk.errors_another_bs_from_can; + + + // reply_a->digit_data.byte44.byte_data = 0; + + + reply_a->digit_data.byte51.bit_data.bit0 = inc_sensor.break_sensor1; + reply_a->digit_data.byte51.bit_data.bit1 = inc_sensor.break_sensor2; + reply_a->digit_data.byte51.bit_data.bit2 = pll1.output.flag_find_pll; + reply_a->digit_data.byte51.bit_data.bit3 = log_params.stop_log_slow; + reply_a->digit_data.byte51.bit_data.bit4 = log_params.stop_log_level_1; + reply_a->digit_data.byte51.bit_data.bit5 = log_params.stop_log_level_2; + reply_a->digit_data.byte51.bit_data.bit6 = log_params.stop_log_slow_level_1; + reply_a->digit_data.byte51.bit_data.bit7 = log_params.stop_log_slow_level_2; + + + + reply_a->digit_data.byte52.bit_data.bit0 = edrk.from_zadat4ik.bits.KVITIR; + reply_a->digit_data.byte52.bit_data.bit1 = edrk.from_zadat4ik.bits.PLUS; + reply_a->digit_data.byte52.bit_data.bit2 = edrk.from_zadat4ik.bits.MINUS; + reply_a->digit_data.byte52.bit_data.bit3 = edrk.from_zadat4ik.bits.PROVOROT; + reply_a->digit_data.byte52.bit_data.bit4 = edrk.from_zadat4ik.bits.UOM_READY_ACTIVE; + reply_a->digit_data.byte52.bit_data.bit5 = edrk.from_zadat4ik.bits.UOM_LIMIT_3; + reply_a->digit_data.byte52.bit_data.bit6 = edrk.from_zadat4ik.bits.UOM_LIMIT_2; + reply_a->digit_data.byte52.bit_data.bit7 = edrk.from_zadat4ik.bits.UOM_LIMIT_1; + + + + reply_a->digit_data.byte53.bit_data.bit0 = edrk.Run_UMP; + reply_a->digit_data.byte53.bit_data.bit1 = edrk.Status_UMP_Ok; + reply_a->digit_data.byte53.bit_data.bit2 = edrk.Zaryad_UMP_Ok; + reply_a->digit_data.byte53.bit_data.bit3 = edrk.cmd_to_ump; + reply_a->digit_data.byte53.bit_data.bit4 = edrk.sbor_wait_ump1; + reply_a->digit_data.byte53.bit_data.bit5 = edrk.sbor_wait_ump2; + reply_a->digit_data.byte53.bit_data.bit6 = edrk.flag_enable_on_ump; + + reply_a->digit_data.byte53.bit_data.bit7 = edrk.local_ump_on_off; + reply_a->digit_data.byte54.bit_data.bit0 = edrk.local_ready_ump; + +/// + reply_a->digit_data.byte54.bit_data.bit1 = (modbus_table_can_in[128].all) ? 1 : 0; //cmd_local_charge PCH 0 + reply_a->digit_data.byte54.bit_data.bit2 = (modbus_table_can_in[131].all) ? 1 : 0; //cmd_local_uncharge PCH 0 + + reply_a->digit_data.byte54.bit_data.bit3 = (modbus_table_can_in[129].all) ? 1 : 0; //cmd_local_charge PCH 1 + reply_a->digit_data.byte54.bit_data.bit4 = (modbus_table_can_in[132].all) ? 1 : 0; //cmd_local_uncharge PCH 1 + + reply_a->digit_data.byte54.bit_data.bit5 = edrk.from_shema_filter.bits.UMP_ON_OFF; + reply_a->digit_data.byte54.bit_data.bit6 = edrk.SumSbor; + + reply_a->digit_data.byte55.bit_data.bit0 = edrk.power_limit.bits.limit_Iout; + reply_a->digit_data.byte55.bit_data.bit1 = edrk.power_limit.bits.limit_UOM; + reply_a->digit_data.byte55.bit_data.bit2 = edrk.power_limit.bits.limit_by_temper; + reply_a->digit_data.byte55.bit_data.bit3 = edrk.power_limit.bits.limit_from_SVU; + reply_a->digit_data.byte55.bit_data.bit4 = edrk.power_limit.bits.limit_from_uom_fast; + reply_a->digit_data.byte55.bit_data.bit5 = edrk.power_limit.bits.limit_from_freq; + reply_a->digit_data.byte55.bit_data.bit6 = edrk.power_limit.bits.limit_moment; + reply_a->digit_data.byte55.bit_data.bit7 = simple_scalar1.flag_decr_mzz_power; + + + reply_a->digit_data.byte56.bit_data.bit0 = (edrk.pult_cmd.log_what_memory & 0x1) ? 1 : 0; + reply_a->digit_data.byte56.bit_data.bit1 = (edrk.pult_cmd.log_what_memory & 0x2) ? 1 : 0; + + reply_a->digit_data.byte56.bit_data.bit2 = edrk.pult_data.flagSaveDataMoto ? 1 : 0; + + reply_a->digit_data.byte56.bit_data.bit3 = (edrk.pult_data.flagSaveSlowLogs) ? 1 : 0; + reply_a->digit_data.byte56.bit_data.bit4 = edrk.pult_cmd.send_log ? 1 : 0; + + reply_a->digit_data.byte56.bit_data.bit5 = (log_to_HMI.send_log==1) ? 1 : 0; + reply_a->digit_data.byte56.bit_data.bit6 = (log_to_HMI.send_log==2) ? 1 : 0; + reply_a->digit_data.byte56.bit_data.bit7 = (log_to_HMI.send_log==3) ? 1 : 0; + +// + reply_a->digit_data.byte57.bit_data.bit0 = (edrk.break_tempers[0] > ABNORMAL_TEMPER_BREAK_INT) ? 1 : 0; + reply_a->digit_data.byte57.bit_data.bit1 = (edrk.break_tempers[1] > ABNORMAL_TEMPER_BREAK_INT) ? 1 : 0; + reply_a->digit_data.byte57.bit_data.bit2 = (edrk.break_tempers[2] > ABNORMAL_TEMPER_BREAK_INT) ? 1 : 0; + reply_a->digit_data.byte57.bit_data.bit3 = (edrk.break_tempers[3] > ABNORMAL_TEMPER_BREAK_INT) ? 1 : 0; + + reply_a->digit_data.byte57.bit_data.bit4 = (edrk.break_tempers[0] > ALARM_TEMPER_BREAK_INT) ? 1 : 0; + reply_a->digit_data.byte57.bit_data.bit5 = (edrk.break_tempers[1] > ALARM_TEMPER_BREAK_INT) ? 1 : 0; + reply_a->digit_data.byte57.bit_data.bit6 = (edrk.break_tempers[2] > ALARM_TEMPER_BREAK_INT) ? 1 : 0; + reply_a->digit_data.byte57.bit_data.bit7 = (edrk.break_tempers[3] > ALARM_TEMPER_BREAK_INT) ? 1 : 0; + + reply_a->digit_data.byte58.bit_data.bit0 = (edrk.breaker_on==1) ? 1 : 0; + + reply_a->digit_data.byte58.bit_data.bit1 = edrk.warnings.e9.bits.BREAK_TEMPER_WARNING; + reply_a->digit_data.byte58.bit_data.bit2 = edrk.warnings.e9.bits.BREAK_TEMPER_ALARM; + reply_a->digit_data.byte58.bit_data.bit3 = edrk.warnings.e9.bits.BREAKER_GED_ON; + + + +// reply_a->digit_data.byte57.byte_data = 0;//(((unsigned long)edrk.canes_reg>>16) & 0x0ff); +// reply_a->digit_data.byte58.byte_data = 0;//(((unsigned long)edrk.canes_reg) & 0x3f); + reply_a->digit_data.byte59.byte_data = 0;//(((unsigned long)edrk.canes_reg>>24) & 0x1); + reply_a->digit_data.byte60.byte_data = 0; + + + + + return; +} + + diff --git a/Inu/Src2/551/main/message2.h b/Inu/Src2/551/main/message2.h new file mode 100644 index 0000000..0f93c42 --- /dev/null +++ b/Inu/Src2/551/main/message2.h @@ -0,0 +1,33 @@ +//////////////////////////////////////////// +// message.h +// +// : +// 1. y +// 2. +// 3. y +// +// +// y y y +// . INTEL 386SX Octagon +// TMS320C32 Texas Instruments. +// +// . +// y +// unsigned char = 8 +// TMS320C32 unsigned char = 32 , y +// 8 . +// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +// +// y +// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//////////////////////////////////////////// + +#ifndef MESSAGE_H +#define MESSAGE_H + +#include "RS_Function_terminal.h" + +//void func_fill_answer_to_TMS(TMS_TO_TERMINAL_STRUCT* reply_ans, CMD_TO_TMS_STRUCT* pcommand); +void func_pack_answer_to_TMS(TMS_TO_TERMINAL_STRUCT* reply_a); +void func_unpack_answer_from_TMS_RS232(CMD_TO_TMS_STRUCT* pcommand); +#endif //MESSAGE_H diff --git a/Inu/Src2/551/main/message2can.c b/Inu/Src2/551/main/message2can.c new file mode 100644 index 0000000..5b0a883 --- /dev/null +++ b/Inu/Src2/551/main/message2can.c @@ -0,0 +1,278 @@ +/* + * message2can.c + * + * Created on: 3 . 2020 . + * Author: Yura + */ +#include +#include +#include +#include +#include +#include +#include + +#include "control_station.h" +#include "CAN_Setup.h" +#include "global_time.h" +#include "IQmathLib.h" +#include "DSP281x_Device.h" +#include "x_basic_types.h" +#include "xp_cds_in.h" +#include "xp_hwp.h" +#include "xp_project.h" + + +void detecting_cmd_from_can(void) +{ + + if (control_station.alive_control_station[CONTROL_STATION_TERMINAL_CAN]) + { + func_unpack_answer_from_TMS_CAN((TERMINAL_UNITES_STRUCT_handle)&TerminalUnites[edrk.number_can_box_terminal_cmd][0]); + } + +} + + +void func_unpack_answer_from_TMS_CAN(TERMINAL_UNITES_STRUCT_handle unites_t) +{ + // y + unsigned int DataOut,h; + int Data, Data1, Data2, DataAnalog1, DataAnalog2, DataAnalog3, DataAnalog4,DataAnalog5,DataAnalog6, i; + unsigned char *pByte; + // static int vs11,vs12,vs1; + // static int DataCnt=0; + // int GoT,Assemble_scheme; + // static int prev_temp_Rele1=0, temp_Rele1=0, prev_temp_Rele2=0, temp_Rele2=0; + + static int flag_prev_turn_on = 0; + static int flag_prev_turn_off = 0; + static int prev_byte01_bit4 = 0; + static int prev_byte01_bit1 = 0; + static int flag_wait_revers_sbor = 1; + static int flag_wait_revers_go = 1; + + static unsigned int count_transmited = 0; + + + // + + if (TERMINAL_UNIT_LEN>CONTROL_STATION_MAX_RAW_DATA) + xerror(main_er_ID(2),(void *)0); + + + + // , .. RS232 + // pByte = (unsigned char *)(pcommand);//->analog_data.analog1_lo; + + for (h=0;hbuf[h].all; + } + + /* + + if (control_station.alive_control_station[CONTROL_STATION_TERMINAL_CAN]==0) + { + edrk.from_can.bits.ACTIVE = 0; + return; + } + + if ((control_station.active_control_station[CONTROL_STATION_TERMINAL_RS232]==1)) + { + edrk.from_can.bits.ACTIVE = 0; + return; + } + + // unites_t->buf[0].bits.bit0 + + edrk.test_mode = 0; + + edrk.from_can.bits.ACTIVE = unites_t->buf[6].bits.bit3; + + if (edrk.from_can.bits.ACTIVE==0) + return; + +// f.RScount = SECOND * 3; + + // unites_t-> +// StartGED + + if (edrk.summ_errors) + { + flag_wait_revers_go = 1; + } + + if (flag_wait_revers_go==1) + edrk.StartGEDRS = 0; + if (unites_t->buf[6].bits.bit0 && flag_wait_revers_go) + edrk.StartGEDRS = 0; + if (unites_t->buf[6].bits.bit0==0) + edrk.StartGEDRS = 0; + if (unites_t->buf[6].bits.bit0==0 && flag_wait_revers_go) + flag_wait_revers_go = 0; + if (unites_t->buf[6].bits.bit0==1 && flag_wait_revers_go==0) + edrk.StartGEDRS = 1; + +// edrk.StartGEDRS = pcommand->digit_data.Byte01.bit_data.bit0; + +// end StartGED + + + edrk.Mode_UFConst = unites_t->buf[6].bits.bit2; + + +//////////////// + + if (unites_t->buf[6].bits.bit1 && prev_byte01_bit1==0) + edrk.KvitirRS = 1; + + prev_byte01_bit1 = unites_t->buf[6].bits.bit1; + + +// edrk.from_rs.bits.RAZBOR_SHEMA = pcommand->digit_data.Byte01.bit_data.bit5; + + + +// SBOR SHEMA + if (edrk.summ_errors) + { + flag_wait_revers_sbor = 1; + } + + if (flag_wait_revers_sbor==1) + edrk.from_can.bits.SBOR_SHEMA = 0; + + if (unites_t->buf[6].bits.bit4 && flag_wait_revers_sbor) + edrk.from_can.bits.SBOR_SHEMA = 0; + + if (unites_t->buf[6].bits.bit4==0) + edrk.from_can.bits.SBOR_SHEMA = 0; + + if (unites_t->buf[6].bits.bit4==0 && flag_wait_revers_sbor) + flag_wait_revers_sbor = 0; + + if (unites_t->buf[6].bits.bit4==1 && flag_wait_revers_sbor==0) + edrk.from_can.bits.SBOR_SHEMA = unites_t->buf[6].bits.bit4; + + prev_byte01_bit4 = unites_t->buf[6].bits.bit4; + +// end SBOR SHEMA + + + +// if (edrk.from_rs.bits.RAZBOR_SHEMA) + // edrk.from_rs.bits.SBOR_SHEMA = 0; + + //edrk.SborRS = pcommand->digit_data.Byte01.bit_data.bit4; + + + edrk.SelectPump0_1 = unites_t->buf[6].bits.bit6; + edrk.DirectOUT = unites_t->buf[6].bits.bit7; + + edrk.DirectNagrevOff = unites_t->buf[6].bits.bit8; + edrk.DirectBlockKeyOff = unites_t->buf[6].bits.bit9; + edrk.DirectPumpON = unites_t->buf[6].bits.bit10; + edrk.DirectZaryadOn = unites_t->buf[6].bits.bit11; + +#ifdef STENDD + + // edrk.to_shema.bits.QTV_ON = pcommand->digit_data.Byte02.bit_data.bit3; + +#endif + + edrk.Status_Ready.bits.ImitationReady2 = unites_t->buf[6].bits.bit12; + + edrk.SetSpeed = unites_t->buf[6].bits.bit13; + + + +// edrk.RemouteFromRS = pcommand->digit_data.Byte01.bit_data.bit3; + + + + +// edrk.VozbudOnOffFromRS = pcommand->digit_data.Byte01.bit_data.bit1; +// edrk.enable_set_vozbud = pcommand->digit_data.Byte01.bit_data.bit1; +// edrk.SborRS = pcommand->digit_data.Byte01.bit_data.bit2; +// edrk.RazborRS = pcommand->digit_data.Byte01.bit_data.bit3; +// edrk.DirectOUT = pcommand->digit_data.Byte01.bit_data.bit4; + +// edrk.StartGED = pcommand->digit_data.Byte01.bit_data.bit6; + + +// f.flag_distance = pcommand->digit_data.Byte01.bit_data.bit6; +// f.Set_power = pcommand->digit_data.Byte01.bit_data.bit7; + + f.Obmotka1 = unites_t->buf[6].bits.bit15; + f.Obmotka2 = unites_t->buf[7].bits.bit0; + + edrk.disable_alg_u_disbalance = unites_t->buf[7].bits.bit1; + + // f.Down50 = pcommand->digit_data.Byte02.bit_data.bit2; +// f.Up50 = pcommand->digit_data.Byte02.bit_data.bit3; +// f.Ciclelog = pcommand->digit_data.Byte02.bit_data.bit4; + + // if (SPEED_SELECT_ZADAT==1) +// f.Provorot = pcommand->digit_data.Byte02.bit_data.bit5; + + +// Data1 = pcommand->analog_data.analog1_hi; +// Data2 = pcommand->analog_data.analog1_lo; +// Data = (Data2 + Data1 * 256); +// if (Data > 32767) +// Data = Data - 65536; + DataAnalog1 = unites_t->buf[0].all; + +// Data1 = pcommand->analog_data.analog2_hi; +// Data2 = pcommand->analog_data.analog2_lo; +// Data = (Data2 + Data1 * 256); +// if (Data > 32767) +// Data = Data - 65536; + DataAnalog2 = unites_t->buf[1].all; + +// Data1 = pcommand->analog_data.analog3_hi; +// Data2 = pcommand->analog_data.analog3_lo; +// Data = (Data2 + Data1 * 256); +// if (Data > 32767) +// Data = Data - 65536; + DataAnalog3 = unites_t->buf[2].all; + +// Data1 = pcommand->analog_data.analog4_hi; +// Data2 = pcommand->analog_data.analog4_lo; +// Data = (Data2 + Data1 * 256); +// if (Data > 32767) +// Data = Data - 65536; + DataAnalog4 = unites_t->buf[3].all; + DataAnalog5 = unites_t->buf[4].all; + DataAnalog6 = unites_t->buf[5].all; + + + edrk.W_from_RS = DataAnalog1; + edrk.I_zad_vozb_add_from_RS = 0;//DataAnalog4; + + + if (!edrk.SetSpeed) + { + if (DataAnalog3<0) + edrk.ZadanieU_Charge_RS = 0; + else + edrk.ZadanieU_Charge_RS = DataAnalog3; + } + + if (edrk.SetSpeed) + { + edrk.fzad = DataAnalog1/100.0; + edrk.kzad = DataAnalog2/10000.0; + edrk.k_u_disbalance = _IQ(DataAnalog4/100.0); + edrk.kplus_u_disbalance = _IQ(DataAnalog3/1000.0); + + } +*/ + return; +} + + + + + diff --git a/Inu/Src2/551/main/message2can.h b/Inu/Src2/551/main/message2can.h new file mode 100644 index 0000000..14ad7da --- /dev/null +++ b/Inu/Src2/551/main/message2can.h @@ -0,0 +1,18 @@ +/* + * message2can.h + * + * Created on: 3 . 2020 . + * Author: Yura + */ + +#ifndef SRC_MAIN_MESSAGE2CAN_H_ +#define SRC_MAIN_MESSAGE2CAN_H_ + +#include "CAN_Setup.h" + +void func_unpack_answer_from_TMS_CAN(TERMINAL_UNITES_STRUCT_handle); +void detecting_cmd_from_can(void); + + + +#endif /* SRC_MAIN_MESSAGE2CAN_H_ */ diff --git a/Inu/Src2/551/main/message2test.c b/Inu/Src2/551/main/message2test.c new file mode 100644 index 0000000..fbcff9e --- /dev/null +++ b/Inu/Src2/551/main/message2test.c @@ -0,0 +1,678 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "CAN_Setup.h" +#include "IQmathLib.h" +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "RS_Functions.h" +#include "xp_project.h" + +#include "x_wdog.h" +#include "params_hwp.h" +#include "detect_errors.h" + + +//XilinxV2 + + +void func_fill_answer_to_TMS_test(TMS_TO_TERMINAL_TEST_ALL_STRUCT* reply_ans, CMD_TO_TMS_TEST_ALL_STRUCT* pcommand) +{ + // y + unsigned int crc, DataOut, sinusImpulse, doubleImpulse,adc_plate; + int Data,Data1,Data2/*,bitt, DataAnalog1, DataAnalog2*/, tk0,tk1,tk2,tk3,period1,period2, period3; + + //static int vs11,vs12,vs1; + static int prev_Go = 0; + static int prev_Prepare = 0; + + static int flag_prev_turn_on = 0; + static int flag_prev_turn_off = 0; + static int flag_prev_lamp_on_off = 0; + static int soft_off_enable = 0, soft_on_enable = 0; + static float tk_time_soft_off = 0; + static unsigned long tk_time_soft_off_d = 0; + static unsigned int i_af_protect_a = 0, i_af_protect_d = 0; + int enable_line_err = 0, disable_tk_soft_off, disable_protect_tk_soft_off; + + + stop_wdog(); + + edrk.test_mode = 1; + // const + // + +// TMS_TO_TERMINAL_TEST_ALL_STRUCT* const pcommand = ((TMS_TO_TERMINAL_TEST_ALL_STRUCT*)reply); + + // - y + // ? + +// f.RScount = SECOND*3; + + f.terminal_prepare = pcommand->digit_data.byte05.bit_data.bit1; + soft_off_enable = pcommand->digit_data.byte06.bit_data.bit0; + soft_on_enable = pcommand->digit_data.byte06.bit_data.bit1; +// edrk.direct_write_out = pcommand->digit_data.byte06.bit_data.bit2; + + disable_tk_soft_off = pcommand->digit_data.byte06.bit_data.bit3; + disable_protect_tk_soft_off = pcommand->digit_data.byte06.bit_data.bit4; + + enable_line_err = pcommand->digit_data.byte06.bit_data.bit5; + + // + +#if (CHECK_IN_OUT_TERMINAL==1) + +#if(C_cds_out_number>=1) + project.cds_out[0].write.sbus.data_out.all = ~(pcommand->digit_data.byte07.byte_data | ((pcommand->digit_data.byte08.byte_data) << 8)); +#endif +#if(C_cds_out_number>=2) + project.cds_out[1].write.sbus.data_out.all = ~(pcommand->digit_data.byte09.byte_data | ((pcommand->digit_data.byte10.byte_data) << 8)); +#endif +#if(C_cds_out_number>=3) + project.cds_out[2].write.sbus.data_out.all = ~(pcommand->digit_data.byte11.byte_data | ((pcommand->digit_data.byte12.byte_data) << 8)); +#endif + +#endif //CHECK_IN_OUT + + if (pcommand->digit_data.byte05.bit_data.bit1 == 1) + { + + //xreset_error_all(); + } + + + +// write_dig_out(); + + //calc_norm_ADC(0); + calc_norm_ADC_0(1); + calc_norm_ADC_1(1); + + // + tk0 = (pcommand->digit_data.byte01.byte_data); + tk1 = (pcommand->digit_data.byte02.byte_data); + tk2 = (pcommand->digit_data.byte03.byte_data); + tk3 = (pcommand->digit_data.byte04.byte_data); + + Data1 = pcommand->analog_data.analog1_hi; + Data2 = pcommand->analog_data.analog1_lo; + Data = (Data2 + Data1*256); + period1 = Data; + + Data1 = pcommand->analog_data.analog2_hi; + Data2 = pcommand->analog_data.analog2_lo; + Data = (Data2 + Data1*256); + period2 = Data; + + Data1 = pcommand->analog_data.analog3_hi; + Data2 = pcommand->analog_data.analog3_lo; + Data = (Data2 + Data1*256); + period3 = Data; + + Data1 = pcommand->analog_data.analog4_hi; + Data2 = pcommand->analog_data.analog4_lo; + Data = (Data2 + Data1*256); + // Data = 200; + tk_time_soft_off = Data*100.0; // mks*10->ns + if (tk_time_soft_off>1300000.0) + tk_time_soft_off = 1300000.0; + tk_time_soft_off_d = (unsigned long)(tk_time_soft_off / DIV_TIME_TK_SOFT_OFF); + + if (tk_time_soft_off_d>65535) + tk_time_soft_off_d = 65535; + + + Data1 = pcommand->analog_data.analog5_hi; + Data2 = pcommand->analog_data.analog5_lo; + Data = (Data2 + Data1*256); + i_af_protect_a = Data; + + if (i_af_protect_a>LEVEL_HWP_I_AF) i_af_protect_a = LEVEL_HWP_I_AF; + if (i_af_protect_a<10) i_af_protect_a = 10; + i_af_protect_d = convert_real_to_mv_hwp(4,i_af_protect_a); + if (i_af_protect_d>1500) i_af_protect_d = 1500; // max 1500 mV + + update_maz_level_i_af(0, i_af_protect_d); + project.read_all_hwp(); + + + + if(pcommand->digit_data.byte05.bit_data.bit3 == 1) + doubleImpulse = 1; + else + doubleImpulse = 0; + + if(pcommand->digit_data.byte05.bit_data.bit5 == 1) + sinusImpulse = 1; + else + sinusImpulse = 0; + + if ((pcommand->digit_data.byte05.bit_data.bit0 == 1) && (prev_Go == 0)) + { + if (pcommand->digit_data.byte05.bit_data.bit2 == 1) // + { + update_maz_level_i_af(0, 1500); + project.write_all_hwp(); + clear_errors(); + project.clear_errors_all_plates(); + update_maz_level_i_af(0, i_af_protect_d); + project.write_all_hwp(); + + } + + +// test_tk_ak_one_impulse( tk0, tk1, tk2, tk3, period1, period2); +#if (USE_TK_0) + project.cds_tk[0].write.sbus.protect_error.bit.enable_soft_disconnect = !disable_tk_soft_off; + project.cds_tk[0].write.sbus.protect_error.bit.detect_soft_disconnect = !disable_protect_tk_soft_off; + project.cds_tk[0].write.sbus.protect_error.bit.enable_line_err = enable_line_err; + project.cds_tk[0].write.sbus.time_after_err = tk_time_soft_off_d;//(int)(tk_time_soft_off / DIV_TIME_TK_SOFT_OFF); +#endif +#if (USE_TK_1) + project.cds_tk[1].write.sbus.protect_error.bit.enable_soft_disconnect = !disable_tk_soft_off; + project.cds_tk[1].write.sbus.protect_error.bit.detect_soft_disconnect = !disable_protect_tk_soft_off; + project.cds_tk[1].write.sbus.protect_error.bit.enable_line_err = enable_line_err; + project.cds_tk[1].write.sbus.time_after_err = tk_time_soft_off_d;//(int)(tk_time_soft_off / DIV_TIME_TK_SOFT_OFF); +#endif +#if (USE_TK_3) + project.cds_tk[3].write.sbus.protect_error.bit.enable_soft_disconnect = !disable_tk_soft_off; + project.cds_tk[3].write.sbus.protect_error.bit.detect_soft_disconnect = !disable_protect_tk_soft_off; + project.cds_tk[3].write.sbus.protect_error.bit.enable_line_err = enable_line_err; + project.cds_tk[3].write.sbus.time_after_err = tk_time_soft_off_d;//(int)(tk_time_soft_off / DIV_TIME_TK_SOFT_OFF); +#endif + + + project.write_all_sbus(); + project.write_all_hwp(); + + test_tk_ak_one_impulse( tk0, tk1, tk2, tk3, period1, period2, period3, doubleImpulse, sinusImpulse, soft_off_enable, soft_on_enable); + } + + if ((pcommand->digit_data.byte05.bit_data.bit0 == 1) && + (pcommand->digit_data.byte05.bit_data.bit3 == 1) && (prev_Go == 0)) + { +// test_tk_ak_sinus_period( tk0, tk1, tk2, tk3, period1, period2); + } + prev_Go = pcommand->digit_data.byte05.bit_data.bit0; + + f.Prepare = pcommand->digit_data.byte05.bit_data.bit1; + if (pcommand->digit_data.byte05.bit_data.bit1 != prev_Prepare) + { + if (pcommand->digit_data.byte05.bit_data.bit1==1) + { + stop_wdog(); + update_maz_level_i_af(0, 1500); + project.write_all_hwp(); + clear_errors(); + project.clear_errors_all_plates(); + update_maz_level_i_af(0, i_af_protect_d); + project.write_all_hwp(); + } + } + prev_Prepare = pcommand->digit_data.byte05.bit_data.bit1; + + if (pcommand->digit_data.byte05.bit_data.bit2 == 1) + { + + prev_Go = 0; // Go + } + +// break_all_on_off(pcommand->digit_data.byte05.bit_data.bit5); + +/* + if (pcommand->digit_data.byte05.bit_data.bit5 != flag_prev_turn_off) //turn off + { + if(pcommand->digit_data.byte05.bit_data.bit5 == 1) + { + project.cds_out[0].fpga.Write.Dout.bit.dout2 = 1; + project.cds_out[0].fpga.Write.Dout.bit.dout12 = 1; + cds_out_all(cds_out_WriteAll); + pause_1000(100000); + pause_1000(100000); + pause_1000(100000); + pause_1000(100000); + project.cds_out[0].fpga.Write.Dout.bit.dout2 = 0; + project.cds_out[0].fpga.Write.Dout.bit.dout12 = 0; + cds_out_all(cds_out_WriteAll); + //f.Ready2 = 0; + f.On_Power_QTV = 0; + edrk.Go = 0; + + } + + flag_prev_turn_off = pcommand->digit_data.byte05.bit_data.bit5; + cds_out_all(cds_out_WriteAll); + + } + if ((pcommand->digit_data.byte05.bit_data.bit6 != flag_prev_turn_on) && !f.Stop && +// ((filter.iqU_1_long > 11184810) || (filter.iqU_3_long > 11184810))) //turn_on + ((filter.iqU_1_long > 5590240) || (filter.iqU_3_long > 5590240))) + { + if(pcommand->digit_data.byte05.bit_data.bit6 == 1) + { + project.cds_out[0].fpga.Write.Dout.bit.dout7 = 0; + cds_out_all(cds_out_WriteAll); + pause_1000(100000); + pause_1000(100000); + pause_1000(100000); + pause_1000(100000); + pause_1000(100000); + project.cds_out[0].fpga.Write.Dout.bit.dout7 = 1; + cds_out_all(cds_out_WriteAll); + //f.Ready2 = 1; + f.On_Power_QTV = 1; + } + + flag_prev_turn_on = pcommand->digit_data.byte05.bit_data.bit6; + cds_out_all(cds_out_WriteAll); + + } + if(project.cds_in[1].fpga.input_new.ChanalsPtr.ChanalPtr[7].rd_status != flag_prev_lamp_on_off) //turnig on lamp when power is on + { + if(project.cds_in[1].fpga.input_new.ChanalsPtr.ChanalPtr[7].rd_status == 1) + { + project.cds_out[1].fpga.Write.Dout.bit.dout1 = 0; + cds_out_all(cds_out_WriteAll); + } + else + { + project.cds_out[1].fpga.Write.Dout.bit.dout1 = 1; + cds_out_all(cds_out_WriteAll); + } + flag_prev_lamp_on_off = project.cds_in[1].fpga.input_new.ChanalsPtr.ChanalPtr[7].rd_status; + } + + +*/ + +// run_break = pcommand->digit_data.byte05.bit_data.bit4; + + + if (pcommand->digit_data.byte05.bit_data.bit4 == 1) + { + adc_plate = 1; + + } + else + adc_plate = 0; + + if (pcommand->digit_data.byte05.bit_data.bit6 == 1) + i_sync_pin_on(); + else + i_sync_pin_off(); + + + + Data = project.adc[adc_plate].read.pbus.adc_value[0];//InternalADC[0];//0;//ADC_sf[0];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog1_lo=LOBYTE(Data); + reply_test_all.analog_data.analog1_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[1];// InternalADC[1];//0;//ADC_sf[1];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog2_lo=LOBYTE(Data); + reply_test_all.analog_data.analog2_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[2];// InternalADC[2];//0;//ADC_sf[2];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog3_lo=LOBYTE(Data); + reply_test_all.analog_data.analog3_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[3];// InternalADC[3];//0;//ADC_sf[3];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog4_lo=LOBYTE(Data); + reply_test_all.analog_data.analog4_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[4];// InternalADC[4];//0;//ADC_sf[4];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog5_lo=LOBYTE(Data); + reply_test_all.analog_data.analog5_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[5];// InternalADC[5];//0;//ADC_sf[5];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog6_lo=LOBYTE(Data); + reply_test_all.analog_data.analog6_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[6];// InternalADC[6];//0;//ADC_sf[6];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog7_lo=LOBYTE(Data); + reply_test_all.analog_data.analog7_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[7];//InternalADC[7];//0;//ADC_sf[7];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog8_lo=LOBYTE(Data); + reply_test_all.analog_data.analog8_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[8];//InternalADC[8];//0;//ADC_sf[8];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog9_lo=LOBYTE(Data); + reply_test_all.analog_data.analog9_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[9];//InternalADC[9];//0;//ADC_sf[9];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog10_lo=LOBYTE(Data); + reply_test_all.analog_data.analog10_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[10];//InternalADC[10];//0;//ADC_sf[10];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog11_lo=LOBYTE(Data); + reply_test_all.analog_data.analog11_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[11];//InternalADC[11];//0;//ADC_sf[11];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog12_lo=LOBYTE(Data); + reply_test_all.analog_data.analog12_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[12];//InternalADC[12];//0;//ADC_sf[12];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog13_lo=LOBYTE(Data); + reply_test_all.analog_data.analog13_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[13];//InternalADC[13];//0;//ADC_sf[13];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog14_lo=LOBYTE(Data); + reply_test_all.analog_data.analog14_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[14];//InternalADC[14];//0;//ADC_sf[14];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog15_lo=LOBYTE(Data); + reply_test_all.analog_data.analog15_hi=HIBYTE(Data); + + Data = project.adc[adc_plate].read.pbus.adc_value[15];//InternalADC[15];//0;//ADC_sf[15];//_IQtoF(analog.iqIa1_1_fir_n)*2000.0;// + reply_test_all.analog_data.analog16_lo=LOBYTE(Data); + reply_test_all.analog_data.analog16_hi=HIBYTE(Data); + + + Data = _IQtoF(analog.iqU_1) * NORMA_ACP; + reply_ans->analog_data.analog17_lo=LOBYTE(Data); + reply_ans->analog_data.analog17_hi=HIBYTE(Data); + + Data = _IQtoF(analog.iqU_2) * NORMA_ACP; + reply_ans->analog_data.analog18_lo=LOBYTE(Data); + reply_ans->analog_data.analog18_hi=HIBYTE(Data); + + Data = project.cds_tk[0].read.sbus.time_err_tk_all.bit.tk_3210; + reply_ans->analog_data.analog19_lo=LOBYTE(Data); + reply_ans->analog_data.analog19_hi=HIBYTE(Data); + + Data = project.cds_tk[0].read.sbus.time_err_tk_all.bit.tk_7654; + reply_ans->analog_data.analog20_lo=LOBYTE(Data); + reply_ans->analog_data.analog20_hi=HIBYTE(Data); + + Data = project.cds_tk[1].read.sbus.time_err_tk_all.bit.tk_3210; + reply_ans->analog_data.analog21_lo=LOBYTE(Data); + reply_ans->analog_data.analog21_hi=HIBYTE(Data); + + Data = project.cds_tk[1].read.sbus.time_err_tk_all.bit.tk_7654; + reply_ans->analog_data.analog22_lo=LOBYTE(Data); + reply_ans->analog_data.analog22_hi=HIBYTE(Data); + + Data = project.cds_tk[2].read.sbus.time_err_tk_all.bit.tk_3210; + reply_ans->analog_data.analog23_lo=LOBYTE(Data); + reply_ans->analog_data.analog23_hi=HIBYTE(Data); + + Data = project.cds_tk[2].read.sbus.time_err_tk_all.bit.tk_7654; + reply_ans->analog_data.analog24_lo=LOBYTE(Data); + reply_ans->analog_data.analog24_hi=HIBYTE(Data); + +// Data = project.cds_tk[3].read.sbus.time_err_tk_all.bit.tk_3210; +// reply_ans->analog_data.analog25_lo=LOBYTE(Data); +// reply_ans->analog_data.analog25_hi=HIBYTE(Data); +// +// Data = project.cds_tk[3].read.sbus.time_err_tk_all.bit.tk_7654; +// reply_ans->analog_data.analog26_lo=LOBYTE(Data); +// reply_ans->analog_data.analog26_hi=HIBYTE(Data); + +reply_ans->digit_data.byte01.byte_data = 0; +reply_ans->digit_data.byte02.byte_data = 0; +reply_ans->digit_data.byte03.byte_data = 0; +reply_ans->digit_data.byte04.byte_data = 0; +reply_ans->digit_data.byte05.byte_data = 0; +reply_ans->digit_data.byte06.byte_data = 0; +reply_ans->digit_data.byte07.byte_data = 0; +reply_ans->digit_data.byte08.byte_data = 0; +reply_ans->digit_data.byte09.byte_data = 0; +reply_ans->digit_data.byte10.byte_data = 0; +reply_ans->digit_data.byte11.byte_data = 0; +reply_ans->digit_data.byte12.byte_data = 0; +reply_ans->digit_data.byte13.byte_data = 0; +reply_ans->digit_data.byte14.byte_data = 0; +reply_ans->digit_data.byte15.byte_data = 0; +reply_ans->digit_data.byte16.byte_data = 0; +reply_ans->digit_data.byte17.byte_data = 0; +reply_ans->digit_data.byte18.byte_data = 0; +reply_ans->digit_data.byte19.byte_data = 0; +reply_ans->digit_data.byte20.byte_data = 0; +reply_ans->digit_data.byte21.byte_data = 0; +reply_ans->digit_data.byte22.byte_data = 0; +reply_ans->digit_data.byte23.byte_data = 0; +reply_ans->digit_data.byte24.byte_data = 0; + + + reply_ans->digit_data.byte01.bit_data.bit0 = project.cds_tk[0].read.sbus.current_status_error.bit.err0_local; + reply_ans->digit_data.byte01.bit_data.bit1 = project.cds_tk[1].read.sbus.current_status_error.bit.err0_local; + reply_ans->digit_data.byte01.bit_data.bit2 = project.cds_tk[2].read.sbus.current_status_error.bit.err0_local; + reply_ans->digit_data.byte01.bit_data.bit3 = project.cds_tk[3].read.sbus.current_status_error.bit.err0_local; + + reply_ans->digit_data.byte01.bit_data.bit4 = project.cds_tk[0].read.sbus.current_status_error.bit.err_power; + reply_ans->digit_data.byte01.bit_data.bit5 = project.cds_tk[1].read.sbus.current_status_error.bit.err_power; + reply_ans->digit_data.byte01.bit_data.bit6 = project.cds_tk[2].read.sbus.current_status_error.bit.err_power; + reply_ans->digit_data.byte01.bit_data.bit7 = project.cds_tk[3].read.sbus.current_status_error.bit.err_power; + + reply_ans->digit_data.byte02.bit_data.bit0 = project.cds_in[0].read.sbus.current_status_error.bit.err_power; + reply_ans->digit_data.byte02.bit_data.bit1 = project.cds_in[1].read.sbus.current_status_error.bit.err_power; +#if(C_cds_in_number>=3) + reply_ans->digit_data.byte02.bit_data.bit2 = project.cds_in[2].read.sbus.current_status_error.bit.err_power; +#endif + reply_ans->digit_data.byte02.bit_data.bit3 = project.cds_out[0].read.sbus.current_status_error.bit.err_power; + + reply_ans->digit_data.byte02.bit_data.bit4 = project.cds_out[1].read.sbus.current_status_error.bit.err_power; + reply_ans->digit_data.byte02.bit_data.bit5 = 0; + reply_ans->digit_data.byte02.bit_data.bit6 = project.cds_tk[0].read.sbus.current_status_error.bit.err_switch; + reply_ans->digit_data.byte02.bit_data.bit7 = project.cds_tk[1].read.sbus.current_status_error.bit.err_switch; + + reply_ans->digit_data.byte03.bit_data.bit0 = project.cds_tk[2].read.sbus.current_status_error.bit.err_switch; + reply_ans->digit_data.byte03.bit_data.bit1 = project.cds_tk[3].read.sbus.current_status_error.bit.err_switch; + reply_ans->digit_data.byte03.bit_data.bit2 = project.cds_in[0].read.sbus.current_status_error.bit.err_switch; + reply_ans->digit_data.byte03.bit_data.bit3 = project.cds_in[1].read.sbus.current_status_error.bit.err_switch; + + +#if(C_cds_in_number>=3) + reply_ans->digit_data.byte03.bit_data.bit4 = project.cds_in[2].read.sbus.current_status_error.bit.err_switch; +#endif + reply_ans->digit_data.byte03.bit_data.bit5 = project.cds_out[0].read.sbus.current_status_error.bit.err_switch; + reply_ans->digit_data.byte03.bit_data.bit6 = project.cds_out[1].read.sbus.current_status_error.bit.err_switch; + reply_ans->digit_data.byte03.bit_data.bit7 = 0; + + //TK0 acknolege-current + reply_ans->digit_data.byte04.byte_data = project.cds_tk[0].read.sbus.status_protect_current_ack.all & 0xFF; + reply_ans->digit_data.byte05.byte_data = (project.cds_tk[0].read.sbus.status_protect_current_ack.all >> 8) & 0xFF; + + //TK1 acknolege-current + reply_ans->digit_data.byte06.byte_data = project.cds_tk[1].read.sbus.status_protect_current_ack.all & 0xFF; + reply_ans->digit_data.byte07.byte_data = (project.cds_tk[1].read.sbus.status_protect_current_ack.all >> 8) & 0xFF; + + //TK2 acknolege-current + reply_ans->digit_data.byte08.byte_data = project.cds_tk[2].read.sbus.status_protect_current_ack.all & 0xFF; + reply_ans->digit_data.byte09.byte_data = (project.cds_tk[2].read.sbus.status_protect_current_ack.all >> 8) & 0xFF; + + //TK3 acknolege-current + reply_ans->digit_data.byte10.byte_data = project.cds_tk[3].read.sbus.status_protect_current_ack.all & 0xFF; + reply_ans->digit_data.byte11.byte_data = (project.cds_tk[3].read.sbus.status_protect_current_ack.all >> 8) & 0xFF; + + +//IN1 + reply_ans->digit_data.byte13.byte_data = project.cds_in[0].read.pbus.data_in.all & 0xFF; + reply_ans->digit_data.byte14.byte_data = (project.cds_in[0].read.pbus.data_in.all >> 8) & 0xFF; + +//IN2 + reply_ans->digit_data.byte15.byte_data = project.cds_in[1].read.pbus.data_in.all & 0xFF; + reply_ans->digit_data.byte16.byte_data = (project.cds_in[1].read.pbus.data_in.all >> 8) & 0xFF; + +//IN3 +#if(C_cds_in_number>=3) + reply_ans->digit_data.byte17.byte_data = project.cds_in[2].read.pbus.data_in.all & 0xFF; + reply_ans->digit_data.byte18.byte_data = (project.cds_in[2].read.pbus.data_in.all >> 8) & 0xFF; +#endif + + reply_ans->digit_data.byte19.bit_data.bit0 = get_status_sync_line();//CAN_timeout[UKSS1_CAN_DEVICE]; + //reply.digit_data.byte21.bit_data.bit1 = CAN_timeout[UKSS4_CAN_DEVICE]; + reply_ans->digit_data.byte19.bit_data.bit2 = 0;// CAN_timeout[UKSS2_CAN_DEVICE]; + reply_ans->digit_data.byte19.bit_data.bit3 = 0;// CAN_timeout[UKSS3_CAN_DEVICE]; + reply_ans->digit_data.byte19.bit_data.bit4 = CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,ZADATCHIK_CAN)]; + //reply_test_all.digit_data.byte19.bit_data.bit5 = CAN_timeout[VPU2_CAN_DEVICE]; + reply_ans->digit_data.byte19.bit_data.bit6 = CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,UMU_CAN_DEVICE)]; + //reply.digit_data.byte21.bit_data.bit7 = CAN_timeout[VPU1_CAN_DEVICE]; + + reply_ans->digit_data.byte20.bit_data.bit0 = project.controller.read.errors.bit.er0_out; + reply_ans->digit_data.byte20.bit_data.bit1 = project.controller.read.errors.bit.er0_trig; + reply_ans->digit_data.byte20.bit_data.bit2 = project.controller.read.errors.bit.errHWP; + reply_ans->digit_data.byte20.bit_data.bit3 = project.controller.read.errors.bit.errHWP_trig; + reply_ans->digit_data.byte20.bit_data.bit4 = project.controller.read.errors.bit.error_pbus; + reply_ans->digit_data.byte20.bit_data.bit5 = project.controller.read.errors.bit.pwm_wdog; + reply_ans->digit_data.byte20.bit_data.bit6 = project.controller.read.errors.bit.status_er0; +// reply_ans->digit_data.byte20.bit_data.bit0 = project.controller.read.errors.bit.er0_out; +// reply_ans->digit_data.byte20.bit_data.bit0 = CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,VPU_CAN)]; +// reply_ans->digit_data.byte20.bit_data.bit1 = CAN_timeout[get_real_in_mbox(MPU_TYPE_BOX,0)]; + reply_ans->digit_data.byte20.bit_data.bit2 = 0;//READY_UKSS_6; + reply_ans->digit_data.byte20.bit_data.bit3 = 0;//READY_UKSS_7; + reply_ans->digit_data.byte20.bit_data.bit4 = 0;//READY_UKSS_8; + //reply_test_all.digit_data.byte20.bit_data.bit5 = READY_UKSS_1; + //reply_test_all.digit_data.byte20.bit_data.bit6 = READY_UKSS_2; + //reply_test_all.digit_data.byte20.bit_data.bit7 = READY_UKSS_3; + + + + reply_ans->digit_data.byte21.bit_data.bit0 = !project.hwp[0].status;//XProject_balzam.IsReady_reg.bit.XPlaneHWP_Chanals_IsReady; + reply_ans->digit_data.byte21.bit_data.bit2 = !project.adc[0].status;//XProject_balzam.IsReady_reg.bit.XPlaneHWP_Chanals_IsReady; +#if(C_cds_in_number>=1) + reply_ans->digit_data.byte21.bit_data.bit3 = !project.cds_in[0].status;//XProject_balzam.IsReady_reg.bit.XPlaneIN0_IsReady; +#endif +#if(C_cds_in_number>=2) + reply_ans->digit_data.byte21.bit_data.bit4 = !project.cds_in[1].status;//XProject_balzam.IsReady_reg.bit.XPlaneIN1_IsReady; +#endif +#if(C_cds_in_number>=3) + reply_ans->digit_data.byte21.bit_data.bit5 = !project.cds_in[2].status;//XProject_balzam.IsReady_reg.bit.XPlaneIN2_IsReady; +#endif + +#if(C_cds_out_number>=1) + reply_ans->digit_data.byte21.bit_data.bit6 = !project.cds_out[0].status;//XProject_balzam.IsReady_reg.bit.XPlaneOUT0_IsReady; +#endif +#if(C_cds_out_number>=2) + reply_ans->digit_data.byte21.bit_data.bit7 = !project.cds_out[1].status;//XProject_balzam.IsReady_reg.bit.XPlaneOUT1_IsReady; +#endif +#if(C_cds_out_number>=3) + reply_ans->digit_data.byte22.bit_data.bit0 = !project.cds_out[2].status;//XProject_balzam.IsReady_reg.bit.XPlaneOUT2_IsReady; +#endif + + + reply_ans->digit_data.byte22.bit_data.bit1 = !project.cds_tk[0].status;//XProject_balzam.IsReady_reg.bit.XPlaneTK0_IsReady; + reply_ans->digit_data.byte22.bit_data.bit2 = !project.cds_tk[1].status;//XProject_balzam.IsReady_reg.bit.XPlaneTK1_IsReady; + reply_ans->digit_data.byte22.bit_data.bit3 = !project.cds_tk[2].status;//XProject_balzam.IsReady_reg.bit.XPlaneTK2_IsReady; + reply_ans->digit_data.byte22.bit_data.bit4 = !project.cds_tk[3].status;//!XProject_balzam.IsReady_reg.bit.XPlaneTK3_IsReady; + reply_ans->digit_data.byte22.bit_data.bit5 = !project.adc[1].status;//XProject_balzam.IsReady_reg.bit.XPlaneHWP_Chanals_IsReady; + + reply_ans->digit_data.byte23.byte_data=project.hwp[0].read.comp_s.minus.all & 0x00ff; + reply_ans->digit_data.byte24.byte_data=((project.hwp[0].read.comp_s.minus.all >> 8) & 0x00ff); + + reply_ans->digit_data.byte23.byte_data|=project.hwp[0].read.comp_s.plus.all & 0x00ff; + reply_ans->digit_data.byte24.byte_data|=((project.hwp[0].read.comp_s.plus.all >> 8) & 0x00ff); + +#if (USE_TK_0) + if (project.cds_tk[0].useit) + { +// reply_ans->digit_data.byte22.bit_data.bit0 = project.cds_tk[0].read.sbus.lock_status_error.bit.err0_in; + reply_ans->digit_data.byte25.bit_data.bit0 = project.cds_tk[0].read.sbus.lock_status_error.bit.err_hwp; + reply_ans->digit_data.byte25.bit_data.bit1 = project.cds_tk[0].read.sbus.lock_status_error.bit.err0_local; + reply_ans->digit_data.byte25.bit_data.bit2 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + reply_ans->digit_data.byte25.bit_data.bit3 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + reply_ans->digit_data.byte25.bit_data.bit4 = project.cds_tk[0].read.sbus.lock_status_error.bit.line_err_keys_7654; + reply_ans->digit_data.byte25.bit_data.bit5 = project.cds_tk[0].read.sbus.lock_status_error.bit.line_err_keys_3210; + reply_ans->digit_data.byte25.bit_data.bit6 = project.cds_tk[0].read.sbus.lock_status_error.bit.ErrorSoftShutdownFromErr0; + reply_ans->digit_data.byte25.bit_data.bit7 = project.cds_tk[0].read.sbus.lock_status_error.bit.ErrorSoftShutdownForbidComb; + } + else + reply_ans->digit_data.byte25.byte_data = 0; + +#else + reply_ans->digit_data.byte25.byte_data = 0; +#endif + +#if (USE_TK_1) + if (project.cds_tk[1].useit) + { + reply_ans->digit_data.byte26.bit_data.bit0 = project.cds_tk[1].read.sbus.lock_status_error.bit.err_hwp; + reply_ans->digit_data.byte26.bit_data.bit1 = project.cds_tk[1].read.sbus.lock_status_error.bit.err0_local; + reply_ans->digit_data.byte26.bit_data.bit2 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + reply_ans->digit_data.byte26.bit_data.bit3 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + reply_ans->digit_data.byte26.bit_data.bit4 = project.cds_tk[1].read.sbus.lock_status_error.bit.line_err_keys_7654; + reply_ans->digit_data.byte26.bit_data.bit5 = project.cds_tk[1].read.sbus.lock_status_error.bit.line_err_keys_3210; + reply_ans->digit_data.byte26.bit_data.bit6 = project.cds_tk[1].read.sbus.lock_status_error.bit.ErrorSoftShutdownFromErr0; + reply_ans->digit_data.byte26.bit_data.bit7 = project.cds_tk[1].read.sbus.lock_status_error.bit.ErrorSoftShutdownForbidComb; + } + else + reply_ans->digit_data.byte26.byte_data = 0; +#else + reply_ans->digit_data.byte26.byte_data = 0; +#endif + +#if (USE_TK_2) + if (project.cds_tk[2].useit) + { + reply_ans->digit_data.byte27.bit_data.bit0 = project.cds_tk[2].read.sbus.lock_status_error.bit.err_hwp; + reply_ans->digit_data.byte27.bit_data.bit1 = project.cds_tk[2].read.sbus.lock_status_error.bit.err0_local; + reply_ans->digit_data.byte27.bit_data.bit2 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + reply_ans->digit_data.byte27.bit_data.bit3 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + reply_ans->digit_data.byte27.bit_data.bit4 = project.cds_tk[2].read.sbus.lock_status_error.bit.line_err_keys_7654; + reply_ans->digit_data.byte27.bit_data.bit5 = project.cds_tk[2].read.sbus.lock_status_error.bit.line_err_keys_3210; + reply_ans->digit_data.byte27.bit_data.bit6 = project.cds_tk[2].read.sbus.lock_status_error.bit.ErrorSoftShutdownFromErr0; + reply_ans->digit_data.byte27.bit_data.bit7 = project.cds_tk[2].read.sbus.lock_status_error.bit.ErrorSoftShutdownForbidComb; + } + else + reply_ans->digit_data.byte27.byte_data = 0; +#else + reply_ans->digit_data.byte27.byte_data = 0; +#endif + +#if (USE_TK_3) + if (project.cds_tk[3].useit) + { + reply_ans->digit_data.byte28.bit_data.bit0 = project.cds_tk[3].read.sbus.lock_status_error.bit.err_hwp; + reply_ans->digit_data.byte28.bit_data.bit1 = project.cds_tk[3].read.sbus.lock_status_error.bit.err0_local; + reply_ans->digit_data.byte28.bit_data.bit2 = project.cds_tk[3].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + reply_ans->digit_data.byte28.bit_data.bit3 = project.cds_tk[3].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + reply_ans->digit_data.byte28.bit_data.bit4 = project.cds_tk[3].read.sbus.lock_status_error.bit.line_err_keys_7654; + reply_ans->digit_data.byte28.bit_data.bit5 = project.cds_tk[3].read.sbus.lock_status_error.bit.line_err_keys_3210; + reply_ans->digit_data.byte28.bit_data.bit6 = project.cds_tk[3].read.sbus.lock_status_error.bit.ErrorSoftShutdownFromErr0; + reply_ans->digit_data.byte28.bit_data.bit7 = project.cds_tk[3].read.sbus.lock_status_error.bit.ErrorSoftShutdownForbidComb; + } + else + reply_ans->digit_data.byte28.byte_data = 0; +#else + reply_ans->digit_data.byte28.byte_data = 0; +#endif + + +/* + +//IN1 ready + reply_ans->digit_data.byte21.byte_data = project.cds_in[0].read.pbus.ready_in.all & 0xFF; + reply_ans->digit_data.byte22.byte_data = (project.cds_in[0].read.pbus.ready_in.all >> 8) & 0xFF; + +//TK0 acknolege-current + reply_ans->digit_data.byte23.byte_data = project.cds_tk[0].read.sbus.status_protect_current_ack.all & 0xFF; + reply_ans->digit_data.byte24.byte_data = (project.cds_tk[0].read.sbus.status_protect_current_ack.all >> 8) & 0xFF; +*/ + return; +} + + + + + + + + + + + + + + + + + + + + + diff --git a/Inu/Src2/551/main/message2test.h b/Inu/Src2/551/main/message2test.h new file mode 100644 index 0000000..3f1406c --- /dev/null +++ b/Inu/Src2/551/main/message2test.h @@ -0,0 +1,33 @@ +//////////////////////////////////////////// +// message.h +// +// : +// 1. y +// 2. +// 3. y +// +// +// y y y +// . INTEL 386SX Octagon +// TMS320C32 Texas Instruments. +// +// . +// y +// unsigned char = 8 +// TMS320C32 unsigned char = 32 , y +// 8 . +// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +// +// y +// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//////////////////////////////////////////// + +#ifndef MESSAGE_TEST_H +#define MESSAGE_TEST_H + +#include "RS_Function_terminal.h" + +void func_fill_answer_to_TMS_test(TMS_TO_TERMINAL_TEST_ALL_STRUCT* reply_ans, CMD_TO_TMS_TEST_ALL_STRUCT* pcommand); + + +#endif //MESSAGE_H diff --git a/Inu/Src2/551/main/message_modbus.c b/Inu/Src2/551/main/message_modbus.c new file mode 100644 index 0000000..024db30 --- /dev/null +++ b/Inu/Src2/551/main/message_modbus.c @@ -0,0 +1,897 @@ +#include +#include +#include +#include +#include +#include +#include +#include "CAN_Setup.h" +#include "global_time.h" +#include "modbus_table_v2.h" +#include "oscil_can.h" +#include "RS_modbus_pult.h" +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "CRC_Functions.h" +#include "RS_Function_terminal.h" +#include "RS_modbus_svu.h" +#include "TuneUpPlane.h" +#if (USE_CONTROL_STATION==1) +#include "control_station.h" +#endif +#include +#include + +#include "pwm_test_lines.h" +#include "params.h" +#include "logs_hmi.h" + + +//#include "can_setup_21300.h" +//#include "modbus_can.h" + +//static int err_modbus3=1; +//static int err_modbus16=1; +//static int cmd_3_or_16=0; + +int enable_can = 0; + +void write_all_data_to_mpu_485(int run_force) +{ + static unsigned int time_tick_modbus = 0; + static unsigned int old_PWM_ticks = 0; + static int count_write_to_modbus = 0; + static int cur_position_buf_modbus16 = 0; + + if (global_time.pwm_tics != old_PWM_ticks) + { + if (global_time.pwm_tics > old_PWM_ticks) + time_tick_modbus = time_tick_modbus + (global_time.pwm_tics - old_PWM_ticks); + else + time_tick_modbus++; + } + + if (time_tick_modbus > TIME_PAUSE_MODBUS_MPU) + { + // pause_1000() + + time_tick_modbus = 0; + pause_1000(10); + // SendCommandModbus3(&rs_b, 0x1, 0xc012,1); + // rs_b.flag_LEADING = 0; + if (!rs_b.flag_LEADING) + { + time_tick_modbus = 0; + //Fast answer to SVU when command changed + // if (flag_send_answer_rs) { + // flag_send_answer_rs = 0; + // err_modbus16++; + // SendCommandModbus16(&rs_b,1,210,SIZE_BUF_WRITE_TO_MODBUS16); + // return; + // } + if (err_modbus16 == 0) + cur_position_buf_modbus16 = cur_position_buf_modbus16 + SIZE_BUF_WRITE_TO_MODBUS16_VPU; + + if (cur_position_buf_modbus16 >= SIZE_MODBUS_TABLE) + cur_position_buf_modbus16 = 0; + + if ((cur_position_buf_modbus16 + SIZE_BUF_WRITE_TO_MODBUS16_VPU) > SIZE_MODBUS_TABLE) + count_write_to_modbus = SIZE_MODBUS_TABLE - cur_position_buf_modbus16; + else + count_write_to_modbus = SIZE_BUF_WRITE_TO_MODBUS16_VPU; + + // count_write_to_modbus = SIZE_BUF_WRITE_TO_MODBUS16_VPU; + // cur_position_buf_modbus=0; + + err_modbus16++; + + if (err_modbus16 > MAX_COUNT_ERROR_FROM_RS_MPU) + f.RS_MPU_ERROR = 1; + + ModbusRTUsend16(&rs_b, 1, + ADR_MODBUS_TABLE + cur_position_buf_modbus16, + count_write_to_modbus); + // SendCommandModbus16(&rs_b,1,ADR_MODBUS_TABLE+cur_position_buf_modbus16,count_write_to_modbus); + // SendCommandModbus16(&rs_b,1,1,30); + + // + // SendCommandModbus16(&rs_b,1,0xc001,0x64); + // err_modbus + } + } +} + +void read_all_data_from_mpu_485(int run_force) +{ + static unsigned int time_tick_modbus = 0; + static unsigned int old_PWM_ticks = 0; + static unsigned int count_write_to_modbus = 0; + static int cur_position_buf_modbus3 = 0; + + if (global_time.pwm_tics != old_PWM_ticks) + { + if (global_time.pwm_tics > old_PWM_ticks) + time_tick_modbus = time_tick_modbus + (global_time.pwm_tics - old_PWM_ticks); + else + time_tick_modbus++; + } + + old_PWM_ticks = global_time.pwm_tics; + + if (TIME_PAUSE_MODBUS_MPU < time_tick_modbus) + { + // pause_1000() + + pause_1000(10); + // SendCommandModbus3(&rs_b, 0x1, 0xc012,1); + //rs_b.flag_LEADING = 0; + if (!rs_b.flag_LEADING) + { + time_tick_modbus = 0; + + if (err_modbus3 == 0) + cur_position_buf_modbus3 = cur_position_buf_modbus3 + SIZE_BUF_WRITE_TO_MODBUS16_VPU; + + if (cur_position_buf_modbus3 >= SIZE_MODBUS_TABLE) + cur_position_buf_modbus3 = 0; + + if ((cur_position_buf_modbus3 + SIZE_BUF_WRITE_TO_MODBUS16_VPU) > SIZE_MODBUS_TABLE) + count_write_to_modbus = SIZE_MODBUS_TABLE - cur_position_buf_modbus3; + else + count_write_to_modbus = SIZE_BUF_WRITE_TO_MODBUS16_VPU; + + // count_write_to_modbus = SIZE_BUF_WRITE_TO_MODBUS16_VPU; + // cur_position_buf_modbus=0; + + err_modbus3++; + + if (err_modbus3 > MAX_COUNT_ERROR_FROM_RS_MPU) + f.RS_MPU_ERROR = 1; + + // SendCommandModbus3(&rs_b,1,ADR_MODBUS_TABLE+cur_position_buf_modbus3,count_write_to_modbus); + ModbusRTUsend3(&rs_b, 1, + ADR_MODBUS_TABLE + cur_position_buf_modbus3, + count_write_to_modbus); + } + } + + // time_tick_modbus++; +} + +void write_all_data_to_mpu_can(int run_force, unsigned int pause) +{ +// static int time_tick_modbus_can = 0; + static unsigned int old_time = 0; + static int count_write_to_modbus_can = 0; +// static int time_send_to_can = 0; + // static unsigned int counter_max_I = 0, counter_max_M = 0; + + static int cur_position_buf_modbus16_can = 0, prev_send_to_can = 0; + int real_mbox; + unsigned int i; + + real_mbox = get_real_out_mbox(MPU_TYPE_BOX, edrk.flag_second_PCH); + + if (prev_send_to_can && CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_OFF)==0) + { + old_time = (unsigned int)global_time.miliseconds; + return; + } + prev_send_to_can = 0; + + if (!detect_pause_milisec(pause,&old_time)) + return; + + +// +// +// if (cmd_3_or_16 == 1 || run_force) +// { +// +// if (global_time.pwm_tics != old_PWM_ticks) +// { +// if (global_time.pwm_tics > old_PWM_ticks) +// time_tick_modbus_can = time_tick_modbus_can + (global_time.pwm_tics - old_PWM_ticks); +// else +// time_tick_modbus_can++; +// } +// +// old_PWM_ticks = global_time.pwm_tics; +// } +// else +// { +// old_PWM_ticks = global_time.pwm_tics; +// return; +// } +// +// +// +// if (CAN_cycle_free(real_mbox)) +// { +// if (time_send_to_can == 0) +// time_send_to_can = time_tick_modbus_can; +// +// // time_tick_modbus_can=0; +// +// } + // if(f.Prepare && CAN_cycle_free(real_mbox)) + // { + // CAN_cycle_send( MPU_TYPE_BOX, 0, 198, &modbus_table_can_out[197].all, 1); + // } + + +// if (time_tick_modbus_can > TIME_PAUSE_MODBUS_CAN) +// { +// time_tick_modbus_can = 0; +// time_send_to_can = 0; +// // pause_1000(300); + + + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_ON)) + { + ///////////////////////////////////////////////////////////////////////////////////////////// + + //////////////////////////////////////////////////////////////////////////////////////////// + + + if (cur_position_buf_modbus16_can >= SIZE_MODBUS_TABLE) + { + cur_position_buf_modbus16_can = 0; + // modbus_table_can_out[ADR_CAN_TEST_PLUS_ONE].all++; + } + + // + if (cur_position_buf_modbus16_can == 0) + { + for (i=0;i= SIZE_MODBUS_TABLE) + count_write_to_modbus_can = SIZE_MODBUS_TABLE - cur_position_buf_modbus16_can; + else + count_write_to_modbus_can = SIZE_BUF_WRITE_TO_MODBUS16_CAN; + + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_ON)) + { + // modbus_table_can_out[0x124].all++; + // CAN_cycle_send(MPU_CAN_DEVICE, cur_position_buf_modbus16_can+1, &modbus_table_can_out[cur_position_buf_modbus16_can].all, count_write_to_modbus_can); + + CAN_cycle_send( + MPU_TYPE_BOX, + edrk.flag_second_PCH, + cur_position_buf_modbus16_can + 1, +// &modbus_table_can_out[cur_position_buf_modbus16_can].all, + &modbus_table_can_out_temp[cur_position_buf_modbus16_can].all, + count_write_to_modbus_can, CAN_BOX_STANDART_ADR, CAN_BOX_PRIORITY_NORMAL); + + cur_position_buf_modbus16_can = cur_position_buf_modbus16_can + SIZE_BUF_WRITE_TO_MODBUS16_CAN; + } + } + +// } + +} + +//void test_rs_can_with_svu_mpu() +//{ +// int test_a, test_b; +// +// test_a = test_rs_live(&rs_a); +// test_b = test_rs_live(&rs_b); +// +// if (test_a == 0 && test_b == 0 && f.status_MODE_WORK_SVU == 0) +// { +// /* RS232 */ +// if (test_can_live_mpu() == 0) +// { +// // if (f.cmd_to_go == 0) f.cmd_to_go = ERROR_CMD_GO_1; +// edrk.Go = 0; /* */ +// } +// } +// +// if (test_a == 0 && test_b == 0 && f.status_MODE_WORK_MPU == 0 /*&& f.status_SPEED_SELECT_KEY==0*/) +// { +// /* RS232 */ +// if (test_can_live_mpu() == 0) +// { +// // if (f.cmd_to_go == 0) f.cmd_to_go = ERROR_CMD_GO_2; +// edrk.Go = 0; /* */ +// } +// } +// +// if (test_a == 2) +// { +// /* RS232 */ +// // edrk.Go=0; /* */ +// resetup_rs(&rs_a); +// } +// +// if (test_b == 2) +// { +// /* RS232 */ +// resetup_rs(&rs_b); +//// flag_waiting_answer = 0; //, , +// // slave , . +// } +// +// if (test_b == 5) +// { +// /* RS232 */ +// resetup_rs(&rs_b); +//// flag_waiting_answer = 0; //, , +// // slave , . +// } +// +// if (test_a == 4 && test_b == 4) //TODO: && SPEED_SELECT_REMOTE==1) +// { +// // RS232 +// if (test_can_live_mpu() == 0) +// { +// // if (f.cmd_to_go == 0) f.cmd_to_go = ERROR_CMD_GO_3; +// edrk.Go = 0; // +// } +// resetup_mpu_rs(&rs_a); +// resetup_mpu_rs(&rs_b); +//// flag_waiting_answer = 0; +// } +// +// if (test_a == 4 && test_b == 4) //TOD: && SPEED_SELECT_REMOTE==0) +// { +// // RS232 +// // if (test_can_live_mpu()==0) +// +// // test_can_live_terminal // +// +// { +// // if (f.cmd_to_go == 0) f.cmd_to_go = ERROR_CMD_GO_20; +// edrk.Go = 0; // +// } +// resetup_mpu_rs(&rs_a); +// resetup_mpu_rs(&rs_b); +// } +// +// if (test_a == 0 && f.status_MODE_WORK_MPU == 0) // && SPEED_SELECT_REMOTE==0) +// { +// /* RS232 */ +// // if (test_can_live_mpu()==0) +// // if (f.cmd_to_go == 0) f.cmd_to_go = ERROR_CMD_GO_4; +// edrk.Go = 0; /* */ +// } +// +// // if (CAN_timeout[]==1) +// // f.CAN_MPU_ERROR=CAN_timeout[MPU_CAN_DEVICE]; +//} + + + +#define TIME_REINIT_PULT_INGETEAM 5 + + +void test_alive_pult_485(void) +{ + static unsigned int time_pause = 0, old_time = 0; + +// +// if (control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485]>control_station.setup_time_detect_active_resend_485[CONTROL_STATION_INGETEAM_PULT_RS485]) +// { +// resetup_mpu_rs(&rs_b); +// control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; +// control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; +// control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; +// } +/* + if (control_station.time_detect_active[CONTROL_STATION_INGETEAM_PULT_RS485]>control_station.setup_time_detect_active_resend_485[CONTROL_STATION_INGETEAM_PULT_RS485]) + { + resetup_mpu_rs(&rs_b); + control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; + // control_station.time_detect_active[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; + } +*/ + +// if (control_station.time_detect_active[CONTROL_STATION_INGETEAM_PULT_RS485]>control_station.setup_time_detect_active[CONTROL_STATION_INGETEAM_PULT_RS485]) +// { +// resetup_mpu_rs(&rs_b); +// control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; +// control_station.time_detect_active[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; +// } + + +/* + if (!detect_pause_milisec(CONTROL_STATION_TIME_WAIT,&old_time)) + return; + + time_pause++; + + if (time_pause>=TIME_REINIT_PULT_INGETEAM) + { + flag_waiting_answer = 0; //, + } +*/ + +} + + +#define MAX_COUNT_WORK_IN_LOG 150 + + +int modbusNetworkSharing(int flag_update_only_hmi) +{ + static unsigned int old_time = 0 , old_time_refresh = 0, time_pause = TIME_PAUSE_MODBUS_REMOUTE; + static unsigned int old_time_status_3 = 0, time_pause_status_3 = 500; + int final_code=0; + static unsigned int status=0; + static int numberInT=0, enable_send_cmd = 0; + + static int run_pause = 1, flag_next = 0, prev_flag_next = 0; + static int last_ok_cmd=0; + static int flag_only_one_cmd=0; + static int status_ok = 1, status_err = 0, flag_work_rs_send_log = 0, count_free = 0, count_work_in_log = 0; + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_20_ON; +#endif + + RS232_WorkingWith(0,1,0); + + // - + // control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] = 1; + + control_station_test_alive_all_control(); + + // if (detect_pause_milisec(100,&old_time_refresh)) + control_station.update_timers(&control_station); + + detecting_cmd_from_can(); + + // test_rs_can_with_svu_mpu(); +// test_alive_pult_485(); + + + // if (rs_b.RS_DataSended==0 && rs_b.RS_DataReadyAnswerAnalyze==0) + // status = 0; + + control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] = rs_b.RS_DataSended; + + final_code = 0; + + + switch(status) + { + case 0: + + old_time = global_time.miliseconds; + status = 1; + if (time_pause==0) + status = 2; + + break; + case 1: + // if (numberInT==0) + // { + if (detect_pause_milisec(time_pause,&old_time)) + status = 2; + // } + // else + // status = 2; + + break; + case 2: + enable_send_cmd = 1; + control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; + status = 3; + old_time_status_3 = global_time.miliseconds; + + break; + case 3: + // // rs485 + // if (flag_work_rs_send_log) + // { + // status = 0; + // status_ok++; + // if (status_ok<0) status_ok=1; + // } + + // rs485 ! + if (rs_b.RS_DataWillSend2 == 0 && enable_send_cmd == 0) + { + status = 0; + status_ok++; + count_free++; + } + else + if (rs_b.RS_DataReadyAnswerAnalyze) + { +// i_led2_on_off(0); + + control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; + control_station.count_ok_modbus[CONTROL_STATION_INGETEAM_PULT_RS485]++; + rs_b.RS_DataReadyAnswerAnalyze = 0; + rs_b.RS_DataWillSend2 = 0; + status = 0; + + if (last_ok_cmd==4) // readAnalogDataFromRemote() + { + edrk.get_new_data_from_hmi = 1;// ? + edrk.get_new_data_from_hmi2 = 1;// ? + } + final_code = last_ok_cmd;//numberInT+1; + + //status_err = 0; + status_ok++; + } + else + { + if ( (control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485]>control_station.setup_time_detect_active_resend_485[CONTROL_STATION_INGETEAM_PULT_RS485]) + || (detect_pause_milisec(time_pause_status_3,&old_time_status_3)) ) + { + resetup_mpu_rs(&rs_b); + control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; + rs_b.RS_DataWillSend2 = 0; + status = 0; + control_station.count_error_modbus[CONTROL_STATION_INGETEAM_PULT_RS485]++; + status_err++;// = 1; + } + + } + + if (status_ok<0) status_ok=1; + + break; + case 4: + + break; + case 5: + + break; + case 6: + + break; + default: + break; + + + + } + +/* + if (status==0) + { + old_time = global_time.miliseconds; + status = 1; + if (time_pause==0) + status = 2; + } + + if (status==1) + { +// if (numberInT==0) +// { + if (detect_pause_milisec(time_pause,&old_time)) + status = 2; +// } +// else +// status = 2; + } + + if (status==2) + { + enable_send_cmd = 1; + control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; + status = 3; + old_time_status_3 = global_time.miliseconds; + } + + if (status==3) + { + if (rs_b.RS_DataWillSend2 == 0) + { + + count_free++; + + } + + // rs485 + if (flag_work_rs_send_log) + { + status = 0; + status_ok++; + if (status_ok<0) status_ok=1; + } + + if (rs_b.RS_DataReadyAnswerAnalyze) + { +// i_led2_on_off(0); + + control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; + control_station.count_ok_modbus[CONTROL_STATION_INGETEAM_PULT_RS485]++; + rs_b.RS_DataReadyAnswerAnalyze = 0; + rs_b.RS_DataWillSend2 = 0; + status = 0; + + if (last_ok_cmd==4) // readAnalogDataFromRemote() + edrk.get_new_data_from_hmi = 1;// ? + final_code = last_ok_cmd;//numberInT+1; + + //status_err = 0; + status_ok++; + if (status_ok<0) status_ok=1; + } + else + { + if ( (control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485]>control_station.setup_time_detect_active_resend_485[CONTROL_STATION_INGETEAM_PULT_RS485]) + || (detect_pause_milisec(time_pause_status_3,&old_time_status_3)) ) + { + resetup_mpu_rs(&rs_b); + control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; + rs_b.RS_DataWillSend2 = 0; + status = 0; + control_station.count_error_modbus[CONTROL_STATION_INGETEAM_PULT_RS485]++; + status_err++;// = 1; + } + + } + + } +*/ +// switch (status) +// { +// case 0 : status = 1; +// break; +// +// case 1 : old_time = global_time.miliseconds; +// status = 2; +// break; +// +// case 2 : +// if (run_pause) +// { +// status = 3; +// run_pause = 0; +// } +// if (detect_pause_milisec(time_pause,&old_time)) +// status = 3; +// break; +// +// case 3 : +// enable_send_cmd = 1; +//// control_station.count_error_modbus_15[CONTROL_STATION_INGETEAM_PULT_RS485]++; +// control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; +// status = 4; +// break; +// +// +// case 4 : +// if (rs_b.RS_DataReadyAnswerAnalyze) +// { +// control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; +// control_station.count_ok_modbus[CONTROL_STATION_INGETEAM_PULT_RS485]++; +// rs_b.RS_DataReadyAnswerAnalyze = 0; +// status = 1; +// final_code = numberInT+1; +// } +// else +// { +// if (control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485]>control_station.setup_time_detect_active_resend_485[CONTROL_STATION_INGETEAM_PULT_RS485]) +// { +// resetup_mpu_rs(&rs_b); +// control_station.time_detect_answer_485[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; +// status = 1; +// control_station.count_error_modbus[CONTROL_STATION_INGETEAM_PULT_RS485]++; +// } +// } +// break; +// +// +// case 5 : break; +// +// +// case 6 : break; +// +// default : break; +// } + + +// +// +// if (control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] == 1) +// { +// if (control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] == 0 && prev_flag_waiting_answer == 1) +// { +// old_time = global_time.miliseconds; +// } +// +// if (control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] == 0) +// { +// if (detect_pause_milisec(time_pause,&old_time)) +// { +// control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] = 0; +// } +// +// } +// } +// prev_flag_waiting_answer = control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485]; +// +// +// if (control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] == 0 && +// control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] == 0 ) +// { +// enable_send_cmd = 1; +//// numberInT++; +//// if (numberInT>3) +//// numberInT = 1; +// } +// + + +// + if (flag_only_one_cmd) + numberInT=flag_only_one_cmd-1; +// + + + if (enable_send_cmd +// && (log_to_HMI.send_log == 0) + ) + { +//i_led2_on_off(1); + last_ok_cmd = numberInT; + switch (numberInT) + { + + case 0: + + if ((flag_update_only_hmi==0) && (edrk.flag_enable_update_hmi)) + update_tables_HMI_discrete(); + + writeDiscreteDataToRemote(); + edrk.test++; + + numberInT++; + enable_send_cmd = 0; + break; + + case 1: + + if ((flag_update_only_hmi==0) && (edrk.flag_enable_update_hmi)) +// if (edrk.flag_enable_update_hmi) + update_tables_HMI_analog(); + + writeAnalogDataToRemote(); // 1 + +// if (flag_update_only_hmi==1) +// // +// numberInT = 0; +// else + numberInT++; + + enable_send_cmd = 0; + break; + + case 2: + +// if (edrk.flag_enable_update_hmi) +// update_tables_HMI_analog(); + + writeAnalogDataToRemote(); // 2 + +// if (flag_update_only_hmi==1) +// // +// numberInT = 0; +// else + numberInT++; + + enable_send_cmd = 0; + break; + + + case 3: + readAnalogDataFromRemote(); // 1 + numberInT++; + enable_send_cmd = 0; + break; + + case 4: + readAnalogDataFromRemote(); // 2 + + if (log_to_HMI.send_log) + { + numberInT++; + } + else + // + numberInT = 0; + + enable_send_cmd = 0; + count_work_in_log = 0; // + break; + + case 5: + if (log_to_HMI.send_log) + { + time_pause = 2; + // ccc[0] = 1; + flag_work_rs_send_log = !sendLogToHMI(status_ok); + edrk.flag_slow_in_main = 1; + enable_send_cmd = 0; + + if (count_work_in_log>MAX_COUNT_WORK_IN_LOG) + { + count_work_in_log = 0; + numberInT = 0; // + + } + else + { + count_work_in_log++; + // + } + + } + else + { + time_pause = TIME_PAUSE_MODBUS_REMOUTE; + // ccc[0] = 0; + numberInT = 0; + enable_send_cmd = 0; + edrk.flag_slow_in_main = 0; + } + break; + + + default: + enable_send_cmd = 0; + break; + } + + +//i_led2_on_off(0); + + } + //sendLogToHMI(); + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_RS) + PWM_LINES_TK_20_OFF; +#endif + + if (flag_update_only_hmi) + return final_code; + + + return 0; +} + + + +int modbusNetworkSharingCAN(void) +{ +// static unsigned int old_time1 = 0 , time_pause1 = TIME_PAUSE_NETWORK_CAN1; +// static unsigned int old_time2 = 0 , time_pause2 = TIME_PAUSE_NETWORK_CAN2; +// static unsigned int old_time3 = 0 , time_pause3 = TIME_PAUSE_NETWORK_CAN3; + static unsigned int time_pause_modbus_can_terminals = TIME_PAUSE_MODBUS_CAN_TERMINALS; + + + +#if (ENABLE_CAN_SEND_TO_MPU_FROM_MAIN) +// if (detect_pause_milisec(time_pause1,&old_time1)) + static unsigned int time_pause_modbus_can_mpu = TIME_PAUSE_MODBUS_CAN_MPU; + write_all_data_to_mpu_can(1, time_pause_modbus_can_mpu); +#endif + +#if (ENABLE_CAN_SEND_TO_TERMINAL_FROM_MAIN) +// if (detect_pause_milisec(time_pause2,&old_time2)) + write_all_data_to_terminals_can(1, time_pause_modbus_can_terminals); +#endif + + +#if (ENABLE_CAN_SEND_TO_TERMINAL_OSCIL) +// if (detect_pause_milisec(time_pause3,&old_time3)) + oscil_can.pause_can = TIME_PAUSE_MODBUS_CAN_OSCIL; + oscil_can.send(&oscil_can); +#endif + + return 0; +} + diff --git a/Inu/Src2/551/main/message_modbus.h b/Inu/Src2/551/main/message_modbus.h new file mode 100644 index 0000000..971e5a9 --- /dev/null +++ b/Inu/Src2/551/main/message_modbus.h @@ -0,0 +1,61 @@ + +#ifndef _MESSAGE_MODBUS_H +#define _MESSAGE_MODBUS_H + + + +// void ReceiveCommandModbus3(RS_DATA *rs_arr); +// void ReceiveCommandModbus16(RS_DATA *rs_arr); +// void ReceiveCommandModbus15(RS_DATA *rs_arr); + +// void SendCommandModbus3(RS_DATA *rs_arr,int adr_contr, unsigned int adr_start,unsigned int count_word); +// void SendCommandModbus16(RS_DATA *rs_arr,int adr_contr, unsigned int adr_start,unsigned int count_word); + +// void ReceiveAnswerCommandModbus16(RS_DATA *rs_arr); +// void ReceiveAnswerCommandModbus3(RS_DATA *rs_arr); + +#define TIME_PAUSE_MODBUS_MPU 250 //100//500 +#define TIME_PAUSE_MODBUS_REMOUTE 20 //100 //500 + +#define TIME_PAUSE_NETWORK_CAN1 444 //500 +#define TIME_PAUSE_NETWORK_CAN2 990 //500 +#define TIME_PAUSE_NETWORK_CAN3 1855 //500 + +//#define START_ADR_ARR 0xc000 +//#define LENGTH_ADR_ARR 0x100 +//#define SIZE_MODBUS_TABLE_DISCRETE_REMOUTE 36 // = 576/16 +#define SIZE_BUF_WRITE_TO_MODBUS1_REMOUTE SIZE_MODBUS_TABLE_DISCRET_REMOUTE // SIZE_MODBUS_TABLE_DISCRET_BITS //576 // 3 modbus . +#define SIZE_BUF_WRITE_TO_MODBUS15_REMOUTE SIZE_MODBUS_TABLE_DISCRET_REMOUTE //SIZE_MODBUS_TABLE_DISCRET_BITS //576 //96 + + +#define SIZE_BUF_WRITE_TO_MODBUS16_VPU 100 // + +#define SIZE_BUF_WRITE_TO_MODBUS16_REMOUTE 120 //100 // , . , SIZE_ANALOG_DATA_REMOUTE +#define SIZE_ANALOG_DATA_REMOUTE 240 //165 // , + + +#define SIZE_BUF_READ_FROM_MODBUS16_REMOUTE 120 //20//36 // , . , SIZE_ANALOG_DATA_FROM_MODBUS16_REMOUTE +#define SIZE_ANALOG_DATA_FROM_MODBUS16_REMOUTE SIZE_ANALOG_DATA_REMOUTE //20//36 // , + + +#define SIZE_BUF_WRITE_TO_MODBUS16_CAN 100 //10 //1000//400//04.04.2012 //100// //800 +#define START_LOG_MODBUS16_ADRES 100 +#define SIZE_BUF_WRITE_LOG_TO_MODBUS16 120 +//#define SIZE_ANALOG_DATA 61 + + +#define MAX_COUNT_ERROR_FROM_RS_MPU 10 + +//void test_rs_can_with_svu_mpu(); +void write_all_data_to_mpu_can(int run_force, unsigned int pause); +void read_all_data_from_mpu_485(int run_force); +void write_all_data_to_mpu_485(int run_force); +extern int enable_can; + +int modbusNetworkSharing(int flag_update_only_hmi); +int modbusNetworkSharingCAN(void); + + + +#endif //_MESSAGE_MODBUS_H + diff --git a/Inu/Src2/551/main/message_terminals_can.c b/Inu/Src2/551/main/message_terminals_can.c new file mode 100644 index 0000000..c21892a --- /dev/null +++ b/Inu/Src2/551/main/message_terminals_can.c @@ -0,0 +1,128 @@ +/* + * message_terminals_can.c + * + * Created on: 15 2020 . + * Author: yura + */ +#include +#include +#include +#include + +#include "CAN_Setup.h" +#include "global_time.h" +#include "modbus_table_v2.h" +#include "oscil_can.h" +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "CRC_Functions.h" +#include "RS_Function_terminal.h" +#include "TuneUpPlane.h" +#include "control_station.h" + + + +#define TERMINALS_CAN_TIME_WAIT 500 // +#pragma DATA_SECTION(buf_message_can_cmd,".slow_vars") +int buf_message_can_cmd[sizeof(CMD_TO_TMS_STRUCT)+10]; +#pragma DATA_SECTION(buf_message_can_data,".slow_vars") +int buf_message_can_data[sizeof(TMS_TO_TERMINAL_STRUCT)+10]; +#pragma DATA_SECTION(buf_message_can_data2,".slow_vars") +int buf_message_can_data2[sizeof(TMS_TO_TERMINAL_STRUCT)+10]; + +int *p_buf_message_can_data3; + + +void write_all_data_to_terminals_can(int run_force, unsigned int pause) +{ + static unsigned int old_time = 0; + static unsigned int send_time = 0; + static int prev_send_to_can = 0; + + static int count_sends = 0; + + unsigned long old_t; + unsigned int i; + int real_mbox; + CMD_TO_TMS_STRUCT* pcommand = (CMD_TO_TMS_STRUCT *)(buf_message_can_cmd); + + + real_mbox = get_real_out_mbox(TERMINAL_TYPE_BOX, edrk.number_can_box_terminal_cmd); + + // , , + // .. TERMINALS_CAN_TIME_WAIT . + if (prev_send_to_can && CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_OFF)==0) + { + old_time = (unsigned int)global_time.miliseconds; + return; + } + prev_send_to_can = 0; + + if (!detect_pause_milisec(pause,&old_time)) + return; + + + //func_fill_answer_to_TMS(&reply, pcommand); + func_pack_answer_to_TMS(&reply); + + *(TMS_TO_TERMINAL_STRUCT*)buf_message_can_data2 = reply; // + + + + // reply.digit_data.byte01.byte_data = send_time; +/* reply.digit_data.byte02.byte_data = 0x66; + reply.analog_data.analog60_hi = 0x33; + reply.analog_data.analog60_lo = 0x44; +*/ + reply.analog_data.analog58_hi = HIBYTE((unsigned int)control_station.raw_array_data[CONTROL_STATION_TERMINAL_CAN][0].all); + reply.analog_data.analog58_lo = LOBYTE((unsigned int)control_station.raw_array_data[CONTROL_STATION_TERMINAL_CAN][0].all); + +// control_station.raw_array_data[CONTROL_STATION_TERMINAL_CAN][0].all + + reply.analog_data.analog59_hi = HIBYTE((unsigned int)global_time.miliseconds); + reply.analog_data.analog59_lo = LOBYTE((unsigned int)global_time.miliseconds); + + reply.analog_data.analog60_hi = HIBYTE(count_sends); + reply.analog_data.analog60_lo = LOBYTE(count_sends); + count_sends++; + if (count_sends>32768) count_sends=0; + +// reply.analog_data.analog1_hi = HIBYTE(send_time); + // reply.analog_data.analog1_lo = LOBYTE(send_time); + +// reply.analog_data.analog2_hi = HIBYTE(oscil_can.timer_send); +// reply.analog_data.analog2_lo = LOBYTE(oscil_can.timer_send); + + p_buf_message_can_data3 = (int *)&reply.digit_data; + + + for (i=0;i>1] |= ( (*p_buf_message_can_data3++) << 8) & 0xff00; + } + else + buf_message_can_data[i>>1] = ( (*p_buf_message_can_data3++) ) & 0x00ff; + + } + + if (CAN_cycle_full_free(real_mbox,CAN_BOX_STAT_ON)) + { + + old_t = global_time.microseconds; + CAN_cycle_send( + TERMINAL_TYPE_BOX, + edrk.number_can_box_terminal_cmd, + 0, + &buf_message_can_data[0], ((sizeof(TMS_TO_TERMINAL_STRUCT)-5)>>1), CAN_BOX_STANDART_ADR, CAN_BOX_PRIORITY_NORMAL); + + prev_send_to_can = 1; + + + send_time = (global_time.microseconds - old_t)/100; + } + + +} diff --git a/Inu/Src2/551/main/message_terminals_can.h b/Inu/Src2/551/main/message_terminals_can.h new file mode 100644 index 0000000..90cf1c6 --- /dev/null +++ b/Inu/Src2/551/main/message_terminals_can.h @@ -0,0 +1,15 @@ +/* + * message_terminals_can.h + * + * Created on: 22 2020 . + * Author: yura + */ + +#ifndef SRC_MAIN_MESSAGE_TERMINALS_CAN_H_ +#define SRC_MAIN_MESSAGE_TERMINALS_CAN_H_ + +void write_all_data_to_terminals_can(int run_force, unsigned int pause); + + + +#endif /* SRC_MAIN_MESSAGE_TERMINALS_CAN_H_ */ diff --git a/Inu/Src2/551/main/modbus_hmi.c b/Inu/Src2/551/main/modbus_hmi.c new file mode 100644 index 0000000..f28cb25 --- /dev/null +++ b/Inu/Src2/551/main/modbus_hmi.c @@ -0,0 +1,393 @@ +#include "log_to_memory.h" +#include +#include +#include +#include + +#include "control_station.h" +#include "global_time.h" +#include "modbus_table_v2.h" +#include "RS_modbus_pult.h" +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "RS_modbus_svu.h" +#include "log_params.h" + + +#pragma DATA_SECTION(modbus_table_discret_in,".logs"); +MODBUS_REG_STRUCT modbus_table_discret_in[SIZE_MODBUS_TABLE_DISCRET_REMOUTE]; //registers 10001-19999 modbus RTU + +#pragma DATA_SECTION(modbus_table_discret_out,".logs"); +MODBUS_REG_STRUCT modbus_table_discret_out[SIZE_MODBUS_TABLE_DISCRET_REMOUTE]; //registers 1-9999 modbus RTU + +#pragma DATA_SECTION(modbus_table_analog_in, ".logs"); +MODBUS_REG_STRUCT modbus_table_analog_in[SIZE_MODBUS_ANALOG_REMOUTE]; //registers 30001-39999 modbus RTU + +#pragma DATA_SECTION(modbus_table_analog_out, ".logs"); +//MODBUS_REG_STRUCT modbus_table_analog_out[700]; //registers 40001-49999 modbus RTU +MODBUS_REG_STRUCT modbus_table_analog_out[SIZE_MODBUS_ANALOG_REMOUTE]; //registers 40001-49999 modbus RTU + +//#pragma DATA_SECTION(modbus_table_analog_out2, ".logs"); +//MODBUS_REG_STRUCT modbus_table_analog_out[700]; //registers 40001-49999 modbus RTU +//MODBUS_REG_STRUCT modbus_table_analog_out2[SIZE_MODBUS_ANALOG_REMOUTE]; //registers 40001-49999 modbus RTU + + +//unsigned int flag_waiting_answer = 1; +//unsigned int flag_message_sent = 0; + + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +void clear_table_remoute(void) +{ + int i; + + for (i=0;i= 0 && adres < SIZE_MODBUS_TABLE_DISCRET_BITS) + { +// word_number = (adres % 16 == 0) && (adres != 0) ? adres / 16 + 1 : +// adres / 16; + word_number = (adres % 16 == 0) && (adres != 0) ? adres / 16 : + adres / 16; + bit_number = adres % 16; + + if (word_number= 0 && adres < SIZE_MODBUS_TABLE_DISCRET_BITS) { + word_number = adres / 16; + bit_number = adres % 16; + return (modbus_table_discret_out[word_number].all >> bit_number) & 1; + } + + return 0; +} + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +int readDiscreteOutputsFromRemote() +{ + int succed = 0; + static unsigned int time_tick_modbus = 0; + static unsigned int old_PWM_ticks = 0; + static unsigned int count_write_to_modbus = 0; + static int cur_position_buf_modbus1 = 0; + + ModbusRTUsetDiscretDataArray(modbus_table_discret_out, modbus_table_discret_out); + +// if (global_time.pwm_tics != old_PWM_ticks) +// { +// if (global_time.pwm_tics > old_PWM_ticks) +// time_tick_modbus = time_tick_modbus + (global_time.pwm_tics - old_PWM_ticks); +// else +// time_tick_modbus++; +// } +// old_PWM_ticks = global_time.pwm_tics; +// if (TIME_PAUSE_MODBUS < time_tick_modbus) +// { + if (!rs_b.flag_LEADING) + { +// time_tick_modbus = 0; + + if (control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] == 0) + cur_position_buf_modbus1 = cur_position_buf_modbus1 + SIZE_BUF_WRITE_TO_MODBUS1_REMOUTE; + + if (cur_position_buf_modbus1 >= SIZE_MODBUS_TABLE_DISCRET_REMOUTE) + cur_position_buf_modbus1 = 0; + + if ((cur_position_buf_modbus1 + SIZE_BUF_WRITE_TO_MODBUS1_REMOUTE) > SIZE_MODBUS_TABLE_DISCRET_REMOUTE) + count_write_to_modbus = SIZE_MODBUS_TABLE_DISCRET_REMOUTE - cur_position_buf_modbus1; + else + count_write_to_modbus = SIZE_BUF_WRITE_TO_MODBUS1_REMOUTE; + + ModbusRTUsend1(&rs_b, 2, + ADR_MODBUS_TABLE_REMOUTE + cur_position_buf_modbus1, + count_write_to_modbus); + succed = 1; + // control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] = 1; + } +// } + return succed; +} + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +int writeSigleDiscreteDataToRemote(unsigned int adres) +{ + ModbusRTUsetDiscretDataArray(modbus_table_discret_out, modbus_table_discret_out); + if (!rs_b.flag_LEADING && !control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] && + (adres < SIZE_MODBUS_TABLE_DISCRET_BITS)) { + ModbusRTUsend5(&rs_b, 2, ADR_MODBUS_TABLE_REMOUTE + adres); + return 1; + } + return 0; +} + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +int writeSingleAnalogOutputToRemote(unsigned int adres) +{ + ModbusRTUsetDataArrays(modbus_table_analog_in, modbus_table_analog_out); + if (!rs_b.flag_LEADING && !control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] && + (adres < SIZE_MODBUS_ANALOG_REMOUTE)) { + ModbusRTUsend6(&rs_b, 2, ADR_MODBUS_TABLE_REMOUTE + adres); + return 1; + } + return 0; +} + + + + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +int writeDiscreteDataToRemote() +{ + int succed = 0; + static unsigned int old_time = 0; + + static unsigned int count_write_to_modbus = 0; + static int cur_position_buf_modbus15 = 0; + + //ModbusRTUsetDiscretDataArray(modbus_table_discret_out, modbus_table_discret_out); + ModbusRTUsetDiscretDataArray(modbus_table_discret_in, modbus_table_discret_out); + + + if (!rs_b.flag_LEADING) + { + +// if (rs_b.RS_DataReadyAnswerAnalyze) +// { +// cur_position_buf_modbus15 += SIZE_BUF_WRITE_TO_MODBUS15_REMOUTE; +// } + + if (cur_position_buf_modbus15 >= (SIZE_MODBUS_TABLE_DISCRET_REMOUTE)) + cur_position_buf_modbus15 = 0; + + if ((cur_position_buf_modbus15 + SIZE_BUF_WRITE_TO_MODBUS15_REMOUTE) > (SIZE_MODBUS_TABLE_DISCRET_REMOUTE)) + count_write_to_modbus = SIZE_MODBUS_TABLE_DISCRET_REMOUTE - cur_position_buf_modbus15; + else + count_write_to_modbus = SIZE_BUF_WRITE_TO_MODBUS15_REMOUTE; + + // count_write_to_modbus = SIZE_BUF_WRITE_TO_MODBUS16; + // cur_position_buf_modbus=0; + + ModbusRTUsend15(&rs_b, 2, ADR_MODBUS_TABLE_REMOUTE + cur_position_buf_modbus15*16, + count_write_to_modbus*16); +// ModbusRTUsend15(&rs_a, 2, ADR_MODBUS_TABLE_REMOUTE + cur_position_buf_modbus15*16, +// count_write_to_modbus*16); + + cur_position_buf_modbus15 += SIZE_BUF_WRITE_TO_MODBUS15_REMOUTE; + + // control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] = 1; + // control_station.count_error_modbus_15[CONTROL_STATION_INGETEAM_PULT_RS485]++; + + // hmi_watch_dog = !hmi_watch_dog; //was transmitted, need to change + succed = 1; + + } + return succed; +} + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +#define ADRESS_END_FIRST_BLOCK 20 +#define ADRESS_START_PROTECTION_LEVELS 91 + +int readAnalogDataFromRemote() +{ + int succed = 0; + static unsigned int old_time = 0; + + static unsigned int count_write_to_modbus = 0; + static int cur_position_buf_modbus3 = 0, size_buf = SIZE_BUF_READ_FROM_MODBUS16_REMOUTE; + + + ModbusRTUsetDataArrays(modbus_table_analog_in, modbus_table_analog_out); + + + + if (!rs_b.flag_LEADING) + { + + if (control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] == 0) + cur_position_buf_modbus3 = cur_position_buf_modbus3 + size_buf; + + if (cur_position_buf_modbus3 >= SIZE_ANALOG_DATA_FROM_MODBUS16_REMOUTE) + cur_position_buf_modbus3 = 0; + // . . + if ((cur_position_buf_modbus3 > ADRESS_END_FIRST_BLOCK) && + (cur_position_buf_modbus3 < ADRESS_START_PROTECTION_LEVELS)) { + cur_position_buf_modbus3 = ADRESS_START_PROTECTION_LEVELS; + } + if((cur_position_buf_modbus3 < ADRESS_END_FIRST_BLOCK) && + (cur_position_buf_modbus3 + size_buf) > ADRESS_END_FIRST_BLOCK) { + count_write_to_modbus = ADRESS_END_FIRST_BLOCK - cur_position_buf_modbus3; + } + + if ((cur_position_buf_modbus3 + size_buf) > SIZE_ANALOG_DATA_FROM_MODBUS16_REMOUTE) + count_write_to_modbus = SIZE_ANALOG_DATA_FROM_MODBUS16_REMOUTE - cur_position_buf_modbus3; + else + count_write_to_modbus = size_buf; + + // count_write_to_modbus = SIZE_BUF_WRITE_TO_MODBUS16; + // cur_position_buf_modbus=0; + + + // SendCommandModbus3(&rs_b,1,ADR_MODBUS_TABLE+cur_position_buf_modbus3,count_write_to_modbus); + ModbusRTUsend4(&rs_b, 2, + ADR_MODBUS_TABLE_REMOUTE + cur_position_buf_modbus3, + count_write_to_modbus); + // control_station.count_error_modbus_4[CONTROL_STATION_INGETEAM_PULT_RS485]++; + + // control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] = 1; + succed = 1; + } + return succed; +} + + +int writeSingleAnalogDataToRemote(int from_adr, int count_wr) +{ + int succed = 0; + static unsigned int old_time = 0; + + static int count_write_to_modbus = 0; + static int cur_position_buf_modbus16 = 0; + + + ModbusRTUsetDataArrays(modbus_table_analog_in, modbus_table_analog_out); + + + if (!rs_b.flag_LEADING) + { + cur_position_buf_modbus16 = from_adr; + +// if (control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] == 0) +// cur_position_buf_modbus16 = cur_position_buf_modbus16 + SIZE_BUF_WRITE_TO_MODBUS16_REMOUTE; +// +// if (cur_position_buf_modbus16 >= SIZE_ANALOG_DATA_REMOUTE) +// cur_position_buf_modbus16 = 0; + +// // . . +// if ((cur_position_buf_modbus16 > ADRESS_END_FIRST_BLOCK) && +// (cur_position_buf_modbus16 < ADRESS_START_PROTECTION_LEVELS)) { +// cur_position_buf_modbus16 = ADRESS_START_PROTECTION_LEVELS; +// } + + if ((cur_position_buf_modbus16 + count_wr) > SIZE_ANALOG_DATA_REMOUTE) + count_write_to_modbus = SIZE_ANALOG_DATA_REMOUTE - cur_position_buf_modbus16; + else + count_write_to_modbus = count_wr; + + ModbusRTUsend16(&rs_b, 2, + ADR_MODBUS_TABLE_REMOUTE + cur_position_buf_modbus16, + count_write_to_modbus); + + succed = 1; + } + return succed; +} + + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +int writeAnalogDataToRemote() +{ + int succed = 0; + static unsigned int old_time = 0; + + static int count_write_to_modbus = 0; + static int cur_position_buf_modbus16 = 0; + + + ModbusRTUsetDataArrays(modbus_table_analog_in, modbus_table_analog_out); + + + if (!rs_b.flag_LEADING) + { + if (control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485] == 0) + cur_position_buf_modbus16 = cur_position_buf_modbus16 + SIZE_BUF_WRITE_TO_MODBUS16_REMOUTE; + + if (cur_position_buf_modbus16 >= SIZE_ANALOG_DATA_REMOUTE) + cur_position_buf_modbus16 = 0; + +// // . . +// if ((cur_position_buf_modbus16 > ADRESS_END_FIRST_BLOCK) && +// (cur_position_buf_modbus16 < ADRESS_START_PROTECTION_LEVELS)) { +// cur_position_buf_modbus16 = ADRESS_START_PROTECTION_LEVELS; +// } + + if ((cur_position_buf_modbus16 + SIZE_BUF_WRITE_TO_MODBUS16_REMOUTE) > SIZE_ANALOG_DATA_REMOUTE) + count_write_to_modbus = SIZE_ANALOG_DATA_REMOUTE - cur_position_buf_modbus16; + else + count_write_to_modbus = SIZE_BUF_WRITE_TO_MODBUS16_REMOUTE; + + ModbusRTUsend16(&rs_b, 2, + ADR_MODBUS_TABLE_REMOUTE + cur_position_buf_modbus16, + count_write_to_modbus); + // control_station.count_error_modbus_16[CONTROL_STATION_INGETEAM_PULT_RS485]++; + + // control_station.flag_message_sent[CONTROL_STATION_INGETEAM_PULT_RS485] = 1; + succed = 1; + } + return succed; +} + + + + + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// + + + diff --git a/Inu/Src2/551/main/modbus_hmi.h b/Inu/Src2/551/main/modbus_hmi.h new file mode 100644 index 0000000..887b537 --- /dev/null +++ b/Inu/Src2/551/main/modbus_hmi.h @@ -0,0 +1,39 @@ +#ifndef _MODBUS_HMI +#define _MODBUS_HMI + +#include "modbus_struct.h" + + +int readDiscreteOutputsFromRemote(); +int writeSigleDiscreteDataToRemote(unsigned int adres); +int writeSingleAnalogOutputToRemote(unsigned int adres); +int writeDiscreteDataToRemote(); +int readAnalogDataFromRemote(); +int writeAnalogDataToRemote(); +int writeSingleAnalogDataToRemote(int from_adr, int count_wr); + +void setRegisterDiscreteOutput(int value, int adres); +int getRegisterDiscreteOutput(int adres); + + + + +void clear_table_remoute(void); // clear table + +#define ADRES_LOG_REGISTERS 100 + + +#define SIZE_MODBUS_TABLE_DISCRET_REMOUTE 36 +#define SIZE_MODBUS_TABLE_DISCRET_BITS (SIZE_MODBUS_TABLE_DISCRET_REMOUTE * 16) +#define SIZE_MODBUS_ANALOG_REMOUTE 900 + + +extern MODBUS_REG_STRUCT modbus_table_analog_in[SIZE_MODBUS_ANALOG_REMOUTE]; +extern MODBUS_REG_STRUCT modbus_table_analog_out[SIZE_MODBUS_ANALOG_REMOUTE]; +extern MODBUS_REG_STRUCT modbus_table_discret_in[SIZE_MODBUS_TABLE_DISCRET_REMOUTE]; +extern MODBUS_REG_STRUCT modbus_table_discret_out[SIZE_MODBUS_TABLE_DISCRET_REMOUTE]; + +//extern unsigned int flag_waiting_answer; +//extern unsigned int flag_message_sent; + +#endif //_MODBUS_HMI diff --git a/Inu/Src2/551/main/modbus_hmi_read.c b/Inu/Src2/551/main/modbus_hmi_read.c new file mode 100644 index 0000000..9718943 --- /dev/null +++ b/Inu/Src2/551/main/modbus_hmi_read.c @@ -0,0 +1,222 @@ +/* + * modbus_hmi_read.c + * + * Created on: 21 . 2020 . + * Author: star + */ +#include +#include +#include +#include +#include + + +#define DELTA_ABNORMAL_P_WATER_MIN 50 +#define DELTA_ABNORMAL_P_WATER_MAX 100 + +void parse_protect_levels_HMI() { + + if (modbus_table_analog_in[91].all > 0) { + protect_levels.abnormal_temper_acdrive_winding_U1 = modbus_table_analog_in[91].all * 10; + } + if(modbus_table_analog_in[92].all > 0) { + protect_levels.abnormal_temper_acdrive_winding_V1 = modbus_table_analog_in[92].all * 10; + } + if(modbus_table_analog_in[93].all > 0) { + protect_levels.abnormal_temper_acdrive_winding_W1 = modbus_table_analog_in[93].all * 10; + } + if (modbus_table_analog_in[94].all > 0) { + protect_levels.abnormal_temper_acdrive_winding_U2 = modbus_table_analog_in[94].all * 10; + } + if (modbus_table_analog_in[95].all > 0) { + protect_levels.abnormal_temper_acdrive_winding_V2 = modbus_table_analog_in[95].all * 10; + } + if (modbus_table_analog_in[96].all > 0) { + protect_levels.abnormal_temper_acdrive_winding_W2 = modbus_table_analog_in[96].all * 10; + } + if (modbus_table_analog_in[97].all > 0) { + protect_levels.abnormal_temper_acdrive_bear_DNE = modbus_table_analog_in[97].all * 10; + } + if(modbus_table_analog_in[98].all > 0) { + protect_levels.abnormal_temper_acdrive_bear_NE = modbus_table_analog_in[98].all * 10; + } + + if (modbus_table_analog_in[99].all > 0) { + protect_levels.alarm_temper_acdrive_winding_U1 = modbus_table_analog_in[99].all * 10; + } + if (modbus_table_analog_in[100].all > 0) { + protect_levels.alarm_temper_acdrive_winding_V1 = modbus_table_analog_in[100].all * 10; + } + if (modbus_table_analog_in[101].all > 0) { + protect_levels.alarm_temper_acdrive_winding_W1 = modbus_table_analog_in[101].all * 10; + } + if (modbus_table_analog_in[102].all > 0) { + protect_levels.alarm_temper_acdrive_winding_U2 = modbus_table_analog_in[102].all * 10; + } + if (modbus_table_analog_in[103].all > 0) { + protect_levels.alarm_temper_acdrive_winding_V2 = modbus_table_analog_in[103].all * 10; + } + if (modbus_table_analog_in[104].all > 0) { + protect_levels.alarm_temper_acdrive_winding_W2 = modbus_table_analog_in[104].all * 10; + } + if (modbus_table_analog_in[105].all > 0) { + protect_levels.alarm_temper_acdrive_bear_DNE = modbus_table_analog_in[105].all * 10; + } + if (modbus_table_analog_in[106].all > 0) { + protect_levels.alarm_temper_acdrive_bear_NE = modbus_table_analog_in[106].all * 10; + } + + if (modbus_table_analog_in[107].all > 0) { + protect_levels.abnormal_temper_u_01 = modbus_table_analog_in[107].all * 10; + } + if (modbus_table_analog_in[108].all > 0) { + protect_levels.abnormal_temper_u_02 = modbus_table_analog_in[108].all * 10; + } + if (modbus_table_analog_in[109].all > 0) { + protect_levels.abnormal_temper_u_03 = modbus_table_analog_in[109].all * 10; + } + if (modbus_table_analog_in[110].all > 0) { + protect_levels.abnormal_temper_u_04 = modbus_table_analog_in[110].all * 10; + } + if (modbus_table_analog_in[111].all > 0) { + protect_levels.abnormal_temper_u_05 = modbus_table_analog_in[111].all * 10; + } + if (modbus_table_analog_in[112].all > 0) { + protect_levels.abnormal_temper_u_06 = modbus_table_analog_in[112].all * 10; + } + if (modbus_table_analog_in[113].all > 0) { + protect_levels.abnormal_temper_u_07 = modbus_table_analog_in[113].all * 10; + } + if (modbus_table_analog_in[114].all > 0) { + protect_levels.alarm_temper_u_01 = modbus_table_analog_in[114].all * 10; + } + if (modbus_table_analog_in[115].all > 0) { + protect_levels.alarm_temper_u_02 = modbus_table_analog_in[115].all * 10; + } + if (modbus_table_analog_in[116].all > 0) { + protect_levels.alarm_temper_u_03 = modbus_table_analog_in[116].all * 10; + } + if (modbus_table_analog_in[117].all > 0) { + protect_levels.alarm_temper_u_04 = modbus_table_analog_in[117].all * 10; + } + if (modbus_table_analog_in[118].all > 0) { + protect_levels.alarm_temper_u_05 = modbus_table_analog_in[118].all * 10; + } + if (modbus_table_analog_in[119].all > 0) { + protect_levels.alarm_temper_u_06 = modbus_table_analog_in[119].all * 10; + } + if (modbus_table_analog_in[120].all > 0) { + protect_levels.alarm_temper_u_07 = modbus_table_analog_in[120].all * 10; + } + + if (modbus_table_analog_in[123].all > 0) { + protect_levels.abnormal_temper_water_int = modbus_table_analog_in[123].all * 10; + } + if (modbus_table_analog_in[124].all > 0) { + protect_levels.abnormal_temper_water_ext = modbus_table_analog_in[124].all * 10; + } + if (modbus_table_analog_in[125].all > 0) { + protect_levels.alarm_p_water_min_int = modbus_table_analog_in[125].all * 10; + protect_levels.abnormal_p_water_min_int = protect_levels.alarm_p_water_min_int + DELTA_ABNORMAL_P_WATER_MIN; + } + if (modbus_table_analog_in[126].all > 0) { + protect_levels.alarm_temper_water_int = modbus_table_analog_in[126].all * 10; + } + if (modbus_table_analog_in[127].all > 0) { + protect_levels.alarm_temper_water_ext = modbus_table_analog_in[127].all * 10; + } + if (modbus_table_analog_in[128].all > 0) { + protect_levels.alarm_p_water_max_int = modbus_table_analog_in[128].all * 10; + protect_levels.abnormal_p_water_max_int = protect_levels.alarm_p_water_max_int - DELTA_ABNORMAL_P_WATER_MAX; + } + + if (modbus_table_analog_in[129].all > 0) { + protect_levels.abnormal_temper_air_int_01 = modbus_table_analog_in[129].all * 10; + } + if (modbus_table_analog_in[130].all > 0) { + protect_levels.abnormal_temper_air_int_02 = modbus_table_analog_in[130].all * 10; + } + if (modbus_table_analog_in[131].all > 0) { + protect_levels.abnormal_temper_air_int_03 = modbus_table_analog_in[131].all * 10; + } + if (modbus_table_analog_in[132].all > 0) { + protect_levels.abnormal_temper_air_int_04 = modbus_table_analog_in[132].all * 10; + } + if (modbus_table_analog_in[133].all > 0) { + protect_levels.alarm_temper_air_int_01 = modbus_table_analog_in[133].all * 10; + } + if (modbus_table_analog_in[134].all > 0) { + protect_levels.alarm_temper_air_int_02 = modbus_table_analog_in[134].all * 10; + } + if (modbus_table_analog_in[135].all > 0) { + protect_levels.alarm_temper_air_int_03 = modbus_table_analog_in[135].all * 10; + } + if (modbus_table_analog_in[136].all > 0) { + protect_levels.alarm_temper_air_int_04 = modbus_table_analog_in[136].all * 10; + } + + if (modbus_table_analog_in[137].all > 0) { + edrk.iqMIN_U_IN = _IQ(((float)modbus_table_analog_in[137].all) / NORMA_ACP); + } + if (modbus_table_analog_in[138].all > 0) { + edrk.iqMIN_U_IN = _IQ(((float)modbus_table_analog_in[138].all) / NORMA_ACP); + } + + if (modbus_table_analog_in[139].all > 0) { + edrk.iqMIN_U_ZPT = _IQ(((float)modbus_table_analog_in[139].all) / NORMA_ACP); + } + if (modbus_table_analog_in[140].all > 0) { + edrk.iqMIN_U_ZPT = _IQ(((float)modbus_table_analog_in[140].all) / NORMA_ACP); + } + + if (modbus_table_analog_in[142].all > 0) { + edrk.iqMAX_U_IN = _IQ(((float)modbus_table_analog_in[142].all) / NORMA_ACP); + } + if (modbus_table_analog_in[143].all > 0) { + edrk.iqMAX_U_IN = _IQ(((float)modbus_table_analog_in[143].all) / NORMA_ACP); + } + + if (modbus_table_analog_in[144].all > 0) { + edrk.iqMAX_U_ZPT = _IQ(((float)modbus_table_analog_in[144].all) / NORMA_ACP); + } + if (modbus_table_analog_in[145].all > 0) { + edrk.iqMAX_U_ZPT = _IQ(((float)modbus_table_analog_in[145].all) / NORMA_ACP); + } + + if (modbus_table_analog_in[146].all > 0) { + protect_levels.alarm_Izpt_max = modbus_table_analog_in[146].all; + } + + if (modbus_table_analog_in[155].all > 0) { + protect_levels.alarm_Imax_U01 = modbus_table_analog_in[155].all; + } + if (modbus_table_analog_in[156].all > 0) { + protect_levels.alarm_Imax_U02 = modbus_table_analog_in[156].all; + } + if (modbus_table_analog_in[157].all > 0) { + protect_levels.alarm_Imax_U03 = modbus_table_analog_in[157].all; + } + if (modbus_table_analog_in[158].all > 0) { + protect_levels.alarm_Imax_U04 = modbus_table_analog_in[158].all; + } + if (modbus_table_analog_in[159].all > 0) { + protect_levels.alarm_Imax_U05 = modbus_table_analog_in[159].all; + } + if (modbus_table_analog_in[160].all > 0) { + protect_levels.alarm_Imax_U06 = modbus_table_analog_in[160].all; + } + if (modbus_table_analog_in[161].all > 0) { + protect_levels.alarm_Imax_U07 = modbus_table_analog_in[161].all; + } + if (modbus_table_analog_in[162].all > 0) { + protect_levels.alarm_Iged_max = modbus_table_analog_in[162].all; + } + + + + + +} + + + diff --git a/Inu/Src2/551/main/modbus_hmi_read.h b/Inu/Src2/551/main/modbus_hmi_read.h new file mode 100644 index 0000000..7f3e0db --- /dev/null +++ b/Inu/Src2/551/main/modbus_hmi_read.h @@ -0,0 +1,15 @@ +/* + * modbus_hmi_read.h + * + * Created on: 21 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_MODBUS_HMI_READ_H_ +#define SRC_MAIN_MODBUS_HMI_READ_H_ + + +void parse_protect_levels_HMI(void); + + +#endif /* SRC_MAIN_MODBUS_HMI_READ_H_ */ diff --git a/Inu/Src2/551/main/modbus_hmi_update.c b/Inu/Src2/551/main/modbus_hmi_update.c new file mode 100644 index 0000000..7c1e83c --- /dev/null +++ b/Inu/Src2/551/main/modbus_hmi_update.c @@ -0,0 +1,2022 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "edrk_main.h" +#include "global_time.h" +#include "control_station.h" +#include "CAN_Setup.h" +#include "global_time.h" +#include "RS_Functions.h" +#include "mathlib.h" +#include "logs_hmi.h" +#include "detect_errors.h" +/* +#include "mathlib.h" +#include +#include "IQmathLib.h" +*/ +int hmi_watch_dog = 0; +int prev_kvitir = 0; +int prev_sbor = 0; +int kvitir1 = 0; +int sbor1 = 0; +int razbor1 = 0; + +//30001 ResetErrors command to controller to reset errors 1-reset +//30002 SchemeAssemble Command to change scheme state 0-scheme dissasemble 1- assemble +//30003 IsPowerSetMode 0-control enigine by turnovers, 1- by power +//30004 SpecifiedPower Power set by user +//30005 SpecifiedTurnovers Turnovers set by user + +//30006 UserValueUpdated command to controller to update set value 1-ative + +//30007 ReportGet Command to get report 1-get 0- nothinhg +//30008 ReportArraySaved Sets to 1 when HMI is ready to get array(part of report) +//30009 PumpsControlMode Pumps Control mode. 0 = auto, 1= pump 1, 2= pump 2 + +//30010 MotoHoursPanel () +//30011 MotoHoursFan1 1 () +//30012 MotoHoursFan2 2 () +//30013 MotoHoursPump1 () +//30014 MotoHoursPump2 () +//30015 MotoHoursInvertorCharged "" "" () +//30016 MotoHoursInvertorGo """" () +//30017 MotoHoursInvertorGoFault "" "" () +//30018 MotoHoursInvertorAlarm """" () + +#define COUNT_ANALOG_DATA_FROM_INGETEAM SIZE_ANALOG_DATA_REMOUTE //(18+1) +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +void func_unpack_answer_from_Ingeteam(unsigned int cc) +{ + // y + unsigned int DataOut; + int Data, Data1, Data2, DataAnalog1, DataAnalog2, DataAnalog3, DataAnalog4, i; + unsigned int h; + volatile unsigned char *pByte; + // static int vs11,vs12,vs1; + // static int DataCnt=0; + // int GoT,Assemble_scheme; + // static int prev_temp_Rele1=0, temp_Rele1=0, prev_temp_Rele2=0, temp_Rele2=0; + + static int flag_prev_turn_on = 0; + static int flag_prev_turn_off = 0; + static int prev_byte01_bit4 = 0; + static int prev_byte01_bit1 = 0; + static int flag_wait_revers_sbor = 1; + static int flag_wait_revers_go = 1; + + static unsigned int count_transmited = 0; + + + // y + // + + if (COUNT_ANALOG_DATA_FROM_INGETEAM > CONTROL_STATION_MAX_RAW_DATA) + xerror(main_er_ID(2),(void *)0); + + for (h=1;h=0 && prev_send_log != edrk.pult_cmd.send_log) + { + if (edrk.pult_cmd.send_log) + log_to_HMI.send_log = edrk.pult_cmd.send_log; + + log_to_HMI.sdusb = edrk.pult_cmd.sdusb; + + } +// else +// log_to_HMI.send_log = 0; + + prev_send_log = edrk.pult_cmd.send_log; + + ///////////////// + ///////////////// + ///////////////// + + control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MODE_PUMP] = edrk.pult_cmd.pump_mode; + + +// +// control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_PUMP] = modbus_table_analog_in[188].all; +// control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_QTV] = modbus_table_analog_in[189].all; +// control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_DISABLE_ON_UMP] = modbus_table_analog_in[190].all; +// control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_ENABLE_ON_CHARGE] = modbus_table_analog_in[191].all; +// control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_MANUAL_DISCHARGE] = modbus_table_analog_in[180].all; +// control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_GO] = !modbus_table_analog_in[192].all; +// +// control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_] = modbus_table_analog_in[188].all; + + ///////////////// + ///////////////// + ///////////////// + ///////////////// + + parse_protect_levels_HMI(); + +} + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// + +int update_progress_load_hmi(int proc_load) +{ + static unsigned int old_time_5 = 0; + volatile int perc_load=0, final_code = 0, c_l = 0; + +// return 0; + + update_tables_HMI_on_inited(proc_load); + + + old_time_5 = global_time.miliseconds; + do + { + + if (final_code >= 4) + { + return 1; + } + +// if (control_station.flag_waiting_answer[CONTROL_STATION_INGETEAM_PULT_RS485]==0) +// final_code = modbusNetworkSharing(0); +// else + final_code = modbusNetworkSharing(1); + +// RS232_WorkingWith(0,1,0); + + } + while (detect_pause_milisec(1500, &old_time_5)==0);//(100,&old_time)); + + return 0; + + + +} + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// + + +void update_tables_HMI_on_inited(int perc_load) +{ + Inverter_state state; + static int nn=0, ss=0; + static int prev_edrk_KVITIR=0; + int i,status; + +// log_to_HMI.send_log = modbus_table_analog_in[7].all; + //setRegisterDiscreteOutput(log_to_HMI.flag_log_array_ready_sent, 310); + + // LoadMode Read 00544 00544 + setRegisterDiscreteOutput(0, 544);// + + // Loading ReadWrite 30088 40088 0-10 + modbus_table_analog_out[88].all = perc_load; + + // + modbus_table_analog_out[4].all++; + + + // build version + modbus_table_analog_out[219].all = edrk.buildYear; + modbus_table_analog_out[220].all = edrk.buildMonth; + modbus_table_analog_out[221].all = edrk.buildDay; + + +} + +/////////////////////////////////////////////////// +/// +/////////////////////////////////////////////////// +void update_tables_HMI_discrete(void) +{ + int real_box; + // !!! + // if (edrk.from_display.bits.KVITIR) + // setRegisterDiscreteOutput(edrk.from_display.bits.KVITIR, 301); + setRegisterDiscreteOutput(control_station.array_cmd[CONTROL_STATION_INGETEAM_PULT_RS485][CONTROL_STATION_CMD_CHECKBACK], 513); + // prev_edrk_KVITIR = edrk.from_display.bits.KVITIR; + ///// + + //setRegisterDiscreteOutput(edrk.RemouteFromDISPLAY, 302); + setRegisterDiscreteOutput(control_station.active_control_station[CONTROL_STATION_INGETEAM_PULT_RS485], 514); + + setRegisterDiscreteOutput(hmi_watch_dog, 515); + + + setRegisterDiscreteOutput(edrk.StatusFunAll, 516); + setRegisterDiscreteOutput(edrk.StatusFunAll, 517); + + setRegisterDiscreteOutput(edrk.StatusPump0, 518); + setRegisterDiscreteOutput(edrk.StatusPump1, 519); + + setRegisterDiscreteOutput(edrk.from_shema_filter.bits.SVU,524); + setRegisterDiscreteOutput(edrk.from_shema_filter.bits.ZADA_DISPLAY,525); + // ___ Read 00523 + // ___ Read 00524 + // __ Read 00525 + + + setRegisterDiscreteOutput(edrk.from_ing1.bits.OHLAD_UTE4KA_WATER, 526);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.NASOS_NORMA, 527);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.OP_PIT_NORMA, 528);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.UPC_24V_NORMA, 529);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.ALL_KNOPKA_AVARIA, 530);// + setRegisterDiscreteOutput(edrk.SumSbor, 531);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.ZARYAD_ON, 532);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.VIPR_PREDOHR_NORMA, 533);// + setRegisterDiscreteOutput(!edrk.temper_limit_koeffs.code_status, 534);// + // setRegisterDiscreteOutput(1, 331);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.ZAZEML_ON, 535);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.NAGREV_ON, 536);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.BLOCK_IZOL_NORMA, 537);// + setRegisterDiscreteOutput(edrk.from_ing1.bits.BLOCK_IZOL_AVARIA, 538);// + + ////////////// + // schemeStateOnController ReadWrite 00539 00539 0 - , 1- + // StateAnotherPowerChannel Read 00540 00540 : 0 - , 1 + // InterfaceOpticalBus Read 00541 00541 : 0 - , 1 - + // StateDriver Read 00542 00542 : 0 - , 1 - + // NumberPowerChannel Read 00543 00543 : 0 - , 1 - + + + setRegisterDiscreteOutput(edrk.Status_Ready.bits.ready_final, 539); + setRegisterDiscreteOutput(edrk.errors.e7.bits.ANOTHER_BS_ALARM, 540); + setRegisterDiscreteOutput(optical_read_data.status == 1 && optical_write_data.status == 1 ? 1 : 0, 541); + setRegisterDiscreteOutput(edrk.Status_Rascepitel_Ok, 542); + + if (edrk.flag_second_PCH==0) + setRegisterDiscreteOutput(0, 543); + else + setRegisterDiscreteOutput(1, 543); + + // LoadMode Read 00544 00544 + setRegisterDiscreteOutput(1, 544); // + + // Loading ReadWrite 30088 40088 0-10 + + setRegisterDiscreteOutput(control_station.active_array_cmd[CONTROL_STATION_CMD_BLOCK_BS] + || edrk.from_shema.bits.SVU_BLOCK_QTV, 545); + ////////////// + + + + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_ack, 17);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_ack, 18);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_ack, 19);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_ack, 20);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_ack, 21);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_ack, 22);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_ack, 23);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_ack, 24);// + + setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_ack, 25);// + setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_ack, 26);// + ///////////////////// + if (edrk.flag_second_PCH==0) + setRegisterDiscreteOutput(edrk.errors.e4.bits.ANOTHER_BS_POWER_OFF, 27); + else + setRegisterDiscreteOutput(edrk.errors.e4.bits.ANOTHER_BS_POWER_OFF, 28); + + + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_current, 33);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_current, 34);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_current, 35);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_current, 36);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_current, 37);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_current, 38);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_current, 39);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_current, 40);// + + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_current, 41);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_current, 42);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_current, 43);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_current, 44);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_current, 45);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_current, 46);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_current, 47);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_current, 48);// + + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_current, 49);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_current, 50);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_current, 51);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_current, 52);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_current, 53);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_current, 54);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_current, 55);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_current, 56);// + + setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_current, 57);// + setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_current, 58);// + ////////////////////////// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 65);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 66);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 67);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 68);// + + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 69);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 70);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 71);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 72);// + + + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 73);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 74);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 75);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 76);// + + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 77);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 78);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 79);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 80);// + + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 81);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 82);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 83);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 84);// + + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 85);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 86);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 87);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654, 88);// + + setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 89);// + setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.lock_status_error.bit.mintime_err_keys_3210, 90);// + + ///////////////// + + + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_TK_0, 97);// + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_TK_1, 98);// + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_TK_2, 99);// + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_TK_3, 100);// + + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_IN_0, 101);// + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_IN_1, 102);// + + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_OUT_0, 103);// + // setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_OUT_1, 105);// + + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_ADC_0, 104);// + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_HWP_0, 105);// + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_ADC_1, 106);// + + setRegisterDiscreteOutput(edrk.errors.e3.bits.NOT_READY_CONTR, 107);// + + + /////////////////// + + + setRegisterDiscreteOutput(edrk.errors.e5.bits.KEY_AVARIA, 113);// + + setRegisterDiscreteOutput(edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER, 114); + setRegisterDiscreteOutput(edrk.errors.e7.bits.SVU_BLOCK_ON_QTV + || control_station.active_array_cmd[CONTROL_STATION_CMD_BLOCK_BS], 115); + setRegisterDiscreteOutput(edrk.errors.e7.bits.UMP_NOT_ANSWER, 116); + setRegisterDiscreteOutput(edrk.errors.e7.bits.UMP_NOT_READY, 117); + setRegisterDiscreteOutput(edrk.errors.e6.bits.RASCEPITEL_ERROR_NOT_ANSWER, 118); + setRegisterDiscreteOutput(edrk.errors.e7.bits.ANOTHER_RASCEPITEL_ON, 119); + + setRegisterDiscreteOutput(edrk.errors.e7.bits.AUTO_SET_MASTER, 120); + setRegisterDiscreteOutput(edrk.errors.e7.bits.ANOTHER_PCH_NOT_ANSWER, 121); + setRegisterDiscreteOutput(edrk.errors.e8.bits.WDOG_OPTICAL_BUS, 122); + setRegisterDiscreteOutput(edrk.errors.e2.bits.ERROR_RAZBOR_SHEMA, 123); + + setRegisterDiscreteOutput(edrk.errors.e1.bits.NO_CONFIRM_ON_RASCEPITEL, 124); + + setRegisterDiscreteOutput(edrk.errors.e1.bits.ANOTHER_BS_NOT_ON_RASCEPITEL, 125); + setRegisterDiscreteOutput(edrk.errors.e1.bits.ANOTHER_BS_VERY_LONG_WAIT, 126); + setRegisterDiscreteOutput(edrk.errors.e1.bits.VERY_LONG_BOTH_READY2, 127); + setRegisterDiscreteOutput(edrk.errors.e1.bits.BOTH_KEYS_CHARGE_DISCHARGE, 128); + + // setRegisterDiscreteOutput(edrk.errors.e5.bits.OP_PIT, 115);// + // setRegisterDiscreteOutput(edrk.errors.e5.bits.POWER_UPC, 116);// + /////////////////// + + setRegisterDiscreteOutput(!control_station.alive_control_station[CONTROL_STATION_ZADATCHIK_CAN], 129); + setRegisterDiscreteOutput(!control_station.alive_control_station[CONTROL_STATION_MPU_SVU_CAN], 130); + // setRegisterDiscreteOutput(CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,UMU_CAN_DEVICE)], 131); + real_box = get_real_in_mbox(UNITS_TYPE_BOX,BKSSD_CAN_DEVICE); + if (real_box != -1) + setRegisterDiscreteOutput(CAN_timeout[real_box], 132); + + real_box = get_real_in_mbox(UNITS_TYPE_BOX,VPU_CAN); + if (real_box != -1) + setRegisterDiscreteOutput(CAN_timeout[real_box], 133); + real_box = get_real_in_mbox(UNITS_TYPE_BOX,ANOTHER_BSU1_CAN_DEVICE); + if (real_box != -1) + setRegisterDiscreteOutput(CAN_timeout[real_box], 134); + setRegisterDiscreteOutput(edrk.errors.e7.bits.CAN2CAN_BS, 135); + + + if (edrk.flag_second_PCH==0) + setRegisterDiscreteOutput(edrk.warnings.e4.bits.ANOTHER_BS_POWER_OFF, 137); + else + setRegisterDiscreteOutput(edrk.warnings.e4.bits.ANOTHER_BS_POWER_OFF, 136); + + setRegisterDiscreteOutput(edrk.errors.e7.bits.ANOTHER_BS_ALARM, 138); // ; edrk.errors.e4.bits.FAST_OPTICAL_ALARM + setRegisterDiscreteOutput(edrk.warnings.e7.bits.ANOTHER_BS_ALARM, 139);// ; edrk.warnings.e4.bits.FAST_OPTICAL_ALARM + + setRegisterDiscreteOutput(edrk.warnings.e7.bits.UMP_NOT_READY, 140); + + setRegisterDiscreteOutput(edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK, 141); + setRegisterDiscreteOutput(edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK, 142); + + setRegisterDiscreteOutput(edrk.errors.e9.bits.SENSOR_ROTOR_1_2_BREAK, 143); + + + + /// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_ack, 145);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_ack, 146);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_ack, 147);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_ack, 148);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_ack, 149);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_ack, 150);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_ack, 151);// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_ack, 152);// + + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_ack, 153);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_ack, 154);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_ack, 155);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_ack, 156);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_ack, 157);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_ack, 158);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_ack, 159);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_ack, 160);// + + + + + // setRegisterDiscreteOutput(edrk.errors.e5.bits.KEY_AVARIA, 243);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.OP_PIT, 161);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.UTE4KA_WATER, 162);// + setRegisterDiscreteOutput(edrk.errors.e1.bits.BLOCK_DOOR, 163);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_PRE_CHARGE_ON, 164);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.FAN, 165);// + + setRegisterDiscreteOutput(edrk.errors.e5.bits.PUMP_1, 166);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.PRE_READY_PUMP, 167);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_HEAT, 168);// + + setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_PRED_VIPR, 170);// + + setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_ISOLATE, 171);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.POWER_UPC, 172);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_GROUND_NET, 173);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.PUMP_2, 174);// + setRegisterDiscreteOutput(edrk.warnings.e5.bits.ERROR_ISOLATE, 175);// + setRegisterDiscreteOutput(edrk.warnings.e5.bits.PRE_READY_PUMP, 176);// + + + /////////////////// + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_1_MAX, 177);// + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_2_MAX, 178);// + + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_1_MIN, 179);// + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_2_MIN, 180);// + + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_A1B1_MAX, 181);// + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_A2B2_MAX, 182);// + + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_B1C1_MAX, 183);// + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_B2C2_MAX, 184);// + + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_A1B1_MIN, 185);// + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_A2B2_MIN, 186);// + + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_B1C1_MIN, 187);// + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_B2C2_MIN, 188);// + + + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_IN_MAX, 189);// + setRegisterDiscreteOutput(edrk.errors.e0.bits.U_IN_MIN, 190);// + + // setRegisterDiscreteOutput(edrk.errors.e0.bits.I_1_MAX, 191);// + // setRegisterDiscreteOutput(edrk.errors.e0.bits.I_2_MAX, 192);// + + + ////////////// + + setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO2_MAX, 193);// + setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO3_MAX, 194);// + setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO4_MAX, 195);// + setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO5_MAX, 196);// + setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO6_MAX, 197);// + setRegisterDiscreteOutput(edrk.errors.e1.bits.I_UO7_MAX, 198);// + + setRegisterDiscreteOutput(edrk.errors.e1.bits.I_BREAK_1_MAX, 199);// + setRegisterDiscreteOutput(edrk.errors.e1.bits.I_BREAK_2_MAX, 200);// + + // setRegisterDiscreteOutput(edrk.errors.e1.bits.HWP_ERROR, 201);// + //////////////////// + + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_AIR0_MAX, 203);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_AIR1_MAX, 204);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_AIR2_MAX, 205);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_AIR3_MAX, 206);// + + setRegisterDiscreteOutput(edrk.power_limit.bits.limit_by_temper, 207);// + setRegisterDiscreteOutput(edrk.power_limit.bits.limit_from_freq, 211);// + setRegisterDiscreteOutput(edrk.power_limit.bits.limit_from_uom_fast, 212);// + setRegisterDiscreteOutput(edrk.power_limit.bits.limit_from_SVU, 213);// + setRegisterDiscreteOutput(edrk.power_limit.bits.limit_moment, 214);// + setRegisterDiscreteOutput(edrk.power_limit.bits.limit_Iout, 216);// + + //////////////////// + setRegisterDiscreteOutput(edrk.errors.e5.bits.ERROR_PRE_CHARGE_ON, 209);// + setRegisterDiscreteOutput(edrk.errors.e7.bits.ERROR_SBOR_SHEMA, 210);// + + ///////////////////// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch0, 225);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch1, 226);// + + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch2, 227);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch3, 228);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch4, 229);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch5, 230);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch6, 231);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch7, 232);// + + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch8, 234);// + + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch10, 235);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch11, 236);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch12, 237);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch13, 238);// + + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch14, 239);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.plus.bit.ch15, 240);// + + + //////////////////// + setRegisterDiscreteOutput(edrk.errors.e5.bits.LINE_ERR0, 241);// + setRegisterDiscreteOutput(edrk.errors.e5.bits.LINE_HWP, 242);// + //////////////////// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch2, 243);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch3, 244);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch4, 245);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch5, 246);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch6, 247);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch7, 248);// + + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch8, 250);// + + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch10, 251);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch11, 252);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch12, 253);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch13, 254);// + + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch14, 255);// + setRegisterDiscreteOutput(project.hwp[0].read.comp_s.minus.bit.ch15, 256);// + + + + //////////////////// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_INPUT_A1B1, 257);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_INPUT_B1C1, 258);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_INPUT_A2B2, 259);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_INPUT_B2C2, 260);// + + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOW_FREQ_50HZ, 261);// + setRegisterDiscreteOutput(edrk.warnings.e8.bits.LOW_FREQ_50HZ, 262);// + + setRegisterDiscreteOutput(edrk.errors.e7.bits.READ_OPTBUS || edrk.errors.e7.bits.WRITE_OPTBUS, 263);// + setRegisterDiscreteOutput(edrk.errors.e7.bits.MASTER_SLAVE_SYNC, 264); // + + setRegisterDiscreteOutput(edrk.errors.e6.bits.ERR_SBUS, 265);// + setRegisterDiscreteOutput(edrk.errors.e6.bits.ERR_PBUS, 266);// + + setRegisterDiscreteOutput(edrk.errors.e6.bits.ER_DISBAL_BATT, 267);// + + setRegisterDiscreteOutput(edrk.errors.e6.bits.QTV_ERROR_NOT_U, 268);// + setRegisterDiscreteOutput(edrk.errors.e6.bits.ERROR_PRE_CHARGE_U, 269);// + + setRegisterDiscreteOutput(edrk.errors.e8.bits.U_IN_20_PROCENTS_HIGH, 270);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.U_IN_10_PROCENTS_LOW, 271);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.U_IN_20_PROCENTS_LOW, 272);// + + + //////////////// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.err_power, 273);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.err_power, 274);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.err_power, 275);// + setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.lock_status_error.bit.err_power, 276);// + setRegisterDiscreteOutput(project.cds_in[0].read.sbus.lock_status_error.bit.err_power, 277);// + setRegisterDiscreteOutput(project.cds_in[1].read.sbus.lock_status_error.bit.err_power, 278);// + setRegisterDiscreteOutput(project.cds_out[0].read.sbus.lock_status_error.bit.err_power, 279);// + + + setRegisterDiscreteOutput(edrk.errors.e7.bits.NOT_VALID_CONTROL_STATION, 280);// + + //////////////// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_U1, 281);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_V1, 282);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_W1, 283);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_U2, 284);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_V2, 285);// + setRegisterDiscreteOutput(edrk.errors.e8.bits.LOSS_OUTPUT_W2, 286);// + + setRegisterDiscreteOutput(edrk.errors.e8.bits.DISBALANCE_IM1_IM2, 287);// + setRegisterDiscreteOutput(edrk.errors.e7.bits.VERY_FAST_GO_0to1, 288);// + + //////////////// + setRegisterDiscreteOutput(project.cds_tk[0].read.sbus.lock_status_error.bit.err_switch, 289);// + setRegisterDiscreteOutput(project.cds_tk[1].read.sbus.lock_status_error.bit.err_switch, 290);// + setRegisterDiscreteOutput(project.cds_tk[2].read.sbus.lock_status_error.bit.err_switch, 291);// + setRegisterDiscreteOutput(project.cds_tk[3].read.sbus.lock_status_error.bit.err_switch, 292);// + setRegisterDiscreteOutput(project.cds_in[0].read.sbus.lock_status_error.bit.err_switch, 293);// + setRegisterDiscreteOutput(project.cds_in[1].read.sbus.lock_status_error.bit.err_switch, 294);// + setRegisterDiscreteOutput(project.cds_out[0].read.sbus.lock_status_error.bit.err_switch, 295);// + + setRegisterDiscreteOutput(project.adc[0].read.sbus.lock_status_error.bit.err_switch, 296);// + setRegisterDiscreteOutput(project.adc[1].read.sbus.lock_status_error.bit.err_switch, 298);// + + //////////////// + + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO1_MAX, 305);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO2_MAX, 306);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO3_MAX, 307);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO4_MAX, 308);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO5_MAX, 309);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO6_MAX, 310);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_UO7_MAX, 311);// + + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO1_MAX, 312);// + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO2_MAX, 313);// + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO3_MAX, 314);// + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO4_MAX, 315);// + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO5_MAX, 316);// + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO6_MAX, 317);// + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_UO7_MAX, 318);// + + + + + ///////////////////// + + setRegisterDiscreteOutput(edrk.warnings.e7.bits.READ_OPTBUS || edrk.warnings.e7.bits.WRITE_OPTBUS, 321);// + setRegisterDiscreteOutput(edrk.warnings.e7.bits.MASTER_SLAVE_SYNC, 322);// + + setRegisterDiscreteOutput(edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER, 323);// + + setRegisterDiscreteOutput(edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL, 324);// + setRegisterDiscreteOutput(edrk.errors.e1.bits.NO_INPUT_SYNC_SIGNAL, 325);// + setRegisterDiscreteOutput(edrk.errors.e3.bits.ERR_INT_PWM_LONG + || edrk.errors.e9.bits.ERR_PWM_WDOG + || edrk.errors.e9.bits.ERR_INT_PWM_VERY_LONG, 326);// + + setRegisterDiscreteOutput(edrk.errors.e5.bits.T_VIPR_MAX, 336); + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_AIR0_MAX, 337); + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_AIR1_MAX, 338); + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_AIR2_MAX, 339); + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_AIR3_MAX, 340); + setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_BSU_Sensor_BK1, 341); + setRegisterDiscreteOutput(edrk.errors.e10.bits.T_BSU_Sensor_BK1, 342); + setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_BSU_Sensor_BK2, 343); + setRegisterDiscreteOutput(edrk.errors.e10.bits.T_BSU_Sensor_BK2, 344); + ////// + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_WATER_EXT_MAX, 345);// + setRegisterDiscreteOutput(edrk.errors.e2.bits.T_WATER_INT_MAX, 346);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_WATER_EXT_MAX, 347);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.T_WATER_INT_MAX, 348);// + + setRegisterDiscreteOutput(edrk.errors.e7.bits.T_ACDRIVE_BEAR_MAX_DNE, 349);// + setRegisterDiscreteOutput(edrk.errors.e9.bits.T_ACDRIVE_BEAR_MAX_NE, 350);// + setRegisterDiscreteOutput(edrk.warnings.e7.bits.T_ACDRIVE_BEAR_MAX_DNE, 351);// + setRegisterDiscreteOutput(edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE, 352);// + + ////////////// + + setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1, 353);// + setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_V1, 354);// + setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_W1, 355);// + setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_U2, 356);// + setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_V2, 357);// + setRegisterDiscreteOutput(edrk.errors.e10.bits.T_ACDRIVE_WINDING_W2, 358);// + + setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1, 359);// + setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1, 360);// + setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1, 361);// + setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2, 362);// + setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2, 363);// + setRegisterDiscreteOutput(edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2, 364);// + + //////////////////// + + setRegisterDiscreteOutput(edrk.errors.e2.bits.P_WATER_INT_MAX, 369);// + setRegisterDiscreteOutput(edrk.errors.e2.bits.P_WATER_INT_MIN, 370);// + + setRegisterDiscreteOutput(edrk.warnings.e2.bits.P_WATER_INT_MAX, 371);// + setRegisterDiscreteOutput(edrk.warnings.e2.bits.P_WATER_INT_MIN, 372);// + setRegisterDiscreteOutput(edrk.warnings.e5.bits.PUMP_1, 373);// + setRegisterDiscreteOutput(edrk.warnings.e5.bits.PUMP_2, 374);// + + + + //// + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_PUMP_ON_SBOR, 385); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_RESTART_PUMP_1_ON_SBOR, 386); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_RESTART_PUMP_2_ON_SBOR, 387); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_RESTART_PUMP_ALL_ON_SBOR, 388); + + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_PRED_ZARYAD, 389); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_PRED_ZARYAD_AFTER, 390); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_READY_UMP_BEFORE_QTV, 391); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_STATUS_QTV, 392); + + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_UMP_ON_AFTER, 393); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_UMP_NOT_ON, 394); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_UMP_NOT_OFF, 395); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_RASCEPITEL_WAIT_CMD, 396); + + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_RASCEPITEL_ON_AFTER, 397); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_DISABLE_SBOR, 398); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_VERY_LONG_SBOR, 399); + setRegisterDiscreteOutput(edrk.errors.e11.bits.ERROR_CONTROLLER_BUS, 400); + + setRegisterDiscreteOutput(edrk.warnings.e9.bits.BREAK_TEMPER_WARNING, 417);// + setRegisterDiscreteOutput(edrk.warnings.e9.bits.BREAK_TEMPER_ALARM, 418);// + setRegisterDiscreteOutput(edrk.warnings.e9.bits.BREAKER_GED_ON, 419);// + + ////////////////// + + + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER || + edrk.Mode_ScalarVectorUFConst == ALG_MODE_SCALAR_POWER) { + setRegisterDiscreteOutput(1, 520); + } else { + setRegisterDiscreteOutput(0, 520); + } + // setRegisterDiscreteOutput(TODO , 546);// + setRegisterDiscreteOutput(!edrk.from_ing1.bits.UPC_24V_NORMA, 546);// + setRegisterDiscreteOutput(edrk.from_ing2.bits.SOST_ZAMKA, 547);// + setRegisterDiscreteOutput(edrk.from_shema_filter.bits.READY_UMP, 548);// + + + //////////////// + + +} + + + +void update_tables_HMI_analog(void) +{ + int power_kw_full; + int power_kw; + int oborots; + + Inverter_state state; + static int nn=0, ss=0, pl = 0; +// static int prev_edrk_KVITIR=0; + int i,status; +// static int check = 0; + + hmi_watch_dog = !hmi_watch_dog; //was transmitted, need to change + + //log_to_HMI.send_log = modbus_table_analog_in[7].all; + //setRegisterDiscreteOutput(log_to_HMI.flag_log_array_ready_sent, 310); + +// setRegisterDiscreteOutput(ss, nn); + + // + modbus_table_analog_out[4].all++;// = ++check; +// test +// setRegisterDiscreteOutput(1, 293); +// setRegisterDiscreteOutput(1, 294); + + + + + + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + + if (edrk.summ_errors) + { + modbus_table_analog_out[1].all = 6; // + modbus_table_analog_out[2].all = 3; // red + } + else + { + + if (edrk.SumSbor || edrk.Status_Ready.bits.ImitationReady2) + { + if (edrk.Status_Ready.bits.ready_final) + { + //modbus_table_analog_out[2].all = 1; // green + if (edrk.Go) + { + modbus_table_analog_out[1].all = 3; // + if (edrk.Provorot) + modbus_table_analog_out[1].all = 12; // = 11 + + } + else + modbus_table_analog_out[1].all = 2; // ready2 + } + else + modbus_table_analog_out[1].all = 4; // building + } + else + { + if (edrk.Status_Ready.bits.ready1) + modbus_table_analog_out[1].all = 1; // ready1 + else + modbus_table_analog_out[1].all = 0; // waiting + } + + if (edrk.RazborNotFinish) + modbus_table_analog_out[1].all = 11; // + + if (edrk.Status_Perehod_Rascepitel==1 && edrk.cmd_to_rascepitel==1) + modbus_table_analog_out[1].all = 7; // + + if (edrk.Status_Perehod_Rascepitel==1 && edrk.cmd_to_rascepitel==0) + modbus_table_analog_out[1].all = 8; // + + if (edrk.RunZahvatRascepitel) + modbus_table_analog_out[1].all = 9; // = 9 + if (edrk.RunUnZahvatRascepitel) + modbus_table_analog_out[1].all = 10; // = 10 + + // + //modbus_table_analog_out[1].all = 5; // + + if (modbus_table_analog_out[1].all == 1) + modbus_table_analog_out[2].all = 0; // gray + else + if (modbus_table_analog_out[1].all == 3 || + modbus_table_analog_out[1].all == 12 || + modbus_table_analog_out[1].all == 2) + modbus_table_analog_out[2].all = 1; // green + else + { + if (modbus_table_analog_out[2].all==0) + modbus_table_analog_out[2].all = 1; // green + else + modbus_table_analog_out[2].all = 0; // gray + } + + } + + + + + if (edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER || edrk.errors.e6.bits.QTV_ERROR_NOT_U) + { + modbus_table_analog_out[10].all = 3; + modbus_table_analog_out[11].all = 3; + } + else + { + if (edrk.from_shema_filter.bits.QTV_ON_OFF) + { + modbus_table_analog_out[10].all = 1; + modbus_table_analog_out[11].all = 1; + } + else + { + modbus_table_analog_out[10].all = 0; + modbus_table_analog_out[11].all = 0; + } + } + + + if (edrk.from_ing1.bits.VIPR_PREDOHR_NORMA==1) + { + if (edrk.from_shema_filter.bits.QTV_ON_OFF==1) + modbus_table_analog_out[12].all = 1; + else + modbus_table_analog_out[12].all = 0; + } + else + modbus_table_analog_out[12].all = 3; + + + if (edrk.errors.e6.bits.UO1_KEYS || edrk.errors.e1.bits.I_BREAK_1_MAX || edrk.errors.e1.bits.I_BREAK_2_MAX || edrk.errors.e2.bits.T_UO1_MAX) + modbus_table_analog_out[13].all = 3; + else + if (edrk.warnings.e2.bits.T_UO1_MAX) + modbus_table_analog_out[13].all = 2; + else + modbus_table_analog_out[13].all = 1; + + if (edrk.errors.e6.bits.UO2_KEYS || edrk.errors.e1.bits.I_UO2_MAX || edrk.errors.e2.bits.T_UO2_MAX) + modbus_table_analog_out[14].all = 3; + else + if (edrk.warnings.e2.bits.T_UO2_MAX) + modbus_table_analog_out[14].all = 2; + else + modbus_table_analog_out[14].all = 1; + + if (edrk.errors.e6.bits.UO3_KEYS || edrk.errors.e1.bits.I_UO3_MAX || edrk.errors.e2.bits.T_UO3_MAX) + modbus_table_analog_out[15].all = 3; + else + if (edrk.warnings.e2.bits.T_UO3_MAX) + modbus_table_analog_out[15].all = 2; + else + modbus_table_analog_out[15].all = 1; + + if (edrk.errors.e6.bits.UO4_KEYS || edrk.errors.e1.bits.I_UO4_MAX || edrk.errors.e2.bits.T_UO4_MAX) + modbus_table_analog_out[16].all = 3; + else + if (edrk.warnings.e2.bits.T_UO4_MAX) + modbus_table_analog_out[16].all = 2; + else + modbus_table_analog_out[16].all = 1; + + if (edrk.errors.e6.bits.UO5_KEYS || edrk.errors.e1.bits.I_UO5_MAX || edrk.errors.e2.bits.T_UO5_MAX) + modbus_table_analog_out[17].all = 3; + else + if (edrk.warnings.e2.bits.T_UO5_MAX) + modbus_table_analog_out[17].all = 2; + else + modbus_table_analog_out[17].all = 1; + + if (edrk.errors.e6.bits.UO6_KEYS || edrk.errors.e1.bits.I_UO6_MAX || edrk.errors.e2.bits.T_UO6_MAX) + modbus_table_analog_out[18].all = 3; + else + if (edrk.warnings.e2.bits.T_UO6_MAX) + modbus_table_analog_out[18].all = 2; + else + modbus_table_analog_out[18].all = 1; + + if (edrk.errors.e6.bits.UO7_KEYS || edrk.errors.e1.bits.I_UO7_MAX || edrk.errors.e2.bits.T_UO7_MAX) + modbus_table_analog_out[19].all = 3; + else + if (edrk.warnings.e2.bits.T_UO7_MAX) + modbus_table_analog_out[19].all = 2; + else + modbus_table_analog_out[19].all = 1; + + + // motor_state + if (edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_V1 || + edrk.errors.e10.bits.T_ACDRIVE_WINDING_W1 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_U2 || + edrk.errors.e10.bits.T_ACDRIVE_WINDING_V2 || edrk.errors.e10.bits.T_ACDRIVE_WINDING_W2 || + edrk.errors.e7.bits.T_ACDRIVE_BEAR_MAX_DNE || edrk.errors.e9.bits.T_ACDRIVE_BEAR_MAX_NE) { + modbus_table_analog_out[20].all = 3; + } else if (edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1 || + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2 || + edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2 || edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2 || + edrk.warnings.e7.bits.T_ACDRIVE_BEAR_MAX_DNE || edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE + || edrk.power_limit.all + ) { + modbus_table_analog_out[20].all = 2; + } else { + modbus_table_analog_out[20].all = 1; + } + + + // ump state + if (edrk.from_ing1.bits.ZARYAD_ON || edrk.from_shema_filter.bits.UMP_ON_OFF) + { + modbus_table_analog_out[21].all = 1; //green + } + else + { + if (edrk.errors.e7.bits.ERROR_SBOR_SHEMA || edrk.errors.e5.bits.ERROR_PRE_CHARGE_ON || + edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER || edrk.errors.e6.bits.ERROR_PRE_CHARGE_U || edrk.errors.e7.bits.UMP_NOT_READY) + modbus_table_analog_out[21].all = 3; // alarm + else + if (edrk.warnings.e7.bits.UMP_NOT_READY) + modbus_table_analog_out[21].all = 2; //fault + else + { + if (edrk.Stage_Sbor == STAGE_SBOR_STATUS_UMP_ON && edrk.SumSbor) + { + if (modbus_table_analog_out[21].all==0) + modbus_table_analog_out[21].all = 1; //green + else + modbus_table_analog_out[21].all = 0; //gray + } + else + modbus_table_analog_out[21].all = 0; + } + } + + + modbus_table_analog_out[30].all = fast_round_with_limiter(_IQtoF(filter.iqUin_m1)*NORMA_ACP/1.41, LIMITER_U_I_PULT); + modbus_table_analog_out[31].all = fast_round_with_limiter(_IQtoF(filter.iqUin_m2)*NORMA_ACP/1.41, LIMITER_U_I_PULT); + +// if (edrk.Status_Ready.bits.ready_final==0) +// { +// modbus_table_analog_out[32].all = edrk.Stage_Sbor; +// modbus_table_analog_out[33].all = edrk.Sbor_Mode;//_IQtoF(analog.iqIin_1)*NORMA_ACP; +// } +// else +// { + modbus_table_analog_out[32].all = fast_round_with_limiter(_IQtoF(analog.iqIin_1)*NORMA_ACP, LIMITER_U_I_PULT); + modbus_table_analog_out[33].all = fast_round_with_limiter(_IQtoF(analog.iqIin_2)*NORMA_ACP, LIMITER_U_I_PULT); +// } + + +// modbus_table_analog_out[34].all = _IQtoF(filter.iqU_1_long)*NORMA_ACP; + modbus_table_analog_out[35].all = fast_round_with_limiter(_IQtoF(filter.iqU_2_long)*NORMA_ACP, LIMITER_U_I_PULT); + modbus_table_analog_out[34].all = fast_round_with_limiter(_IQtoF(filter.iqU_1_long)*NORMA_ACP, LIMITER_U_I_PULT); + + modbus_table_analog_out[36].all = fast_round_with_limiter(_IQtoF(analog.iqIbreak_1+analog.iqIbreak_2)*NORMA_ACP, LIMITER_U_I_PULT);//Ibreak + + + +// modbus_table_analog_out[37].all = fast_round(_IQtoF(analog.iqIu_1_rms)*NORMA_ACP); +// modbus_table_analog_out[38].all = fast_round(_IQtoF(analog.iqIv_1_rms)*NORMA_ACP); +// modbus_table_analog_out[39].all = fast_round(_IQtoF(analog.iqIw_1_rms)*NORMA_ACP); +// +// modbus_table_analog_out[40].all = fast_round(_IQtoF(analog.iqIu_2_rms)*NORMA_ACP); +// modbus_table_analog_out[41].all = fast_round(_IQtoF(analog.iqIv_2_rms)*NORMA_ACP); +// modbus_table_analog_out[42].all = fast_round(_IQtoF(analog.iqIw_2_rms)*NORMA_ACP); + + modbus_table_analog_out[37].all = //fast_round(_IQtoF(filter.iqIm_1)*NORMA_ACP_RMS); + modbus_table_analog_out[38].all = //fast_round(_IQtoF(filter.iqIm_1)*NORMA_ACP_RMS); + modbus_table_analog_out[39].all = fast_round_with_limiter(_IQtoF(filter.iqIm_1)*NORMA_ACP_RMS, LIMITER_U_I_PULT); + + modbus_table_analog_out[40].all = //fast_round(_IQtoF(filter.iqIm_2)*NORMA_ACP_RMS); + modbus_table_analog_out[41].all = //fast_round(_IQtoF(filter.iqIm_2)*NORMA_ACP_RMS); + modbus_table_analog_out[42].all = fast_round_with_limiter(_IQtoF(filter.iqIm_2)*NORMA_ACP_RMS, LIMITER_U_I_PULT); + +// if (edrk.flag_second_PCH == 0) { +// modbus_table_analog_out[43].all = modbus_table_analog_out[44].all = fast_round(_IQtoF(filter.iqIm_1 + filter.iqIm_2)*NORMA_ACP_RMS); +// //modbus_table_analog_out[44].all = fast_round(_IQtoF(filter.iqIm_1 + filter.iqIm_2)*NORMA_ACP_RMS); +// } else { +// modbus_table_analog_out[43].all = modbus_table_analog_out[44].all = fast_round(_IQtoF(filter.iqIm_1 + filter.iqIm_2)*NORMA_ACP_RMS); +// //modbus_table_analog_out[44].all = fast_round(_IQtoF(filter.iqIm_1 + filter.iqIm_2)*NORMA_ACP_RMS); +// } + modbus_table_analog_out[43].all = modbus_table_analog_out[44].all = fast_round_with_limiter(_IQtoF(filter.iqIm_1 + filter.iqIm_2)*NORMA_ACP_RMS, LIMITER_U_I_PULT); + + modbus_table_analog_out[45].all = 0; //edrk.I_zad_vozbud_exp; + +// modbus_table_analog_out[4].all = control_station.active_array_cmd[CONTROL_STATION_CMD_SET_ROTOR]; +// modbus_table_analog_out[5].all = control_station.active_array_cmd[CONTROL_STATION_CMD_SET_POWER]; + + +//#if (_FLOOR6__) +// power_kw_full = edrk.power_kw_full; +// power_kw = edrk.power_kw; +// oborots = edrk.oborots; +// +// if (edrk.oborots) +// oborots = edrk.oborots; +// else +// oborots = edrk.zadanie.oborots_zad; +// +// +// if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_SCALAR_OBOROTS +// || (edrk.Mode_ScalarVectorUFConst==ALG_MODE_FOC_OBOROTS) +// || (edrk.Mode_ScalarVectorUFConst==ALG_MODE_UF_CONST) +// ) // oborots +// { +// power_kw_full = (edrk.zadanie.oborots_zad)*50; +// power_kw = (edrk.zadanie.oborots_zad)*25; +// } +// else +// { +// oborots = edrk.zadanie.power_zad/25; +//// modbus_table_analog_out[48].all = abs(edrk.zadanie.power_zad); +// } +// +// +// +// +// +//#else + power_kw_full = fast_round_with_limiter(edrk.power_kw_full, LIMITER_U_I_PULT); + power_kw = edrk.power_kw; + oborots = edrk.oborots; +//#endif + + + if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_UF_CONST) // UFCONST + { + modbus_table_analog_out[47].all = 0;//fast_round(edrk.zadanie.fzad*100.0); // + modbus_table_analog_out[46].all = 0; // + } + else + if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_SCALAR_OBOROTS) // scalar oborots + { + modbus_table_analog_out[47].all = edrk.zadanie.oborots_zad; // + + if (oborots>=0) + modbus_table_analog_out[46].all = power_kw_full; // + else + modbus_table_analog_out[46].all = -power_kw_full; // + + } + else + if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_SCALAR_POWER) // scalar power + { + modbus_table_analog_out[47].all = oborots; // + modbus_table_analog_out[46].all = edrk.zadanie.power_zad; // + + } + else + if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_FOC_OBOROTS) // foc oborots + { + modbus_table_analog_out[47].all = edrk.zadanie.oborots_zad; // + + if (oborots>=0) + modbus_table_analog_out[46].all = power_kw_full; // + else + modbus_table_analog_out[46].all = -power_kw_full; // + +// modbus_table_analog_out[46].all = 0; // + + } + else + if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_FOC_POWER) // foc power + { + modbus_table_analog_out[47].all = oborots; // + modbus_table_analog_out[46].all = edrk.zadanie.power_zad; // + + } + else + { + modbus_table_analog_out[46].all = 0;//-1; // + modbus_table_analog_out[47].all = 0;//-1; // + } + + + + + +//#if (_FLOOR6___) +// if (edrk.Mode_ScalarVectorUFConst==ALG_MODE_SCALAR_OBOROTS +// || (edrk.Mode_ScalarVectorUFConst==ALG_MODE_FOC_OBOROTS) +// || (edrk.Mode_ScalarVectorUFConst==ALG_MODE_UF_CONST) +// ) // oborots +// { +// // +// if (edrk.oborots == 0) +// { +// if (edrk.zadanie.oborots_zad>0) +// modbus_table_analog_out[49].all = edrk.zadanie.oborots_zad - 1; +// else if (edrk.zadanie.oborots_zad<0) +// modbus_table_analog_out[49].all = edrk.zadanie.oborots_zad + 1; +// else +// modbus_table_analog_out[49].all = 0; +// +// } +// else +// { +// modbus_table_analog_out[49].all = edrk.oborots; // +// } +// +// if (edrk.zadanie.oborots_zad<0) +// modbus_table_analog_out[48].all = -(edrk.zadanie.oborots_zad)*25; // +// else +// modbus_table_analog_out[48].all = (edrk.zadanie.oborots_zad)*25; // +// +// } +// else +// { +// modbus_table_analog_out[49].all = edrk.zadanie.power_zad/25; +// modbus_table_analog_out[48].all = abs(edrk.zadanie.power_zad); +// } +// +// modbus_table_analog_out[5].all = abs(power_kw*2);//power_kw_full; // +//#else + + modbus_table_analog_out[48].all = abs(power_kw); // + modbus_table_analog_out[49].all = oborots; // + modbus_table_analog_out[5].all = abs(power_kw_full); // + modbus_table_analog_out[6].all = fast_round(_IQtoF(edrk.zadanie.iq_limit_power_zad_rmp)*NORMA_ACP*NORMA_ACP/1000.0);//abs(power_kw_full); // +//#endif + + + // modbus_table_analog_out[48].all = fast_round(_IQtoF((filter.Power) * NORMA_ACP * NORMA_ACP) / 1000.0); // + + for (i=0;i<2;i++) + modbus_table_analog_out[50+i].all = fast_round_with_delta(modbus_table_analog_out[50+i].all, edrk.temper_edrk.real_int_temper_water[i]/10.0, 1); + + + modbus_table_analog_out[52].all = fast_round_with_delta(modbus_table_analog_out[52].all, edrk.p_water_edrk.filter_real_int_p_water[0]/10.0, 1); + + for (i=0;i<6;i++) + modbus_table_analog_out[53+i].all = fast_round_with_delta(modbus_table_analog_out[53+i].all, edrk.temper_edrk.real_int_temper_u[1+i]/10.0, 1); + + modbus_table_analog_out[59].all = fast_round_with_delta(modbus_table_analog_out[59].all, edrk.temper_edrk.real_int_temper_u[0]/10.0, 1); + + for (i=0;i<4;i++) + modbus_table_analog_out[60+i].all = fast_round_with_delta(modbus_table_analog_out[60+i].all, edrk.temper_edrk.real_int_temper_air[i]/10.0, 1); + + modbus_table_analog_out[8].all = fast_round_with_delta(modbus_table_analog_out[8].all, edrk.temper_edrk.max_real_int_temper_u/10.0, 1); + + if (edrk.errors.e2.bits.T_AIR0_MAX) + modbus_table_analog_out[64].all = 3; + else + if (edrk.warnings.e2.bits.T_AIR0_MAX) + modbus_table_analog_out[64].all = 2; + else + modbus_table_analog_out[64].all = 1; + + if (edrk.errors.e2.bits.T_AIR1_MAX) + modbus_table_analog_out[65].all = 3; + else + if (edrk.warnings.e2.bits.T_AIR1_MAX) + modbus_table_analog_out[65].all = 2; + else + modbus_table_analog_out[65].all = 1; + + if (edrk.errors.e2.bits.T_AIR2_MAX) + modbus_table_analog_out[66].all = 3; + else + if (edrk.warnings.e2.bits.T_AIR2_MAX) + modbus_table_analog_out[66].all = 2; + else + modbus_table_analog_out[66].all = 1; + + if (edrk.errors.e2.bits.T_AIR3_MAX) + modbus_table_analog_out[67].all = 3; + else + if (edrk.warnings.e2.bits.T_AIR3_MAX) + modbus_table_analog_out[67].all = 2; + else + modbus_table_analog_out[67].all = 1; + + + + if (edrk.auto_master_slave.local.bits.master) + modbus_table_analog_out[68].all = 0; // master salve + else + if (edrk.auto_master_slave.local.bits.slave) + modbus_table_analog_out[68].all = 1; // master salve + else + if (edrk.auto_master_slave.local.bits.try_master) + modbus_table_analog_out[68].all = 3; // master salve + else + if (edrk.errors.e7.bits.AUTO_SET_MASTER) + modbus_table_analog_out[68].all = 4; // master salve + else + modbus_table_analog_out[68].all = 2; // master salve + + for (i=0;i<6;i++) + modbus_table_analog_out[69+i].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[0+i]); + + modbus_table_analog_out[9].all = fast_round(edrk.temper_acdrive.winding.max_real_int_temper/10.0); + + modbus_table_analog_out[75].all = fast_round(edrk.temper_acdrive.bear.filter_real_temper[0]); + modbus_table_analog_out[76].all = fast_round(edrk.temper_acdrive.bear.filter_real_temper[1]); + + modbus_table_analog_out[23].all = fast_round(edrk.temper_acdrive.bear.max_real_int_temper/10.0); + + for (i=0;i<6;i++) + { + status = get_status_temper_acdrive_winding(i); + if (status==4) + modbus_table_analog_out[77+i].all = 3; + if (status==2) + modbus_table_analog_out[77+i].all = 2; + if (status==1) + modbus_table_analog_out[77+i].all = 1; + } + + for (i=0;i<2;i++) + { + status = get_status_temper_acdrive_bear(i); + if (status==4) + modbus_table_analog_out[83+i].all = 3; + if (status==2) + modbus_table_analog_out[83+i].all = 2; + if (status==1) + modbus_table_analog_out[83+i].all = 1; + } + + +//UOM + modbus_table_analog_out[85].all = edrk.from_uom.level_value; + + if (edrk.from_uom.ready==1) + { + if (edrk.from_uom.error) + modbus_table_analog_out[86].all = 1; // + else + { + if (edrk.from_uom.level_value==0) + modbus_table_analog_out[86].all = 2; // + else + { + if (edrk.power_limit.bits.limit_UOM || edrk.power_limit.bits.limit_from_uom_fast) + { + // - + if (modbus_table_analog_out[86].all==0) + modbus_table_analog_out[86].all = 3; // + else + modbus_table_analog_out[86].all = 0; //gray + } + else + modbus_table_analog_out[86].all = 3; + + //modbus_table_analog_out[86].all = 3; // + } + } + } + else + modbus_table_analog_out[86].all = 0; // + + +// active control station +// CONTROL_STATION_TERMINAL_RS232 = 0, - +// CONTROL_STATION_TERMINAL_CAN, - +// +// CONTROL_STATION_INGETEAM_PULT_RS485, - +// CONTROL_STATION_MPU_SVU_CAN, +// CONTROL_STATION_MPU_KEY_CAN, +// CONTROL_STATION_MPU_SVU_RS485, +// CONTROL_STATION_MPU_KEY_RS485, +// CONTROL_STATION_ZADATCHIK_CAN, +// CONTROL_STATION_VPU_CAN, + + modbus_table_analog_out[87].all = edrk.active_post_upravl; + + + // load procents + modbus_table_analog_out[88].all = 0; //error + + // 0- , , , - . [87]. + if (modbus_table_analog_out[87].all == 10) + modbus_table_analog_out[89].all = 3; //red + else + modbus_table_analog_out[89].all = 1; //no error + + ///////////////////////////// + ///////////////////////////// + if (edrk.warnings.e7.bits.READ_OPTBUS + && edrk.warnings.e7.bits.WRITE_OPTBUS + && edrk.warnings.e7.bits.MASTER_SLAVE_SYNC) + modbus_table_analog_out[90].all = 2; //warning + else + if (edrk.errors.e7.bits.READ_OPTBUS + || edrk.errors.e7.bits.WRITE_OPTBUS + || edrk.errors.e7.bits.MASTER_SLAVE_SYNC + || edrk.errors.e1.bits.NO_INPUT_SYNC_SIGNAL) + modbus_table_analog_out[90].all = 3; //error + else + if (edrk.warnings.e7.bits.READ_OPTBUS + || edrk.warnings.e7.bits.WRITE_OPTBUS + || edrk.warnings.e7.bits.MASTER_SLAVE_SYNC + || edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL) + modbus_table_analog_out[90].all = 5; //warning + else + if (edrk.ms.ready1==0) + modbus_table_analog_out[90].all = 1; //find + else + modbus_table_analog_out[90].all = 0; //ok + + modbus_table_analog_out[91].all = protect_levels.abnormal_temper_acdrive_winding_U1 / 10; + modbus_table_analog_out[92].all = protect_levels.abnormal_temper_acdrive_winding_V1 / 10; + modbus_table_analog_out[93].all = protect_levels.abnormal_temper_acdrive_winding_W1 / 10; + modbus_table_analog_out[94].all = protect_levels.abnormal_temper_acdrive_winding_U2 / 10; + modbus_table_analog_out[95].all = protect_levels.abnormal_temper_acdrive_winding_V2 / 10; + modbus_table_analog_out[96].all = protect_levels.abnormal_temper_acdrive_winding_W2 / 10; + modbus_table_analog_out[97].all = protect_levels.abnormal_temper_acdrive_bear_DNE / 10; + modbus_table_analog_out[98].all = protect_levels.abnormal_temper_acdrive_bear_NE / 10; + + modbus_table_analog_out[99].all = protect_levels.alarm_temper_acdrive_winding_U1 / 10; + modbus_table_analog_out[100].all = protect_levels.alarm_temper_acdrive_winding_V1 / 10; + modbus_table_analog_out[101].all = protect_levels.alarm_temper_acdrive_winding_W1 / 10; + modbus_table_analog_out[102].all = protect_levels.alarm_temper_acdrive_winding_U2 / 10; + modbus_table_analog_out[103].all = protect_levels.alarm_temper_acdrive_winding_V2 / 10; + modbus_table_analog_out[104].all = protect_levels.alarm_temper_acdrive_winding_W2 / 10; + modbus_table_analog_out[105].all = protect_levels.alarm_temper_acdrive_bear_DNE / 10; + modbus_table_analog_out[106].all = protect_levels.alarm_temper_acdrive_bear_NE / 10; + + modbus_table_analog_out[107].all = protect_levels.abnormal_temper_u_01 / 10; + modbus_table_analog_out[108].all = protect_levels.abnormal_temper_u_02 / 10; + modbus_table_analog_out[109].all = protect_levels.abnormal_temper_u_03 / 10; + modbus_table_analog_out[110].all = protect_levels.abnormal_temper_u_04 / 10; + modbus_table_analog_out[111].all = protect_levels.abnormal_temper_u_05 / 10; + modbus_table_analog_out[112].all = protect_levels.abnormal_temper_u_06 / 10; + modbus_table_analog_out[113].all = protect_levels.abnormal_temper_u_07 / 10; + modbus_table_analog_out[114].all = protect_levels.alarm_temper_u_01 / 10; + modbus_table_analog_out[115].all = protect_levels.alarm_temper_u_02 / 10; + modbus_table_analog_out[116].all = protect_levels.alarm_temper_u_03 / 10; + modbus_table_analog_out[117].all = protect_levels.alarm_temper_u_04 / 10; + modbus_table_analog_out[118].all = protect_levels.alarm_temper_u_05 / 10; + modbus_table_analog_out[119].all = protect_levels.alarm_temper_u_06 / 10; + modbus_table_analog_out[120].all = protect_levels.alarm_temper_u_07 / 10; + + modbus_table_analog_out[123].all = protect_levels.abnormal_temper_water_int / 10; + modbus_table_analog_out[124].all = protect_levels.abnormal_temper_water_ext / 10; + modbus_table_analog_out[125].all = protect_levels.alarm_p_water_min_int / 10; + modbus_table_analog_out[126].all = protect_levels.alarm_temper_water_int / 10; + modbus_table_analog_out[127].all = protect_levels.alarm_temper_water_ext / 10; + modbus_table_analog_out[128].all = protect_levels.alarm_p_water_max_int / 10; + + modbus_table_analog_out[129].all = protect_levels.abnormal_temper_air_int_01 / 10; + modbus_table_analog_out[130].all = protect_levels.abnormal_temper_air_int_02 / 10; + modbus_table_analog_out[131].all = protect_levels.abnormal_temper_air_int_03 / 10; + modbus_table_analog_out[132].all = protect_levels.abnormal_temper_air_int_04 / 10; + modbus_table_analog_out[133].all = protect_levels.alarm_temper_air_int_01 / 10; + modbus_table_analog_out[134].all = protect_levels.alarm_temper_air_int_02 / 10; + modbus_table_analog_out[135].all = protect_levels.alarm_temper_air_int_03 / 10; + modbus_table_analog_out[136].all = protect_levels.alarm_temper_air_int_04 / 10; + +// toControllerAlarmMinUlineA1B1C1 30137 +// toControllerAlarmMinUlineA2B2C2 30138 +// toControllerAlarmMinUdcUP 30139 +// toControllerAlarmMinUdcDOWN 30140 +// toControllerAlarmMaxUlineA1B1C1 30142 +// toControllerAlarmMaxUlineA2B2C2 30143 +// toControllerAlarmMaxUdcUP 30144 +// toControllerAlarmMaxUdcDOWN 30145 + + modbus_table_analog_out[137].all = _IQtoF(analog_protect.in_voltage[0].setup.levels.iqNominal_minus20) * NORMA_ACP;//_IQtoF(edrk.iqMIN_U_IN) * NORMA_ACP; + modbus_table_analog_out[138].all = _IQtoF(analog_protect.in_voltage[1].setup.levels.iqNominal_minus20) * NORMA_ACP; + + modbus_table_analog_out[139].all = _IQtoF(edrk.iqMIN_U_ZPT) * NORMA_ACP; + modbus_table_analog_out[140].all = _IQtoF(edrk.iqMIN_U_ZPT) * NORMA_ACP; + + modbus_table_analog_out[142].all = _IQtoF(analog_protect.in_voltage[0].setup.levels.iqNominal_plus20) * NORMA_ACP; + modbus_table_analog_out[143].all = _IQtoF(analog_protect.in_voltage[1].setup.levels.iqNominal_plus20) * NORMA_ACP; + +// modbus_table_analog_out[141].all = //_IQtoF(edrk.iqMAX_U_IN) * NORMA_ACP; +// modbus_table_analog_out[140].all = _IQtoF(edrk.iqMAX_U_IN) * NORMA_ACP; + + modbus_table_analog_out[144].all = _IQtoF(edrk.iqMAX_U_ZPT) * NORMA_ACP; + modbus_table_analog_out[145].all = _IQtoF(edrk.iqMAX_U_ZPT) * NORMA_ACP; + + modbus_table_analog_out[146].all = protect_levels.alarm_Izpt_max; + + modbus_table_analog_out[155].all = protect_levels.alarm_Imax_U01; + modbus_table_analog_out[156].all = protect_levels.alarm_Imax_U02; + modbus_table_analog_out[157].all = protect_levels.alarm_Imax_U03; + modbus_table_analog_out[158].all = protect_levels.alarm_Imax_U04; + modbus_table_analog_out[159].all = protect_levels.alarm_Imax_U05; + modbus_table_analog_out[160].all = protect_levels.alarm_Imax_U06; + modbus_table_analog_out[161].all = protect_levels.alarm_Imax_U07; + modbus_table_analog_out[162].all = protect_levels.alarm_Iged_max; + + + // save nPCH TimeToChangePump + modbus_table_analog_out[163].all = edrk.pult_data.data_to_pult.nPCH; + modbus_table_analog_out[154].all = edrk.pult_data.data_to_pult.TimeToChangePump; + + modbus_table_analog_out[222].all = edrk.pult_data.data_to_pult.count_build; + modbus_table_analog_out[223].all = edrk.pult_data.data_to_pult.count_revers; + + + + modbus_table_analog_out[197].all = edrk.pult_data.flagSaveDataPCH; + + + + + // build version + modbus_table_analog_out[219].all = edrk.buildYear; + modbus_table_analog_out[220].all = edrk.buildMonth; + modbus_table_analog_out[221].all = edrk.buildDay; + + //moto + for (i=0;i32760) + edrk.pult_data.data.count_build = 1; + + // edrk.pult_data.data_to_pult.count_build = edrk.pult_data.data.count_build; + // edrk.pult_data.data_to_pult.moto[21] = edrk.pult_data.data_to_pult.count_build; +} + + + +void inc_count_revers(void) +{ +// edrk.pult_data.data.count_revers = edrk.pult_data.data_from_pult.moto[22]; + + edrk.pult_data.data.count_revers++; + if (edrk.pult_data.data.count_revers>32760) + edrk.pult_data.data.count_revers = 1; + +// edrk.pult_data.data_to_pult.count_revers = edrk.pult_data.data.count_revers; + // edrk.pult_data.data_to_pult.moto[22] = edrk.pult_data.data_to_pult.count_revers + +} + + +void update_nPCH(void) +{ + + static int pause_w = 5, first_run = 1; // 10 + int flag_1 = 0, flag_2 = 0, i; + static int prev_active = 0; + + if (control_station.alive_control_station[CONTROL_STATION_INGETEAM_PULT_RS485]==0) + { + pause_w = 5; + } + + if (pause_w > 1) + { + pause_w--; +// if (edrk.pult_data.nPCH_from_pult) +// if (pause_w > 1) +// pause_w = 1; + prev_active = control_station.alive_control_station[CONTROL_STATION_INGETEAM_PULT_RS485]; + return; + } + + // -1 + // -1 , + // + if (pause_w==1 && first_run) + { + // + if (edrk.pult_data.data_from_pult.nPCH==-1) // + { + edrk.pult_data.data_to_pult.nPCH = edrk.pult_data.data.nPCH = 0; + } + else + edrk.pult_data.data_to_pult.nPCH = edrk.pult_data.data.nPCH = edrk.pult_data.data_from_pult.nPCH; + + // + if (edrk.pult_data.data_from_pult.TimeToChangePump == -1) // + edrk.pult_data.data_to_pult.TimeToChangePump = edrk.pult_data.data.TimeToChangePump = 0; + else + edrk.pult_data.data_to_pult.TimeToChangePump = edrk.pult_data.data.TimeToChangePump = edrk.pult_data.data_from_pult.TimeToChangePump; + + // + + - + for (i=0;i=0) + { + edrk.pult_data.data_to_pult.nPCH = edrk.pult_data.data_from_pult.nPCH; + flag_1 = 1; + edrk.pult_data.data.nPCH = edrk.pult_data.data_from_pult.nPCH; + } + + // -1 + if (edrk.pult_data.data_from_pult.nPCH != edrk.pult_data.data.nPCH && edrk.pult_data.data_from_pult.nPCH == -1) + { + edrk.pult_data.data_to_pult.nPCH = edrk.pult_data.data.nPCH; + flag_1 = 1; + } + + + // + // + if (edrk.pult_data.data_from_pult.TimeToChangePump != edrk.pult_data.data.TimeToChangePump + && edrk.pult_data.data_from_pult.TimeToChangePump >= 0) + { + edrk.pult_data.data_to_pult.TimeToChangePump = edrk.pult_data.data_from_pult.TimeToChangePump; + flag_1 = 1; + edrk.pult_data.data.TimeToChangePump = edrk.pult_data.data_from_pult.TimeToChangePump; + } + + // -1 + if (edrk.pult_data.data_from_pult.TimeToChangePump != edrk.pult_data.data.TimeToChangePump + && edrk.pult_data.data_from_pult.TimeToChangePump == -1) + { + edrk.pult_data.data_to_pult.TimeToChangePump = edrk.pult_data.data.TimeToChangePump; + flag_1 = 1; + } + + // build + // -1 + if (edrk.pult_data.data_from_pult.count_build != edrk.pult_data.data.count_build + && edrk.pult_data.data_from_pult.count_build == -1) + { + edrk.pult_data.data_to_pult.count_build = edrk.pult_data.data.count_build; + flag_1 = 1; + } + + if (edrk.pult_data.data_from_pult.count_build != edrk.pult_data.data.count_build) + { + edrk.pult_data.data_to_pult.count_build = edrk.pult_data.data.count_build; + flag_1 = 1; + } + + // revers + // -1 + if (edrk.pult_data.data_from_pult.count_revers != edrk.pult_data.data.count_revers + && edrk.pult_data.data_from_pult.count_revers == -1) + { + edrk.pult_data.data_to_pult.count_revers = edrk.pult_data.data.count_revers; + flag_1 = 1; + } + + if (edrk.pult_data.data_from_pult.count_revers != edrk.pult_data.data.count_revers ) + { + edrk.pult_data.data_to_pult.count_revers = edrk.pult_data.data.count_revers; + flag_1 = 1; + } + // + edrk.pult_data.flagSaveDataPCH = flag_1; + + + // moto + for (i=0;i= 2) + to_store = 2; + else + if (edrk.pult_cmd.log_what_memory >= 1) + to_store = 1; + else + to_store = 0; + + //40198 - ( ) (2), (1), +usb (3) + if (prev_cmd == 0 && cmd && to_store && flag_wait == 0) + { + edrk.pult_data.flagSaveSlowLogs = to_store; + flag_wait = 1; + time_wait_save_log = global_time.miliseconds; + } + + + if (flag_wait) + { + if (detect_pause_milisec(COUNT_WAIT_SAVE_LOG, &time_wait_save_log)) + { + flag_wait = 0; + flag_clear = 1; // + edrk.pult_data.flagSaveSlowLogs = 0; + time_wait_clear_log = global_time.miliseconds; + } + + } + else + { + + } + + + + + if (flag_clear) // + { + edrk.pult_data.flagSaveSlowLogs = 100; + if (detect_pause_milisec(COUNT_WAIT_SAVE_LOG, &time_wait_clear_log)) + { + flag_wait = 0; + flag_clear = 0; + edrk.pult_data.flagSaveSlowLogs = 0; + } + + } + + // 30033: + +// 0 - , ; +// 1 - , ; +// 2 - , ; +// 3 - ; +} + diff --git a/Inu/Src2/551/main/modbus_hmi_update.h b/Inu/Src2/551/main/modbus_hmi_update.h new file mode 100644 index 0000000..3ed0c05 --- /dev/null +++ b/Inu/Src2/551/main/modbus_hmi_update.h @@ -0,0 +1,39 @@ +#ifndef _HMI_UPDATE +#define _HMI_UPDATE + + +#define LIMITER_U_I_PULT 5.0 //10.0 + + +typedef enum { + state_not_init = 0, state_ready1 = 1, state_ready2, state_go, state_assemble, state_fault, state_accident +} Inverter_state; + +void update_tables_HMI(void); +void update_logs_cmd_HMI(void); +void update_tables_HMI_on_inited(int perc_load); + +void update_tables_HMI_analog(void); +void update_tables_HMI_discrete(void); + +int update_progress_load_hmi(int proc_load); + +void setStateHMI(Inverter_state state); +void setElementsColorsHMI(Inverter_state state); + +void get_command_HMI(void); +void func_unpack_answer_from_Ingeteam(unsigned int cc); + +extern int hmi_watch_dog; + +void update_nPCH(void); + +void inc_count_build(void); +void inc_count_revers(void); + +void set_write_slow_logs(int cmd); + +void update_LoggerParams(void); + + +#endif //_HMI_UPDATE diff --git a/Inu/Src2/551/main/modbus_svu_update.c b/Inu/Src2/551/main/modbus_svu_update.c new file mode 100644 index 0000000..d9e6fe2 --- /dev/null +++ b/Inu/Src2/551/main/modbus_svu_update.c @@ -0,0 +1,710 @@ +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "math.h" +#include "control_station.h" +#include "CAN_Setup.h" +#include "modbus_table_v2.h" +#include "mathlib.h" + +void update_errors_to_svu(void); +void update_protect_levels_to_MPU(void); + +void update_svu_modbus_table(void) +{ + int current_active_control; + + modbus_table_can_out[0].all = edrk.Stop ? 7 : +// edrk.Provorot ? 6 : + edrk.Go ? 5 : + edrk.Status_Ready.bits.ready_final ? 4 : + edrk.to_ing.bits.RASCEPITEL_ON ? 3 : + edrk.SumSbor ? 2 : + edrk.Status_Ready.bits.ready1 ? 1 : 0; + modbus_table_can_out[1].all = edrk.warning; + modbus_table_can_out[2].all = edrk.overheat; +// modbus_table_can_out[3].all = ; +// modbus_table_can_out[4].all = ; + modbus_table_can_out[5].all = edrk.Status_Ready.bits.Batt; + modbus_table_can_out[6].all = edrk.from_ing1.bits.UPC_24V_NORMA | edrk.from_ing1.bits.OP_PIT_NORMA ? 0 : 1; + modbus_table_can_out[7].all = WRotor.RotorDirectionSlow >= 0 ? 0 : 1; + modbus_table_can_out[8].all = edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER || + edrk.Mode_ScalarVectorUFConst == ALG_MODE_SCALAR_POWER ? 1 : 0; + current_active_control = get_current_station_control(); + modbus_table_can_out[9].all = current_active_control == CONTROL_STATION_INGETEAM_PULT_RS485 ? 1 : + current_active_control == CONTROL_STATION_MPU_KEY_CAN || current_active_control == CONTROL_STATION_MPU_KEY_RS485 ? 2 : + current_active_control == CONTROL_STATION_ZADATCHIK_CAN ? 3 : + current_active_control == CONTROL_STATION_VPU_CAN ? 4 : + current_active_control == CONTROL_STATION_MPU_SVU_CAN || current_active_control == CONTROL_STATION_MPU_SVU_RS485 ? 5 : + 0; + modbus_table_can_out[10].all = edrk.errors.e2.bits.T_UO1_MAX || edrk.errors.e6.bits.UO1_KEYS ? 3 : + edrk.warnings.e2.bits.T_UO1_MAX ? 2 : 1; + modbus_table_can_out[11].all = edrk.errors.e2.bits.T_UO2_MAX || edrk.errors.e6.bits.UO2_KEYS ? 3 : + edrk.warnings.e2.bits.T_UO2_MAX ? 2 : 1; + modbus_table_can_out[12].all = edrk.errors.e2.bits.T_UO3_MAX || edrk.errors.e6.bits.UO3_KEYS ? 3 : + edrk.warnings.e2.bits.T_UO3_MAX ? 2 : 1; + modbus_table_can_out[13].all = edrk.errors.e2.bits.T_UO4_MAX || edrk.errors.e6.bits.UO4_KEYS ? 3 : + edrk.warnings.e2.bits.T_UO4_MAX ? 2 : 1; + modbus_table_can_out[14].all = edrk.errors.e2.bits.T_UO5_MAX || edrk.errors.e6.bits.UO5_KEYS ? 3 : + edrk.warnings.e2.bits.T_UO5_MAX ? 2 : 1; + modbus_table_can_out[15].all = edrk.errors.e2.bits.T_UO6_MAX || edrk.errors.e6.bits.UO6_KEYS ? 3 : + edrk.warnings.e2.bits.T_UO6_MAX ? 2 : 1; + modbus_table_can_out[16].all = edrk.errors.e2.bits.T_UO7_MAX || edrk.errors.e6.bits.UO7_KEYS ? 3 : + edrk.warnings.e2.bits.T_UO7_MAX ? 2 : 1; + modbus_table_can_out[17].all = edrk.Status_QTV_Ok;// edrk.from_shema.bits.QTV_ON_OFF; + modbus_table_can_out[18].all = edrk.from_svu.bits.BLOCKED; + modbus_table_can_out[19].all = edrk.from_shema_filter.bits.UMP_ON_OFF; + modbus_table_can_out[20].all = edrk.from_shema_filter.bits.READY_UMP; + modbus_table_can_out[21].all = edrk.from_ing1.bits.RASCEPITEL_ON; + modbus_table_can_out[22].all = edrk.from_ing1.bits.UPC_24V_NORMA; + modbus_table_can_out[23].all = edrk.from_ing1.bits.OHLAD_UTE4KA_WATER; + modbus_table_can_out[24].all = edrk.from_ing2.bits.SOST_ZAMKA; + modbus_table_can_out[25].all = edrk.from_ing1.bits.ZARYAD_ON | edrk.from_shema_filter.bits.UMP_ON_OFF; //, , + modbus_table_can_out[26].all = edrk.from_ing1.bits.VENTIL_ON; + modbus_table_can_out[27].all = edrk.to_ing.bits.NASOS_1_ON == 1 && edrk.from_ing1.bits.NASOS_ON == 1 ? 1 : 0; + modbus_table_can_out[28].all = edrk.to_ing.bits.NASOS_2_ON == 1 && edrk.from_ing1.bits.NASOS_ON == 1 ? 1 : 0; + modbus_table_can_out[29].all = edrk.from_ing1.bits.NASOS_NORMA; + modbus_table_can_out[30].all = edrk.from_ing1.bits.ZAZEML_ON; + modbus_table_can_out[31].all = edrk.from_ing1.bits.NAGREV_ON; + modbus_table_can_out[32].all = edrk.from_ing1.bits.BLOCK_IZOL_NORMA == 1 ? 1 : 0; + modbus_table_can_out[33].all = edrk.errors.e5.bits.ERROR_ISOLATE == 0 && edrk.from_ing1.bits.BLOCK_IZOL_NORMA == 1 ? 0 : 1; + modbus_table_can_out[34].all = edrk.from_ing1.bits.ALL_KNOPKA_AVARIA; + + if (edrk.MasterSlave == MODE_MASTER) + modbus_table_can_out[35].all = 1; + else + if (edrk.MasterSlave == MODE_SLAVE) + modbus_table_can_out[35].all = 0; + else + modbus_table_can_out[35].all = 2; // MODE_DONTKNOW + +// modbus_table_can_out[35].all = edrk.MasterSlave == MODE_MASTER ? 1 : 0; + modbus_table_can_out[36].all = edrk.from_ing1.bits.OP_PIT_NORMA & edrk.from_ing1.bits.UPC_24V_NORMA; + modbus_table_can_out[37].all = optical_read_data.status == 1 && optical_write_data.status == 1 ? 1 : 0; + modbus_table_can_out[38].all = edrk.warnings.e7.bits.MASTER_SLAVE_SYNC == 0 ? 1 : 0; + modbus_table_can_out[39].all = fast_round(_IQtoF(filter.iqIm) * NORMA_ACP); + modbus_table_can_out[40].all = fast_round(_IQtoF(filter.iqIin_sum) * NORMA_ACP); + modbus_table_can_out[41].all = fast_round(_IQtoF(filter.iqU_1_long + filter.iqU_2_long) * NORMA_ACP); + + if (filter.iqUin_m1>=filter.iqUin_m2) + modbus_table_can_out[42].all = fast_round(_IQtoF(filter.iqUin_m1) * NORMA_ACP / 1.41); + else + modbus_table_can_out[42].all = fast_round(_IQtoF(filter.iqUin_m2) * NORMA_ACP / 1.41); + + modbus_table_can_out[43].all = fast_round(_IQtoF(filter.iqU_1_long) * NORMA_ACP); + modbus_table_can_out[44].all = fast_round(_IQtoF(filter.iqU_2_long) * NORMA_ACP); + modbus_table_can_out[45].all = fast_round(_IQtoF(filter.iqIm_1) * NORMA_ACP / 1.41); + modbus_table_can_out[46].all = fast_round(_IQtoF(filter.iqIm_1) * NORMA_ACP / 1.41); + modbus_table_can_out[47].all = fast_round(_IQtoF(filter.iqIm_1) * NORMA_ACP / 1.41); + modbus_table_can_out[48].all = fast_round(_IQtoF(filter.iqIm_2) * NORMA_ACP / 1.41); + modbus_table_can_out[49].all = fast_round(_IQtoF(filter.iqIm_2) * NORMA_ACP / 1.41); + modbus_table_can_out[50].all = fast_round(_IQtoF(filter.iqIm_2) * NORMA_ACP / 1.41); + modbus_table_can_out[51].all = fast_round(_IQtoF(filter.iqIin_sum) * NORMA_ACP); +// modbus_table_can_out[52].all = Uvh rms +// modbus_table_can_out[53].all = +// modbus_table_can_out[54].all = +// modbus_table_can_out[55].all = + modbus_table_can_out[56].all = _IQtoF(analog.iqIbreak_1) * NORMA_ACP; + modbus_table_can_out[57].all = _IQtoF(analog.iqIbreak_2) * NORMA_ACP; + + //Temperatures + modbus_table_can_out[58].all = fast_round(edrk.temper_edrk.real_temper_u[0]); + modbus_table_can_out[59].all = fast_round(edrk.temper_edrk.real_temper_u[1]); + modbus_table_can_out[60].all = fast_round(edrk.temper_edrk.real_temper_u[2]); + modbus_table_can_out[61].all = fast_round(edrk.temper_edrk.real_temper_u[3]); + modbus_table_can_out[62].all = fast_round(edrk.temper_edrk.real_temper_u[4]); + modbus_table_can_out[63].all = fast_round(edrk.temper_edrk.real_temper_u[5]); + modbus_table_can_out[64].all = fast_round(edrk.temper_edrk.real_temper_u[6]); + modbus_table_can_out[65].all = fast_round(edrk.temper_edrk.real_temper_water[1]); + modbus_table_can_out[66].all = fast_round(edrk.temper_edrk.real_temper_water[0]); + modbus_table_can_out[67].all = fast_round(edrk.temper_edrk.real_temper_air[0]); + modbus_table_can_out[68].all = fast_round(edrk.temper_edrk.real_temper_air[1]); + modbus_table_can_out[69].all = fast_round(edrk.temper_edrk.real_temper_air[2]); + modbus_table_can_out[70].all = fast_round(edrk.temper_edrk.real_temper_air[3]); + + modbus_table_can_out[71].all = fast_round(edrk.p_water_edrk.real_p_water[0]); + + modbus_table_can_out[72].all = fast_round(_IQtoF(edrk.zadanie.iq_oborots_zad_hz_rmp) * NORMA_FROTOR * 60); + modbus_table_can_out[73].all = edrk.oborots;// fast_round(_IQtoF(WRotor.iqWRotorSumFilter3) * NORMA_FROTOR * 60); + modbus_table_can_out[74].all = edrk.oborots;//fast_round(_IQtoF(WRotor.iqWRotorSumFilter3) * NORMA_FROTOR * 60); //Sensor 1 + modbus_table_can_out[75].all = edrk.oborots;//fast_round(_IQtoF(WRotor.iqWRotorSumFilter3) * NORMA_FROTOR * 60); //Sensor 1 + + modbus_table_can_out[76].all = fast_round(_IQtoF(edrk.zadanie.iq_power_zad_rmp) * NORMA_ACP * NORMA_ACP / 1000.0); + modbus_table_can_out[77].all = fabs(edrk.power_kw);// fast_round(_IQtoF(filter.PowerScalar) * NORMA_ACP* NORMA_ACP / 1000.0); + + modbus_table_can_out[78].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[0]); + modbus_table_can_out[79].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[1]); + modbus_table_can_out[80].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[2]); + modbus_table_can_out[81].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[3]); + modbus_table_can_out[82].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[4]); + modbus_table_can_out[83].all = fast_round(edrk.temper_acdrive.winding.filter_real_temper[5]); + modbus_table_can_out[84].all = fast_round(edrk.temper_acdrive.bear.filter_real_temper[0]); // TODO: + modbus_table_can_out[85].all = fast_round(edrk.temper_acdrive.bear.filter_real_temper[1]); // + + modbus_table_can_out[86].all = Unites[UMU_CAN_DEVICE][24]; + modbus_table_can_out[87].all = Unites[UMU_CAN_DEVICE][25]; + modbus_table_can_out[88].all = Unites[UMU_CAN_DEVICE][28]; + modbus_table_can_out[89].all = Unites[UMU_CAN_DEVICE][29]; + modbus_table_can_out[90].all = Unites[UMU_CAN_DEVICE][34]; + modbus_table_can_out[91].all = Unites[UMU_CAN_DEVICE][35]; + modbus_table_can_out[92].all = Unites[UMU_CAN_DEVICE][34]; //, + modbus_table_can_out[93].all = Unites[UMU_CAN_DEVICE][35]; //, + + modbus_table_can_out[94].all = edrk.warnings.e2.bits.T_UO1_MAX | edrk.warnings.e2.bits.T_UO2_MAX | + edrk.warnings.e2.bits.T_UO3_MAX | edrk.warnings.e2.bits.T_UO4_MAX | + edrk.warnings.e2.bits.T_UO5_MAX | edrk.warnings.e2.bits.T_UO6_MAX | + edrk.warnings.e2.bits.T_UO7_MAX; + modbus_table_can_out[95].all = edrk.errors.e2.bits.T_UO1_MAX | edrk.errors.e2.bits.T_UO2_MAX | + edrk.errors.e2.bits.T_UO3_MAX | edrk.errors.e2.bits.T_UO4_MAX | + edrk.errors.e2.bits.T_UO5_MAX | edrk.errors.e2.bits.T_UO6_MAX | + edrk.errors.e2.bits.T_UO7_MAX; + modbus_table_can_out[96].all = edrk.warnings.e2.bits.T_AIR0_MAX | edrk.warnings.e2.bits.T_AIR1_MAX | + edrk.warnings.e2.bits.T_AIR2_MAX | edrk.warnings.e2.bits.T_AIR3_MAX; + modbus_table_can_out[97].all = edrk.errors.e2.bits.T_AIR0_MAX | edrk.errors.e2.bits.T_AIR1_MAX | + edrk.errors.e2.bits.T_AIR2_MAX | edrk.errors.e2.bits.T_AIR3_MAX; + modbus_table_can_out[98].all = edrk.warnings.e2.bits.T_WATER_EXT_MAX; + modbus_table_can_out[99].all = edrk.errors.e2.bits.T_WATER_EXT_MAX; + modbus_table_can_out[100].all = edrk.warnings.e2.bits.T_WATER_INT_MAX; + modbus_table_can_out[101].all = edrk.errors.e2.bits.T_WATER_INT_MAX; + + modbus_table_can_out[102].all = edrk.warnings.e2.bits.P_WATER_INT_MAX; + modbus_table_can_out[103].all = edrk.errors.e2.bits.P_WATER_INT_MAX; + modbus_table_can_out[104].all = edrk.warnings.e2.bits.P_WATER_INT_MIN; + modbus_table_can_out[105].all = edrk.errors.e2.bits.P_WATER_INT_MIN; + + modbus_table_can_out[106].all = edrk.warnings.e7.bits.T_ACDRIVE_WINDING_MAX; + modbus_table_can_out[107].all = edrk.errors.e7.bits.T_ACDRIVE_WINDING_MAX; + modbus_table_can_out[108].all = edrk.warnings.e7.bits.T_ACDRIVE_BEAR_MAX_DNE; // + modbus_table_can_out[109].all = edrk.errors.e7.bits.T_ACDRIVE_BEAR_MAX_DNE; + modbus_table_can_out[110].all = edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE; // + modbus_table_can_out[111].all = edrk.errors.e9.bits.T_ACDRIVE_BEAR_MAX_NE; + + modbus_table_can_out[112].all = edrk.warnings.e9.bits.I_GED_MAX; + modbus_table_can_out[113].all = edrk.errors.e1.bits.I_UO2_MAX | edrk.errors.e1.bits.I_UO3_MAX | + edrk.errors.e1.bits.I_UO4_MAX | edrk.errors.e1.bits.I_UO5_MAX | + edrk.errors.e1.bits.I_UO6_MAX | edrk.errors.e1.bits.I_UO7_MAX; //TODO add adc errors + modbus_table_can_out[114].all = edrk.errors.e0.bits.I_1_MAX | edrk.errors.e0.bits.I_2_MAX; + modbus_table_can_out[115].all = edrk.errors.e0.bits.U_1_MAX | edrk.errors.e0.bits.U_2_MAX; + modbus_table_can_out[116].all = edrk.warnings.e0.bits.U_IN_MIN; + modbus_table_can_out[117].all = edrk.errors.e0.bits.U_IN_MIN; + modbus_table_can_out[118].all = edrk.warnings.e0.bits.U_IN_MAX; + modbus_table_can_out[119].all = edrk.errors.e0.bits.U_IN_MAX; + modbus_table_can_out[120].all = edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK; //TODO + modbus_table_can_out[121].all = edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK; //TODO + modbus_table_can_out[122].all = edrk.Kvitir; + + + modbus_table_can_out[137].all = edrk.pult_data.data_from_pult.moto[15]; + modbus_table_can_out[138].all = edrk.pult_data.data_from_pult.moto[6]; + + update_errors_to_svu(); + update_protect_levels_to_MPU(); + + copy_from_can_out_to_rs_out(); + +} + +#define MPU_ADRESS_CMD_START 122 // -1 14, 122 123 14 +#define MPU_ADRESS_CMD_END 144 //138 // + +#if (MPU_ADRESS_CMD_END>=SIZE_MODBUS_TABLE) +#define MPU_ADRESS_CMD_END (SIZE_MODBUS_TABLE-1) +#endif + + +#if (MPU_ADRESS_CMD_END - MPU_ADRESS_CMD_START +1 )>CONTROL_STATION_MAX_RAW_DATA +#define MPU_LENGTH_CMD CONTROL_STATION_MAX_RAW_DATA +#else +#define MPU_LENGTH_CMD (MPU_ADRESS_CMD_END - MPU_ADRESS_CMD_START + 1) +#endif +///////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + +void unpack_answer_from_MPU_SVU_CAN_filter(unsigned int cc) +{ + unsigned int i = 0, j = 0, k, max_data; + + for (i = 0; i < MPU_LENGTH_CMD; i++) + { + max_data = 0;//control_station.raw_array_data_temp[cc][i][0].all; + //min_data = 0;//control_station.raw_array_data_temp[cc][i][0].all; + + for (j=0; j max_data) + max_data = control_station.raw_array_data_temp[cc][i][j].all; + } + + control_station.raw_array_data[cc][i].all = max_data; + + } + +} + +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// + + +void unpack_answer_from_MPU_SVU_CAN(unsigned int cc) { + int i = 0, j = 0, k; +// static unsigned int prev_CAN_count_cycle_input_units = 0; + + if (control_station.prev_CAN_count_cycle_input_units[cc] != mpu_can_setup.CAN_count_cycle_input_units[0]) + { + k = control_station.count_raw_array_data_temp[cc]; + for (i = 0, j = 0; i < MPU_LENGTH_CMD && j < CONTROL_STATION_MAX_RAW_DATA; i++, j++) + { + control_station.raw_array_data_temp[cc][j][k].all = modbus_table_can_in[MPU_ADRESS_CMD_START+i].all; + } + + control_station.count_raw_array_data_temp[cc]++; + if (control_station.count_raw_array_data_temp[cc]>=CONTROL_STATION_MAX_RAW_DATA_TEMP) + control_station.count_raw_array_data_temp[cc] = 0; + + control_station.prev_CAN_count_cycle_input_units[cc] = mpu_can_setup.CAN_count_cycle_input_units[0]; + } + + +// for (i = ADRESS_CMD_START, j = 0; i < SIZE_MODBUS_TABLE && j < CONTROL_STATION_MAX_RAW_DATA; i++, j++) +// { +// control_station.raw_array_data[cc][j].all = modbus_table_can_in[i].all; +// } + + unpack_answer_from_MPU_SVU_CAN_filter(cc); + +} + +void unpack_answer_from_MPU_SVU_RS(unsigned int cc) { + int i = 0, j = 0; + for (i = MPU_ADRESS_CMD_START, j = 0; i < SIZE_MODBUS_TABLE && j < CONTROL_STATION_MAX_RAW_DATA; i++, j++) + control_station.raw_array_data[cc][j].all = modbus_table_rs_in[i].all; +} + +void update_errors_to_svu() { + modbus_table_can_out[208].bit.bit0 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_ack; + modbus_table_can_out[208].bit.bit1 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_ack; + modbus_table_can_out[208].bit.bit2 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_ack; + modbus_table_can_out[208].bit.bit3 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_ack; + modbus_table_can_out[208].bit.bit4 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_ack; + modbus_table_can_out[208].bit.bit5 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_ack; + modbus_table_can_out[208].bit.bit6 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_ack; + modbus_table_can_out[208].bit.bit7 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_ack; + + modbus_table_can_out[208].bit.bit8 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_ack; + modbus_table_can_out[208].bit.bit9 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_ack; + modbus_table_can_out[208].bit.bit10 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_ack; + modbus_table_can_out[208].bit.bit11 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_ack; + modbus_table_can_out[208].bit.bit12 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_ack; + modbus_table_can_out[208].bit.bit13 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_ack; + modbus_table_can_out[208].bit.bit14 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_ack; + modbus_table_can_out[208].bit.bit15 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_ack; + + modbus_table_can_out[200].bit.bit0 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_ack; + modbus_table_can_out[200].bit.bit1 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_ack; + modbus_table_can_out[200].bit.bit2 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_ack; + modbus_table_can_out[200].bit.bit3 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_ack; + modbus_table_can_out[200].bit.bit4 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_ack; + modbus_table_can_out[200].bit.bit5 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_ack; + modbus_table_can_out[200].bit.bit6 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_ack; + modbus_table_can_out[200].bit.bit7 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_ack; + modbus_table_can_out[200].bit.bit8 = project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_ack; + modbus_table_can_out[200].bit.bit9 = project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_ack; + + if (edrk.flag_second_PCH == 1) { + modbus_table_can_out[200].bit.bit10 = edrk.errors.e4.bits.ANOTHER_BS_POWER_OFF; + } else { + modbus_table_can_out[200].bit.bit11 = edrk.errors.e4.bits.ANOTHER_BS_POWER_OFF; + } + + modbus_table_can_out[201].bit.bit0 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk0_current; + modbus_table_can_out[201].bit.bit1 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk1_current; + modbus_table_can_out[201].bit.bit2 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk2_current; + modbus_table_can_out[201].bit.bit3 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk3_current; + modbus_table_can_out[201].bit.bit4 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk4_current; + modbus_table_can_out[201].bit.bit5 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk5_current; + modbus_table_can_out[201].bit.bit6 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk6_current; + modbus_table_can_out[201].bit.bit7 = project.cds_tk[0].read.sbus.status_protect_current_ack.bit.tk7_current; + modbus_table_can_out[201].bit.bit8 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk0_current; + modbus_table_can_out[201].bit.bit9 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk1_current; + modbus_table_can_out[201].bit.bit10 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk2_current; + modbus_table_can_out[201].bit.bit11 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk3_current; + modbus_table_can_out[201].bit.bit12 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk4_current; + modbus_table_can_out[201].bit.bit13 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk5_current; + modbus_table_can_out[201].bit.bit14 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk6_current; + modbus_table_can_out[201].bit.bit15 = project.cds_tk[1].read.sbus.status_protect_current_ack.bit.tk7_current; + + modbus_table_can_out[202].bit.bit0 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk0_current; + modbus_table_can_out[202].bit.bit1 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk1_current; + modbus_table_can_out[202].bit.bit2 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk2_current; + modbus_table_can_out[202].bit.bit3 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk3_current; + modbus_table_can_out[202].bit.bit4 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk4_current; + modbus_table_can_out[202].bit.bit5 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk5_current; + modbus_table_can_out[202].bit.bit6 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk6_current; + modbus_table_can_out[202].bit.bit7 = project.cds_tk[2].read.sbus.status_protect_current_ack.bit.tk7_current; + modbus_table_can_out[202].bit.bit8 = project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk0_current; + modbus_table_can_out[202].bit.bit9 = project.cds_tk[3].read.sbus.status_protect_current_ack.bit.tk1_current; + + modbus_table_can_out[203].bit.bit0 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[203].bit.bit1 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[203].bit.bit2 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[203].bit.bit3 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[203].bit.bit4 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[203].bit.bit5 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[203].bit.bit6 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[203].bit.bit7 = project.cds_tk[0].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[203].bit.bit8 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[203].bit.bit9 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[203].bit.bit10 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[203].bit.bit11 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[203].bit.bit12 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[203].bit.bit13 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[203].bit.bit14 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[203].bit.bit15 = project.cds_tk[1].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + + modbus_table_can_out[204].bit.bit0 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[204].bit.bit1 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[204].bit.bit2 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[204].bit.bit3 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[204].bit.bit4 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[204].bit.bit5 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[204].bit.bit6 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[204].bit.bit7 = project.cds_tk[2].read.sbus.lock_status_error.bit.mintime_err_keys_7654; + modbus_table_can_out[204].bit.bit8 = project.cds_tk[3].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + modbus_table_can_out[204].bit.bit9 = project.cds_tk[3].read.sbus.lock_status_error.bit.mintime_err_keys_3210; + + modbus_table_can_out[205].bit.bit0 = edrk.errors.e3.bits.NOT_READY_TK_0; + modbus_table_can_out[205].bit.bit1 = edrk.errors.e3.bits.NOT_READY_TK_1; + modbus_table_can_out[205].bit.bit2 = edrk.errors.e3.bits.NOT_READY_TK_2; + modbus_table_can_out[205].bit.bit3 = edrk.errors.e3.bits.NOT_READY_TK_3; + modbus_table_can_out[205].bit.bit4 = edrk.errors.e3.bits.NOT_READY_IN_0; + modbus_table_can_out[205].bit.bit5 = edrk.errors.e3.bits.NOT_READY_IN_1; + modbus_table_can_out[205].bit.bit6 = edrk.errors.e3.bits.NOT_READY_OUT_0; + modbus_table_can_out[205].bit.bit7 = edrk.errors.e3.bits.NOT_READY_ADC_0; + modbus_table_can_out[205].bit.bit8 = edrk.errors.e3.bits.NOT_READY_HWP_0; + modbus_table_can_out[205].bit.bit9 = edrk.errors.e3.bits.NOT_READY_ADC_1; + modbus_table_can_out[205].bit.bit10 = edrk.errors.e3.bits.NOT_READY_CONTR; + + modbus_table_can_out[206].bit.bit0 = edrk.errors.e5.bits.KEY_AVARIA; + modbus_table_can_out[206].bit.bit1 = edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER; + modbus_table_can_out[206].bit.bit2 = edrk.errors.e7.bits.SVU_BLOCK_ON_QTV; + modbus_table_can_out[206].bit.bit3 = edrk.errors.e7.bits.UMP_NOT_ANSWER; + modbus_table_can_out[206].bit.bit4 = edrk.errors.e7.bits.UMP_NOT_READY; + modbus_table_can_out[206].bit.bit5 = edrk.errors.e6.bits.RASCEPITEL_ERROR_NOT_ANSWER; + modbus_table_can_out[206].bit.bit6 = edrk.errors.e7.bits.ANOTHER_RASCEPITEL_ON; + modbus_table_can_out[206].bit.bit7 = edrk.warnings.e7.bits.AUTO_SET_MASTER; + modbus_table_can_out[206].bit.bit8 = edrk.errors.e7.bits.ANOTHER_PCH_NOT_ANSWER; + modbus_table_can_out[206].bit.bit9 = edrk.errors.e8.bits.WDOG_OPTICAL_BUS; + modbus_table_can_out[206].bit.bit10 = edrk.errors.e6.bits.QTV_ERROR_NOT_ANSWER; // + modbus_table_can_out[206].bit.bit11 = edrk.errors.e1.bits.NO_CONFIRM_ON_RASCEPITEL; // + modbus_table_can_out[206].bit.bit12 = edrk.errors.e6.bits.RASCEPITEL_ERROR_NOT_ANSWER; + modbus_table_can_out[206].bit.bit13 = edrk.errors.e1.bits.ANOTHER_BS_VERY_LONG_WAIT; + modbus_table_can_out[206].bit.bit14 = edrk.errors.e1.bits.VERY_LONG_BOTH_READY2; + modbus_table_can_out[206].bit.bit15 = edrk.errors.e1.bits.BOTH_KEYS_CHARGE_DISCHARGE; + + + modbus_table_can_out[207].bit.bit0 = !control_station.alive_control_station[CONTROL_STATION_ZADATCHIK_CAN]; + modbus_table_can_out[207].bit.bit1 = !control_station.alive_control_station[CONTROL_STATION_MPU_SVU_CAN]; + modbus_table_can_out[207].bit.bit2 = 0;// CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,UMU_CAN_DEVICE)]; + modbus_table_can_out[207].bit.bit3 = CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,BKSSD_CAN_DEVICE)]; + modbus_table_can_out[207].bit.bit4 = CAN_timeout[get_real_in_mbox(UNITS_TYPE_BOX,VPU_CAN)]; + modbus_table_can_out[207].bit.bit5 = edrk.warnings.e7.bits.CAN2CAN_BS; + modbus_table_can_out[207].bit.bit6 = edrk.errors.e7.bits.CAN2CAN_BS; + + if (edrk.flag_second_PCH == 1) { + modbus_table_can_out[207].bit.bit7 = edrk.warnings.e4.bits.ANOTHER_BS_POWER_OFF; + } else { + modbus_table_can_out[207].bit.bit8 = edrk.warnings.e4.bits.ANOTHER_BS_POWER_OFF; + } + modbus_table_can_out[207].bit.bit9 = edrk.errors.e7.bits.ANOTHER_BS_ALARM; // ( ) + modbus_table_can_out[207].bit.bit10 = edrk.warnings.e7.bits.READ_OPTBUS; // + + modbus_table_can_out[209].bit.bit0 = edrk.errors.e5.bits.OP_PIT; + modbus_table_can_out[209].bit.bit1 = edrk.errors.e5.bits.UTE4KA_WATER; + modbus_table_can_out[209].bit.bit2 = edrk.errors.e1.bits.BLOCK_DOOR; + modbus_table_can_out[209].bit.bit3 = edrk.errors.e7.bits.UMP_NOT_READY; + modbus_table_can_out[209].bit.bit4 = edrk.errors.e5.bits.FAN; + modbus_table_can_out[209].bit.bit5 = edrk.errors.e5.bits.PUMP_1; + modbus_table_can_out[209].bit.bit6 = edrk.errors.e5.bits.PRE_READY_PUMP; + modbus_table_can_out[209].bit.bit7 = edrk.errors.e5.bits.ERROR_HEAT; + modbus_table_can_out[209].bit.bit8 = edrk.warnings.e5.bits.ERROR_ISOLATE; + modbus_table_can_out[209].bit.bit9 = edrk.errors.e5.bits.ERROR_PRED_VIPR; + modbus_table_can_out[209].bit.bit10 = edrk.errors.e5.bits.ERROR_ISOLATE; + modbus_table_can_out[209].bit.bit11 = edrk.errors.e5.bits.POWER_UPC; + modbus_table_can_out[209].bit.bit12 = edrk.errors.e5.bits.ERROR_GROUND_NET; + modbus_table_can_out[209].bit.bit13 = edrk.errors.e5.bits.PUMP_2; + modbus_table_can_out[209].bit.bit14 = edrk.from_ing1.bits.BLOCK_IZOL_NORMA ? 0 : 1; + + modbus_table_can_out[210].bit.bit0 = edrk.errors.e0.bits.U_1_MAX; + modbus_table_can_out[210].bit.bit1 = edrk.errors.e0.bits.U_2_MAX; + modbus_table_can_out[210].bit.bit2 = edrk.errors.e0.bits.U_1_MIN; + modbus_table_can_out[210].bit.bit3 = edrk.errors.e0.bits.U_2_MIN; + modbus_table_can_out[210].bit.bit4 = edrk.errors.e0.bits.U_A1B1_MAX; + modbus_table_can_out[210].bit.bit5 = edrk.errors.e0.bits.U_A2B2_MAX; + modbus_table_can_out[210].bit.bit6 = edrk.errors.e0.bits.U_B1C1_MAX; + modbus_table_can_out[210].bit.bit7 = edrk.errors.e0.bits.U_B2C2_MAX; + modbus_table_can_out[210].bit.bit8 = edrk.errors.e0.bits.U_A1B1_MIN; + modbus_table_can_out[210].bit.bit9 = edrk.errors.e0.bits.U_A2B2_MIN; + modbus_table_can_out[210].bit.bit10 = edrk.errors.e0.bits.U_B1C1_MIN; + modbus_table_can_out[210].bit.bit11 = edrk.errors.e0.bits.U_B2C2_MIN; + modbus_table_can_out[210].bit.bit12 = edrk.errors.e0.bits.U_IN_MAX; + modbus_table_can_out[210].bit.bit13 = edrk.errors.e0.bits.U_IN_MIN; + + modbus_table_can_out[211].bit.bit0 = edrk.errors.e1.bits.I_UO2_MAX; + modbus_table_can_out[211].bit.bit1 = edrk.errors.e1.bits.I_UO3_MAX; + modbus_table_can_out[211].bit.bit2 = edrk.errors.e1.bits.I_UO4_MAX; + modbus_table_can_out[211].bit.bit3 = edrk.errors.e1.bits.I_UO5_MAX; + modbus_table_can_out[211].bit.bit4 = edrk.errors.e1.bits.I_UO6_MAX; + modbus_table_can_out[211].bit.bit5 = edrk.errors.e1.bits.I_UO7_MAX; + modbus_table_can_out[211].bit.bit6 = edrk.errors.e1.bits.I_BREAK_1_MAX; + modbus_table_can_out[211].bit.bit7 = edrk.errors.e1.bits.I_BREAK_2_MAX; + modbus_table_can_out[211].bit.bit8 = edrk.errors.e0.bits.I_1_MAX; + modbus_table_can_out[211].bit.bit9 = edrk.errors.e0.bits.I_1_MAX; + + modbus_table_can_out[211].bit.bit10 = edrk.warnings.e2.bits.T_AIR0_MAX; + modbus_table_can_out[211].bit.bit11 = edrk.warnings.e2.bits.T_AIR1_MAX; + modbus_table_can_out[211].bit.bit12 = edrk.warnings.e2.bits.T_AIR2_MAX; + modbus_table_can_out[211].bit.bit13 = edrk.warnings.e2.bits.T_AIR3_MAX; + + if (edrk.power_limit.all) + modbus_table_can_out[211].bit.bit14 = 1; + else + modbus_table_can_out[211].bit.bit14 = 0; + + modbus_table_can_out[211].bit.bit15 = edrk.warnings.e10.bits.WARNING_I_OUT_OVER_1_6_NOMINAL; + + modbus_table_can_out[212].bit.bit0 = edrk.errors.e5.bits.ERROR_PRE_CHARGE_ON; + modbus_table_can_out[212].bit.bit1 = edrk.errors.e7.bits.ERROR_SBOR_SHEMA; + + + + + modbus_table_can_out[213].bit.bit0 = project.hwp[0].read.comp_s.plus.bit.ch0; + modbus_table_can_out[213].bit.bit1 = project.hwp[0].read.comp_s.plus.bit.ch1; + modbus_table_can_out[213].bit.bit2 = project.hwp[0].read.comp_s.plus.bit.ch2; + modbus_table_can_out[213].bit.bit3 = project.hwp[0].read.comp_s.plus.bit.ch3; + modbus_table_can_out[213].bit.bit4 = project.hwp[0].read.comp_s.plus.bit.ch4; + modbus_table_can_out[213].bit.bit5 = project.hwp[0].read.comp_s.plus.bit.ch5; + modbus_table_can_out[213].bit.bit6 = project.hwp[0].read.comp_s.plus.bit.ch6; + modbus_table_can_out[213].bit.bit7 = project.hwp[0].read.comp_s.plus.bit.ch7; + modbus_table_can_out[213].bit.bit8 = 0; + modbus_table_can_out[213].bit.bit9 = project.hwp[0].read.comp_s.plus.bit.ch9; + modbus_table_can_out[213].bit.bit10 = project.hwp[0].read.comp_s.plus.bit.ch10; + modbus_table_can_out[213].bit.bit11 = project.hwp[0].read.comp_s.plus.bit.ch11; + modbus_table_can_out[213].bit.bit12 = project.hwp[0].read.comp_s.plus.bit.ch12; + modbus_table_can_out[213].bit.bit13 = project.hwp[0].read.comp_s.plus.bit.ch13; + modbus_table_can_out[213].bit.bit14 = project.hwp[0].read.comp_s.plus.bit.ch14; + modbus_table_can_out[213].bit.bit15 = project.hwp[0].read.comp_s.plus.bit.ch15; + + modbus_table_can_out[214].bit.bit0 = edrk.errors.e5.bits.LINE_ERR0; + modbus_table_can_out[214].bit.bit1 = edrk.errors.e5.bits.LINE_HWP; + modbus_table_can_out[214].bit.bit2 = project.hwp[0].read.comp_s.minus.bit.ch2; + modbus_table_can_out[214].bit.bit3 = project.hwp[0].read.comp_s.minus.bit.ch3; + modbus_table_can_out[214].bit.bit4 = project.hwp[0].read.comp_s.minus.bit.ch4; + modbus_table_can_out[214].bit.bit5 = project.hwp[0].read.comp_s.minus.bit.ch5; + modbus_table_can_out[214].bit.bit6 = project.hwp[0].read.comp_s.minus.bit.ch6; + modbus_table_can_out[214].bit.bit7 = project.hwp[0].read.comp_s.minus.bit.ch7; + modbus_table_can_out[214].bit.bit8 = 0; + modbus_table_can_out[214].bit.bit9 = project.hwp[0].read.comp_s.minus.bit.ch9; + modbus_table_can_out[214].bit.bit10 = project.hwp[0].read.comp_s.minus.bit.ch10; + modbus_table_can_out[214].bit.bit11 = project.hwp[0].read.comp_s.minus.bit.ch11; + modbus_table_can_out[214].bit.bit12 = project.hwp[0].read.comp_s.minus.bit.ch12; + modbus_table_can_out[214].bit.bit13 = project.hwp[0].read.comp_s.minus.bit.ch13; + modbus_table_can_out[214].bit.bit14 = project.hwp[0].read.comp_s.minus.bit.ch14; + modbus_table_can_out[214].bit.bit15 = project.hwp[0].read.comp_s.minus.bit.ch15; + + modbus_table_can_out[215].bit.bit0 = edrk.errors.e8.bits.LOSS_INPUT_A1B1 | edrk.errors.e9.bits.DISBALANCE_Uin_1; //TODO: + modbus_table_can_out[215].bit.bit1 = edrk.errors.e8.bits.LOSS_INPUT_B1C1 | edrk.errors.e9.bits.DISBALANCE_Uin_1; + modbus_table_can_out[215].bit.bit2 = edrk.errors.e8.bits.LOSS_INPUT_A2B2 | edrk.errors.e9.bits.DISBALANCE_Uin_2; + modbus_table_can_out[215].bit.bit3 = edrk.errors.e8.bits.LOSS_INPUT_B2C2 | edrk.errors.e9.bits.DISBALANCE_Uin_2; + modbus_table_can_out[215].bit.bit4 = edrk.errors.e9.bits.U_IN_FREQ_NOT_NORMA; + modbus_table_can_out[215].bit.bit5 = edrk.errors.e9.bits.U_IN_FREQ_NOT_STABLE; + modbus_table_can_out[215].bit.bit6 = edrk.errors.e7.bits.READ_OPTBUS | edrk.errors.e7.bits.WRITE_OPTBUS; + modbus_table_can_out[215].bit.bit7 = edrk.errors.e7.bits.MASTER_SLAVE_SYNC; + modbus_table_can_out[215].bit.bit8 = project.controller.read.errors_buses.bit.err_sbus; + modbus_table_can_out[215].bit.bit9 = project.controller.read.errors.bit.error_pbus || project.controller.read.errors_buses.bit.slave_addr_error + || project.controller.read.errors_buses.bit.count_error_pbus; + modbus_table_can_out[215].bit.bit10 = edrk.errors.e6.bits.ER_DISBAL_BATT; + modbus_table_can_out[215].bit.bit11 = edrk.errors.e6.bits.QTV_ERROR_NOT_U; + modbus_table_can_out[215].bit.bit12 = edrk.errors.e6.bits.ERROR_PRE_CHARGE_U; + modbus_table_can_out[215].bit.bit13 = edrk.errors.e8.bits.U_IN_20_PROCENTS_HIGH; + modbus_table_can_out[215].bit.bit14 = edrk.errors.e8.bits.U_IN_10_PROCENTS_LOW; + modbus_table_can_out[215].bit.bit15 = edrk.errors.e8.bits.U_IN_20_PROCENTS_LOW; + + modbus_table_can_out[216].bit.bit0 = project.cds_tk[0].read.sbus.lock_status_error.bit.err_power; + modbus_table_can_out[216].bit.bit1 = project.cds_tk[1].read.sbus.lock_status_error.bit.err_power; + modbus_table_can_out[216].bit.bit2 = project.cds_tk[2].read.sbus.lock_status_error.bit.err_power; + modbus_table_can_out[216].bit.bit3 = project.cds_tk[3].read.sbus.lock_status_error.bit.err_power; + modbus_table_can_out[216].bit.bit4 = project.cds_in[0].read.sbus.lock_status_error.bit.err_power; + modbus_table_can_out[216].bit.bit5 = project.cds_in[1].read.sbus.lock_status_error.bit.err_power; + modbus_table_can_out[216].bit.bit6 = project.cds_out[0].read.sbus.lock_status_error.bit.err_power; + modbus_table_can_out[216].bit.bit7 = edrk.errors.e7.bits.NOT_VALID_CONTROL_STATION; + modbus_table_can_out[216].bit.bit8 = edrk.errors.e8.bits.LOSS_OUTPUT_U1; + modbus_table_can_out[216].bit.bit9 = edrk.errors.e8.bits.LOSS_OUTPUT_V1; + modbus_table_can_out[216].bit.bit10 = edrk.errors.e8.bits.LOSS_OUTPUT_W1; + modbus_table_can_out[216].bit.bit11 = edrk.errors.e8.bits.LOSS_OUTPUT_U2; + modbus_table_can_out[216].bit.bit12 = edrk.errors.e8.bits.LOSS_OUTPUT_V2; + modbus_table_can_out[216].bit.bit13 = edrk.errors.e8.bits.LOSS_OUTPUT_W2; + modbus_table_can_out[216].bit.bit14 = edrk.errors.e8.bits.DISBALANCE_IM1_IM2; + modbus_table_can_out[216].bit.bit15 = edrk.errors.e7.bits.VERY_FAST_GO_0to1; + + modbus_table_can_out[217].bit.bit0 = project.cds_tk[0].read.sbus.lock_status_error.bit.err_switch; + modbus_table_can_out[217].bit.bit1 = project.cds_tk[1].read.sbus.lock_status_error.bit.err_switch; + modbus_table_can_out[217].bit.bit2 = project.cds_tk[2].read.sbus.lock_status_error.bit.err_switch; + modbus_table_can_out[217].bit.bit3 = project.cds_tk[3].read.sbus.lock_status_error.bit.err_switch; + modbus_table_can_out[217].bit.bit4 = project.cds_in[0].read.sbus.lock_status_error.bit.err_switch; + modbus_table_can_out[217].bit.bit5 = project.cds_in[1].read.sbus.lock_status_error.bit.err_switch; + modbus_table_can_out[217].bit.bit6 = project.cds_out[0].read.sbus.lock_status_error.bit.err_switch; + modbus_table_can_out[217].bit.bit7 = project.adc[0].read.sbus.lock_status_error.bit.err_switch; + modbus_table_can_out[217].bit.bit8 = 0; + modbus_table_can_out[217].bit.bit9 = project.adc[1].read.sbus.lock_status_error.bit.err_switch; + + modbus_table_can_out[218].bit.bit0 = edrk.warnings.e2.bits.T_UO1_MAX; + modbus_table_can_out[218].bit.bit1 = edrk.warnings.e2.bits.T_UO2_MAX; + modbus_table_can_out[218].bit.bit2 = edrk.warnings.e2.bits.T_UO3_MAX; + modbus_table_can_out[218].bit.bit3 = edrk.warnings.e2.bits.T_UO4_MAX; + modbus_table_can_out[218].bit.bit4 = edrk.warnings.e2.bits.T_UO5_MAX; + modbus_table_can_out[218].bit.bit5 = edrk.warnings.e2.bits.T_UO6_MAX; + modbus_table_can_out[218].bit.bit6 = edrk.warnings.e2.bits.T_UO7_MAX; + modbus_table_can_out[218].bit.bit7 = edrk.errors.e2.bits.T_UO1_MAX; + modbus_table_can_out[218].bit.bit8 = edrk.errors.e2.bits.T_UO2_MAX; + modbus_table_can_out[218].bit.bit9 = edrk.errors.e2.bits.T_UO3_MAX; + modbus_table_can_out[218].bit.bit10 = edrk.errors.e2.bits.T_UO4_MAX; + modbus_table_can_out[218].bit.bit11 = edrk.errors.e2.bits.T_UO5_MAX; + modbus_table_can_out[218].bit.bit12 = edrk.errors.e2.bits.T_UO6_MAX; + modbus_table_can_out[218].bit.bit13 = edrk.errors.e2.bits.T_UO7_MAX; + + modbus_table_can_out[219].bit.bit0 = edrk.warnings.e7.bits.READ_OPTBUS | edrk.warnings.e7.bits.WRITE_OPTBUS; + modbus_table_can_out[219].bit.bit1 = edrk.warnings.e7.bits.MASTER_SLAVE_SYNC; + modbus_table_can_out[219].bit.bit2 = edrk.errors.e6.bits.ERROR_PRE_CHARGE_ANSWER; + modbus_table_can_out[219].bit.bit3 = edrk.warnings.e1.bits.NO_INPUT_SYNC_SIGNAL; + modbus_table_can_out[219].bit.bit4 = edrk.errors.e1.bits.NO_INPUT_SYNC_SIGNAL; + modbus_table_can_out[219].bit.bit5 = edrk.errors.e3.bits.ERR_INT_PWM_LONG + || edrk.errors.e9.bits.ERR_PWM_WDOG + || edrk.errors.e9.bits.ERR_INT_PWM_VERY_LONG; + modbus_table_can_out[219].bit.bit15 = edrk.errors.e5.bits.T_VIPR_MAX; + + modbus_table_can_out[220].bit.bit0 = edrk.errors.e2.bits.T_AIR0_MAX; + modbus_table_can_out[220].bit.bit1 = edrk.errors.e2.bits.T_AIR1_MAX; + modbus_table_can_out[220].bit.bit2 = edrk.errors.e2.bits.T_AIR2_MAX; + modbus_table_can_out[220].bit.bit3 = edrk.errors.e2.bits.T_AIR3_MAX; + modbus_table_can_out[220].bit.bit4 = edrk.warnings.e10.bits.T_BSU_Sensor_BK1; + modbus_table_can_out[220].bit.bit5 = edrk.errors.e10.bits.T_BSU_Sensor_BK1; + modbus_table_can_out[220].bit.bit6 = edrk.warnings.e10.bits.T_BSU_Sensor_BK2; + modbus_table_can_out[220].bit.bit7 = edrk.errors.e10.bits.T_BSU_Sensor_BK2; + + modbus_table_can_out[220].bit.bit8 = edrk.errors.e2.bits.T_WATER_EXT_MAX; + modbus_table_can_out[220].bit.bit9 = edrk.errors.e2.bits.T_WATER_INT_MAX; + modbus_table_can_out[220].bit.bit10 = edrk.warnings.e2.bits.T_WATER_EXT_MAX; + modbus_table_can_out[220].bit.bit11 = edrk.warnings.e2.bits.T_WATER_INT_MAX; + + modbus_table_can_out[220].bit.bit12 = edrk.errors.e7.bits.T_ACDRIVE_BEAR_MAX_DNE; + modbus_table_can_out[220].bit.bit13 = edrk.errors.e9.bits.T_ACDRIVE_BEAR_MAX_NE; + modbus_table_can_out[220].bit.bit14 = edrk.warnings.e7.bits.T_ACDRIVE_BEAR_MAX_DNE; + modbus_table_can_out[220].bit.bit15 = edrk.warnings.e9.bits.T_ACDRIVE_BEAR_MAX_NE; + + modbus_table_can_out[221].bit.bit0 = edrk.errors.e10.bits.T_ACDRIVE_WINDING_U1; + modbus_table_can_out[221].bit.bit1 = edrk.errors.e10.bits.T_ACDRIVE_WINDING_V1; + modbus_table_can_out[221].bit.bit2 = edrk.errors.e10.bits.T_ACDRIVE_WINDING_W1; + modbus_table_can_out[221].bit.bit3 = edrk.errors.e10.bits.T_ACDRIVE_WINDING_U2; + modbus_table_can_out[221].bit.bit4 = edrk.errors.e10.bits.T_ACDRIVE_WINDING_V2; + modbus_table_can_out[221].bit.bit5 = edrk.errors.e10.bits.T_ACDRIVE_WINDING_W2; + modbus_table_can_out[221].bit.bit6 = edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U1; + modbus_table_can_out[221].bit.bit7 = edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V1; + modbus_table_can_out[221].bit.bit8 = edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W1; + modbus_table_can_out[221].bit.bit9 = edrk.warnings.e10.bits.T_ACDRIVE_WINDING_U2; + modbus_table_can_out[221].bit.bit10 = edrk.warnings.e10.bits.T_ACDRIVE_WINDING_V2; + modbus_table_can_out[221].bit.bit11 = edrk.warnings.e10.bits.T_ACDRIVE_WINDING_W2; + + modbus_table_can_out[222].bit.bit0 = edrk.errors.e2.bits.P_WATER_INT_MAX; + modbus_table_can_out[222].bit.bit1 = edrk.errors.e2.bits.P_WATER_INT_MIN; + modbus_table_can_out[222].bit.bit2 = edrk.warnings.e2.bits.P_WATER_INT_MAX; + modbus_table_can_out[222].bit.bit3 = edrk.warnings.e2.bits.P_WATER_INT_MIN; + + + modbus_table_can_out[223].all = edrk.errors.e11.all; + + + +} + +void update_protect_levels_to_MPU() { + modbus_table_can_out[139].all = protect_levels.abnormal_temper_acdrive_winding_U1 / 10; + modbus_table_can_out[140].all = protect_levels.abnormal_temper_acdrive_winding_V1 / 10; + modbus_table_can_out[141].all = protect_levels.abnormal_temper_acdrive_winding_W1 / 10; + modbus_table_can_out[142].all = protect_levels.abnormal_temper_acdrive_winding_U2 / 10; + modbus_table_can_out[143].all = protect_levels.abnormal_temper_acdrive_winding_V2 / 10; + modbus_table_can_out[144].all = protect_levels.abnormal_temper_acdrive_winding_W2 / 10; + modbus_table_can_out[145].all = protect_levels.abnormal_temper_acdrive_bear_DNE / 10; + modbus_table_can_out[146].all = protect_levels.abnormal_temper_acdrive_bear_NE / 10; + + modbus_table_can_out[147].all = protect_levels.alarm_temper_acdrive_winding_U1 / 10; + modbus_table_can_out[148].all = protect_levels.alarm_temper_acdrive_winding_V1 / 10; + modbus_table_can_out[149].all = protect_levels.alarm_temper_acdrive_winding_W1 / 10; + modbus_table_can_out[150].all = protect_levels.alarm_temper_acdrive_winding_U2 / 10; + modbus_table_can_out[151].all = protect_levels.alarm_temper_acdrive_winding_V2 / 10; + modbus_table_can_out[152].all = protect_levels.alarm_temper_acdrive_winding_W2 / 10; + modbus_table_can_out[153].all = protect_levels.alarm_temper_acdrive_bear_DNE / 10; + modbus_table_can_out[154].all = protect_levels.alarm_temper_acdrive_bear_NE / 10; + + modbus_table_can_out[155].all = protect_levels.abnormal_temper_u_01 / 10; + modbus_table_can_out[156].all = protect_levels.abnormal_temper_u_02 / 10; + modbus_table_can_out[157].all = protect_levels.abnormal_temper_u_03 / 10; + modbus_table_can_out[158].all = protect_levels.abnormal_temper_u_04 / 10; + modbus_table_can_out[159].all = protect_levels.abnormal_temper_u_05 / 10; + modbus_table_can_out[160].all = protect_levels.abnormal_temper_u_06 / 10; + modbus_table_can_out[161].all = protect_levels.abnormal_temper_u_07 / 10; + modbus_table_can_out[162].all = protect_levels.alarm_temper_u_01 / 10; + modbus_table_can_out[163].all = protect_levels.alarm_temper_u_02 / 10; + modbus_table_can_out[164].all = protect_levels.alarm_temper_u_03 / 10; + modbus_table_can_out[165].all = protect_levels.alarm_temper_u_04 / 10; + modbus_table_can_out[166].all = protect_levels.alarm_temper_u_05 / 10; + modbus_table_can_out[167].all = protect_levels.alarm_temper_u_06 / 10; + modbus_table_can_out[168].all = protect_levels.alarm_temper_u_07 / 10; + + modbus_table_can_out[169].all = protect_levels.abnormal_temper_water_ext / 10; + modbus_table_can_out[170].all = protect_levels.abnormal_temper_water_int / 10; + modbus_table_can_out[171].all = protect_levels.alarm_p_water_min_int / 100; + modbus_table_can_out[172].all = protect_levels.alarm_temper_water_int / 10; + modbus_table_can_out[173].all = protect_levels.alarm_temper_water_ext / 10; + modbus_table_can_out[174].all = protect_levels.alarm_p_water_max_int / 100; + + modbus_table_can_out[175].all = protect_levels.abnormal_temper_air_int_01 / 10; + modbus_table_can_out[176].all = protect_levels.abnormal_temper_air_int_02 / 10; + modbus_table_can_out[177].all = protect_levels.abnormal_temper_air_int_03 / 10; + modbus_table_can_out[178].all = protect_levels.abnormal_temper_air_int_04 / 10; + modbus_table_can_out[179].all = protect_levels.alarm_temper_air_int_01 / 10; + modbus_table_can_out[180].all = protect_levels.alarm_temper_air_int_02 / 10; + modbus_table_can_out[181].all = protect_levels.alarm_temper_air_int_03 / 10; + modbus_table_can_out[182].all = protect_levels.alarm_temper_air_int_04 / 10; + + modbus_table_can_out[183].all = _IQtoF(analog_protect.in_voltage[0].setup.levels.iqNominal_minus20) * NORMA_ACP;//_IQtoF(edrk.iqMIN_U_IN) * NORMA_ACP; + modbus_table_can_out[184].all = _IQtoF(analog_protect.in_voltage[1].setup.levels.iqNominal_minus20) * NORMA_ACP; + modbus_table_can_out[185].all = _IQtoF(analog_protect.in_voltage[0].setup.levels.iqNominal_plus20) * NORMA_ACP;//_IQtoF(edrk.iqMIN_U_ZPT) * NORMA_ACP; + modbus_table_can_out[186].all = _IQtoF(analog_protect.in_voltage[1].setup.levels.iqNominal_plus20) * NORMA_ACP; + modbus_table_can_out[187].all = //_IQtoF(edrk.iqMAX_U_IN) * NORMA_ACP; + modbus_table_can_out[188].all = _IQtoF(edrk.iqMAX_U_IN) * NORMA_ACP; + modbus_table_can_out[189].all = //_IQtoF(edrk.iqMAX_U_ZPT) * NORMA_ACP; + modbus_table_can_out[190].all = _IQtoF(edrk.iqMAX_U_ZPT) * NORMA_ACP; + + modbus_table_can_out[191].all = protect_levels.alarm_Izpt_max; + + modbus_table_can_out[192].all = protect_levels.alarm_Imax_U01; + modbus_table_can_out[193].all = protect_levels.alarm_Imax_U02; + modbus_table_can_out[194].all = protect_levels.alarm_Imax_U03; + modbus_table_can_out[195].all = protect_levels.alarm_Imax_U04; + modbus_table_can_out[196].all = protect_levels.alarm_Imax_U05; + modbus_table_can_out[197].all = protect_levels.alarm_Imax_U06; + modbus_table_can_out[198].all = protect_levels.alarm_Imax_U07; + modbus_table_can_out[199].all = protect_levels.alarm_Iged_max; +} diff --git a/Inu/Src2/551/main/modbus_svu_update.h b/Inu/Src2/551/main/modbus_svu_update.h new file mode 100644 index 0000000..d58d103 --- /dev/null +++ b/Inu/Src2/551/main/modbus_svu_update.h @@ -0,0 +1,17 @@ +/* + * modbus_update_table.h + * + * Created on: 4 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_MODBUS_SVU_UPDATE_H_ +#define SRC_MAIN_MODBUS_SVU_UPDATE_H_ + + + +void update_svu_modbus_table(void); +void unpack_answer_from_MPU_SVU_CAN(unsigned int cc); +void unpack_answer_from_MPU_SVU_RS(unsigned int cc); + +#endif /* SRC_MAIN_MODBUS_SVU_UPDATE_H_ */ diff --git a/Inu/Src2/551/main/not_use/log_to_mem.c b/Inu/Src2/551/main/not_use/log_to_mem.c new file mode 100644 index 0000000..8a5c223 --- /dev/null +++ b/Inu/Src2/551/main/not_use/log_to_mem.c @@ -0,0 +1,249 @@ +/****************************************************************/ +/* TMS320C32 */ +/* ====== BIOS, , ====== */ +/* () 1998-2001. */ +/****************************************************************/ +/* log_to_mem.c + **************************************************************** + * y * + ****************************************************************/ + +#include + +#include "MemoryFunctions.h" + + +// +// / logs_data(), write_to_mem clear_mem +// y y (. / write_to_mem) +//#pragma DATA_SECTION(count_mem,".fast_vars"); +//static long count_mem = START_ADDRESS_LOG; + +#pragma DATA_SECTION(count_mem_slow,".fast_vars"); +static long count_mem_slow = START_ADDRESS_LOG_SLOW; + + +// y y +// y +int hb_logs_data = 0; +#pragma DATA_SECTION(stop_log,".fast_vars"); +int stop_log = 0; +int stop_log_slow = 0; + + +#pragma DATA_SECTION(logpar,".fast_vars"); +LOGSPARAMS logpar = LOGSPARAMS_DEFAULTS; + +#pragma DATA_SECTION(no_write,".fast_vars"); +int no_write = 0; // , ( ) +#pragma DATA_SECTION(no_write_slow,".fast_vars"); +int no_write_slow = 0; // , ( ) + +#pragma CODE_SECTION(clear_logpar,".fast_run"); +void clear_logpar() +{ + int i; + for(i=0;i= END_ADDRESS_LOG) logpar.addres_mem = END_ADDRESS_LOG; + + i_WriteMemory(logpar.addres_mem,DataM); + // *(int *)logpar.count_mem = ((DataM & 0xFFFF) ); + logpar.addres_mem++; + } + + if (tlog==SLOW_LOG) + { + if (no_write_slow) return; + + if (logpar.stop_log_slow_level_1) return; + + if (count_mem_slow >= END_ADDRESS_LOG_SLOW) count_mem_slow = END_ADDRESS_LOG_SLOW; + + i_WriteMemory(count_mem_slow,DataM); + // *(int *)logpar.count_mem = ((DataM & 0xFFFF) ); + count_mem_slow++; + } + + + + +} + + +#pragma CODE_SECTION(test_mem_limit,".fast_run"); +void test_mem_limit(int tlog,int ciclelog) +{ + if (tlog==FAST_LOG) + { + if( logpar.addres_mem >= (END_ADDRESS_LOG - LENGTH_HAZARD)) + { + logpar.real_finish_addres_mem = logpar.addres_mem; + + if (ciclelog==1) + { + stop_log = 0; + logpar.stop_log_level_1=0; + logpar.addres_mem = START_ADDRESS_LOG; + } + else + { + stop_log = 1; + logpar.stop_log_level_1=1; + } + } + + if( logpar.addres_mem >= (END_ADDRESS_LOG_LEVEL_2)) + { + logpar.stop_log_level_2=1; + } + else + { + logpar.stop_log_level_2=0; + } + + if( logpar.addres_mem >= (END_ADDRESS_LOG_LEVEL_3)) + { + logpar.stop_log_level_3=1; + } + else + { + logpar.stop_log_level_3=0; + } + } + else + { + if (tlog==SLOW_LOG) + { + if (ciclelog==1) + { + logpar.stop_log_slow_level_1=0; + } + + if( count_mem_slow >= (END_ADDRESS_LOG_SLOW - LENGTH_HAZARD)) + { + if (ciclelog==1) + { + stop_log_slow = 0; + logpar.stop_log_slow_level_1=0; + count_mem_slow = START_ADDRESS_LOG_SLOW; + } + else + { + stop_log_slow = 1; + logpar.stop_log_slow_level_1=1; + } + } + + if( count_mem_slow >= (END_ADDRESS_LOG_SLOW_LEVEL_2)) + { + logpar.stop_log_slow_level_2=1; + } + else + { + logpar.stop_log_slow_level_2=0; + } + + if( count_mem_slow >= (END_ADDRESS_LOG_SLOW_LEVEL_3)) + { + logpar.stop_log_slow_level_3=1; + } + else + { + logpar.stop_log_slow_level_3=0; + } + } + } +} + + + +// y, +void clear_mem(int tlog) +{ + if (tlog==FAST_LOG) + { + logpar.real_finish_addres_mem = 0; + + for (logpar.addres_mem=START_ADDRESS_LOG; logpar.addres_mem +#include +#include +#include +#include +#include + +#include "IQmathLib.h" +#include "xp_project.h" + + +OPTICAL_BUS_DATA optical_write_data = OPTICAL_BUS_DATA_DEFAULT; +OPTICAL_BUS_DATA optical_read_data = OPTICAL_BUS_DATA_DEFAULT; + +void parse_task_from_optical_bus(void); + + +#pragma CODE_SECTION(optical_bus_update_data_write,".fast_run"); +void optical_bus_update_data_write(void) +{ + + optical_write_data.data.cmd.bit.alarm = edrk.summ_errors; + + optical_write_data.data.cmd.bit.master = edrk.auto_master_slave.local.bits.master; + optical_write_data.data.cmd.bit.slave = edrk.auto_master_slave.local.bits.slave; + optical_write_data.data.cmd.bit.maybe_master = edrk.auto_master_slave.local.bits.try_master; + + +// optical_write_data.cmd.bit.controlMode = ; + +// optical_write_data.cmd.bit.err_optbus = +// optical_write_data.cmd.bit.master = +// optical_write_data.cmd.bit.maybe_master = +// optical_write_data.cmd.bit.pwm_status = +// + + if (edrk.Status_Rascepitel_Ok==0) + { + if (edrk.RunZahvatRascepitel) + optical_write_data.data.cmd.bit.rascepitel_cmd = CODE_RASCEPITEL_CMD_REQUEST_AND_THIS_OFF;// 10 - , + else + optical_write_data.data.cmd.bit.rascepitel_cmd = CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_OFF;//00 - , + } + else + { + + if (edrk.Status_Ready.bits.ready_final==0) // + { + if (edrk.RunUnZahvatRascepitel) + optical_write_data.data.cmd.bit.rascepitel_cmd = CODE_RASCEPITEL_CMD_REQUEST_AND_THIS_OFF;// 10 - , + else + optical_write_data.data.cmd.bit.rascepitel_cmd = CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_ON;// 01 - , + } + else + { + if (edrk.you_can_on_rascepitel==0) + optical_write_data.data.cmd.bit.rascepitel_cmd = CODE_RASCEPITEL_CMD_DISABLE_THIS_ON; // 11 - , + else + optical_write_data.data.cmd.bit.rascepitel_cmd = CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_ON; // 01 - , + } + } + + if (edrk.Status_Ready.bits.ready7 || (edrk.Status_Ready.bits.ready5 && edrk.Status_Ready.bits.ImitationReady2) ) + optical_write_data.data.cmd.bit.ready_cmd = CODE_READY_CMD_READY2; + else + if (edrk.SumSbor) + optical_write_data.data.cmd.bit.ready_cmd = CODE_READY_CMD_READY1TO2; + else + optical_write_data.data.cmd.bit.ready_cmd = CODE_READY_CMD_READY1; + +// optical_write_data.cmd.bit.ready_to_go = +// optical_write_data.cmd.bit.slave = +// +// optical_write_data.cmd.bit.start_pwm = + optical_write_data.data.cmd.bit.statusQTV = edrk.from_shema_filter.bits.QTV_ON_OFF; +// optical_write_data.cmd.bit.stop_pwm = + + optical_write_data.data.cmd.bit.sync_1_2 = sync_data.local_flag_sync_1_2; + optical_write_data.data.cmd.bit.sync_line_detect = !sync_data.timeout_sync_signal; + +// optical_write_data.data1 = f.Mode == 1 ? f.fzad * 60.0 + 0.5 : +// f.Mode == 2 ? f.p_zad / 1000.0 : +// 0; +// optical_write_data.data2 = rotor.direct_rotor == -1 ? -_IQtoIQ15(rotor.iqFout) : +// _IQtoIQ15(rotor.iqFout); +// optical_write_data.data3 = _IQtoIQ15(analog.iqIq_zadan); +// optical_write_data.data4.bit.controlMode = f.Mode == 2 ? 1 : 0; +// optical_write_data.data4.bit.leading_ready = f.Ready2 && (f.Mode == 1 || f.Mode == 2) ? 1 : 0; +// optical_write_data.data4.bit.leading_Go = edrk.Go; + + + +} + + + +#pragma CODE_SECTION(optical_bus_write,".fast_run"); +void optical_bus_write(void) +{ +#if(USE_TK_3) + // check error write PBUS OPTICAL BUS + project.cds_tk[3].optical_bus_check_error_write(&project.cds_tk[3]); + + // write data to OPTICAL BUS + project.cds_tk[3].optical_data_out.buf[0] = optical_write_data.data.pzad_or_wzad; + project.cds_tk[3].optical_data_out.buf[1] = optical_write_data.data.angle_pwm; + project.cds_tk[3].optical_data_out.buf[2] = optical_write_data.data.iq_zad_i_zad; + project.cds_tk[3].optical_data_out.buf[3] = optical_write_data.data.cmd.all; + + optical_write_data.status = 1; + + + project.cds_tk[3].optical_bus_write_data(&project.cds_tk[3]); +#endif +} + + + + + +#pragma CODE_SECTION(optical_bus_read_old,".fast_run"); +void optical_bus_read_old(void) +{ + +// // check error write PBUS OPTICAL BUS +// project.cds_tk[3].optical_bus_check_error_write(&project.cds_tk[3]); +//// read data from OPTICAL BUS +// project.cds_tk[3].read_pbus(&project.cds_tk[3]); +// // check error read PBUS OPTICAL BUS +// project.cds_tk[3].optical_bus_check_error_read(&project.cds_tk[3]); +// +// +// if (project.cds_tk[3].optical_data_in.new_data_ready) +// { +// if (project.cds_tk[3].optical_data_in.overfull_new_data) +// optical_read_data.overfull_data++; +// +// optical_read_data.raw.pzad_or_wzad = (int)project.cds_tk[3].optical_data_in.buf[0]; +// optical_read_data.raw.angle_pwm = (int)project.cds_tk[3].optical_data_in.buf[1]; +// optical_read_data.raw.iq_zad = (int)project.cds_tk[3].optical_data_in.buf[2]; +// optical_read_data.raw.cmd.all = project.cds_tk[3].optical_data_in.buf[3]; +// +// +// optical_read_data.data.pzad_or_wzad = optical_read_data.raw.pzad_or_wzad; +// optical_read_data.data.angle_pwm = optical_read_data.raw.angle_pwm ; +// optical_read_data.data.iq_zad = optical_read_data.raw.iq_zad; +// optical_read_data.data.cmd.all = optical_read_data.raw.cmd.all; +// +// optical_read_data.code_status.bit.ready = 1; +// optical_read_data.code_status.bit.recive_error = 0; +// optical_read_data.code_status.bit.overfull = 0; +// optical_read_data.code_status.bit.timeout = 0; +// optical_read_data.code_status.bit.wait = 0; +// +// project.cds_tk[3].optical_data_in.new_data_ready = 0; +// +// return (optical_read_data.code_status); +// +// } +// else +// { +// +// if (project.cds_tk[3].optical_data_in.ready == 1) +// { +// optical_read_data.code_status.bit.ready = 0; +// +// if (project.cds_tk[3].optical_data_in.raw_local_error) +// optical_read_data.code_status.bit.recive_error = 1; +// else +// optical_read_data.code_status.bit.recive_error = 0; +// +// optical_read_data.code_status.bit.overfull = 0; +// optical_read_data.code_status.bit.timeout = 0; +// optical_read_data.code_status.bit.wait = 1; +// +// return (optical_read_data.code_status); +// } +// +// } +// +// +// if (project.cds_tk[3].optical_data_out.ready == 0) { +// +// project.cds_tk[3].optical_data_out.error_not_ready_count += 1; +// +//// optical_read_data.code_status.bit.ready = 0; +// optical_read_data.code_status.bit.send_error = 1; +//// optical_read_data.code_status.bit.overfull = 0; +//// optical_read_data.code_status.bit.timeout = 0; +//// optical_read_data.code_status.bit.wait = 0; +// +//// optical_write_data.status = 2; +//// return (optical_read_data.code_status); +// } +// else +// optical_read_data.code_status.bit.send_error = 0; +// +// +// if (project.cds_tk[3].optical_data_in.ready == 0) { +// +//// f.read_task_from_optical_bus = 0; +// project.cds_tk[3].optical_data_in.error_not_ready_count += 1; +// +// optical_read_data.code_status.bit.ready = 0; +// // optical_read_data.code_status.bit.send_error = 0; +// //optical_read_data.code_status.bit.recive_error = 1; +// optical_read_data.code_status.bit.overfull = 0; +// optical_read_data.code_status.bit.timeout = 1; +// optical_read_data.code_status.bit.wait = 0; +// +// optical_read_data.data.pzad_or_wzad = 0; +// optical_read_data.data.angle_pwm = 0; +// optical_read_data.data.iq_zad = 0; +// optical_read_data.data.cmd.all = 0; +// +// // optical_read_data.status = 2; +// +// // return (project.cds_tk[3].optical_data_in.raw_local_error); +// } +// else +// { +// +// +// +// } +// +// return (optical_read_data.code_status); +// +// +//// optical_read_data.status = 1; +// +// // return (project.cds_tk[3].optical_data_in.raw_local_error); +// +//// if (f.flag_leading == 0 && f.flag_distance && f.Ready1){ +//// parse_task_from_optical_bus(); +//// } else { +//// f.read_task_from_optical_bus = 0; +//// } +//// rotor.iqFrotFromOptica = _IQ15toIQ(optical_read_data.data2); //Frot +//// analog.iqIq_zad_from_optica = _IQ15toIQ(optical_read_data.data3); + +} + + +#pragma CODE_SECTION(optical_bus_read,".fast_run"); +void optical_bus_read(void) +{ + + // check error write PBUS OPTICAL BUS +// project.cds_tk[3].optical_bus_check_error_write(&project.cds_tk[3]); +// read data from OPTICAL BUS +#if(USE_TK_3) + project.cds_tk[3].read_pbus(&project.cds_tk[3]); +#endif + + return; +} + +#pragma CODE_SECTION(optical_bus_read_clear_count_error,".fast_run"); +void optical_bus_read_clear_count_error(void) +{ +#if(USE_TK_3) + project.cds_tk[3].optical_data_in.local_count_error = 0; +#endif + + return; +} + + + +#pragma CODE_SECTION(optical_bus_get_status_and_read,".fast_run"); +STATUS_DATA_READ_OPT_BUS optical_bus_get_status_and_read(void) +{ + STATUS_DATA_READ_OPT_BUS status_read; + // check error write PBUS OPTICAL BUS + // project.cds_tk[3].optical_bus_check_error_write(&project.cds_tk[3]); +// read data from OPTICAL BUS +// project.cds_tk[3].read_pbus(&project.cds_tk[3]); + +#if(USE_TK_3) + // check error read PBUS OPTICAL BUS + project.cds_tk[3].optical_bus_check_error_read(&project.cds_tk[3]); + + status_read.all = project.cds_tk[3].optical_data_in.status_read.all; + + project.cds_tk[3].optical_data_in.prev_status_read.all = status_read.all; + project.cds_tk[3].optical_data_in.status_read.all = 0; + + optical_read_data.status = project.cds_tk[3].optical_data_in.ready; + + + if (status_read.bit.new_data_ready) + { + if (status_read.bit.overfull_new_data) + optical_read_data.overfull_data++; + + optical_read_data.raw.pzad_or_wzad = (int)project.cds_tk[3].optical_data_in.buf[0]; + optical_read_data.raw.angle_pwm = (int)project.cds_tk[3].optical_data_in.buf[1]; + optical_read_data.raw.iq_zad_i_zad = (int)project.cds_tk[3].optical_data_in.buf[2]; + optical_read_data.raw.cmd.all = project.cds_tk[3].optical_data_in.buf[3]; + + + optical_read_data.data.pzad_or_wzad = optical_read_data.raw.pzad_or_wzad; + optical_read_data.data.angle_pwm = optical_read_data.raw.angle_pwm ; + optical_read_data.data.iq_zad_i_zad = optical_read_data.raw.iq_zad_i_zad; + optical_read_data.data.cmd.all = optical_read_data.raw.cmd.all; + + + return (status_read); // + + } + else + { + // ? + // optical_bus, ! + +// optical_read_data.data.pzad_or_wzad = 0; +// optical_read_data.data.angle_pwm = 0; +// optical_read_data.data.iq_zad_i_zad = 0; +// optical_read_data.data.cmd.all = 0; + + + + } +#else + status_read.all = 0; +#endif + return status_read; // + +} + + + + +void parse_task_from_optical_bus(void) { + + // if (optical_read_data.data4.bit.leading_ready == 1) { +// f.read_task_from_optical_bus = 1; +// f.Mode = optical_read_data.data4.bit.controlMode == 0 ? 1 : 2; +// if (f.Mode == 1) { +// f.fzad = (float)optical_read_data.data1 / 60.0; +// f.iq_fzad = _IQ(f.fzad / NORMA_FROTOR); +// limit_mzz_zad_turns(); +// } +// if (f.Mode == 2) { +// f.p_zad = (float)optical_read_data.data1 * 1000.0; +// f.iq_p_zad = _IQ(f.p_zad/NORMA_ACP/NORMA_ACP); +// // +// if (f.iq_p_zad > f.iq_p_limit_zad) { f.iq_p_zad = f.iq_p_limit_zad;} +// if (f.iq_p_zad < -f.iq_p_limit_zad) { f.iq_p_zad = -f.iq_p_limit_zad;} +// +// limit_mzz_zad_power(); +// } + +// if (f.Ready1 && f.Ready2) { +// if (((f.Mode == 1 && f.fzad != 0) || (f.Mode == 2 && f.p_zad != 0)) +// && (!f.Is_Blocked || (f.Is_Blocked && edrk.Go)) +// && (f.rotor_stopped == 0) +//// && (faults.faults5.bit.rotor_stopped == 0) +// //&& (optical_read_data.data4.bit.leading_Go == 1) +// ){ +// edrk.Go = 1; +// } else { +// if (edrk.Go) { +// f.p_zad = 0; +// f.fzad = 0; +// f.iq_fzad = 0; +// f.iq_p_zad = 0; +// if(f.Mode == 1) +// { +// if(a.iqk < 1677722 || rotor.iqFout < 48210 //1677722 ~ 0.1 503316 = 3% 838860 = 5% +// || (analog.iqIm_1 < 1677721 && analog.iqIm_2 < 1677721)) //1677721 ~ 300A +// { +// edrk.Go = 0; +// f.iq_fzad = 0; +// } +// +// } +// if(edrk.Go && f.Mode == 2) +// { +// if(analog.iqW < 186413) +// { +// if(a.iqk < 1677722 || //1677722 ~ 0.1 +// (analog.iqIm_1 < 1677721 && analog.iqIm_2 < 1677721)) //1677721 ~ 300A +// { +// edrk.Go = 0; +// } +// } +// } +// +// } else { +// f.iq_mzz_zad = _IQ(500.0/NORMA_MZZ); +// } +// } +// } else { +// edrk.Go = 0; +// } + + + // _IQ15toIQ(optical_read_data.data3); //Iq_zad +// } else { + // f.read_task_from_optical_bus = 0; +// } + +} + diff --git a/Inu/Src2/551/main/optical_bus.h b/Inu/Src2/551/main/optical_bus.h new file mode 100644 index 0000000..ce30d7c --- /dev/null +++ b/Inu/Src2/551/main/optical_bus.h @@ -0,0 +1,109 @@ +/* + * optical_bus.h + * + * Created on: 18 . 2020 . + * Author: stud + */ + +#ifndef SRC_MAIN_OPTICAL_BUS_H_ +#define SRC_MAIN_OPTICAL_BUS_H_ + +#include "xp_cds_tk_23550.h" + +enum +{ +CODE_READY_CMD_NOT_READY=0, //// 0 - not ready +CODE_READY_CMD_READY1, //1-ready1 +CODE_READY_CMD_READY1TO2, //2-ready1to2 +CODE_READY_CMD_READY2 //3 -ready2 +}; + +enum +{ + CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_OFF=0, //0 - , + CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_ON, // 1 - , + CODE_RASCEPITEL_CMD_REQUEST_AND_THIS_OFF, // 2 - , + CODE_RASCEPITEL_CMD_DISABLE_THIS_ON // 3 - , +}; + + + typedef union { + struct { + unsigned int wdog_tick :1; // 0_1_0 .. + unsigned int statusQTV :1; //1-QTV On, QTV - off + unsigned int master :1; // 1 -Master, 0 - not Master + unsigned int slave :1; // 1 -Slave, 0 - not Slave + + unsigned int sync_line_detect :1; // 1 - yes, 0 - no + unsigned int sync_1_2 :1; // 1 - yes, 0 - no + unsigned int alarm :1; // 1 - yes, 0 - no + unsigned int ready_cmd :2; // 00 - not ready,01-ready1,10-ready1to2, 11 -ready2 + + unsigned int prepare_stop_PWM :1; // 0 - regul turns; 1 - power +// unsigned int ready_to_go :1; // 1 - yes, 0 - no , + unsigned int start_pwm :1; // 1 - yes, 0 - no + unsigned int stop_pwm :1; // 1 - yes, 0 - no + + unsigned int pwm_status :1; // 1 -On, 0 - Off +// unsigned int can_on_rascepitel :1; // 1 - yes, 0 - no + unsigned int maybe_master :1; // 1 - yes, 0 - no Master + unsigned int rascepitel_cmd :2; // + // 00 - , + // 01 - , + // 10 - , + // 11 - , + } bit; + unsigned int all; + } OPTICAL_BUS_DATA_LOW_CMD; + + +// typedef union { +// struct { +// unsigned int ready :1; // +// unsigned int overfull :1; // +// unsigned int recive_error :1; // +// unsigned int send_error :1; // +// unsigned int wait :1; // +// unsigned int timeout :1; // +// } bit; +// unsigned int all; +// } OPTICAL_BUS_CODE_STATUS; + + +typedef struct { + int pzad_or_wzad; //given turns or power, depends on controlMode; + int angle_pwm; //current rotor turns + int iq_zad_i_zad; // Iq_zadan or Izad + OPTICAL_BUS_DATA_LOW_CMD cmd; +} OPTICAL_BUS_DATA_LOW; + +typedef struct { + OPTICAL_BUS_DATA_LOW raw; + OPTICAL_BUS_DATA_LOW data; + unsigned int status; + unsigned int overfull_data; + unsigned int timer; + unsigned int flag_clear; + unsigned int data_was_update_between_pwm_int; + unsigned int error_wdog; + unsigned int count_error_wdog; + unsigned int count_read_optical_bus_old_data; // + + +// OPTICAL_BUS_CODE_STATUS code_status; +} OPTICAL_BUS_DATA; + + +#define OPTICAL_BUS_DATA_DEFAULT {{0,0,0,0},{0,0,0,0},0,0,0,0,0,0,0,0} + +extern OPTICAL_BUS_DATA optical_write_data; +extern OPTICAL_BUS_DATA optical_read_data; + + +void optical_bus_read(void); +STATUS_DATA_READ_OPT_BUS optical_bus_get_status_and_read(void); +void optical_bus_write(void); +void optical_bus_read_clear_count_error(void); +void optical_bus_update_data_write(void); + +#endif /* SRC_MAIN_OPTICAL_BUS_H_ */ diff --git a/Inu/Src2/551/main/optical_bus_tools.c b/Inu/Src2/551/main/optical_bus_tools.c new file mode 100644 index 0000000..431ade9 --- /dev/null +++ b/Inu/Src2/551/main/optical_bus_tools.c @@ -0,0 +1,791 @@ +/* + * optical_bus_tools.c + * + * Created on: 19 . 2024 . + * Author: user + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "global_time.h" +#include "IQmathLib.h" +#include "oscil_can.h" +#include "uf_alg_ing.h" +#include "MemoryFunctions.h" +#include "RS_Functions.h" +#include "v_rotor_22220.h" +#include "log_to_memory.h" +#include "log_params.h" + + + + + +/////////////////////////////////////////////////////////////////// + + +#pragma CODE_SECTION(optical_bus_read_write_interrupt,".fast_run2"); +void optical_bus_read_write_interrupt(void) +{ + + + static unsigned int prev_error_read = 0, count_read_optical_bus_error = 0, count_read_optical_bus_old_data = 0; + static unsigned int max_count_read_old_data_optical_bus = 15; + static unsigned int flag_disable_resend = 0; + static unsigned int count_resend = 0, cc=0; +// static STATUS_DATA_READ_OPT_BUS buf_status[10]; + static STATUS_DATA_READ_OPT_BUS optbus_status; + static unsigned int tt=0; + static unsigned int cmd_wdog_sbus = 0, count_wait_wdog_sbus = 0, wdog_sbus = 0; + static int prepare_time = 0; + + + static unsigned int t_finish_optbus = 14, t_read_optbus = 6, t_write_optbus = 10, max_count_read_error_optical_bus = 15, max_count_read_wdog_optical_bus = 48; + static int cmd_optbus = 0; + + static int flag_enable_read=0, flag_finish_read = 0, flag_enable_write = 0, flag_finish_write = 0, count_wait_write = 0; + + if (prepare_time==0) + { + if (edrk.flag_second_PCH==0) + { + t_read_optbus = 6; + t_write_optbus = 8; + t_finish_optbus = 20; + } + + if (edrk.flag_second_PCH==1) + { + t_read_optbus = 12; + t_write_optbus = 14; + t_finish_optbus = 10; + } + prepare_time = 1; + } + + if (flag_special_mode_rs==1) + return; + + if (edrk.KvitirProcess) + return; + + if (edrk.disable_interrupt_timer2) + return; + +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_17_ON; +#endif + +//i_led2_on_off(1); + + +//#if (ENABLE_LOG_INTERRUPTS) +// add_log_interrupts(2); +//#endif + + +// pause_1000(100); + if (optical_read_data.flag_clear) + { + // stage_1 = 0; + optical_read_data.timer = 0; + optical_read_data.flag_clear = 0; + optical_read_data.error_wdog = 0; +// count_wait_wdog_sbus = 0; + +// if (optical_read_data.data_was_update_between_pwm_int==0) +// sum_count_err_read_opt_bus++; +// +// optical_read_data.data_was_update_between_pwm_int = 0; + + // optical_read_data.data_was_update_between_pwm_int = 0; + cc = 0; + prev_error_read = 0; + } + + +#if(_ENABLE_PWM_LINES_FOR_TESTS) + if (optical_read_data.timer==0) + { + PWM_LINES_TK_16_ON; + } + else + { + PWM_LINES_TK_16_OFF; + } +#endif + + + +// else + optical_read_data.timer++; + +// if (edrk.into_pwm_interrupt==1) +// { +// if (optical_read_data.timer>=2) +// { +// optical_read_data.timer--; +// optical_read_data.timer--; +// } +// flag_disable_resend = 0; +// count_resend = 0; +// +// } + +// +// +// +// if (stage_1==0) +// tt = t1; +// +// if (stage_1==1) +// tt = t2; + + if (edrk.ms.another_bs_maybe_on==1 && edrk.flag_second_PCH==0 /*edrk.auto_master_slave.local.bits.master*/ ) + { + + if (optical_read_data.data.cmd.bit.wdog_tick) + { + // i_led1_on(); +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_21_ON; +#endif + } + else + { + // i_led1_off(); +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_21_OFF; +#endif + + } + + optical_write_data.data.cmd.bit.wdog_tick = optical_read_data.data.cmd.bit.wdog_tick; + + if (optical_write_data.data.cmd.bit.wdog_tick) + { + // i_led2_on(); +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_22_ON; +#endif + + } + else + { + // i_led2_off(); +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_22_OFF; +#endif + } + + + + } + + + if (edrk.ms.another_bs_maybe_on==1 && edrk.flag_second_PCH==1 /*edrk.auto_master_slave.local.bits.slave*/ ) + { + + if (optical_write_data.data.cmd.bit.wdog_tick) + { + // i_led2_on(); +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_22_ON; +#endif + + } + else + { + // i_led2_off(); +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_22_OFF; +#endif + } + + + + if (optical_read_data.data.cmd.bit.wdog_tick) + { + // i_led1_on(); +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_21_ON; +#endif + } + else + { + // i_led1_off(); +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_21_OFF; +#endif + } + + + + + // + optical_write_data.data.cmd.bit.wdog_tick = wdog_sbus; + if (cmd_wdog_sbus==0) + { +// optical_write_data.data.cmd.bit.wdog_tick = wdog_sbus; + count_wait_wdog_sbus = 0; + cmd_wdog_sbus++; + } + else + // + if (cmd_wdog_sbus==1) + { + if (optical_read_data.data.cmd.bit.wdog_tick == wdog_sbus) //&& prev_error_read==0 + { + // result_code_wdog_sbus = 1; + optical_read_data.count_error_wdog = count_wait_wdog_sbus; + count_wait_wdog_sbus = 0; + wdog_sbus = !wdog_sbus; + cmd_wdog_sbus = 0; + } + else + { + if (count_wait_wdog_sbus=t_finish_optbus) + cmd_optbus = 1; + break; + case 5: + break; + case 6: + break; + case 7: + break; + case 8: + break; + case 9: + break; + default: + break; + } +} + + + +if (edrk.flag_second_PCH==0) +{ + switch (cmd_optbus) + { + case 0 : if (optical_read_data.timer==t_write_optbus) + cmd_optbus = 1; + break; + + case 1: flag_enable_read = 0; + flag_finish_read = 0; + flag_enable_write = 1; + flag_finish_write = 0; + count_wait_write = TIME_WAIT_CMD_WRITE; + cmd_optbus = 2; + break; + + case 2: if (flag_enable_write==0) + { + if (count_wait_write) + { + count_wait_write--; + } + else + cmd_optbus = 3; + } + break; + case 3: flag_enable_read = 1; + flag_finish_read = 0; + flag_enable_write = 0; + flag_finish_write = 0; + count_wait_write = 0; + cmd_optbus = 4; + break; + + case 4: if (flag_finish_read) + { + //flag_enable_write = 1; + //count_wait_write = 2; + //cmd_optbus = 2; + flag_enable_read = 0; + flag_finish_read = 0; + flag_enable_write = 1; + flag_finish_write = 0; + count_wait_write = TIME_WAIT_CMD_WRITE; + cmd_optbus = 2; // case 5: case 1: + } + break; + + case 5: if (optical_read_data.timer>=t_finish_optbus) + cmd_optbus = 1; + break; + case 6: + break; + case 7: + break; + case 8: + break; + case 9: + break; + case 10: + break; + default: + break; + } +} +// if (optical_read_data.timer==t_read_optbus) +// flag_run_cycle = 1; +// +// if (flag_run_cycle==t_read_optbus) +// { +// flag_enable_read = 1; +// flag_finish_read = 0; +// flag_enable_write = 0; +// flag_finish_write = 0; +// flag_run_cycle = 0; +// } +// +// +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_18_OFF; +#endif + + if (flag_enable_read) + { + +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_19_ON; +#endif + +#if(USE_TK_3) + project.cds_tk[3].read_pbus(&project.cds_tk[3]); +#endif + optbus_status = optical_bus_get_status_and_read(); + +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_19_OFF; +#endif + cc++; + + if (optbus_status.bit.new_data_ready) + { + + prev_error_read = 0; + optical_read_data.count_read_optical_bus_old_data = 0; + + if (optical_read_data.data_was_update_between_pwm_int<10000) + optical_read_data.data_was_update_between_pwm_int += 1; + + count_read_optical_bus_error = 0; + flag_finish_read = 1; + flag_enable_read = 0; + } + + if (optbus_status.bit.receiver_error || optbus_status.bit.bad_status12 ) + { + + prev_error_read = 1; + + if (count_read_optical_bus_error<=max_count_read_error_optical_bus) + count_read_optical_bus_error++; + else + { + optical_read_data.data.pzad_or_wzad = 0; + optical_read_data.data.angle_pwm = 0; + optical_read_data.data.iq_zad_i_zad = 0; + optical_read_data.data.cmd.all = 0; + flag_finish_read = 1; + } + } + + + if (optbus_status.bit.old_data) + { + +// prev_error_read = 1; + + flag_finish_read = 1; + + if (optical_read_data.count_read_optical_bus_old_data<=max_count_read_old_data_optical_bus) + optical_read_data.count_read_optical_bus_old_data++; + else + { + optical_read_data.data.pzad_or_wzad = 0; + optical_read_data.data.angle_pwm = 0; + optical_read_data.data.iq_zad_i_zad = 0; + optical_read_data.data.cmd.all = 0; + } + } + + +#if(_ENABLE_PWM_LINES_FOR_TESTS) + if (optbus_status.bit.new_data_ready) + { + PWM_LINES_TK_18_ON; + } +#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS) + if (optbus_status.bit.receiver_busy || optbus_status.bit.receiver_error || optbus_status.bit.bad_status12) + { + // PWM_LINES_TK_16_ON; + } +#endif + + } + +// +// +// if (flag_finish_read) +// { +// flag_enable_write = 1; +// count_wait_write = 10; +// } + + + if (flag_enable_write) + { +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_20_ON; +#endif +#if(_ENABLE_PWM_LINES_FOR_TESTS) + static unsigned int ccc = 0; + ccc++; + optical_write_data.data.angle_pwm = ccc; +#endif + optical_bus_write(); + + +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_20_OFF; +#endif + flag_enable_write = 0; + } +// +// if (count_wait_write) +// { +// count_wait_write--; +// } +// else +// flag_finish_write = 1; +// +// +// +//// read +// +// if (optical_read_data.timer==(t_read_optbus-1)) +// prev_error_read = 1; +// else +// if (optical_read_data.timer==t_read_optbus || prev_error_read==1) +// { +// +//#if(_ENABLE_PWM_LINES_FOR_TESTS) +// PWM_LINES_TK_18_OFF; +//#endif +// +//#if(_ENABLE_PWM_LINES_FOR_TESTS) +// PWM_LINES_TK_19_ON; +//#endif +// +// project.cds_tk[3].read_pbus(&project.cds_tk[3]); +// +// optbus_status = optical_bus_get_status_and_read(); +// +//#if(_ENABLE_PWM_LINES_FOR_TESTS) +// PWM_LINES_TK_19_OFF; +//#endif +// cc++; +// +// if (optbus_status.bit.new_data_ready) +// { +// +// prev_error_read = 0; +// +// if (optical_read_data.data_was_update_between_pwm_int<10000) +// optical_read_data.data_was_update_between_pwm_int += 1; +// +// count_read_optical_bus_error = 0; +// } +// +// if (optbus_status.bit.receiver_error || optbus_status.bit.bad_status12 ) +// { +// +// prev_error_read = 1; +// +// if (count_read_optical_bus_error<=max_count_read_error_optical_bus) +// count_read_optical_bus_error++; +// else +// { +// optical_read_data.data.pzad_or_wzad = 0; +// optical_read_data.data.angle_pwm = 0; +// optical_read_data.data.iq_zad_i_zad = 0; +//// optical_read_data.data.cmd.all = 0x40; // ! alarm = 1 +// optical_read_data.data.cmd.all = 0; +// } +// } +// +//#if(_ENABLE_PWM_LINES_FOR_TESTS) +// if (optbus_status.bit.new_data_ready) +// { +// PWM_LINES_TK_18_ON; +// } +//#endif +// +//#if(_ENABLE_PWM_LINES_FOR_TESTS) +// if (optbus_status.bit.receiver_busy || optbus_status.bit.receiver_error || optbus_status.bit.bad_status12) +// { +// // PWM_LINES_TK_16_ON; +// } +//#endif +// +// } +// +// +// +// +//// write +// +// if (optical_read_data.timer==t_write_optbus) +// { +//#if(_ENABLE_PWM_LINES_FOR_TESTS) +// PWM_LINES_TK_20_ON; +//#endif +// +// optical_bus_write(); +// +// +//#if(_ENABLE_PWM_LINES_FOR_TESTS) +// PWM_LINES_TK_20_OFF; +//#endif +// } + + + +// finish + +// if (optical_read_data.timer>=t_finish_optbus) +// { +// optical_read_data.timer = 0; +// } + +// if (prev_error_read==0) +// i_led2_off(); + + +// if (optical_read_data.timer==t2) +// { +// +// // if (edrk.flag_second_PCH==0) +// stage_2 = 1; +// // else +// // stage_1 = 1; +// +// optical_read_data.timer = 0; +// } + +// if (optical_read_data.timer>=t3) +// { +// optical_read_data.timer = 0; +// } + + + + + +// +// if (stage_1==2 && prev_stage1!=stage_1) +// { +// // i_led2_on(); +//// if (flag_disable_resend==0) +//// { +// // if (edrk.ms.another_bs_maybe_on==1 && (edrk.auto_master_slave.local.bits.master ) ) +// +// // if (edrk.flag_second_PCH==0) +// { +// i_led2_on(); +// i_led2_off(); +// i_led2_on(); +// +// optical_bus_write(); +// } +//// else +//// { +//// i_led2_on(); +//// +//// optical_bus_read(); +//// optbus_status = optical_bus_get_status_and_read(); +//// buf_status[cc] = optbus_status; +//// cc++; +//// +//// if (optbus_status.bit.new_data_ready) +//// optical_read_data.data_was_update_between_pwm_int = 1; +//// +//// if (optbus_status.bit.receiver_busy || optbus_status.bit.receiver_error || optbus_status.bit.bad_status12 +//// ) +//// { +//// i_led1_on(); +//// i_led1_off(); +//// +//// } +//// +//// } +// stage_1 = 0; +// } + +// if (stage_1==1 && prev_stage1!=stage_1) +// { +// +//// if (edrk.flag_second_PCH==1) +//// { +//// i_led2_on(); +//// i_led2_off(); +//// i_led2_on(); +//// +//// optical_bus_write(); +//// } +//// else +// // { +// i_led2_on(); +// +// optical_bus_read(); +// optbus_status = optical_bus_get_status_and_read(); +// buf_status[cc] = optbus_status; +// cc++; +// +// if (optbus_status.bit.new_data_ready) +// optical_read_data.data_was_update_between_pwm_int = 1; +// +// if (optbus_status.bit.receiver_busy || optbus_status.bit.receiver_error || optbus_status.bit.bad_status12 +// ) +// { +// i_led1_on(); +// i_led1_off(); +// +// } +// +// // } +// +// +// // stage_1 = 0; +// } + + // prev_stage1 = stage_1; + // } +// if (edrk.flag_second_PCH==1) +// { +// i_led2_off(); +// } + +//i_led2_on_off(0); + +//#if (ENABLE_LOG_INTERRUPTS) +// add_log_interrupts(102); +//#endif + +#if(_ENABLE_PWM_LINES_FOR_TESTS) + PWM_LINES_TK_17_OFF; +#endif + + +} +/////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////// + + diff --git a/Inu/Src2/551/main/optical_bus_tools.h b/Inu/Src2/551/main/optical_bus_tools.h new file mode 100644 index 0000000..89c6bc6 --- /dev/null +++ b/Inu/Src2/551/main/optical_bus_tools.h @@ -0,0 +1,14 @@ +/* + * optical_bus_tools.h + * + * Created on: 19 . 2024 . + * Author: user + */ + +#ifndef SRC_MAIN_OPTICAL_BUS_TOOLS_H_ +#define SRC_MAIN_OPTICAL_BUS_TOOLS_H_ + +void optical_bus_read_write_interrupt(void); + + +#endif /* SRC_MAIN_OPTICAL_BUS_TOOLS_H_ */ diff --git a/Inu/Src2/551/main/overheat_limit.c b/Inu/Src2/551/main/overheat_limit.c new file mode 100644 index 0000000..e2c2720 --- /dev/null +++ b/Inu/Src2/551/main/overheat_limit.c @@ -0,0 +1,80 @@ +/* + * overheat_limit.c + * + * Created on: 17 . 2020 . + * Author: star + */ + +#include +#include +#include +#include + +#include "IQmathLib.h" +#include "math_pi.h" +#include "limit_lib.h" + + +TEMPERATURE_LIMIT_KOEFFS temper_limit_koeffs = TEMPERATURE_LIMIT_KOEFFS_DEFAULTS; + +void calc_limit_overheat() +{ + int *p_alarm, *p_abnormal; + _iq sum_limit = CONST_IQ_1; + _iq val; + int i = 0; + + p_alarm = &protect_levels.alarm_temper_u_01; + p_abnormal = &protect_levels.abnormal_temper_u_01; + edrk.temper_limit_koeffs.power_units = CONST_IQ_1; + for (i = 0; i < 7; i++) { + val = linear_decrease(edrk.temper_edrk.real_int_temper_u[i], + *(p_alarm + i), *(p_abnormal + i)); + edrk.temper_limit_koeffs.power_units = _IQmpy(val, edrk.temper_limit_koeffs.power_units); + } + sum_limit = _IQmpy(sum_limit,edrk.temper_limit_koeffs.power_units); + + p_alarm = &protect_levels.alarm_temper_air_int_01; + p_abnormal = &protect_levels.abnormal_temper_air_int_01; + edrk.temper_limit_koeffs.area = CONST_IQ_1; + for (i = 0; i < 4; i++) { + val = linear_decrease(edrk.temper_edrk.real_int_temper_air[i], + *(p_alarm + i), *(p_abnormal + i)); + edrk.temper_limit_koeffs.area = _IQmpy(val, edrk.temper_limit_koeffs.area); + } + sum_limit = _IQmpy(sum_limit,edrk.temper_limit_koeffs.area); + + edrk.temper_limit_koeffs.water_int = linear_decrease(edrk.temper_edrk.real_temper_water[0] * 10.0, + protect_levels.alarm_temper_water_int, protect_levels.abnormal_temper_water_int); + sum_limit = _IQmpy(sum_limit,edrk.temper_limit_koeffs.water_int); + + edrk.temper_limit_koeffs.water_ext = linear_decrease(edrk.temper_edrk.real_temper_water[1] * 10.0, + protect_levels.alarm_temper_water_ext, protect_levels.abnormal_temper_water_ext); + sum_limit = _IQmpy(sum_limit,edrk.temper_limit_koeffs.water_ext); + + + p_alarm = &protect_levels.alarm_temper_acdrive_winding_U1; + p_abnormal = &protect_levels.abnormal_temper_acdrive_winding_U1; + edrk.temper_limit_koeffs.acdrive_windings = CONST_IQ_1; + for (i = 0; i < 6; i++) { + val = linear_decrease(edrk.temper_acdrive.winding.real_int_temper[i], + *(p_alarm + i), *(p_abnormal + i)); + edrk.temper_limit_koeffs.acdrive_windings = _IQmpy(val, edrk.temper_limit_koeffs.acdrive_windings); + } + sum_limit = _IQmpy(sum_limit,edrk.temper_limit_koeffs.acdrive_windings); + + edrk.temper_limit_koeffs.acdrive_bears = linear_decrease(edrk.temper_acdrive.bear.real_int_temper[0], + protect_levels.alarm_temper_acdrive_bear_DNE, protect_levels.abnormal_temper_acdrive_bear_DNE); + sum_limit = _IQmpy(sum_limit,edrk.temper_limit_koeffs.acdrive_bears); + edrk.temper_limit_koeffs.acdrive_bears = linear_decrease(edrk.temper_acdrive.bear.real_int_temper[1], + protect_levels.alarm_temper_acdrive_bear_NE, protect_levels.abnormal_temper_acdrive_bear_NE); + sum_limit = _IQmpy(sum_limit,edrk.temper_limit_koeffs.acdrive_bears); + + edrk.temper_limit_koeffs.sum_limit = sum_limit; + + if (edrk.temper_limit_koeffs.sum_limit < (CONST_IQ_1 - 1000)) + edrk.temper_limit_koeffs.code_status = 1; + else + edrk.temper_limit_koeffs.code_status = 0; + +} diff --git a/Inu/Src2/551/main/overheat_limit.h b/Inu/Src2/551/main/overheat_limit.h new file mode 100644 index 0000000..dc1199d --- /dev/null +++ b/Inu/Src2/551/main/overheat_limit.h @@ -0,0 +1,13 @@ +/* + * overheat_limit.h + * + * Created on: 17 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_OVERHEAT_LIMIT_H_ +#define SRC_MAIN_OVERHEAT_LIMIT_H_ + +void calc_limit_overheat(); + +#endif /* SRC_MAIN_OVERHEAT_LIMIT_H_ */ diff --git a/Inu/Src2/551/main/params.h b/Inu/Src2/551/main/params.h new file mode 100644 index 0000000..7abc592 --- /dev/null +++ b/Inu/Src2/551/main/params.h @@ -0,0 +1,182 @@ +#ifndef _PARAMS +#define _PARAMS + + +#if(_FLOOR6) + + +#define _ENABLE_PWM_LINES_FOR_TESTS 0//1 +#define _ENABLE_PWM_LINES_FOR_TESTS_ROTOR 0//1 +#define _ENABLE_PWM_LINES_FOR_TESTS_PWM 0//1 +#define _ENABLE_PWM_LINES_FOR_TESTS_RS 0//1 +#define _ENABLE_PWM_LINES_FOR_TESTS_SYNC 0//1 +#define _ENABLE_PWM_LINES_FOR_TESTS_GO 0//1 + +#else + +#define _ENABLE_PWM_LINES_FOR_TESTS 0 +#define _ENABLE_PWM_LINES_FOR_TESTS_ROTOR 0 +#define _ENABLE_PWM_LINES_FOR_TESTS_PWM 0 +#define _ENABLE_PWM_LINES_FOR_TESTS_RS 0 +#define _ENABLE_PWM_LINES_FOR_TESTS_SYNC 0//1 +#define _ENABLE_PWM_LINES_FOR_TESTS_GO 0//1 +#endif + + +#if(_FLOOR6) +#define MODE_DISABLE_ENABLE_WDOG 1 // 0 - wdog , 1 - +#else +#define MODE_DISABLE_ENABLE_WDOG 0 // 0 - wdog , 1 - +#endif + + + + + + +#define CHECK_IN_OUT_TERMINAL 1 + +#define WORK_ON_STEND_D 0//1 + + + +//////////////////////////////////////////////////////////////////// +#ifndef MODE_DISABLE_ENABLE_WDOG +#define MODE_DISABLE_ENABLE_WDOG 0 +#endif + + +#ifndef CHECK_IN_OUT_TERMINAL +#define CHECK_IN_OUT_TERMINAL 0 +#endif + +#ifndef WORK_ON_STEND_D +#define WORK_ON_STEND_D 0 +#endif + + + +/*************************************************************************************/ +//#define BAN_ROTOR_REVERS_DIRECT 1 + +//#define TIME_PAUSE_ZADATCHIK 750//500 + +//#define TIME_SET_LINE_RELAY_FAN 3000 // +//#define LEVEL_FAN_ON_TEMPER_ACDRIVE 1400 // +//#define LEVEL_FAN_OFF_TEMPER_ACDRIVE 1200 // +//( LEVEL_FAN_ON_TEMPER_ACDRIVE ~20 ) +//#define TIME_SET_LINE_RELAY_FAN 3000 // + +/* +#define MAX_TIME_DIRECT_ROTOR 5000 // . +#define MIN_TIME_DIRECT_ROTOR -5000 // + +#define LEVEL_FORWARD_TIME_DIRECT_ROTOR 4000 // +#define LEVEL_BACK_TIME_DIRECT_ROTOR -4000 // + +#define MAX_TIME_ERROR_ROTOR 5000 // . +#define MIN_TIME_ERROR_ROTOR 0 // . + + +#define LEVEL_ON_ERROR_ROTOR 4000 // +#define LEVEL_OFF_ERROR_ROTOR 1000 // +*/ + + +/* +#define PID_KP_IM 0.018 //0.036 //0.018 //0.18 //0.095 // PID Kp +#define PID_KI_IM 0.08 // 0.008 // PID Ki +#define PID_KD_IM 0.0000 //100 // PID Kd +#define PID_KC_IM 0.09 // PID Kc + + +#define PID_KP_F 12//26//12 //40 //20 //12 //20 //60.0 //20.0 //0.095 // PID Kp +#define PID_KI_F 0.00010 // 0.008 // PID Ki +#define PID_KD_F 0.000 //100 PID Kd +#define PID_KC_F 0.005 // PID Kc +//#define PID_KC_F 0.000 // PID Kc + +#define ADD_KP_DF (1000.0/NORMA_MZZ)//(500.0/NORMA_MZZ)//(50.0/NORMA_MZZ) +#define ADD_KI_DF (2000.0/NORMA_MZZ)//(1000.0/NORMA_MZZ)//(100.0/NORMA_MZZ) +#define MAX_DELTA_pidF 2.0 +#define MIN_MZZ_FOR_DF 1761607 //(210/NORMA_MZZ) +*/ + +/* +#define Im_PREDEL 600 // +#define I_OUT_PREDEL -20 // . y +#define U_IN_PREDEL 500 // y + +#define IQ_NORMAL_CHARGE_UD_MAX 12163481 // 1450 V //13002342 // 1550 //_IQtoF(filter.iqU_1_long)*NORMA_ACP +#define IQ_NORMAL_CHARGE_UD_MIN 10066329 // 1200 V + + +#define U_D_MAX_ERROR_GLOBAL 17616076 // 2100 V //17196646 //2050V // 16777216 //2000V/2000*2^24 +#define U_D_MAX_ERROR 16777216 // 2000V //16357785 //1950V //15938355 //1900V/2000*2^24 + +//#define U_D_NORMA_MIN 3774873 // 450 V // 13421772 // 450 V 22.05.08 //1600V/2000*2^24 +//#define U_D_NORMA_MAX 15518924 // //15099494 //1850V/2000*2^24 + +#define U_D_MIN_ERROR 10905190 // 1300V/2000*2^24 + +#define I_IN_MAX_ERROR_GLOBAL 18454937 // 2200 A //16777216 //2000 A // 13421772 //1600 A //10905190 //1300 // 900A + +#define KOEFF_WROTOR_FILTER_SPARTAN 7//8 +#define MAX_DELTA_WROTOR_S_1_2 1 + +#define ENABLE_I_HDW_PROTECT_ON_GLOBAL 1 // + +#define TIME_WAIT_CHARGE 2000 //5000 // 10000 +#define TIME_WAIT_CHARGE_OUT 15000 //15000 +#define TIME_SET_LINE_RELAY 10000 +#define TIME_SET_LINE_RELAY5 3000 +#define TIME_WAIT_LEVEL_QPU2 3000 +*/ + + +/* +///--------------------------- 22220 paremetrs -------------------///////// + +//////////////////////////////////////////////////////////////// +// Loaded capasitors level +#define V_CAPASITORS_LOADED_IQ 11184810 //13421772 ~ 2400V // 11184810 ~ 2000V +#define V_NOMINAL 15099494 //15099494 ~ 2700V + +// Level of nominal currents +#define I_OUT_NOMINAL_IQ 10066329 //8388608 ~ 1500A //5592405 ~ 1000A // 10066329 ~ 1800A + //11184811 ~ 2000A // 12482249 ~ 2232A // 6710886 ~ 1200A +#define I_ZPT_NOMINAL_IQ 6123683 //1095A + + + +#define NORMA_MZZ 3000 //5000 +//#define NORMA_ACP 3000 +#define DISABLE_TEST_TKAK_ON_START 1 +//#define MOTOR_STEND 1 + + +//#define FREQ_PWM 350 //401 //379 + +#ifdef MOTOR_STEND +#define POLUS 4 // + +#define BPSI_NORMAL 0.9//0.7 //Hz +#define MAX_FZAD_FROM_SU 16.7 // +#define MAX_FZAD_FROM_SU_OBOROT 1100 + +#else +#define POLUS 6 // +#define BPSI_NORMAL 0.9 //Hz +#define MAX_FZAD_FROM_SU 16.7 // +#define MAX_FZAD_FROM_SU_OBOROT 1650 +#define COS_FI 0.83 + +#endif +*/ + +#define KOEF_TEMPER_DECR_MZZ 2.0 + +#endif + + + diff --git a/Inu/Src2/551/main/params_alg.h b/Inu/Src2/551/main/params_alg.h new file mode 100644 index 0000000..8529a80 --- /dev/null +++ b/Inu/Src2/551/main/params_alg.h @@ -0,0 +1,218 @@ +/* + * params_alg.h + * + * Created on: 26 . 2020 . + * Author: Yura + */ + +#ifndef SRC_MAIN_PARAMS_ALG_H_ +#define SRC_MAIN_PARAMS_ALG_H_ + +// , +#define DISABLE_CALC_KM_ON_SLAVE 0//1 + +#define DISABLE_WORK_BREAK 0 // + +#define SENSOR_ALG_22220 1 +#define SENSOR_ALG_23550 2 + + +#define SENSOR_ALG SENSOR_ALG_22220 +//#define SENSOR_ALG SENSOR_ALG_23550 + + +#define NOMINAL_U_ZARYAD 2520 // +#define NOMINAL_U_BREAK_LEVEL 2580 // + IQ_DELTA_U_START_RECUP=100V +#define NOMINAL_SET_IZAD 910 // +#define NOMINAL_SET_K_U_DISBALANCE 40//20 // . , >0 +#define NOMINAL_SET_LIMIT_POWER 6300 // + + + + + +/////////////////////////////////////////////////////////////// +#define U_D_MAX_ERROR_GLOBAL IQ_I_U_VALUE_PLUS_2850 //U_D_MAX_ERROR_GLOBAL_2850 + +#define MAX_U_PROC_SMALL 2.5 //1.4 +#define MAX_U_PROC 1.1 //1.11 //1.4 +#define MIN_U_PROC 0.8 //0.7 + +#define ADD_U_MAX_GLOBAL 200.0 //V GLOBAL ZadanieU_Charge +#define ADD_U_MAX_GLOBAL_SMALL 500.0 //V GLOBAL ZadanieU_Charge +#define LEVEL_DETECT_U_SMALL 1000.0 //V GLOBAL ZadanieU_Charge + +#define KOEF_IM_ON_TORMOG 0.65// 0.75 // +#define KOEF_IM_ON_TORMOG_WITH_MAX_TEMPER_BREAK 0.1// + +/////////////////////////////////////////////////////////////// + + +#define MZZ_ADD_1 0.5 // 0.25 //0.5 1 +#define MZZ_ADD_2 0.15 ///0.1 //0.05 //0.1 1 +#define MZZ_ADD_3 0.25 //0.05 ///0.1 //0.05 //0.1 1 + +#define FZAD_ADD_MAX 0.08 //0.005 //0.08 fzad 1 +#define FZAD_DEC 0.0004 // fzad 1 + +#define POWERZAD_ADD_MAX 0.08 //0.005 //0.08 fzad 1 +#define POWERZAD_DEC 0.0004 // fzad 1 + +#define POLUS 6 //6 // +#define BPSI_NORMAL 0.22 //0.3 // +#define BPSI_MAXIMAL 0.35 //0.3 // +#define BPSI_MINIMAL 0.05 //0.3 // +#define PROVOROT_F_HZ 0.2 // +#define PROVOROT_OBOROTS 10 // + + +#define ADD_KP_DF (1000.0/NORMA_MZZ)//(500.0/NORMA_MZZ)//(50.0/NORMA_MZZ) +#define ADD_KI_DF (2000.0/NORMA_MZZ)//(1000.0/NORMA_MZZ)//(100.0/NORMA_MZZ) + +#define ADD_KP_DPOWER (1000.0/NORMA_MZZ)//(500.0/NORMA_MZZ)//(50.0/NORMA_MZZ) +#define ADD_KI_DPOWER (2000.0/NORMA_MZZ)//(1000.0/NORMA_MZZ)//(100.0/NORMA_MZZ) + +#define MIN_MZZ_FOR_DF 210 +#define MIN_MZZ_FOR_DPOWER 210 + + +//////////////////// + + +#define PID_KP_IM 0.036 //0.018 //0.0013// 0.018 //0.036 //0.018 //0.18 //0.095 // PID Kp +#define PID_KI_IM 0.32 // 0.16 //0.32 //0.16 //0.08//0.8//0.025 //0.08 // PID Ki +#define PID_KD_IM 0.0000 //*100 // PID Kd +#define PID_KC_IM 0.09 // PID Kc + + +#define PID_KP_F 12.0//6.0//12.0 //6.0 //18 //12//6//26//12 //40 //20 //12 //20 //60.0 //20.0 //0.095 // PID Kp +#define PID_KI_F 0.00020 //0.00010 // 0.008 // PID Ki +//#define PID_KI_F 0.00030 //0.00010 // 0.008 // PID Ki +#define PID_KD_F 0.000 //*100 PID Kd +#define PID_KC_F 0.00005//0.005 // PID Kc +//#define PID_KC_F 0.000 // PID Kc + +#define PID_KP_POWER 9//3//26//12 //40 //20 //12 //20 //60.0 //20.0 //0.095 // PID Kp +//#define PID_KI_F 0.00020 //0.00010 // 0.008 // PID Ki +#define PID_KI_POWER 0.00030 //0.00010 // 0.008 // PID Ki +#define PID_KD_POWER 0.000 //*100 PID Kd +#define PID_KC_POWER 0.0001 // PID Kc + + + +/////////////////// +// . k + +#define K_STATOR_MAX 0.93 // 0.91 // DEF_PERIOD_MIN_MKS = 60 +#define K_STATOR_MIN 0.020 // 0.91 // DEF_PERIOD_MIN_MKS = 60 + +//#define K_STATOR_MAX 0.89 // DEF_PERIOD_MIN_MKS = 80 + + + + +#define MAX_ZADANIE_I_VOZBUD 200.0 // A + +#define MAX_ZADANIE_U_CHARGE 2800.0//1500.0 //V +//#define MAX_ZADANIE_F_ROTOR 70 + +#define MAX_ZADANIE_OBOROTS_ROTOR 230.0 //340 //240 1000 //260.0 // +/- ob/min +#define MIN_ZADANIE_OBOROTS_ROTOR -230.0 //-180.0 //-230.0 // 1000 //260.0 // +/- ob/min + +#define MAX_1_ZADANIE_OBOROTS_ROTOR 120.0 //340 //240 1000 //260.0 // +/- ob/min +#define MIN_1_ZADANIE_OBOROTS_ROTOR -90.0 //-230.0 // 1000 //260.0 // +/- ob/min + + +#define DEAD_ZONE_ZADANIE_OBOROTS_ROTOR 10.0 + +#define MAX_ZADANIE_I_M 950.0// 1000.0 //750.0 // A + +#define MAX_ZADANIE_POWER 6300.0 // kWt +#define MIN_ZADANIE_POWER -6300.0 // kWt + +#define MAX_1_ZADANIE_POWER 3000.0 // kWt +#define MIN_1_ZADANIE_POWER -3000.0 // kWt + + +#define SUPER_MAX_ZADANIE_LIMIT_POWER 6500.0 // kWt + +#define MAX_ZADANIE_LIMIT_POWER 6300.0 // kWt +#define MAX_1_ZADANIE_LIMIT_POWER 2000.0 // kWt + +#define MIN_ZADANIE_LIMIT_POWER 100.0 // kWt +#define MIN_ZADANIE_LIMIT_POWER_FROM_SVU 50.0 // kWt +#define POWER_ZAPAS_FOR_UOM 5 //50 // + +#define DEAD_ZONE_ZADANIE_POWER 50.0 // kWt +#define DEAD_ZONE_ZADANIE_LIMIT_POWER 50.0 // kWt + + + +#define MAX_ZADANIE_K_M K_STATOR_MAX // A +#define MAX_ZADANIE_F 30.0 // Hz +#define MIN_ZADANIE_F -30.0 //60.0 // Hz + + +#define MAX_ZADANIE_K_U_DISBALANCE 2.0 //1.0 // k +#define MAX_ZADANIE_KPLUS_U_DISBALANCE 1.0 // k + + + +#define T_NARAST_ZADANIE_F 5.0 // sec +#define T_NARAST_ZADANIE_OBOROTS_ROTOR 80.0 //20.0 //30.0 //15.0 // sec + +#define T1_NARAST_ZADANIE_OBOROTS_ROTOR_PLUS 80.0 //20.0 //30.0 //15.0 // sec +#define T1_NARAST_ZADANIE_OBOROTS_ROTOR_MINUS 40.0 //20.0 //30.0 //15.0 // sec + +#define T2_NARAST_ZADANIE_OBOROTS_ROTOR_PLUS 80.0 //160.0 //20.0 //30.0 //15.0 // sec +#define T2_NARAST_ZADANIE_OBOROTS_ROTOR_MINUS 40.0 //20.0 //30.0 //15.0 // sec + +#define T_SLOW_NARAST_ZADANIE_OBOROTS_ROTOR_PLUS 600.0 //160.0 //20.0 //30.0 //15.0 // sec +#define T_SLOW_NARAST_ZADANIE_OBOROTS_ROTOR_MINUS 600.0 //20.0 //30.0 //15.0 // sec + + + +#define T_NARAST_ZADANIE_K_M 15.0 // sec +#define T_NARAST_ZADANIE_I_M 15.0 // sec + +#define T1_NARAST_ZADANIE_POWER_PLUS 80.0 //30.0 // sec +#define T1_NARAST_ZADANIE_POWER_MINUS 30.0 //30.0 // sec +#define T2_NARAST_ZADANIE_POWER_PLUS 80.0 //30.0 // sec +#define T2_NARAST_ZADANIE_POWER_MINUS 30.0 //30.0 // sec + +#define T_NARAST_ZADANIE_LIMIT_POWER 5.0 //30.0 // sec + +#define T1_NARAST_ZADANIE_LIMIT_POWER_PLUS 30.0 //30.0 // sec +#define T1_NARAST_ZADANIE_LIMIT_POWER_MINUS 5.0 //30.0 // sec +#define T2_NARAST_ZADANIE_LIMIT_POWER_PLUS 80.0 //30.0 // sec +#define T2_NARAST_ZADANIE_LIMIT_POWER_MINUS 5.0 //30.0 // sec + + +#define T_NARAST_ZADANIE_U_CHARGE 2.0 // sec +#define T_NARAST_ZADANIE_K_U_DISBALANCE 15.0 // sec +#define T_NARAST_ZADANIE_KPLUS_U_DISBALANCE 15.0 // sec + +#define T_NARAST_ZADANIE_IMITATION_OBOROTS_ROTOR 30.0 // sec + + + + + + +#define ENABLE_DECR_MZZ_POWER_IZAD 1 +// +#define POWER_AIN_100KW 186413 + +#define DELTA_LEVEL_POWER_AIN_DECR_MZZ_DEF (3*POWER_AIN_100KW) // 300 kW // 559240 //300 //186413 //100kW // iqP = P (W) /3000/3000 * 2^24 // +#define MIN_DELTA_LEVEL_POWER_AIN_DECR_MZZ_DEF (5*POWER_AIN_100KW) // 500 kW +#define SMEWENIE_LEVEL_POWER_AIN_DECR_MZZ_DEF 0 //(1*POWER_AIN_100KW) // 100 kW + +// 1 - 0 - +#define MAX_KOEF_OGRAN_POWER_LIMIT CONST_IQ_05 // 0.5 +#define EXP_FILTER_KOEF_OGRAN_POWER_LIMIT 4.40//2.22 // + + + + + +#endif /* SRC_MAIN_PARAMS_ALG_H_ */ diff --git a/Inu/Src2/551/main/params_bsu.h b/Inu/Src2/551/main/params_bsu.h new file mode 100644 index 0000000..a58cc2c --- /dev/null +++ b/Inu/Src2/551/main/params_bsu.h @@ -0,0 +1,123 @@ +/* + * params_bsu.h + * + * Created on: 14 . 2020 . + * Author: yura + */ + +#ifndef SRC_MAIN_PARAMS_BSU_H_ +#define SRC_MAIN_PARAMS_BSU_H_ + +#include "iq_values_norma_f.h" +#include "iq_values_norma_iu.h" +#include "iq_values_norma_oborot.h" + + + +#define TKAK_23550 1 +#define TKAK_EDRK 2 + + +#define TKAK_VERSION TKAK_23550 +//#define TKAK_VERSION TKAK_EDRK + + +// 23550_sp2 +#define TK_DEAD_TIME_NS 25000 //25.0 //40.0 +#define TK_ACKN_TIME_NS 2200 +#define TK_MIN_TIME_NS 25000 //80.0 //35.0 // 15.0 //40.0 +#define TK_SOFT_OFF_TIME_NS 20000 //25.0 //40.0 + +#define DIV_TIME_TK_SOFT_OFF 20 // 20 nsec -> 1 bit +#define DIV_TIME_TK_DEAD 640 //0.16 // 160 nsec -> 1 bit +#define DIV_TIME_TK_MIN 640 //0.16 // 160 nsec -> 1 bit + +#define DIV_TIME_TK_ACKN 20 // 20 nsec -> 1 bit + + +// sp2 + +#define TK_DEAD_TIME_MKS 25.0 //40.0 +#define TK_ACKN_TIME_MKS 2.2 +#define TK_MIN_TIME_MKS 25.0 // 15.0 //40.0 +#define DIV_TIME_TK 0.4 // 0.16 + + +#define MAX_READ_SBUS 1 //10 + + +#if (_FLOOR6==1) +// tkak +#define TKAK0_OFF_PROTECT 1 +#define TKAK1_OFF_PROTECT 1 +#define TKAK2_OFF_PROTECT 1 +#define TKAK3_OFF_PROTECT 1 +#define IN0_OFF_PROTECT 1 +#define IN1_OFF_PROTECT 1 +#define OUT0_OFF_PROTECT 1 + +#else +// tkak +#define TKAK0_OFF_PROTECT 0 +#define TKAK1_OFF_PROTECT 0 +#define TKAK2_OFF_PROTECT 0 +#define TKAK3_OFF_PROTECT 0 +#define IN0_OFF_PROTECT 0 +#define IN1_OFF_PROTECT 0 +#define OUT0_OFF_PROTECT 0 +#endif + +// +#define TK_DISABLE_OUTPUT_A1 0 +#define TK_DISABLE_OUTPUT_B1 0 +#define TK_DISABLE_OUTPUT_C1 0 + +#define TK_DISABLE_OUTPUT_A2 0 +#define TK_DISABLE_OUTPUT_B2 0 +#define TK_DISABLE_OUTPUT_C2 0 + +////////////////////// + +#define ENABLE_ROTOR_SENSOR_ZERO_SIGNAL 0 +#define ENABLE_ROTOR_SENSOR_1_PM67 1 +#define ENABLE_ROTOR_SENSOR_2_PM67 0 + +#define ENABLE_ROTOR_SENSOR_1_PBUS 0//1 +#define ENABLE_ROTOR_SENSOR_2_PBUS 0//1 + + +#if (ENABLE_ROTOR_SENSOR_1_PM67==1 && ENABLE_ROTOR_SENSOR_2_PM67==0) +// 1- 2- +#define ENABLE_COMBO_SENSOR_1_TO_2 1 +#define ENABLE_COMBO_SENSOR_2_TO_1 0 +#endif + +#if (ENABLE_ROTOR_SENSOR_1_PM67==0 && ENABLE_ROTOR_SENSOR_2_PM67==1) +// 2- 1- +#define ENABLE_COMBO_SENSOR_2_TO_1 1 +#define ENABLE_COMBO_SENSOR_1_TO_2 0 +#endif + + + +#if (ENABLE_ROTOR_SENSOR_1_PM67==1 && ENABLE_ROTOR_SENSOR_2_PM67==1) + +#define ENABLE_COMBO_SENSOR_1 0 +#define ENABLE_COMBO_SENSOR_1 0 + +#endif + + +#define ROTOR_SENSOR_IMPULSES_PER_ROTATE 4096 // 1024 // - 1 + + + + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////// + + + +#endif /* SRC_MAIN_PARAMS_BSU_H_ */ diff --git a/Inu/Src2/551/main/params_hwp.h b/Inu/Src2/551/main/params_hwp.h new file mode 100644 index 0000000..d3ebed4 --- /dev/null +++ b/Inu/Src2/551/main/params_hwp.h @@ -0,0 +1,9 @@ + + +#define LEVEL_HWP_U_ZPT 2900 //2800 // V 0-2900 V +#define LEVEL_HWP_I_AF 800 //700 // A 0-450A +#define LEVEL_HWP_I_ZPT 1600 // A 0-2000?? +#define LEVEL_HWP_U_ABC 3100 //2900 //2800 // V 0-2000V +#define LEVEL_HWP_I_BREAK 900 //750 // A 0-2000A + +#define convert_real_to_mv_hwp(nc,value) ((float)value*(float)R_ADC[0][nc]/(float)K_LEM_ADC[0][nc]*10.0) diff --git a/Inu/Src2/551/main/params_motor.h b/Inu/Src2/551/main/params_motor.h new file mode 100644 index 0000000..1e8c030 --- /dev/null +++ b/Inu/Src2/551/main/params_motor.h @@ -0,0 +1,59 @@ +/* + * params_motor.h + * + * Created on: 14 . 2020 . + * Author: yura + */ + +#ifndef SRC_MAIN_PARAMS_MOTOR_H_ +#define SRC_MAIN_PARAMS_MOTOR_H_ + + + +#define SDVIG_OBMOTKI_ZERO 1 +#define SDVIG_OBMOTKI_30_PLUS 2 +#define SDVIG_OBMOTKI_30_MINUS 3 + + +#define SETUP_SDVIG_OBMOTKI SDVIG_OBMOTKI_ZERO //SDVIG_OBMOTKI_ZERO +//#define SETUP_SDVIG_OBMOTKI SDVIG_OBMOTKI_30_PLUS //SDVIG_OBMOTKI_ZERO + +#define COS_FI 0.87 +// Level of nominal currents +#define I_OUT_NOMINAL_IQ 5033164// 900 A //8388608 ~ 1500A //5592405 ~ 1000A // 10066329 ~ 1800A + //11184811 ~ 2000A // 12482249 ~ 2232A // 6710886 ~ 1200A +#define I_OUT_NOMINAL 900 + +#define MOTOR_CURRENT_NOMINAL 650.0 //930.0 +#define MOTOR_CURRENT_MAX 900.00 //1489.0 + + + + +#define P_NOMINAL 6300 //KWt +#define WROT_NOMINAL 180.0 +#define WROT_MAX 530.0 +#define FROT_NOMINAL (WROT_NOMINAL / 60.0) +#define FROT_MAX (WROT_MAX / 60.0) + +//#define REVERS_ON_CLOCK 1 // 0 // 1- .. 0 - + + + +//#define WORK_TWICE 0 /* y */ + + +//#define MAX_ZAD_OBOROTS 200 + +#define L_SIGMA_S 0.0001467 +#define L_SIGMA_R 0.00000923 +#define L_M 0.00421 +#define R_STATOR 0.002 +#define R_ROTOR_SHTRIH 0.0021 +#define SLIP_NOM 0.006 +#define R_ROTOR (R_ROTOR_SHTRIH / SLIP_NOM) +#define F_STATOR_NOM 50.0 + + + +#endif /* SRC_MAIN_PARAMS_MOTOR_H_ */ diff --git a/Inu/Src2/551/main/params_norma.h b/Inu/Src2/551/main/params_norma.h new file mode 100644 index 0000000..9c3e790 --- /dev/null +++ b/Inu/Src2/551/main/params_norma.h @@ -0,0 +1,70 @@ +/* + * params_norma.h + * + * Created on: 14 . 2020 . + * Author: yura + */ + +#ifndef _PARAMS_NORMA_H_ +#define _PARAMS_NORMA_H_ + + +//////////////////////////////////////////////////// +#define NORMA_FROTOR_INT 20 +#define NORMA_ACP_INT 3000 +#define NORMA_ANGLE 360 +//////////////////////////////////////////////////// +//////////////////////////////////////////////////// +//#define NORMA_FROTOR 20.0 +//#define NORMA_ACP 3000.0 + +#define NORMA_FROTOR ((float)NORMA_FROTOR_INT) +#define NORMA_ACP ((float)NORMA_ACP_INT) + + +#define NORMA_MZZ_INT NORMA_ACP_INT +#define NORMA_MZZ ((float)NORMA_MZZ_INT) + +#define NORMA_I_U_INT NORMA_MZZ_INT + +//////////////////////////////////////////////////// +//////////////////////////////////////////////////// +//////////////////////////////////////////////////// + +//#define F_STATOR_MAX NORMA_FROTOR // . + + + + +#define NORMA_ACP_P 100.0 + +#define NORMA_ACP_RMS 2127.66 + +#define NORMA_ACP_TEMPER_MILL_AMP 100.0 // + +#ifndef PROJECT_SHIP +#error PROJECT_SHIP predifine Name +#else + + +#if (PROJECT_SHIP == 1) +#define NORMA_ACP_TEMPER 100.0 // 23550.1 +#endif + + +#if (PROJECT_SHIP == 2) +#define NORMA_ACP_TEMPER 200.0 // 23550.3 +#endif + +#if (PROJECT_SHIP== 3) +#define NORMA_ACP_TEMPER 200.0 // 23550.3 + +#endif + + +#endif + + + + +#endif /* _PARAMS_NORMA_H_ */ diff --git a/Inu/Src2/551/main/params_protect_adc.h b/Inu/Src2/551/main/params_protect_adc.h new file mode 100644 index 0000000..b5772bd --- /dev/null +++ b/Inu/Src2/551/main/params_protect_adc.h @@ -0,0 +1,25 @@ +/* + * params_protect_adc.h + * + * Created on: 8 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_PARAMS_PROTECT_ADC_H_ +#define SRC_MAIN_PARAMS_PROTECT_ADC_H_ +#include +#include + + +#define LEVEL_ADC_I_AF LEVEL_HWP_I_AF // A 0-450A +#define LEVEL_ADC_I_ZPT LEVEL_HWP_I_ZPT // A 0-2000?? +//#define LEVEL_ADC_U_ABC 1000 // V 0-2000V +#define LEVEL_ADC_I_BREAK LEVEL_HWP_I_BREAK // A 0-2000A +#define LEVEL_ADC_U_ZPT_MAX LEVEL_HWP_U_ZPT +#define LEVEL_ADC_U_ZPT_MIN 1800 +#define LEVEL_ADC_U_IN_MAX LEVEL_HWP_U_ABC +#define LEVEL_ADC_U_IN_MIN 1380 +#define LEVEL_ADC_I_OUT_MAX I_OUT_NOMINAL //(I_OUT_NOMINAL * 1.9) + + +#endif /* SRC_MAIN_PARAMS_PROTECT_ADC_H_ */ diff --git a/Inu/Src2/551/main/params_pwm24.h b/Inu/Src2/551/main/params_pwm24.h new file mode 100644 index 0000000..a2571a6 --- /dev/null +++ b/Inu/Src2/551/main/params_pwm24.h @@ -0,0 +1,48 @@ +/* + * params_pwm24.h + * + * Created on: 14 . 2020 . + * Author: yura + */ + +#ifndef SRC_MAIN_PARAMS_PWM24_H_ +#define SRC_MAIN_PARAMS_PWM24_H_ + +/////////////////////////////////////////////////////// +#if (_SIMULATE_AC==1) +#define FREQ_PWM 100 //450 //800 /* */ //3138 // 2360//2477 // +#else +#define FREQ_PWM 450 //800 /* */ //3138 // 2360//2477 // +#endif + +#define DEF_PERIOD_MIN_MKS 60 // 80 //60 // = 2*TK_MIN_TIME_MKS = 30 + // + TK_DEAD_TIME_MKS + 5mks = 60 +#define DEF_PERIOD_MIN_BR_XTICS 165 + +///////////////// + + + +#define PWM_ONE_INTERRUPT_RUN 1 +#define PWM_TWICE_INTERRUPT_RUN 0 + + + +//#define PWN_COUNT_RUN_PER_INTERRUPT PWM_ONE_INTERRUPT_RUN // +#define PWN_COUNT_RUN_PER_INTERRUPT PWM_TWICE_INTERRUPT_RUN // + + + + + +/////////////////////////// +#define FREQ_INTERNAL_GENERATOR_XILINX_TMS 1875000 // 67 + + +////////////////////// + + + + + +#endif /* SRC_MAIN_PARAMS_PWM24_H_ */ diff --git a/Inu/Src2/551/main/params_temper_p.h b/Inu/Src2/551/main/params_temper_p.h new file mode 100644 index 0000000..2864649 --- /dev/null +++ b/Inu/Src2/551/main/params_temper_p.h @@ -0,0 +1,58 @@ + +#define INDEX_T_WATER_EXT 0 +#define INDEX_T_WATER_INT 1 + + +#define ALARM_TEMPER_BREAK_INT 1100 +#define ABNORMAL_TEMPER_BREAK_INT 900 +#define DELTA_TEMPER_BREAK_INT 20 + + + + +// koef to svu +#define K_TEMPER_TO_SVU 10.0 +#define K_P_WATER_TO_SVU 100.0 + + + +// T UO1_7 +#define ALARM_TEMPER_AF 400 +#define ABNORMAL_TEMPER_AF 350 + + +// T water INT EXT +#define ALARM_TEMPER_WATER_INT 400 +#define ABNORMAL_TEMPER_WATER_INT 350 + + +#define ALARM_TEMPER_WATER_EXT 400 +#define ABNORMAL_TEMPER_WATER_EXT 350 + + +// P water max +#define ALARM_P_WATER_MAX_INT 600 +#define ABNORMAL_P_WATER_MAX_INT 500 + +// P water min +#define ALARM_P_WATER_MIN_INT 150//300 +#define ABNORMAL_P_WATER_MIN_INT 180//320 + +#define ALARM_P_WATER_MIN_INT_ON_OFF_PUMP 60// 110 +#define ABNORMAL_P_WATER_MIN_INT_ON_OFF_PUMP 110// 130 + + +// air +#define ALARM_TEMPER_AIR_INT 450 +#define ABNORMAL_TEMPER_AIR_INT 400 + +//ac drive +#define ALARM_TEMPER_ACDRIVE_WINDING 1300 +#define ABNORMAL_TEMPER_ACDRIVE_WINDING 1200 + +#define ALARM_TEMPER_ACDRIVE_BEAR 900 +#define ABNORMAL_TEMPER_ACDRIVE_BEAR 800 + +#define ALARM_TEMPER_BSU 600 +#define ABNORMAL_TEMPER_BSU 500 + diff --git a/Inu/Src2/551/main/pll_tools.c b/Inu/Src2/551/main/pll_tools.c new file mode 100644 index 0000000..decc342 --- /dev/null +++ b/Inu/Src2/551/main/pll_tools.c @@ -0,0 +1,105 @@ +/* + * pll_tools.c + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + + +#include + +#include +#include +#include +#include +#include +#include +#include "IQmathLib.h" +#include "mathlib.h" +#include "adc_tools.h" +#include "limit_power.h" +#include "pll_tools.h" + + +//#pragma DATA_SECTION(pll1, ".slow_vars") +PLL_REC pll1 = PLL_REC_DEFAULT; + + + +void init_50hz_input_net50hz(void) +{ + + //1. + + pll1.setup.freq_run_pll = (FREQ_RUN_PLL); // . + pll1.setup.rotation_u_cba = 0;//0;//1; // : 0 - A-B-C, 1 - A-C-B + + pll1.init(&pll1); // + + // + +} + +void calc_pll_50hz(void) +{ + + // . + pll1.input.Input_U_AB = analog.iqUin_A1B1; + pll1.input.Input_U_BC = analog.iqUin_B1C1; + pll1.input.Input_U_CA = analog.iqUin_C1A1; + + // , setup.freq_run_pll + pll1.calc_pll(&pll1); +// + + +} + + +void get_freq_50hz_float(void) +{ + float int_delta_freq_test; + // 3. . + + // *100. + // - . + pll1.get_freq_float(&pll1); + + if (edrk.Status_Ready.bits.preImitationReady2) + edrk.freq_50hz_1 = 5001; + else + edrk.freq_50hz_1 = pll1.output.int_freq_net; + + if (delta_freq_test>0) + { + int_delta_freq_test = _IQtoF( delta_freq_test) * pll1.setup.freq_run_pll / PI * 50.00; // freq*100 + edrk.freq_50hz_1 -= int_delta_freq_test; + } + + // + + +} + +void get_freq_50hz_iq(void) +{ + + // 3. . + + // *100. + // - . + pll1.get_freq_iq(&pll1); + + if (edrk.Status_Ready.bits.preImitationReady2) + edrk.iq_freq_50hz = level_50hz; + else + edrk.iq_freq_50hz = pll1.output.iq_freq_net; + + if (delta_freq_test>0) + edrk.iq_freq_50hz -= delta_freq_test; + + // + + +} + diff --git a/Inu/Src2/551/main/pll_tools.h b/Inu/Src2/551/main/pll_tools.h new file mode 100644 index 0000000..1659e90 --- /dev/null +++ b/Inu/Src2/551/main/pll_tools.h @@ -0,0 +1,22 @@ +/* + * pll_tools.h + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef SRC_MAIN_PLL_TOOLS_H_ +#define SRC_MAIN_PLL_TOOLS_H_ + + +#define FREQ_RUN_PLL (2*FREQ_PWM) + + +void get_freq_50hz_float(void); +void get_freq_50hz_iq(void); +void calc_pll_50hz(void); +void init_50hz_input_net50hz(void); + +extern PLL_REC pll1; + +#endif /* SRC_MAIN_PLL_TOOLS_H_ */ diff --git a/Inu/Src2/551/main/project.c b/Inu/Src2/551/main/project.c new file mode 100644 index 0000000..a8fcec9 --- /dev/null +++ b/Inu/Src2/551/main/project.c @@ -0,0 +1,1049 @@ +#include +#include +#include + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "xp_cds_in.h" +#include "xp_cds_out.h" +#include "xp_cds_rs.h" +#include "xp_cds_tk.h" +#include "xp_cds_tk_balzam.h" +#include "xp_project.h" + + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + + +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// +///////////////////////////////////////////////////////// + + + + + + + +void tkak_init_plate(int k, int tkak0_off_protect, int tk_disable_output_a, int tk_disable_output_b) +{ + unsigned int t_ticks; + //tkak 0 + project.cds_tk[k].status_serial_bus.max_read_error = MAX_READ_SBUS;// SERIAL_BUS Timing setup + + + if (k==3) + { +// project.cds_tk[k].setup_pbus.use_reg_in_pbus.all = 0x0; // PBUS all off + // + if (tkak0_off_protect==1) + project.cds_tk[k].write.sbus.mask_protect_tk.all = 0x0000; // only break ack+cur + else + project.cds_tk[k].write.sbus.mask_protect_tk.all = 0x0303; // only break ack+cur + +// project.cds_tk[k].write.sbus.mask_tk_out_40pin.all = 0x0003; // optical bus+break + project.cds_tk[k].write.sbus.mask_tk_out_40pin.all = 0x00cf; // optical bus+break + +#if (TKAK_VERSION==TKAK_EDRK) + project.cds_tk[k].write.sbus.ack_time.bit.time = (int)(TK_ACKN_TIME_MKS / 0.02); + project.cds_tk[k].write.sbus.dead_min_time.bit.mintime = (int)(TK_MIN_TIME_MKS / DIV_TIME_TK); + project.cds_tk[k].write.sbus.dead_min_time.bit.deadtime = (int)(TK_DEAD_TIME_MKS / DIV_TIME_TK); +#endif + +#if (TKAK_VERSION==TKAK_23550) + project.cds_tk[k].write.sbus.ack_time.bit.time = (int)(TK_ACKN_TIME_NS/1000.0 / 0.02); + project.cds_tk[k].write.sbus.dead_min_time.bit.mintime = (int)(TK_MIN_TIME_NS/1000.0 / DIV_TIME_TK); + project.cds_tk[k].write.sbus.dead_min_time.bit.deadtime = (int)(TK_DEAD_TIME_NS/1000.0 / DIV_TIME_TK); +#endif + } + else + { + project.cds_tk[k].setup_pbus.use_reg_in_pbus.all = 0x0; // PBUS all off + + if (tk_disable_output_a==1 && tk_disable_output_b==1) + { + project.cds_tk[k].write.sbus.mask_tk_out_40pin.all = 0x0000; //mask key 1-use key,0-not use key + project.cds_tk[k].write.sbus.mask_protect_tk.all = 0xff00; // cur+ack 1-on protect. + } + else + if (tk_disable_output_a==0 && tk_disable_output_b==1) + { + project.cds_tk[k].write.sbus.mask_tk_out_40pin.all = 0x000f; //mask key 1-use key,0-not use key + project.cds_tk[k].write.sbus.mask_protect_tk.all = 0x0f0f; // cur+ack 1-on protect. + } + else + if (tk_disable_output_a==1 && tk_disable_output_b==0) + { + project.cds_tk[k].write.sbus.mask_tk_out_40pin.all = 0x00f0; //mask key 1-use key,0-not use key + project.cds_tk[k].write.sbus.mask_protect_tk.all = 0xf0f0; // cur+ack 1-on protect. + } + else + if (tk_disable_output_a==0 && tk_disable_output_b==0) + { + project.cds_tk[k].write.sbus.mask_tk_out_40pin.all = 0x00ff; //mask key 1-use key,0-not use key + project.cds_tk[k].write.sbus.mask_protect_tk.all = 0xffff; // cur+ack 1-on protect. + } + + if (tkak0_off_protect==1) + project.cds_tk[k].write.sbus.mask_protect_tk.all = 0x0000; // cur+ack 1-on protect. + + +#if (TKAK_VERSION==TKAK_EDRK) + project.cds_tk[k].write.sbus.ack_time.bit.time = (int)(TK_ACKN_TIME_MKS / 0.02); + project.cds_tk[k].write.sbus.dead_min_time.bit.mintime = (int)(TK_MIN_TIME_MKS / DIV_TIME_TK); + project.cds_tk[k].write.sbus.dead_min_time.bit.deadtime = (int)(TK_DEAD_TIME_MKS / DIV_TIME_TK); +#endif + + +#if (TKAK_VERSION==TKAK_23550) + + +// TK_ACKN_TIME_NS + + t_ticks = (unsigned int)(TK_ACKN_TIME_NS / DIV_TIME_TK_ACKN); + +#if (TK_ACKN_TIME_NS>(DIV_TIME_TK_ACKN*255)) +#error "TK_ACKN_TIME_NS !" +#endif + project.cds_tk[k].write.sbus.ack_time.bit.time = (unsigned int)t_ticks; + + +// TK_MIN_TIME_NS + + t_ticks = (unsigned int)(TK_MIN_TIME_NS / DIV_TIME_TK_MIN); + +#if (TK_MIN_TIME_NS>(DIV_TIME_TK_MIN*255)) +#error "TK_MIN_TIME_NS !" +#endif + + project.cds_tk[k].write.sbus.dead_min_time.bit.mintime = (unsigned int)t_ticks; + + +//TK_DEAD_TIME_NS + + // dead_time = 5 , - 5 + t_ticks = (unsigned int)(TK_DEAD_TIME_NS / DIV_TIME_TK_DEAD); + +#if (TK_DEAD_TIME_NS>(DIV_TIME_TK_DEAD*255)) +#error "TK_DEAD_TIME_MKS !" +#endif + project.cds_tk[k].write.sbus.dead_min_time.bit.deadtime = (unsigned int)(t_ticks); + + +// TK_SOFT_OFF_TIME_NS + + t_ticks = (unsigned int)(TK_SOFT_OFF_TIME_NS / DIV_TIME_TK_SOFT_OFF); + +#if (TK_SOFT_OFF_TIME_NS>(DIV_TIME_TK_SOFT_OFF*65535)) +#error "TK_SOFT_OFF_TIME_MKS !" +#endif + project.cds_tk[k].write.sbus.time_after_err = (unsigned int)t_ticks; + +#endif + + + + + project.cds_tk[k].write.sbus.protect_error.bit.enable_soft_disconnect = 1; + project.cds_tk[k].write.sbus.protect_error.bit.detect_soft_disconnect = 0;//1; + + } + + if (tkak0_off_protect==1) + { + project.cds_tk[k].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_tk[k].write.sbus.protect_error.bit.enable_err_switch = 0; + project.cds_tk[k].write.sbus.protect_error.bit.disable_err_hwp = 0; + project.cds_tk[k].write.sbus.protect_error.bit.disable_err0_in = 0; + project.cds_tk[k].write.sbus.protect_error.bit.disable_err_mintime = 0; + project.cds_tk[k].write.sbus.protect_error.bit.enable_line_err = 0; + project.cds_tk[k].write.sbus.protect_error.bit.enable_soft_disconnect = 0; + project.cds_tk[k].write.sbus.protect_error.bit.detect_soft_disconnect = 0; + } + else + { + + project.cds_tk[k].write.sbus.protect_error.bit.enable_err_power = 1; + project.cds_tk[k].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_tk[k].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_tk[k].write.sbus.protect_error.bit.disable_err_mintime = 1; + project.cds_tk[k].write.sbus.protect_error.bit.enable_line_err = 1;//1;//0;//1; + + // ! ! + if (project.cds_tk[k].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_tk[k].write.sbus.protect_error.bit.enable_err_switch = 0; + else + project.cds_tk[k].write.sbus.protect_error.bit.enable_err_switch = 1; + } + + +} + + +//////////////////////////////////////////////////////////////// +// . HWP +//////////////////////////////////////////////////////////////// +void project_prepare_config(void) +{ + int k = 0; +// write here setup for all plates +// +// +// +// ... +// project.cds_tk[0].write.sbus.ack_time.bit.delay = ...; + + + + +////////////////////////////////////////////////////////////////// +/// +// PBUS +///////////////////////////////////////////////////////////////// + +#if (USE_IN_0) + project.cds_in[0].type_plate = cds_in_type_in_1; +////////////////////////////////////////////////////////////////// +// PBUS IN0 sensors +// + project.cds_in[0].setup_pbus.use_reg_in_pbus.all = 0; +//DataFromIn + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg0 = 1; // use +//Gotov + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg1 = 1; // use +//Direction + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg2 = 1; // use + +//#if (ENABLE_ROTOR_SENSOR_1_PBUS==1) +// sensor1 +//SpeedS1_cnt + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg3 = 1; // use +//SpeedS1_cnt90 + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg4 = 1; // use +//#endif + +//#if (ENABLE_ROTOR_SENSOR_2_PBUS==1) +// sensor2 +//SpeedS2_cnt + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg5 = 1; // use +//SpeedS2_cnt90 + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg6 = 1; // use +//#endif + +//#if (TYPE_CDS_XILINX_IN_0==TYPE_CDS_XILINX_SP2) +// if (project.cds_in[0].type_cds_xilinx == TYPE_CDS_XILINX_SP2) +//is Channel Alive +// project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg13 = 1; // use +//#endif + + + if (project.cds_in[0].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + + #if (ENABLE_ROTOR_SENSOR_1_PBUS==1) + //Time since zero point S1 + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg7 = 1; // use + // Impulses since zero point Rising S1 + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg8 = 1; // use + //Impulses since zero point Falling S1 + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg9 = 1; // use + #endif + + + #if (ENABLE_ROTOR_SENSOR_2_PBUS==1) + //Time since zero point S2 + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg10 = 1; // use + // Impulses since zero point Rising S2 + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg11 = 1; // use + //Impulses since zero point Falling S2 + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg12 = 1; // use + #endif + + //is Channel Alive + project.cds_in[0].setup_pbus.use_reg_in_pbus.bit.reg13 = 1; // use + + } + project.cds_in[0].status_serial_bus.max_read_error = MAX_READ_SBUS; + + +#endif + + +#if (USE_IN_1) + project.cds_in[1].type_plate = cds_in_type_in_2; +// IN1 + project.cds_in[1].setup_pbus.use_reg_in_pbus.all = 0; + project.cds_in[1].setup_pbus.use_reg_in_pbus.bit.reg0 = 1; // use + project.cds_in[1].setup_pbus.use_reg_in_pbus.bit.reg1 = 0; // not use + project.cds_in[1].setup_pbus.use_reg_in_pbus.bit.reg2 = 0; // not use + + project.cds_in[1].status_serial_bus.max_read_error = MAX_READ_SBUS; + +#endif + +#if (USE_IN_2) + project.cds_in[2].type_plate = cds_in_type_in_2; +// IN2 + project.cds_in[2].setup_pbus.use_reg_in_pbus.all = 0; + project.cds_in[2].setup_pbus.use_reg_in_pbus.bit.reg0 = 1; // use + project.cds_in[2].setup_pbus.use_reg_in_pbus.bit.reg1 = 0; // not use + project.cds_in[2].setup_pbus.use_reg_in_pbus.bit.reg2 = 0; // not use + project.cds_in[2].status_serial_bus.max_read_error = MAX_READ_SBUS; + +#endif + +#if (USE_ROT_1) +// CDS_RS + project.cds_rs[0].setup_pbus.use_reg_in_pbus.all = 0xffff; // use all 16 +#endif + +#if (USE_ADC_0) +//ADC0 + project.adc[0].setup_pbus.use_reg_in_pbus.all = 0xffff; // use all 16 + ///////////////////////////////////////////////////////////////////////////// + // SERIAL_BUS Timing setup + ///////////////////////////////////////////////////////////////////////////// + project.adc[0].status_serial_bus.max_read_error = 2;//MAX_READ_SBUS; + project.adc[0].status_serial_bus.max_write_error = 2;//MAX_READ_SBUS; +#endif + +#if (USE_ADC_1) +//ADC1 + project.adc[1].setup_pbus.use_reg_in_pbus.all = 0xffff; // use all 16 + ///////////////////////////////////////////////////////////////////////////// + // SERIAL_BUS Timing setup + ///////////////////////////////////////////////////////////////////////////// + project.adc[1].status_serial_bus.max_read_error = 2;//MAX_READ_SBUS; + project.adc[1].status_serial_bus.max_write_error = 2;//MAX_READ_SBUS; + +#endif + +#if (USE_ADC_2) +//ADC1 + project.adc[1].setup_pbus.use_reg_in_pbus.all = 0xffff; // use all 16 + ///////////////////////////////////////////////////////////////////////////// + // SERIAL_BUS Timing setup + ///////////////////////////////////////////////////////////////////////////// + + project.adc[1].status_serial_bus.max_read_error = 2;//MAX_READ_SBUS; + project.adc[1].status_serial_bus.max_write_error = 2;//MAX_READ_SBUS; + +#endif + + + +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + +#if (USE_TK_0) + tkak_init_plate(0, TKAK0_OFF_PROTECT, TK_DISABLE_OUTPUT_A1, TK_DISABLE_OUTPUT_B1); +#endif +#if (USE_TK_1) + tkak_init_plate(1, TKAK1_OFF_PROTECT, TK_DISABLE_OUTPUT_C1, TK_DISABLE_OUTPUT_A2); +#endif +#if (USE_TK_2) + tkak_init_plate(2, TKAK2_OFF_PROTECT, TK_DISABLE_OUTPUT_B2, TK_DISABLE_OUTPUT_C2); +#endif + +#if (USE_TK_3) + tkak_init_plate(3, TKAK3_OFF_PROTECT, 0, 0); +#endif + +/* +#if (USE_TK_0) +//tkak 0 + project.cds_tk[0].status_serial_bus.max_read_error = MAX_READ_SBUS;// SERIAL_BUS Timing setup + project.cds_tk[0].setup_pbus.use_reg_in_pbus.all = 0x0; // PBUS all off + +#if (TK_DISABLE_OUTPUT_A1==1 && TK_DISABLE_OUTPUT_B1==1) + project.cds_tk[0].write.sbus.mask_tk_out_40pin.all = 0x0000; //mask key 1-use key,0-not use key + project.cds_tk[0].write.sbus.mask_protect_tk.all = 0xff00; // cur+ack 1-on protect. +#else +#if (TK_DISABLE_OUTPUT_A1==0 && TK_DISABLE_OUTPUT_B1==1) + project.cds_tk[0].write.sbus.mask_tk_out_40pin.all = 0x000f; //mask key 1-use key,0-not use key + project.cds_tk[0].write.sbus.mask_protect_tk.all = 0xff0f; // cur+ack 1-on protect. +#else +#if (TK_DISABLE_OUTPUT_A1==1 && TK_DISABLE_OUTPUT_B1==0) + project.cds_tk[0].write.sbus.mask_tk_out_40pin.all = 0x00f0; //mask key 1-use key,0-not use key + project.cds_tk[0].write.sbus.mask_protect_tk.all = 0xfff0; // cur+ack 1-on protect. +#else +#if (TK_DISABLE_OUTPUT_A1==0 && TK_DISABLE_OUTPUT_B1==0) + project.cds_tk[0].write.sbus.mask_tk_out_40pin.all = 0x00ff; //mask key 1-use key,0-not use key + project.cds_tk[0].write.sbus.mask_protect_tk.all = 0xffff; // cur+ack 1-on protect. +#endif +#endif +#endif +#endif + +#if (TKAK0_OFF_PROTECT==1) + project.cds_tk[0].write.sbus.mask_protect_tk.all = 0x0000; // cur+ack 1-on protect. +#endif + + + project.cds_tk[0].write.sbus.ack_time.bit.time = (int)(TK_ACKN_TIME_MKS / 0.02); + project.cds_tk[0].write.sbus.dead_min_time.bit.mintime = (int)(TK_MIN_TIME_MKS / DIV_TIME_TK); + project.cds_tk[0].write.sbus.dead_min_time.bit.deadtime = (int)(TK_DEAD_TIME_MKS / DIV_TIME_TK); + + + +#if (TKAK0_OFF_PROTECT==1) + project.cds_tk[0].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_tk[0].write.sbus.protect_error.bit.enable_err_switch = 0; + project.cds_tk[0].write.sbus.protect_error.bit.disable_err_hwp = 0; + project.cds_tk[0].write.sbus.protect_error.bit.disable_err0_in = 0; + project.cds_tk[0].write.sbus.protect_error.bit.disable_err_mintime = 0; + project.cds_tk[0].write.sbus.protect_error.bit.enable_line_err = 0; +#else + + + project.cds_tk[0].write.sbus.protect_error.bit.enable_err_power = 1; + project.cds_tk[0].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_tk[0].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_tk[0].write.sbus.protect_error.bit.disable_err_mintime = 1; + project.cds_tk[0].write.sbus.protect_error.bit.enable_line_err = 1; + + // ! ! + if (project.cds_tk[0].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_tk[0].write.sbus.protect_error.bit.enable_err_switch = 0; + else + project.cds_tk[0].write.sbus.protect_error.bit.enable_err_switch = 1; + + +#endif + + +#endif + + +#if (USE_TK_1) +////////////////////////////////////////////////////////////// +// tkak1 + project.cds_tk[1].status_serial_bus.max_read_error = MAX_READ_SBUS;// SERIAL_BUS Timing setup + project.cds_tk[1].setup_pbus.use_reg_in_pbus.all = 0x0; // PBUS all off + + +#if (TK_DISABLE_OUTPUT_C1==1 && TK_DISABLE_OUTPUT_A2==1) + project.cds_tk[1].write.sbus.mask_tk_out_40pin.all = 0x0000; //mask key 1-use key,0-not use key + project.cds_tk[1].write.sbus.mask_protect_tk.all = 0xff00; // cur+ack 1-on protect. +#else +#if (TK_DISABLE_OUTPUT_C1==0 && TK_DISABLE_OUTPUT_A2==1) + project.cds_tk[1].write.sbus.mask_tk_out_40pin.all = 0x000f; //mask key 1-use key,0-not use key + project.cds_tk[1].write.sbus.mask_protect_tk.all = 0xff0f; // cur+ack 1-on protect. +#else +#if (TK_DISABLE_OUTPUT_C1==1 && TK_DISABLE_OUTPUT_A2==0) + project.cds_tk[1].write.sbus.mask_tk_out_40pin.all = 0x00f0; //mask key 1-use key,0-not use key + project.cds_tk[1].write.sbus.mask_protect_tk.all = 0xfff0; // cur+ack 1-on protect. +#else +#if (TK_DISABLE_OUTPUT_C1==0 && TK_DISABLE_OUTPUT_A2==0) + project.cds_tk[1].write.sbus.mask_tk_out_40pin.all = 0x00ff; //mask key 1-use key,0-not use key + project.cds_tk[1].write.sbus.mask_protect_tk.all = 0xffff; // cur+ack 1-on protect. +#endif +#endif +#endif +#endif + + +#if (TKAK1_OFF_PROTECT==1) + project.cds_tk[1].write.sbus.mask_protect_tk.all = 0x0000; // cur+ack 1-on protect. +#endif + + project.cds_tk[1].write.sbus.ack_time.bit.time = (int)(TK_ACKN_TIME_MKS / 0.02); + project.cds_tk[1].write.sbus.dead_min_time.bit.mintime = (int)(TK_MIN_TIME_MKS / DIV_TIME_TK); + project.cds_tk[1].write.sbus.dead_min_time.bit.deadtime = (int)(TK_DEAD_TIME_MKS / DIV_TIME_TK); + +#if (TKAK1_OFF_PROTECT==1) + project.cds_tk[1].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_tk[1].write.sbus.protect_error.bit.enable_err_switch = 0; + project.cds_tk[1].write.sbus.protect_error.bit.disable_err_hwp = 0; + project.cds_tk[1].write.sbus.protect_error.bit.disable_err0_in = 0; + project.cds_tk[1].write.sbus.protect_error.bit.disable_err_mintime = 0; + project.cds_tk[1].write.sbus.protect_error.bit.enable_line_err = 0; +#else + + project.cds_tk[1].write.sbus.protect_error.bit.enable_err_power = 1; + project.cds_tk[1].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_tk[1].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_tk[1].write.sbus.protect_error.bit.disable_err_mintime = 1; + project.cds_tk[1].write.sbus.protect_error.bit.enable_line_err = 1; + + // ! ! + if (project.cds_tk[1].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_tk[1].write.sbus.protect_error.bit.enable_err_switch = 0; + else + project.cds_tk[1].write.sbus.protect_error.bit.enable_err_switch = 1; + +#endif + +#endif + + +#if (USE_TK_2) +////////////////////////////////////////////////////////////// +// tkak2 + project.cds_tk[2].status_serial_bus.max_read_error = MAX_READ_SBUS;// SERIAL_BUS Timing setup + project.cds_tk[2].setup_pbus.use_reg_in_pbus.all = 0x0; // PBUS all off + +#if (TK_DISABLE_OUTPUT_B2==1 && TK_DISABLE_OUTPUT_C2==1) + project.cds_tk[2].write.sbus.mask_tk_out_40pin.all = 0x0000; //mask key 1-use key,0-not use key + project.cds_tk[2].write.sbus.mask_protect_tk.all = 0xff00; // cur+ack 1-on protect. +#else +#if (TK_DISABLE_OUTPUT_B2==0 && TK_DISABLE_OUTPUT_C2==1) + project.cds_tk[2].write.sbus.mask_tk_out_40pin.all = 0x000f; //mask key 1-use key,0-not use key + project.cds_tk[2].write.sbus.mask_protect_tk.all = 0xff0f; // cur+ack 1-on protect. +#else +#if (TK_DISABLE_OUTPUT_B2==1 && TK_DISABLE_OUTPUT_C2==0) + project.cds_tk[2].write.sbus.mask_tk_out_40pin.all = 0x00f0; //mask key 1-use key,0-not use key + project.cds_tk[2].write.sbus.mask_protect_tk.all = 0xfff0; // cur+ack 1-on protect. +#else +#if (TK_DISABLE_OUTPUT_B2==0 && TK_DISABLE_OUTPUT_C2==0) + project.cds_tk[2].write.sbus.mask_tk_out_40pin.all = 0x00ff; //mask key 1-use key,0-not use key + project.cds_tk[2].write.sbus.mask_protect_tk.all = 0xffff; // cur+ack 1-on protect. +#endif +#endif +#endif +#endif + +#if (TKAK1_OFF_PROTECT==1) + project.cds_tk[2].write.sbus.mask_protect_tk.all = 0x0000; // cur+ack 1-on protect. +#endif + + + project.cds_tk[2].write.sbus.ack_time.bit.time = (int)(TK_ACKN_TIME_MKS / 0.02); + project.cds_tk[2].write.sbus.dead_min_time.bit.mintime = (int)(TK_MIN_TIME_MKS / DIV_TIME_TK); + project.cds_tk[2].write.sbus.dead_min_time.bit.deadtime = (int)(TK_DEAD_TIME_MKS / DIV_TIME_TK); + +#if (TKAK2_OFF_PROTECT==1) + + project.cds_tk[2].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_tk[2].write.sbus.protect_error.bit.enable_err_switch = 0; + project.cds_tk[2].write.sbus.protect_error.bit.disable_err_hwp = 0; + project.cds_tk[2].write.sbus.protect_error.bit.disable_err0_in = 0; + project.cds_tk[2].write.sbus.protect_error.bit.disable_err_mintime = 0; + project.cds_tk[2].write.sbus.protect_error.bit.enable_line_err = 0; + +#else + + project.cds_tk[2].write.sbus.protect_error.bit.enable_err_power = 1; + project.cds_tk[2].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_tk[2].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_tk[2].write.sbus.protect_error.bit.disable_err_mintime = 1; + project.cds_tk[2].write.sbus.protect_error.bit.enable_line_err = 1; + + // ! ! + if (project.cds_tk[2].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_tk[2].write.sbus.protect_error.bit.enable_err_switch = 0; + else + project.cds_tk[2].write.sbus.protect_error.bit.enable_err_switch = 1; + +#endif + +#endif + + + +#if (USE_TK_3) +////////////////////////////////////////////////////////////// + +// + project.cds_tk[3].status_serial_bus.max_read_error = MAX_READ_SBUS;// SERIAL_BUS Timing setup +// project.cds_tk[3].setup_pbus.use_reg_in_pbus.all = 0x0; // PBUS all off + +#if (TKAK3_OFF_PROTECT==1) + project.cds_tk[3].write.sbus.mask_protect_tk.all = 0x0000; // only break ack+cur +#else + project.cds_tk[3].write.sbus.mask_protect_tk.all = 0x0303; // only break ack+cur +#endif + project.cds_tk[3].write.sbus.mask_tk_out_40pin.all = 0x00cf; // optical bus+break + + project.cds_tk[3].write.sbus.ack_time.bit.time = (int)(TK_ACKN_TIME_MKS / 0.02); + project.cds_tk[3].write.sbus.dead_min_time.bit.mintime = (int)(TK_MIN_TIME_MKS / DIV_TIME_TK); + project.cds_tk[3].write.sbus.dead_min_time.bit.deadtime = (int)(TK_DEAD_TIME_MKS / DIV_TIME_TK); + + +#if (TKAK3_OFF_PROTECT==1) + + project.cds_tk[3].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_tk[3].write.sbus.protect_error.bit.enable_err_switch = 0; + project.cds_tk[3].write.sbus.protect_error.bit.disable_err_hwp = 0; + project.cds_tk[3].write.sbus.protect_error.bit.disable_err0_in = 0; + project.cds_tk[3].write.sbus.protect_error.bit.disable_err_mintime = 0; + project.cds_tk[3].write.sbus.protect_error.bit.enable_line_err = 0; + +#else + + project.cds_tk[3].write.sbus.protect_error.bit.enable_err_power = 1; + project.cds_tk[3].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_tk[3].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_tk[3].write.sbus.protect_error.bit.disable_err_mintime = 1; + project.cds_tk[3].write.sbus.protect_error.bit.enable_line_err = 1; + + // ! ! + if (project.cds_tk[3].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_tk[3].write.sbus.protect_error.bit.enable_err_switch = 0; + else + project.cds_tk[3].write.sbus.protect_error.bit.enable_err_switch = 1; + + +#endif + +#endif +*/ +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + +// Out plane setup + + +#if (USE_OUT_0) +////////////////////////////////////////////////////////////// +// out0 + + project.cds_out[0].status_serial_bus.max_read_error = MAX_READ_SBUS;// SERIAL_BUS Timing setup + + + +#if (OUT0_OFF_PROTECT==1) + + project.cds_out[0].write.sbus.protect_error.bit.disable_err0_in = 0; + project.cds_out[0].write.sbus.protect_error.bit.disable_err_hwp = 0; + project.cds_out[0].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_out[0].write.sbus.protect_error.bit.enable_err_switch = 0; + +#else + + project.cds_out[0].write.sbus.protect_error.bit.enable_err_power = 1; + project.cds_out[0].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_out[0].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_out[0].write.sbus.protect_error.bit.enable_err_switch = 1; + // ! ! + if (project.cds_out[0].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_out[0].write.sbus.protect_error.bit.enable_err_switch = 0; + else + project.cds_out[0].write.sbus.protect_error.bit.enable_err_switch = 1; + +#endif + + project.cds_out[0].write.sbus.enable_protect_out.all = 0x0000; + + +// OUT ERR + project.cds_out[0].write.sbus.enable_protect_out.bit.dout0 = 1; // . + project.cds_out[0].write.sbus.enable_protect_out.bit.dout6 = 1; // 6 - QTV +// project.cds_out[0].write.sbus.enable_protect_out.bit.dout7 = 1; // QTV OFF + project.cds_out[0].write.sbus.enable_protect_out.bit.dout8 = 1; // 8 - QTV + project.cds_out[0].write.sbus.enable_protect_out.bit.dout13 = 1; // 13 - + +#endif + +#if (USE_OUT_1) + +// out1 + project.cds_out[1].status_serial_bus.max_read_error = MAX_READ_SBUS;// SERIAL_BUS Timing setup + +#if (OUT1_OFF_PROTECT==1) + + project.cds_out[1].write.sbus.protect_error.bit.disable_err0_in = 0; + project.cds_out[1].write.sbus.protect_error.bit.disable_err_hwp = 0; + project.cds_out[1].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_out[1].write.sbus.protect_error.bit.enable_err_switch = 0; + +#else + project.cds_out[1].write.sbus.protect_error.bit.enable_err_power = 1; + project.cds_out[1].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_out[1].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_out[1].write.sbus.protect_error.bit.enable_err_switch = 1; + + + project.cds_out[1].write.sbus.protect_error.bit.enable_err_power = 1; + // ! ! + if (project.cds_out[1].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_out[1].write.sbus.protect_error.bit.enable_err_switch = 0; + else + project.cds_out[1].write.sbus.protect_error.bit.enable_err_switch = 1; +#endif + + project.cds_out[1].write.sbus.enable_protect_out.all = 0x0000; + +#endif + +#if (USE_OUT_2) + +//out2 + project.cds_out[2].status_serial_bus.max_read_error = MAX_READ_SBUS;// SERIAL_BUS Timing setup + + + project.cds_out[2].write.sbus.protect_error.bit.enable_err_power = 1; + project.cds_out[2].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_out[2].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_out[2].write.sbus.protect_error.bit.enable_err_switch = 1; + + + project.cds_out[2].write.sbus.protect_error.bit.enable_err_power = 1; + + // ! ! + if (project.cds_out[2].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_out[2].write.sbus.protect_error.bit.enable_err_switch = 0; + else + project.cds_out[2].write.sbus.protect_error.bit.enable_err_switch = 1; + + project.cds_out[2].write.sbus.enable_protect_out.all = 0x0000; + +#endif + +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///////////// + +#if (USE_IN_0) + +///////////////////////////////////////////////////////////////////// +// setup incremental sensor rotor +///////////////////////////////////////////////////////////////////// +// +// 1 - 20ns 0 - 2us. + project.cds_in[0].write.sbus.enabled_channels.bit.discret = 0; + + +// In0- , In1-, In2-90. +// , 67 , +// In1-, In2-90. + + project.cds_in[0].write.sbus.enabled_channels.bit.sens_1_direct_ch = 1; //1 + project.cds_in[0].write.sbus.enabled_channels.bit.sens_1_direct_ch_90deg = 1; //0 + project.cds_in[0].write.sbus.enabled_channels.bit.sens_1_inv_ch = 0; + project.cds_in[0].write.sbus.enabled_channels.bit.sens_1_inv_ch_90deg = 0; + + project.cds_in[0].write.sbus.enabled_channels.bit.sens_2_direct_ch = 1; + project.cds_in[0].write.sbus.enabled_channels.bit.sens_2_direct_ch_90deg = 1; + project.cds_in[0].write.sbus.enabled_channels.bit.sens_2_inv_ch = 0; + project.cds_in[0].write.sbus.enabled_channels.bit.sens_2_inv_ch_90deg = 0; + +// In1-, In2-90. +// 0xf + project.cds_in[0].write.sbus.first_sensor.bit.direct_ch = 0x0; // in2 + project.cds_in[0].write.sbus.first_sensor.bit.direct_ch_90deg = 0x1; // in1 +// + project.cds_in[0].write.sbus.first_sensor.bit.inv_ch = 0x0f; // in0 + project.cds_in[0].write.sbus.first_sensor.bit.inv_ch_90deg = 0x0f; // in0 + +// , In2-, In1-90. + project.cds_in[0].write.sbus.second_sensor.bit.direct_ch = 0x01; // in0 + project.cds_in[0].write.sbus.second_sensor.bit.direct_ch_90deg = 0x00; // in1 +// + project.cds_in[0].write.sbus.second_sensor.bit.inv_ch = 0x0f; // in0 + project.cds_in[0].write.sbus.second_sensor.bit.inv_ch_90deg = 0x0f; // in0 +// + project.cds_in[0].write.sbus.zero_sensors.bit.for_sensor1 = 0x02; // + project.cds_in[0].write.sbus.zero_sensors.bit.for_sensor2 = 0x0f; // +// + project.cds_in[0].write.sbus.zero_sensors.bit.enable_sensor1 = 1; + project.cds_in[0].write.sbus.zero_sensors.bit.enable_sensor2 = 0; + +///////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////// + +// In plane setup +//in0 + +#if (IN0_OFF_PROTECT==1) + + project.cds_in[0].write.sbus.protect_error.bit.disable_err0_in = 0; + project.cds_in[0].write.sbus.protect_error.bit.disable_err_hwp = 0; + project.cds_in[0].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_in[0].write.sbus.protect_error.bit.enable_err_switch = 0; + +#else + + project.cds_in[0].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_in[0].write.sbus.protect_error.bit.disable_err_hwp = 1; + + // ! ! + if (project.cds_in[0].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + project.cds_in[0].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_in[0].write.sbus.protect_error.bit.enable_err_switch = 0; + } + else + { + project.cds_in[0].write.sbus.protect_error.bit.enable_err_power = 1; + project.cds_in[0].write.sbus.protect_error.bit.enable_err_switch = 1; + } + +#endif + + +#endif + + +#if (USE_IN_1) + +// in1 + +#if (IN1_OFF_PROTECT==1) + + project.cds_in[1].write.sbus.protect_error.bit.disable_err0_in = 0; + project.cds_in[1].write.sbus.protect_error.bit.disable_err_hwp = 0; + project.cds_in[1].write.sbus.protect_error.bit.enable_err_power = 0; + project.cds_in[1].write.sbus.protect_error.bit.enable_err_switch = 0; + +#else + + + project.cds_in[1].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_in[1].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_in[1].write.sbus.protect_error.bit.enable_err_power = 1; + + // ! ! + if (project.cds_in[1].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_in[1].write.sbus.protect_error.bit.enable_err_switch = 0; + else + project.cds_in[1].write.sbus.protect_error.bit.enable_err_switch = 1; + +#endif + +#endif + + + +#if (USE_IN_2) + +// in2 + project.cds_in[2].write.sbus.protect_error.bit.disable_err0_in = 1; + project.cds_in[2].write.sbus.protect_error.bit.disable_err_hwp = 1; + project.cds_in[2].write.sbus.protect_error.bit.enable_err_power = 1; + + // ! ! + if (project.cds_in[2].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + project.cds_in[2].write.sbus.protect_error.bit.enable_err_switch = 0; + + else + project.cds_in[2].write.sbus.protect_error.bit.enable_err_switch = 1; + + +#endif + +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +#if (USE_HWP_0) + + // HWP setup +// project.hwp[0].write.HWP_Speed = MODE_HWP_SPEED_AUTO;//MODE_HWP_SPEED_NORMAL;// MODE_HWP_SPEED_AUTO; // MODE_HWP_SPEED_SLOW;//MODE_HWP_SPEED_NORMAL;// MODE_HWP_SPEED_SLOW; + + project.hwp[0].write.test_all_channel = 1; + + project.hwp[0].write.use_channel.minus.all = 0xfffc; + project.hwp[0].write.use_channel.plus.all = 0xffff; + +/* + project.hwp[0].write.use_channel.plus.bit.ch0 = 1; + + project.hwp[0].write.use_channel.minus.bit.ch5 = 1; + project.hwp[0].write.use_channel.plus.bit.ch5 = 1; + + project.hwp[0].write.use_channel.minus.bit.ch11 = 1; + project.hwp[0].write.use_channel.plus.bit.ch11 = 1; + +*/ + + project.hwp[0].write.values[0].plus = convert_real_to_mv_hwp(0,LEVEL_HWP_U_ZPT); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[0].minus = convert_real_to_mv_hwp(0,LEVEL_HWP_U_ZPT); + + project.hwp[0].write.values[1].plus = convert_real_to_mv_hwp(1,LEVEL_HWP_U_ZPT); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[1].minus = convert_real_to_mv_hwp(1,LEVEL_HWP_U_ZPT); + + project.hwp[0].write.values[2].plus = convert_real_to_mv_hwp(2,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[2].minus = convert_real_to_mv_hwp(2,LEVEL_HWP_I_AF); + project.hwp[0].write.values[3].plus = convert_real_to_mv_hwp(3,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[3].minus = convert_real_to_mv_hwp(3,LEVEL_HWP_I_AF); + project.hwp[0].write.values[4].plus = convert_real_to_mv_hwp(4,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[4].minus = convert_real_to_mv_hwp(4,LEVEL_HWP_I_AF); + project.hwp[0].write.values[5].plus = convert_real_to_mv_hwp(5,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[5].minus = convert_real_to_mv_hwp(5,LEVEL_HWP_I_AF); + project.hwp[0].write.values[6].plus = convert_real_to_mv_hwp(6,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[6].minus = convert_real_to_mv_hwp(6,LEVEL_HWP_I_AF); + project.hwp[0].write.values[7].plus = convert_real_to_mv_hwp(7,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[7].minus = convert_real_to_mv_hwp(7,LEVEL_HWP_I_AF); + + project.hwp[0].write.values[8].plus = convert_real_to_mv_hwp(8,LEVEL_HWP_I_ZPT); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[8].minus = convert_real_to_mv_hwp(8,LEVEL_HWP_I_ZPT); + project.hwp[0].write.values[9].plus = convert_real_to_mv_hwp(9,LEVEL_HWP_I_ZPT); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[9].minus = convert_real_to_mv_hwp(9,LEVEL_HWP_I_ZPT); + + project.hwp[0].write.use_channel.minus.bit.ch9 = 0; + project.hwp[0].write.use_channel.plus.bit.ch9 = 0; + + project.hwp[0].write.values[10].plus = convert_real_to_mv_hwp(10,LEVEL_HWP_U_ABC); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[10].minus = convert_real_to_mv_hwp(10,LEVEL_HWP_U_ABC); + project.hwp[0].write.values[11].plus = convert_real_to_mv_hwp(11,LEVEL_HWP_U_ABC); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[11].minus = convert_real_to_mv_hwp(11,LEVEL_HWP_U_ABC); + project.hwp[0].write.values[12].plus = convert_real_to_mv_hwp(12,LEVEL_HWP_U_ABC); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[12].minus = convert_real_to_mv_hwp(12,LEVEL_HWP_U_ABC); + project.hwp[0].write.values[13].plus = convert_real_to_mv_hwp(13,LEVEL_HWP_U_ABC); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[13].minus = convert_real_to_mv_hwp(13,LEVEL_HWP_U_ABC); + + + project.hwp[0].write.values[14].plus = convert_real_to_mv_hwp(14,LEVEL_HWP_I_BREAK); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[14].minus = convert_real_to_mv_hwp(14,LEVEL_HWP_I_BREAK); + project.hwp[0].write.values[15].plus = convert_real_to_mv_hwp(15,LEVEL_HWP_I_BREAK); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[0].write.values[15].minus = convert_real_to_mv_hwp(15,LEVEL_HWP_I_BREAK); +#endif +////////////////////////////////////////////////////////////// +#if (USE_HWP_1) + + // HWP setup + // project.hwp[1].write.HWP_Speed = MODE_HWP_SPEED_AUTO;//MODE_HWP_SPEED_NORMAL;// MODE_HWP_SPEED_SLOW; + project.hwp[1].write.test_all_channel = 1; + + project.hwp[1].write.use_channel.minus.all = 0xfffc; + project.hwp[1].write.use_channel.plus.all = 0xffff; + + + project.hwp[1].write.values[0].plus = convert_real_to_mv_hwp(0,LEVEL_HWP_U_ZPT); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[0].minus = convert_real_to_mv_hwp(0,LEVEL_HWP_U_ZPT); + + project.hwp[1].write.values[1].plus = convert_real_to_mv_hwp(1,LEVEL_HWP_U_ZPT); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[1].minus = convert_real_to_mv_hwp(1,LEVEL_HWP_U_ZPT); + + project.hwp[1].write.values[2].plus = convert_real_to_mv_hwp(2,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[2].minus = convert_real_to_mv_hwp(2,LEVEL_HWP_I_AF); + project.hwp[1].write.values[3].plus = convert_real_to_mv_hwp(3,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[3].minus = convert_real_to_mv_hwp(3,LEVEL_HWP_I_AF); + project.hwp[1].write.values[4].plus = convert_real_to_mv_hwp(4,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[4].minus = convert_real_to_mv_hwp(4,LEVEL_HWP_I_AF); + project.hwp[1].write.values[5].plus = convert_real_to_mv_hwp(5,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[5].minus = convert_real_to_mv_hwp(5,LEVEL_HWP_I_AF); + project.hwp[1].write.values[6].plus = convert_real_to_mv_hwp(6,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[6].minus = convert_real_to_mv_hwp(6,LEVEL_HWP_I_AF); + project.hwp[1].write.values[7].plus = convert_real_to_mv_hwp(7,LEVEL_HWP_I_AF); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[7].minus = convert_real_to_mv_hwp(7,LEVEL_HWP_I_AF); + + project.hwp[1].write.values[8].plus = convert_real_to_mv_hwp(8,LEVEL_HWP_I_ZPT); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[8].minus = convert_real_to_mv_hwp(8,LEVEL_HWP_I_ZPT); + project.hwp[1].write.values[9].plus = convert_real_to_mv_hwp(9,LEVEL_HWP_I_ZPT); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[9].minus = convert_real_to_mv_hwp(9,LEVEL_HWP_I_ZPT); + + + project.hwp[1].write.values[10].plus = convert_real_to_mv_hwp(10,LEVEL_HWP_U_ABC); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[10].minus = convert_real_to_mv_hwp(10,LEVEL_HWP_U_ABC); + project.hwp[1].write.values[11].plus = convert_real_to_mv_hwp(11,LEVEL_HWP_U_ABC); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[11].minus = convert_real_to_mv_hwp(11,LEVEL_HWP_U_ABC); + project.hwp[1].write.values[12].plus = convert_real_to_mv_hwp(12,LEVEL_HWP_U_ABC); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[12].minus = convert_real_to_mv_hwp(12,LEVEL_HWP_U_ABC); + project.hwp[1].write.values[13].plus = convert_real_to_mv_hwp(13,LEVEL_HWP_U_ABC); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[13].minus = convert_real_to_mv_hwp(13,LEVEL_HWP_U_ABC); + + + project.hwp[1].write.values[14].plus = convert_real_to_mv_hwp(14,LEVEL_HWP_I_BREAK); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[14].minus = convert_real_to_mv_hwp(14,LEVEL_HWP_I_BREAK); + project.hwp[1].write.values[15].plus = convert_real_to_mv_hwp(15,LEVEL_HWP_I_BREAK); //Uzpt1 //2 3000V - 845; 3977V - 1120; 2800V - 789; 2600V - 732 + project.hwp[1].write.values[15].minus = convert_real_to_mv_hwp(15,LEVEL_HWP_I_BREAK); + #endif + + +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + //Incremental sensor_init +#if (ENABLE_ROTOR_SENSOR_1_PM67==1) + inc_sensor.use_sensor1 = 1; +#else + inc_sensor.use_sensor1 = 0; +#endif + +#if (ENABLE_ROTOR_SENSOR_2_PM67==1) + inc_sensor.use_sensor2 = 1; +#else + inc_sensor.use_sensor2 = 0; +#endif + + +#if (ENABLE_COMBO_SENSOR_1_TO_2==1) + inc_sensor.use_sensor2 = 1; +#endif +#if (ENABLE_COMBO_SENSOR_2_TO_1==1) + inc_sensor.use_sensor1 = 1; +#endif + + + inc_sensor.pm67regs.write_comand_reg.bit.set_sampling_time = SAMPLING_TIME_MS; +// 23550 +// inc_sensor.pm67regs.write_comand_reg.bit.filter_sensitivity = 5; //0x0; // 170 . +// 22220 + inc_sensor.pm67regs.write_comand_reg.bit.filter_sensitivity = 300;//5; //0x0; // 170 . + + + + inc_sensor.set(&inc_sensor); + + //Rotation sensor_init +/* + rotation_sensor.in_plane.cds_in = &project.cds_in[0]; + rotation_sensor.use_sensor1 = 1; + rotation_sensor.use_sensor2 = 1; + rotation_sensor.use_angle_plane = 0; + + + + + rotation_sensor.in_plane.write.sbus.enabled_channels.bit.sens_1_direct_ch =1; + rotation_sensor.in_plane.write.sbus.enabled_channels.bit.sens_2_direct_ch_90deg =1; + +// rotation_sensor.in_plane.write.sbus.enabled_channels.bit.sens_1_direct_ch_90deg = 1; + +// rotation_sensor.in_plane.write.sbus.enabled_channels.bit.sens_2_direct_ch = 1; +// rotation_sensor.in_plane.write.sbus.enabled_channels.bit.sens_2_direct_ch_90deg = 1; + + rotation_sensor.in_plane.write.sbus.first_sensor_inputs.bit.direct_ch = 0; +// rotation_sensor.in_plane.write.sbus.first_sensor_inputs.bit.direct_ch_90deg = 1; + +// rotation_sensor.in_plane.write.sbus.second_sensor_inputs.bit.direct_ch = 3; + rotation_sensor.in_plane.write.sbus.second_sensor_inputs.bit.direct_ch_90deg = 1; + + + + + + + rotation_sensor.in_plane.write.regs.comand_reg.bit.set_sampling_time = SAMPLING_TIME_MS; + rotation_sensor.in_plane.write.regs.comand_reg.bit.filter_sensitivity = 0xF; // 170 . + +*/ + + + + + //filter 1 ~ 20nsec + /* rotation_sensor.rotation_plane.cds_rs = &project.cds_rs[0]; + rotation_sensor.rotation_plane.write.sbus.config.all = 0; + rotation_sensor.rotation_plane.write.sbus.config.bit.channel1_enable = 1; + rotation_sensor.rotation_plane.write.sbus.config.bit.plane_is_master = 1; + rotation_sensor.rotation_plane.write.sbus.config.bit.survey_time = 49; + rotation_sensor.rotation_plane.write.sbus.config.bit.transmition_speed = TS250; + */ +// rotation_sensor.set(&rotation_sensor); + + if (project.controller.status != component_Ready) + return; + +// project.load_cfg_to_plates(); + +} + + + diff --git a/Inu/Src2/551/main/project.h b/Inu/Src2/551/main/project.h new file mode 100644 index 0000000..32dba9a --- /dev/null +++ b/Inu/Src2/551/main/project.h @@ -0,0 +1,74 @@ +#ifndef PROJECT_H +#define PROJECT_H + + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_GlobalPrototypes.h" +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "DSP281x_Ev.h" // DSP281x Examples Include File +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "Spartan2E_Functions.h" +#include "TuneUpPlane.h" +#include "x_parallel_bus.h" +#include "x_serial_bus.h" +#include "xerror.h" +#include "xp_adc.h" +#include "xp_cds_in.h" +#include "xp_cds_out.h" +#include "xp_cds_tk.h" +#include "xp_controller.h" +#include "xp_hwp.h" +#include "xp_project.h" +#include "xPeriphSP6_loader.h" +//#include "xp_omega.h" +//#include "xp_dispatcher.h" + +//#include "x_error_buffer.h" + +//#include "x_project_plane.h" + +/* Define this macros to add to project files, contaning code */ +/* communicating with test terminal by RS232 */ +#define USE_TEST_TERMINAL 1 + +/* Define this macros to add to project files, contaning code */ +/* communicating with SVO and MPU by RS, using modbus protokol */ +#define USE_MODBUS_TABLE_SVU 1 + +/* Define this macros to add to project files, contaning code */ +/* communicating with Ingeteam Pult by RS, using modbus protocol */ +#define USE_MODBUS_TABLE_PULT 1 + + +// control_station.c control_station.h +#define USE_CONTROL_STATION 1 + + + + + +///////////////////////////////////////////////////////////////// +#ifndef USE_CONTROL_STATION +#define USE_CONTROL_STATION 0 +#endif + +#ifndef USE_TEST_TERMINAL +#define USE_TEST_TERMINAL 0 +#endif + +#ifndef USE_MODBUS_TABLE_SVU +#define USE_MODBUS_TABLE_SVU 0 +#endif + +#ifndef USE_MODBUS_TABLE_PULT +#define USE_MODBUS_TABLE_PULT 0 +#endif +//////////////////////////////////////////////////////////////// +// . HWP +//////////////////////////////////////////////////////////////// +void project_prepare_config(void); + + +#endif // end PROJECT_H diff --git a/Inu/Src2/551/main/project_setup.h b/Inu/Src2/551/main/project_setup.h new file mode 100644 index 0000000..4f3ec93 --- /dev/null +++ b/Inu/Src2/551/main/project_setup.h @@ -0,0 +1,414 @@ +#ifndef PROJECT_SETUP_H +#define PROJECT_SETUP_H + +/* + + myXilinx + C_PROJECT_TYPE + + project_setup.h /main/ + .. /myXilinx/ + .. ! +*/ + +/*------------------------------------------------------------------------------ + Project type +------------------------------------------------------------------------------*/ +// +///////////////////////////////////////////////////////////////////////////// +#define PROJECT_22220 10 +#define PROJECT_21300 11 +#define PROJECT_21180 12 +#define PROJECT_BALZAM 13 +#define PROJECT_23470 14 +#define PROJECT_23550 15 +#define PROJECT_10510 16 + + +#define PROJECT_STEND_D PROJECT_BALZAM + +/////////////////////////////////////////////// +// +/////////////////////////////////////////////// + +//#define C_PROJECT_TYPE PROJECT_21180 +//#define C_PROJECT_TYPE PROJECT_21300 +//#define C_PROJECT_TYPE PROJECT_22220 +//#define C_PROJECT_TYPE PROJECT_BALZAM +//#define C_PROJECT_TYPE PROJECT_23470 +//#define C_PROJECT_TYPE PROJECT_STEND_D + +#define C_PROJECT_TYPE PROJECT_23550 +//#define C_PROJECT_TYPE PROJECT_10510 + +// RS232 +#define RS232_SPEED_A 57600//115200//57600 +#define RS232_SPEED_B 57600//115200//57600// + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// +// +/////////////////////////////////////////////////////////////////////////////////// + +#if (C_PROJECT_TYPE==PROJECT_23550 || C_PROJECT_TYPE==PROJECT_BALZAM) +#define XPWMGEN 1 // xilinx 24 +#define TMSPWMGEN 0 // tms +#else +#define XPWMGEN 0 // xilinx 24 +#define TMSPWMGEN 1 // tms +#endif + + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +#if (TMSPWMGEN==1) && (XPWMGEN==1) + #error " . !!!" + +#endif + + +#if (TMSPWMGEN==1) + +#else //TMSPWMGEN + +#if (XPWMGEN==1) +#else + + #error " . !!!" + +#endif //XPWMGEN +#endif //TMSPWMGEN + +//////////////////////////////////////////////// +//////////////////////////////////////////////// +///////////////////////////////////////////////// +// +//////////////////////////////////////////////// +///////////////////////////////////////////////// +#if (_FLOOR6==0) +#define USE_ADC_0 1 +#define USE_ADC_1 1 +////#define USE_ADC_2 1 +// +#define USE_IN_0 1 + +#define USE_IN_1 1 +//////#define USE_IN_2 1 +//// +#define USE_OUT_0 1 +//////#define USE_OUT_1 1 +//////#define USE_OUT_2 1 +//// +//// +#define USE_TK_0 1 +#define USE_TK_1 1 +//// +#define USE_TK_2 1 +#define USE_TK_3 1 +//// +//////#define USE_TK_4 1 +//////#define USE_TK_5 1 +//////#define USE_TK_6 1 +//////#define USE_TK_7 1 +//// +#define USE_HWP_0 1 +////#define USE_HWP_1 1 +//////#define USE_HWP_2 1 +//// +//////#define USE_ROT_1 1 + +#else + +#if (_FLOOR6_ADD==1) + +#define USE_ADC_0 1 +#define USE_ADC_1 1 +////// +#define USE_IN_0 1 +//// +//#define USE_IN_1 1 +//////// +//#define USE_OUT_0 1 +//////// +//////// +#define USE_TK_0 1 +#define USE_TK_1 1 +////// +#define USE_TK_2 1 +#define USE_TK_3 1 + +//#define USE_HWP_0 1 + + +#else + +#define USE_ADC_0 1 +#define USE_ADC_1 1 +//// +#define USE_IN_0 1 +// +#define USE_IN_1 1 +////// +#define USE_OUT_0 1 +////// +////// +#define USE_TK_0 1 +#define USE_TK_1 1 +//// +#define USE_TK_2 1 +#define USE_TK_3 1 + +#define USE_HWP_0 1 +#define USE_HWP_1 1 + +#endif + +#endif + + +//////////////////////////////////////////////// +// SP2 SP6 +//////////////////////////////////////////////// +//////////////////////////////////////////////// +//////////////////////////////////////////////// + +#define TYPE_CDS_XILINX_IN_0 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_IN_1 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_IN_2 TYPE_CDS_XILINX_SP2 + +#define TYPE_CDS_XILINX_OUT_0 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_OUT_1 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_OUT_2 TYPE_CDS_XILINX_SP2 + +#define TYPE_CDS_XILINX_TK_0 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_TK_1 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_TK_2 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_TK_3 TYPE_CDS_XILINX_SP6 +#define TYPE_CDS_XILINX_TK_4 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_TK_5 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_TK_6 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_TK_7 TYPE_CDS_XILINX_SP2 + +#define TYPE_CDS_XILINX_ADC_0 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_ADC_1 TYPE_CDS_XILINX_SP2 +#define TYPE_CDS_XILINX_ADC_2 TYPE_CDS_XILINX_SP2 + +#define TYPE_CDS_XILINX_RS_0 TYPE_CDS_XILINX_SP2 + +//////////////////////////////////////////////// +//////////////////////////////////////////////// +//////////////////////////////////////////////// + +//#define TYPE_CDS_XILINX_HWP_0_1 MODE_HWP_SPEED_SLOW + +#ifndef USE_ADC_0 +#define USE_ADC_0 0 +#endif + +#ifndef USE_ADC_1 +#define USE_ADC_1 0 +#endif + +#ifndef USE_ADC_2 +#define USE_ADC_2 0 +#endif + + +#ifndef USE_IN_0 +#define USE_IN_0 0 +#endif + +#ifndef USE_IN_1 +#define USE_IN_1 0 +#endif + +#ifndef USE_IN_2 +#define USE_IN_2 0 +#endif + + +#ifndef USE_OUT_0 +#define USE_OUT_0 0 +#endif + +#ifndef USE_OUT_1 +#define USE_OUT_1 0 +#endif + +#ifndef USE_OUT_2 +#define USE_OUT_2 0 +#endif + + + +#ifndef USE_TK_0 +#define USE_TK_0 0 +#endif + +#ifndef USE_TK_1 +#define USE_TK_1 0 +#endif + + +// +#ifndef USE_TK_2 +#define USE_TK_2 0 +#endif + +#ifndef USE_TK_3 +#define USE_TK_3 0 +#endif + + +#ifndef USE_TK_4 +#define USE_TK_4 0 +#endif + +#ifndef USE_TK_5 +#define USE_TK_5 0 +#endif + +#ifndef USE_TK_6 +#define USE_TK_6 0 +#endif + +#ifndef USE_TK_7 +#define USE_TK_7 0 +#endif + + +#ifndef USE_HWP_0 +#define USE_HWP_0 0 +#endif + +#ifndef USE_HWP_1 +#define USE_HWP_1 0 +#endif + +#ifndef USE_HWP_2 +#define USE_HWP_2 0 +#endif + + +#ifndef USE_ROT_1 +#define USE_ROT_1 0 +#endif + + + +//////////////////////////////////////////////// +// +//////////////////////////////////////////////// +#if (USE_HWP_2==1) +#define MAX_COUNT_PLATES_HWP 3 +#else +#if (USE_HWP_1==1) +#define MAX_COUNT_PLATES_HWP 2 +#else +#define MAX_COUNT_PLATES_HWP 1 +#endif +#endif +//////////////////////////////////////////////// + +#if (USE_TK_7==1) +#define MAX_COUNT_PLATES_CDS_TK 8 +#else +#if (USE_TK_6==1) +#define MAX_COUNT_PLATES_CDS_TK 7 +#else +#if (USE_TK_5==1) +#define MAX_COUNT_PLATES_CDS_TK 6 +#else +#if (USE_TK_4==1) +#define MAX_COUNT_PLATES_CDS_TK 5 +#else +#if (USE_TK_3==1) +#define MAX_COUNT_PLATES_CDS_TK 4 +#else +#if (USE_TK_2==1) +#define MAX_COUNT_PLATES_CDS_TK 3 +#else +#if (USE_TK_1==1) +#define MAX_COUNT_PLATES_CDS_TK 2 +#else +#if (USE_TK_0==1) +#define MAX_COUNT_PLATES_CDS_TK 1 +#else +#define MAX_COUNT_PLATES_CDS_TK 1 + +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif +//////////////////////////////////////////////// + +#if (USE_ADC_2==1) +#define MAX_COUNT_PLATES_ADC 3 +#else +#if (USE_ADC_1==1) +#define MAX_COUNT_PLATES_ADC 2 +#else +#if (USE_ADC_0==1) +#define MAX_COUNT_PLATES_ADC 1 +#else +#define MAX_COUNT_PLATES_ADC 1 +#endif +#endif +#endif + + +//////////////////////////////////////////////// +#if (USE_OUT_2==1) +#define MAX_COUNT_PLATES_OUT 3 +#else +#if (USE_OUT_1==1) +#define MAX_COUNT_PLATES_OUT 2 +#else +#if (USE_OUT_0==1) +#define MAX_COUNT_PLATES_OUT 1 +#else +#define MAX_COUNT_PLATES_OUT 1 +#endif +#endif +#endif + + +//////////////////////////////////////////////// +//////////////////////////////////////////////// +#if (USE_IN_2==1) +#define MAX_COUNT_PLATES_IN 3 +#else +#if (USE_IN_1==1) +#define MAX_COUNT_PLATES_IN 2 +#else +#if (USE_IN_0==1) +#define MAX_COUNT_PLATES_IN 1 +#else +#define MAX_COUNT_PLATES_IN 1 +#endif +#endif +#endif + + +//////////////////////////////////////////////// + + +#if (USE_ROT_1==1) +#define MAX_COUNT_PLATES_CDS_RS 1 +#else +#define MAX_COUNT_PLATES_CDS_RS 0 +#endif + +//////////////////////////////////////////////// + + +#include + +#endif // end PROJECT_SETUP_H + diff --git a/Inu/Src2/551/main/protect_levels.h b/Inu/Src2/551/main/protect_levels.h new file mode 100644 index 0000000..b9bf78f --- /dev/null +++ b/Inu/Src2/551/main/protect_levels.h @@ -0,0 +1,119 @@ +/* + * params_protect.h + * + * Created on: 17 . 2020 . + * Author: star + */ + +#ifndef SRC_MAIN_PROTECT_LEVELS_H_ +#define SRC_MAIN_PROTECT_LEVELS_H_ + +#include + +typedef struct { + + int alarm_temper_u_01; + int alarm_temper_u_02; + int alarm_temper_u_03; + int alarm_temper_u_04; + int alarm_temper_u_05; + int alarm_temper_u_06; + int alarm_temper_u_07; + + int abnormal_temper_u_01; + int abnormal_temper_u_02; + int abnormal_temper_u_03; + int abnormal_temper_u_04; + int abnormal_temper_u_05; + int abnormal_temper_u_06; + int abnormal_temper_u_07; + + int alarm_temper_water_int; + int abnormal_temper_water_int; + + int alarm_temper_water_ext; + int abnormal_temper_water_ext; + + int alarm_p_water_max_int; + int abnormal_p_water_max_int; + + int alarm_p_water_min_int; + int abnormal_p_water_min_int; + + int alarm_temper_air_int_01; + int alarm_temper_air_int_02; + int alarm_temper_air_int_03; + int alarm_temper_air_int_04; + + int abnormal_temper_air_int_01; + int abnormal_temper_air_int_02; + int abnormal_temper_air_int_03; + int abnormal_temper_air_int_04; + + int alarm_temper_acdrive_winding_U1; + int alarm_temper_acdrive_winding_V1; + int alarm_temper_acdrive_winding_W1; + int alarm_temper_acdrive_winding_U2; + int alarm_temper_acdrive_winding_V2; + int alarm_temper_acdrive_winding_W2; + + int abnormal_temper_acdrive_winding_U1; + int abnormal_temper_acdrive_winding_V1; + int abnormal_temper_acdrive_winding_W1; + int abnormal_temper_acdrive_winding_U2; + int abnormal_temper_acdrive_winding_V2; + int abnormal_temper_acdrive_winding_W2; + + int alarm_temper_acdrive_bear_DNE; + int alarm_temper_acdrive_bear_NE; + int abnormal_temper_acdrive_bear_DNE; + int abnormal_temper_acdrive_bear_NE; + + int alarm_Uin_max_Up; + int alarm_Uin_max_Down; + int alarm_Uin_min_Up; + int alarm_Uin_min_Down; + + int alarm_Udc_max_Up; + int alarm_Udc_max_Down; + int alarm_Udc_min_Up; + int alarm_Udc_min_Down; + int alarm_Izpt_max; + + int alarm_Imax_U01; + int alarm_Imax_U02; + int alarm_Imax_U03; + int alarm_Imax_U04; + int alarm_Imax_U05; + int alarm_Imax_U06; + int alarm_Imax_U07; + + int alarm_Iged_max; + +} PROTECT_LEVELS; + +#define PROTECT_LEVELS_DEFAULTS {ALARM_TEMPER_AF,ALARM_TEMPER_AF,ALARM_TEMPER_AF,\ + ALARM_TEMPER_AF,ALARM_TEMPER_AF,ALARM_TEMPER_AF,ALARM_TEMPER_AF,\ + ABNORMAL_TEMPER_AF,ABNORMAL_TEMPER_AF,ABNORMAL_TEMPER_AF,ABNORMAL_TEMPER_AF,\ + ABNORMAL_TEMPER_AF,ABNORMAL_TEMPER_AF,ABNORMAL_TEMPER_AF,\ + ALARM_TEMPER_WATER_INT,ABNORMAL_TEMPER_WATER_INT,\ + ALARM_TEMPER_WATER_EXT,ABNORMAL_TEMPER_WATER_EXT,\ + ALARM_P_WATER_MAX_INT,ABNORMAL_P_WATER_MAX_INT,\ + ALARM_P_WATER_MIN_INT,ABNORMAL_P_WATER_MIN_INT,\ + ALARM_TEMPER_AIR_INT,ALARM_TEMPER_AIR_INT,ALARM_TEMPER_AIR_INT,ALARM_TEMPER_AIR_INT,\ + ABNORMAL_TEMPER_AIR_INT,ABNORMAL_TEMPER_AIR_INT,ABNORMAL_TEMPER_AIR_INT,ABNORMAL_TEMPER_AIR_INT,\ + ALARM_TEMPER_ACDRIVE_WINDING,ALARM_TEMPER_ACDRIVE_WINDING,ALARM_TEMPER_ACDRIVE_WINDING,\ + ALARM_TEMPER_ACDRIVE_WINDING,ALARM_TEMPER_ACDRIVE_WINDING,ALARM_TEMPER_ACDRIVE_WINDING,\ + ABNORMAL_TEMPER_ACDRIVE_WINDING,ABNORMAL_TEMPER_ACDRIVE_WINDING,ABNORMAL_TEMPER_ACDRIVE_WINDING,\ + ABNORMAL_TEMPER_ACDRIVE_WINDING,ABNORMAL_TEMPER_ACDRIVE_WINDING,ABNORMAL_TEMPER_ACDRIVE_WINDING,\ + ALARM_TEMPER_ACDRIVE_BEAR,ALARM_TEMPER_ACDRIVE_BEAR,\ + ABNORMAL_TEMPER_ACDRIVE_BEAR,ABNORMAL_TEMPER_ACDRIVE_BEAR,\ + LEVEL_ADC_U_IN_MAX,LEVEL_ADC_U_IN_MAX, LEVEL_ADC_U_IN_MIN,LEVEL_ADC_U_IN_MIN,\ + LEVEL_ADC_U_ZPT_MAX,LEVEL_ADC_U_ZPT_MAX,LEVEL_ADC_U_ZPT_MIN,LEVEL_ADC_U_ZPT_MIN,\ + LEVEL_ADC_I_ZPT,\ + LEVEL_ADC_I_BREAK, LEVEL_ADC_I_AF,LEVEL_ADC_I_AF,LEVEL_ADC_I_AF,LEVEL_ADC_I_AF,LEVEL_ADC_I_AF,LEVEL_ADC_I_AF,\ + LEVEL_ADC_I_OUT_MAX} + +extern PROTECT_LEVELS protect_levels; + +#endif /* SRC_MAIN_PROTECT_LEVELS_H_ */ diff --git a/Inu/Src2/551/main/pump_control.c b/Inu/Src2/551/main/pump_control.c new file mode 100644 index 0000000..212473c --- /dev/null +++ b/Inu/Src2/551/main/pump_control.c @@ -0,0 +1,255 @@ +/* + * pump_management.c + * + * Created on: 28 . 2020 . + * Author: stud + */ + +#include +#include + +#include "control_station.h" +#include "digital_filters.h" +#include "sbor_shema.h" + +#pragma DATA_SECTION(pumps, ".slow_vars") +PUMP_CONTROL pumps = PUMP_CONTROL_DEFAULTS; + +void turn_on_nasos_1_2(unsigned int without_time_wait); +int select_pump(void); + +void pump_control(void) +{ + unsigned int pump_off_without_time_wait; + + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_MODE_PUMP] == 0) + { +// edrk.SelectPump1_2 = 0; + pumps.SelectedPump1_2 = 0; + edrk.ManualStartPump = 0; + // edrk.AutoStartPump = 1; + pump_off_without_time_wait = 0; + } + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_MODE_PUMP] == 1) + { +// edrk.SelectPump1_2 = 1; + pumps.SelectedPump1_2 = 1; + edrk.ManualStartPump = 0; + // edrk.AutoStartPump = 1; + pump_off_without_time_wait = 0; + } + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_MODE_PUMP] == 2) + { +// edrk.SelectPump1_2 = 2; + pumps.SelectedPump1_2 = 2; + edrk.ManualStartPump = 0; + // edrk.AutoStartPump = 1; + pump_off_without_time_wait = 0; + } + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_MODE_PUMP] == 3) + { +// edrk.SelectPump1_2 = 1; + pumps.SelectedPump1_2 = 1; + edrk.ManualStartPump = 1; + edrk.AutoStartPump = 0; + pump_off_without_time_wait = 1; + } + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_MODE_PUMP] == 4) + { +// edrk.SelectPump1_2 = 2; + pumps.SelectedPump1_2 = 2; + edrk.ManualStartPump = 1; + edrk.AutoStartPump = 0; + pump_off_without_time_wait = 1; + } + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_MODE_PUMP] == 5) + { +// edrk.SelectPump1_2 = 0; + pumps.SelectedPump1_2 = 0; + edrk.ManualStartPump = 0; + edrk.AutoStartPump = 0; + pump_off_without_time_wait = 1; + } + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_MODE_PUMP] == 6) + { +// edrk.SelectPump1_2 = 1; + pumps.SelectedPump1_2 = 0; + edrk.ManualStartPump = 1; + edrk.AutoStartPump = 0; + pump_off_without_time_wait = 1; + } + + edrk.SumStartPump = edrk.AutoStartPump || edrk.ManualStartPump; + + turn_on_nasos_1_2(pump_off_without_time_wait); + + set_status_pump_fan(); + +} + + +#define TIME_WAIT_PUMP_ON 30 //3 sec +#define TIME_WAIT_ALL_PUMP_OFF 600 //30 sec + +/////////////////////////////////////////////// +void turn_on_nasos_1_2(unsigned int without_time_wait) +{ +static unsigned int time_wait_on_pump1=0; +static unsigned int time_wait_on_pump2=0; + +static unsigned int time_wait_off_all_pump1=0; +static unsigned int time_wait_off_all_pump2=0; + +static unsigned int prev_without_time_wait = 0; + + + +int cmd_p1 = 0, + cmd_p2 = 0, + add_cmd_without_time_wait1 = 0, + add_cmd_without_time_wait2 = 0; + +int fast_stop_pump=0; + + +// if () +//(prev_start_nasos!=edrk.StartPump) && + + + cmd_p1 = 0; + cmd_p2 = 0; + + fast_stop_pump = ( edrk.errors.e5.bits.ERROR_ISOLATE || edrk.errors.e5.bits.FAN || + edrk.errors.e5.bits.PRE_READY_PUMP || edrk.errors.e5.bits.UTE4KA_WATER || edrk.errors.e2.bits.P_WATER_INT_MIN || + edrk.errors.e2.bits.P_WATER_INT_MAX || edrk.errors.e5.bits.PUMP_1 || edrk.errors.e5.bits.PUMP_2); + + if ( edrk.SumStartPump==1 && edrk.errors.e5.bits.PRE_READY_PUMP == 0 && fast_stop_pump==0) + { + if (pumps.SelectedPump1_2 == 0 /*&& edrk.ManualStartPump == 0*/) + { + // + switch (select_pump()) { + case 1: + cmd_p1 = 1; + cmd_p2 = 0; + break; + case 2: + cmd_p1 = 0; + cmd_p2 = 1; + break; + default: + cmd_p1 = 0; + cmd_p2 = 0; + } + pumps.lock_pump = 1; + } else + if (pumps.SelectedPump1_2==1 && edrk.errors.e5.bits.PUMP_1==0) + cmd_p1 = 1; + else if (pumps.SelectedPump1_2==2 && edrk.errors.e5.bits.PUMP_2==0) + cmd_p2 = 1; + } + else + { + cmd_p1 = 0; + cmd_p2 = 0; + } + + + if (cmd_p1) + { + edrk.SelectPump1_2 = 1; + if (pause_detect_error(&time_wait_on_pump1,TIME_WAIT_PUMP_ON,1)) + { + edrk.to_ing.bits.NASOS_1_ON = 1; + time_wait_off_all_pump1 = 0; + } + } + else + { + time_wait_on_pump1 = 0; + + if (without_time_wait==0 && prev_without_time_wait != without_time_wait) + add_cmd_without_time_wait1 = 1; + + if (cmd_p1!=cmd_p2 || fast_stop_pump || without_time_wait || add_cmd_without_time_wait1) { + edrk.to_ing.bits.NASOS_1_ON = 0; + } + else + { + if (pause_detect_error(&time_wait_off_all_pump1,TIME_WAIT_ALL_PUMP_OFF,1)) { + edrk.to_ing.bits.NASOS_1_ON = 0; + } + } + + } + + + if (cmd_p2) + { + edrk.SelectPump1_2 = 2; + if (pause_detect_error(&time_wait_on_pump2,TIME_WAIT_PUMP_ON,1)) + { + edrk.to_ing.bits.NASOS_2_ON = 1; + time_wait_off_all_pump2 = 0; + } + } + else + { + time_wait_on_pump2 = 0; + + if (without_time_wait==0 && prev_without_time_wait != without_time_wait) + add_cmd_without_time_wait2 = 1; + + if (cmd_p1!=cmd_p2 || fast_stop_pump || without_time_wait || add_cmd_without_time_wait2) { + edrk.to_ing.bits.NASOS_2_ON = 0; + } + else + { + if (pause_detect_error(&time_wait_off_all_pump2,TIME_WAIT_ALL_PUMP_OFF,1)) { + edrk.to_ing.bits.NASOS_2_ON = 0; + } + } + } + + if (edrk.to_ing.bits.NASOS_1_ON == 0 && edrk.to_ing.bits.NASOS_2_ON == 0) { + pumps.lock_pump = 0; + } + + prev_without_time_wait = without_time_wait; + +} + +int select_pump() { + int p_n = 0; + if (pumps.lock_pump == 0) { + + p_n = calc_auto_moto_pump(); + if (p_n == 0) + p_n = 1; +// if (pumps.pump1_engine_minutes > pumps.pump2_engine_minutes) { +// p_n = 2; +// } else { +// p_n = 1; +// } + + } else { + p_n = edrk.SelectPump1_2; + } + if ((edrk.errors.e5.bits.PUMP_1 == 1) && (edrk.errors.e5.bits.PUMP_2 == 1)) { + p_n = 0; + } + if (p_n == 1 && edrk.warnings.e5.bits.PUMP_1 == 1) { + p_n = 2; + } + if (p_n == 2 && edrk.warnings.e5.bits.PUMP_2 == 1) { + p_n = 1; + } + return p_n; +} diff --git a/Inu/Src2/551/main/pump_control.h b/Inu/Src2/551/main/pump_control.h new file mode 100644 index 0000000..92a5931 --- /dev/null +++ b/Inu/Src2/551/main/pump_control.h @@ -0,0 +1,27 @@ +/* + * pump_management.h + * + * Created on: 28 . 2020 . + * Author: stud + */ + +#ifndef SRC_MAIN_PUMP_CONTROL_H_ +#define SRC_MAIN_PUMP_CONTROL_H_ + +typedef struct { + int pump1_engine_minutes; + int pump2_engine_minutes; + int time_switch_minuts; + int SelectedPump1_2; + int lock_pump; +} PUMP_CONTROL; + +#define PUMP_CONTROL_DEFAULTS {0,0,5,0,0} + +extern PUMP_CONTROL pumps; + +void pump_control(void); + + + +#endif /* SRC_MAIN_PUMP_CONTROL_H_ */ diff --git a/Inu/Src2/551/main/pwm_logs.c b/Inu/Src2/551/main/pwm_logs.c new file mode 100644 index 0000000..42ca3e7 --- /dev/null +++ b/Inu/Src2/551/main/pwm_logs.c @@ -0,0 +1,476 @@ +/* + * pwm_logs.c + * + * Created on: 19 . 2024 . + * Author: user + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "global_time.h" +#include "IQmathLib.h" +#include "oscil_can.h" +#include "uf_alg_ing.h" +#include "MemoryFunctions.h" +#include "RS_Functions.h" +#include "v_rotor_22220.h" +#include "log_to_memory.h" +#include "log_params.h" +#include "logs_hmi.h" +#include "vector_control.h" + + +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +#pragma CODE_SECTION(prepare_data_to_logs,".fast_run"); +unsigned int prepare_data_to_logs(void) +{ + logsdata.logs[0] = (int16) global_time.total_seconds10full;// = 0;//(int16)(_IQtoIQ15(Izad)); + logsdata.logs[1] = (int16) _IQtoIQ15(analog.iqIu_1); + logsdata.logs[2] = (int16) _IQtoIQ15(analog.iqIv_1); + logsdata.logs[3] = (int16) _IQtoIQ15(analog.iqIw_1); + + logsdata.logs[4] = (int16) _IQtoIQ15(analog.iqIu_2); + logsdata.logs[5] = (int16) _IQtoIQ15(analog.iqIv_2); + logsdata.logs[6] = (int16) _IQtoIQ15(analog.iqIw_2); + + logsdata.logs[7] = (int16) _IQtoIQ15(analog.iqUin_A1B1);// (int16) _IQtoIQ15(analog.iqUin_m1); + logsdata.logs[8] = (int16) _IQtoIQ15(analog.iqUin_A2B2);// (int16) _IQtoIQ15(analog.iqUin_m2); + + + logsdata.logs[9] = (int16) _IQtoIQ15(analog.iqU_1); + logsdata.logs[10] = (int16) _IQtoIQ15(analog.iqU_2);//11 + + logsdata.logs[11] = (int16) _IQtoIQ15(analog.iqIin_1); + logsdata.logs[12] = (int16) _IQtoIQ15(analog.iqIin_2); + + logsdata.logs[13] = (int16) _IQtoIQ15(analog.iqIm_1); + logsdata.logs[14] = (int16) _IQtoIQ15(analog.iqIm_2); + + logsdata.logs[15] = (int16) _IQtoIQ15(analog.iqIbreak_1);//(int16) _IQtoIQ15(filter.iqU_1_long); + logsdata.logs[16] = (int16) _IQtoIQ15(analog.iqIbreak_2);//(int16) _IQtoIQ15(filter.iqU_2_long); + + + logsdata.logs[17] = (int16)svgen_pwm24_1.Ta_0; + logsdata.logs[18] = (int16)svgen_pwm24_1.Ta_1; + logsdata.logs[19] = (int16)break_result_1; + logsdata.logs[20] = (int16)break_result_2; +// logpar.log21 = (int16)svgen_pwm24_1.Tb_1; +// logpar.log22 = (int16)svgen_pwm24_1.Tc_0; +// logpar.log23 = (int16)svgen_pwm24_1.Tc_1; //23 + + logsdata.logs[21] = (int16)(_IQtoIQ14(edrk.iq_power_kw_full_znak));// edrk.from_uom.iq_level_value_kwt + //(int16) _IQtoIQ15(rotor_22220.iqFdirty); + // + + logsdata.logs[22] = (int16) _IQtoIQ15(WRotor.iqWRotorSumFilter2); + logsdata.logs[23] = (int16) _IQtoIQ15(WRotor.iqWRotorSumFilter);//WRotor.iqWRotorSumFilter WRotor.iqWRotorSum + logsdata.logs[24] = (int16) _IQtoIQ15(simple_scalar1.iq_decr_mzz_power);//WRotor.iqWRotorSumFilter2 WRotor.iqWRotorSumFilter3 + + logsdata.logs[25] = (int16) edrk.from_uom.level_value;// (int16) _IQtoIQ15(WRotor.iqWRotorSumFilter); +// logpar.log25 = (int16) _IQtoIQ15(WRotor.iqWRotorSumFilter); +// logsdata.logs[25] = (int16) _IQtoIQ15(WRotor.iqWRotorSum); + + logsdata.logs[26] = (int16) edrk.power_limit.all;//_IQtoIQ15(pll1.vars.pll_Uq); + logsdata.logs[27] = (int16)(_IQtoIQ14(edrk.zadanie.iq_limit_power_zad));//(int16) _IQtoIQ15(pll1.vars.pll_Ud);//28 + + logsdata.logs[28] = (int16) _IQtoIQ12(edrk.master_theta);//29 + logsdata.logs[29] = (int16) _IQtoIQ15(edrk.master_Uzad);//30 + logsdata.logs[30] = (int16) _IQtoIQ14(edrk.f_stator); + logsdata.logs[31] = (int16) _IQtoIQ12(edrk.k_stator1); + + logsdata.logs[32] = optical_read_data.data.cmd.all; + logsdata.logs[33] = optical_read_data.data.pzad_or_wzad; + logsdata.logs[34] = optical_read_data.data.angle_pwm; + logsdata.logs[35] = optical_read_data.data.iq_zad_i_zad; + + logsdata.logs[36] = optical_write_data.data.cmd.all; + logsdata.logs[37] = optical_write_data.data.angle_pwm; + logsdata.logs[38] = optical_write_data.data.pzad_or_wzad; + logsdata.logs[39] = optical_write_data.data.iq_zad_i_zad; + + ///////////// + logsdata.logs[40] = (int16)(_IQtoIQ15(simple_scalar1.Izad)); + logsdata.logs[41] = (int16)(_IQtoIQ15(simple_scalar1.mzz_zad_in2));//(int16)(_IQtoIQ15(Uze_t1)); + logsdata.logs[42] = (int16)(_IQtoIQ15(simple_scalar1.pidF.OutMax)); + logsdata.logs[43] = (int16)(_IQtoIQ15(simple_scalar1.mzz_zad_int)); + logsdata.logs[44] = (int16)(_IQtoIQ15(simple_scalar1.Izad_from_master)); + + logsdata.logs[45] = (int16)(_IQtoIQ14(simple_scalar1.pidF.Fdb)); + logsdata.logs[46] = (int16)(_IQtoIQ14(simple_scalar1.pidF.Ref)); + logsdata.logs[47] = (int16)(_IQtoIQ14(simple_scalar1.pidF.Ui)); + logsdata.logs[48] = (int16)(_IQtoIQ14(simple_scalar1.pidF.Up)); + logsdata.logs[49] = (int16)(_IQtoIQ14(simple_scalar1.pidF.SatErr)); + logsdata.logs[50] = (int16)(_IQtoIQ14(simple_scalar1.pidF.Out)); + + logsdata.logs[51] = (int16)(_IQtoIQ14(simple_scalar1.pidPower.Fdb)); + logsdata.logs[52] = (int16)(_IQtoIQ14(simple_scalar1.pidPower.Ref)); + logsdata.logs[53] = (int16)(_IQtoIQ14(simple_scalar1.pidPower.Ui)); + logsdata.logs[54] = (int16)(_IQtoIQ14(simple_scalar1.pidPower.Up)); + logsdata.logs[55] = (int16)(_IQtoIQ14(simple_scalar1.pidPower.SatErr)); + logsdata.logs[56] = (int16)(_IQtoIQ14(simple_scalar1.pidPower.Out)); + + logsdata.logs[57] = (int16)(_IQtoIQ15(simple_scalar1.pidIm1.Fdb)); + logsdata.logs[58] = (int16)(_IQtoIQ15(simple_scalar1.pidIm1.Ref)); + logsdata.logs[59] = (int16)(_IQtoIQ15(simple_scalar1.pidIm1.Ui)); + logsdata.logs[60] = (int16)(_IQtoIQ15(simple_scalar1.pidIm1.Up)); + logsdata.logs[61] = (int16)(_IQtoIQ15(simple_scalar1.pidIm1.SatErr)); + logsdata.logs[62] = (int16)(_IQtoIQ15(simple_scalar1.pidIm1.Out)); + logsdata.logs[63] = (int16)(_IQtoIQ12(simple_scalar1.Uze_t1)); + + logsdata.logs[64] = (int16)(_IQtoIQ15(simple_scalar1.bpsi_curent)); + + logsdata.logs[65] = (int16)(_IQtoIQ14(simple_scalar1.iqKoefOgran)); + + logsdata.logs[66] = (int16)(_IQtoIQ14(simple_scalar1.Fz)); + logsdata.logs[67] = (int16) (_IQtoIQ15(simple_scalar1.iq_decr_mzz_power_filter));//rotor_22220.direct_rotor + + logsdata.logs[68] = (int16)(_IQtoIQ14(simple_scalar1.pidF.OutMin));//(int16)edrk.Status_Sbor; + logsdata.logs[69] = (int16)(_IQtoIQ14(simple_scalar1.pidPower.OutMax));//(int16)edrk.Stage_Sbor; + logsdata.logs[70] = (int16)(_IQtoIQ14(filter.iqUin_m1));//(int16)edrk.Sbor_Mode; + + logsdata.logs[71] = (int16)edrk.from_shema.all; + logsdata.logs[72] = (int16)(_IQtoIQ15(simple_scalar1.iqKoefOgranIzad));//(int16)edrk.from_shema_filter.all; +// + logsdata.logs[73] = (int16)(_IQtoIQ14(filter.iqUin_m2));//simple_scalar1.direction; + logsdata.logs[74] = (int16)(_IQtoIQ14(edrk.iq_power_kw_full_filter_znak));// + logsdata.logs[75] = (int16)(_IQtoIQ15(edrk.iq_freq_50hz));//edrk.iq_freq_50hz + logsdata.logs[76] = (int16)(_IQtoIQ15(simple_scalar1.mzz_zad_in1)); + + + + // can regs +// logsdata.logs[77] = (int16)(((unsigned long)edrk.canes_reg >> 16) & 0x1ff); +// logsdata.logs[78] = (int16)((unsigned long)edrk.canes_reg & 0x3f); +// +// logsdata.logs[79] = (int16)(edrk.cantec_reg & 0xff); +// logsdata.logs[80] = (int16)(edrk.canrec_reg & 0xff); + + logsdata.logs[77] = (int16)(_IQtoIQ14(uf_alg.Ud)); + logsdata.logs[78] = (int16)(_IQtoIQ14(uf_alg.Uq)); + logsdata.logs[79] = (int16)(_IQtoIQ14(edrk.all_limit_koeffs.uom_limit));//edrk.MasterSlave; + + logsdata.logs[80] = (int16)(_IQtoIQ14(edrk.Kplus)); + +// logsdata.logs[65] = (int16)(_IQtoIQ14(edrk.all_limit_koeffs.temper_limit)); + logsdata.logs[81] = (int16)(_IQtoIQ14(edrk.all_limit_koeffs.uin_freq_limit)); + + logsdata.logs[82] = (int16)(_IQtoIQ14(uf_alg.svgen_dq_Ta)); + logsdata.logs[83] = (int16)(_IQtoIQ14(uf_alg.svgen_dq_Tb)); + logsdata.logs[84] = (int16)(_IQtoIQ14(uf_alg.svgen_dq_Tc)); + + // uf_alg.tetta_bs + + // logsdata.logs[64] = (int16)(_IQtoIQ15()); + +// logsdata.logs[64] = (int16)(_IQtoIQ15()); + + logsdata.logs[85] = edrk.from_uom.digital_line.all; +// logsdata.logs[75] = edrk.errors.e2.all; +// logsdata.logs[76] = edrk.errors.e3.all; +// logsdata.logs[77] = edrk.errors.e4.all; +// logsdata.logs[78] = edrk.errors.e5.all; +// logsdata.logs[79] = edrk.errors.e6.all; +// logsdata.logs[80] = edrk.errors.e7.all; +// + + + + +// logsdata.logs[67] = (int16) _IQtoIQ15(WRotor.iqWRotorCalcBeforeRegul1); +// logsdata.logs[68] = (int16) _IQtoIQ15(WRotor.iqWRotorCalcBeforeRegul2); +// logsdata.logs[69] = (int16) _IQtoIQ15(WRotor.iqWRotorCalc1); + +// logsdata.logs[24] = (int16) _IQtoIQ15(WRotor.iqWRotorCalc2); + +// logsdata.logs[70] = (int16) _IQtoIQ15(WRotor.iqWRotorSumRamp); + +// logsdata.logs[72] = (int16) (WRotorPBus.RotorDirectionSlow); + // logsdata.logs[73] = (int16) (WRotorPBus.RotorDirectionSlow2); + // logsdata.logs[74] = (int16) (WRotorPBus.RotorDirectionInstant); //(int16) (WRotorPBus.); + +// logsdata.logs[75] = (int16) (WRotor.iqTimeSensor1); +// logsdata.logs[76] = (int16) (WRotor.iqTimeSensor2); +// +// logsdata.logs[77] = (int16) _IQtoIQ15(WRotor.iqWRotorCalc1Ramp); +// logsdata.logs[78] = (int16) _IQtoIQ15(WRotor.iqWRotorCalc2Ramp); +// +// logsdata.logs[79] = (int16) _IQtoIQ15(WRotor.iqPrevWRotorCalc1); +// logsdata.logs[80] = (int16) _IQtoIQ15(WRotor.iqPrevWRotorCalc2); + +// logsdata.logs[81] = (int16) modbus_table_can_in[124].all;// (); +// logsdata.logs[82] = (int16) modbus_table_can_in[134].all;// +// logsdata.logs[83] = (int16) modbus_table_can_in[125].all;// () +// +// logsdata.logs[84] = (int16) project.cds_in[0].read.pbus.data_in.all; +// logsdata.logs[85] = (int16) project.cds_in[1].read.pbus.data_in.all; + + logsdata.logs[86] = (int16) _IQtoIQ15(vect_control.iqId1); + logsdata.logs[87] = (int16) _IQtoIQ15(vect_control.iqIq1); + + logsdata.logs[88] = (int16) _IQtoIQ15(vect_control.iqId2); + logsdata.logs[89] = (int16) _IQtoIQ15(vect_control.iqIq2); + logsdata.logs[90] = 0; + + return 90; +} + + +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// + +#define PAUSE_SLOW_LOG 20 + +void save_slow_logs(int run, int t_slow) +{ + static int c_step=0; +// static int c_all = (FREQ_PWM>>2); // 0,125 + static int c_all = (FREQ_PWM>>1); // 0,250 + + static int prev_run=0; + static unsigned int c_pause=0; + + if (rs_a.RS_PrevCmd==CMD_RS232_UPLOAD) + return; + + if (run==0 && c_pause>=PAUSE_SLOW_LOG) + return; + + c_all = (FREQ_PWM>>(1+t_slow)); + + if (c_all<2) + c_all = 2; + + + if (c_step>=c_all) + { + test_mem_limit(SLOW_LOG, 1); + + // prepare_data_to_logs(); + + getSlowLogs(1); + c_step = 0; + + if (run==1) + c_pause = 0; + else + { + if (c_pause= 1)//1 + { + count_step_run++; + // i_led1_on_off(1); +// write_to_mem(FAST_LOG, (int16)count_step_run); + + getFastLogs(!f.Ciclelog); +// for (i_log=0;i_log<72;i_log++) +// write_to_mem(FAST_LOG, (int16) logsdata.logs[i_log]); + +// write_to_mem(FAST_LOG, (int16) logpar.log85); + + + +// if (logpar.start_write_fast_log) { +// get_log_params_count(); +// logpar.start_write_fast_log = 0; +// } + count_step = 0; + } + } + else { + if (f.Stop && log_params.log_saved_to_const_mem == 0) { + log_params.copy_log_to_const_memory = 1; + log_params.log_saved_to_const_mem = 1; + f.flag_send_alarm_log_to_MPU = 1; + } + } + + +#if(_ENABLE_PWM_LINES_FOR_TESTS_PWM) + PWM_LINES_TK_23_OFF; +#endif + + if (filter.iqU_1_long>edrk.iqMIN_U_ZPT || filter.iqU_2_long>edrk.iqMIN_U_ZPT) + local_enable_slow_log = 1; + else + local_enable_slow_log = 0; + + if (edrk.stop_logs_rs232 == 0 && edrk.stop_slow_log ==0 && log_to_HMI.send_log == 0) + save_slow_logs(edrk.Go || (local_enable_slow_log && edrk.Status_Ready.bits.ready_final==0), edrk.t_slow_log); +} +////////////////////////////////////////////////////////////////// + + + + diff --git a/Inu/Src2/551/main/pwm_logs.h b/Inu/Src2/551/main/pwm_logs.h new file mode 100644 index 0000000..8eb5f07 --- /dev/null +++ b/Inu/Src2/551/main/pwm_logs.h @@ -0,0 +1,16 @@ +/* + * pwm_logs.h + * + * Created on: 19 . 2024 . + * Author: user + */ + +#ifndef SRC_MAIN_PWM_LOGS_H_ +#define SRC_MAIN_PWM_LOGS_H_ + +unsigned int prepare_data_to_logs(void); +void save_slow_logs(int run, int t_slow); +void run_write_logs(void); + + +#endif /* SRC_MAIN_PWM_LOGS_H_ */ diff --git a/Inu/Src2/551/main/pwm_test_lines.c b/Inu/Src2/551/main/pwm_test_lines.c new file mode 100644 index 0000000..ef24f64 --- /dev/null +++ b/Inu/Src2/551/main/pwm_test_lines.c @@ -0,0 +1,36 @@ + +#include <281xEvTimersInit.h> +#include +#include + +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "x_wdog.h" + +#include + +unsigned int cmd_pwm_test_lines = 0xffff; + +void pwm_test_lines_start(void) +{ + cmd_pwm_test_lines = 0xffff; + +// i_WriteMemory(ADR_TK_MASK_1, 0); + i_WriteMemory(ADR_PWM_DIRECT2,0xffff); +// i_WriteMemory(ADR_PWM_DRIVE_MODE, 3); // on direct tk lines +// i_WriteMemory(ADR_PWM_DIRECT2,0xffff); + + i_WriteMemory(ADR_TK_MASK_1, 0x0); //Turn on additional 16 tk lines +} + +void pwm_test_lines_stop(void) +{ + cmd_pwm_test_lines = 0xffff; + + i_WriteMemory(ADR_TK_MASK_1, 0xffff); //Turn off additional 16 tk lines + i_WriteMemory(ADR_PWM_DIRECT2,0xffff); + +// i_WriteMemory(ADR_PWM_DRIVE_MODE, 0); // off direct tk lines +} + diff --git a/Inu/Src2/551/main/pwm_test_lines.h b/Inu/Src2/551/main/pwm_test_lines.h new file mode 100644 index 0000000..d411550 --- /dev/null +++ b/Inu/Src2/551/main/pwm_test_lines.h @@ -0,0 +1,63 @@ + + + + + + +extern unsigned int cmd_pwm_test_lines; + +#define PWM_LINES_TK_16_OFF {cmd_pwm_test_lines &= 0xfffe; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +#define PWM_LINES_TK_16_ON {cmd_pwm_test_lines |= 0x0001; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} + +#define PWM_LINES_TK_17_OFF {cmd_pwm_test_lines &= 0xfffd; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +#define PWM_LINES_TK_17_ON {cmd_pwm_test_lines |= 0x0002; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} + +#define PWM_LINES_TK_18_OFF {cmd_pwm_test_lines &= 0xfffb; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +#define PWM_LINES_TK_18_ON {cmd_pwm_test_lines |= 0x0004; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} + +#define PWM_LINES_TK_19_OFF {cmd_pwm_test_lines &= 0xfff7; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +#define PWM_LINES_TK_19_ON {cmd_pwm_test_lines |= 0x0008; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//// +#define PWM_LINES_TK_20_OFF {cmd_pwm_test_lines &= 0xffef; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +#define PWM_LINES_TK_20_ON {cmd_pwm_test_lines |= 0x0010; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} + +#define PWM_LINES_TK_21_OFF {cmd_pwm_test_lines &= 0xffdf; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +#define PWM_LINES_TK_21_ON {cmd_pwm_test_lines |= 0x0020; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} + +#define PWM_LINES_TK_22_OFF {cmd_pwm_test_lines &= 0xffbf; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +#define PWM_LINES_TK_22_ON {cmd_pwm_test_lines |= 0x0040; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} + +#define PWM_LINES_TK_23_OFF {cmd_pwm_test_lines &= 0xff7f; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +#define PWM_LINES_TK_23_ON {cmd_pwm_test_lines |= 0x0080; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +////// +//#define PWM_LINES_TK_24_ON {cmd_pwm_test_lines &= 0xfeff; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//#define PWM_LINES_TK_24_OFF {cmd_pwm_test_lines |= 0x0100; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +// +//#define PWM_LINES_TK_25_ON {cmd_pwm_test_lines &= 0xfdff; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//#define PWM_LINES_TK_25_OFF {cmd_pwm_test_lines |= 0x0200; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +// +//#define PWM_LINES_TK_26_ON {cmd_pwm_test_lines &= 0xfbff; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//#define PWM_LINES_TK_26_OFF {cmd_pwm_test_lines |= 0x0400; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +// +//#define PWM_LINES_TK_27_ON {cmd_pwm_test_lines &= 0xf7ff; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//#define PWM_LINES_TK_27_OFF {cmd_pwm_test_lines |= 0x0800; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +////// +//#define PWM_LINES_TK_28_ON {cmd_pwm_test_lines &= 0xefff; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//#define PWM_LINES_TK_28_OFF {cmd_pwm_test_lines |= 0x1000; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +// +//#define PWM_LINES_TK_29_ON {cmd_pwm_test_lines &= 0xdfff; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//#define PWM_LINES_TK_29_OFF {cmd_pwm_test_lines |= 0x2000; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +// +//#define PWM_LINES_TK_30_ON {cmd_pwm_test_lines &= 0xbfff; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//#define PWM_LINES_TK_30_OFF {cmd_pwm_test_lines |= 0x4000; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +// +//#define PWM_LINES_TK_31_ON {cmd_pwm_test_lines &= 0x7fff; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//#define PWM_LINES_TK_31_OFF {cmd_pwm_test_lines |= 0x8000; i_WriteMemory(ADR_PWM_DIRECT2, cmd_pwm_test_lines);} +//// + + + + +///////////////////////////////////////// +void pwm_test_lines_start(void); +void pwm_test_lines_stop(void); diff --git a/Inu/Src2/551/main/ramp_zadanie_tools.c b/Inu/Src2/551/main/ramp_zadanie_tools.c new file mode 100644 index 0000000..61a6689 --- /dev/null +++ b/Inu/Src2/551/main/ramp_zadanie_tools.c @@ -0,0 +1,417 @@ +/* + * ramp_zadanie_tools.c + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + + + +#include + +#include +#include +#include +#include +#include +#include +#include "IQmathLib.h" +#include "mathlib.h" +#include "ramp_zadanie_tools.h" +#include "v_rotor.h" + + + +void change_ramp_zadanie(void) +{ + _iq rampafloat, rampafloat_plus, rampafloat_minus; + + if (edrk.cmd_very_slow_start) + { + rampafloat_plus = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T_SLOW_NARAST_ZADANIE_OBOROTS_ROTOR_PLUS)); + rampafloat_minus = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T_SLOW_NARAST_ZADANIE_OBOROTS_ROTOR_MINUS)); + edrk.zadanie.rmp_oborots_zad_hz.PosRampPlus1 = rampafloat_plus; + edrk.zadanie.rmp_oborots_zad_hz.PosRampMinus1 = -rampafloat_minus; + + edrk.zadanie.rmp_oborots_zad_hz.NegRampPlus1 = rampafloat_minus; + edrk.zadanie.rmp_oborots_zad_hz.NegRampMinus1 = -rampafloat_plus; + +// rampafloat_plus = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T_SLOW_NARAST_ZADANIE_OBOROTS_ROTOR_PLUS)); +// rampafloat_minus = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T_SLOW_NARAST_ZADANIE_OBOROTS_ROTOR_MINUS)); + edrk.zadanie.rmp_oborots_zad_hz.PosRampPlus2 = rampafloat_plus; + edrk.zadanie.rmp_oborots_zad_hz.PosRampMinus2 = -rampafloat_minus; + + edrk.zadanie.rmp_oborots_zad_hz.NegRampPlus2 = rampafloat_minus; + edrk.zadanie.rmp_oborots_zad_hz.NegRampMinus2 = -rampafloat_plus; + } + else + { + rampafloat_plus = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T1_NARAST_ZADANIE_OBOROTS_ROTOR_PLUS)); + rampafloat_minus = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T1_NARAST_ZADANIE_OBOROTS_ROTOR_MINUS)); + edrk.zadanie.rmp_oborots_zad_hz.PosRampPlus1 = rampafloat_plus; + edrk.zadanie.rmp_oborots_zad_hz.PosRampMinus1 = -rampafloat_minus; + + edrk.zadanie.rmp_oborots_zad_hz.NegRampPlus1 = rampafloat_minus; + edrk.zadanie.rmp_oborots_zad_hz.NegRampMinus1 = -rampafloat_plus; + + rampafloat_plus = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T2_NARAST_ZADANIE_OBOROTS_ROTOR_PLUS)); + rampafloat_minus = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T2_NARAST_ZADANIE_OBOROTS_ROTOR_MINUS)); + edrk.zadanie.rmp_oborots_zad_hz.PosRampPlus2 = rampafloat_plus; + edrk.zadanie.rmp_oborots_zad_hz.PosRampMinus2 = -rampafloat_minus; + + edrk.zadanie.rmp_oborots_zad_hz.NegRampPlus2 = rampafloat_minus; + edrk.zadanie.rmp_oborots_zad_hz.NegRampMinus2 = -rampafloat_plus; + + } + +} + +void init_ramp_all_zadanie(void) +{ + _iq rampafloat, rampafloat_plus, rampafloat_minus; + +//rmp_oborots_imitation + edrk.zadanie.rmp_oborots_imitation.RampLowLimit = _IQ(MIN_ZADANIE_OBOROTS_ROTOR/60.0/NORMA_FROTOR); + edrk.zadanie.rmp_oborots_imitation.RampHighLimit = _IQ(MAX_ZADANIE_OBOROTS_ROTOR/60.0/NORMA_FROTOR); + rampafloat = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_IMITATION_OBOROTS_ROTOR)); + edrk.zadanie.rmp_oborots_imitation.RampPlus = rampafloat; + edrk.zadanie.rmp_oborots_imitation.RampMinus = -rampafloat; + + edrk.zadanie.rmp_oborots_imitation.Out = 0; + edrk.zadanie.rmp_oborots_imitation.DesiredInput = 0; + +// rmp_fzad + edrk.zadanie.rmp_fzad.RampLowLimit = _IQ(-MAX_ZADANIE_F/NORMA_FROTOR); //0 + edrk.zadanie.rmp_fzad.RampHighLimit = _IQ(MAX_ZADANIE_F/NORMA_FROTOR); + +// rampafloat = _IQ(1.0/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_F)); + rampafloat = _IQ((MAX_ZADANIE_F/NORMA_FROTOR)/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_F)); + edrk.zadanie.rmp_fzad.RampPlus = rampafloat; + edrk.zadanie.rmp_fzad.RampMinus = -rampafloat; + + edrk.zadanie.rmp_fzad.DesiredInput = 0; + edrk.zadanie.rmp_fzad.Out = 0; + +// rmp_oborots_hz + edrk.zadanie.rmp_oborots_zad_hz.RampLowLimit = _IQ(MIN_ZADANIE_OBOROTS_ROTOR/60.0/NORMA_FROTOR); //0 + edrk.zadanie.rmp_oborots_zad_hz.RampHighLimit = _IQ(MAX_ZADANIE_OBOROTS_ROTOR/60.0/NORMA_FROTOR); + + edrk.zadanie.rmp_oborots_zad_hz.RampLowLimit1 = _IQ(MIN_1_ZADANIE_OBOROTS_ROTOR/60.0/NORMA_FROTOR); //0 + edrk.zadanie.rmp_oborots_zad_hz.RampHighLimit1 = _IQ(MAX_1_ZADANIE_OBOROTS_ROTOR/60.0/NORMA_FROTOR); + +// rampafloat = _IQ(1.0/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_OBOROTS_ROTOR)); +// rampafloat = _IQ((MAX_ZADANIE_OBOROTS_ROTOR/NORMA_FROTOR/60.0)/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_OBOROTS_ROTOR)); +// edrk.zadanie.rmp_oborots_zad_hz.RampPlus = rampafloat; +// edrk.zadanie.rmp_oborots_zad_hz.RampMinus = -rampafloat; + + change_ramp_zadanie(); + + edrk.zadanie.rmp_oborots_zad_hz.DesiredInput = 0; + edrk.zadanie.rmp_oborots_zad_hz.Out = 0; + + +// + edrk.zadanie.rmp_Izad.RampLowLimit = _IQ(0); //0 + edrk.zadanie.rmp_Izad.RampHighLimit = _IQ(MAX_ZADANIE_I_M/NORMA_ACP); + +// rampafloat = _IQ(1.0/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_I_M)); + rampafloat = _IQ((MAX_ZADANIE_I_M/NORMA_ACP)/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_I_M)); + edrk.zadanie.rmp_Izad.RampPlus = rampafloat; + edrk.zadanie.rmp_Izad.RampMinus = -rampafloat; + + edrk.zadanie.rmp_Izad.DesiredInput = 0; + edrk.zadanie.rmp_Izad.Out = 0; + +// + edrk.zadanie.rmp_ZadanieU_Charge.RampLowLimit = _IQ(0); //0 + edrk.zadanie.rmp_ZadanieU_Charge.RampHighLimit = _IQ(MAX_ZADANIE_U_CHARGE/NORMA_ACP); + +// rampafloat = _IQ(1.0/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_U_CHARGE)); + rampafloat = _IQ((MAX_ZADANIE_U_CHARGE/NORMA_ACP)/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_U_CHARGE)); + edrk.zadanie.rmp_ZadanieU_Charge.RampPlus = rampafloat; + edrk.zadanie.rmp_ZadanieU_Charge.RampMinus = -rampafloat; + + edrk.zadanie.rmp_ZadanieU_Charge.DesiredInput = _IQ(NOMINAL_U_ZARYAD/NORMA_ACP); + edrk.zadanie.rmp_ZadanieU_Charge.Out = _IQ(NOMINAL_U_ZARYAD/NORMA_ACP); + + + +// + edrk.zadanie.rmp_k_u_disbalance.RampLowLimit = _IQ(0); //0 + edrk.zadanie.rmp_k_u_disbalance.RampHighLimit = _IQ(MAX_ZADANIE_K_U_DISBALANCE); + +// rampafloat = _IQ(1.0/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_K_U_DISBALANCE)); + rampafloat = _IQ((MAX_ZADANIE_K_U_DISBALANCE)/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_K_U_DISBALANCE)); + edrk.zadanie.rmp_k_u_disbalance.RampPlus = rampafloat; + edrk.zadanie.rmp_k_u_disbalance.RampMinus = -rampafloat; + + edrk.zadanie.rmp_k_u_disbalance.DesiredInput = 0; + edrk.zadanie.rmp_k_u_disbalance.Out = 0; + + +// + edrk.zadanie.rmp_kplus_u_disbalance.RampLowLimit = _IQ(0); //0 + edrk.zadanie.rmp_kplus_u_disbalance.RampHighLimit = _IQ(MAX_ZADANIE_KPLUS_U_DISBALANCE); + +// rampafloat = _IQ(1.0/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_KPLUS_U_DISBALANCE)); + rampafloat = _IQ((MAX_ZADANIE_KPLUS_U_DISBALANCE)/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_KPLUS_U_DISBALANCE)); + edrk.zadanie.rmp_kplus_u_disbalance.RampPlus = rampafloat; + edrk.zadanie.rmp_kplus_u_disbalance.RampMinus = -rampafloat; + + edrk.zadanie.rmp_kplus_u_disbalance.DesiredInput = 0; + edrk.zadanie.rmp_kplus_u_disbalance.Out = 0; + + + +// + edrk.zadanie.rmp_kzad.RampLowLimit = _IQ(0); //0 + edrk.zadanie.rmp_kzad.RampHighLimit = _IQ(MAX_ZADANIE_K_M); + +// rampafloat = _IQ(1.0/(2.0*FREQ_PWM*T_NARAST_ZADANIE_K_M)); + rampafloat = _IQ((MAX_ZADANIE_K_M)/(2.0*FREQ_PWM*T_NARAST_ZADANIE_K_M)); + edrk.zadanie.rmp_kzad.RampPlus = rampafloat; + edrk.zadanie.rmp_kzad.RampMinus = -rampafloat; + + edrk.zadanie.rmp_kzad.DesiredInput = 0; + edrk.zadanie.rmp_kzad.Out = 0; + + +// + edrk.zadanie.rmp_powers_zad.RampLowLimit = _IQ(MIN_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ)); //0 + edrk.zadanie.rmp_powers_zad.RampHighLimit = _IQ(MAX_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ)); + + edrk.zadanie.rmp_powers_zad.RampLowLimit1 = _IQ(MIN_1_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ)); + edrk.zadanie.rmp_powers_zad.RampHighLimit1 = _IQ(MAX_1_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ)); + +// rampafloat = _IQ((MAX_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_POWER)); +// edrk.zadanie.rmp_powers_zad.RampPlus = rampafloat; +// edrk.zadanie.rmp_powers_zad.RampMinus = -rampafloat; + + +//// + rampafloat_plus = _IQ((MAX_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T1_NARAST_ZADANIE_POWER_PLUS)); + rampafloat_minus = _IQ((MAX_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T1_NARAST_ZADANIE_POWER_MINUS)); + + edrk.zadanie.rmp_powers_zad.PosRampPlus1 = rampafloat_plus; + edrk.zadanie.rmp_powers_zad.PosRampMinus1 = -rampafloat_minus; + + edrk.zadanie.rmp_powers_zad.NegRampPlus1 = rampafloat_minus; + edrk.zadanie.rmp_powers_zad.NegRampMinus1 = -rampafloat_plus; + + rampafloat_plus = _IQ((MAX_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T2_NARAST_ZADANIE_POWER_PLUS)); + rampafloat_minus = _IQ((MAX_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T2_NARAST_ZADANIE_POWER_MINUS)); + + edrk.zadanie.rmp_powers_zad.PosRampPlus2 = rampafloat_plus; + edrk.zadanie.rmp_powers_zad.PosRampMinus2 = -rampafloat_minus; + + edrk.zadanie.rmp_powers_zad.NegRampPlus2 = rampafloat_minus; + edrk.zadanie.rmp_powers_zad.NegRampMinus2 = -rampafloat_plus; + +//// + + edrk.zadanie.rmp_powers_zad.DesiredInput = 0; + edrk.zadanie.rmp_powers_zad.Out = 0; + +// + + edrk.zadanie.rmp_limit_powers_zad.RampLowLimit = 0;//_IQ(0); //0 + edrk.zadanie.rmp_limit_powers_zad.RampHighLimit = _IQ(SUPER_MAX_ZADANIE_LIMIT_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ)); + + edrk.zadanie.rmp_limit_powers_zad.RampLowLimit1 = 0; + edrk.zadanie.rmp_limit_powers_zad.RampHighLimit1 = _IQ(MAX_1_ZADANIE_LIMIT_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ)); + + rampafloat_plus = _IQ((SUPER_MAX_ZADANIE_LIMIT_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T1_NARAST_ZADANIE_LIMIT_POWER_PLUS)); + rampafloat_minus = _IQ((SUPER_MAX_ZADANIE_LIMIT_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T1_NARAST_ZADANIE_LIMIT_POWER_MINUS)); + + edrk.zadanie.rmp_limit_powers_zad.PosRampPlus1 = rampafloat_plus; + edrk.zadanie.rmp_limit_powers_zad.PosRampMinus1 = -rampafloat_minus; + + edrk.zadanie.rmp_limit_powers_zad.NegRampPlus1 = rampafloat_minus; + edrk.zadanie.rmp_limit_powers_zad.NegRampMinus1 = -rampafloat_plus; + + rampafloat_plus = _IQ((MAX_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T2_NARAST_ZADANIE_POWER_PLUS)); + rampafloat_minus = _IQ((MAX_ZADANIE_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T2_NARAST_ZADANIE_POWER_MINUS)); + + edrk.zadanie.rmp_limit_powers_zad.PosRampPlus2 = rampafloat_plus; + edrk.zadanie.rmp_limit_powers_zad.PosRampMinus2 = -rampafloat_minus; + + edrk.zadanie.rmp_limit_powers_zad.NegRampPlus2 = rampafloat_minus; + edrk.zadanie.rmp_limit_powers_zad.NegRampMinus2 = -rampafloat_plus; + +// rampafloat = _IQ((MAX_ZADANIE_LIMIT_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ))/(FREQ_RUN_RAMP*T_NARAST_ZADANIE_LIMIT_POWER)); + +// edrk.zadanie.rmp_limit_powers_zad.RampPlus = rampafloat; +// edrk.zadanie.rmp_limit_powers_zad.RampMinus = -rampafloat; + + edrk.zadanie.rmp_limit_powers_zad.DesiredInput = 0; + edrk.zadanie.rmp_limit_powers_zad.Out = 0; + +// + + +} + +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +#pragma CODE_SECTION(ramp_all_zadanie,".fast_run"); +void load_current_ramp_oborots_power(void) +{ + int mode=0; + static int prev_mode = 0; + + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_OBOROTS || + edrk.Mode_ScalarVectorUFConst == ALG_MODE_SCALAR_OBOROTS) + mode = 1; + + if (edrk.Mode_ScalarVectorUFConst == ALG_MODE_FOC_POWER || + edrk.Mode_ScalarVectorUFConst == ALG_MODE_SCALAR_POWER) + mode = 2; + + if (mode==1 && prev_mode==2) + { + // , + edrk.zadanie.rmp_oborots_zad_hz.Out = WRotor.iqWRotorSumFilter3; + //edrk.zadanie.iq_oborots_zad_hz = WRotor.iqWRotorSumFilter3; + } + + + if (mode==2 && prev_mode==1) + { + // , + edrk.zadanie.rmp_powers_zad.Out = edrk.iq_power_kw_one_filter_znak;//filter.PowerScalarFilter2; + } + + prev_mode = mode; + +} +////////////////////////////////////////////////////////// +#pragma CODE_SECTION(ramp_all_zadanie,".fast_run"); +void ramp_all_zadanie(int flag_set_zero) +{ + +// if (edrk.Status_Ready.bits.ImitationReady2) + { + edrk.zadanie.rmp_oborots_imitation.DesiredInput = edrk.zadanie.iq_oborots_zad_hz; + edrk.zadanie.rmp_oborots_imitation.calc(&edrk.zadanie.rmp_oborots_imitation); + edrk.zadanie.rmp_oborots_imitation_rmp = edrk.zadanie.rmp_oborots_imitation.Out; + } + ////////////////////////////////////////////// + if (flag_set_zero==0) + edrk.zadanie.rmp_Izad.DesiredInput = edrk.zadanie.iq_Izad; + else + if (flag_set_zero==2) + { + edrk.zadanie.rmp_Izad.DesiredInput = 0; + edrk.zadanie.rmp_Izad.Out = 0; + } + else + edrk.zadanie.rmp_Izad.DesiredInput = 0; + + edrk.zadanie.rmp_Izad.calc(&edrk.zadanie.rmp_Izad); + edrk.zadanie.iq_Izad_rmp = edrk.zadanie.rmp_Izad.Out; + ////////////////////////////////////////////// + edrk.zadanie.rmp_ZadanieU_Charge.DesiredInput = edrk.zadanie.iq_ZadanieU_Charge; + edrk.zadanie.rmp_ZadanieU_Charge.calc(&edrk.zadanie.rmp_ZadanieU_Charge); + edrk.zadanie.iq_ZadanieU_Charge_rmp = edrk.zadanie.rmp_ZadanieU_Charge.Out; + ////////////////////////////////////////////// + if (flag_set_zero==0) + edrk.zadanie.rmp_fzad.DesiredInput = edrk.zadanie.iq_fzad; + else + if (flag_set_zero==2) + { + edrk.zadanie.rmp_fzad.DesiredInput = 0; + edrk.zadanie.rmp_fzad.Out = 0; + } + else + edrk.zadanie.rmp_fzad.DesiredInput = 0; + + edrk.zadanie.rmp_fzad.calc(&edrk.zadanie.rmp_fzad); + edrk.zadanie.iq_fzad_rmp = edrk.zadanie.rmp_fzad.Out; + ////////////////////////////////////////////// + edrk.zadanie.rmp_k_u_disbalance.DesiredInput = edrk.zadanie.iq_k_u_disbalance; + edrk.zadanie.rmp_k_u_disbalance.calc(&edrk.zadanie.rmp_k_u_disbalance); + edrk.zadanie.iq_k_u_disbalance_rmp = edrk.zadanie.rmp_k_u_disbalance.Out; + ////////////////////////////////////////////// + edrk.zadanie.rmp_kplus_u_disbalance.DesiredInput = edrk.zadanie.iq_kplus_u_disbalance; + edrk.zadanie.rmp_kplus_u_disbalance.calc(&edrk.zadanie.rmp_kplus_u_disbalance); + edrk.zadanie.iq_kplus_u_disbalance_rmp = edrk.zadanie.rmp_kplus_u_disbalance.Out; + ////////////////////////////////////////////// + if (flag_set_zero==0) + edrk.zadanie.rmp_kzad.DesiredInput = edrk.zadanie.iq_kzad; + else + if (flag_set_zero==2) + { + edrk.zadanie.rmp_kzad.DesiredInput = 0; + edrk.zadanie.rmp_kzad.Out = 0; + } + else + edrk.zadanie.rmp_kzad.DesiredInput = 0; + edrk.zadanie.rmp_kzad.calc(&edrk.zadanie.rmp_kzad); + edrk.zadanie.iq_kzad_rmp = edrk.zadanie.rmp_kzad.Out; + ////////////////////////////////////////////// + if (flag_set_zero==0) + edrk.zadanie.rmp_oborots_zad_hz.DesiredInput = edrk.zadanie.iq_oborots_zad_hz; + else + if (flag_set_zero==2) + { + edrk.zadanie.rmp_oborots_zad_hz.DesiredInput = 0; + edrk.zadanie.rmp_oborots_zad_hz.Out = 0; + } + else + edrk.zadanie.rmp_oborots_zad_hz.DesiredInput = 0; + + edrk.zadanie.rmp_oborots_zad_hz.calc(&edrk.zadanie.rmp_oborots_zad_hz); + edrk.zadanie.iq_oborots_zad_hz_rmp = edrk.zadanie.rmp_oborots_zad_hz.Out; + + ////////////////////////////////////////////// +// if (flag_set_zero==0) +// edrk.zadanie.rmp_limit_powers_zad.DesiredInput = edrk.zadanie.iq_limit_power_zad; +// else +// if (flag_set_zero==2) +// { +// edrk.zadanie.rmp_limit_powers_zad.DesiredInput = 0; +// edrk.zadanie.rmp_limit_powers_zad.Out = 0; +// } +// else +// edrk.zadanie.rmp_limit_powers_zad.DesiredInput = 0; + + edrk.zadanie.rmp_limit_powers_zad.DesiredInput = edrk.zadanie.iq_limit_power_zad; + edrk.zadanie.rmp_limit_powers_zad.calc(&edrk.zadanie.rmp_limit_powers_zad); + edrk.zadanie.iq_limit_power_zad_rmp = edrk.zadanie.rmp_limit_powers_zad.Out; + + + + ////////////////////////////////////////////// + if (flag_set_zero==0) + { + if (edrk.zadanie.iq_power_zad>=0) + { + if (edrk.zadanie.iq_power_zad>edrk.zadanie.iq_limit_power_zad_rmp) + edrk.zadanie.rmp_powers_zad.DesiredInput = edrk.zadanie.iq_limit_power_zad_rmp; + else + edrk.zadanie.rmp_powers_zad.DesiredInput = edrk.zadanie.iq_power_zad; + } + else + { + if (edrk.zadanie.iq_power_zad<-edrk.zadanie.iq_limit_power_zad_rmp) + edrk.zadanie.rmp_powers_zad.DesiredInput = -edrk.zadanie.iq_limit_power_zad_rmp; + else + edrk.zadanie.rmp_powers_zad.DesiredInput = edrk.zadanie.iq_power_zad; + } + + } + else + if (flag_set_zero==2) + { + edrk.zadanie.rmp_powers_zad.DesiredInput = 0; + edrk.zadanie.rmp_powers_zad.Out = 0; + } + else + edrk.zadanie.rmp_powers_zad.DesiredInput = 0; + + edrk.zadanie.rmp_powers_zad.calc(&edrk.zadanie.rmp_powers_zad); + edrk.zadanie.iq_power_zad_rmp = edrk.zadanie.rmp_powers_zad.Out; + +} + +////////////////////////////////////////////////////////// diff --git a/Inu/Src2/551/main/ramp_zadanie_tools.h b/Inu/Src2/551/main/ramp_zadanie_tools.h new file mode 100644 index 0000000..c90acb6 --- /dev/null +++ b/Inu/Src2/551/main/ramp_zadanie_tools.h @@ -0,0 +1,20 @@ +/* + * ramp_zadanie_tools.h + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef SRC_MAIN_RAMP_ZADANIE_TOOLS_H_ +#define SRC_MAIN_RAMP_ZADANIE_TOOLS_H_ + +#define FREQ_RUN_RAMP FREQ_PWM // (2.0*FREQ_PWM) + + +void ramp_all_zadanie(int flag_set_zero); +void change_ramp_zadanie(void); +void init_ramp_all_zadanie(void); +void load_current_ramp_oborots_power(void); + + +#endif /* SRC_MAIN_RAMP_ZADANIE_TOOLS_H_ */ diff --git a/Inu/Src2/551/main/sbor_shema.c b/Inu/Src2/551/main/sbor_shema.c new file mode 100644 index 0000000..7157fd1 --- /dev/null +++ b/Inu/Src2/551/main/sbor_shema.c @@ -0,0 +1,1764 @@ +/* + * sbor_shema.c + * + * Created on: 18 . 2021 . + * Author: stud + */ +#include "sbor_shema.h" +#include "IQmathLib.h" +#include "edrk_main.h" +#include "optical_bus.h" +#include "adc_tools.h" +#include "control_station.h" +#include "control_station_project.h" +#include "digital_filters.h" +#include "detect_errors.h" + +#define RASCEPITEL_MANUAL_ALWAYS_ON 0//1 +/////////////////////////////////////////////// +/////////////////////////////////////////////// +//#define IQ_MINIMAL_DELTA_RUN_CHARGE_1 559240 //100V +//#define IQ_MINIMAL_DELTA_RUN_CHARGE_2 1118480 //200V + +//#define IQ_MINIMAL_DELTA_RUN_CHARGE 279620 // 50V +#define IQ_MINIMAL_DELTA_RUN_CHARGE_1 1118480// 200 V ///279620 // 50V +#define IQ_MINIMAL_DELTA_RUN_CHARGE_2 1118480// 200 V //279620 // 50V + +#define IQ_MINIMAL_DELTA_RUN_WORK 2796202 // 500V // 2236960 // 400V // 1677720 // 300 V // 559240 // 100V + +#define IQ_MINIMAL_ZAD_U_CHARGE 55924 // 10V +#define IQ_MAXIMAL_ZAD_U_CHARGE 14596177 // 2610V +#define IQ_MINIMAL_DELTA_RUN_CHARGE2 139810 //25 V +#define TIME_WAIT_CHARGE_ON 300 //30 sec +#define TIME_PAUSE_U_RISE 30 // 1 sec + +#define IQ_MINIMAL_RISE_U 55924 // 10V + +unsigned int zaryad_on_off(unsigned int flag) +{ + static int restart_charge=0, batt_ok = 0; + static unsigned int time_wait_on_charge=0; + static unsigned int time_pause_detect_u_rise=0; + + static _iq prev_U1=0, prev_U2 = 0; + + batt_ok = 0; +// - !!! + if (_IQabs(filter.iqU_1_long-filter.iqU_2_long)>IQ_MINIMAL_DELTA_RUN_WORK) + { +// edrk.errors.e6.bits.ERROR_PRE_CHARGE_U |= 1; + edrk.errors.e6.bits.ER_DISBAL_BATT |= 1; + edrk.to_ing.bits.ZARYAD_ON = 0; + batt_ok = 0; + } + + if (flag && edrk.summ_errors==0 && edrk.errors.e6.bits.ERROR_PRE_CHARGE_U==0 && edrk.errors.e6.bits.ER_DISBAL_BATT==0 ) + { +// !!! + if ((edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_ZAD_U_CHARGE) <= 0) + { + edrk.errors.e5.bits.ERROR_PRE_CHARGE_ON |= 1; + edrk.to_ing.bits.ZARYAD_ON = 0; + return 0; + } + // !!! + + if ((IQ_MAXIMAL_ZAD_U_CHARGE - edrk.zadanie.iq_ZadanieU_Charge) < 0) + { + edrk.errors.e5.bits.ERROR_PRE_CHARGE_ON |= 1; + edrk.to_ing.bits.ZARYAD_ON = 0; + return 0; + } + +// + if (_IQabs(filter.iqU_1_long-filter.iqU_2_long)>IQ_MINIMAL_DELTA_RUN_WORK) //IQ_MINIMAL_DELTA_RUN_CHARGE_1 + { + edrk.errors.e6.bits.ER_DISBAL_BATT |= 1; + edrk.to_ing.bits.ZARYAD_ON = 0; + return 0; + } + + if (restart_charge == 0) + { + + // , + if ( edrk.from_ing1.bits.ZARYAD_ON && + (filter.iqU_1_long>=(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_1) + || filter.iqU_2_long>=(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_1)) + ) + { + restart_charge = 1; + edrk.to_ing.bits.ZARYAD_ON = 0; + } + else + { + //TODO !!! if. ? + if ( edrk.from_ing1.bits.ZARYAD_ON==0 && + (filter.iqU_1_long>=(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_2) + || filter.iqU_2_long>=(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_2)) ) + { + restart_charge = 1; + edrk.to_ing.bits.ZARYAD_ON = 0; + } + else + { + // , . + if ( (filter.iqU_1_long<(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_2)) + && (filter.iqU_2_long<(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_2)) ) + edrk.to_ing.bits.ZARYAD_ON = 1; + + } + + } + + if (pause_detect_error(&time_pause_detect_u_rise,TIME_PAUSE_U_RISE,1)) + { + time_pause_detect_u_rise = 0; + + if (((filter.iqU_1_long-prev_U1)>=IQ_MINIMAL_RISE_U) || + ((filter.iqU_2_long-prev_U2)>=IQ_MINIMAL_RISE_U) ) + time_wait_on_charge = 0; + + + prev_U1 = filter.iqU_1_long; + prev_U2 = filter.iqU_2_long; + } + + + // !!! + if (pause_detect_error(&time_wait_on_charge,TIME_WAIT_CHARGE_ON,1)) + edrk.errors.e6.bits.ERROR_PRE_CHARGE_U |= 1; +/* + + if (filter.iqU_1_long>=(edrk.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE2) + || filter.iqU_2_long>=(edrk.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE2)) + { + restart_charge = 1; + edrk.to_ing.bits.ZARYAD_ON = 0; + } + else + { + // + if (_IQabs(filter.iqU_1_long-filter.iqU_2_long)>IQ_MINIMAL_DELTA_RUN_CHARGE) + edrk.errors.e6.bits.ER_DISBAL_BATT |= 1; + + // , . + if ( (filter.iqU_1_long<(edrk.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE)) + || (filter.iqU_2_long<(edrk.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE)) ) + edrk.to_ing.bits.ZARYAD_ON = 1; + + if ( (filter.iqU_1_long>=(edrk.iq_ZadanieU_Charge)) + && (filter.iqU_2_long>=(edrk.iq_ZadanieU_Charge)) ) + { + restart_charge = 1; + edrk.to_ing.bits.ZARYAD_ON = 0; + } + } +*/ + + } + else//restart_charge==0 + { + // - !!! + if ( (filter.iqU_1_long<(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_2)) + || (filter.iqU_2_long<(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_2)) ) + edrk.errors.e6.bits.ERROR_PRE_CHARGE_U |= 1; + + } //restart_charge==0 + } + else // flag==1 + { + restart_charge = 0; + edrk.to_ing.bits.ZARYAD_ON = 0; + time_wait_on_charge = 0; + prev_U1 = filter.iqU_1_long; + prev_U2 = filter.iqU_2_long; + } + + if ( (filter.iqU_1_long>=(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_2)) + && (filter.iqU_2_long>=(edrk.zadanie.iq_ZadanieU_Charge-IQ_MINIMAL_DELTA_RUN_CHARGE_2)) + && (_IQabs(filter.iqU_1_long-filter.iqU_2_long)=edrk.iqMIN_U_IN) + && (filter.iqUin_m2>=edrk.iqMIN_U_IN) + && (filter.iqUin_m1<=edrk.iqMAX_U_IN) + && (filter.iqUin_m2<=edrk.iqMAX_U_IN) ) + return 1; + else + return 0; + + } + else + return 0; +} +/////////////////////////////////////////////// + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// + +#define TIME_WAIT_SBOR 8500 +#define TIME_WAIT_ANSWER_NASOS 500 +#define TIME_WAIT_OK_NASOS 50 + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +void sbor_shema_pusk_nasos(unsigned int t_start, unsigned int t_finish) +{ + static unsigned int time_error_nasos = 0; + static unsigned int time_ok_nasos = 0; + + int status_pump, status_pump_long; + + // + if (edrk.Sbor_Mode == t_start) + { + edrk.enter_to_pump_stage = 1; + // , ! + edrk.warnings.e5.bits.PUMP_1 = edrk.warnings.e5.bits.PUMP_2 = 0; + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_PUMP]==0) + edrk.AutoStartPump = 1; + + time_error_nasos = 0; + time_ok_nasos = 0; + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_PUMP]==1) + edrk.Sbor_Mode = t_finish; // + } + + // + if (edrk.Sbor_Mode>t_start && edrk.Sbor_Mode>1) )) + { + + + } + + // , + if (edrk.Sbor_Mode==(t_finish-1)) + { + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_PUMP_ON_SBOR |= 1; + edrk.Status_Sbor = 2; + edrk.AutoStartPump = 0; + } + + } +// + if (edrk.Sbor_Mode>t_finish) + { + if (edrk.StatusPumpFanAll==0) + { + // + if (edrk.SelectPump1_2==1) + { + // 1 + // + if (pause_detect_error(&time_error_nasos,TIME_WAIT_ANSWER_NASOS,1)) + { + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_RESTART_PUMP_1_ON_SBOR |= 1; + edrk.Status_Sbor = 102; + edrk.AutoStartPump = 0; + } + } + else + if (edrk.SelectPump1_2==2) + { + // 2 + // + if (pause_detect_error(&time_error_nasos,TIME_WAIT_ANSWER_NASOS,1)) + { + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_RESTART_PUMP_1_ON_SBOR |= 1; + edrk.Status_Sbor = 102; + edrk.AutoStartPump = 0; + } + } + else + { + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_RESTART_PUMP_ALL_ON_SBOR |= 1; + edrk.Status_Sbor = 102; + edrk.AutoStartPump = 0; + } + } + else + time_error_nasos = 0; + + } +} + +void sbor_shema_pusk_zaryad(unsigned int t_start, unsigned int t_finish) +{ + ///////////////////////////////////// + // + if (edrk.Sbor_Mode == t_start) + { + if (control_station.active_array_cmd[CONTROL_STATION_CMD_ENABLE_ON_CHARGE]==1) + edrk.Run_Pred_Zaryad = 1; // ! + } + + // + // + + if (edrk.Sbor_Mode>t_start && edrk.Sbor_Modet_finish) + { + if (edrk.Zaryad_OK==0 || edrk.from_ing1.bits.ZARYAD_ON==1 ) + { + edrk.Run_Pred_Zaryad = 0; + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_PRED_ZARYAD_AFTER |= 1; + edrk.Status_Sbor = 104; + } + } + +} +void sbor_shema_pusk_ump(unsigned int t_start, unsigned int t_finish) +{ + static int enable_run_ump=0; + // UMP + if (edrk.Sbor_Mode==t_start && edrk.Zaryad_OK == 1) + { + // edrk.Run_UMP = 1; + enable_run_ump = 0; + } + + + if (edrk.Sbor_Mode>t_start && edrk.Sbor_Modet_finish && (edrk.Zaryad_OK == 0 || edrk.Status_UMP_Ok==0)) +// { +// +// edrk.Run_UMP = 0; +// edrk.Run_Pred_Zaryad = 0; +// edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; +// edrk.errors.e7.bits.UMP_NOT_ANSWER |= 1; +// edrk.Run_QTV = 0; +// edrk.Status_Sbor = 105; +// } + + +} + +void sbor_shema_pusk_qtv(unsigned int t_start, unsigned int t_finish) +{ + if (edrk.Sbor_Mode==t_start && edrk.Zaryad_OK == 1 && edrk.Status_UMP_Ok) + { + edrk.Run_QTV = 1; + } + + + if (edrk.Sbor_Mode>t_start && edrk.Sbor_Modet_finish) + { + if (edrk.Zaryad_OK == 0 || edrk.Status_QTV_Ok==0) + { + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_STATUS_QTV |= 1; + edrk.Run_QTV = 0; + edrk.Status_Sbor = 106; + } + + } + +} + +void sbor_shema_stop_ump(unsigned int t_start, unsigned int t_finish) +{ + // UMP + if (edrk.Sbor_Mode==t_start && edrk.Status_QTV_Ok == 1) + { + edrk.Run_UMP = 0; + } + + + if (edrk.Sbor_Mode>t_start && edrk.Sbor_Modet_finish && edrk.Status_UMP_Ok==1) + { + + edrk.Run_UMP = 0; + edrk.Run_Pred_Zaryad = 0; + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_UMP_ON_AFTER |= 1; + edrk.Run_QTV = 0; + edrk.Status_Sbor = 107; + } + + +} + + +void sbor_shema_rascepitel_level_1(unsigned int t_start, unsigned int t_finish) +{ + +#if(RASCEPITEL_MANUAL_ALWAYS_ON==1) + if (edrk.Sbor_Mode==t_start && (edrk.Zaryad_OK == 1 && edrk.Status_QTV_Ok==1 )) + { + edrk.Stage_Sbor = STAGE_SBOR_STATUS_RASCEPITEL_1; + // , + if (optical_read_data.data.cmd.bit.ready_cmd != CODE_READY_CMD_READY2 ) + { + edrk.Run_Rascepitel = 1; + edrk.Sbor_Mode = t_finish; // + } + else + edrk.RunZahvatRascepitel = 1; // + } + + if (edrk.Sbor_Mode>t_start && edrk.Sbor_Modet_start && edrk.Sbor_Modet_finish) + { + if (edrk.Run_Rascepitel==0) + { + // + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_RASCEPITEL_WAIT_CMD |= 1; + edrk.Run_QTV = 0; + + edrk.Status_Sbor = 108; + // + if (edrk.RunZahvatRascepitel) + edrk.errors.e1.bits.NO_CONFIRM_ON_RASCEPITEL |= 1; + + edrk.RunZahvatRascepitel = 0; + edrk.Run_Rascepitel = 0; + } + } + +} + +void sbor_shema_rascepitel_level_2(unsigned int t_start, unsigned int t_finish) +{ + + if (edrk.Sbor_Mode>t_start && edrk.Sbor_Modet_finish && edrk.Status_Rascepitel_Ok==0) + { + // , + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.Run_QTV = 0; + edrk.Status_Sbor = 109; +// edrk.errors.e6.bits.RASCEPITEL_ERROR_NOT_ANSWER |= 1; + edrk.errors.e11.bits.ERROR_RASCEPITEL_ON_AFTER |= 1; + edrk.RunZahvatRascepitel = 0; + edrk.Run_Rascepitel = 0; + + + } + + + // + // edrk.RunZahvatRascepitel + + +// +// if (edrk.Sbor_Mode>t_start && edrk.Sbor_Modet_start && edrk.Sbor_Modet_start && edrk.Sbor_Modet_finish) +// { +// if (edrk.Status_Rascepitel_Ok==0) +// { +// edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; +// edrk.Run_QTV = 0; +// edrk.RunZahvatRascepitel = 0; +// edrk.Status_Sbor = 9; +// edrk.Run_Rascepitel = 0; +// +// } +// +// } + +} + +void sbor_shema_wait_ready_another(unsigned int t_start, unsigned int t_finish) +{ + + if (edrk.Sbor_Mode>t_start && edrk.Sbor_Modet_start && (edrk.Zaryad_OK == 1 && edrk.Status_QTV_Ok==1 && edrk.Status_Rascepitel_Ok)) + { + edrk.Stage_Sbor = STAGE_SBOR_STATUS_FINISH; + edrk.SborFinishOk = 1; + // allow_discharge = 1; + } + + + if (edrk.Sbor_Mode>t_finish && (edrk.SborFinishOk) ) + { + edrk.time_wait_sbor = 0; + } + else + edrk.Sbor_Mode++; + +} + + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +#define TIME_WAIT_RELE_UMP_ON 20 //2 sec +#define TIME_WAIT_RELE_UMP_OFF 20 //2 sec + +#define TIME_WAIT_ANSWER_UMP_ON 150 //15 sec +#define TIME_WAIT_ANSWER_UMP_OFF 40 //4 sec + +#define TIME_PAUSE_AFTER_GET_READY_UMP 50 // 5 sec + +/////////////////////////////////////////////// +int ump_on_off(unsigned int flag) +{ +static unsigned int time_wait_rele_on_ump=0; +static unsigned int time_wait_rele_off_ump=0; +static unsigned int time_wait_answer_on_ump=0; +static unsigned int time_wait_answer_off_ump=0; + + +int cmd_ump=0;//,cmd_p2=0; +static int UMP_Ok = 0; +static int prev_error = 0, count_ready_upm = 0; //, flag_enable_on_ump = 0; + + + cmd_ump = 0; +// cmd_p2 = 0; + + if ( flag==1 && edrk.summ_errors==0) + { + cmd_ump = 1; + } + else + { + cmd_ump = 0; + } + + + + edrk.cmd_to_ump = cmd_ump; + + + if (cmd_ump) + { + +// if ((pause_detect_error(&time_wait_rele_on_qtv,TIME_WAIT_RELE_UMP_ON,1)==0) && edrk.from_shema.bits.UMP_ON_OFF==0) +// { +// edrk.to_shema.bits.QTV_ON_OFF = 1; +// } +// else + + // ! + if (edrk.from_shema_filter.bits.READY_UMP == 1) + { + // TIME_PAUSE_AFTER_GET_READY_UMP + if (count_ready_upm10) && edrk.Status_Ready.bits.ready1; + + if (mode && edrk.summ_errors==0 && enable_sbor==0) + { + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_DISABLE_SBOR |= 1; + // + edrk.AutoStartPump = 0; + edrk.Sbor_Mode = 0; + edrk.Razbor_Mode = 0; + edrk.time_wait_sbor = 0; + time_wait_razbor = 0; + + edrk.Run_Pred_Zaryad = 0; + edrk.Zaryad_OK = 0; + edrk.Run_QTV = 0; + edrk.Run_UMP = 0; + edrk.SborFinishOk = 0; + edrk.RunZahvatRascepitel = 0; + +// edrk.Run_Rascepitel = 0; + + edrk.Status_Sbor = 1; + first_run = 1; + edrk.enter_to_pump_stage = 0; + return (edrk.Sbor_Mode); + } + +// + if (mode && edrk.summ_errors==0 && enable_sbor) + { + + if (pause_detect_error(&edrk.time_wait_sbor,TIME_WAIT_SBOR,1)) + { +// if (edrk.SborFinishOk==0) + edrk.errors.e7.bits.ERROR_SBOR_SHEMA |= 1; + edrk.errors.e11.bits.ERROR_VERY_LONG_SBOR |= 1; + } + + if (first_run) + { + if (edrk.flag_another_bs_first_ready12==1 && edrk.flag_this_bs_first_ready12==0) + { + // ? + add_t1 = 80; // 12 + } + else + if (edrk.flag_another_bs_first_ready12==0 && edrk.flag_this_bs_first_ready12==1) + { + // ? + add_t1 = 5; // 1 + } + else + if (edrk.flag_this_bs_first_ready12==0 && edrk.flag_another_bs_first_ready12==0) + { + // + if (edrk.flag_second_PCH == 1) + add_t1 = 120; // 18 + else + add_t1 = 80; // 7 + } + + + + +// if (optical_read_data.data.cmd.bit.ready_cmd==CODE_READY_CMD_READY1TO2 && edrk.flag_second_PCH == 1) +// { +// // ? +// add_t1 = 150; // 15 +// } +// else +// { +// if (edrk.flag_second_PCH == 0) +// add_t1 = 0; +// else +// add_t1 = 70; // 7 +// } + + first_run = 0; + } + + // + t1 = 10 + add_t1; + delta_t = 300;//200; + t2 = t1 + delta_t; + sbor_shema_pusk_nasos(t1,t2);//350 + + t1 = t2+30;//380 + delta_t = 700; + t2 = t1 + delta_t; + sbor_shema_pusk_zaryad(t1,t2);//1080 + + t1 = t2+10;//1090 + delta_t = 750+750+300+600;//2400 + t2 = t1 + delta_t; + sbor_shema_pusk_ump(t1,t2);//3490 + + t1 = t2+30; //3520 3 + delta_t = 200; + t2 = t1 + delta_t; + sbor_shema_pusk_qtv(t1,t2);//3720 + + t1 = t2; + delta_t = 150; + t2 = t1 + delta_t; + sbor_shema_stop_ump(t1,t2);//3870 + + // , tfinish + // tstart tfinish + // ! + t1 = t2; + delta_t = 250; + t2 = t1 + delta_t; + sbor_shema_rascepitel_level_1(t1,t2);//4120 + + // tfinish + // tfinish + t1 = t2; + delta_t = 300; + t2 = t1 + delta_t; + sbor_shema_rascepitel_level_2(t1,t2);//4420 + + t1 = t2; + delta_t = 200; + t2 = t1 + delta_t; + sbor_shema_rascepitel_level_3(t1,t2);//4620 + + // , , + // tfinish + t1 = t2; + delta_t = 300; + t2 = t1 + delta_t; + sbor_shema_rascepitel_level_4(t1,t2);//4920 + + // tfinish + // , + t1 = t2; + delta_t = 1800; + t2 = t1 + delta_t; + sbor_shema_wait_ready_another(t1,t2);//6720 + + t1 = t2; + delta_t = 50; + t2 = t1 + delta_t; + sbor_shema_wait_finish(t1,t2);//6770 + + edrk.Razbor_Mode = 0; + edrk.RazborNotFinish = 0; + edrk.RunUnZahvatRascepitel = 0; + + if (edrk.Zaryad_OK) + may_be_discharge = 1; + + } + ///////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////// + // + ///////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////// + else + { + first_run = 1; + edrk.enter_to_pump_stage = 0; + // + if (edrk.Razbor_Mode==0) + edrk.RazborNotFinish = 1; + + if (edrk.Status_QTV_Ok==0 && edrk.Status_UMP_Ok==0 && may_be_discharge && edrk.Razbor_Mode>100) + { + allow_discharge = 1; + may_be_discharge = 0; + } + + edrk.AutoStartPump = 0; + edrk.Sbor_Mode = 0; + edrk.time_wait_sbor = 0; + edrk.Zaryad_OK = 0; + edrk.Run_QTV = 0; + edrk.Run_UMP = 0; + edrk.SborFinishOk = 0; + edrk.Run_Pred_Zaryad = 0; + edrk.RunZahvatRascepitel = 0; + + if (edrk.Razbor_Mode==10 && edrk.Status_QTV_Ok==1) + { + // + edrk.errors.e2.bits.ERROR_RAZBOR_SHEMA |= 1; + + } + + if (edrk.Run_Rascepitel && edrk.Razbor_Mode==20 && edrk.Status_QTV_Ok==0 && edrk.Status_Rascepitel_Ok==0) + { + // , -, + edrk.Run_Rascepitel = 0; + edrk.Razbor_Mode=1000; // + } + + + + if (edrk.Run_Rascepitel && edrk.Razbor_Mode==30 && edrk.Status_QTV_Ok==0 && edrk.Status_Rascepitel_Ok==1) + { + // , + if (optical_read_data.data.cmd.bit.ready_cmd != CODE_READY_CMD_READY2 ) + edrk.Run_Rascepitel = 0; + else + edrk.RunUnZahvatRascepitel = 1; // + } + + + + if (edrk.Razbor_Mode>40 && edrk.Razbor_Mode<390 && (edrk.Status_QTV_Ok==0) + && edrk.RunUnZahvatRascepitel && edrk.Status_Rascepitel_Ok==1) + { + // , + // + if (optical_read_data.data.cmd.bit.rascepitel_cmd == CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_ON ) // 01 - , + { + edrk.Run_Rascepitel = 0; + edrk.RunUnZahvatRascepitel = 0; + edrk.Razbor_Mode = 390; + } + } + + + + // , + if (edrk.Razbor_Mode>40 && edrk.Razbor_Mode<600 && (edrk.Status_QTV_Ok==0) + && edrk.RunUnZahvatRascepitel==0 && edrk.Run_Rascepitel==0) + { + if (edrk.Status_Rascepitel_Ok == 0 ) + { + edrk.Razbor_Mode = 600; + } + } + + + + if (edrk.Razbor_Mode>390 && (edrk.Status_QTV_Ok==0) + && edrk.RunUnZahvatRascepitel && edrk.Status_Rascepitel_Ok==1 && edrk.Run_Rascepitel) + { + if (optical_read_data.data.cmd.bit.rascepitel_cmd != CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_ON ) // + { + edrk.RunUnZahvatRascepitel = 0; + edrk.errors.e1.bits.NO_CONFIRM_ON_RASCEPITEL |= 1; + edrk.errors.e2.bits.ERROR_RAZBOR_SHEMA |= 1; + } + + } + + + + + +// +// if (edrk.Razbor_Mode==400 && (edrk.Status_QTV_Ok==0) +// && edrk.RunUnZahvatRascepitel && edrk.Status_Rascepitel_Ok==1) +// { +// // , +// // +// if (optical_read_data.data.cmd.bit.rascepitel_cmd != CODE_RASCEPITEL_CMD_ENABLE_ON_AND_THIS_ON ) // 01 - , +// { +//// edrk.Run_Rascepitel = 0; +// edrk.RunUnZahvatRascepitel = 0; +// edrk.errors.e1.bits.NO_CONFIRM_ON_RASCEPITEL |= 1; +// edrk.errors.e2.bits.ERROR_RAZBOR_SHEMA |= 1; +// +// } +// } +// + + + + + if (edrk.Razbor_Mode==600 && edrk.Status_QTV_Ok==0 + && edrk.Run_Rascepitel == 0 + && edrk.Status_Rascepitel_Ok==1 ) + { +#if(RASCEPITEL_MANUAL_ALWAYS_ON==1) + +#else + // ! + if (edrk.Run_Rascepitel_from_RS==0) // rs232? + { + edrk.errors.e6.bits.RASCEPITEL_ERROR_NOT_ANSWER |= 1; + edrk.errors.e2.bits.ERROR_RAZBOR_SHEMA |= 1; + } +#endif + } + +#if(RASCEPITEL_MANUAL_ALWAYS_ON==1) + + edrk.RazborNotFinish = 0; + edrk.RunUnZahvatRascepitel = 0; + edrk.Razbor_Mode=650; // + + +#else + + // , , + if (edrk.Run_Rascepitel==0 && edrk.Razbor_Mode>20 && edrk.Status_QTV_Ok==0 && (edrk.Status_Rascepitel_Ok==0 || edrk.Run_Rascepitel_from_RS==1) ) + { + edrk.RazborNotFinish = 0; + edrk.RunUnZahvatRascepitel = 0; + edrk.Razbor_Mode=650; // + } +#endif + +// edrk.Run_Rascepitel = 0; + + if (edrk.Razbor_Mode>650) + { + time_wait_razbor = 0; + } + else + edrk.Razbor_Mode++; + + } + + + if (edrk.errors.e7.bits.ERROR_SBOR_SHEMA) + { + // + edrk.AutoStartPump = 0; + edrk.Sbor_Mode = 0; + edrk.Run_Pred_Zaryad = 0; + edrk.time_wait_sbor = 0; + edrk.Zaryad_OK = 0; + edrk.Run_QTV = 0; + edrk.Run_UMP = 0; + edrk.SborFinishOk = 0; + edrk.RunZahvatRascepitel = 0; +// edrk.Run_Rascepitel = 0; // , ???? + + } + + + ////////////////////////////////////// + ////////////////////////////////////// + + edrk.Status_Charge = zaryad_on_off(edrk.Run_Pred_Zaryad); + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_UMP]==1 || edrk.Status_Ready.bits.ImitationReady2) + { + edrk.Status_UMP_Ok = edrk.Run_UMP; + edrk.Zaryad_UMP_Ok = 1; + edrk.to_shema.bits.UMP_ON_OFF = 0; + } + else + { + edrk.Status_UMP_Ok = ump_on_off(edrk.Run_UMP); + edrk.Zaryad_UMP_Ok = detect_zaryad_ump(); + } + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_DISABLE_ON_QTV]==1 || edrk.Status_Ready.bits.ImitationReady2) + { + edrk.Status_QTV_Ok = edrk.Run_QTV; + edrk.to_shema.bits.QTV_ON_OFF = 0; + edrk.to_shema.bits.QTV_ON = 0; + } + else + edrk.Status_QTV_Ok = qtv_on_off(edrk.Run_QTV); + + rascepitel_on_off ( edrk.Run_Rascepitel || edrk.Run_Rascepitel_from_RS, + &edrk.Status_Perehod_Rascepitel, + &edrk.Status_Rascepitel_Ok, + &edrk.Final_Status_Rascepitel + ); + + + ////////////////////////////////////// + ////////////////////////////////////// + + + + + + + ////////////////////////////////////// + ////////////////////////////////////// + + + if (control_station.active_array_cmd[CONTROL_STATION_CMD_MANUAL_DISCHARGE]==1 && edrk.SborFinishOk==0) + edrk.ManualDischarge = 1; + else + edrk.ManualDischarge = 0; + + if (allow_discharge && edrk.SborFinishOk == 0) + { + edrk.Discharge = 1; + allow_discharge = 0; + } + + + if ( edrk.Zaryad_OK == 1 && edrk.Status_QTV_Ok==1 && edrk.Status_Rascepitel_Ok) + edrk.Status_Ready.bits.ready7 = 1; + else + edrk.Status_Ready.bits.ready7 = 0; + +// if (edrk.StatusPumpFanAll) +// edrk.Status_Ready.bits.ready1 = 1; +// else +// edrk.Status_Ready.bits.ready1 = 0; + + if (edrk.Run_Pred_Zaryad) + edrk.Status_Ready.bits.ready2 = 1; + else + edrk.Status_Ready.bits.ready2 = 0; + + if (edrk.Zaryad_OK) + edrk.Status_Ready.bits.ready3 = 1; + else + edrk.Status_Ready.bits.ready3 = 0; + + if (edrk.Status_QTV_Ok) + edrk.Status_Ready.bits.ready4 = 1; + else + edrk.Status_Ready.bits.ready4 = 0; + + if (edrk.SborFinishOk || edrk.Status_Ready.bits.ImitationReady2==1) + edrk.Status_Ready.bits.ready5 = 1; + else + edrk.Status_Ready.bits.ready5 = 0; + + if (edrk.ms.ready3 || edrk.ms.another_bs_maybe_on==0) + edrk.Status_Ready.bits.ready6 = 1; + else + edrk.Status_Ready.bits.ready6 = 0; + + + if (edrk.Status_Ready.bits.ready5==1 && edrk.Status_Ready.bits.ready6==1 && edrk.Status_Ready.bits.MasterSlaveActive) + { + if (edrk.Status_Ready.bits.ImitationReady2) + edrk.Status_Ready.bits.preImitationReady2 = 1; + edrk.Status_Ready.bits.ready_final = 1; + } + else + { + edrk.Status_Ready.bits.ready_final = 0; + edrk.Status_Ready.bits.preImitationReady2 = 0; + } + + if (edrk.Status_Ready.bits.ready_final && prev_ready_final==0) + edrk.count_sbor++; + + prev_ready_final = edrk.Status_Ready.bits.ready_final; + + return (edrk.Sbor_Mode); +} + + + + + +unsigned int imit_signals_rascepitel(unsigned int *counter, unsigned int max_pause, unsigned int s, unsigned int cmd_clear) +{ + if (cmd_clear==1) + { + (*counter) = 0; + return 0; + } + + if (s) + { + if ((*counter)>=max_pause) + return 1; + else + (*counter)++; + + return 0; + } + + if (s==0) + { + if ((*counter)==0) + return 0; + else + (*counter)--; + + return 1; + } + return 0; +} + + +#define TIME_WAIT_OFF_BLOCK_KEY 100 +void auto_block_key_on_off(void) +{ + static unsigned int count_err = TIME_WAIT_OFF_BLOCK_KEY; + + if (edrk.SumSbor && edrk.enter_to_pump_stage) + { + edrk.Status_Ready.bits.Batt = 1; + edrk.to_ing.bits.BLOCK_KEY_OFF = 0; + count_err = 0; + } + + if (filter.iqU_1_long >= U_LEVEL_ON_BLOCK_KEY || filter.iqU_2_long >= U_LEVEL_ON_BLOCK_KEY) + { + edrk.Status_Ready.bits.Batt = 1; + edrk.to_ing.bits.BLOCK_KEY_OFF = 0; + count_err = 0; + } + + if (filter.iqU_1_long <= U_LEVEL_OFF_BLOCK_KEY && filter.iqU_2_long <= U_LEVEL_OFF_BLOCK_KEY && edrk.SumSbor==0) + { + if (pause_detect_error(&count_err,TIME_WAIT_OFF_BLOCK_KEY,1)) + { + edrk.to_ing.bits.BLOCK_KEY_OFF = 1; + edrk.Status_Ready.bits.Batt = 0; + } + } + else + count_err = 0; + + +} + + +/////////////////////////////////////////////// + + diff --git a/Inu/Src2/551/main/sbor_shema.h b/Inu/Src2/551/main/sbor_shema.h new file mode 100644 index 0000000..fdde9ff --- /dev/null +++ b/Inu/Src2/551/main/sbor_shema.h @@ -0,0 +1,24 @@ +/* + * sbor_shema.h + * + * Created on: 18 . 2021 . + * Author: stud + */ + +#ifndef SRC_MAIN_SBOR_SHEMA_H_ +#define SRC_MAIN_SBOR_SHEMA_H_ + + +#define U_LEVEL_ON_BLOCK_KEY 559240 // 100V +#define U_LEVEL_OFF_BLOCK_KEY 279620 // 50V + +unsigned int sbor_shema(int mode); +void rascepitel_on_off(unsigned int flag, int *status_perehod, int *status_on_off, int *final_status_on_off); +void auto_block_key_on_off(void); + +unsigned int imit_signals_rascepitel(unsigned int *counter, unsigned int max_pause, unsigned int s, unsigned int cmd_clear); +void set_status_pump_fan(void); + + + +#endif /* SRC_MAIN_SBOR_SHEMA_H_ */ diff --git a/Inu/Src2/551/main/sim_model.c b/Inu/Src2/551/main/sim_model.c new file mode 100644 index 0000000..a84fa72 --- /dev/null +++ b/Inu/Src2/551/main/sim_model.c @@ -0,0 +1,222 @@ +/* + * sim_model.c + * + * Created on: 30 . 2024 . + * Author: yura + */ + +#if (_SIMULATE_AC==1) + +#ifdef __TI_COMPILER_VERSION__ +#pragma SET_DATA_SECTION(".slow_vars") +#endif + +//#include "math.h" + + +#include "V_MotorModel.h" +//#include "V_MotorParams.h" +//#include +#include "IQmathLib.h" +//#include "main.h" + +#include "v_pwm24_v2.h" +#include "edrk_main.h" +#include "params_norma.h" +#include "adc_tools.h" +#include "filter_v1.h" +#include "mathlib.h" +#include "v_rotor_22220.h" + +// +//#pragma DATA_SECTION(sim_model, ".slow_vars") +TMotorModel sim_model = MOTOR_MODEL_DEFAULTS; + + + +void sim_model_init(void) +{ + + //model.motorInternals.udc = 540; // + + sim_model.motorInternals.udc = 540; // + sim_model.tpr = svgen_pwm24_1.Tclosed_high;//450; // + sim_model.cmpr0 = svgen_pwm24_1.Tclosed_high/2; + sim_model.cmpr1 = svgen_pwm24_1.Tclosed_high/2; + sim_model.cmpr2 = svgen_pwm24_1.Tclosed_high/2; + sim_model.cmpr3 = svgen_pwm24_1.Tclosed_high/2; + + + sim_model.MotorParametersNum = 10;// + sim_model.dt = 0;//_IQ4mpy(_IQ4(150 / 4), pwm.DeadBand >> 20) >> 4; // + + // + sim_model.Init(&sim_model); // + + + + sim_model.Init(&sim_model); + +} + +void sim_model_execute(void) +{ + // + sim_model.cmpr0 = svgen_pwm24_1.Ta_imp/2 + svgen_pwm24_1.Tclosed_high/2;//PWM0->CMPA_bit.CMPA; + sim_model.cmpr1 = svgen_pwm24_1.Tb_imp/2 + svgen_pwm24_1.Tclosed_high/2;//PWM1->CMPA_bit.CMPA; + sim_model.cmpr2 = svgen_pwm24_1.Tc_imp/2 + svgen_pwm24_1.Tclosed_high/2;;//PWM2->CMPA_bit.CMPA; + + sim_model.InvertorEna = edrk.Go;// + + // + sim_model.Execute(&sim_model); + +} + + +void calc_norm_ADC_0_sim(int run_norma) +{ + _iq a1,a2,a3; + +#if (1) + +#if (_FLOOR6) + analog.iqU_1 = _IQ(sim_model.motorInternals.udc/NORMA_ACP/2.0);// iq_norm_ADC[0][0] - analog_zero.iqU_1 + analog.iqU_1_imit; + analog.iqU_2 = analog.iqU_1;//iq_norm_ADC[0][1] - analog_zero.iqU_2 + analog.iqU_1_imit; +#else + analog.iqU_1 = iq_norm_ADC[0][0] - analog_zero.iqU_1; + analog.iqU_2 = iq_norm_ADC[0][1] - analog_zero.iqU_2; +#endif + + analog.iqIu_1 = _IQ(sim_model.motorInternals.isPhaseA/NORMA_ACP/2.0); + analog.iqIv_1 = _IQ(sim_model.motorInternals.isPhaseB/NORMA_ACP/2.0); + analog.iqIw_1 = _IQ(sim_model.motorInternals.isPhaseC/NORMA_ACP/2.0); + + analog.iqIu_2 = analog.iqIu_1; + analog.iqIv_2 = analog.iqIv_1; + analog.iqIw_2 = analog.iqIw_1; + + analog.iqIin_1 = 0;//_IQ(sim_model.motorInternals.power/sim_model.motorInternals.udc/NORMA_ACP/2.0); //-iq_norm_ADC[0][9]; // + analog.iqIin_2 = analog.iqIin_1;//-iq_norm_ADC[0][9]; // + + analog.iqUin_A1B1 = 0;//iq_norm_ADC[0][10]; + +// 23550.1 - +// 23550.1 + + analog.iqUin_B1C1 = 0;//iq_norm_ADC[0][11]; // 23550.1 + analog.iqUin_A2B2 = 0;//iq_norm_ADC[0][12]; // 23550.1 + +// 23550.3 bs1 bs2 + +// analog.iqUin_B1C1 = iq_norm_ADC[0][12]; // 23550.3 +// analog.iqUin_A2B2 = iq_norm_ADC[0][11]; // 23550.3 +// + analog.iqUin_B2C2 = 0;//iq_norm_ADC[0][13]; + + analog.iqIbreak_1 = 0;//iq_norm_ADC[0][14]; + analog.iqIbreak_2 = 0;//iq_norm_ADC[0][15]; + +#else + analog.iqU_1 = analog.iqIu_1 = analog.iqIu_2 = analog.iqIv_1 = analog.iqIv_2 = + analog.iqIw_1 = analog.iqIw_2 = analog.iqIin_1 = analog.iqIin_2 = analog.iqUin_A1B1 = + analog.iqUin_B1C1 = analog.iqUin_A2B2 = analog.iqUin_B2C2 = analog.iqIbreak_1 = analog.iqIbreak_2 + = 0; +#endif + + analog.iqUin_C1A1 = -(analog.iqUin_A1B1 + analog.iqUin_B1C1); + analog.iqUin_C2A2 = -(analog.iqUin_A2B2 + analog.iqUin_B2C2); + + + + filter.iqU_1_long = exp_regul_iq(koef_Uzpt_long_filter, filter.iqU_1_long, analog.iqU_1); + filter.iqU_2_long = exp_regul_iq(koef_Uzpt_long_filter, filter.iqU_2_long, analog.iqU_2); + + +// analog.iqU_1_fast = filter_U1_3point(analog.iqU_1_fast); + filter.iqU_1_fast = exp_regul_iq(koef_Uzpt_fast_filter, filter.iqU_1_fast, analog.iqU_1); + filter.iqU_2_fast = exp_regul_iq(koef_Uzpt_fast_filter, filter.iqU_2_fast, analog.iqU_2); + + +// filter.iqUzpt_2_2_fast = exp_regul_iq(koef_Uzpt_fast_filter, filter.iqUzpt_2_2_fast, analog.iqUzpt_2_2); + + + +//15 + + + analog.iqIm_1 = im_calc(analog.iqIu_1, analog.iqIv_1, analog.iqIw_1); + analog.iqIm_2 = im_calc(analog.iqIu_2, analog.iqIv_2, analog.iqIw_2); + + analog.iqIu = analog.iqIu_1+analog.iqIu_2; + analog.iqIv = analog.iqIv_1+analog.iqIv_2; + analog.iqIw = analog.iqIw_1+analog.iqIw_2; + + analog.iqIm = im_calc(analog.iqIu, analog.iqIv, analog.iqIw); + + + analog.iqIin_sum = analog.iqIin_1+analog.iqIin_2; + +// analog.iqIm_3 = im_calc(analog.iqIa1_1_fir_n+analog.iqIa2_1_fir_n, analog.iqIb1_1_fir_n+analog.iqIb2_1_fir_n, analog.iqIc1_1_fir_n+analog.iqIc2_1_fir_n); + + analog.iqUin_m1 = im_calc(analog.iqUin_A1B1, analog.iqUin_B1C1, analog.iqUin_C1A1); + analog.iqUin_m2 = im_calc(analog.iqUin_A2B2, analog.iqUin_B2C2, analog.iqUin_C2A2); + +// analog.iqUin_m2 = im_calc(analog.UinA2, analog.UinB2, analog.UinC2); + + filter.iqUin_m1 = exp_regul_iq(koef_Uin_filter, filter.iqUin_m1, analog.iqUin_m1); + filter.iqUin_m2 = exp_regul_iq(koef_Uin_filter, filter.iqUin_m2, analog.iqUin_m2); + + + +// i_led1_on_off(0); +// i_led1_on_off(1); + +//1 + + filter.iqIm_1 = exp_regul_iq(koef_Im_filter, filter.iqIm_1, analog.iqIm_1); + filter.iqIm_2 = exp_regul_iq(koef_Im_filter, filter.iqIm_2, analog.iqIm_2); + filter.iqIm = exp_regul_iq(koef_Im_filter, filter.iqIm, analog.iqIm); + + filter.iqIin_sum = exp_regul_iq(koef_Im_filter, filter.iqIin_sum, analog.iqIin_sum); + +//3 +// filter_batter2_Iin.InpVarCurr = (analog.iqIin_1)-ZERO_I_IN; + // filter_batter2_Iin.calc(&filter_batter2_Iin); + +// filter.iqIin = _IQmpy(filter_batter2_Iin.Out,_IQ_09); + + + filter.iqIin_1 = exp_regul_iq(koef_Im_filter, filter.iqIin_1, analog.iqIin_1); + filter.iqIin_2 = exp_regul_iq(koef_Im_filter, filter.iqIin_2, analog.iqIin_2); + + a1 = analog.iqU_1+analog.iqU_2; + a2 = analog.iqIin_1; + a3 = _IQmpy(a1,a2); + analog.PowerScalar = a3; +// filter.Power = analog.iqU_1+analog.iqU_2; + filter.PowerScalar = exp_regul_iq(koef_Power_filter, filter.PowerScalar, analog.PowerScalar); + filter.PowerScalarFilter2 = exp_regul_iq(koef_Power_filter2, filter.PowerScalarFilter2, filter.PowerScalar); + +} + + + +void calc_rotors_sim(void) +{ + rotor_22220.direct_rotor = 1; + rotor_22220.iqF = _IQ(sim_model.motorInternals.omega_rpm/60.0/NORMA_FROTOR); + + + rotor_22220.iqFout = exp_regul_iq(koef_Wout_filter, rotor_22220.iqFout, rotor_22220.iqF); + rotor_22220.iqFlong = exp_regul_iq(koef_Wout_filter_long, rotor_22220.iqFlong, rotor_22220.iqF); + +} + + + +//#ifdef __TI_COMPILER_VERSION__ +//#pragma RESET_DATA_SECTION +//#endif + +#endif diff --git a/Inu/Src2/551/main/sim_model.h b/Inu/Src2/551/main/sim_model.h new file mode 100644 index 0000000..9a27c91 --- /dev/null +++ b/Inu/Src2/551/main/sim_model.h @@ -0,0 +1,21 @@ +/* + * sim_model.h + * + * Created on: 30 . 2024 . + * Author: yura + */ + +#ifndef SRC_MAIN_SIM_MODEL_H_ +#define SRC_MAIN_SIM_MODEL_H_ + +#include "V_MotorModel.h" + +void sim_model_init(void); +void sim_model_execute(void); +void calc_norm_ADC_0_sim(int run_norma); +void calc_rotors_sim(void); + + +extern TMotorModel sim_model; + +#endif /* SRC_MAIN_SIM_MODEL_H_ */ diff --git a/Inu/Src2/551/main/sync_tools.c b/Inu/Src2/551/main/sync_tools.c new file mode 100644 index 0000000..ee9ee9d --- /dev/null +++ b/Inu/Src2/551/main/sync_tools.c @@ -0,0 +1,520 @@ +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File + +#include +#include +#include + +#include "big_dsp_module.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "Spartan2E_Functions.h" +#include "TuneUpPlane.h" +#include "pwm_test_lines.h" +#include "xp_write_xpwm_time.h" +#include "profile_interrupt.h" + +#include "edrk_main.h" +#define SIZE_SYNC_BUF 20 + +//#pragma DATA_SECTION(logbuf_sync1,".fa"); +unsigned int logbuf_sync1[SIZE_SYNC_BUF]; +unsigned int c_logbuf_sync1=0; + +//unsigned int capnum0; +//unsigned int capnum1; +//unsigned int capnum2; +//unsigned int capnum3; + +int delta_capnum = 0; +int delta_error = 0; +//int level_find_sync_zero = LEVEL_FIND_SYNC_ZERO; +unsigned int temp; + +unsigned int count_error_sync = 0; + +unsigned int count_timeout_sync = 0; +//unsigned int enable_profile_led1_sync = 1; +//unsigned int enable_profile_led2_sync = 0; + +SYNC_TOOLS_DATA sync_data=SYNC_TOOLS_DATA_DEFAULT; + + +#pragma CODE_SECTION(calculate_sync_detected,".fast_run2"); +void calculate_sync_detected(void) +{ + + + +// if (capnum0 > 1000) { +// return; +// } +// sync_data.level_find_sync_zero = LEVEL_FIND_SYNC_ZERO; + + delta_capnum = sync_data.capnum0 - sync_data.capnum1; + + if (delta_capnum > 0) // + { + sync_data.pwm_freq_plus_minus_zero = -1;//1; + + if (count_error_sync < MAX_COUNT_ERROR_SYNC) { + count_error_sync++; + count_error_sync++; + count_error_sync++; + } else + sync_data.local_flag_sync_1_2 = 0; + } + else + if (delta_capnum < 0) // + { + + if (sync_data.capnum0 > sync_data.level_find_sync_zero) + { + delta_error = sync_data.capnum0 - sync_data.level_find_sync_zero; + + if (delta_error > 50) { + if (count_error_sync < MAX_COUNT_ERROR_SYNC) { + count_error_sync++; + count_error_sync++; + count_error_sync++; + } else + sync_data.local_flag_sync_1_2 = 0; + } else { + if (count_error_sync > 0) { + count_error_sync--; + } + if (count_error_sync == 0) + sync_data.local_flag_sync_1_2 = 1; + } + sync_data.pwm_freq_plus_minus_zero = 1; + } + else + if (sync_data.capnum0 < sync_data.level_find_sync_zero) + { + + delta_error = sync_data.level_find_sync_zero - sync_data.capnum0; + + if (delta_error > 50) { + if (count_error_sync < MAX_COUNT_ERROR_SYNC) { + count_error_sync++; + count_error_sync++; + count_error_sync++; + } else + sync_data.local_flag_sync_1_2 = 0; + } else { + if (count_error_sync > 0) { + count_error_sync--; + } + if (count_error_sync == 0) + sync_data.local_flag_sync_1_2 = 1; + } + + sync_data.pwm_freq_plus_minus_zero = -1; + + } + else + { + sync_data.pwm_freq_plus_minus_zero = 0; + sync_data.local_flag_sync_1_2 = 1; + count_error_sync = 0; + } + } else + sync_data.pwm_freq_plus_minus_zero = 0; + + sync_data.delta_error_sync = delta_error; + sync_data.delta_capnum = sync_data.capnum0 - sync_data.level_find_sync_zero; //delta_capnum; + sync_data.count_error_sync = count_error_sync; + + +} + + +#pragma CODE_SECTION(sync_detected,".fast_run2"); +void sync_detected(void) +{ + +#if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) + PWM_LINES_TK_18_ON; +#endif + + sync_data.latch_interrupt = 1; + // stop_sync_interrupt(); + + + // i_led2_on_off(1); + + // //Enable more interrupts from this capture + // EvbRegs.EVBIMRC.bit.CAP6INT = 0; + + // if (edrk.disable_interrupt_sync==0) + + +// WriteMemory(ADR_SAW_REQUEST, 0x8000); +// sync_data.capnum0 = ReadMemory(ADR_SAW_VALUE); + +// WriteMemory(ADR_SAW_REQUEST, 0x8000); +// sync_data.capnum0 = ReadMemory(ADR_SAW_VALUE); + + // pause_1000(1); + + WriteMemory(ADR_SAW_REQUEST, 0x8000); + sync_data.capnum1 = ReadMemory(ADR_SAW_VALUE); + + WriteMemory(ADR_SAW_REQUEST, 0x8000); + sync_data.capnum1 = ReadMemory(ADR_SAW_VALUE); + + sync_data.count_timeout_sync = 0; + sync_data.timeout_sync_signal = 0; + + logbuf_sync1[c_logbuf_sync1++] = sync_data.capnum0; +// logbuf_sync1[c_logbuf_sync1++] = sync_data.capnum1; + + if (c_logbuf_sync1==SIZE_SYNC_BUF) + c_logbuf_sync1=0; + + + if (sync_data.count_pause_ready < MAX_COUNT_PAUSE_READY) { + sync_data.count_pause_ready++; + sync_data.count_pause_ready++; + } else + sync_data.sync_ready = 1; + +//////////////////////////////////// + + // calculate_sync_detected(); + + + +// sync_data.capnum0 = capnum0; + + + + // + // stop_sync_interrupt(); + // EvbRegs.EVBIFRC.all = BIT2; + // + + + // // Acknowledge interrupt to receive more interrupts from PIE group 5 + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + // if (edrk.disable_interrupt_sync==0) + // { + //// //Enable more interrupts from this capture + //// EvbRegs.EVBIMRC.bit.CAP6INT = 1; + //// + //// //use mask to clear EVAIFRA register + //// EvbRegs.EVBIFRC.bit.CAP6INT = 1; + // } + + //Enable more interrupts from this capture +// EvbRegs.EVBIMRC.bit.CAP6INT = 1; + + //use mask to clear EVAIFRA register +// EvbRegs.EVBIFRC.bit.CAP6INT = 1; + + + + + // DINT; + // PieCtrlRegs.PIEIER5.all = TempPIEIER; + + // return; + + + + // IER &= ~(M_INT5); + + //Enable more interrupts from this capture + // EvbRegs.EVBIMRC.bit.CAP6INT = 1; + + // Note: To be safe, use a mask value to write to the entire + // EVAIFRA register. Writing to one bit will cause a read-modify-write + // operation that may have the result of writing 1's to clear + // bits other then those intended. + //use mask to clear EVAIFRA register + // EvbRegs.EVBIFRC.bit.CAP6INT = 1; + // EvbRegs.EVBIFRC.all = BIT2; + + // IER &= ~(M_INT5); + + + // asm(" NOP;"); + + // i_led2_on_off(0); + + + // start_sync_interrupt(); + // EvbRegs.EVBIMRC.bit.CAP6INT = 1; + // Clear CAPINT6 interrupt flag + + // Acknowledge interrupt to receive more interrupts from PIE group 5 + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + + sync_data.count_interrupts++; + +#if(_ENABLE_PWM_LINES_FOR_TESTS_SYNC) + PWM_LINES_TK_18_OFF; +#endif + +} + + +//static long k_3=50; + +#pragma CODE_SECTION(Sync_handler,".fast_run2"); +interrupt void Sync_handler(void) { + + // Set interrupt priority: + volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER5.all; + IER |= M_INT5; + IER &= MINT5; // Set "global" priority + PieCtrlRegs.PIEIER5.all &= MG57; // Set "group" priority + PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts + + WriteMemory(ADR_SAW_REQUEST, 0x8000); + sync_data.capnum0 = ReadMemory(ADR_SAW_VALUE); + + stop_sync_interrupt_local(); // , , . + + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.sync) + i_led1_on_off_special(1); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.sync) + i_led2_on_off_special(1); +#endif + + EINT; + +// i_led2_on_off(1); + + // Insert ISR Code here....... + sync_detected(); +// pause_1000(k_3); + // Next line for debug only (remove after inserting ISR Code): + //ESTOP0; + +// i_led2_on_off(0); + + // Enable more interrupts from this timer +// EvbRegs.EVBIMRC.bit.CAP6INT = 1; + // Note: To be safe, use a mask value to write to the entire + // EVBIFRA register. Writing to one bit will cause a read-modify-write + // operation that may have the result of writing 1's to clear + // bits other then those intended. + EvbRegs.EVBIFRC.all = BIT2; + // Acknowledge interrupt to recieve more interrupts from PIE group 5 +// PieCtrlRegs.PIEACK.all |= PIEACK_GROUP5; + + // Restore registers saved: + DINT; + PieCtrlRegs.PIEIER5.all = TempPIEIER; + +#if (_ENABLE_INTERRUPT_PROFILE_LED1) + if (profile_interrupt.for_led1.bits.sync) + i_led1_on_off_special(0); +#endif +#if (_ENABLE_INTERRUPT_PROFILE_LED2) + if (profile_interrupt.for_led2.bits.sync) + i_led2_on_off_special(0); +#endif + + +} + +void setup_sync_int(void) { + +// return; + +// EALLOW; + + if (edrk.flag_second_PCH==1) + sync_data.level_find_sync_zero = xpwm_time.pwm_tics+5; + else + sync_data.level_find_sync_zero = LEVEL_FIND_SYNC_ZERO; + + sync_data.timeout_sync_signal = 0; + sync_data.count_timeout_sync = 0; + +// sync_data.what_main_pch = 1; // +// sync_data.what_main_pch = 2; // + sync_data.what_main_pch = 0; // + + + +///////////////////////////////////////////// + +// EvbRegs.EVBIFRC.bit.CAP6INT = 1; //Resets flag EVB Interrupt Flag Register + EvbRegs.EVBIFRC.all = BIT2; //Resets flag EVB Interrupt Flag Register + EvbRegs.EVBIMRC.bit.CAP6INT = 0; //1 //SET flag EVB Interrupt Mask Register C + // CAP6INT ENABLE + //0 Disable + //1 Enable + + +///////////////////////////////////////////// + EvbRegs.T4PR = 0xFFFF; //Set timer period + EvbRegs.T4CNT = 0; // Clear timer counter + + EvbRegs.T4CON.all = 0; // Disable timer + EvbRegs.T4CON.bit.FREE = 1; // FREE/SOFT, 00 = stop immediately on emulator suspend + EvbRegs.T4CON.bit.SOFT = 0; + EvbRegs.T4CON.bit.TMODE = 2; //TMODEx, 10 = continuous-up count mode + EvbRegs.T4CON.bit.TPS = 0; //TPSx, 111 = x/1 prescaler + EvbRegs.T4CON.bit.TENABLE = 0; // TENABLE, 1 = enable timer + EvbRegs.T4CON.bit.TCLKS10 = 0; //TCLKS, 00 = HSPCLK is clock source + EvbRegs.T4CON.bit.TCLD10 = 0; //Timer compare register reload condition, 00 When counter is 0 + EvbRegs.T4CON.bit.TECMPR = 1; // TECMPR, 1 = Enable timer compare operation + EvbRegs.T4CON.bit.SET3PR = 0; // SELT3PR: 0 - Use own period register + + +//////////////////////////////////////////////////// + EvbRegs.CAPCONB.all = 0; // Clear + + EvbRegs.CAPCONB.bit.CAP6EDGE = 2; //3:2 Edge Detection for Unit 6 + //Edge detection control for Capture Unit 6. +// 00 No detection +// 01 Detects rising edge +// 10 Detects falling edge +// 11 Detects both edges + + EvbRegs.CAPCONB.bit.CAP6TSEL = 0; // GP Timer selection for Unit 6 +// GP timer selection for Capture Units 4 and 5 +// 0 Selects GP timer 4 +// 1 Selects GP timer 3 + EvbRegs.CAPFIFOB.bit.CAP6FIFO = 0; //CAP6 FIFO status + EvbRegs.CAPCONB.bit.CAP6EN = 1; //Enables Capture Unit 6 +///////////////////////////////////////// + + + EALLOW; + PieVectTable.CAPINT6 = &Sync_handler; //?CAP????????????????? + EDIS; + + + PieCtrlRegs.PIEIER5.bit.INTx7 = 1; + + + +} + +void start_sync_interrupt(void) +{ + EvbRegs.EVBIFRC.all = BIT2; //Resets flag EVB Interrupt Flag Register + + IER |= M_INT5; // @suppress("Symbol is not resolved") +// PieCtrlRegs.PIEIER5.bit.INTx7 = 1; + + EvbRegs.EVBIMRC.bit.CAP6INT = 1; //SET flag EVB Interrupt Mask Register C + // //use mask to clear EVAIFRA register +// PieCtrlRegs.PIEACK.all |= PIEACK_GROUP5; + sync_data.latch_interrupt = 0; + sync_data.enabled_interrupt = 1; + +} + +void stop_sync_interrupt(void) +{ + sync_data.latch_interrupt = 0; + sync_data.enabled_interrupt = 0; + + IER &= ~(M_INT5); // @suppress("Symbol is not resolved") +// PieCtrlRegs.PIEIER5.bit.INTx7 = 0; + EvbRegs.EVBIMRC.bit.CAP6INT = 0; //SET flag EVB Interrupt Mask Register C + EvbRegs.EVBIFRC.all = BIT2; //Resets flag EVB Interrupt Flag Register +// PieCtrlRegs.PIEACK.all |= PIEACK_GROUP5; +} + +void stop_sync_interrupt_local(void) +{ + sync_data.latch_interrupt = 0; + + IER &= ~(M_INT5); // @suppress("Symbol is not resolved") + EvbRegs.EVBIMRC.bit.CAP6INT = 0; //SET flag EVB Interrupt Mask Register C + EvbRegs.EVBIFRC.all = BIT2; //Resets flag EVB Interrupt Flag Register +} + + +void setup_sync_line(void) { + + // output + EALLOW; + GpioMuxRegs.GPBMUX.bit.TCLKINB_GPIOB12 = 0; + GpioMuxRegs.GPBDIR.bit.GPIOB12 = 1; + EDIS; + + //input + EALLOW; + GpioMuxRegs.GPBMUX.bit.CAP6QI2_GPIOB10 = 1;// Configure as CAP6 +// GpioMuxRegs.GPBDIR.bit.GPIOB10 = 1; + EDIS; + +} + +#pragma CODE_SECTION(sync_inc_error,".fast_run"); +void sync_inc_error(void) +{ + + + if (sync_data.count_pause_ready > 0) { + sync_data.count_pause_ready--; + } else + sync_data.sync_ready = 0; + + + if (sync_data.count_timeout_sync < MAX_COUNT_TIMEOUT_SYNC) + { + sync_data.count_timeout_sync++; + } + else + { + sync_data.timeout_sync_signal = 1; + sync_data.count_pause_ready = 0; + sync_data.local_flag_sync_1_2 = 0; + } + + + if (count_error_sync < MAX_COUNT_ERROR_SYNC) { + count_error_sync++; + } else + sync_data.local_flag_sync_1_2 = 0; +} + +void clear_sync_error(void) +{ + sync_data.count_timeout_sync = 0; + sync_data.timeout_sync_signal = 0; +} + + +int get_status_sync_line(void) +{ + return !GpioDataRegs.GPBDAT.bit.GPIOB10; +} + +//int index_sync_ar = 0; +// +// +//void write_sync_logs(void) +//{ +// static int c=0; +// return; +// +//// logbuf1[index_filter_ar]=active_rect1.Id;//EvaRegs.CMPR1;//(active_rect1.pll_Ud);//svgenDQ.Wt; +//// logbuf2[index_filter_ar]=active_rect1.Iq;//EvaRegs.CMPR2;//filter.iqU_1_long;// (active_rect1.pll_Uq);//Iq; +//// logbuf3[index_filter_ar]=EvaRegs.CMPR1;//active_rect1.SetUzpt;////(active_rect1.Tetta);//abc_to_dq.Ud; +// +// index_sync_ar++; +// if (index_sync_ar>=SIZE_SYNC_BUF) +// { +// index_sync_ar=0; +// c++; +// if (c>=10) +// c=0; +// } +// +//} diff --git a/Inu/Src2/551/main/sync_tools.h b/Inu/Src2/551/main/sync_tools.h new file mode 100644 index 0000000..e41ee87 --- /dev/null +++ b/Inu/Src2/551/main/sync_tools.h @@ -0,0 +1,113 @@ + + +#define LEVEL_FIND_SYNC_ZERO 10 //74 //24 +#define MAX_COUNT_ERROR_SYNC 100 +#define MAX_COUNT_TIMEOUT_SYNC 100 +#define MAX_COUNT_PAUSE_READY 100 + + + + + + + +typedef struct { + //Sync vals + int pwm_freq_plus_minus_zero; + int disable_sync; + int sync_ready; + unsigned int level_find_sync_zero; + + int delta_error_sync; + int delta_capnum; + int count_error_sync; + unsigned int capnum0; + unsigned int capnum1; + + int PWMcounterVal; + int local_flag_sync_1_2; + int global_flag_sync_1_2; + int timeout_sync_signal; + + unsigned int count_timeout_sync; + unsigned int count_pause_ready; + int enable_do_sync; + int latch_interrupt; + int enabled_interrupt; + unsigned int count_interrupts; + unsigned int what_main_pch; + + + +// int pzad_or_wzad; //given turns or power, depends on controlMode; +// int angle_pwm; //current rotor turns +// int iq_zad; // Iq_zadan +// union { +// struct { +// unsigned int wdog_tick :1; // 0_1_0 .. +// unsigned int statusQTV :1; //1-QTV On, QTV - off +// unsigned int master :1; // 1 -Master, 0 - not Master +// unsigned int slave :1; // 1 -Slave, 0 - not Slave +// +// unsigned int sync_1_2 :1; // 1 - yes, 0 - no +// unsigned int alarm :1; // 1 - yes, 0 - no +// unsigned int ready_cmd :2; // 00 - not ready,01-ready1,10-ready1to2, 11 -ready2 +// +// unsigned int controlMode :1; // 0 - regul turns; 1 - power +// unsigned int ready_to_go :1; // 1 - yes, 0 - no , +// unsigned int start_pwm :1; // 1 - yes, 0 - no +// unsigned int stop_pwm :1; // 1 - yes, 0 - no +// +// unsigned int pwm_status :1; // 1 -On, 0 - Off +// unsigned int err_optbus :1; // 1 - yes, 0 - no optbus +// unsigned int maybe_master :1; // 1 - yes, 0 - no Master +// unsigned int rascepitel :1; // 1 - yes, 0 - no +// +//// unsigned int leading_ready :1; //1 - second inverter ready to work or in work +//// unsigned int leading_Go :1; +// } bit; +// unsigned int all; +// } cmd; +} SYNC_TOOLS_DATA; + +#define SYNC_TOOLS_DATA_DEFAULT {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} + +extern SYNC_TOOLS_DATA sync_data; + + + + +void setup_sync_line(void); +void sync_inc_error(void); +void setup_sync_int(void); +void start_sync_interrupt(void); +void stop_sync_interrupt(void); +void stop_sync_interrupt_local(void); + + +int get_status_sync_line(void); + +void clear_sync_error(void); + +void Sync_alg(void); +void calculate_sync_detected(void); + + + + +inline void i_sync_pin_on() +{ + EALLOW; + GpioDataRegs.GPBSET.bit.GPIOB12 = 1; + EDIS; +} + + +inline void i_sync_pin_off() +{ + EALLOW; + GpioDataRegs.GPBCLEAR.bit.GPIOB12 = 1; + EDIS; +} + + diff --git a/Inu/Src2/551/main/synhro_tools.c b/Inu/Src2/551/main/synhro_tools.c new file mode 100644 index 0000000..47bbc5e --- /dev/null +++ b/Inu/Src2/551/main/synhro_tools.c @@ -0,0 +1,144 @@ +/* + * synhro_tools.c + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + + + +#include + +#include +#include +#include +#include +#include +#include +#include "IQmathLib.h" +#include "mathlib.h" +#include "optical_bus.h" +#include "sync_tools.h" + +////////////////////////////////////////////////////////// +unsigned int wait_synhro_optical_bus(void) +{ + static unsigned int cmd = 0; + static unsigned int count_wait_synhro = 0; + + +// +// switch(cmd) +// { +// 0 : if (optical_read_data.data.cmd.bit.wdog_tick == 0) +// cmd = 1; +// +// break; +// +// 1 : optical_write_data.data.cmd.bit.wdog_tick = 1; +// break; +// +// +// default: break +// } + + + + return 0; +} + +////////////////////////////////////////////////////////// +void clear_wait_synhro_optical_bus(void) +{ + + // optical_read_data.data.cmd.bit.wdog_tick = 0; + // optical_write_data.data.cmd.bit.wdog_tick = 0; + +} +////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////// +void who_select_sync_signal(void) +{ + + if (sync_data.what_main_pch) + { + if (sync_data.what_main_pch==2) + { + // !!! + if (edrk.flag_second_PCH) + sync_data.enable_do_sync = 1; + else + sync_data.enable_do_sync = 0; + return; + } + + if (sync_data.what_main_pch==1) + { + // !!! + if (edrk.flag_second_PCH) + sync_data.enable_do_sync = 0; + else + sync_data.enable_do_sync = 1; + return; + } + + } + +// if (optical_read_data.status == 1) + sync_data.global_flag_sync_1_2 = (sync_data.local_flag_sync_1_2 || optical_read_data.data.cmd.bit.sync_1_2); +// else + // sync_data.global_flag_sync_1_2 = (sync_data.local_flag_sync_1_2); + + + if (sync_data.timeout_sync_signal && optical_read_data.data.cmd.bit.sync_line_detect) + { + // , , + // . + + sync_data.enable_do_sync = 0; + + return; + } + + if (sync_data.timeout_sync_signal==0 && optical_read_data.data.cmd.bit.sync_line_detect==0) + { + // , , + // . + + sync_data.enable_do_sync = 1; + + return; + } + + if (sync_data.sync_ready && sync_data.timeout_sync_signal==0 && optical_read_data.data.cmd.bit.sync_line_detect) + { + + + if (optical_read_data.data.cmd.bit.sync_1_2 && sync_data.enable_do_sync==0) + { + // , + + } + else + if (optical_read_data.data.cmd.bit.sync_1_2 && sync_data.enable_do_sync==1) + { + // , , + + } + else + { + // , + // , + // . + if (edrk.flag_second_PCH==0) + sync_data.enable_do_sync = 1; + else + sync_data.enable_do_sync = 0; + } + return; + } + +} + +////////////////////////////////////////////////////////// + diff --git a/Inu/Src2/551/main/synhro_tools.h b/Inu/Src2/551/main/synhro_tools.h new file mode 100644 index 0000000..e6de9f1 --- /dev/null +++ b/Inu/Src2/551/main/synhro_tools.h @@ -0,0 +1,19 @@ +/* + * synhro_tools.h + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef SRC_MAIN_SYNHRO_TOOLS_H_ +#define SRC_MAIN_SYNHRO_TOOLS_H_ + +void who_select_sync_signal(void); + +void clear_wait_synhro_optical_bus(void); + +unsigned int wait_synhro_optical_bus(void); +void clear_wait_synhro_optical_bus(void); + + +#endif /* SRC_MAIN_SYNHRO_TOOLS_H_ */ diff --git a/Inu/Src2/551/main/temper_p_tools.c b/Inu/Src2/551/main/temper_p_tools.c new file mode 100644 index 0000000..c6a773a --- /dev/null +++ b/Inu/Src2/551/main/temper_p_tools.c @@ -0,0 +1,77 @@ +/* + * temper_p_tools.c + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + + + +#include + +#include +#include +#include +#include +#include +#include +#include "IQmathLib.h" +#include "mathlib.h" +#include "adc_tools.h" + +#include "temper_p_tools.h" +/////////////////////////////////////////////// +void nagrev_auto_on_off(void) +{ + //min_real_int_temper_air + +// if (edrk.temper_edrk.max_real_int_temper_waterTEMPER_NAGREF_OFF) +// edrk.to_ing.bits.NAGREV_OFF = 1; + + if (edrk.temper_edrk.min_real_int_temper_airTEMPER_NAGREF_OFF_1 || edrk.temper_edrk.max_real_int_temper_air>TEMPER_NAGREF_OFF_2) + edrk.to_ing.bits.NAGREV_OFF = 1; + +} +/////////////////////////////////////////////// + + + +//#define koef_P_Water_filter 1600000 //0.095367431640625 +void calc_p_water_edrk(void) +{ + _iq iqtain,iq_temp; + static _iq koef_P_Water_filter = _IQ (0.1/2.0); // 5 + + edrk.p_water_edrk.adc_p_water[0] = ADC_f[1][14]; + + edrk.p_water_edrk.real_p_water[0] = (_IQtoF(analog.P_Water_internal) * NORMA_ACP_P - 4.0) / 1.6; + edrk.p_water_edrk.real_int_p_water[0] = edrk.p_water_edrk.real_p_water[0] * K_P_WATER_TO_SVU; + + + iqtain = _IQ(edrk.p_water_edrk.real_p_water[0]/100.0); + iq_temp = _IQ(edrk.p_water_edrk.filter_real_p_water[0]/100.0); + + if (edrk.p_water_edrk.flag_init_filter_temp[0]==0) + { + iq_temp = iqtain; + edrk.p_water_edrk.flag_init_filter_temp[0]=1; + } + +// iq_temp_engine[i] = exp_regul_iq(koef_Temper_ENGINE_filter, iq_temp_engine[i], iqtain); + + iq_temp += _IQmpy( (iqtain-iq_temp), koef_P_Water_filter); + edrk.p_water_edrk.filter_real_p_water[0] = _IQtoF(iq_temp)*100.0; + edrk.p_water_edrk.filter_real_int_p_water[0] = edrk.p_water_edrk.filter_real_p_water[0]*K_P_WATER_TO_SVU; + + + +} + +////////////////////////////////////////////////////////// + diff --git a/Inu/Src2/551/main/temper_p_tools.h b/Inu/Src2/551/main/temper_p_tools.h new file mode 100644 index 0000000..d99cb89 --- /dev/null +++ b/Inu/Src2/551/main/temper_p_tools.h @@ -0,0 +1,22 @@ +/* + * temper_p_tools.h + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef SRC_MAIN_TEMPER_P_TOOLS_H_ +#define SRC_MAIN_TEMPER_P_TOOLS_H_ + + +#define TEMPER_NAGREF_ON_1 120 +#define TEMPER_NAGREF_ON_2 200 + +#define TEMPER_NAGREF_OFF_1 170 +#define TEMPER_NAGREF_OFF_2 250 + +void nagrev_auto_on_off(void); +void calc_p_water_edrk(void); + + +#endif /* SRC_MAIN_TEMPER_P_TOOLS_H_ */ diff --git a/Inu/Src2/551/main/tk_Test.c b/Inu/Src2/551/main/tk_Test.c new file mode 100644 index 0000000..fd5cc61 --- /dev/null +++ b/Inu/Src2/551/main/tk_Test.c @@ -0,0 +1,369 @@ + +#include <281xEvTimersInit.h> +#include +#include + +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "x_wdog.h" +#include "project.h" + +#pragma CODE_SECTION(pause_10,".fast_run"); +void pause_10(unsigned long t) +{ + unsigned long i; + + for (i = 0; i < t; i++) + { + asm(" NOP"); + } +} + + +void test_impulse(unsigned int impulse_channel,long impulse_time) +{ + i_WriteMemory(ADR_PWM_DIRECT,impulse_channel); + pause_10(impulse_time); + i_WriteMemory(ADR_PWM_DIRECT,0xffff); +} + +#pragma CODE_SECTION(test_double_impulse,".fast_run"); +void test_double_impulse(unsigned int impulse_channel_1,unsigned int impulse_channel_2,long impulse_time,long middle_impulse_time,long last_impulse_time, int soft_off_enable, int soft_on_enable) +{ + project.disable_all_interrupt(); +// i_WriteMemory(ADR_PWM_DIRECT,impulse_channel_2); +// pause_10(middle_impulse_time); + + if (soft_on_enable) + { + i_WriteMemory(ADR_PWM_DIRECT,impulse_channel_2); + pause_10(last_impulse_time); + } + + i_WriteMemory(ADR_PWM_DIRECT,impulse_channel_1); +// pause_10(impulse_time); + pause_10(impulse_time); + + + i_WriteMemory(ADR_PWM_DIRECT,impulse_channel_2); + pause_10(middle_impulse_time); + + i_WriteMemory(ADR_PWM_DIRECT, impulse_channel_1); + pause_10(last_impulse_time); + + if (soft_off_enable) + { + i_WriteMemory(ADR_PWM_DIRECT,impulse_channel_2); + pause_10(last_impulse_time); + } + + i_WriteMemory(ADR_PWM_DIRECT,0xffff); + + project.enable_all_interrupt(); +} + +void test_sin_impulse(unsigned int impulse_channel_1,unsigned int impulse_channel_2, unsigned int impulse_channel_3, long impulse_time,long middle_impulse_time) +{ + project.disable_all_interrupt(); + + i_WriteMemory(ADR_PWM_DIRECT,impulse_channel_2); + pause_10(middle_impulse_time); + + i_WriteMemory(ADR_PWM_DIRECT,impulse_channel_1); + pause_10(impulse_time); + + + i_WriteMemory(ADR_PWM_DIRECT,impulse_channel_2); + pause_10(middle_impulse_time); + + i_WriteMemory(ADR_PWM_DIRECT,impulse_channel_3); + pause_10(impulse_time); + i_WriteMemory(ADR_PWM_DIRECT,0xffff); + + project.enable_all_interrupt(); +} + + +void test_tk_ak_one_impulse(int tk0, int tk1, int tk2, int tk3, int period, int periodMiddle, int periodLast, int doubleImpulse, int sinImpulse, int soft_off_enable, int soft_on_enable) +{ + long p2 = 0, pM = 0, pL = 0; + float pf; + unsigned int tk0_0 = 0, tk0_1 = 0, tk0_2 = 0, tk0_3 = 0, tk0_4 = 0, tk0_5 = 0, tk0_6 = 0, tk0_7 = 0; + unsigned int tk1_0 = 0, tk1_1 = 0, tk1_2 = 0, tk1_3 = 0, tk1_4 = 0, tk1_5 = 0, tk1_6 = 0, tk1_7 = 0; + unsigned int tk2_0 = 0, tk2_1 = 0, tk2_2 = 0, tk2_3 = 0, tk2_4 = 0, tk2_5 = 0, tk2_6 = 0, tk2_7 = 0; + unsigned int tk3_0 = 0, tk3_1 = 0, tk3_2 = 0, tk3_3 = 0, tk3_4 = 0, tk3_5 = 0, tk3_6 = 0, tk3_7 = 0; + unsigned int break1 = 0, break2 = 0, break3 = 0, break4 = 0,key0 = 0, key1 = 0, key2 = 0, key3 = 0, key4 = 0, key5 = 0, key6 = 0, key7 = 0, key8 = 0,key9 = 0,key10 = 0,key11 = 0; + unsigned int Dkey0 = 0xffff, Dkey1 = 0xffff, Dkey2 = 0xffff; + unsigned int currentPWMMode1, currentPWMMode0, currPWMPeriod; + + + //// ////////// +#if (XPWMGEN==1) + i_WriteMemory(ADR_PWM_DRIVE_MODE, 3); +// pause_1000(100000L); + i_WriteMemory(ADR_PWM_DIRECT,0xffff); + i_WriteMemory(ADR_TK_MASK_0, 0); + +#endif + stop_eva_timer2(); + IER &= ~M_INT9; //stop CAN + //////////////////////////////////// + + if (period<=1) + period=1; + if (period>=1000) + period=1000; + pf = (float)(period) *11.724;/// 2.8328173374613003095975232198142;//(periodMiddle)*12; + p2 = pf; +// p2=(period) * 19 / 10;//(period)*12; + + if (periodMiddle<=1) + periodMiddle=1; + if (periodMiddle>=1000) + periodMiddle=1000; +// pM=(periodMiddle) * 19 / 10;//(periodMiddle)*12; + pf = (float)(periodMiddle)*11.724;// / 2.8328173374613003095975232198142;//(periodMiddle)*12; + pM = pf; + + if (periodLast<=1) + periodLast=1; + if (periodLast>=1000) + periodLast=1000; +// pM=(periodMiddle) * 19 / 10;//(periodMiddle)*12; + pf = (float)(periodLast)*11.724;// / 2.8328173374613003095975232198142;//(periodMiddle)*12; + pL = pf; + + + + tk0_0 = (tk0 >> 0) & 0x1; + tk0_1 = (tk0 >> 1) & 0x1; + tk0_2 = (tk0 >> 2) & 0x1; + tk0_3 = (tk0 >> 3) & 0x1; + tk0_4 = (tk0 >> 4) & 0x1; + tk0_5 = (tk0 >> 5) & 0x1; + tk0_6 = (tk0 >> 6) & 0x1; + tk0_7 = (tk0 >> 7) & 0x1; + + tk1_0 = (tk1 >> 0) & 0x1; + tk1_1 = (tk1 >> 1) & 0x1; + tk1_2 = (tk1 >> 2) & 0x1; + tk1_3 = (tk1 >> 3) & 0x1; + tk1_4 = (tk1 >> 4) & 0x1; + tk1_5 = (tk1 >> 5) & 0x1; + tk1_6 = (tk1 >> 6) & 0x1; + tk1_7 = (tk1 >> 7) & 0x1; + + tk2_0 = (tk2 >> 0) & 0x1; + tk2_1 = (tk2 >> 1) & 0x1; + tk2_2 = (tk2 >> 2) & 0x1; + tk2_3 = (tk2 >> 3) & 0x1; + tk2_4 = (tk2 >> 4) & 0x1; + tk2_5 = (tk2 >> 5) & 0x1; + tk2_6 = (tk2 >> 6) & 0x1; + tk2_7 = (tk2 >> 7) & 0x1; + + tk3_0 = (tk3 >> 0) & 0x1; + tk3_1 = (tk3 >> 1) & 0x1; + tk3_2 = (tk3 >> 2) & 0x1; + tk3_3 = (tk3 >> 3) & 0x1; + tk3_4 = (tk3 >> 4) & 0x1; + tk3_5 = (tk3 >> 5) & 0x1; + tk3_6 = (tk3 >> 6) & 0x1; + tk3_7 = (tk3 >> 7) & 0x1; + + if(doubleImpulse) + { + if(tk0_0 && tk0_7){ + Dkey0 = 0xfff6; + Dkey1 = 0xfff0; + } + else if(tk0_4 && tk0_3){ + Dkey0 = 0xfff9; + Dkey1 = 0xfff0; + } + else if(tk1_3 && tk0_0){ + Dkey0 = 0xffde; + Dkey1 = 0xffcc; + } + else if(tk1_0 && tk0_3){ + Dkey0 = 0xffed; + Dkey1 = 0xffcc; + } + else if(tk0_4 && tk1_3){ + Dkey0 = 0xffdb; + Dkey1 = 0xffc3; + } + else if(tk0_7 && tk1_0){ + Dkey0 = 0xffe7; + Dkey1 = 0xffc3; + }///// + else if(tk1_4 && tk2_3){ + Dkey0 = 0xFDBF; + Dkey1 = 0xFC3F; + } + else if(tk1_7 && tk2_0){ + Dkey0 = 0xFE7F; + Dkey1 = 0xFC3F; + } + else if(tk1_4 && tk2_7){ + Dkey0 = 0xF7BF; + Dkey1 = 0xF33F; + } + else if(tk1_7 && tk2_4){ + Dkey0 = 0xFB7F; + Dkey1 = 0xF33F; + } + else if(tk2_0 && tk2_7){ + Dkey0 = 0xF6FF; + Dkey1 = 0xF0FF; + } + else if(tk2_3 && tk2_4){ + Dkey0 = 0xF9FF; + Dkey1 = 0xF0FF; + } + else if (tk0_0){ + Dkey0 = 0xfffe; + Dkey1 = 0xfffc; + } + else if (tk0_3){ + Dkey0 = 0xfffd; + Dkey1 = 0xfffc; + } + else if (tk0_4){ + Dkey0 = 0xfffb; + Dkey1 = 0xfff3; + } + else if (tk0_7){ + Dkey0 = 0xfff7; + Dkey1 = 0xfff3; + } + else if (tk1_0){ + Dkey0 = 0xffef; + Dkey1 = 0xffcf; + } + else if (tk1_3){ + Dkey0 = 0xffdf; + Dkey1 = 0xffcf; + } + else if (tk1_4){ + Dkey0 = 0xffbf; + Dkey1 = 0xff3f; + } + else if (tk1_7){ + Dkey0 = 0xff7f; + Dkey1 = 0xff3f; + } + else if (tk2_0){ + Dkey0 = 0xfeff; + Dkey1 = 0xfcff; + } + else if (tk2_3){ + Dkey0 = 0xfdff; + Dkey1 = 0xfcff; + } + else if (tk2_4){ + Dkey0 = 0xfbff; + Dkey1 = 0xf3ff; + } + else if (tk2_7){ + Dkey0 = 0xf7ff; + Dkey1 = 0xf3ff; + } + + } + else if(sinImpulse) + { + if(tk0_0){ + Dkey0 = 0xfff6; + Dkey1 = 0xfff0; + Dkey2 = 0xfff9; + } + else if(tk0_7){ + Dkey0 = 0xfff9; + Dkey1 = 0xfff0; + Dkey2 = 0xfff6; + } + else if(tk1_0){ + Dkey0 = 0xffde; + Dkey1 = 0xffcc; + Dkey2 = 0xffed; + } + else if(tk0_4){ + Dkey0 = 0xffed; + Dkey1 = 0xffcc; + Dkey2 = 0xffde; + } + else if(tk1_4){ + Dkey0 = 0xffdb; + Dkey1 = 0xffc3; + Dkey2 = 0xffe7; + } + else if(tk1_7){ + Dkey0 = 0xffe7; + Dkey1 = 0xffc3; + Dkey2 = 0xffdb; + } + } + else + { + key0 = !(((tk0_0 == 1) && (tk0_1 == 1) && (tk0_2 == 0) && (tk0_3 == 0)) || + ((tk0_0 == 0) && (tk0_1 == 1) && (tk0_2 == 1) && (tk0_3 == 0))); + + key1 = !(((tk0_0 == 0) && (tk0_1 == 1) && (tk0_2 == 1) && (tk0_3 == 0)) || + ((tk0_0 == 0) && (tk0_1 == 0) && (tk0_2 == 1) && (tk0_3 == 1))); + + key2 = !(((tk0_4 == 1) && (tk0_5 == 1) && (tk0_6 == 0) && (tk0_7 == 0)) || + ((tk0_4 == 0) && (tk0_5 == 1) && (tk0_6 == 1) && (tk0_7 == 0))); + + key3 = !(((tk0_4 == 0) && (tk0_5 == 1) && (tk0_6 == 1) && (tk0_7 == 0)) || + ((tk0_4 == 0) && (tk0_5 == 0) && (tk0_6 == 1) && (tk0_7 == 1))); + + key4 = !(((tk1_0 == 1) && (tk1_1 == 1) && (tk1_2 == 0) && (tk1_3 == 0)) || + ((tk1_0 == 0) && (tk1_1 == 1) && (tk1_2 == 1) && (tk1_3 == 0))); + + key5 = !(((tk1_0 == 0) && (tk1_1 == 1) && (tk1_2 == 1) && (tk1_3 == 0)) || + ((tk1_0 == 0) && (tk1_1 == 0) && (tk1_2 == 1) && (tk1_3 == 1))); + + key6 = !(((tk1_4 == 1) && (tk1_5 == 1) && (tk1_6 == 0) && (tk1_7 == 0)) || + ((tk1_4 == 0) && (tk1_5 == 1) && (tk1_6 == 1) && (tk1_7 == 0))); + + key7 = !(((tk1_4 == 0) && (tk1_5 == 1) && (tk1_6 == 1) && (tk1_7 == 0)) || + ((tk1_4 == 0) && (tk1_5 == 0) && (tk1_6 == 1) && (tk1_7 == 1))); + + key8 = !(((tk2_0 == 1) && (tk2_1 == 1) && (tk2_2 == 0) && (tk2_3 == 0)) || + ((tk2_0 == 0) && (tk2_1 == 1) && (tk2_2 == 1) && (tk2_3 == 0))); + + key9 =!(((tk2_0 == 0) && (tk2_1 == 1) && (tk2_2 == 1) && (tk2_3 == 0)) || + ((tk2_0 == 0) && (tk2_1 == 0) && (tk2_2 == 1) && (tk2_3 == 1))); + + key10 = !(((tk2_4 == 1) && (tk2_5 == 1) && (tk2_6 == 0) && (tk2_7 == 0)) || + ((tk2_4 == 0) && (tk2_5 == 1) && (tk2_6 == 1) && (tk2_7 == 0))); + + key11 = !(((tk2_4 == 0) && (tk2_5 == 1) && (tk2_6 == 1) && (tk2_7 == 0)) || + ((tk2_4 == 0) && (tk2_5 == 0) && (tk2_6 == 1) && (tk2_7 == 1))); + + break1 = !tk3_1; + break2 = !tk3_2; + break3 = !tk3_3; + break4 = !tk3_4; + + Dkey0 &= ((break4 << 15)|(break3 << 14)|(break2 << 13)|(break1 << 12)| (key11 << 11) | (key10 << 10) | (key9 << 9) | (key8 << 8)| (key7 << 7)| (key6 << 6)| (key5 << 5)| (key4 << 4)| (key3 << 3)| (key2 << 2)| (key1 << 1)| (key0 << 0)); + + } + if(doubleImpulse) + test_double_impulse(Dkey0, Dkey1, p2, pM, pL, soft_off_enable, soft_on_enable); + else if(sinImpulse) + test_sin_impulse(Dkey0, Dkey1, Dkey2, p2, pM); + else + test_impulse(Dkey0,p2); + + // + start_eva_timer2(); + IER |= M_INT9; //start CAN +#if (XPWMGEN==1) + i_WriteMemory(ADR_PWM_DIRECT,0xffff); + i_WriteMemory(ADR_PWM_DRIVE_MODE, 0); +#endif + return; +} diff --git a/Inu/Src2/551/main/tk_Test.h b/Inu/Src2/551/main/tk_Test.h new file mode 100644 index 0000000..2a44453 --- /dev/null +++ b/Inu/Src2/551/main/tk_Test.h @@ -0,0 +1,12 @@ + +#ifndef TK_TEST_H +#define TK_TEST_H + + + +void test_tk_ak_one_impulse(int tk0, int tk1, int tk2, int tk3, int period, int periodMiddle, int periodLast, int doubleImpulse, int sinImpulse, int soft_off_enable, int soft_on_enable); +void test_double_impulse(unsigned int impulse_channel_1,unsigned int impulse_channel_2,long impulse_time,long middle_impulse_time, long last_impulse_time, int soft_off_enable, int soft_on_enable); + + +#endif + diff --git a/Inu/Src2/551/main/ukss_tools.c b/Inu/Src2/551/main/ukss_tools.c new file mode 100644 index 0000000..097fc1e --- /dev/null +++ b/Inu/Src2/551/main/ukss_tools.c @@ -0,0 +1,605 @@ +/* + * ukss_tools.c + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + + + +#include + +#include +#include +#include +#include +#include +#include +#include "IQmathLib.h" +#include "mathlib.h" +#include +#include "adc_tools.h" +#include "CAN_project.h" +#include "CAN_Setup.h" +#include "global_time.h" +#include "v_rotor.h" +#include "ukss_tools.h" +#include "control_station_project.h" +#include "control_station.h" +#include "sync_tools.h" + + +#pragma DATA_SECTION(Unites2VPU, ".slow_vars") +int Unites2VPU[SIZE_UNITS_OUT]={0}; + +#pragma DATA_SECTION(Unites2Zadat4ik, ".slow_vars") +int Unites2Zadat4ik[SIZE_UNITS_OUT]={0}; + +#pragma DATA_SECTION(Unites2BKSSD, ".slow_vars") +int Unites2BKSSD[SIZE_UNITS_OUT]={0}; + +#pragma DATA_SECTION(Unites2UMU, ".slow_vars") +int Unites2UMU[SIZE_UNITS_OUT]={0}; + + + +void edrk_clear_cmd_ukss(void) +{ + int i; + + for (i=0;i + +#include +#include +#include +#include +#include +#include +#include "IQmathLib.h" +#include "mathlib.h" +#include "CAN_Setup.h" +#include "uom_tools.h" + + +#pragma DATA_SECTION(uom_levels, ".slow_vars") +int uom_levels[9] = {0, 0, 15, 30, 45, 60, 75, 90, 100}; +#pragma DATA_SECTION(iq_uom_levels, ".slow_vars") +_iq iq_uom_levels[9] = {_IQ(1.0), _IQ(1.0), _IQ(0.85), _IQ(0.7), _IQ(0.55), _IQ(0.4), _IQ(0.25), _IQ(0.1), _IQ(0.016)}; +void update_uom(void) +{ +// int index; + static _iq max_nominal_power = _IQ(MAX_ZADANIE_LIMIT_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ)); + static _iq super_max_nominal_power = _IQ(SUPER_MAX_ZADANIE_LIMIT_POWER*1000.0/(NORMA_MZZ*NORMA_MZZ)); + + static unsigned int prev_CAN_count_cycle_input_units = 0, c_data = 0; + unsigned int cur_can_cycle; + + static FROM_ZADAT4IK zad = {0}, zad_w = {0}; + static unsigned int temp_code = 0 , temp_code1 = 0, temp_code2 = 0, temp_code3 = 0; + + + + cur_can_cycle = unites_can_setup.CAN_count_cycle_input_units[0]; + + if (prev_CAN_count_cycle_input_units != cur_can_cycle) + { + zad = edrk.from_zadat4ik; + + temp_code = (zad.bits.UOM_READY_ACTIVE & 0x1) + + (zad.bits.UOM_LIMIT_1 & 0x1) << 1 + + (zad.bits.UOM_LIMIT_2 & 0x1) << 2 + + (zad.bits.UOM_LIMIT_3 & 0x1) << 3 ; + + if (c_data == 0) + { + temp_code1 = temp_code; + c_data = 1; + } + else + if (c_data == 1) + { + temp_code2 = temp_code; + c_data = 2; + } + else + if (c_data == 2) + { + temp_code3 = temp_code; + c_data = 0; + } + + } + + prev_CAN_count_cycle_input_units = cur_can_cycle; + + if ((temp_code1 == temp_code2) && (temp_code2 == temp_code3)) + zad_w = zad; + + + edrk.from_uom.digital_line.bits.ready = zad_w.bits.UOM_READY_ACTIVE; + edrk.from_uom.digital_line.bits.level0 = zad_w.bits.UOM_LIMIT_1; + edrk.from_uom.digital_line.bits.level1 = zad_w.bits.UOM_LIMIT_2; + edrk.from_uom.digital_line.bits.level2 = zad_w.bits.UOM_LIMIT_3; + + + if (edrk.from_uom.digital_line.bits.ready && edrk.disable_uom==0) + { + edrk.from_uom.ready = 1; +//000 - 100 + if (edrk.from_uom.digital_line.bits.level0 == 0 && + edrk.from_uom.digital_line.bits.level1 == 0 && + edrk.from_uom.digital_line.bits.level2 == 0 ) + edrk.from_uom.code = 1; +//001 - 85 + if (edrk.from_uom.digital_line.bits.level0 == 1 && + edrk.from_uom.digital_line.bits.level1 == 0 && + edrk.from_uom.digital_line.bits.level2 == 0 ) + edrk.from_uom.code = 2; +//011 - 70 + if (edrk.from_uom.digital_line.bits.level0 == 1 && + edrk.from_uom.digital_line.bits.level1 == 1 && + edrk.from_uom.digital_line.bits.level2 == 0 ) + edrk.from_uom.code = 3; +//010 - 55 + if (edrk.from_uom.digital_line.bits.level0 == 0 && + edrk.from_uom.digital_line.bits.level1 == 1 && + edrk.from_uom.digital_line.bits.level2 == 0 ) + edrk.from_uom.code = 4; +//110 - 40 + if (edrk.from_uom.digital_line.bits.level0 == 0 && + edrk.from_uom.digital_line.bits.level1 == 1 && + edrk.from_uom.digital_line.bits.level2 == 1 ) + edrk.from_uom.code = 5; +//111 - 25 + if (edrk.from_uom.digital_line.bits.level0 == 1 && + edrk.from_uom.digital_line.bits.level1 == 1 && + edrk.from_uom.digital_line.bits.level2 == 1 ) + edrk.from_uom.code = 6; +//101 - 10 + if (edrk.from_uom.digital_line.bits.level0 == 1 && + edrk.from_uom.digital_line.bits.level1 == 0 && + edrk.from_uom.digital_line.bits.level2 == 1 ) + edrk.from_uom.code = 7; +//100 - 0 + if (edrk.from_uom.digital_line.bits.level0 == 0 && + edrk.from_uom.digital_line.bits.level1 == 0 && + edrk.from_uom.digital_line.bits.level2 == 1 ) + edrk.from_uom.code = 8; + } + else + { + edrk.from_uom.ready = 0; + edrk.from_uom.code = 0; + } + + edrk.from_uom.iq_level_value = iq_uom_levels[edrk.from_uom.code]; + + if (edrk.from_uom.code<=1) + edrk.from_uom.iq_level_value_kwt = super_max_nominal_power; + else + edrk.from_uom.iq_level_value_kwt = _IQmpy(max_nominal_power, + edrk.from_uom.iq_level_value); + + edrk.from_uom.level_value = uom_levels[edrk.from_uom.code]; + + + +} + +////////////////////////////////////////////////////////// diff --git a/Inu/Src2/551/main/uom_tools.h b/Inu/Src2/551/main/uom_tools.h new file mode 100644 index 0000000..134648f --- /dev/null +++ b/Inu/Src2/551/main/uom_tools.h @@ -0,0 +1,15 @@ +/* + * uom_tools.h + * + * Created on: 13 . 2024 . + * Author: Evgeniy_Sokolov + */ + +#ifndef SRC_MAIN_UOM_TOOLS_H_ +#define SRC_MAIN_UOM_TOOLS_H_ + + +void update_uom(void); + + +#endif /* SRC_MAIN_UOM_TOOLS_H_ */ diff --git a/Inu/Src2/551/main/v_pwm24_v2.c b/Inu/Src2/551/main/v_pwm24_v2.c new file mode 100644 index 0000000..147c2c9 --- /dev/null +++ b/Inu/Src2/551/main/v_pwm24_v2.c @@ -0,0 +1,948 @@ +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "IQmathLib.h" + +#include +#include +#include +#include +#include +#include + +#include "rmp_cntl_v1.h" +#include "svgen_mf.h" +#include "uf_alg_ing.h" +#include "vhzprof.h" +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" +#include "MemoryFunctions.h" +#include "Spartan2E_Adr.h" +#include "TuneUpPlane.h" +#include "x_wdog.h" +#include "xp_write_xpwm_time.h" + + + + + + + + +// xilinx (60000000 / 16 / FREQ_PWM = 3750000 / FREQ_PWM) +//#pragma DATA_SECTION(var_freq_pwm_xtics,".fast_vars1"); +//int var_freq_pwm_xtics = DEF_FREQ_PWM_XTICS; + +// xilinx +//#pragma DATA_SECTION(var_period_max_xtics,".fast_vars1"); +//int var_period_max_xtics = DEF_FREQ_PWM_XTICS - DEF_PERIOD_MIN_XTICS; + +// xilinx (mintime+deadtime) (F * T.. = (60 / 16 / 2) * T = (60 * T / 16 / 2)) +//#pragma DATA_SECTION(var_period_min_xtics,".fast_vars1"); +//int var_period_min_xtics = DEF_PERIOD_MIN_XTICS;// + +// xilinx (mintime) (F * T.. = (60 / 16 / 2) * T = (60 * T / 16 / 2)) +#pragma DATA_SECTION(var_period_min_br_xtics,".fast_vars1"); +int var_period_min_br_xtics = DEF_PERIOD_MIN_BR_XTICS;// + + + + +#define IQ_ALFA_SATURATION1 15099494//16441671//15099494 +#define IQ_ALFA_SATURATION2 1677721//16441671//15099494 + + +#define PI 3.1415926535897932384626433832795 + +//#pragma DATA_SECTION(iq_alfa_coef,".fast_vars"); +//_iq iq_alfa_coef = 16777216; + + +//#pragma DATA_SECTION(pidCur_Ki,".fast_vars"); +//_iq pidCur_Ki = 0; + +//#pragma DATA_SECTION(ar_tph,".fast_vars"); +//_iq ar_tph[7]; + +//#pragma DATA_SECTION(winding_displacement,".fast_vars"); +//_iq winding_displacement = CONST_IQ_PI6; + + + +#pragma DATA_SECTION(svgen_pwm24_1,".v_24pwm_vars"); +SVGEN_PWM24 svgen_pwm24_1 = SVGEN_PWM24_DEFAULTS; +#pragma DATA_SECTION(svgen_pwm24_2,".v_24pwm_vars"); +SVGEN_PWM24 svgen_pwm24_2 = SVGEN_PWM24_DEFAULTS; + + + + +ALG_PWM24 alg_pwm24 = ALG_PWM24_DEFAULTS; + + + + + + + +#pragma CODE_SECTION(start_PWM24,".fast_run2") +void start_PWM24(int O1, int O2) +{ + if ((O1 == 1) && (O2 == 1)) + { + soft_start_x24_pwm_1_2(); + } + else + { + if ((O1 == 0) && (O2 == 1)) + { + soft_start_x24_pwm_2(); + } + if ((O1 == 1) && (O2 == 0)) + { + soft_start_x24_pwm_1(); + } + } +} + + + + +void InitPWM_Variables(int n_pch) +{ + +// init_DQ_pid(); +// break_resistor_managment_init(); + + +///////////// + + +////////////// +// a.k = 0; +// a.k1 = 0; +// a.k2 = 0; + + alg_pwm24.k1 = 0; + alg_pwm24.k2 = 0; + + alg_pwm24.freq1 = 0; + +/////////////////// + + +/////////////////// + svgen_pwm24_1.prev_level = V_PWM24_PREV_PWM_CLOSE; + svgen_pwm24_1.saw_direct.all = xpwm_time.saw_direct.all & 0x3f; + svgen_pwm24_1.Tclosed_saw_direct_0 = xpwm_time.Tclosed_saw_direct_0;// xpwm_time.Tclosed_high;//var_freq_pwm_xtics + 1; + svgen_pwm24_1.Tclosed_saw_direct_1 = xpwm_time.Tclosed_saw_direct_1; + svgen_pwm24_1.Tclosed_high = xpwm_time.Tclosed_high; + + svgen_pwm24_2.prev_level = V_PWM24_PREV_PWM_CLOSE; + svgen_pwm24_2.saw_direct.all = (xpwm_time.saw_direct.all >> 6) & 0x3f; + svgen_pwm24_2.Tclosed_saw_direct_0 = xpwm_time.Tclosed_saw_direct_0;// xpwm_time.Tclosed_high;//var_freq_pwm_xtics + 1; + svgen_pwm24_2.Tclosed_saw_direct_1 = xpwm_time.Tclosed_saw_direct_1; + svgen_pwm24_2.Tclosed_high = xpwm_time.Tclosed_high; + + + svgen_pwm24_1.XilinxFreq = CONST_IQ_1 / xpwm_time.Tclosed_high;//(var_freq_pwm_xtics + 1); + svgen_pwm24_2.XilinxFreq = svgen_pwm24_1.XilinxFreq; + + svgen_pwm24_1.number_svgen = 1; + svgen_pwm24_2.number_svgen = 2; + + // pwm_minimal_impuls_zero = DEF_PERIOD_MIN_XTICS_80; + + svgen_pwm24_1.pwm_minimal_impuls_zero_minus = (float)DEF_PERIOD_MIN_MKS*1000.0*FREQ_INTERNAL_GENERATOR_XILINX_TMS/1000000000.0;// DEF_PERIOD_MIN_XTICS_100;//DEF_PERIOD_MIN_XTICS_80; + svgen_pwm24_1.pwm_minimal_impuls_zero_plus = (float)DEF_PERIOD_MIN_MKS*1000.0*FREQ_INTERNAL_GENERATOR_XILINX_TMS/1000000000.0;// DEF_PERIOD_MIN_XTICS_80; + + svgen_pwm24_2.pwm_minimal_impuls_zero_minus = svgen_pwm24_1.pwm_minimal_impuls_zero_minus; + svgen_pwm24_2.pwm_minimal_impuls_zero_plus = svgen_pwm24_1.pwm_minimal_impuls_zero_plus; + + + if (n_pch==0) + { + svgen_pwm24_1.phase_sequence = V_PWM24_PHASE_SEQ_REVERS_CBA; + svgen_pwm24_2.phase_sequence = V_PWM24_PHASE_SEQ_REVERS_CBA; + } + else + { +// svgen_pwm24_1.phase_sequence = V_PWM24_PHASE_SEQ_REVERS_ACB; // +// svgen_pwm24_2.phase_sequence = V_PWM24_PHASE_SEQ_REVERS_ACB; + svgen_pwm24_1.phase_sequence = V_PWM24_PHASE_SEQ_REVERS_BAC; + svgen_pwm24_2.phase_sequence = V_PWM24_PHASE_SEQ_REVERS_BAC; + } + + + InitVariablesSvgen_Ing(xpwm_time.freq_pwm); +} + + + + + + + + + + +void InitXPWM(unsigned int freq_pwm) +{ + int i; + unsigned int pwm_t;//, freq_pwm_xtics; + + + + + pwm_t = (FREQ_INTERNAL_GENERATOR_XILINX_TMS / freq_pwm ); + // freq_pwm_xtics = (FREQ_INTERNAL_GENERATOR_XILINX_TMS / freq_pwm ); + +// write init pwm +// , , + xpwm_time.Tclosed_saw_direct_1 = pwm_t + 2;//1; // =1 , + xpwm_time.Tclosed_saw_direct_0 = 0; // =0 , + + xpwm_time.Tclosed_high = pwm_t + 2;//1; + + // + // " =0x0 + // SAW_DIRECTbit = 0 > =0 + // + // SAW_DIRECTbit = 1 <= =0 + // + xpwm_time.saw_direct.all = 0x0555; + + +// + xpwm_time.pwm_tics = pwm_t; + xpwm_time.freq_pwm = freq_pwm; + xpwm_time.half_pwm_tics = xpwm_time.pwm_tics >> 1; + + xpwm_time.one_or_two_interrupts_run = PWN_COUNT_RUN_PER_INTERRUPT; + xpwm_time.init(&xpwm_time); + +// write to xilinx regs + xpwm_time.write_zero_winding_break_times(&xpwm_time); + + +// + i_WriteMemory(ADR_PWM_DIRECT, 0xffff); + i_WriteMemory(ADR_PWM_DRIVE_MODE, 0); //Choose PWM sourse PWMGenerator on Spartan 200e + // DeadTime + i_WriteMemory(ADR_PWM_DEAD_TIME, 360); //Dead time in tics. + stop_wdog(); + + i_WriteMemory(ADR_PWM_PERIOD, pwm_t); // Saw period in tics. 1 tic = FREQ_INTERNAL_GENERATOR_XILINX_TMS + // + i_WriteMemory(ADR_PWM_SAW_DIRECT, xpwm_time.saw_direct.all); + //" (15 0). 0 - , 1 - . + // Xilinx, 0x2006(15) = 0, + // 0x2006(15) = 1, " + i_WriteMemory(ADR_TK_MASK_0, 0); + // " (31 16) Xilinx, 0x2006(15) = 0, + // 0x2006(15) = 1, " + i_WriteMemory(ADR_TK_MASK_1, 0xffff); //Turn off additional 16 tk lines + + + i_WriteMemory(ADR_PWM_IT_TYPE, PWN_COUNT_RUN_PER_INTERRUPT); //1 or 2 interrupt per PWM period + +// +//#if (C_PROJECT_TYPE == PROJECT_BALZAM) || (C_PROJECT_TYPE == PROJECT_23550) +// i_WriteMemory(ADR_PWM_IT_TYPE, 1); //1 interrupt per PWM period +//#else +// i_WriteMemory(ADR_PWM_IT_TYPE, 0); //interrupt on each counter twist +//#endif + +/* End f PWM Gen init */ +} + + + +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + +/* +void init_freq_array(void) +{ + unsigned int i = 0; + //unsigned int j = 0; + int var1 = 0; + + var1 = 32767 / (FREQ_PWM_MAX - FREQ_PWM_MIN); + + for (i = 0; i < COUNT_VAR_FREQ; i++) + { + //j = rand() / 1023; + //freq_array[i] = array_optim_freq[j]; + //do + freq_array[i] = FREQ_PWM_MIN + (rand() / var1); + //while ((freq_array[i] < 945) && (freq_array[i] > 930)); + } + + //freq_array[0] = 991; + //freq_array[1] = 1430; +} +*/ + + +//#pragma CODE_SECTION(calc_freq_pwm,".v_24pwm_run"); +//#pragma CODE_SECTION(calc_freq_pwm,".fast_run"); +/*void calc_freq_pwm() +{ + static int prev_freq_pwm = 0; + static float pwm_period = 0; + static float var0 = 0; + //static int line = 0; + //static int i = 0; + static unsigned int proc_ticks = 1; + int var1 = 0; + //static int i = 0; + + if ((f.flag_change_pwm_freq == 1) && (f.flag_random_freq == 1)) + { + if (proc_ticks >= 1) + { + proc_ticks = 0; + + + if (line == 0) + { + VAR_FREQ_PWM_HZ = VAR_FREQ_PWM_HZ + 1; + if (VAR_FREQ_PWM_HZ > FREQ_PWM_MAX) + { + VAR_FREQ_PWM_HZ = FREQ_PWM_MAX; + line = 1; + } + } + else + { + VAR_FREQ_PWM_HZ = VAR_FREQ_PWM_HZ - 1; + if (VAR_FREQ_PWM_HZ < FREQ_PWM) + { + VAR_FREQ_PWM_HZ = FREQ_PWM; + line = 0; + } + } + + + + + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + //VAR_FREQ_PWM_HZ = freq_array[i]; + //i_led2_on_off(1); + + var1 = 32767 / (freq_pwm_max_hz - freq_pwm_min_hz); + VAR_FREQ_PWM_HZ = freq_pwm_min_hz + (rand() / var1); + + //i_led2_on_off(0); + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + + if (VAR_FREQ_PWM_HZ > freq_pwm_max_hz) + { + VAR_FREQ_PWM_HZ = freq_pwm_max_hz; + } + else + { + if (VAR_FREQ_PWM_HZ < freq_pwm_min_hz) + { + VAR_FREQ_PWM_HZ = freq_pwm_min_hz; + } + } + //i++; + + //if (i >= COUNT_VAR_FREQ) + //{ + //i = 0; + //} + + } + + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + //if (VAR_FREQ_PWM_HZ == FREQ_PWM_MIN) + //{ + //VAR_FREQ_PWM_HZ = FREQ_PWM_MAX; + //} + //else + //{ + //VAR_FREQ_PWM_HZ = FREQ_PWM_MIN; + //} + + //if (f.Rele1 == 1) + //{ + //if (i == 0) + //{ + //VAR_FREQ_PWM_HZ = 1192;; + //i = 1; + //} + //else + //{ + //VAR_FREQ_PWM_HZ = 792; + //} + //} + //else + //{ + //i = 0; + //VAR_FREQ_PWM_HZ = 1192; + //} + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + } + //else + //{ + //VAR_FREQ_PWM_HZ = FREQ_PWM; + //} + + + if (prev_freq_pwm != VAR_FREQ_PWM_HZ) + { + prev_freq_pwm = VAR_FREQ_PWM_HZ; + FREQ_MAX = _IQ(2.0*PI*F_STATOR_MAX/VAR_FREQ_PWM_HZ); + + var0 = (float)VAR_FREQ_PWM_HZ; + //pwm_period = ((float64)HSPCLK) / ((float64)VAR_FREQ_PWM_HZ); + + pwm_period = HSPCLK / var0; + + pwm_period = pwm_period / 2.0; + + FREQ_PWM_XTICS = ((int) pwm_period) >> 3; + + XILINX_FREQ = 16777216/(FREQ_PWM_XTICS + 1); + + FLAG_CHANGE_FREQ_PWM = 1; + } + + proc_ticks++; +} +*/ +/* +#pragma CODE_SECTION(test_calc_pwm24_dq,".v_24pwm_run"); +void test_calc_pwm24_dq(_iq U_zad1, _iq U_zad2,_iq teta) +{ + svgen_pwm24_1.Freq = 0; + svgen_pwm24_2.Freq = 0; + + svgen_pwm24_1.Gain = U_zad1; + svgen_pwm24_2.Gain = U_zad2; + + svgen_pwm24_1.Alpha = teta; + svgen_pwm24_2.Alpha = teta; + + svgen_pwm24_1.delta_U = filter.iqU_1_fast - filter.iqU_2_fast; + svgen_pwm24_2.delta_U = filter.iqU_1_fast - filter.iqU_2_fast; +// svgen_pwm24_2.delta_U = filter.iqU_3_fast - filter.iqU_4_fast; + + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + svgen_pwm24_1.delta_U = 0; + svgen_pwm24_2.delta_U = 0; + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + + svgen_pwm24_1.Ia = analog.iqIu_1; + svgen_pwm24_1.Ib = analog.iqIv_1; + svgen_pwm24_1.Ic = analog.iqIw_1;; + + svgen_pwm24_2.Ia = analog.iqIu_2; + svgen_pwm24_2.Ib = analog.iqIv_2; + svgen_pwm24_2.Ic = analog.iqIw_2; + + svgen_pwm24_1.calc_dq(&svgen_pwm24_1); + svgen_pwm24_2.calc_dq(&svgen_pwm24_2); + + + // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + + set_predel_dshim24(&svgen_pwm24_1.Ta_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + set_predel_dshim24(&svgen_pwm24_1.Ta_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + + set_predel_dshim24(&svgen_pwm24_1.Tb_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + set_predel_dshim24(&svgen_pwm24_1.Tb_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + + set_predel_dshim24(&svgen_pwm24_1.Tc_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + set_predel_dshim24(&svgen_pwm24_1.Tc_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + + set_predel_dshim24(&svgen_pwm24_2.Ta_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + set_predel_dshim24(&svgen_pwm24_2.Ta_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + + set_predel_dshim24(&svgen_pwm24_2.Tb_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + set_predel_dshim24(&svgen_pwm24_2.Tb_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + + set_predel_dshim24(&svgen_pwm24_2.Tc_0,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + set_predel_dshim24(&svgen_pwm24_2.Tc_1,VAR_PERIOD_MIN_XTICS,VAR_FREQ_PWM_XTICS); + + +} +*/ + +/* +#pragma CODE_SECTION(svgen_pwm24_calc,".v_24pwm_run"); +void svgen_pwm24_calc_dq(SVGEN_PWM24 *vt) +{ + + if (vt->Alpha > CONST_IQ_2PI) + { + vt->Alpha -= CONST_IQ_2PI; + } + + if (vt->Alpha < 0) + { + vt->Alpha += CONST_IQ_2PI; + } + + + calc_time_one_tk(vt->Gain, vt->Alpha, vt->delta_U, vt->Ia, vt->Ib, vt->Ic, + vt->number_svgen,vt->direct_rotor, &vt->Ta_0, &vt->Ta_1,&vt->Tb_0, &vt->Tb_1,&vt->Tc_0, &vt->Tc_1); + + + vt->Ta_0.Ti = vt->Ta_0.Ti/vt->XilinxFreq; + vt->Ta_1.Ti = vt->Ta_1.Ti/vt->XilinxFreq; + + vt->Tb_0.Ti = vt->Tb_0.Ti/vt->XilinxFreq; + vt->Tb_1.Ti = vt->Tb_1.Ti/vt->XilinxFreq; + + vt->Tc_0.Ti = vt->Tc_0.Ti/vt->XilinxFreq; + vt->Tc_1.Ti = vt->Tc_1.Ti/vt->XilinxFreq; + +} +*/ + + + + +void svgen_set_time_keys_closed(SVGEN_PWM24 *vt) +{ +//a + if (vt->saw_direct.bits.bit0) + vt->Ta_0 = vt->Tclosed_saw_direct_1; + else + vt->Ta_0 = vt->Tclosed_saw_direct_0; + + if (vt->saw_direct.bits.bit1) + vt->Ta_1 = vt->Tclosed_saw_direct_1; + else + vt->Ta_1 = vt->Tclosed_saw_direct_0; +//b + if (vt->saw_direct.bits.bit2) + vt->Tb_0 = vt->Tclosed_saw_direct_1; + else + vt->Tb_0 = vt->Tclosed_saw_direct_0; + + if (vt->saw_direct.bits.bit3) + vt->Tb_1 = vt->Tclosed_saw_direct_1; + else + vt->Tb_1 = vt->Tclosed_saw_direct_0; +//c + if (vt->saw_direct.bits.bit4) + vt->Tc_0 = vt->Tclosed_saw_direct_1; + else + vt->Tc_0 = vt->Tclosed_saw_direct_0; + + if (vt->saw_direct.bits.bit5) + vt->Tc_1 = vt->Tclosed_saw_direct_1; + else + vt->Tc_1 = vt->Tclosed_saw_direct_0; + + vt->prev_level = V_PWM24_PREV_PWM_CLOSE; + +} + + + + + +#pragma CODE_SECTION(correct_balance_uzpt_pwm24,".fast_run2"); +_iq correct_balance_uzpt_pwm24(_iq Tinput, _iq Kplus) +{ +//_iq pwm_t, timpuls_corr; + volatile _iq timpuls_corr; + + if (Tinput >= (-Kplus)) + timpuls_corr = CONST_IQ_1 - _IQdiv(CONST_IQ_1-Tinput, CONST_IQ_1+Kplus); + else + timpuls_corr = -CONST_IQ_1 + _IQdiv(CONST_IQ_1+Tinput, CONST_IQ_1-Kplus); + + + return timpuls_corr; +} + + + + + +#pragma CODE_SECTION(recalc_time_pwm_minimal_2_xilinx_pwm24,".fast_run2"); +void recalc_time_pwm_minimal_2_xilinx_pwm24(SVGEN_PWM24 *pwm24, + unsigned int *T0, unsigned int *T1, + int *T_imp, + _iq timpuls_corr ) +{ +//_iq pwm_t, timpuls_corr; + + volatile unsigned long pwm_t; + volatile unsigned int minimal_plus, minimal_minus; + + + + minimal_plus = pwm24->pwm_minimal_impuls_zero_plus; + minimal_minus = pwm24->pwm_minimal_impuls_zero_minus; + + // if (pwm24->prev_level == V_PWM24_PREV_PWM_CLOSE || pwm24->prev_level == V_PWM24_PREV_PWM_MIDDLE || pwm24->prev_level == V_PWM24_PREV_PWM_WORK_KM0) + // { + // minimal_plus *= 2; +// minimal_minus *= 2; +// } + + pwm_t = timpuls_corr / pwm24->XilinxFreq; + + *T_imp = pwm_t; + +// if (pwm_t>(pwm24->Tclosed_high-4*minimal_minus)) +// pwm_t=(pwm24->Tclosed_high-4*minimal_minus); + + + if (timpuls_corr >= 0) + { + *T0 = pwm_t + minimal_plus; + *T1 = pwm24->Tclosed_high - minimal_minus; + } + else + { + *T0 = minimal_plus; + *T1 = pwm24->Tclosed_high + pwm_t - minimal_minus; + } + + + if (*T0 < minimal_plus) + *T0 = minimal_plus; + + if (*T0 > (pwm24->Tclosed_high - 2 * minimal_plus)) + *T0 = (pwm24->Tclosed_high - 2 * minimal_plus); + + if (*T1 < (2 * minimal_minus)) + *T1 = 2 * minimal_minus; + + if (*T1 > (pwm24->Tclosed_high - minimal_minus)) + *T1 = (pwm24->Tclosed_high - minimal_minus); + +} + +#define WRITE_SWGEN_PWM_TIMES_VER 2//1 + +#if (WRITE_SWGEN_PWM_TIMES_VER==1) +#pragma CODE_SECTION(write_swgen_pwm_times,".fast_run2"); +void write_swgen_pwm_times(unsigned int mode_reload) +{ + + if (svgen_pwm24_1.phase_sequence == V_PWM24_PHASE_SEQ_NORMAL_ABC) + { + xpwm_time.Ta0_0 = (unsigned int) svgen_pwm24_1.Ta_0; + xpwm_time.Ta0_1 = (unsigned int) svgen_pwm24_1.Ta_1; + xpwm_time.Tb0_0 = (unsigned int) svgen_pwm24_1.Tb_0; + xpwm_time.Tb0_1 = (unsigned int) svgen_pwm24_1.Tb_1; + xpwm_time.Tc0_0 = (unsigned int) svgen_pwm24_1.Tc_0; + xpwm_time.Tc0_1 = (unsigned int) svgen_pwm24_1.Tc_1; + } + + if (svgen_pwm24_2.phase_sequence == V_PWM24_PHASE_SEQ_NORMAL_ABC) + { + xpwm_time.Ta1_0 = (unsigned int) svgen_pwm24_2.Ta_0; + xpwm_time.Ta1_1 = (unsigned int) svgen_pwm24_2.Ta_1; + xpwm_time.Tb1_0 = (unsigned int) svgen_pwm24_2.Tb_0; + xpwm_time.Tb1_1 = (unsigned int) svgen_pwm24_2.Tb_1; + xpwm_time.Tc1_0 = (unsigned int) svgen_pwm24_2.Tc_0; + xpwm_time.Tc1_1 = (unsigned int) svgen_pwm24_2.Tc_1; + } + + if (svgen_pwm24_1.phase_sequence == V_PWM24_PHASE_SEQ_NORMAL_BCA) + { + xpwm_time.Ta0_0 = (unsigned int) svgen_pwm24_1.Tb_0; + xpwm_time.Ta0_1 = (unsigned int) svgen_pwm24_1.Tb_1; + xpwm_time.Tb0_0 = (unsigned int) svgen_pwm24_1.Tc_0; + xpwm_time.Tb0_1 = (unsigned int) svgen_pwm24_1.Tc_1; + xpwm_time.Tc0_0 = (unsigned int) svgen_pwm24_1.Ta_0; + xpwm_time.Tc0_1 = (unsigned int) svgen_pwm24_1.Ta_1; + } + + if (svgen_pwm24_2.phase_sequence == V_PWM24_PHASE_SEQ_NORMAL_BCA) + { + xpwm_time.Ta1_0 = (unsigned int) svgen_pwm24_2.Tb_0; + xpwm_time.Ta1_1 = (unsigned int) svgen_pwm24_2.Tb_1; + xpwm_time.Tb1_0 = (unsigned int) svgen_pwm24_2.Tc_0; + xpwm_time.Tb1_1 = (unsigned int) svgen_pwm24_2.Tc_1; + xpwm_time.Tc1_0 = (unsigned int) svgen_pwm24_2.Ta_0; + xpwm_time.Tc1_1 = (unsigned int) svgen_pwm24_2.Ta_1; + } + + if (svgen_pwm24_1.phase_sequence == V_PWM24_PHASE_SEQ_NORMAL_CAB) + { + xpwm_time.Ta0_0 = (unsigned int) svgen_pwm24_1.Tc_0; + xpwm_time.Ta0_1 = (unsigned int) svgen_pwm24_1.Tc_1; + xpwm_time.Tb0_0 = (unsigned int) svgen_pwm24_1.Ta_0; + xpwm_time.Tb0_1 = (unsigned int) svgen_pwm24_1.Ta_1; + xpwm_time.Tc0_0 = (unsigned int) svgen_pwm24_1.Tb_0; + xpwm_time.Tc0_1 = (unsigned int) svgen_pwm24_1.Tb_1; + } + if (svgen_pwm24_2.phase_sequence == V_PWM24_PHASE_SEQ_NORMAL_CAB) + { + xpwm_time.Ta1_0 = (unsigned int) svgen_pwm24_2.Tc_0; + xpwm_time.Ta1_1 = (unsigned int) svgen_pwm24_2.Tc_1; + xpwm_time.Tb1_0 = (unsigned int) svgen_pwm24_2.Ta_0; + xpwm_time.Tb1_1 = (unsigned int) svgen_pwm24_2.Ta_1; + xpwm_time.Tc1_0 = (unsigned int) svgen_pwm24_2.Tb_0; + xpwm_time.Tc1_1 = (unsigned int) svgen_pwm24_2.Tb_1; + } + + // fix revers + if (svgen_pwm24_1.phase_sequence == V_PWM24_PHASE_SEQ_REVERS_BAC) + { + xpwm_time.Ta0_0 = (unsigned int) svgen_pwm24_1.Tb_0; + xpwm_time.Ta0_1 = (unsigned int) svgen_pwm24_1.Tb_1; + xpwm_time.Tb0_0 = (unsigned int) svgen_pwm24_1.Ta_0; + xpwm_time.Tb0_1 = (unsigned int) svgen_pwm24_1.Ta_1; + xpwm_time.Tc0_0 = (unsigned int) svgen_pwm24_1.Tc_0; + xpwm_time.Tc0_1 = (unsigned int) svgen_pwm24_1.Tc_1; + } + if (svgen_pwm24_2.phase_sequence == V_PWM24_PHASE_SEQ_REVERS_BAC) + { + xpwm_time.Ta1_0 = (unsigned int) svgen_pwm24_2.Tb_0; + xpwm_time.Ta1_1 = (unsigned int) svgen_pwm24_2.Tb_1; + xpwm_time.Tb1_0 = (unsigned int) svgen_pwm24_2.Ta_0; + xpwm_time.Tb1_1 = (unsigned int) svgen_pwm24_2.Ta_1; + xpwm_time.Tc1_0 = (unsigned int) svgen_pwm24_2.Tc_0; + xpwm_time.Tc1_1 = (unsigned int) svgen_pwm24_2.Tc_1; + } + + if (svgen_pwm24_1.phase_sequence == V_PWM24_PHASE_SEQ_REVERS_ACB) + { + xpwm_time.Ta0_0 = (unsigned int) svgen_pwm24_1.Ta_0; + xpwm_time.Ta0_1 = (unsigned int) svgen_pwm24_1.Ta_1; + xpwm_time.Tb0_0 = (unsigned int) svgen_pwm24_1.Tc_0; + xpwm_time.Tb0_1 = (unsigned int) svgen_pwm24_1.Tc_1; + xpwm_time.Tc0_0 = (unsigned int) svgen_pwm24_1.Tb_0; + xpwm_time.Tc0_1 = (unsigned int) svgen_pwm24_1.Tb_1; + } + if (svgen_pwm24_2.phase_sequence == V_PWM24_PHASE_SEQ_REVERS_ACB) + { + xpwm_time.Ta1_0 = (unsigned int) svgen_pwm24_2.Ta_0; + xpwm_time.Ta1_1 = (unsigned int) svgen_pwm24_2.Ta_1; + xpwm_time.Tb1_0 = (unsigned int) svgen_pwm24_2.Tc_0; + xpwm_time.Tb1_1 = (unsigned int) svgen_pwm24_2.Tc_1; + xpwm_time.Tc1_0 = (unsigned int) svgen_pwm24_2.Tb_0; + xpwm_time.Tc1_1 = (unsigned int) svgen_pwm24_2.Tb_1; + } + + if (svgen_pwm24_1.phase_sequence == V_PWM24_PHASE_SEQ_REVERS_CBA) + { + xpwm_time.Ta0_0 = (unsigned int) svgen_pwm24_1.Tc_0; + xpwm_time.Ta0_1 = (unsigned int) svgen_pwm24_1.Tc_1; + xpwm_time.Tb0_0 = (unsigned int) svgen_pwm24_1.Tb_0; + xpwm_time.Tb0_1 = (unsigned int) svgen_pwm24_1.Tb_1; + xpwm_time.Tc0_0 = (unsigned int) svgen_pwm24_1.Ta_0; + xpwm_time.Tc0_1 = (unsigned int) svgen_pwm24_1.Ta_1; + } + if (svgen_pwm24_2.phase_sequence == V_PWM24_PHASE_SEQ_REVERS_CBA) + { + xpwm_time.Ta1_0 = (unsigned int) svgen_pwm24_2.Tc_0; + xpwm_time.Ta1_1 = (unsigned int) svgen_pwm24_2.Tc_1; + xpwm_time.Tb1_0 = (unsigned int) svgen_pwm24_2.Tb_0; + xpwm_time.Tb1_1 = (unsigned int) svgen_pwm24_2.Tb_1; + xpwm_time.Tc1_0 = (unsigned int) svgen_pwm24_2.Ta_0; + xpwm_time.Tc1_1 = (unsigned int) svgen_pwm24_2.Ta_1; + } + + xpwm_time.Tbr0_0 = break_result_1; + xpwm_time.Tbr0_1 = break_result_2; + xpwm_time.Tbr1_0 = 0;//break_result_3; + xpwm_time.Tbr1_1 = 0;//break_result_4; + xpwm_time.mode_reload = mode_reload; + + xpwm_time.write_1_2_winding_break_times(&xpwm_time); +} +#endif +/////////////////////////////////////////////////////// +// ver 2 +/////////////////////////////////////////////////////// +#if (WRITE_SWGEN_PWM_TIMES_VER==2) + +#pragma CODE_SECTION(set_pwm_times,".fast_run2"); +void set_pwm_times(unsigned int Ta0, unsigned int Ta1, unsigned int Tb0, unsigned int Tb1, unsigned int Tc0, unsigned int Tc1, unsigned int winding_num) +{ + if (winding_num == 0) + { + xpwm_time.Ta0_0 = Ta0; + xpwm_time.Ta0_1 = Ta1; + xpwm_time.Tb0_0 = Tb0; + xpwm_time.Tb0_1 = Tb1; + xpwm_time.Tc0_0 = Tc0; + xpwm_time.Tc0_1 = Tc1; + } + else + { + xpwm_time.Ta1_0 = Ta0; + xpwm_time.Ta1_1 = Ta1; + xpwm_time.Tb1_0 = Tb0; + xpwm_time.Tb1_1 = Tb1; + xpwm_time.Tc1_0 = Tc0; + xpwm_time.Tc1_1 = Tc1; + } +} + +#pragma CODE_SECTION(process_phase_sequence,".fast_run2"); +void process_phase_sequence(SVGEN_PWM24 svgen_pwm, unsigned int winding_num) +{ + switch (svgen_pwm.phase_sequence) + { + case V_PWM24_PHASE_SEQ_NORMAL_ABC: + set_pwm_times(svgen_pwm.Ta_0, svgen_pwm.Ta_1, svgen_pwm.Tb_0, svgen_pwm.Tb_1, svgen_pwm.Tc_0, svgen_pwm.Tc_1, winding_num); + break; + case V_PWM24_PHASE_SEQ_NORMAL_BCA: + set_pwm_times(svgen_pwm.Tb_0, svgen_pwm.Tb_1, svgen_pwm.Tc_0, svgen_pwm.Tc_1, svgen_pwm.Ta_0, svgen_pwm.Ta_1, winding_num); + break; + case V_PWM24_PHASE_SEQ_NORMAL_CAB: + set_pwm_times(svgen_pwm.Tc_0, svgen_pwm.Tc_1, svgen_pwm.Ta_0, svgen_pwm.Ta_1, svgen_pwm.Tb_0, svgen_pwm.Tb_1, winding_num); + break; + case V_PWM24_PHASE_SEQ_REVERS_BAC: + set_pwm_times(svgen_pwm.Tb_0, svgen_pwm.Tb_1, svgen_pwm.Ta_0, svgen_pwm.Ta_1, svgen_pwm.Tc_0, svgen_pwm.Tc_1, winding_num); + break; + case V_PWM24_PHASE_SEQ_REVERS_ACB: + set_pwm_times(svgen_pwm.Ta_0, svgen_pwm.Ta_1, svgen_pwm.Tc_0, svgen_pwm.Tc_1, svgen_pwm.Tb_0, svgen_pwm.Tb_1, winding_num); + break; + case V_PWM24_PHASE_SEQ_REVERS_CBA: + set_pwm_times(svgen_pwm.Tc_0, svgen_pwm.Tc_1, svgen_pwm.Tb_0, svgen_pwm.Tb_1, svgen_pwm.Ta_0, svgen_pwm.Ta_1, winding_num); + break; + } +} +#pragma CODE_SECTION(write_swgen_pwm_times,".fast_run2"); +void write_swgen_pwm_times(unsigned int mode_reload) +{ + process_phase_sequence(svgen_pwm24_1, 0); + process_phase_sequence(svgen_pwm24_2, 1); + + // fix breaks + xpwm_time.Tbr0_0 = break_result_1; + xpwm_time.Tbr0_1 = break_result_2; + xpwm_time.Tbr1_0 = 0; // break_result_3; + xpwm_time.Tbr1_1 = 0; // break_result_4; + xpwm_time.mode_reload = mode_reload; + + xpwm_time.write_1_2_winding_break_times(&xpwm_time); +} +#endif + + + + + + + + +/////////////////////////////////////////////////////// + +void svgen_set_time_middle_keys_open(SVGEN_PWM24 *vt) +{ + //a + if (vt->saw_direct.bits.bit0) + vt->Ta_0 = vt->Tclosed_saw_direct_0; + else + vt->Ta_0 = vt->Tclosed_saw_direct_1; + + if (vt->saw_direct.bits.bit1) + vt->Ta_1 = vt->Tclosed_saw_direct_0; + else + vt->Ta_1 = vt->Tclosed_saw_direct_1; + //b + if (vt->saw_direct.bits.bit2) + vt->Tb_0 = vt->Tclosed_saw_direct_0; + else + vt->Tb_0 = vt->Tclosed_saw_direct_1; + + if (vt->saw_direct.bits.bit3) + vt->Tb_1 = vt->Tclosed_saw_direct_0; + else + vt->Tb_1 = vt->Tclosed_saw_direct_1; + //c + if (vt->saw_direct.bits.bit4) + vt->Tc_0 = vt->Tclosed_saw_direct_0; + else + vt->Tc_0 = vt->Tclosed_saw_direct_1; + + if (vt->saw_direct.bits.bit5) + vt->Tc_1 = vt->Tclosed_saw_direct_0; + else + vt->Tc_1 = vt->Tclosed_saw_direct_1; + + + vt->prev_level = V_PWM24_PREV_PWM_MIDDLE; + +/* + + vt->Ta_0 = 0; + vt->Ta_1 = vt->Tclosed;//var_freq_pwm_xtics + 1; + + vt->Tb_0 = 0; + vt->Tb_1 = vt->Tclosed;// var_freq_pwm_xtics + 1; + + vt->Tc_0 = 0; + vt->Tc_1 = vt->Tclosed;// var_freq_pwm_xtics + 1; + */ +} + +/////////////////////////////////////////////////////// +/////////////////////////////////////////////////////// +/////////////////////////////////////////////////////// + + +#pragma CODE_SECTION(detect_level_interrupt,".fast_run"); +unsigned int detect_level_interrupt(int flag_second_PCH) +{ + unsigned int curr_period1, curr_period2, curr_period0; + static unsigned int count_err_read_pwm_xilinx = 0; + + + WriteMemory(ADR_SAW_REQUEST, 0x8000); + curr_period0 = ReadMemory(ADR_SAW_VALUE); + WriteMemory(ADR_SAW_REQUEST, 0x8000); + curr_period1 = ReadMemory(ADR_SAW_VALUE); + WriteMemory(ADR_SAW_REQUEST, 0x8000); + curr_period2 = ReadMemory(ADR_SAW_VALUE); + + xpwm_time.current_period = curr_period2; + + + // ? + if (xpwm_time.current_periodcurr_period1) // + { + if ((curr_period2-curr_period1)>xpwm_time.half_pwm_tics)// + { +// xpwm_time.what_next_interrupt = 1; + // + return 1; + } + } + else// + { + if ((curr_period1-curr_period2)>xpwm_time.half_pwm_tics)// + { + // + return 1; + } + } + + // , ! + return 0; + + +} + diff --git a/Inu/Src2/551/main/v_pwm24_v2.h b/Inu/Src2/551/main/v_pwm24_v2.h new file mode 100644 index 0000000..e0e1baa --- /dev/null +++ b/Inu/Src2/551/main/v_pwm24_v2.h @@ -0,0 +1,161 @@ +#ifndef _V_PWM24_H +#define _V_PWM24_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "IQmathLib.h" +#include "DSP281x_Device.h" +#include "word_structurs.h" + + +#include "vhzprof.h" +#include "rmp_cntl_v1.h" + +enum { V_PWM24_PREV_PWM_CLOSE = 1, + V_PWM24_PREV_PWM_MIDDLE, + V_PWM24_PREV_PWM_WORK_KM0, + V_PWM24_PREV_PWM_WORK +}; + +enum { V_PWM24_PHASE_SEQ_NORMAL_ABC = 1, + V_PWM24_PHASE_SEQ_NORMAL_BCA, + V_PWM24_PHASE_SEQ_NORMAL_CAB, + V_PWM24_PHASE_SEQ_REVERS_ACB, + V_PWM24_PHASE_SEQ_REVERS_CBA, + V_PWM24_PHASE_SEQ_REVERS_BAC +}; + + + + +typedef struct { _iq freq1; + _iq k1; + _iq k2; + } ALG_PWM24; + +typedef ALG_PWM24 *ALG_PWM24_handle; + + +#define ALG_PWM24_DEFAULTS {0,0,0} +//////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////// + + +typedef struct { // _iq Gain; // Input: reference gain voltage (pu) + //_iq Offset; // Input: reference offset voltage (pu) +// _iq Freq; // Input: reference frequency (pu) +// _iq FreqMax; // Parameter: Maximum step angle = 6*base_freq*T (pu) +// _iq Alpha; // History: Sector angle (pu) + //_iq Full_Alpha; + //_iq NewEntry; // History: Sine (angular) look-up pointer (pu) +// _iq delta_U; +// _iq delta_t; + //int16 Periodmax; + //int16 PeriodMin; + unsigned int XilinxFreq; // Xilinx freq in TIC + + unsigned int pwm_minimal_impuls_zero_plus; + unsigned int pwm_minimal_impuls_zero; + unsigned int pwm_minimal_impuls_zero_minus; + + WORD_UINT2BITS_STRUCT saw_direct; + + //int region; + //Uint32 SectorPointer; // History: Sector number (Q0) - independently with global Q + //PIDREG3 delta_t; +// _iq Ia; +// _iq Ib; +// _iq Ic; + unsigned int number_svgen; + unsigned int phase_sequence; // + int prev_level; // , middle close + unsigned int Tclosed_high; + unsigned int Tclosed_saw_direct_0; + unsigned int Tclosed_saw_direct_1; + + + unsigned int Ta_0; + unsigned int Ta_1; + + int Ta_imp; + + unsigned int Tb_0; + unsigned int Tb_1; + + int Tb_imp; + + unsigned int Tc_0; + unsigned int Tc_1; + + int Tc_imp; + +// void (*calc)(); // Pointer to calculation function +// void (*calc_dq)(); // Pointer to calculation function which don`t calculate angle from freq + } SVGEN_PWM24; + +typedef SVGEN_PWM24 *SVGEN_PWM24_handle; + + +//#define SVGEN_PWM24_TIME_DEFAULTS { 0,0,0,0 } + + +#define SVGEN_PWM24_DEFAULTS { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} +// (void (*)(unsigned int))svgen_pwm24_calc } + +//extern int ar_sa_a[3][4][7]; + +extern SVGEN_PWM24 svgen_pwm24_1; +extern SVGEN_PWM24 svgen_pwm24_2; + +extern _iq pidCur_Kp; +extern _iq pidCur_Ki; + +extern _iq iq_alfa_coef; + +extern _iq iq_koef_mod_korrect_1; +extern _iq iq_koef_mod_korrect_2; + + + +void write_swgen_pwm_times(unsigned int mode_reload); + +//void change_freq_pwm(_iq FreqMax, int freq_pwm_xtics, _iq XilinxFreq); + +unsigned int detect_level_interrupt(int flag_second_PCH); + + +void svgen_set_time_keys_closed(SVGEN_PWM24 *vt); +void svgen_set_time_middle_keys_open(SVGEN_PWM24 *vt); + + +_iq correct_balance_uzpt_pwm24(_iq Tinput, _iq Kplus); + +void recalc_time_pwm_minimal_2_xilinx_pwm24(SVGEN_PWM24 *pwm24, + unsigned int *T0, unsigned int *T1, + int *T_imp, + _iq timpuls_corr ); + + + +//////////////////////////////////////////////////////////// + +void InitXPWM(unsigned int freq_pwm); + +void start_PWM24(int O1, int O2); + +void InitPWM_Variables(int n_pch); + +////////////////////////////////////////////// + +extern ALG_PWM24 alg_pwm24; +extern RMP_V1 rmp_freq; +extern VHZPROF vhz1; + + +#ifdef __cplusplus + } +#endif + +#endif /* _V_PWM24_H */ diff --git a/Inu/Src2/551/main/v_rotor.c b/Inu/Src2/551/main/v_rotor.c new file mode 100644 index 0000000..1da2a2f --- /dev/null +++ b/Inu/Src2/551/main/v_rotor.c @@ -0,0 +1,1095 @@ +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "IQmathLib.h" + +#include +#include + +#include "filter_v1.h" +#include "xp_cds_in.h" +#include "xp_inc_sensor.h" +#include "xp_project.h" +#include "params.h" +#include "pwm_test_lines.h" +#include "params_norma.h" +#include "mathlib.h" #include "params_alg.h" + + +#pragma DATA_SECTION(WRotor,".fast_vars"); +WRotorValues WRotor = WRotorValues_DEFAULTS; + +#if (SENSOR_ALG==SENSOR_ALG_23550) + +#pragma DATA_SECTION(WRotorPBus,".slow_vars"); +WRotorValuesAngle WRotorPBus = WRotorValuesAngle_DEFAULTS; + +#pragma DATA_SECTION(rotor_error_update_count,".fast_vars"); +unsigned int rotor_error_update_count = 0; + + +#define SIZE_BUF_SENSOR_LOGS 32 +#pragma DATA_SECTION(sensor_1_zero,".slow_vars"); +unsigned int sensor_1_zero[6+4+8][SIZE_BUF_SENSOR_LOGS], count_sensor_1_zero=0; + +#endif + +_iq koefW = _IQ(0.05); //0.05 +_iq koefW2 = _IQ(0.01); //0.05 +_iq koefW3 = _IQ(0.002); //0.05 + + + + + + + +#if (SENSOR_ALG==SENSOR_ALG_23550) +/////////////////////////////////////////////////////////////// +void rotorInit(void) +{ + WRotorPBus.ModeAutoDiscret = 1; +} + + + +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +#define MAX_COUNT_OVERFULL_DISCRET 2250 +#define MAX_DIRECTION 4000 +#define MAX_DIRECTION_2 2000 +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +void RotorDirectionFilter(int RotorDirectionIn, int *RotorDirectionOut, int *RotorDirectionOut2, int *count_direction) +{ + +// static int count_direction = 0; +// static int count_direction_minus = 0; + + + if (RotorDirectionIn==0) + { + if (*count_direction>0) (*count_direction)--; + if (*count_direction<0) (*count_direction)++; +// if (count_direction_minus>0) count_direction_minus--; + } + else + if (RotorDirectionIn>0) + { + if (*count_direction0) count_direction_minus--; + } + else + { + if (*count_direction>-MAX_DIRECTION) (*count_direction)--; +// if (count_direction_plus>0) count_direction_plus--; + } + + + if (RotorDirectionIn==0) + *RotorDirectionOut = 0; + else + if (RotorDirectionIn>0) + *RotorDirectionOut = 1; + else + *RotorDirectionOut = -1; + + + if (*count_direction>MAX_DIRECTION_2) + *RotorDirectionOut2 = 1; + else + if (*count_direction<-MAX_DIRECTION_2) + *RotorDirectionOut2 = -1; + else + *RotorDirectionOut2 = 0; + + + +} +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +#define LEVEL_VALUE_SENSOR_OVERFULL 65535 +#define MAX_COUNT_ERROR_ANALISATOR_SENSOR_PBUS 4000 +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(AnalisatorRotorSensorPBus,".fast_run"); +int AnalisatorRotorSensorPBus(_iq d1, _iq d2, unsigned int *count_overfull_discret, unsigned int *count_zero_discret, _iq *prev_iqTimeRotor, + unsigned int *discret_out, unsigned int discret_in, _iq *iqWRotorCalcBeforeRegul, _iq *iqWRotorCalc, + int modeS1, int modeS2, + int valid_sensor_direct, int valid_sensor_90, + unsigned int *error_count ) +{ + int flag_not_ready_rotor, flag_overfull_rotor; + _iq iqTimeRotor; + // discret0 = 2 mks +// static long long KoefNorm_discret0 = 409600000LL;//((500 000/1024/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + static long long KoefNorm_discret0 = 102400000LL;//((500 000/4096/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + // discret1 = 20 ns +// static long long KoefNorm_discret1 = 40960000000LL;//((50 000 000/1024/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + static long long KoefNorm_discret1 = 10240000000LL;//((50 000 000/4096/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + +// _iq iqWRotorSumm;//,iqWRotorCalc; + + static _iq time_level_discret_1to0 = 60000 ;//682666; // KoefNorm_discret1/60000 = 0.813801288604736328125 . + static _iq time_level_discret_0to1 = 400;//204800; // KoefNorm_discret0/2000 = 0.244140625 . + static unsigned int discret; + + + if (valid_sensor_direct == 0) + d1 = 0; + if (valid_sensor_90 == 0) + d2 = 0; + + +// - , . + if (valid_sensor_direct == 0 && valid_sensor_90 == 0) + { + if (*error_count>1; + + + +// max OVERFULL + if (flag_overfull_rotor) + { + if (*count_overfull_discret0) + (*count_overfull_discret)--; + } + +// zero? + if (flag_not_ready_rotor) + { + if (*count_zero_discret0) + (*count_zero_discret)--; + } + +// real zero? + if (*count_zero_discret==MAX_COUNT_OVERFULL_DISCRET) + { + // , ! + iqWRotorCalc = 0; + *prev_iqTimeRotor = 0; + iqTimeRotor = 0; + } + else + { + // , prev_iqTimeRotor + if (iqTimeRotor==0) + iqTimeRotor = *prev_iqTimeRotor; + } + *prev_iqTimeRotor = iqTimeRotor; + + + +// + if (WRotorPBus.ModeAutoDiscret==1) + { + if ( (*count_overfull_discret==MAX_COUNT_OVERFULL_DISCRET) || (iqTimeRotor==0) ) + { + // , =0 + // discret_out = 0 + if (discret_in == 1) // discret? + { + // discret =1, 0. + *discret_out = 0; + *count_overfull_discret = 0; // ! + } + + } + else + { + // . discret==0 ... + if (discret==0 && iqTimeRotortime_level_discret_1to0 && iqTimeRotor!=65535) + *discret_out = 0; + } + } + + if (WRotorPBus.ModeAutoDiscret==2) + { + *discret_out = 0; + } + + if (WRotorPBus.ModeAutoDiscret==3) + { + *discret_out = 1; + } + + if ( (*count_overfull_discret==MAX_COUNT_OVERFULL_DISCRET) ) + { + // 0, .. ! + *prev_iqTimeRotor = iqTimeRotor = 0; + } + + + + + if ((iqTimeRotor != 0)) // && (WRotorPBus.iqTimeRotor<65535) + { + if (discret==0) + *iqWRotorCalcBeforeRegul = KoefNorm_discret0 / iqTimeRotor; + if (discret==1) + *iqWRotorCalcBeforeRegul = KoefNorm_discret1 / iqTimeRotor; + + *iqWRotorCalc = exp_regul_iq(koefW, *iqWRotorCalc, *iqWRotorCalcBeforeRegul); + } + else + { + *iqWRotorCalc = 0; + *iqWRotorCalcBeforeRegul = 0; + } + + +// if (*iqWRotorCalc == 0) +// *RotorDirection = 0; + + + return 0; + +} +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// + + +#pragma CODE_SECTION(RotorMeasurePBus,".fast_run"); +void RotorMeasurePBus(void) +{ + // discret0 = 2 mks +// static long long KoefNorm_discret0 = 409600000LL;//((500 000/1024/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + static long long KoefNorm_discret0 = 102400000LL;//((500 000/4096/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + // discret1 = 20 ns +// static long long KoefNorm_discret1 = 40960000000LL;//((50 000 000/1024/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + static long long KoefNorm_discret1 = 10240000000LL;//((50 000 000/4096/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + + static _iq time_level_discret_1to0 = 60000 ;//682666; // KoefNorm_discret1/60000 = 0.813801288604736328125 . + static _iq time_level_discret_0to1 = 400;//204800; // KoefNorm_discret0/2000 = 0.244140625 . + + static long long KoefNorm_angle = 16384LL; //2^24/1024 +// volatile float MyVar0 = 0; + + unsigned int MyVar3 = 0; +// int direction1 = 0, direction2 = 0; + volatile unsigned int discret; + + static unsigned int discret_out1, discret_out2; + + static int count_full_oborots = 0; + static unsigned int count_overfull_discret1 = 0; + static unsigned int count_zero_discret1 = 0; + static unsigned int count_overfull_discret2 = 0; + static unsigned int count_zero_discret2 = 0; + + static unsigned int count_discret_to_1 = 0; + static unsigned int count_discret_to_0 = 0; + + static unsigned int c_error_pbus_1 = 0; + static unsigned int c_error_pbus_2 = 0; + + + static _iq prev_iqTimeRotor1 = 0, prev_iqTimeRotor2 = 0; + + _iq iqWRotorSumm = 0; + + int flag_not_ready_rotor1, flag_overfull_rotor1; + int flag_not_ready_rotor2, flag_overfull_rotor2; + + //i_led1_on_off(1); + + + + flag_not_ready_rotor1 = 0; + flag_overfull_rotor1 = 0; + flag_not_ready_rotor2 = 0; + flag_overfull_rotor2 = 0; + + + + discret = project.cds_in[0].read.sbus.enabled_channels.bit.discret; + if (project.cds_in[0].read.sbus.enabled_channels.bit.discret != project.cds_in[0].write.sbus.enabled_channels.bit.discret) + discret = 2; + + if (project.cds_in[0].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + sensor_1_zero[0][count_sensor_1_zero] = project.cds_in[0].read.pbus.Time_since_zero_point_S1; + sensor_1_zero[1][count_sensor_1_zero] = project.cds_in[0].read.pbus.Impulses_since_zero_point_Rising_S1; + sensor_1_zero[2][count_sensor_1_zero] = project.cds_in[0].read.pbus.Impulses_since_zero_point_Falling_S1; + sensor_1_zero[3][count_sensor_1_zero] = project.cds_in[0].read.pbus.Time_since_zero_point_S2; + sensor_1_zero[4][count_sensor_1_zero] = project.cds_in[0].read.pbus.Impulses_since_zero_point_Rising_S2; + sensor_1_zero[5][count_sensor_1_zero] = project.cds_in[0].read.pbus.Impulses_since_zero_point_Falling_S2; + } + sensor_1_zero[6][count_sensor_1_zero] = project.cds_in[0].read.pbus.SpeedS1_cnt; + sensor_1_zero[7][count_sensor_1_zero] = project.cds_in[0].read.pbus.SpeedS1_cnt90; + sensor_1_zero[8][count_sensor_1_zero] = project.cds_in[0].read.pbus.SpeedS2_cnt; + sensor_1_zero[9][count_sensor_1_zero] = project.cds_in[0].read.pbus.SpeedS2_cnt90; + + sensor_1_zero[10][count_sensor_1_zero] = inc_sensor.data.Time1; + sensor_1_zero[11][count_sensor_1_zero] = inc_sensor.data.Impulses1; + sensor_1_zero[12][count_sensor_1_zero] = inc_sensor.data.CountZero1; + sensor_1_zero[13][count_sensor_1_zero] = inc_sensor.data.CountOne1; + + sensor_1_zero[14][count_sensor_1_zero] = inc_sensor.data.Time2; + sensor_1_zero[15][count_sensor_1_zero] = inc_sensor.data.Impulses2; + sensor_1_zero[16][count_sensor_1_zero] = inc_sensor.data.CountZero2; + sensor_1_zero[17][count_sensor_1_zero] = inc_sensor.data.CountOne2; + + count_sensor_1_zero++; + if (count_sensor_1_zero>=SIZE_BUF_SENSOR_LOGS) + { + count_sensor_1_zero = 0; + count_full_oborots++; + if (count_full_oborots>3) + count_full_oborots = 0; + } +/* + if (count_sensor_1_zero==904) + { + discret = 3; + } +*/ + +#if (ENABLE_ROTOR_SENSOR_ZERO_SIGNAL==1) + if (project.cds_in[0].type_cds_xilinx == TYPE_CDS_XILINX_SP6) + { + +#if (ENABLE_ROTOR_SENSOR_1_PBUS==1) + WRotorPBus.iqWRotorRawAngle1F = project.cds_in[0].read.pbus.Impulses_since_zero_point_Falling_S1-32768; + WRotorPBus.iqWRotorRawAngle1R = project.cds_in[0].read.pbus.Impulses_since_zero_point_Rising_S1-32768; + WRotorPBus.iqAngle1F = KoefNorm_angle * WRotorPBus.iqWRotorRawAngle1F; + WRotorPBus.iqAngle1R = KoefNorm_angle * WRotorPBus.iqWRotorRawAngle1R; +#else + WRotorPBus.iqWRotorRawAngle1F = 0; + WRotorPBus.iqWRotorRawAngle1R = 0; + WRotorPBus.iqAngle1F = 0; + WRotorPBus.iqAngle1R = 0; +#endif + +#if (ENABLE_ROTOR_SENSOR_2_PBUS==1) + WRotorPBus.iqWRotorRawAngle2F = project.cds_in[0].read.pbus.Impulses_since_zero_point_Falling_S2-32768; + WRotorPBus.iqWRotorRawAngle2R = project.cds_in[0].read.pbus.Impulses_since_zero_point_Rising_S2-32768; + WRotorPBus.iqAngle2F = KoefNorm_angle * WRotorPBus.iqWRotorRawAngle2F; + WRotorPBus.iqAngle2R = KoefNorm_angle * WRotorPBus.iqWRotorRawAngle2R; +#else + WRotorPBus.iqWRotorRawAngle2F = 0; + WRotorPBus.iqWRotorRawAngle2R = 0; + WRotorPBus.iqAngle2F = 0; + WRotorPBus.iqAngle2R = 0; +#endif + } + else + { + WRotorPBus.iqWRotorRawAngle1F = 0; + WRotorPBus.iqWRotorRawAngle1R = 0; + WRotorPBus.iqAngle1F = 0; + WRotorPBus.iqAngle1R = 0; + + WRotorPBus.iqWRotorRawAngle2F = 0; + WRotorPBus.iqWRotorRawAngle2R = 0; + WRotorPBus.iqAngle2F = 0; + WRotorPBus.iqAngle2R = 0; + + } +#endif + + +#if (ENABLE_ROTOR_SENSOR_1_PBUS==1) + //************************************************************************************************** + MyVar3 = project.cds_in[0].read.pbus.SpeedS1_cnt; + + if ((MyVar3 <= COUNT_DECODER_ZERO_WROTORPBus) + && (MyVar3 > COUNT_DECODER_MAX_WROTOR)) + { + WRotorPBus.iqWRotorRaw0 = MyVar3; + } + else + { + WRotorPBus.iqWRotorRaw0 = 0; + } + + MyVar3 = project.cds_in[0].read.pbus.SpeedS1_cnt90; + + if ((MyVar3 <= COUNT_DECODER_ZERO_WROTORPBus) + && (MyVar3 > COUNT_DECODER_MAX_WROTOR)) + { + WRotorPBus.iqWRotorRaw1 = MyVar3; + } + else + { + WRotorPBus.iqWRotorRaw1 = 0; + } +#else + WRotorPBus.iqWRotorRaw0 = 0; + WRotorPBus.iqWRotorRaw1 = 0; +#endif + + +#if (ENABLE_ROTOR_SENSOR_2_PBUS==1) + //*************************************************************************************************** + MyVar3 = project.cds_in[0].read.pbus.SpeedS2_cnt; + + if ((MyVar3 <= COUNT_DECODER_ZERO_WROTORPBus) + && (MyVar3 > COUNT_DECODER_MAX_WROTOR)) + { + WRotorPBus.iqWRotorRaw2 = MyVar3; + } + else + { + WRotorPBus.iqWRotorRaw2 = 0; + } + + MyVar3 = project.cds_in[0].read.pbus.SpeedS2_cnt90; + + if ((MyVar3 <= COUNT_DECODER_ZERO_WROTORPBus) + && (MyVar3 > COUNT_DECODER_MAX_WROTOR)) + { + WRotorPBus.iqWRotorRaw3 = MyVar3; + } + else + { + WRotorPBus.iqWRotorRaw3 = 0; + } +#else + WRotorPBus.iqWRotorRaw2 = 0; + WRotorPBus.iqWRotorRaw3 = 0; +#endif + + +#if (ENABLE_ROTOR_SENSOR_1_PBUS==1) +// if (project.cds_in[0].read.pbus.direction_in.bit.value_vaild_sensor1_direct && project.cds_in[0].read.pbus.direction_in.bit.value_vaild_sensor1_90 ) + AnalisatorRotorSensorPBus(WRotorPBus.iqWRotorRaw0, WRotorPBus.iqWRotorRaw1, &count_overfull_discret1, &count_zero_discret1, + &prev_iqTimeRotor1, &discret_out1, project.cds_in[0].read.sbus.enabled_channels.bit.discret, + &WRotorPBus.iqWRotorCalcBeforeRegul1, &WRotorPBus.iqWRotorCalc1, + project.cds_in[0].read.pbus.direction_in.bit.mode_sensor1_direct, project.cds_in[0].read.pbus.direction_in.bit.mode_sensor1_90, + project.cds_in[0].read.pbus.direction_in.bit.value_vaild_sensor1_direct, project.cds_in[0].read.pbus.direction_in.bit.value_vaild_sensor1_90, + &c_error_pbus_1 ); +#endif + +#if (ENABLE_ROTOR_SENSOR_2_PBUS==1) +// if (project.cds_in[0].read.pbus.direction_in.bit.value_vaild_sensor2_direct && project.cds_in[0].read.pbus.direction_in.bit.value_vaild_sensor2_90 ) + AnalisatorRotorSensorPBus(WRotorPBus.iqWRotorRaw2, WRotorPBus.iqWRotorRaw3, &count_overfull_discret2, &count_zero_discret2, + &prev_iqTimeRotor2, &discret_out2, project.cds_in[0].read.sbus.enabled_channels.bit.discret, + &WRotorPBus.iqWRotorCalcBeforeRegul2, &WRotorPBus.iqWRotorCalc2, + project.cds_in[0].read.pbus.direction_in.bit.mode_sensor2_direct, project.cds_in[0].read.pbus.direction_in.bit.mode_sensor2_90, + project.cds_in[0].read.pbus.direction_in.bit.value_vaild_sensor2_direct, project.cds_in[0].read.pbus.direction_in.bit.value_vaild_sensor2_90, + &c_error_pbus_2); +#endif + + + // RotorDirectionFilter(WRotorPBus.RotorDirectionInstant, &WRotorPBus.RotorDirectionSlow); + + + + if (discret_out1==1 || discret_out2==1) + { + project.cds_in[0].write.sbus.enabled_channels.bit.discret = 1; + count_discret_to_1++; + } + else + { + project.cds_in[0].write.sbus.enabled_channels.bit.discret = 0; + count_discret_to_0++; + } + + +} + + + +#define MAX_COUNT_OVERFULL_DISCRET_2 150 +#pragma CODE_SECTION(RotorMeasure,".fast_run"); +void RotorMeasure(void) +{ + + // 600 Khz clock on every edge +// static long long KoefNorm = 53635601LL;//((600 000/6256/NORMA_WROTOR/2) * ((long)2 << 24)); //15 - NormaWRotor 782*8 = 6256 +// static long long KoefNormMS = 491520000LL;//((600 000/1024/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 +// static long long KoefNormNS = 49152000000LL;//((60 000 000/1024/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + static long long KoefNormMS = 122880000LL;//((600 000/4096/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + static long long KoefNormNS = 12288000000LL;//((60 000 000/4096/NORMA_WROTOR) * ((long)2 << 24)); //20 - NORMA_FROTOR 1024*8 = 8129 + static long long KoefNormImpulses = 838860800000000LL;// (2^24 * 1000000000 / (Impulses(ns)) / NORMA_WROTOR + + static _iq max_value_rotor = _IQ(500.0/60.0/NORMA_FROTOR); + static _iq wrotor_add_ramp = _IQ(0.001/NORMA_FROTOR); + +// volatile float MyVar0 = 0; +// volatile unsigned int MyVar1 = 0; +// volatile unsigned int MyVar2 = 0; + unsigned int MyVar3; + + + inc_sensor.read_sensors(&inc_sensor); + + // flag_not_ready_rotor = 0; + +//************************************************************************************************** +// sensor 1 + + if (inc_sensor.use_sensor1) + { + MyVar3 = inc_sensor.data.CountOne1; +// MyVar3 = (unsigned long) rotation_sensor.in_plane.out.CountOne1; + + if ((MyVar3 < COUNT_DECODER_ZERO_WROTOR) + && (MyVar3 > COUNT_DECODER_MAX_WROTOR)) + { + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_21_ON; +#endif + + WRotor.iqWRotorRaw0 = MyVar3; + } + else + { + +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_21_OFF; +#endif + + WRotor.iqWRotorRaw0 = 0; + } + MyVar3 = inc_sensor.data.CountZero1; + + if ((MyVar3 < COUNT_DECODER_ZERO_WROTOR) + && (MyVar3 > COUNT_DECODER_MAX_WROTOR)) + { +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_22_ON; +#endif + WRotor.iqWRotorRaw1 = MyVar3; + } + else + { +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_22_OFF; +#endif + WRotor.iqWRotorRaw1 = 0; + } + } + else + { + WRotor.iqWRotorRaw0 = 0; + WRotor.iqWRotorRaw1 = 0; + } + //logpar.uns_log0 = (Uint16)(my_var1); + //logpar.uns_log1 = (Uint16)(my_var2); + + // sensor 2 + if (inc_sensor.use_sensor2) + { + MyVar3 = inc_sensor.data.CountOne2; + + if ((MyVar3 < COUNT_DECODER_ZERO_WROTOR) + && (MyVar3 > COUNT_DECODER_MAX_WROTOR)) + { +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_18_ON; +#endif + WRotor.iqWRotorRaw2 = MyVar3; + } + else + { +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_18_OFF; +#endif + WRotor.iqWRotorRaw2 = 0; + } + + MyVar3 = inc_sensor.data.CountZero2; + + if ((MyVar3 < COUNT_DECODER_ZERO_WROTOR) + && (MyVar3 > COUNT_DECODER_MAX_WROTOR)) + { +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_23_ON; +#endif + WRotor.iqWRotorRaw3 = MyVar3; + } + else + { +#if(_ENABLE_PWM_LINES_FOR_TESTS_ROTOR) + PWM_LINES_TK_23_OFF; +#endif + WRotor.iqWRotorRaw3 = 0; + } + } + else + { + WRotor.iqWRotorRaw2 = 0; + WRotor.iqWRotorRaw3 = 0; + } + +// if (WRotor.iqWRotorRaw0==0 && WRotor.iqWRotorRaw1==0 && WRotor.iqWRotorRaw2==0 && WRotor.iqWRotorRaw3==0) +// flag_not_ready_rotor = 1; + + if (WRotor.iqWRotorRaw0==0) + { + if (WRotor.count_zero_discret0==MAX_COUNT_OVERFULL_DISCRET_2) + { + WRotor.prev_iqWRotorRaw0 = WRotor.iqWRotorRaw0 = 0; + } + else + { + WRotor.iqWRotorRaw0 = WRotor.prev_iqWRotorRaw0; + WRotor.count_zero_discret0++; + } + } + else + { + WRotor.count_zero_discret0 = 0; + WRotor.prev_iqWRotorRaw0 = WRotor.iqWRotorRaw0; + } + + if (WRotor.iqWRotorRaw1==0) + { + if (WRotor.count_zero_discret1==MAX_COUNT_OVERFULL_DISCRET_2) + { + WRotor.prev_iqWRotorRaw1 = WRotor.iqWRotorRaw1 = 0; + } + else + { + WRotor.iqWRotorRaw1 = WRotor.prev_iqWRotorRaw1; + WRotor.count_zero_discret1++; + } + } + else + { + WRotor.count_zero_discret1 = 0; + WRotor.prev_iqWRotorRaw1 = WRotor.iqWRotorRaw1; + } + + if (WRotor.iqWRotorRaw2==0) + { + if (WRotor.count_zero_discret2==MAX_COUNT_OVERFULL_DISCRET_2) + { + WRotor.prev_iqWRotorRaw2 = WRotor.iqWRotorRaw2 = 0; + } + else + { + WRotor.iqWRotorRaw2 = WRotor.prev_iqWRotorRaw2; + WRotor.count_zero_discret2++; + } + } + else + { + WRotor.count_zero_discret2 = 0; + WRotor.prev_iqWRotorRaw2 = WRotor.iqWRotorRaw2; + } + + if (WRotor.iqWRotorRaw3==0) + { + if (WRotor.count_zero_discret3==MAX_COUNT_OVERFULL_DISCRET_2) + { + WRotor.prev_iqWRotorRaw3 = WRotor.iqWRotorRaw3 = 0; + } + else + { + WRotor.iqWRotorRaw3 = WRotor.prev_iqWRotorRaw3; + WRotor.count_zero_discret3++; + } + } + else + { + WRotor.count_zero_discret3 = 0; + WRotor.prev_iqWRotorRaw3 = WRotor.iqWRotorRaw3; + } + + + WRotor.iqTimeSensor1 = WRotor.iqWRotorRaw0 + WRotor.iqWRotorRaw1; + WRotor.iqTimeSensor2 = WRotor.iqWRotorRaw2 + WRotor.iqWRotorRaw3; + + // +// // zero? +// if (flag_not_ready_rotor) +// { +// if (*count_zero_discret0) +// (*count_zero_discret)--; +// } +// +// // real zero? +// if (count_zero_discret==MAX_COUNT_OVERFULL_DISCRET) +// { +// // , ! +// WRotor.iqTimeSensor1 = 0; +// WRotor.prev_iqTimeSensor1 = 0; +// } +// else +// { +// // , prev_iqTimeRotor +// if (WRotor.iqTimeSensor1==0) +// WRotor.iqTimeSensor1 = WRotor.prev_iqTimeSensor1; +// } +// WRotor.prev_iqTimeSensor1 = WRotor.iqTimeSensor1; +// +// +// // max OVERFULL +// if (flag_overfull_rotor) +// { +// if (*count_overfull_discret0) +// (*count_overfull_discret)--; +// } +// +// // zero? +// if (flag_not_ready_rotor) +// { +// if (*count_zero_discret0) +// (*count_zero_discret)--; +// } +// +// // real zero? +// if (*count_zero_discret==MAX_COUNT_OVERFULL_DISCRET) +// { +// // , ! +// iqWRotorCalc = 0; +// *prev_iqTimeRotor = 0; +// iqTimeRotor = 0; +// } +// else +// { +// // , prev_iqTimeRotor +// if (iqTimeRotor==0) +// iqTimeRotor = *prev_iqTimeRotor; +// } +// *prev_iqTimeRotor = iqTimeRotor; +// +// +// + +/// + if (WRotor.iqTimeSensor1 != 0 && inc_sensor.use_sensor1) + { + if (inc_sensor.pm67regs.read_comand_reg.bit.sampling_time1==0) + WRotor.iqWRotorCalcBeforeRegul1 = KoefNormMS / WRotor.iqTimeSensor1; + if (inc_sensor.pm67regs.read_comand_reg.bit.sampling_time1==1) + WRotor.iqWRotorCalcBeforeRegul1 = KoefNormNS / WRotor.iqTimeSensor1; + + if (WRotor.iqWRotorCalcBeforeRegul1 > max_value_rotor) + { + WRotor.iqWRotorCalc1 = 0; + WRotor.iqWRotorCalcBeforeRegul1 = 0; + } + else + WRotor.iqWRotorCalc1 = exp_regul_iq(koefW, WRotor.iqWRotorCalc1, WRotor.iqWRotorCalcBeforeRegul1); + + ///// + if (WRotor.iqWRotorCalc1) + { + if (WRotor.iqPrevWRotorCalc1 != WRotor.iqWRotorCalc1) + { + WRotor.iqWRotorCalc1Ramp = zad_intensiv_q(wrotor_add_ramp, wrotor_add_ramp, WRotor.iqWRotorCalc1Ramp, WRotor.iqWRotorCalc1); + WRotor.iqPrevWRotorCalc1 = WRotor.iqWRotorCalc1; + } + } + else + { + WRotor.iqPrevWRotorCalc1 = 0; + WRotor.iqWRotorCalc1Ramp = 0; + } + //// + } + else + { + WRotor.iqWRotorCalc1 = 0; + WRotor.iqWRotorCalcBeforeRegul1 = 0; + } +/// + if (WRotor.iqTimeSensor2 != 0 && inc_sensor.use_sensor2) + { + if (inc_sensor.pm67regs.read_comand_reg.bit.sampling_time2==0) + WRotor.iqWRotorCalcBeforeRegul2 = KoefNormMS / WRotor.iqTimeSensor2; + if (inc_sensor.pm67regs.read_comand_reg.bit.sampling_time2==1) + WRotor.iqWRotorCalcBeforeRegul2 = KoefNormNS / WRotor.iqTimeSensor2; + + if (WRotor.iqWRotorCalcBeforeRegul2 > max_value_rotor) + { + WRotor.iqWRotorCalc2 = 0; + WRotor.iqWRotorCalcBeforeRegul2 = 0; + } + else + WRotor.iqWRotorCalc2 = exp_regul_iq(koefW, WRotor.iqWRotorCalc2, WRotor.iqWRotorCalcBeforeRegul2); + + + + ///// + if (WRotor.iqWRotorCalc2) + { + if (WRotor.iqPrevWRotorCalc2 != WRotor.iqWRotorCalc2) + { + WRotor.iqWRotorCalc2Ramp = zad_intensiv_q(wrotor_add_ramp, wrotor_add_ramp, WRotor.iqWRotorCalc2Ramp, WRotor.iqWRotorCalc2); + WRotor.iqPrevWRotorCalc2 = WRotor.iqWRotorCalc2; + } + } + else + { + WRotor.iqPrevWRotorCalc2 = 0; + WRotor.iqWRotorCalc2Ramp = 0; + } + //// + } + else + { + WRotor.iqWRotorCalc2 = 0; + WRotor.iqWRotorCalcBeforeRegul2 = 0; + } +/// + if (inc_sensor.data.TimeCalcFromImpulses1 && inc_sensor.use_sensor1) + WRotor.iqWRotorImpulsesBeforeRegul1 = (long long) KoefNormImpulses / (inc_sensor.data.TimeCalcFromImpulses1 * ROTOR_SENSOR_IMPULSES_PER_ROTATE); + else + WRotor.iqWRotorImpulsesBeforeRegul1 = 0; + + WRotor.iqWRotorImpulses1 = exp_regul_iq(koefW, WRotor.iqWRotorImpulses1, WRotor.iqWRotorImpulsesBeforeRegul1); + + if (inc_sensor.data.TimeCalcFromImpulses2 && inc_sensor.use_sensor2) + WRotor.iqWRotorImpulsesBeforeRegul2 = (long long) KoefNormImpulses / (inc_sensor.data.TimeCalcFromImpulses2 * ROTOR_SENSOR_IMPULSES_PER_ROTATE); + else + WRotor.iqWRotorImpulsesBeforeRegul2 = 0; + + WRotor.iqWRotorImpulses2 = exp_regul_iq(koefW, WRotor.iqWRotorImpulses2, WRotor.iqWRotorImpulsesBeforeRegul2); + + + // WRotor.iqWRotorCalcBeforeRegul = _IQdiv(WRotor.iqWRotorCalcBeforeRegul,IQ_CONST_3); +} +#define LEVEL_SWITCH_TO_GET_IMPULSES_OBOROTS 50 // Oborot +void select_values_wrotor(void) +{ + static _iq level_switch_to_get_impulses_hz = _IQ(LEVEL_SWITCH_TO_GET_IMPULSES_OBOROTS/60.0/NORMA_FROTOR); + static unsigned int prev_RotorDirectionInstant = 0; + static unsigned int status_RotorRotation = 0; // ? + static _iq wrotor_add = _IQ(0.002/NORMA_FROTOR); + + + + + if (WRotor.iqWRotorCalc1>level_switch_to_get_impulses_hz + || WRotor.iqWRotorCalc2>level_switch_to_get_impulses_hz) + { + // + if (WRotor.iqWRotorImpulses1 || WRotor.iqWRotorImpulses2) + { + if(WRotor.iqWRotorImpulses1>WRotor.iqWRotorImpulses2) + WRotor.iqWRotorSum = WRotor.iqWRotorImpulsesBeforeRegul1; + else + WRotor.iqWRotorSum = WRotor.iqWRotorImpulsesBeforeRegul2; + } + else + { + if(WRotor.iqWRotorCalc1>WRotor.iqWRotorCalc2) + WRotor.iqWRotorSum = WRotor.iqWRotorCalcBeforeRegul1; + else + WRotor.iqWRotorSum = WRotor.iqWRotorCalcBeforeRegul2; + } + + + } + else + { + if(WRotor.iqWRotorCalc1>WRotor.iqWRotorCalc2) + WRotor.iqWRotorSum = WRotor.iqWRotorCalcBeforeRegul1; + else + WRotor.iqWRotorSum = WRotor.iqWRotorCalcBeforeRegul2; + + } + + + // +// if (prev_prev_RotorDirectionInstant && WRotorPBus.RotorDirectionSlow) +// if (WRotor.iqWRotorSum) +// { +// inc_sensor.break_direction = 1; +// } +// prev_prev_RotorDirectionInstant = WRotorPBus.RotorDirectionSlow; + + + +//// !!! +// if (WRotorPBus.RotorDirectionSlow==0) +// { +// if (WRotor.iqWRotorSum) +// inc_sensor.break_direction = 1; +// } +// else +// inc_sensor.break_direction = 0; + + +// if (WRotorPBus.RotorDirectionSlow==0) +// { +// // 0 !!! !!! +// WRotor.iqWRotorSumFilter = exp_regul_iq(koefW, WRotor.iqWRotorSumFilter, 0); +// } +// else + + + WRotor.iqWRotorSumFilter = exp_regul_iq(koefW, WRotor.iqWRotorSumFilter, WRotor.iqWRotorSum*WRotorPBus.RotorDirectionSlow); + + WRotor.iqWRotorSumRamp = zad_intensiv_q(wrotor_add, wrotor_add, WRotor.iqWRotorSumRamp, WRotor.iqWRotorSumFilter); + + + WRotor.iqWRotorSumFilter2 = exp_regul_iq(koefW2, WRotor.iqWRotorSumFilter2, WRotor.iqWRotorSumFilter); + WRotor.iqWRotorSumFilter3 = exp_regul_iq(koefW3, WRotor.iqWRotorSumFilter3, WRotor.iqWRotorSumFilter); + +} + + +#pragma CODE_SECTION(RotorMeasure,".fast_run"); +void RotorMeasureDetectDirection(void) +{ + int direction1, direction2, sum_direct; + + direction1 = project.cds_in[0].read.pbus.direction_in.bit.dir_sens_1 == ROTOR_SENSOR_CODE_CLOCKWISE ? 1 : + project.cds_in[0].read.pbus.direction_in.bit.dir_sens_1 == ROTOR_SENSOR_CODE_COUNTERCLOCKWISE ? -1 : + 0; + + direction2 = project.cds_in[0].read.pbus.direction_in.bit.dir_sens_2 == ROTOR_SENSOR_CODE_COUNTERCLOCKWISE ? 1 : + project.cds_in[0].read.pbus.direction_in.bit.dir_sens_2 == ROTOR_SENSOR_CODE_CLOCKWISE ? -1 : + 0; + + sum_direct = (direction1 + direction2) > 0 ? 1 : + (direction1 + direction2) < 0 ? -1 : + 0; + + WRotorPBus.RotorDirectionInstant = sum_direct; + +} + + +/////////////////////////////////////////////////////////////// + +#endif + + + +/////////////////////////////////////////////////////////////// + +#pragma CODE_SECTION(update_rot_sensors,".fast_run"); +void update_rot_sensors(void) +{ + inc_sensor.update_sensors(&inc_sensor); +} +/////////////////////////////////////////////////////////////// diff --git a/Inu/Src2/551/main/v_rotor.h b/Inu/Src2/551/main/v_rotor.h new file mode 100644 index 0000000..aad2216 --- /dev/null +++ b/Inu/Src2/551/main/v_rotor.h @@ -0,0 +1,185 @@ +#ifndef V_ROTOR_H +#define V_ROTOR_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "params_bsu.h" + + +// +#define ROTOR_SENSOR_CODE_CLOCKWISE 2 // +#define ROTOR_SENSOR_CODE_COUNTERCLOCKWISE 1 // + +// +//#define ROTOR_SENSOR_CODE_CLOCKWISE 1 // +//#define ROTOR_SENSOR_CODE_COUNTERCLOCKWISE 2 // + + +void update_rot_sensors(void); +void RotorMeasure(void); +void RotorMeasurePBus(void); +void rotorInit(void); +void select_values_wrotor(void); + + +void RotorDirectionFilter(int RotorDirectionIn, int *RotorDirectionOut, int *RotorDirectionOut2, int *count_direction); + +int AnalisatorRotorSensorPBus(_iq d1, _iq d2, unsigned int *count_overfull_discret, unsigned int *count_zero_discret, _iq *prev_iqTimeRotor, + unsigned int *discret_out, unsigned int discret_in, _iq *iqWRotorCalcBeforeRegul, _iq *iqWRotorCalc, + int modeS1, int modeS2, + int valid_sensor_direct, int valid_sensor_90, + unsigned int *error_count); + +void RotorMeasureDetectDirection(void); + + +typedef struct +{ + _iq iqWRotorRaw0; + _iq iqWRotorRaw1; + _iq iqWRotorRaw2; + _iq iqWRotorRaw3; + + _iq iqWRotorFilter0; + _iq iqWRotorFilter1; + _iq iqWRotorFilter2; + _iq iqWRotorFilter3; + + _iq iqWRotorDelta; + + _iq iqTimeSensor1; + _iq iqTimeSensor2; + + _iq prev_iqWRotorRaw0; + _iq prev_iqWRotorRaw1; + _iq prev_iqWRotorRaw2; + _iq prev_iqWRotorRaw3; + + unsigned int count_zero_discret0; + unsigned int count_zero_discret1; + unsigned int count_zero_discret2; + unsigned int count_zero_discret3; + + + _iq iqWRotorCalc1; + _iq iqWRotorCalcBeforeRegul1; + _iq iqWRotorCalc2; + _iq iqWRotorCalcBeforeRegul2; + +// int RotorDirectionInstant; +// int RotorDirectionSlow; + + _iq iqWRotorImpulses1; + _iq iqWRotorImpulsesBeforeRegul1; + _iq iqWRotorImpulses2; + _iq iqWRotorImpulsesBeforeRegul2; + + _iq iqWRotorSum; + _iq iqWRotorSumFilter; + _iq iqWRotorSumFilter2; + _iq iqWRotorSumFilter3; + + _iq iqWRotorSumRamp; + + _iq iqWRotorCalc1Ramp; + _iq iqPrevWRotorCalc1; + _iq iqWRotorCalc2Ramp; + _iq iqPrevWRotorCalc2; + + int RotorDirectionSlow; + +} WRotorValues; + +#define WRotorValues_DEFAULTS {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0, 0,0,0,0, 0} + +typedef struct +{ + _iq iqWRotorRaw0; + _iq iqWRotorRaw1; + _iq iqWRotorRaw2; + _iq iqWRotorRaw3; + + + _iq iqWRotorFilter0; + _iq iqWRotorFilter1; + _iq iqWRotorFilter2; + _iq iqWRotorFilter3; + + _iq iqWRotorDelta; +// _iq iqWRotorCalcBeforeRegul; + + _iq iqWRotorCalcBeforeRegul1; + _iq iqWRotorCalcBeforeRegul2; + + _iq iqTimeRotor1; + _iq iqTimeRotor2; + + _iq iqTimeRotor; + + + _iq iqWRotorCalc1; + _iq iqWRotorCalc2; +// _iq iqWRotorCalc; + + int ModeAutoDiscret; + + int RotorDirectionInstant; + int RotorDirectionSlow; + int RotorDirectionCount; + int RotorDirectionSlow2; + + + +#if (ENABLE_ROTOR_SENSOR_ZERO_SIGNAL==1) + _iq iqWRotorRawAngle1F; + _iq iqWRotorRawAngle1R; + _iq iqWRotorRawAngle2F; + _iq iqWRotorRawAngle2R; + + _iq iqAngle1F; + _iq iqAngle1R; + + _iq iqAngle2F; + _iq iqAngle2R; + + _iq iqAngleCalc; + +#endif + +} WRotorValuesAngle; + +#if (ENABLE_ROTOR_SENSOR_ZERO_SIGNAL==1) +#define WRotorValuesAngle_DEFAULTS {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} +#else +#define WRotorValuesAngle_DEFAULTS {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0} +#endif + +extern WRotorValues WRotor; +extern WRotorValuesAngle WRotorPBus; + + + + + + +//#define NORMA_WROTOR 15 + +#define IQ_WROTOR_MAX_MIN_DELTA 3744914286 //17920 + + +#define WRMP_COEF 0.001 // 0.24 Hz per sec + +#define IQ_CONST_3 50331648 + +#define COUNT_DECODER_ZERO_WROTORPBus 65535 //0x00fe5000//0x01fca000 +#define COUNT_DECODER_ZERO_WROTOR 65500 //0x00fe5000//0x01fca000 +#define COUNT_DECODER_MAX_WROTOR 10 + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Inu/Src2/551/main/v_rotor_22220.c b/Inu/Src2/551/main/v_rotor_22220.c new file mode 100644 index 0000000..c31de31 --- /dev/null +++ b/Inu/Src2/551/main/v_rotor_22220.c @@ -0,0 +1,666 @@ + +#include "DSP281x_Examples.h" // DSP281x Examples Include File +#include "DSP281x_SWPrioritizedIsrLevels.h" // DSP281x Examples Include File +#include "DSP281x_Device.h" // DSP281x Headerfile Include File +#include "IQmathLib.h" + +#include "params_bsu.h" +#include "v_rotor.h" + +#include "filter_v1.h" +#include "xp_cds_in.h" + +#include "xp_inc_sensor.h" +#include "xp_project.h" +#include "params.h" + +//#include "pwm_test_lines.h" +#include "params_norma.h" +#include "edrk_main.h" +#include "params_pwm24.h" +#include "v_rotor_22220.h" + +#include "rmp_cntl_v1.h" +#include "mathlib.h" + + +//#define _ENABLE_PWM_LED2_PROFILE 1 + +#if (_ENABLE_PWM_LED2_PROFILE) +extern unsigned int profile_pwm[30]; +extern unsigned int pos_profile_pwm; +#endif + +// +//#pragma DATA_SECTION(buf1,".logs2") +//int buf1[SIZE_BUF_W]; +//#pragma DATA_SECTION(buf2,".logs2") +//int buf2[SIZE_BUF_W]; +//#pragma DATA_SECTION(buf3,".logs2") +//int buf3[SIZE_BUF_W]; +//#pragma DATA_SECTION(buf4,".logs2") +//int buf4[SIZE_BUF_W]; +//#pragma DATA_SECTION(buf5,".logs2") +//int buf5[SIZE_BUF_W]; +//#pragma DATA_SECTION(buf6,".logs2") +//int buf6[SIZE_BUF_W]; +//#pragma DATA_SECTION(buf7,".logs2") +//int buf7[SIZE_BUF_W]; +//#pragma DATA_SECTION(buf8,".logs2") +//int buf8[SIZE_BUF_W]; +// + +/////////////////////////////////////////////// +/////////////////////////////////////////////// +/////////////////////////////////////////////// +RMP_V1 rmp_wrot = RMP_V1_DEFAULTS; + +#pragma DATA_SECTION(rotor_22220,".fast_vars"); +ROTOR_VALUE_22220 rotor_22220 = ROTOR_VALUE_22220_DEFAULTS; + + +void rotorInit_22220(void) +{ + unsigned int i = 0, size = 0, *pint = 0; + + rmp_wrot.RampLowLimit = 0; + rmp_wrot.RampHighLimit = _IQ(1.0); + rmp_wrot.RampPlus = _IQ(0.0015/NORMA_FROTOR); + rmp_wrot.RampMinus = _IQ(-0.0015/NORMA_FROTOR); + rmp_wrot.DesiredInput = 0; + rmp_wrot.Out = 0; + + +// pint = (unsigned int*)&rotor; +// size = sizeof(rotor) / sizeof(unsigned int); +// for(i = 0; i < size; i++) +// { +// *(pint + i) = 0; +// } + +} + +_iq koef_Wout_filter = _IQ(0.2); //_IQ(0.15); +_iq koef_Wout_filter_long = _IQ(0.001);//_IQ(0.03); + +#define SIZE_BUF_F1 10 +#pragma DATA_SECTION(f1,".slow_vars") +static _iq f1[SIZE_BUF_F1]={0,0,0,0,0,0,0,0,0,0}; +#pragma DATA_SECTION(f1_int,".slow_vars") +static long f1_int[SIZE_BUF_F1]={0,0,0,0,0,0,0,0,0,0}; + +#pragma CODE_SECTION(clear_iqFsensors,".fast_run"); +void clear_iqFsensors(void) +{ + int i; + + for (i=0;i=(SIZE_BUF_W-1)) +// { +// flag_buf = 0; +// c_s = 0; +// } +// else +// c_s++; +// +// +// buf1[c_s] = inc_sensor.data.CountOne1;// rotation_sensor.in_plane.out.CountOne1; +// buf2[c_s] = inc_sensor.data.CountZero1;//rotation_sensor.in_plane.out.CountZero1; +// buf3[c_s] = inc_sensor.data.CountOne2;//rotation_sensor.in_plane.out.CountOne2; +// buf4[c_s] = inc_sensor.data.CountZero2;//rotation_sensor.in_plane.out.CountZero2; +// buf5[c_s] = direction1;//inc_sensor.data.;//(rotation_sensor.in_plane.out.direction1); +// buf6[c_s] = direction2;//(rotation_sensor.in_plane.out.direction2); +// buf7[c_s] = (project.cds_in[0].read.pbus.direction_in.bit.dir_sens_1); +// buf8[c_s] = (project.cds_in[0].read.pbus.direction_in.bit.dir_sens_2); +// +// } +// prev_flag_buf = flag_buf; + + +#if (_ENABLE_PWM_LED2_PROFILE) + if (profile_pwm[pos_profile_pwm++]) + i_led2_on_off(1); + else + i_led2_on_off(0); +#endif + + + if(inc_sensor.use_sensor1) + { + if((inc_sensor.data.CountOne1 <= 200)// && !rotation_sensor.in_plane.out.counter_freq1) + || inc_sensor.data.CountOne1 == 65535) + { inc_sensor.data.CountOne1 = 0; } + if((inc_sensor.data.CountZero1 <= 200)// && !rotation_sensor.in_plane.out.counter_freq1) + || inc_sensor.data.CountZero1 == 65535) + { inc_sensor.data.CountZero1 = 0; } + + // + if (inc_sensor.data.Impulses1 < 5) { + + if(inc_sensor.data.CountOne1 && inc_sensor.data.CountZero1 ) + { + sum_count = (long)inc_sensor.data.CountOne1 + (long)inc_sensor.data.CountZero1; + + if (s_number3 2) + { + if (s_number 139810L)//10 rpm + { + if (inc_sensor.data.CountOne1 == 0 && inc_sensor.data.CountZero1 == 0 + && inc_sensor.data.Impulses1 == 0) { + sens1_err_count += 1; + } else { + sens1_err_count = 0; + } + if (sens1_err_count > 50) { + sens1_err_count = 50; + edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 1; +// faults.faults4.bit.Speed_Datchik_1_Off |= 1; + } + } else { + sens1_err_count = 0; + edrk.warnings.e9.bits.SENSOR_ROTOR_1_BREAK = 0; + } + } + + +#if (_ENABLE_PWM_LED2_PROFILE) + if (profile_pwm[pos_profile_pwm++]) + i_led2_on_off(1); + else + i_led2_on_off(0); +#endif + + +// logpar.log4 = rotation_sensor.in_plane.out.CountOne2; +// logpar.log20 = rotation_sensor.in_plane.out.CountZero2; + if(inc_sensor.use_sensor2) + { + if((inc_sensor.data.CountOne2 <= 200)// && !rotation_sensor.in_plane.out.counter_freq2) + || inc_sensor.data.CountOne2 == 65535) + { inc_sensor.data.CountOne2 = 0; } + if((inc_sensor.data.CountZero2 <= 200)// && !rotation_sensor.in_plane.out.counter_freq2) + || inc_sensor.data.CountZero2 == 65535) + { inc_sensor.data.CountZero2 = 0; } + + // , + if (inc_sensor.data.Impulses2 < 5) { + + if(inc_sensor.data.CountOne2 && inc_sensor.data.CountZero2 ) + { + sum_count = (long)inc_sensor.data.CountOne2+(long)inc_sensor.data.CountZero2; + if (s_number3 2) + { + if (s_number 139810L)//10 rpm + { + if (inc_sensor.data.CountOne2 == 0 && inc_sensor.data.CountZero2 == 0 + && inc_sensor.data.Impulses2 == 0) { + sens2_err_count += 1; + } else { + sens2_err_count = 0; + } + if (sens2_err_count > 50) { + sens2_err_count = 50; +// faults.faults4.bit.Speed_Datchik_2_Off |= 1; + edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 1; + } + } else { + sens2_err_count = 0; + edrk.warnings.e9.bits.SENSOR_ROTOR_2_BREAK = 0; + } + + } + + if(s_number > SENSORS_NUMBER_ONLY_IN) {s_number = SENSORS_NUMBER_ONLY_IN;} //TODO set SENSORS_NUMBER when tune angle measure + if(s_number > 3) + { + sort_F_array(rotor_22220.iqFsensors, s_number); + deltaF = rotor_22220.iqFout >> 2; + if(deltaF < 43000) // ~3 ob/min + { + deltaF = 43000; + } + i = 0; + begin_data = 0; + end_data = s_number; //TODO test, as usial + while(i < s_number) + { + if(_IQabs(rotor_22220.iqFout - rotor_22220.iqFsensors[i]) >= deltaF) + { + i++; + } + else + { + break; + } + } + if(i < s_number) { begin_data = i; } + else {begin_data = 0;} + while((i < s_number) && (_IQabs(rotor_22220.iqFout - rotor_22220.iqFsensors[i]) < deltaF)) + { + i++; + } + if(i <= SENSORS_NUMBER) + { + end_data = i; + } + else + { + end_data = SENSORS_NUMBER; + } + } + else + { + begin_data = 0; + end_data = s_number; + } + if (begin_data >= end_data) { //This part to prevent freeze of speed on some level if signal lost + begin_data = 0; + end_data = s_number; + } + // + for(i = begin_data; i < end_data; i++) + { + accumulator += rotor_22220.iqFsensors[i]; + } + // + if(end_data != begin_data) + { + rotor_22220.iqFdirty = accumulator / (end_data - begin_data); + prev_wrot_count = 0; + } + else + { + rotor_22220.iqFdirty = prev_wrot; + prev_wrot_count += 1; + } + +// logpar.log19 = (int16)(_IQtoIQ15(rotor.iqF)); +// rotor_22220.iqFdirty = rotor_22220.iqF; + + if (prev_wrot != rotor_22220.iqFdirty || rotor_22220.iqFdirty==0 ) + { + rmp_wrot.DesiredInput = rotor_22220.iqFdirty; + rmp_wrot.calc(&rmp_wrot); + rotor_22220.iqF = rmp_wrot.Out; + } + else + { + rotor_22220.iqF = rotor_22220.iqFdirty; + } + prev_wrot=rotor_22220.iqF; + + +#if (_ENABLE_PWM_LED2_PROFILE) + if (profile_pwm[pos_profile_pwm++]) + i_led2_on_off(1); + else + i_led2_on_off(0); +#endif + + + // . + if (prev_wrot_count > 10) { + prev_wrot = 0; + prev_wrot_count = 10; + } + + rotor_22220.iqFout = exp_regul_iq(koef_Wout_filter, rotor_22220.iqFout, rotor_22220.iqF); + rotor_22220.iqFlong = exp_regul_iq(koef_Wout_filter_long, rotor_22220.iqFlong, rotor_22220.iqF); + +#if (_ENABLE_PWM_LED2_PROFILE) + if (profile_pwm[pos_profile_pwm++]) + i_led2_on_off(1); + else + i_led2_on_off(0); +#endif + + + rotor_22220.direct_rotor_in1 = direction1;//rotation_sensor.in_plane.out.direction1; + +#if (_STEND_40MWT==1) + // , .. , !!! + + rotor_22220.direct_rotor_in2 = -rotation_sensor.in_plane.out.direction2; + +#else + + rotor_22220.direct_rotor_in2 = direction2;//rotation_sensor.in_plane.out.direction2; + +#endif + // rotor.direct_rotor_angle = rotation_sensor.rotation_plane.out.direction; + + rotor_22220.error.sens_err1 = sens_err1; + rotor_22220.error.sens_err2 = sens_err2; + +// rotor.direct_rotor = (rotor.direct_rotor_in1 + rotor.direct_rotor_in2) > 0 ? 1 : // + rotor.direct_rotor_angle +// (rotor.direct_rotor_in1 + rotor.direct_rotor_in2) < 0 ? -1 : // + rotor.direct_rotor_angle +// 0; + if(rotor_22220.iqFout >139810L) //10ob/min + { + if((rotor_22220.direct_rotor_in1 + rotor_22220.direct_rotor_in2) > 0) + { + direct_accum++; + } + else if((rotor_22220.direct_rotor_in1 + rotor_22220.direct_rotor_in2) < 0) + { + direct_accum--; + } + else + { + if(direct_accum > 0) {direct_accum--;} + if(direct_accum < 0) {direct_accum++;} + } + if(direct_accum > 60) { direct_accum = 60; } + if(direct_accum < -60) { direct_accum = -60; } + rotor_22220.direct_rotor = direct_accum > 0 ? 1 : + direct_accum < 0 ? -1 : + 0; +// if (f.flag_second_PCH) { +// rotor.direct_rotor = - rotor.direct_rotor; +// } + } + else + { + rotor_22220.direct_rotor = (rotor_22220.direct_rotor_in1 + rotor_22220.direct_rotor_in2) > 0 ? 1 : // + rotor.direct_rotor_angle + (rotor_22220.direct_rotor_in1 + rotor_22220.direct_rotor_in2) < 0 ? -1 : // + rotor.direct_rotor_angle + 0; +// if (f.flag_second_PCH) { +// rotor.direct_rotor = - rotor.direct_rotor; +// } + direct_accum = rotor_22220.direct_rotor; + } + +// if(rotation_sensor.in_plane.write.regs.comand_reg.bit.set_sampling_time) // +// { +// rotation_sensor.in_plane.write.regs.comand_reg.bit.filter_sensitivity = 0x5C; +// } +// else // , +// { +// rotation_sensor.in_plane.write.regs.comand_reg.bit.filter_sensitivity = 0xA8; +// } + if (s_number2 0; i--) + { + for(j = 1; j < size; j++) + { + if(array[j - 1] > array[j]) + { + tmp = array[j]; + array[j] = array[j - 1]; + array[j - 1] = tmp; + } + } + } +} + + +void select_values_wrotor_22220(void) +{ + // static _iq level_switch_to_get_impulses_hz = _IQ(LEVEL_SWITCH_TO_GET_IMPULSES_OBOROTS/60.0/NORMA_FROTOR); + static unsigned int prev_RotorDirectionInstant = 0; + static unsigned int status_RotorRotation = 0; // ? + static _iq wrotor_add = _IQ(0.002/NORMA_FROTOR); + + WRotor.RotorDirectionSlow = rotor_22220.direct_rotor; + WRotor.iqWRotorSum = rotor_22220.iqFout;// * rotor_22220.direct_rotor; + WRotor.iqWRotorSumFilter = rotor_22220.iqFout * rotor_22220.direct_rotor; + WRotor.iqWRotorSumFilter2 = rotor_22220.iqFlong * rotor_22220.direct_rotor; + WRotor.iqWRotorSumFilter3 = rotor_22220.iqFlong * rotor_22220.direct_rotor; + WRotor.iqWRotorSumRamp = zad_intensiv_q(wrotor_add, wrotor_add, WRotor.iqWRotorSumRamp, WRotor.iqWRotorSumFilter); + + +} diff --git a/Inu/Src2/551/main/v_rotor_22220.h b/Inu/Src2/551/main/v_rotor_22220.h new file mode 100644 index 0000000..aec28c5 --- /dev/null +++ b/Inu/Src2/551/main/v_rotor_22220.h @@ -0,0 +1,54 @@ +#ifndef V_ROTOR_22220_H +#define V_ROTOR_22220_H + +#define SIZE_BUF_W 100 //2000 + +/////// 22220.5 +#define SENSORS_NUMBER 10 +#define SENSORS_NUMBER_ONLY_IN 6 +//#define IMPULSES_PER_TURN (1LL << 13) //Old sensor +#define IMPULSES_PER_TURN 4096 //Lira sensor +//#define ANGLE_RESOLUTION (1LL << 18) //2^18 + +typedef struct +{ + int direct_rotor; + int direct_rotor_in1; + int direct_rotor_in2; + int direct_rotor_angle; + union { + unsigned int sens_err1:1; + unsigned int sens_err2:1; + unsigned int reserved:14; + } error; + + _iq iqFsensors[SENSORS_NUMBER]; + + + _iq iqFdirty; + _iq iqF; + _iq iqFout; + _iq iqFlong; + + _iq iqFrotFromOptica; + + unsigned int error_update_count; +} ROTOR_VALUE_22220; + +#define ROTOR_VALUE_22220_DEFAULTS {0,0,0,0,0, {0,0,0,0,0,0,0,0},0,0,0,0,0,0} + + +_iq counter_To_iqF2(long count, unsigned int freq_mode); +void sort_F_array(_iq *array, unsigned int size); +_iq impulses_To_iqF(unsigned int time, unsigned int impulses); //time mks. impulses count +void Rotor_measure_22220(void); +void rotorInit_22220(void); +void select_values_wrotor_22220(void); + +extern ROTOR_VALUE_22220 rotor_22220; + +extern _iq koef_Wout_filter, koef_Wout_filter_long; + + +#endif + diff --git a/Inu/Src2/551/main/vector.h b/Inu/Src2/551/main/vector.h new file mode 100644 index 0000000..25bc4f1 --- /dev/null +++ b/Inu/Src2/551/main/vector.h @@ -0,0 +1,254 @@ +/* + ???? ??? (?) 2006 ?. + + Processor: TMS320C32 + + Filename: vector_troll.h + + ??????? ?????????? ?????????y + + Edit date: 04-12-02 + + Function: + + Revisions: +*/ + + +#ifndef _VECTOR_SEV +#define _VECTOR_SEV + + +#ifdef __cplusplus + extern "C" { +#endif + + +#include "IQmathLib.h" +#include "x_basic_types.h" + +typedef struct +{ + float W; /* */ + float Angle; /* */ + float Phi; /* */ + float k; /* . */ + float k1; /* . */ + float k2; /* . */ + float f; /* */ + + _iq iqk; + _iq iqk1; + _iq iqk2; + _iq iqf; + + + +} WINDING; + +#define WINDING_DEFAULT {0,0,0,0,0,0,0,0,0,0,0} + + +typedef struct +{ + unsigned int Prepare; + unsigned int terminal_prepare; + unsigned int Test_Lamps; + unsigned int fault; + + + + unsigned int Stop; + unsigned int Mode; + unsigned int Revers; + unsigned int Is_Blocked; + + unsigned int Ready1; + unsigned int Ready2; + unsigned int Discharge; + unsigned int Assemble; + + unsigned int ErrorChannel1; + unsigned int ErrorChannel2; + unsigned int FaultChannel1; + unsigned int FaultChannel2; + + unsigned int Set_power; + + unsigned int Impuls; + + unsigned int Obmotka1; + unsigned int Obmotka2; +// unsigned int Down50; + + unsigned int I_over_nominal; //????????? ?????? ?????? ? ??????????? ???????????? ???? + unsigned int Moment_over_1_6_noninal; //????????? ?????? ?????? ? ??????????? ???????????? ??????? ? 1.6 ??? + unsigned int Moment_over_1_8_nominal; //????????? ?????? ?????? ? ??????????? ???????????? ??????? ? 1.8 ??? + unsigned int DownToNominal; + unsigned int DownToNominalMoment; + unsigned int Down50Temperature; + unsigned int nominal_I_exceeded_counter; //??????? ??? ????????? ??????????? ??? + unsigned int nominal_M_exceeded_counter; //??????? ??? ????????? ??????????? ?????? + + unsigned int Up50; + unsigned int Ciclelog; + unsigned int Provorot; + unsigned int Bpsi; + unsigned int Piregul1; + unsigned int Piregul2; + unsigned int Startstoplog; + unsigned int Setspeed; + + unsigned int BWC_is_ON; + + unsigned int Setsdvigfaza; + unsigned int Off_piregul; + + unsigned int Restart; + unsigned int Log1_Log2; + + unsigned int Work_net; + unsigned int Mask_impuls; + unsigned int Impuls_width; + + + unsigned int Work; + + unsigned int Auto; + + unsigned int Uzad; + unsigned int Umin; + +// unsigned int RScount; + unsigned int vector_run; + unsigned int test_all_run; + + unsigned int decr_mzz_temp; +// unsigned int flag_decr_mzz_temp; + + unsigned int flag_Break_Resistor_Error; + unsigned int flag_local_control; //1 - local + unsigned int flag_leading; //??????? ?? ?????? + unsigned int flag_second_leading; //?????? ?? ?????? + unsigned int flag_distance; + unsigned int flag_kvitirovanie; + unsigned int flag_batary_loaded; + unsigned int flag_Pump_Is_On; + unsigned int power_units_doors_closed; + unsigned int power_units_doors_locked; + + unsigned int flag_decr_mzz_power; + + real decr_mzz_power; + _iq iq_decr_mzz_power; + + _iq iq_decr_mzz_voltage; + + real fzad; + real kzad; + real kzad_plus; +// real fzad_provorot; + real Sdvigfaza; +// real k_3garonica; +// _iq iq_k_3garonica; +// real bpsi_zad; + +// real Piregul1_p; +// real Piregul1_i; + +// real Piregul2_p; +// real Piregul2_i; + + + real mzz_zad; + real fr_zad; + real Power; + real p_zad; + + +// _iq iq_bpsi_zad; + _iq iq_mzz_zad; +// _iq iq_fzad_provorot; + _iq iq_fzad; + + _iq iq_p_zad; + + unsigned int flag_Enable_Prepare; + + + unsigned int status_MODE_WORK_SVU; + unsigned int status_MODE_WORK_MPU; + unsigned int status_MODE_WORK_VPU; +// unsigned int status_MODE_WORK_EVPU; + +// unsigned int filter_READY_UKSS_BV1; +// unsigned int filter_READY_UKSS_BV2; +// unsigned int filter_READY_UKSS_BI1; +// unsigned int filter_READY_UKSS_BI2; + unsigned int filter_READY_UMU; +// unsigned int filter_READY_UKSS_UKSI; + + unsigned int On_Power_QTV; + + unsigned int RS_MPU_ERROR; +// unsigned int CAN_MPU_ERROR; + +// unsigned int enable_fast_prepare; + +// unsigned int tau_break1; +// unsigned int tau_break2; + + unsigned int flag_tormog; + +// unsigned int GoPWM; + + int special_test_from_mpu; + + int MessageToCan1; + int MessageToCan2; + int flag_change_pwm_freq; + int flag_random_freq; + long tmp; + + + + + + +//optical bus data + unsigned int read_task_from_optical_bus; + + + + unsigned int count_wait_after_kvitir; + unsigned int flag_record_log; + unsigned int count_step_ram_off; + unsigned int count_start_impuls; + + int flag_send_alarm_log_to_MPU; + + +} FLAG; + +#define FLAG_DEFAULTS {\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0,0,0,0,0,\ + 0,0,0,0,0,0\ + } +extern FLAG f; +//extern WINDING a; + +#ifdef __cplusplus + } +#endif + +#endif /* _VECTOR_SEV */ + + diff --git a/Inu/Src2/551/main/xPlatesAddress.h b/Inu/Src2/551/main/xPlatesAddress.h new file mode 100644 index 0000000..fa0a62c --- /dev/null +++ b/Inu/Src2/551/main/xPlatesAddress.h @@ -0,0 +1,21 @@ +#ifndef _XPLATESADDRESS_H +#define _XPLATESADDRESS_H + + #define ADC_0_addr 7 + #define ADC_1_addr 8 + + #define TK_0_addr 5 + #define TK_1_addr 6 + #define TK_2_addr 9 + #define TK_3_addr 10 + + #define IN_0_addr 2 + #define IN_1_addr 3 + #define IN_2_addr 4 + + #define OUT_0_addr 11 + #define OUT_1_addr 12 + + #define RotPlane_addr 14 + +#endif diff --git a/Inu/controller.c b/Inu/controller.c index e306f9b..bdbf105 100644 --- a/Inu/controller.c +++ b/Inu/controller.c @@ -13,12 +13,14 @@ #include "wrapper_inu.h" #include "def.h" #include "controller.h" -#include "pwm_vector_regul.h" +#include "edrk_main.h" +#include "vector.h" +#include "vector_control.h" extern UMotorMeasure motor; -extern TimerSimHandle t1sim +extern TimerSimHandle t1sim; extern TimerSimHandle t2sim; extern TimerSimHandle t3sim; extern TimerSimHandle t4sim; @@ -31,7 +33,7 @@ extern TimerSimHandle t10sim; extern TimerSimHandle t11sim; extern TimerSimHandle t12sim; -extern DeadBandSimHandle dt1sim +extern DeadBandSimHandle dt1sim; extern DeadBandSimHandle dt2sim; extern DeadBandSimHandle dt3sim; extern DeadBandSimHandle dt4sim; @@ -54,6 +56,9 @@ int calcAlgUpr = 0; int timers_adc = 0; int timers_pwm = 0; + + + void readInputParameters(const real_T *u) { // int t; //// (begin) diff --git a/Inu/controller.h b/Inu/controller.h index c81e487..d59dfce 100644 --- a/Inu/controller.h +++ b/Inu/controller.h @@ -52,7 +52,7 @@ typedef struct double cmp1A; double cmp1B; }TimerSimHandle; -extern TimerSimHandle t1sim +extern TimerSimHandle t1sim; extern TimerSimHandle t2sim; extern TimerSimHandle t3sim; extern TimerSimHandle t4sim; @@ -100,7 +100,7 @@ typedef struct int ciA_DT; int ciB_DT; }DeadBandSimHandle; -extern DeadBandSimHandle dt1sim +extern DeadBandSimHandle dt1sim; extern DeadBandSimHandle dt2sim; extern DeadBandSimHandle dt3sim; extern DeadBandSimHandle dt4sim; diff --git a/controller.ilk b/controller.ilk new file mode 100644 index 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[%1]==[] (set params_sfunction=.\Inu\%1) -echo %params_f1% +echo %params_sfunction% set params_d1=-D"ML" -D"__IQMATHLIB_H_INCLUDED__" -D"_MATLAB_SIMULATOR" set params_d2=-D"_MATLAB_FAST_SIMULATOR" -D"PROJECT_SHIP=1" @@ -20,40 +20,36 @@ set params_i=-I"..\device_support_ml\include"^ set params_o=-outdir "." -set params_f2=.\Inu\controller.c^ - .\Inu\Src\main_matlab\IQmathLib_matlab.c^ +set params_wrapper_c=.\Inu\controller.c^ .\Inu\Src\main_matlab\main_matlab.c^ - .\Inu\Src\main_matlab\errors_matlab.c^ - .\Inu\Src\main_matlab\adc_tools_matlab.c^ - .\Inu\Src\main\v_pwm24_v2.c^ - .\Inu\Src\N12_Libs\mathlib.c^ - .\Inu\Src\N12_Libs\filter_v1.c^ - .\Inu\Src\N12_Libs\pid_reg3.c^ - .\Inu\Src\N12_Libs\rmp_cntl_v1.c^ - .\Inu\Src\N12_Libs\svgen_dq_v2.c^ - .\Inu\Src\N12_Libs\svgen_mf.c^ - .\Inu\Src\N12_Libs\uf_alg_ing.c^ - .\Inu\Src\N12_Xilinx\xp_write_xpwm_time.c^ - .\Inu\Src\N12_Libs\global_time.c^ - .\Inu\Src\N12_VectorControl\vector_control.c^ - .\Inu\Src\N12_VectorControl\abc_to_dq.c^ + .\Inu\Src\main_matlab\IQmathLib_matlab.c + +set params_vectorcontorl_c=.\Inu\Src\N12_VectorControl\vector_control.c^ + .\Inu\Src\N12_VectorControl\teta_calc.c^ .\Inu\Src\N12_VectorControl\regul_power.c^ .\Inu\Src\N12_VectorControl\regul_turns.c^ - .\Inu\Src\N12_VectorControl\teta_calc.c^ + .\Inu\Src\N12_VectorControl\abc_to_dq.c^ .\Inu\Src\N12_VectorControl\dq_to_alphabeta_cos.c -set params_f3=.\Inu\Src\N12_Libs\modbus_table.c^ - .\Inu\Src\main\detect_overload.c^ - .\Inu\Src\N12_VectorControl\filter_analog.c^ - .\Inu\Src\N12_VectorControl\filter_bat2.c^ - .\Inu\Src\main\PWMTools.c + +set params_libs_c=.\Inu\Src\N12_Libs\mathlib.c^ + .\Inu\Src\N12_Libs\pid_reg3.c^ + .\Inu\Src\N12_Libs\rmp_cntl_v1.c^ + .\Inu\Src\N12_Libs\rmp_cntl_v2.c^ + .\Inu\Src\N12_Libs\filter_v1.c^ + .\Inu\Src\N12_Libs\uf_alg_ing.c^ + .\Inu\Src\N12_Libs\svgen_mf.c^ + .\Inu\Src\N12_Libs\svgen_dq_v2.c^ + .\Inu\Src\N12_Xilinx\xp_write_xpwm_time.c^ + .\Inu\Src\main\adc_tools.c^ + .\Inu\Src\main\v_pwm24_v2.c set params_obj=..\device_support_ml\source\C28x_FPU_FastRTS.obj ..\device_support_ml\source\DSP2833x_GlobalVariableDefs.obj -echo mex %params_d1% %params_d2% %params_i% %params_o% %params_f1% %params_f2% %params_obj% -g +echo mex %params_d1% %params_d2% %params_i% %params_o% %params_sfunction% %params_wrapper_c% %params_vectorcontorl_c% %params_libs_c% %params_obj% -g -mex %params_d1% %params_d2% %params_i% %params_o% %params_f1% %params_f2% %params_obj% -g +mex %params_d1% %params_d2% %params_i% %params_o% %params_sfunction% %params_wrapper_c% %params_vectorcontorl_c% %params_libs_c% %params_obj% -g