diff --git a/Inu/Src/main/v_pwm24_v2.h b/Inu/Src/main/v_pwm24_v2.h
index e0e1baa..fab0949 100644
--- a/Inu/Src/main/v_pwm24_v2.h
+++ b/Inu/Src/main/v_pwm24_v2.h
@@ -54,7 +54,7 @@ typedef struct 	{ //  _iq  Gain;						// Input: reference gain voltage (pu)
 //					_iq delta_t;
 					//int16 Periodmax;
 					//int16 PeriodMin;
-					unsigned int XilinxFreq;	// Xilinx freq in TIC
+					int XilinxFreq;	// Xilinx freq in TIC
 
 					unsigned int pwm_minimal_impuls_zero_plus;
 					unsigned int pwm_minimal_impuls_zero;
diff --git a/Inu/Src/main_matlab/init28335.c b/Inu/Src/main_matlab/init28335.c
index 6298fe1..29cb321 100644
--- a/Inu/Src/main_matlab/init28335.c
+++ b/Inu/Src/main_matlab/init28335.c
@@ -22,10 +22,11 @@ void init28335(void) {
 
     Init_Adc_Variables();
 
-    //svgen_pwm24_1.phase_sequence = SIMULINK_SEQUENCE;
-    //svgen_pwm24_2.phase_sequence = SIMULINK_SEQUENCE;
+    svgen_pwm24_1.phase_sequence = SIMULINK_SEQUENCE;
+    svgen_pwm24_2.phase_sequence = SIMULINK_SEQUENCE;
 
-    edrk.zadanie.iq_Izad = _IQ(1);
+    edrk.zadanie.iq_Izad = _IQ(0.5);
+    edrk.disable_alg_u_disbalance = 1;
     //analog_zero.iqU_1 = 2048;
     //analog_zero.iqU_2 = 2048;
 } //void init28335(void)
diff --git a/Inu/Src/main_matlab/param.c b/Inu/Src/main_matlab/param.c
index d9c5bd7..312a415 100644
--- a/Inu/Src/main_matlab/param.c
+++ b/Inu/Src/main_matlab/param.c
@@ -33,8 +33,8 @@ void readInputParameters(const real_T *u) {
 	u[nn++];
 	edrk.Mode_ScalarVectorUFConst = ALG_MODE_FOC_OBOROTS;
 
-	edrk.zadanie.iq_power_zad = _IQ(u[nn++]);
-	edrk.zadanie.iq_oborots_zad_hz = _IQ(u[nn++]);
+	edrk.zadanie.iq_power_zad = _IQ(0.5);
+	edrk.zadanie.iq_oborots_zad_hz = _IQ(0.5);
 
 	edrk.MasterSlave = MODE_MASTER;
 	edrk.master_theta;
diff --git a/Inu/def.h b/Inu/def.h
index 638e5f4..7babedb 100644
--- a/Inu/def.h
+++ b/Inu/def.h
@@ -11,13 +11,13 @@
 // раскомментировать, если есть сдвиг между обмотками ГЭД (30 град.)
 #define SHIFT
 
-#define SIMULINK_SEQUENCE	V_PWM24_PHASE_SEQ_REVERS_BAC
-/*		V_PWM24_PHASE_SEQ_NORMAL_ABC,
-        V_PWM24_PHASE_SEQ_NORMAL_BCA,
-        V_PWM24_PHASE_SEQ_NORMAL_CAB,
-        V_PWM24_PHASE_SEQ_REVERS_ACB,
-        V_PWM24_PHASE_SEQ_REVERS_CBA,
-        V_PWM24_PHASE_SEQ_REVERS_BAC
+#define SIMULINK_SEQUENCE	V_PWM24_PHASE_SEQ_NORMAL_BCA
+/*		V_PWM24_PHASE_SEQ_NORMAL_ABC, - не то
+        V_PWM24_PHASE_SEQ_NORMAL_BCA, - похоже на правду
+        V_PWM24_PHASE_SEQ_NORMAL_CAB, - жопа
+        V_PWM24_PHASE_SEQ_REVERS_ACB, - жопа
+        V_PWM24_PHASE_SEQ_REVERS_CBA, - жопа
+        V_PWM24_PHASE_SEQ_REVERS_BAC  - жопа
 		*/
 
 // режимы работы (для state)
diff --git a/Inu/pwm_sim.c b/Inu/pwm_sim.c
index ecc2b63..d0fb945 100644
--- a/Inu/pwm_sim.c
+++ b/Inu/pwm_sim.c
@@ -74,10 +74,10 @@ void SimulatePWM(TimerSimHandle* tsim, int compare)
 {
 	simulateTimAndGetCompare(tsim, compare);
 	simulateActionActionQualifierSubmodule(tsim);
-	tsim->ciA = tsim->dtsim.ciA_DT;
-	tsim->ciB = tsim->dtsim.ciB_DT;
-	//simulateDeadBendSubmodule(tsim);
-	//simulateTripZoneSubmodule(tsim);
+	//tsim->ciA = tsim->dtsim.ciA_DT;
+	//tsim->ciB = tsim->dtsim.ciB_DT;
+	simulateDeadBendSubmodule(tsim);
+	simulateTripZoneSubmodule(tsim);
 }