Logic inputs in a native Scope UI

include/logic_scope.h is the portable, allocation-free C model for eight logic inputs and PWM duty reconstruction. The FPGA register mapping and framebuffer UI belong to the board application.

LogicScope: bounded sample buffer, per-channel OFF/LOGIC/PWM mode, sample clock/divider, capture origin, and retained snapshot.
logic_scope_plan: chooses a count/divider for a requested duration; limits are 65,536 samples and divider 65,535. Longer requested intervals produce shorter captures; the UI must not stretch them to fill the view.
logic_scope_pwm: emits midpoint/value pairs for complete active-high PWM periods. Value is 2 * high_samples / period_samples - 1. Initial and final incomplete periods are omitted; constant levels have no PWM period and emit no points. This is normalized modulation, not voltage.

The RK7020 consumer is zynq_7020_OSC/demo/hdmi_usb_menu/. Its tests/test_logic_scope.c checks the capture plan, phase-shifted PWM, constant inputs, menu selection, retained snapshots, and renderer bounds.

include/scope_decoders.h contains the portable DSView catalogue/configuration/annotation model; the isolated ARM adapter is in tools/scope-decoders. The framebuffer UI and UIO acquisition live in the Zynq board project.