2.0 KiB
STM32G474RB emulator peripheral port
Board adapters for the common UMP/TMS/IGBT server and waveform generator.
All peripheral source files have detailed Russian comments matching the F407 port.
The shared algorithms, codecs and register map stay in ../../src.
board.c: application VTOR 0x08010000; HSI16/PLL 160 MHz, APB1 80 MHz; HSI48/CRS USB; board GPIO and 1 ms model ticks.transport.c: USART2 PA2/PA3 RTU, optional RS485 DE PB15; FDCAN1 PB8/PB9, Classic CAN, extended IDs, bounded polling and TX timeout.wave_hal.c: PA4 DAC1_CH1, TIM6, DMA1_Channel1 with DMAMUX DAC1 request; 2..4096 samples in SRAM1/2, exact timer division, maximum 1 MS/s.main.c: service ordering and deferred reboot into the G474 USB bootloader.
IGBT input bits 0..7 use PB0/PB1/PB2/PB10/PB11/PB12/PB13/PB14;
output bits use PC0..PC7. SWD, SWO and USB pins are preserved.
Clock, addresses and RS485 mode come from the board-supplied board_config.h.
The default internal clock does not guarantee CAN or waveform accuracy over
all temperature conditions; use a verified 24 MHz HSE source when required.
The consumer supplies board.h, transport.h, wave_hal.h, emulator.h,
G4 HAL configuration and the common model composition. The reference project
is Nucleo_G474RB in the emulator repository. Compile EMU_CAPACITY=400:
each 32000-byte archive bank fits the MCU's 32 KiB CCM/96 KiB SRAM layout.
DMA samples stay in SRAM1/2. No F407 peripheral implementation is compiled.
Link at 0x08010000 with a 64 KiB Flash limit; install the separate G474RB
USB bootloader first. Require 128 KiB silicon, DBANK=0, BFB2=0 and no bank swap.
The firmware rejects mismatched geometry before peripheral initialization.
Reuse ../stm32g474-usb-boot/boot_usb_port.c and boot_request.c with the
shared USB CDC transport. Device model: STM32G474RB-EMU-EXPERIMENT.
Host tests validate the shared software; peripheral timing and electrical behavior have not yet been validated on a physical board.