60 lines
2.6 KiB
C
60 lines
2.6 KiB
C
/*
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* Воспроизведение таблицы ЦАП STM32F407 через TIM6 и DMA1 Stream5. Частота должна точно делить
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* частоту таймера, а массив находиться в доступной DMA-памяти; старт предварительно загружает
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* последний отсчёт циклической таблицы.
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*/
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#include "set_wave_f407.h"
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#include "stm32f4xx.h"
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static void stop(void *context) {
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unsigned limit=100000; (void)context;
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RCC->AHB1ENR|=RCC_AHB1ENR_GPIOAEN|RCC_AHB1ENR_DMA1EN;
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RCC->APB1ENR|=RCC_APB1ENR_DACEN|RCC_APB1ENR_TIM6EN;
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(void)RCC->APB1ENR;
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TIM6->CR1=0;
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DAC->CR&=~(DAC_CR_DMAEN1|DAC_CR_TEN1);
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DMA1_Stream5->CR&=~DMA_SxCR_EN;
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while((DMA1_Stream5->CR&DMA_SxCR_EN)&&--limit) {}
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/* Leave other DAC channel untouched. Channel 1 outputs zero on stop. */
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DAC->DHR12R1=0;
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DMA1->HIFCR=0xF40u;
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DAC->SR=DAC_SR_DMAUDR1;
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}
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static int start(void *context,const uint16_t *samples,size_t count,uint32_t rate) {
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set_wave_f407 *c=(set_wave_f407 *)context;
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uint32_t ticks,psc,arr; uintptr_t address=(uintptr_t)samples;
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if(!c||!rate||rate>SET_WAVE_MAX_RATE||count<2||count>SET_WAVE_MAX||c->timer_hz%rate
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||address<0x20000000u||address+count*2>0x20020000u) return 1;
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ticks=c->timer_hz/rate;
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for(psc=1;psc<=65536;++psc) if(ticks%psc==0&&ticks/psc<=65536) break;
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if(psc>65536||ticks<psc) return 1;
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arr=ticks/psc;
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stop(context);
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if(DMA1_Stream5->CR&DMA_SxCR_EN) return 1;
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GPIOA->MODER|=3u<<8;
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GPIOA->PUPDR&=~(3u<<8);
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TIM6->PSC=psc-1;TIM6->ARR=arr-1;TIM6->CNT=0;
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TIM6->CR2=0;TIM6->EGR=TIM_EGR_UG;TIM6->SR=0;
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TIM6->CR2=TIM_CR2_MMS_1; /* update -> TRGO */
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DMA1_Stream5->PAR=(uint32_t)&DAC->DHR12R1;
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DMA1_Stream5->M0AR=(uint32_t)samples;DMA1_Stream5->NDTR=(uint32_t)count;
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DMA1_Stream5->FCR=0;
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DMA1_Stream5->CR=(7u<<25)|DMA_SxCR_DIR_0|DMA_SxCR_MINC|DMA_SxCR_CIRC
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|DMA_SxCR_PSIZE_0|DMA_SxCR_MSIZE_0|DMA_SxCR_PL_1;
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/* Prime the previous period's last sample; DMA supplies the next value
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* after each trigger. Cyclic order is last,0,1,... with one priming tick. */
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DAC->CR&=~0xFFFFu;
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DAC->DHR12R1=samples[count-1];
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DAC->CR|=DAC_CR_EN1|DAC_CR_TEN1|DAC_CR_DMAEN1; /* TSEL1=0: TIM6 */
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DMA1_Stream5->CR|=DMA_SxCR_EN;
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TIM6->CR1=TIM_CR1_CEN;
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return 0;
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}
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set_wave_port set_wave_f407_port(set_wave_f407 *context) {
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set_wave_port port={context,start,stop};return port;
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}
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int set_wave_f407_fault(void) {
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return (DMA1->HISR&(DMA_HISR_TEIF5|DMA_HISR_DMEIF5|DMA_HISR_FEIF5))
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||(DAC->SR&DAC_SR_DMAUDR1);
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}
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