#include "parallel_nand_port_tms320f2812.h"
#include "DSP281x_Device.h"

/* C28x addresses are 16-bit word addresses. XA0/XA1 drive CLE/ALE. */
#define PNAND_TMS_DATA_REG (*(volatile unsigned int *)0x100000UL)
#define PNAND_TMS_CMD_REG  (*(volatile unsigned int *)0x100001UL)
#define PNAND_TMS_ADDR_REG (*(volatile unsigned int *)0x100002UL)

#ifndef PNAND_TMS_CPU_MHZ
#define PNAND_TMS_CPU_MHZ 150UL
#endif

static void tms_delay_us(unsigned long us)
{
    volatile unsigned long loops = us * (PNAND_TMS_CPU_MHZ / 5UL);
    while (loops-- != 0UL) asm(" NOP");
}

static int tms_init(void)
{
    EALLOW;
    GpioMuxRegs.GPEMUX.bit.XINT1_XBIO_GPIOE0 = 0;
    GpioMuxRegs.GPEDIR.bit.GPIOE0 = 0;

    XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
    XintfRegs.XINTCNF2.bit.WRBUFF = 0;
    XintfRegs.XINTCNF2.bit.CLKOFF = 0;
    XintfRegs.XINTCNF2.bit.CLKMODE = 1;
    XintfRegs.XTIMING6.bit.XWRLEAD = 3;
    XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
    XintfRegs.XTIMING6.bit.XRDLEAD = 3;
    XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
    XintfRegs.XTIMING6.bit.USEREADY = 0;
    XintfRegs.XTIMING6.bit.READYMODE = 0;
    XintfRegs.XTIMING6.bit.XSIZE = 3;
    EDIS;
    asm(" RPT #7 || NOP");
    return 0;
}

static void tms_select(void) { /* XZCS6AND7 формируется каждым доступом. */ }
static void tms_deselect(void) { }
static void tms_write_command(pnand_octet_t v) { PNAND_TMS_CMD_REG = v & 0xFFU; }
static void tms_write_address(pnand_octet_t v) { PNAND_TMS_ADDR_REG = v & 0xFFU; }
static void tms_write_data(pnand_octet_t v) { PNAND_TMS_DATA_REG = v & 0xFFU; }
static pnand_octet_t tms_read_data(void) { return PNAND_TMS_DATA_REG & 0xFFU; }
static int tms_is_ready(void) { return GpioDataRegs.GPEDAT.bit.GPIOE0 != 0; }
static void tms_set_wp(int enabled)
{
    /* Шаблон платы фиксирует WP# аппаратно. См. README порта. */
    (void)enabled;
}

static const parallel_nand_port_t tms_port = {
    tms_init, tms_select, tms_deselect,
    tms_write_command, tms_write_address, tms_write_data,
    tms_read_data, tms_is_ready, tms_set_wp, tms_delay_us,
    0
};

const parallel_nand_port_t *parallel_nand_port_tms320f2812(void)
{
    return &tms_port;
}