Checkpoint EEPROM, firmware analysis and instrument protocol updates

c/set-protocol/tests/test_periph28335_eeprom.c

@@ -1,5 +1,6 @@
 #include "periph28335.h"
 #include <assert.h>
+#include "balsam167_eeprom_block.h"
 #include <string.h>
 
 static void response(uint8_t *out, unsigned high, unsigned low)
@@ -12,9 +13,100 @@ static void response(uint8_t *out, unsigned high, unsigned low)
     out[8]=out[9]=0;
 }
 
+static void blocks(void)
+{
+    periph28335_eeprom_reader r;
+    uint8_t req[8], reply[245], out[240];
+    unsigned start, transactions, n, a, i, old;
+    int got;
+    assert(!balsam167_eeprom_block_valid(6,0x8000,1));
+    assert(!balsam167_eeprom_block_valid(3,0xbfff,2));
+    assert(!balsam167_eeprom_block_valid(3,0xffff,120));
+    assert(!balsam167_eeprom_block_valid(3,0x8000,121));
+    assert(!balsam167_eeprom_block_valid(3,0x8000,0));
+    assert(balsam167_eeprom_block_valid(3,0xbfff,1));
+    for(start=0;start<2;start++) {
+        assert(!periph28335_eeprom_begin(&r,16,start,32768-start));
+        transactions=0;
+        while(r.received<r.length) {
+            assert(periph28335_eeprom_block_request(&r,req,8)==8);
+            assert(!periph28335_crc16_modbus(req,8));
+            a=((unsigned)req[2]*256+req[3]-0x8000)*2;
+            n=req[5]; assert(n && n<=120 && a+2*n<=32768);
+            reply[0]=5; reply[1]=3; reply[2]=(uint8_t)(2*n);
+            for(i=0;i<2*n;i++) reply[3+i]=(uint8_t)(a+i);
+            assert(periph28335_append_crc(reply,3+2*n,reply,sizeof reply)==5+2*n);
+            old=r.received;
+            reply[4]^=1;
+            assert(periph28335_eeprom_block_accept(&r,reply,5+2*n,out,240)==PERIPH28335_ERROR_CRC);
+            assert(r.received==old); reply[4]^=1;
+            assert(periph28335_eeprom_block_accept(&r,reply,5+2*n,out,0)==PERIPH28335_ERROR_CAPACITY);
+            assert(r.received==old);
+            got=periph28335_eeprom_block_accept(&r,reply,5+2*n,out,240);
+            assert(got>0);
+            for(i=0;i<(unsigned)got;i++) assert(out[i]==(uint8_t)(start+old+i));
+            transactions++;
+        }
+        assert(transactions==137);
+        assert(!periph28335_eeprom_block_request(&r,req,8));
+    }
+}
+
+static void profiles(void)
+{
+    periph28335_eeprom_reader r;
+    uint8_t req[18], reply[245], out[240];
+    unsigned n, i, q, a, bankmask=0;
+    uint32_t pos, before;
+    assert(periph28335_eeprom_capacity_profile(0)==32768);
+    assert(periph28335_eeprom_capacity_profile(1)==262144);
+    assert(periph28335_eeprom_capacity_profile(2)==0);
+    assert(periph28335_eeprom_begin_profile(&r,16,262143,2,1)<0);
+    assert(periph28335_eeprom_begin_profile(&r,16,0,2,2)<0);
+    assert(!balsam167_eeprom_block_valid_profile(3,0xffff,0x8078,1));
+    assert(!balsam167_eeprom_block_valid_profile(3,0x8000,0x8401,1));
+    assert(!balsam167_eeprom_block_valid_profile(3,0x8000,0x8001,0));
+    assert(!balsam167_eeprom_block_valid_profile(3,0x8000,1,1));
+    assert(balsam167_eeprom_block_valid_profile(3,0xffff,0x8301,1));
+    /* Full 256-KiB dump from an odd start exercises every bank transition,
+     * first/last byte trimming, CRC failure and exact physical byte order. */
+    assert(!periph28335_eeprom_begin_profile(&r,16,1,262143,1));
+    while(r.received<r.length) {
+        assert(periph28335_eeprom_block_request_profile(&r,req,8,1)==8);
+        assert(!periph28335_crc16_modbus(req,8));
+        a=req[2]*256U+req[3]; q=req[4]*256U+req[5]; n=q&255U;
+        assert(balsam167_eeprom_block_valid_profile(3,a,q,1));
+        pos=balsam167_eeprom_block_word(a,q)*2UL;
+        assert(pos == (r.start+r.received)/2*2);
+        bankmask |= 1U << ((q>>8)&3U);
+        assert(periph28335_eeprom_block_expected_profile(&r,1)==5+2*n);
+        reply[0]=5; reply[1]=3; reply[2]=(uint8_t)(n*2);
+        for(i=0;i<n*2;i++) reply[3+i]=(uint8_t)((pos+i)^((pos+i)>>16));
+        periph28335_append_crc(reply,3+n*2,reply,sizeof(reply));
+        before=r.received; reply[4]^=1;
+        assert(periph28335_eeprom_block_accept_profile(&r,reply,5+2*n,out,240,1)==PERIPH28335_ERROR_CRC);
+        assert(r.received==before); reply[4]^=1;
+        assert(periph28335_eeprom_block_accept_profile(&r,reply,5+2*n,out,240,1)>0);
+        for(i=0;i<r.received-before;i++) {
+            pos=1+before+i;
+            assert(out[i]==(uint8_t)(pos^(pos>>16)));
+        }
+    }
+    assert(bankmask==15);
+    assert(!periph28335_eeprom_block_request_profile(&r,req,8,1));
+    assert(periph28335_eeprom_write_profile(5,0,0x200000,33514,0,req,18)==0);
+    assert(periph28335_eeprom_write_profile(5,0,0x200000,33514,1,req,18)==18);
+    assert(req[14]==0x44 && req[15]==0 && !periph28335_crc16_modbus(req,18));
+    assert(!periph28335_eeprom_write_profile(5,0x1ff7e,0,2,1,req,18));
+    assert(!periph28335_eeprom_write_profile(5,0xffffffff,0,2,1,req,18));
+    assert(periph28335_eeprom_write_profile(5,0,0,32438,0,req,18)==18 && req[14]==4);
+}
+
 int main(void)
 {
     periph28335_eeprom_reader reader;
+    blocks();
+    profiles();
     uint8_t request[8], reply[10], data[2];
     unsigned i;
     assert(sizeof(reader)==16);