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Extract reusable device protocols, ports and logic analyzers from SETGUI

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andrey
2026-09-23 20:11:37 +03:00
parent 80ba17d77d
commit 795a1279b1
63 changed files with 10181 additions and 6 deletions
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4
python/altera_logic/stream_port.py
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@@ -5,8 +5,8 @@ UART uses the same SETCAN frames inside the shared AA55/CRC16 transport.
Reception and rendering clocks are separate; no packet-rate repainting.
"""
from __future__ import annotations
from PySide6.QtCore import QObject, QTimer, QElapsedTimer, Signal
from PySide6.QtSerialPort import QSerialPort, QSerialPortInfo
from set_devices.qt_ports.qt_compat import QObject, QTimer, QElapsedTimer, Signal
from set_devices.qt_ports.qt_compat import QSerialPort, QSerialPortInfo
from .stream import NativeStream