Add DSLogic capture, signal conversion and DSView decoders

tools/dsview/decoders/transistor_pair/README.md

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+# Transistor pair
+
+Independent two-channel analyzer. Assign Vin1 and Vin2; Vstat is not used.
+Available in DSView's **Пользовательские** section as **Transistor pair**.
+
+- Minimum active ON pulse duration (mintime), independently per input.
+- Minimum inactive OFF duration, independently per input.
+- Deadtime from Vin1 OFF to Vin2 ON and vice versa, with independent minimums.
+- Active overlap is a fault, regardless of the deadtime settings.
+- Period, frequency and active duty cycle for complete cycles on each input.
+- Independent active-high/active-low polarity for both inputs.
+
+All limits are nanoseconds. Zero disables the corresponding lower limit;
+equality passes. Simultaneous handovers measure zero deadtime. These settings
+check measured pulses and do not debounce or filter the source waveform.
+
+Measurements occupy separate waveform rows. Timing violations appear in the
+FAULT row. Unknown edges outside the capture are not fabricated; partial
+pulses do not produce full pulse widths or full-cycle frequency/duty values.
+
+Python: `PairTimingChecker` in `logic_analyzer.decoders.transistor_pair`.
+Offline API: `analyze_capture(..., dict(mode='Transistor pair', channel=0,
+vin2_channel=1, vin1_mintime_ns=100, deadtime_12_ns=50))`.
+
+For Vin/Vstat ACK checks and full driver-cycle OK/WARNING/FAULT results use
+the separate **IGBT 1SP/1SD** decoder.