Add DSLogic capture, signal conversion and DSView decoders

tools/dsview/decoders/gate_driver_timing/README.md

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+# 1SP0635 / 1SD536F2 timing decoder for DSView
+
+This decoder checks driver control and status responses:
+
+- `Vin1`: optional control sent to the first gate driver (legacy channel ID `vin`);
+- `Vstat`: edge acknowledgement and fault feedback returned by the driver.
+
+Built-in data-sheet profiles:
+
+| Profile | ACK delay (typ.) | ACK width (specified) | Long pulse |
+|---|---:|---:|---:|
+| 1SP0635 | 250 ns | 400...1050 ns | fault above 1.5 us |
+| 1SD536F2 | 380 ns | 600...1800 ns | fault above 1.8 us* |
+
+`*` The 1.8 us fault threshold is a project classification choice based on the
+data-sheet ACK maximum, not a verified universal manufacturer fault threshold.
+The previously stated 1.5 us manual threshold could not be verified.
+Correlated pulses within the ACK width limits pass. Uncorrelated pulses up to
+the fault threshold are warnings; pulses above it are faults. Width and fault
+annotations are emitted only when the pulse ends.
+
+The data sheets specify only a *typical* ACK delay, not minimum and maximum
+limits.  DSView therefore emits a warning outside the configurable tolerance
+(default +/-100 ns).  The ACK-width check uses the published min/max values.
+
+## Use in SETGUI
+
+The DSView build recipe packages this adapter together with the canonical
+`python/logic_analyzer/decoders/gate_timing.py` core. In the DSView tab,
+choose **Анализаторы SET → IGBT · 1SP0635 / 1SD536F2** (or search Decode for
+`IGBT 1SP/1SD`). Assign Vstat and, if available, Vin1, choose the driver profile, and set `Vstat acknowledge/fault level`
+to match the receiver circuit. The diagrams in the application manual show
+the logical event; some optical receiver circuits invert it.
+
+Use at least 50 MS/s; 100 MS/s or more is recommended. Never connect a DSLogic
+digital input directly to the IGBT gate (+15/-10 V) or to a power-stage node.
+Use the isolated optical receiver logic signals and a common logic ground.
+
+## Separate transistor pair analyzer
+
+This decoder analyzes only Vin1/Vstat driver responses. Vin1 is optional;
+Vstat alone retains pulse/fault classification, while Vin1 enables ACK timing
+and full-cycle results. Vstat is required. The channel ID `vin` remains stable.
+
+Pair analysis was moved to **Transistor pair** in the **Пользовательские**
+section. Add that decoder separately and assign Vin1/Vin2. Old pair settings
+on IGBT instances must be recreated in the new decoder. The pair checkbox,
+Vin2 assignment and pulse limits are no longer part of the driver decoder.
+
+## Full pulse cycle result
+
+The **Vin1 / ACK full cycle** waveform row displays OK, WARNING or FAULT
+across each complete sequence **Vin1 ON -> ACK -> Vin1 OFF -> ACK**.
+The annotation starts at Vin1 ON and ends at the end of the OFF acknowledgment.
+It is emitted only after both ACKs have been classified. A delay warning makes
+that cycle WARNING; missing ACK, invalid width or fault feedback makes it FAULT.
+A later normal cycle can be OK independently of previous cycles.
+Unfinished cycles are never marked OK. Active-low Vin1 is supported.
+The results panel retains its original layout without a large summary banner.
+Deadtime and mintime are provided by the separate Transistor pair analyzer.