Add DSLogic capture, signal conversion and DSView decoders
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tools/dsview/decoders/gate_driver_timing/README.md
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tools/dsview/decoders/gate_driver_timing/README.md
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# 1SP0635 / 1SD536F2 timing decoder for DSView
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This decoder checks driver control and status responses:
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- `Vin1`: optional control sent to the first gate driver (legacy channel ID `vin`);
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- `Vstat`: edge acknowledgement and fault feedback returned by the driver.
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Built-in data-sheet profiles:
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| Profile | ACK delay (typ.) | ACK width (specified) | Long pulse |
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|---|---:|---:|---:|
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| 1SP0635 | 250 ns | 400...1050 ns | fault above 1.5 us |
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| 1SD536F2 | 380 ns | 600...1800 ns | fault above 1.8 us* |
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`*` The 1.8 us fault threshold is a project classification choice based on the
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data-sheet ACK maximum, not a verified universal manufacturer fault threshold.
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The previously stated 1.5 us manual threshold could not be verified.
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Correlated pulses within the ACK width limits pass. Uncorrelated pulses up to
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the fault threshold are warnings; pulses above it are faults. Width and fault
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annotations are emitted only when the pulse ends.
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The data sheets specify only a *typical* ACK delay, not minimum and maximum
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limits. DSView therefore emits a warning outside the configurable tolerance
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(default +/-100 ns). The ACK-width check uses the published min/max values.
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## Use in SETGUI
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The DSView build recipe packages this adapter together with the canonical
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`python/logic_analyzer/decoders/gate_timing.py` core. In the DSView tab,
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choose **Анализаторы SET → IGBT · 1SP0635 / 1SD536F2** (or search Decode for
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`IGBT 1SP/1SD`). Assign Vstat and, if available, Vin1, choose the driver profile, and set `Vstat acknowledge/fault level`
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to match the receiver circuit. The diagrams in the application manual show
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the logical event; some optical receiver circuits invert it.
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Use at least 50 MS/s; 100 MS/s or more is recommended. Never connect a DSLogic
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digital input directly to the IGBT gate (+15/-10 V) or to a power-stage node.
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Use the isolated optical receiver logic signals and a common logic ground.
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## Separate transistor pair analyzer
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This decoder analyzes only Vin1/Vstat driver responses. Vin1 is optional;
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Vstat alone retains pulse/fault classification, while Vin1 enables ACK timing
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and full-cycle results. Vstat is required. The channel ID `vin` remains stable.
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Pair analysis was moved to **Transistor pair** in the **Пользовательские**
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section. Add that decoder separately and assign Vin1/Vin2. Old pair settings
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on IGBT instances must be recreated in the new decoder. The pair checkbox,
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Vin2 assignment and pulse limits are no longer part of the driver decoder.
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## Full pulse cycle result
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The **Vin1 / ACK full cycle** waveform row displays OK, WARNING or FAULT
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across each complete sequence **Vin1 ON -> ACK -> Vin1 OFF -> ACK**.
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The annotation starts at Vin1 ON and ends at the end of the OFF acknowledgment.
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It is emitted only after both ACKs have been classified. A delay warning makes
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that cycle WARNING; missing ACK, invalid width or fault feedback makes it FAULT.
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A later normal cycle can be OK independently of previous cycles.
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Unfinished cycles are never marked OK. Active-low Vin1 is supported.
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The results panel retains its original layout without a large summary banner.
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Deadtime and mintime are provided by the separate Transistor pair analyzer.
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3
tools/dsview/decoders/gate_driver_timing/__init__.py
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tools/dsview/decoders/gate_driver_timing/__init__.py
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"""DSView protocol decoder for SCALE gate-driver timing checks."""
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from .pd import Decoder
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168
tools/dsview/decoders/gate_driver_timing/pd.py
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tools/dsview/decoders/gate_driver_timing/pd.py
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"""DSView/libsigrokdecode front end for SCALE gate-driver timing checks."""
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import sigrokdecode as srd
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from common.setgui_decoders.gate_timing import TimingChecker
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class SamplerateError(Exception):
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pass
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class Ann(object):
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CONTROL = 0
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DELAY_OK = 1
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WIDTH_OK = 2
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WARNING = 3
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ERROR = 4
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FAULT = 5
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CYCLE_OK = 6
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CYCLE_WARNING = 7
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CYCLE_FAULT = 8
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ANN_FOR_KIND = {
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'control': Ann.CONTROL,
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'delay_ok': Ann.DELAY_OK,
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'width_ok': Ann.WIDTH_OK,
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'delay_warn': Ann.WARNING,
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'width_fail': Ann.ERROR,
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'missing': Ann.ERROR,
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'orphan': Ann.WARNING,
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'fault': Ann.FAULT,
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'cycle_ok': Ann.CYCLE_OK,
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'cycle_warning': Ann.CYCLE_WARNING,
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'cycle_fault': Ann.CYCLE_FAULT,
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}
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'gate_driver_timing'
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name = 'IGBT 1SP/1SD'
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longname = 'Power Integrations 1SP0635 / 1SD536F2 timing checker'
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desc = 'Checks driver Vin1/Vstat ACK timing, faults and full pulse cycles.'
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license = 'gplv2+'
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inputs = ['logic']
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outputs = []
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tags = ['Clock/timing', 'Util']
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channels = ()
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optional_channels = (
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{'id': 'vin', 'name': 'Vin1', 'desc': 'First driver control input'},
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{'id': 'vstat', 'name': 'Vstat', 'desc': 'Driver status/acknowledge output'},
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)
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options = (
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{'id': 'profile', 'desc': 'Driver profile', 'default': '1SP0635',
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'values': ('1SP0635', '1SD536F2', 'custom')},
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{'id': 'vin_active', 'desc': 'Vin1 active level', 'default': 'high',
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'values': ('high', 'low')},
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{'id': 'vstat_active', 'desc': 'Vstat acknowledge/fault level', 'default': 'high',
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'values': ('high', 'low')},
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{'id': 'delay_tolerance_ns',
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'desc': 'Warning tolerance around typical ACK delay (ns)', 'default': 100},
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{'id': 'orphan_min_width_ns',
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'desc': 'ORPHAN minimum pulse width (ns, 0 = off)', 'default': 0},
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{'id': 'custom_delay_ns', 'desc': 'Custom typical ACK delay (ns)', 'default': 250},
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{'id': 'custom_width_min_ns', 'desc': 'Custom ACK width minimum (ns)', 'default': 400},
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{'id': 'custom_width_typ_ns', 'desc': 'Custom ACK width typical (ns)', 'default': 700},
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{'id': 'custom_width_max_ns', 'desc': 'Custom ACK width maximum (ns)', 'default': 1050},
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{'id': 'custom_fault_ns', 'desc': 'Custom fault pulse threshold (ns)', 'default': 1500},
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)
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annotations = (
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('control', 'Vin1 edge'),
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('delay-ok', 'ACK delay pass'),
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('width-ok', 'ACK width pass'),
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('warning', 'Warning'),
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('error', 'Timing failure'),
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('fault', 'Driver fault'),
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('cycle-ok', 'Cycle OK'),
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('cycle-warning', 'Cycle WARNING'),
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('cycle-fault', 'Cycle FAULT'),
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)
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annotation_rows = (
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('cycle', 'Vin1 / ACK full cycle', (Ann.CYCLE_OK, Ann.CYCLE_WARNING, Ann.CYCLE_FAULT)),
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('vin', 'Vin1', (Ann.CONTROL,)),
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('measurements', 'Measurements', (Ann.DELAY_OK, Ann.WIDTH_OK)),
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('checks', 'Warnings / failures', (Ann.WARNING, Ann.ERROR, Ann.FAULT)),
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)
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def __init__(self):
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self.reset()
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# Состояние принадлежит одному запуску декодера. Сброс не должен
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# переносить незавершённый кадр или частоту из предыдущей записи.
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def reset(self):
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self.samplerate = None
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self.checker = None
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# DSView передаёт время в номерах отсчётов. Частота нужна общему ядру
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# для перевода тайм-аутов и измерений в физические единицы.
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def metadata(self, key, value):
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if key == srd.SRD_CONF_SAMPLERATE:
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self.samplerate = value
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# Выходы регистрируются в жизненном цикле sigrok, а не в конструкторе.
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# Здесь регистрируются аннотации для дорожек измерений и предупреждений.
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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# Адаптер переводит настройки DSView в параметры общего TimingChecker.
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# Пороговые алгоритмы остаются в templates/python/logic_analyzer/decoders.
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def _make_checker(self):
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custom = {
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'ack_delay_typ_ns': float(self.options['custom_delay_ns']),
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'ack_width_min_ns': float(self.options['custom_width_min_ns']),
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'ack_width_typ_ns': float(self.options['custom_width_typ_ns']),
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'ack_width_max_ns': float(self.options['custom_width_max_ns']),
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'fault_threshold_ns': float(self.options['custom_fault_ns']),
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}
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return TimingChecker(
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self.samplerate,
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profile=self.options['profile'],
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delay_tolerance_ns=float(self.options['delay_tolerance_ns']),
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vin_active_high=self.options['vin_active'] == 'high',
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vstat_active_high=self.options['vstat_active'] == 'high',
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orphan_min_width_ns=self.options.get('orphan_min_width_ns', 0),
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custom=custom, cycle_results=True)
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def _put_events(self, events):
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for event in events:
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ann = ANN_FOR_KIND[event['kind']]
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self.put(event['start'], max(event['start'], event['end']),
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self.out_ann, [ann, [event['text'], event['short']]])
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def decode(self):
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if not self.samplerate:
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raise SamplerateError('Cannot decode without samplerate.')
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self.checker = self._make_checker()
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has_vin1 = self.has_channel(0)
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if not self.has_channel(1):
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raise ValueError('Connect Vstat for driver response analysis.')
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while True:
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conditions = [{0: 'e'}, {1: 'e'}] if has_vin1 else [{1: 'e'}]
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timer_bit = 1 << len(conditions)
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deadline = self.checker.next_deadline()
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if deadline is not None:
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conditions.append({'skip': max(1, deadline - self.samplenum)})
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# DSView mutates and returns the same native tuple on every wait.
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# Release that tuple before waiting again (PyTuple_SetItem requires
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# exclusive ownership); tuple(...) would not make a copy.
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pins = list(self.wait(conditions))
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vin, vstat = pins[:2]
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now = self.samplenum
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# Both channels may transition at the same sample; preserve both.
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if has_vin1 and self.matched & 0b001:
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self._put_events(self.checker.on_control_edge(now, vin))
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if self.matched & (0b010 if has_vin1 else 0b001):
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self._put_events(self.checker.on_status_edge(now, vstat))
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if deadline is not None and self.matched & timer_bit:
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self._put_events(self.checker.expire(now))
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def end(self):
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if self.checker is not None:
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self._put_events(self.checker.finish_cycles(self.samplenum))
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