запущен проект motor identification c терминалкой
This commit is contained in:
BIN
Inu_im_1wnd_3lvl/.vs/Inu_im_1wnd_3lvl/v16/.suo
Normal file
BIN
Inu_im_1wnd_3lvl/.vs/Inu_im_1wnd_3lvl/v16/.suo
Normal file
Binary file not shown.
BIN
Inu_im_1wnd_3lvl/.vs/Inu_im_1wnd_3lvl/v16/Browse.VC.db
Normal file
BIN
Inu_im_1wnd_3lvl/.vs/Inu_im_1wnd_3lvl/v16/Browse.VC.db
Normal file
Binary file not shown.
BIN
Inu_im_1wnd_3lvl/.vs/Inu_im_1wnd_3lvl/v16/Browse.VC.db-shm
Normal file
BIN
Inu_im_1wnd_3lvl/.vs/Inu_im_1wnd_3lvl/v16/Browse.VC.db-shm
Normal file
Binary file not shown.
BIN
Inu_im_1wnd_3lvl/.vs/Inu_im_1wnd_3lvl/v16/Browse.VC.opendb
Normal file
BIN
Inu_im_1wnd_3lvl/.vs/Inu_im_1wnd_3lvl/v16/Browse.VC.opendb
Normal file
Binary file not shown.
3
Inu_im_1wnd_3lvl/.vs/ProjectSettings.json
Normal file
3
Inu_im_1wnd_3lvl/.vs/ProjectSettings.json
Normal file
@@ -0,0 +1,3 @@
|
||||
{
|
||||
"CurrentProjectSetting": "No Configurations"
|
||||
}
|
||||
BIN
Inu_im_1wnd_3lvl/.vs/slnx.sqlite
Normal file
BIN
Inu_im_1wnd_3lvl/.vs/slnx.sqlite
Normal file
Binary file not shown.
665
Inu_im_1wnd_3lvl/Inu/controller.c
Normal file
665
Inu_im_1wnd_3lvl/Inu/controller.c
Normal file
@@ -0,0 +1,665 @@
|
||||
/**************************************************************************
|
||||
Description: Ïðîãðàììà ìîäåëèðóåò ðàáîòó ïðîöåññîðà - îñóùåñòâëÿåò
|
||||
âûçîâ ôóíêöèé init28335, detcoeff, isr.
|
||||
Òàêæå ìîäåëèðóåò ðàçëè÷íûå ïåðèôåðèéíûå óñòðîéñòâà ïðîöåññîðà
|
||||
TMS320F28335/TMS320F28379D (ADC, PWM, QEP è ò.ä.).
|
||||
|
||||
Àâòîð: Óëèòîâñêèé Ä.È.
|
||||
Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.11.08
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
#include "simstruc.h"
|
||||
#include "wrapper_inu.h"
|
||||
#include "def.h"
|
||||
#include "controller.h"
|
||||
|
||||
|
||||
extern void init28335(void);
|
||||
extern void detcoeff(void);
|
||||
extern void isr(void);
|
||||
extern void input_param(unsigned short num, unsigned short val);
|
||||
|
||||
|
||||
void controller(SimStruct *S, const real_T *u, real_T *xD, real_T *rW, int_T *iW) {
|
||||
// ÂÕÎÄÛ (begin)
|
||||
nn = 0;
|
||||
// àíàëîãîâûå âåëè÷èíû
|
||||
udc1_ml = u[nn++];//Â
|
||||
ia1_ml = u[nn++];//À
|
||||
ib1_ml = u[nn++];//À
|
||||
ic1_ml = u[nn++];//À
|
||||
wm_ml = u[nn++];//ðàä/ñ
|
||||
// óïðàâëåíèå (íàïðèìåð, ñ ÂÓ)
|
||||
mst.faultReset = (unsigned short)u[nn++];
|
||||
mst.start = (unsigned short)u[nn++];
|
||||
mst.pzMode = (unsigned short)u[nn++];
|
||||
mst.wmZz = u[nn++];//o.e. (îò N_BAZ)
|
||||
mst.pmZz = u[nn++]*(P_NOM/S_BAZ);//o.e. (îò S_BAZ)
|
||||
mst.wmLim = u[nn++];//o.e. (îò N_BAZ)
|
||||
mst.pmLim = u[nn++]*(P_NOM/S_BAZ);//o.e. (îò S_BAZ)
|
||||
mst.pIncrMaxTy = u[nn++]*TY*DECIM_PSI_WM_PM*(P_NOM/S_BAZ);//o.e. (îò S_BAZ)
|
||||
mst.pDecrMaxTy = u[nn++]*TY*DECIM_PSI_WM_PM*(P_NOM/S_BAZ);//o.e. (îò S_BAZ)
|
||||
iref = u[nn++];//î.å.
|
||||
// ïàðàìåòðû (íàïðèìåð, ñ ÏÓ)
|
||||
paramNo = FIRST_WRITE_PAR_NUM;
|
||||
paramNew[paramNo++] = (unsigned short)u[nn++];
|
||||
paramNew[paramNo++] = (unsigned short)u[nn++];
|
||||
// ÂÕÎÄÛ (end)
|
||||
|
||||
//wm_ml = wm_ml_0*wm_err;//óãëîâàÿ ñêîðîñòü ñ ó÷åòîì ïîãðåøíîñòè
|
||||
|
||||
|
||||
// îáðàáàòûâàåì ïàðàìåòðû S-Function êàæäûé ðàç, êîãäà îíè èçìåíèëèñü
|
||||
if ( iW[0] == 1 ) {
|
||||
iW[0] = 0;
|
||||
kkk = 0;
|
||||
for ( lll = 0; lll < NPARAMS; lll++ ) {
|
||||
// îïðåäåëÿåì êîë-âî ýëåìåíòîâ â ïàðàìåòðå
|
||||
dimen = mxGetNumberOfElements(ssGetSFcnParam(S,lll));
|
||||
// îáðàáàòûâàåì ïàðàìåòð â çàâèñèìîñòè îò åãî ðàçìåðà
|
||||
if ( dimen > LEN_PARAM_MATR*2 ) {
|
||||
ssSetErrorStatus(S,"Â ïàðàìåòðå-ìàññèâå ñëèøêîì ìíîãî ýëåìåíòîâ");
|
||||
return;
|
||||
}
|
||||
else if ( dimen > 1 ) {
|
||||
// çàïîìèíàåì êîë-âî ýëåìåíòîâ ïàðàìåòðà-ìàòðèöû
|
||||
paramMatrDimen = dimen;
|
||||
// çàïîìèíàåì çíà÷åíèÿ ýëåìåíòîâ ïàðàìåòðà-ìàòðèöû
|
||||
for ( mmm = 0; mmm < dimen; mmm++ )
|
||||
paramMatr[mmm] = mxGetPr(ssGetSFcnParam(S,lll))[mmm];
|
||||
}
|
||||
else {
|
||||
// çàïîìèíàåì çíà÷åíèÿ ïàðàìåòðîâ-ñêàëÿðîâ
|
||||
paramScal[kkk++] = mxGetPr(ssGetSFcnParam(S,lll))[0];
|
||||
}
|
||||
}
|
||||
// ÏÀÐÀÌÅÒÐÛ (begin)
|
||||
nn = 0;
|
||||
dt = paramScal[nn++];//øàã äèñêðåòèçàöèè (âñåãäà äîëæåí ïåðåäàâàòüñÿ â S-function ïîñëåäíèì!)
|
||||
// ÏÀÐÀÌÅÒÐÛ (end)
|
||||
} //if ( iW[0] == 1 )
|
||||
|
||||
|
||||
|
||||
|
||||
// êîå-÷òî âûïîëíÿåì îäèí ðàç ïðè çàïóñêå ìîäåëè
|
||||
if ( iW[1] == 1 ) {
|
||||
iW[1] = 0;
|
||||
|
||||
// èíèöèàëèçàöèÿ ïðîöåññîðà
|
||||
init28335();
|
||||
|
||||
// èìèòàöèÿ ñ÷èòûâàíèÿ ïàðàìåòðîâ èç EEPROM
|
||||
// ... ïàðàìåòðû èç ìîäåëè (ñì. áëîê "Parameters")
|
||||
for ( j = FIRST_WRITE_PAR_NUM; j < paramNo; j++ ) {
|
||||
param[j] = paramNew[j];
|
||||
}
|
||||
// ... ïàðàìåòðû èç ôàéëà
|
||||
param[180] = 930;//rf.PsiZ, %*10 îò PSI_BAZ
|
||||
|
||||
param[200] = 2048;//offset.Ia1, åä. ÀÖÏ
|
||||
param[201] = 2048;//offset.Ib1, åä. ÀÖÏ
|
||||
param[202] = 2048;//offset.Ic1, åä. ÀÖÏ
|
||||
param[203] = 2048;//offset.Udc1, åä. ÀÖÏ
|
||||
param[206] = 2048;//offset.Ia2, åä. ÀÖÏ
|
||||
param[207] = 2048;//offset.Ib2, åä. ÀÖÏ
|
||||
param[208] = 2048;//offset.Ic2, åä. ÀÖÏ
|
||||
param[209] = 2048;//offset.Udc2, åä. ÀÖÏ
|
||||
|
||||
param[210] = 100;//cc.Kp, %
|
||||
param[211] = 100;//cc.Ki, %
|
||||
param[212] = 100;//cf.Kp, %
|
||||
param[213] = 100;//cf.Ki, %
|
||||
param[214] = 100;//csp.Kp, %
|
||||
param[215] = 100;//csp.Ki, %
|
||||
|
||||
param[220] = 99;//protect.IacMax, % îò IAC_SENS_MAX
|
||||
param[221] = 130;//protect.UdcMax, % îò U_NOM
|
||||
param[222] = 110;//IzLim, % îò I_BAZ (ä.á. áîëüøå cf.IdLim)
|
||||
param[223] = 105;//cf.IdLim, % îò I_BAZ (ä.á. ìåíüøå IzLim)
|
||||
param[224] = 105;//csp.IqLim, % îò I_BAZ
|
||||
param[225] = 97;//protect.UdcMin, % îò U_NOM
|
||||
param[226] = 115;//protect.WmMax, % îò N_NOM
|
||||
param[228] = 103;//rf.WmNomPsi, % îò N_NOM
|
||||
param[229] = 97;//rf.YlimPsi, % îò Y_LIM
|
||||
param[231] = 300;//protect.TudcMin, ìñ
|
||||
param[233] = 1000;//protect.TwmMax, ìñ
|
||||
|
||||
param[244] = 26000;//rs.WlimIncr, ìñ
|
||||
param[245] = 2000;//csp.IlimIncr, ìñ
|
||||
param[248] = 6000;//rp.PlimIncr, ìñ
|
||||
|
||||
param[269] = 9964;//9700;//KmeCorr, %*100
|
||||
|
||||
param[285] = 10;//Kudc, ìñ*10
|
||||
param[286] = 700;//Kwm, ìñ*10
|
||||
param[288] = 250;//rs.Kwmz, ìñ
|
||||
param[289] = 50;//rf.Kpsiz, ìñ
|
||||
param[290] = 40;//Kme, ìñ
|
||||
param[292] = 80;//rp.Kpmz, ìñ
|
||||
|
||||
param[303] = (unsigned short)(19200.);//sgmPar.Rs, ìêÎì
|
||||
param[304] = (unsigned short)(19364.);//sgmPar.Lls, ìêÃí*10
|
||||
param[305] = (unsigned short)(8500.);//sgmPar.Rr, ìêÎì
|
||||
param[306] = (unsigned short)(10212.);//sgmPar.Llr, ìêÃí*10
|
||||
param[307] = (unsigned short)(35810.);//sgmPar.Lm, ìêÃí
|
||||
|
||||
// èíèöèàëèçàöèÿ ïðîãðàììû
|
||||
detcoeff();
|
||||
|
||||
// äëÿ ìîäåëèðîâàíèÿ òàéìåðîâ
|
||||
T1Pr = (double)EPwm1Regs.TBPRD;
|
||||
T2Pr = (double)EPwm2Regs.TBPRD;
|
||||
T3Pr = (double)EPwm3Regs.TBPRD;
|
||||
T4Pr = (double)EPwm4Regs.TBPRD;
|
||||
T5Pr = (double)EPwm5Regs.TBPRD;
|
||||
T6Pr = (double)EPwm6Regs.TBPRD;
|
||||
t1cntAux = (double)EPwm1Regs.TBCTR;
|
||||
t2cntAux = (double)EPwm2Regs.TBCTR;
|
||||
t3cntAux = (double)EPwm3Regs.TBCTR;
|
||||
t4cntAux = (double)EPwm4Regs.TBCTR;
|
||||
t5cntAux = (double)EPwm5Regs.TBCTR;
|
||||
t6cntAux = (double)EPwm6Regs.TBCTR;
|
||||
// ... ïðèðàùåíèå ñ÷¸ò÷èêîâ òàéìåðîâ çà øàã äèñêðåòèçàöèè
|
||||
TxCntPlus = FTBCLK*dt;
|
||||
|
||||
// äëÿ ìîäåëèðîâàíèÿ eQEP
|
||||
Qposmax = (double)EQep2Regs.QPOSMAX;
|
||||
qposcnt = 1.;//(double)EQep2Regs.QPOSCNT;
|
||||
|
||||
// äëÿ ìîäåëèðîâàíèÿ ÀÖÏ
|
||||
// (íà ñ÷¸ò 1e-6 ñì. SetupAdc(), õîòÿ òàì ñêîðåå íå 1.0 ìêñ, à 0.8 ìêñ)
|
||||
Tadc = (int)(1e-6/dt);
|
||||
// ... íà âñÿêèé ñëó÷àé
|
||||
if ( Tadc < 1 )
|
||||
Tadc = 1;
|
||||
tAdc = 0;
|
||||
// ... ÷òîáû ÀÖÏ æäàë çàïóñêà
|
||||
nAdc = 10;
|
||||
|
||||
// äëÿ ìîäåëèðîâàíèÿ Dead-Band Unit
|
||||
CntDt = (int)(DT/dt);
|
||||
stateDt1 = stateDt2 = stateDt3 = stateDt4 = stateDt5 = stateDt6 = 1;
|
||||
cntDt1 = cntDt2 = cntDt3 = cntDt4 = cntDt5 = cntDt6 = 0;
|
||||
|
||||
// äëÿ çàùèò
|
||||
DI_24V_SOURCE_FAULT = 0;
|
||||
|
||||
// äëÿ âûâîäà
|
||||
inuWork = 0;
|
||||
ivc.psi = 0;
|
||||
rf.psiZ = 0;
|
||||
rs.wmZ = 0;
|
||||
csp.wmLimZi = 0;
|
||||
pm = 0;
|
||||
rp.pmZ = 0;
|
||||
csp.pmLimZi = 0;
|
||||
id1 = 0;
|
||||
iq1 = 0;
|
||||
idZ = 0;
|
||||
iqZ = 0;
|
||||
cf.idP = 0;
|
||||
cf.idFF = 0;
|
||||
cf.idI = 0;
|
||||
csp.iqP = 0;
|
||||
csp.iqFF = 0;
|
||||
csp.iqI = 0;
|
||||
cc.yd1 = 0;
|
||||
cc.yq1 = 0;
|
||||
cc.y1 = 0;
|
||||
} //if ( iW[1] == 1 )
|
||||
|
||||
|
||||
|
||||
|
||||
// Ìîäåëèðóåì Time-Base Submodule, Counter-Compare Submodule è
|
||||
// Event-Trigger Submodule
|
||||
// ePWM1 (up-down-count mode)
|
||||
// -------------------------
|
||||
t1cntAuxPrev = t1cntAux;
|
||||
t1cntAux += TxCntPlus;
|
||||
if ( t1cntAux > T1Pr ) {
|
||||
t1cntAux -= T1Pr*2.;
|
||||
// active CMPA load from shadow when TBCTR == TBPRD
|
||||
cmp1A = (double)EPwm1Regs.CMPA.half.CMPA;
|
||||
// çàïóñê ÀÖÏ
|
||||
tAdc = Tadc;
|
||||
nAdc = 0;
|
||||
}
|
||||
if ( (t1cntAuxPrev < 0) && (t1cntAux >= 0) ) {
|
||||
// active CMPA load from shadow when TBCTR == 0
|
||||
cmp1A = (double)EPwm1Regs.CMPA.half.CMPA;
|
||||
// çàïóñê ÀÖÏ
|
||||
tAdc = Tadc;
|
||||
nAdc = 0;
|
||||
}
|
||||
t1cnt = fabs(t1cntAux);
|
||||
|
||||
// ePWM2 (up-down-count mode)
|
||||
// -------------------------
|
||||
t2cntAuxPrev = t2cntAux;
|
||||
t2cntAux += TxCntPlus;
|
||||
if ( t2cntAux > T2Pr ) {
|
||||
t2cntAux -= T2Pr*2.;
|
||||
// active CMPA load from shadow when TBCTR == TBPRD
|
||||
cmp2A = (double)EPwm2Regs.CMPA.half.CMPA;
|
||||
}
|
||||
if ( (t2cntAuxPrev < 0) && (t2cntAux >= 0) ) {
|
||||
// active CMPA load from shadow when TBCTR == 0
|
||||
cmp2A = (double)EPwm2Regs.CMPA.half.CMPA;
|
||||
}
|
||||
t2cnt = fabs(t2cntAux);
|
||||
|
||||
// ePWM3 (up-down-count mode)
|
||||
// -------------------------
|
||||
t3cntAuxPrev = t3cntAux;
|
||||
t3cntAux += TxCntPlus;
|
||||
if ( t3cntAux > T3Pr ) {
|
||||
t3cntAux -= T3Pr*2.;
|
||||
// active CMPA load from shadow when TBCTR == TBPRD
|
||||
cmp3A = (double)EPwm3Regs.CMPA.half.CMPA;
|
||||
}
|
||||
if ( (t3cntAuxPrev < 0) && (t3cntAux >= 0) ) {
|
||||
// active CMPA load from shadow when TBCTR == 0
|
||||
cmp3A = (double)EPwm3Regs.CMPA.half.CMPA;
|
||||
}
|
||||
t3cnt = fabs(t3cntAux);
|
||||
|
||||
// ePWM4 (up-down-count mode)
|
||||
// -------------------------
|
||||
t4cntAuxPrev = t4cntAux;
|
||||
t4cntAux += TxCntPlus;
|
||||
if ( t4cntAux > T4Pr ) {
|
||||
t4cntAux -= T4Pr*2.;
|
||||
// active CMPA load from shadow when TBCTR == TBPRD
|
||||
cmp4A = (double)EPwm4Regs.CMPA.half.CMPA;
|
||||
}
|
||||
if ( (t4cntAuxPrev < 0) && (t4cntAux >= 0) ) {
|
||||
// active CMPA load from shadow when TBCTR == 0
|
||||
cmp4A = (double)EPwm4Regs.CMPA.half.CMPA;
|
||||
}
|
||||
t4cnt = fabs(t4cntAux);
|
||||
|
||||
// ePWM5 (up-down-count mode)
|
||||
// -------------------------
|
||||
t5cntAuxPrev = t5cntAux;
|
||||
t5cntAux += TxCntPlus;
|
||||
if ( t5cntAux > T5Pr ) {
|
||||
t5cntAux -= T5Pr*2.;
|
||||
// active CMPA load from shadow when TBCTR == TBPRD
|
||||
cmp5A = (double)EPwm5Regs.CMPA.half.CMPA;
|
||||
}
|
||||
if ( (t5cntAuxPrev < 0) && (t5cntAux >= 0) ) {
|
||||
// active CMPA load from shadow when TBCTR == 0
|
||||
cmp5A = (double)EPwm5Regs.CMPA.half.CMPA;
|
||||
}
|
||||
t5cnt = fabs(t5cntAux);
|
||||
|
||||
// ePWM6 (up-down-count mode)
|
||||
// -------------------------
|
||||
t6cntAuxPrev = t6cntAux;
|
||||
t6cntAux += TxCntPlus;
|
||||
if ( t6cntAux > T6Pr ) {
|
||||
t6cntAux -= T6Pr*2.;
|
||||
// active CMPA load from shadow when TBCTR == TBPRD
|
||||
cmp6A = (double)EPwm6Regs.CMPA.half.CMPA;
|
||||
}
|
||||
if ( (t6cntAuxPrev < 0) && (t6cntAux >= 0) ) {
|
||||
// active CMPA load from shadow when TBCTR == 0
|
||||
cmp6A = (double)EPwm6Regs.CMPA.half.CMPA;
|
||||
}
|
||||
t6cnt = fabs(t6cntAux);
|
||||
|
||||
|
||||
// Ìîäåëèðóåì ðàáîòó ñ÷¸ò÷èêà â eQEP
|
||||
qposcnt += wm_ml/PI2*NOP*4.*dt;
|
||||
if ( qposcnt >= (Qposmax + 1.) )
|
||||
qposcnt -= (Qposmax + 1.);
|
||||
else if ( qposcnt < 0 )
|
||||
qposcnt += (Qposmax + 1.);
|
||||
EQep2Regs.QPOSCNT = (short)qposcnt;
|
||||
|
||||
|
||||
/* Ìîäåëèðóåì ïðåîáðàçîâàíèÿ èçìåðÿåìûõ âåëè÷èí äàò÷èêàìè,
|
||||
îïåðàöèîííèêàìè è ÀÖÏ (ñ ïîìîùüþ nAdc ó÷èòûâàåì ñäâèã ïî âðåìåíè
|
||||
ìåæäó ÀÖÏ ðàçíûõ ñèãíàëîâ) */
|
||||
if ( tAdc < Tadc ) {
|
||||
tAdc++;
|
||||
}
|
||||
else {
|
||||
tAdc = 1;
|
||||
nAdc++;
|
||||
switch ( nAdc ) {
|
||||
case 5:
|
||||
// Udc1
|
||||
if ( udc1_ml > UDC_SENS_MAX )
|
||||
udc1_ml = UDC_SENS_MAX;
|
||||
else if ( udc1_ml < -UDC_SENS_MAX )
|
||||
udc1_ml = -UDC_SENS_MAX;
|
||||
AdcMirror.ADCRESULT0 =
|
||||
(unsigned short)(udc1_ml/UDC_SENS_MAX*2048. + (float)offset.Udc1);
|
||||
// Ic1
|
||||
if ( ic1_ml > IAC_SENS_MAX )
|
||||
ic1_ml = IAC_SENS_MAX;
|
||||
else if ( ic1_ml < -IAC_SENS_MAX )
|
||||
ic1_ml = -IAC_SENS_MAX;
|
||||
AdcMirror.ADCRESULT2 =
|
||||
(unsigned short)(ic1_ml/IAC_SENS_MAX*2048. + (float)offset.Ic1);
|
||||
break;
|
||||
case 6:
|
||||
// Ia1
|
||||
if ( ia1_ml > IAC_SENS_MAX )
|
||||
ia1_ml = IAC_SENS_MAX;
|
||||
else if ( ia1_ml < -IAC_SENS_MAX )
|
||||
ia1_ml = -IAC_SENS_MAX;
|
||||
AdcMirror.ADCRESULT4 =
|
||||
(unsigned short)(ia1_ml/IAC_SENS_MAX*2048. + (float)offset.Ia1);
|
||||
// Ib1
|
||||
if ( ib1_ml > IAC_SENS_MAX )
|
||||
ib1_ml = IAC_SENS_MAX;
|
||||
else if ( ib1_ml < -IAC_SENS_MAX )
|
||||
ib1_ml = -IAC_SENS_MAX;
|
||||
AdcMirror.ADCRESULT6 =
|
||||
(unsigned short)(ib1_ml/IAC_SENS_MAX*2048. + (float)offset.Ib1);
|
||||
break;
|
||||
case 7:
|
||||
// êàê áû ñ ÏÓ
|
||||
for ( j = FIRST_WRITE_PAR_NUM; j < paramNo; j++ ) {
|
||||
if ( paramNew[j] != param[j] ) {
|
||||
input_param((short)j, paramNew[j]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
// ïîñëå çàâåðøåíèÿ ñåðèè ÀÖÏ âûçûâàåì isr()
|
||||
isr();
|
||||
break;
|
||||
} //switch ( nAdc )
|
||||
} //tAdc
|
||||
|
||||
|
||||
// Ìîäåëèðóåì Action-Qualifier Submodule
|
||||
// ... ePWM1
|
||||
if ( cmp1A > t1cnt ) {
|
||||
ci1A = 1;
|
||||
ci1B = 0;
|
||||
}
|
||||
else if ( cmp1A < t1cnt ) {
|
||||
ci1A = 0;
|
||||
ci1B = 1;
|
||||
}
|
||||
// ... ePWM2
|
||||
if ( cmp2A < t2cnt ) {
|
||||
ci2A = 1;
|
||||
ci2B = 0;
|
||||
}
|
||||
else if ( cmp2A > t2cnt ) {
|
||||
ci2A = 0;
|
||||
ci2B = 1;
|
||||
}
|
||||
// ... ePWM3
|
||||
if ( cmp3A > t3cnt ) {
|
||||
ci3A = 1;
|
||||
ci3B = 0;
|
||||
}
|
||||
else if ( cmp3A < t3cnt ) {
|
||||
ci3A = 0;
|
||||
ci3B = 1;
|
||||
}
|
||||
// ... ePWM4
|
||||
if ( cmp4A < t4cnt ) {
|
||||
ci4A = 1;
|
||||
ci4B = 0;
|
||||
}
|
||||
else if ( cmp4A > t4cnt ) {
|
||||
ci4A = 0;
|
||||
ci4B = 1;
|
||||
}
|
||||
// ... ePWM5
|
||||
if ( cmp5A > t5cnt ) {
|
||||
ci5A = 1;
|
||||
ci5B = 0;
|
||||
}
|
||||
else if ( cmp5A < t5cnt ) {
|
||||
ci5A = 0;
|
||||
ci5B = 1;
|
||||
}
|
||||
// ... ePWM6
|
||||
if ( cmp6A < t6cnt ) {
|
||||
ci6A = 1;
|
||||
ci6B = 0;
|
||||
}
|
||||
else if ( cmp6A > t6cnt ) {
|
||||
ci6A = 0;
|
||||
ci6B = 1;
|
||||
}
|
||||
|
||||
|
||||
// Ìîäåëèðóåì Dead-Band Submodule
|
||||
// ... ePWM1
|
||||
if ( stateDt1 == 1 ) {
|
||||
ci1A_DT = ci1A;
|
||||
ci1B_DT = 0;
|
||||
if ( ci1A == 1 )
|
||||
cntDt1 = CntDt;
|
||||
if ( cntDt1 > 0 )
|
||||
cntDt1--;
|
||||
else
|
||||
stateDt1 = 2;
|
||||
}
|
||||
else if ( stateDt1 == 2 ) {
|
||||
ci1A_DT = 0;
|
||||
ci1B_DT = ci1B;
|
||||
if ( ci1B == 1 )
|
||||
cntDt1 = CntDt;
|
||||
if ( cntDt1 > 0 )
|
||||
cntDt1--;
|
||||
else
|
||||
stateDt1 = 1;
|
||||
}
|
||||
// ... ePWM2
|
||||
if ( stateDt2 == 1 ) {
|
||||
ci2A_DT = ci2A;
|
||||
ci2B_DT = 0;
|
||||
if ( ci2A == 1 )
|
||||
cntDt2 = CntDt;
|
||||
if ( cntDt2 > 0 )
|
||||
cntDt2--;
|
||||
else
|
||||
stateDt2 = 2;
|
||||
}
|
||||
else if ( stateDt2 == 2 ) {
|
||||
ci2A_DT = 0;
|
||||
ci2B_DT = ci2B;
|
||||
if ( ci2B == 1 )
|
||||
cntDt2 = CntDt;
|
||||
if ( cntDt2 > 0 )
|
||||
cntDt2--;
|
||||
else
|
||||
stateDt2 = 1;
|
||||
}
|
||||
// ... ePWM3
|
||||
if ( stateDt3 == 1 ) {
|
||||
ci3A_DT = ci3A;
|
||||
ci3B_DT = 0;
|
||||
if ( ci3A == 1 )
|
||||
cntDt3 = CntDt;
|
||||
if ( cntDt3 > 0 )
|
||||
cntDt3--;
|
||||
else
|
||||
stateDt3 = 2;
|
||||
}
|
||||
else if ( stateDt3 == 2 ) {
|
||||
ci3A_DT = 0;
|
||||
ci3B_DT = ci3B;
|
||||
if ( ci3B == 1 )
|
||||
cntDt3 = CntDt;
|
||||
if ( cntDt3 > 0 )
|
||||
cntDt3--;
|
||||
else
|
||||
stateDt3 = 1;
|
||||
}
|
||||
// ... ePWM4
|
||||
if ( stateDt4 == 1 ) {
|
||||
ci4A_DT = ci4A;
|
||||
ci4B_DT = 0;
|
||||
if ( ci4A == 1 )
|
||||
cntDt4 = CntDt;
|
||||
if ( cntDt4 > 0 )
|
||||
cntDt4--;
|
||||
else
|
||||
stateDt4 = 2;
|
||||
}
|
||||
else if ( stateDt4 == 2 ) {
|
||||
ci4A_DT = 0;
|
||||
ci4B_DT = ci4B;
|
||||
if ( ci4B == 1 )
|
||||
cntDt4 = CntDt;
|
||||
if ( cntDt4 > 0 )
|
||||
cntDt4--;
|
||||
else
|
||||
stateDt4 = 1;
|
||||
}
|
||||
// ... ePWM5
|
||||
if ( stateDt5 == 1 ) {
|
||||
ci5A_DT = ci5A;
|
||||
ci5B_DT = 0;
|
||||
if ( ci5A == 1 )
|
||||
cntDt5 = CntDt;
|
||||
if ( cntDt5 > 0 )
|
||||
cntDt5--;
|
||||
else
|
||||
stateDt5 = 2;
|
||||
}
|
||||
else if ( stateDt5 == 2 ) {
|
||||
ci5A_DT = 0;
|
||||
ci5B_DT = ci5B;
|
||||
if ( ci5B == 1 )
|
||||
cntDt5 = CntDt;
|
||||
if ( cntDt5 > 0 )
|
||||
cntDt5--;
|
||||
else
|
||||
stateDt5 = 1;
|
||||
}
|
||||
// ... ePWM6
|
||||
if ( stateDt6 == 1 ) {
|
||||
ci6A_DT = ci6A;
|
||||
ci6B_DT = 0;
|
||||
if ( ci6A == 1 )
|
||||
cntDt6 = CntDt;
|
||||
if ( cntDt6 > 0 )
|
||||
cntDt6--;
|
||||
else
|
||||
stateDt6 = 2;
|
||||
}
|
||||
else if ( stateDt6 == 2 ) {
|
||||
ci6A_DT = 0;
|
||||
ci6B_DT = ci6B;
|
||||
if ( ci6B == 1 )
|
||||
cntDt6 = CntDt;
|
||||
if ( cntDt6 > 0 )
|
||||
cntDt6--;
|
||||
else
|
||||
stateDt6 = 1;
|
||||
}
|
||||
|
||||
|
||||
// Ìîäåëèðóåì Trip-Zone Submodule
|
||||
// ... clear flag for one-shot trip latch
|
||||
if ( EPwm1Regs.TZCLR.all == 0x0004 ) {
|
||||
EPwm1Regs.TZCLR.all = 0x0000;
|
||||
EPwm1Regs.TZFRC.all = 0x0000;
|
||||
}
|
||||
if ( EPwm2Regs.TZCLR.all == 0x0004 ) {
|
||||
EPwm2Regs.TZCLR.all = 0x0000;
|
||||
EPwm2Regs.TZFRC.all = 0x0000;
|
||||
}
|
||||
if ( EPwm3Regs.TZCLR.all == 0x0004 ) {
|
||||
EPwm3Regs.TZCLR.all = 0x0000;
|
||||
EPwm3Regs.TZFRC.all = 0x0000;
|
||||
}
|
||||
if ( EPwm4Regs.TZCLR.all == 0x0004 ) {
|
||||
EPwm4Regs.TZCLR.all = 0x0000;
|
||||
EPwm4Regs.TZFRC.all = 0x0000;
|
||||
}
|
||||
if ( EPwm5Regs.TZCLR.all == 0x0004 ) {
|
||||
EPwm5Regs.TZCLR.all = 0x0000;
|
||||
EPwm5Regs.TZFRC.all = 0x0000;
|
||||
}
|
||||
if ( EPwm6Regs.TZCLR.all == 0x0004 ) {
|
||||
EPwm6Regs.TZCLR.all = 0x0000;
|
||||
EPwm6Regs.TZFRC.all = 0x0000;
|
||||
}
|
||||
|
||||
// ... forces a one-shot trip event
|
||||
if ( EPwm1Regs.TZFRC.all == 0x0004 )
|
||||
ci1A_DT = ci1B_DT = 0;
|
||||
if ( EPwm2Regs.TZFRC.all == 0x0004 )
|
||||
ci2A_DT = ci2B_DT = 0;
|
||||
if ( EPwm3Regs.TZFRC.all == 0x0004 )
|
||||
ci3A_DT = ci3B_DT = 0;
|
||||
if ( EPwm4Regs.TZFRC.all == 0x0004 )
|
||||
ci4A_DT = ci4B_DT = 0;
|
||||
if ( EPwm5Regs.TZFRC.all == 0x0004 )
|
||||
ci5A_DT = ci5B_DT = 0;
|
||||
if ( EPwm6Regs.TZFRC.all == 0x0004 )
|
||||
ci6A_DT = ci6B_DT = 0;
|
||||
|
||||
|
||||
|
||||
|
||||
// ÂÛÕÎÄÛ (begin)
|
||||
nn = 0;
|
||||
// Óïðàâëåíèå
|
||||
// ... INU1
|
||||
xD[nn++] = ci1A_DT;
|
||||
xD[nn++] = ci2A_DT;
|
||||
xD[nn++] = ci1B_DT;
|
||||
xD[nn++] = ci2B_DT;
|
||||
|
||||
xD[nn++] = ci3A_DT;
|
||||
xD[nn++] = ci4A_DT;
|
||||
xD[nn++] = ci3B_DT;
|
||||
xD[nn++] = ci4B_DT;
|
||||
|
||||
xD[nn++] = ci5A_DT;
|
||||
xD[nn++] = ci6A_DT;
|
||||
xD[nn++] = ci5B_DT;
|
||||
xD[nn++] = ci6B_DT;
|
||||
|
||||
// Òîëüêî äëÿ ïðîñìîòðà
|
||||
xD[nn++] = state;
|
||||
xD[nn++] = faultNo;
|
||||
|
||||
xD[nn++] = mst.start;
|
||||
xD[nn++] = inuWork;
|
||||
xD[nn++] = mst.pzMode;
|
||||
|
||||
xD[nn++] = psi;
|
||||
xD[nn++] = rf.psiZ;
|
||||
|
||||
xD[nn++] = wm;
|
||||
xD[nn++] = rs.wmZ;
|
||||
xD[nn++] = csp.wmLimZi;
|
||||
|
||||
xD[nn++] = pm*S_BAZ/P_NOM;
|
||||
xD[nn++] = rp.pmZ*S_BAZ/P_NOM;
|
||||
xD[nn++] = csp.pmLimZi*S_BAZ/P_NOM;
|
||||
|
||||
xD[nn++] = id1;
|
||||
xD[nn++] = iq1;
|
||||
xD[nn++] = idZ;
|
||||
xD[nn++] = iqZ;
|
||||
|
||||
xD[nn++] = me*M_BAZ/M_NOM;
|
||||
|
||||
xD[nn++] = sqrt(idZ*idZ + iqZ*iqZ);
|
||||
xD[nn++] = IzLim;
|
||||
|
||||
xD[nn++] = sqrt(cc.yd1*cc.yd1 + cc.yq1*cc.yq1);
|
||||
xD[nn++] = Y_LIM;
|
||||
|
||||
xD[nn++] = theta_out;
|
||||
// ÂÛÕÎÄÛ (end)
|
||||
|
||||
} //void controller(SimStruct ...
|
||||
229
Inu_im_1wnd_3lvl/Inu/controller.h
Normal file
229
Inu_im_1wnd_3lvl/Inu/controller.h
Normal file
@@ -0,0 +1,229 @@
|
||||
// Ìàêñèìàëüíàÿ äëèíà ïàðàìåòðà-âåêòîðà
|
||||
#define LEN_PARAM_MATR 21
|
||||
|
||||
// Ìàññèâû ñ ïàðàìåòðàìè S_Function
|
||||
double paramScal[NPARAMS];
|
||||
double paramMatr[LEN_PARAM_MATR*2];
|
||||
int paramMatrDimen;
|
||||
|
||||
// Èíäåêñ âõîäíîãî è âûõîäíîãî ìàññèâà, à òàêæå ìàññèâà ïàðàìåòðîâ
|
||||
int nn;
|
||||
// Øàã èíòåãðèðîâàíèÿ
|
||||
double dt;
|
||||
// Äëÿ îáðàáîòêè ïàðàìåòðîâ
|
||||
int kkk, lll, mmm, dimen;
|
||||
|
||||
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â controller.c (begin)
|
||||
//#########################################################################
|
||||
// Ïàðàìåòðû
|
||||
//double ;
|
||||
|
||||
// Âõîäû
|
||||
double udc1_ml;
|
||||
double ia1_ml;
|
||||
double ib1_ml;
|
||||
double ic1_ml;
|
||||
double wm_ml;
|
||||
double wm_ml_0;
|
||||
double iref;
|
||||
|
||||
// Äëÿ èìèòàöèè îáìåíà ñ ÏÓ
|
||||
int j;
|
||||
unsigned short paramNo;
|
||||
unsigned short paramNew[PAR_NUMBER];
|
||||
|
||||
// Äëÿ ìîäåëèðîâàíèÿ Event Manager
|
||||
// ... Time-Base Submodule, Counter-Compare Submodule è Event-Trigger Submodule
|
||||
double TxCntPlus;
|
||||
double T1Pr;
|
||||
double t1cntAux;
|
||||
double t1cntAuxPrev;
|
||||
double t1cnt;
|
||||
double cmp1A;
|
||||
double cmp1B;
|
||||
|
||||
double T2Pr;
|
||||
double t2cntAux;
|
||||
double t2cntAuxPrev;
|
||||
double t2cnt;
|
||||
double cmp2A;
|
||||
double cmp2B;
|
||||
|
||||
double T3Pr;
|
||||
double t3cntAux;
|
||||
double t3cntAuxPrev;
|
||||
double t3cnt;
|
||||
double cmp3A;
|
||||
double cmp3B;
|
||||
|
||||
double T4Pr;
|
||||
double t4cntAux;
|
||||
double t4cntAuxPrev;
|
||||
double t4cnt;
|
||||
double cmp4A;
|
||||
double cmp4B;
|
||||
|
||||
double T5Pr;
|
||||
double t5cntAux;
|
||||
double t5cntAuxPrev;
|
||||
double t5cnt;
|
||||
double cmp5A;
|
||||
double cmp5B;
|
||||
|
||||
double T6Pr;
|
||||
double t6cntAux;
|
||||
double t6cntAuxPrev;
|
||||
double t6cnt;
|
||||
double cmp6A;
|
||||
double cmp6B;
|
||||
|
||||
|
||||
|
||||
// ... Action-Qualifier Submodule
|
||||
int ci1A;
|
||||
int ci1B;
|
||||
int ci2A;
|
||||
int ci2B;
|
||||
int ci3A;
|
||||
int ci3B;
|
||||
int ci4A;
|
||||
int ci4B;
|
||||
int ci5A;
|
||||
int ci5B;
|
||||
int ci6A;
|
||||
int ci6B;
|
||||
// ... Dead-Band Submodule
|
||||
int CntDt;
|
||||
int stateDt1;
|
||||
int cntDt1;
|
||||
int ci1A_DT;
|
||||
int ci1B_DT;
|
||||
|
||||
int stateDt2;
|
||||
int cntDt2;
|
||||
int ci2A_DT;
|
||||
int ci2B_DT;
|
||||
|
||||
int stateDt3;
|
||||
int cntDt3;
|
||||
int ci3A_DT;
|
||||
int ci3B_DT;
|
||||
|
||||
int stateDt4;
|
||||
int cntDt4;
|
||||
int ci4A_DT;
|
||||
int ci4B_DT;
|
||||
|
||||
int stateDt5;
|
||||
int cntDt5;
|
||||
int ci5A_DT;
|
||||
int ci5B_DT;
|
||||
|
||||
int stateDt6;
|
||||
int cntDt6;
|
||||
int ci6A_DT;
|
||||
int ci6B_DT;
|
||||
|
||||
|
||||
// Äëÿ ìîäåëèðîâàíèÿ eQEP
|
||||
double Qposmax;
|
||||
double qposcnt;
|
||||
|
||||
// Äëÿ ìîäåëèðîâàíèÿ ADC
|
||||
int tAdc;
|
||||
int Tadc;
|
||||
int nAdc;
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â controller.c (end)
|
||||
|
||||
|
||||
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â controller.c (begin)
|
||||
//#########################################################################
|
||||
// Äëÿ isr.c
|
||||
//-------------------------------------------------------------------------
|
||||
extern struct Offset offset;
|
||||
extern volatile struct Result result;
|
||||
extern volatile short state;
|
||||
extern volatile short faultNo;
|
||||
extern volatile struct Out out;
|
||||
// Udc
|
||||
extern float Kudc;
|
||||
extern volatile float udc1Nf;
|
||||
extern volatile float udc1;
|
||||
// Iac
|
||||
extern volatile float ia1Nf;
|
||||
extern volatile float ib1Nf;
|
||||
extern volatile float ix1;
|
||||
extern volatile float iy1;
|
||||
extern volatile float iac1Nf;
|
||||
// Wm
|
||||
extern float Kwm;
|
||||
extern volatile float wmNf;
|
||||
extern volatile float wm;
|
||||
extern volatile float wmAbs;
|
||||
// Me
|
||||
extern volatile float kMe;
|
||||
extern float KmeCorr;
|
||||
extern float Kme;
|
||||
extern volatile float meNf;
|
||||
extern volatile float me;
|
||||
// Pm
|
||||
extern volatile float pm;
|
||||
// çàùèòû
|
||||
extern struct Protect protect;
|
||||
extern volatile struct Emerg emerg;
|
||||
extern short csmSuccess;
|
||||
// óïðàâëÿþùàÿ ëîãèêà
|
||||
extern volatile short onceShutdown;
|
||||
extern volatile short testParamFaultNo;
|
||||
extern volatile short onceFaultReset;
|
||||
extern volatile short stopPause;
|
||||
extern volatile short inuWork;
|
||||
// îáìåí
|
||||
extern struct Mst mst;
|
||||
|
||||
|
||||
|
||||
// Äëÿ main.c
|
||||
//-------------------------------------------------------------------------
|
||||
extern struct Eprom eprom;
|
||||
|
||||
|
||||
|
||||
// Äëÿ upr.c
|
||||
//-------------------------------------------------------------------------
|
||||
extern volatile short onceUpr;
|
||||
extern struct SgmPar sgmPar;
|
||||
extern struct Rf rf;
|
||||
extern struct Rs rs;
|
||||
extern struct Rp rp;
|
||||
|
||||
extern float IzLim;
|
||||
extern volatile float psi;
|
||||
extern float idZ;
|
||||
extern float iqZ;
|
||||
extern float iZ;
|
||||
extern float ws;
|
||||
extern float sinTheta;
|
||||
extern float cosTheta;
|
||||
extern float id1;
|
||||
extern float iq1;
|
||||
extern float id2;
|
||||
extern float iq2;
|
||||
extern struct Cc cc;
|
||||
extern struct Cf cf;
|
||||
extern struct Csp csp;
|
||||
extern struct Ivc ivc;
|
||||
extern struct Ip ip;
|
||||
extern volatile float theta_out; // óãîë ? äëß âûâîäà
|
||||
|
||||
|
||||
// Äëÿ param.c
|
||||
//-------------------------------------------------------------------------
|
||||
extern unsigned short param[];
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â controller.c (end)
|
||||
482
Inu_im_1wnd_3lvl/Inu/def.h
Normal file
482
Inu_im_1wnd_3lvl/Inu/def.h
Normal file
@@ -0,0 +1,482 @@
|
||||
/**************************************************************************
|
||||
Description: Âñÿêèå ðàçíûå ïåðåêëþ÷àòåëè è óñòàâêè.
|
||||
|
||||
Àâòîð: Óëèòîâñêèé Ä.È.
|
||||
Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.11.08
|
||||
**************************************************************************/
|
||||
|
||||
#ifndef DEF
|
||||
#define DEF
|
||||
|
||||
// ðàñêîììåíòèðîâàòü, åñëè åñòü ñäâèã ìåæäó îáìîòêàìè ÃÝÄ (30 ãðàä.)
|
||||
#define SHIFT
|
||||
|
||||
|
||||
// ðåæèìû ðàáîòû (äëÿ state)
|
||||
#define STATE_SHUTDOWN 0 //àâàðèéíàÿ îñòàíîâêà
|
||||
#define STATE_STOP 1 //øòàòíàÿ îñòàíîâêà
|
||||
#define STATE_WORK 2 //ðàáîòà
|
||||
|
||||
|
||||
// ÷àñòîòà òàêòîâûõ èìïóëüñîâ ïðîöåññîðà, Ãö
|
||||
#define FSYSCLKOUT 200e6 //150e6 //
|
||||
// prescaled version of the system clock and is used by
|
||||
// all submodules within the ePWM, Ãö
|
||||
// (ñì. EPwmxRegs.TBCTL.bit.CLKDIV è EPwmxRegs.TBCTL.bit.HSPCLKDIV)
|
||||
#define FTBCLK (FSYSCLKOUT*0.5*0.5)
|
||||
//#define FTBCLK (FSYSCLKOUT*0.5*0.5*0.5*0.5)
|
||||
// ïåðèîä ØÈÌ, c
|
||||
#define T_PWM 2220e-6 //F_PWM = 450 Ãö
|
||||
//#define T_PWM 6000e-6 //F_PWM = 166.7 Ãö
|
||||
// ïåðèîä âûçîâà îñíîâíîé ïðîãðàììû, ñ
|
||||
#define TY (T_PWM*0.5)
|
||||
// "ìåðòâîå âðåìÿ", ñ
|
||||
#define DT 30e-6
|
||||
//#define DT 60e-6
|
||||
// Time-Base Period Register, åä. ñ÷¸ò÷èêà òàéìåðà
|
||||
#define T1_PRD (FTBCLK*T_PWM*0.5)
|
||||
// ìàêñèìàëüíîå çíà÷åíèå àìïëèòóäû íàïðÿæåíèÿ óïðàâëåíèÿ óñòàíàâëèâàåì òàê,
|
||||
// ÷òîáû ìèíèìàëüíàÿ øèðèíà èìïóëüñà áûëà 10 ìêñ, åä. ñ÷¸ò÷èêà òàéìåðà
|
||||
#define Y_LIM (T1_PRD - (DT + 10e-6)*FTBCLK)
|
||||
|
||||
|
||||
// êîíñòàíòû äëÿ âû÷èñëåíèÿ âñÿêîãî
|
||||
#define PI2 6.283185307179586476925286766559 //pi*2
|
||||
#define SQRT2 1.4142135623730950488016887242097 //sqrt(2)
|
||||
#define SQRT3 1.7320508075688772935274463415059 //sqrt(3)
|
||||
#define ISQRT3 0.57735026918962576450914878050196 //1./sqrt(3)
|
||||
|
||||
// Íîìèíàëüíûå âåëè÷èíû ÃÝÄ
|
||||
// ... ìîùíîñòü íà âàëó, Âò
|
||||
#define P_NOM (5000e3)
|
||||
// ... ëèíåéíîå íàïðÿæåíèå, Â (ampl)
|
||||
#define U_NOM (3000.*SQRT2)
|
||||
// ... ìåõàíè÷åñêàÿ ñêîðîñòü, îá/ìèí
|
||||
#define N_NOM 165.
|
||||
// ... ÷èñëî ïàð ïîëþñîâ
|
||||
#define PP 6.
|
||||
// ... êîýôôèöèåíò ìîùíîñòè
|
||||
#define COS_FI 0.89
|
||||
// ... ÊÏÄ
|
||||
#define EFF 0.962
|
||||
// ... ïðèâåäåííûé ê âàëó ìîìåíò èíåðöèè, êã*ì^2
|
||||
#define J (87e3)
|
||||
// ... ïîëíàÿ ìîùíîñòü, ÂÀ
|
||||
#define S_NOM (P_NOM/(COS_FI*EFF))
|
||||
// ... ìåõàíè÷åñêàÿ ñêîðîñòü, ðàä/ñ
|
||||
#define WM_NOM (N_NOM/60.*PI2)
|
||||
// ... ìîìåíò íà âàëó, Í*ì
|
||||
#define M_NOM (P_NOM/WM_NOM)
|
||||
|
||||
|
||||
// Áàçîâûå âåëè÷èíû ÃÝÄ
|
||||
// ... ïîëíàÿ ìîùíîñòü, BA
|
||||
#define S_BAZ S_NOM
|
||||
// ... ëèíåéíîå íàïðÿæåíèå, Â (ampl)
|
||||
#define U_BAZ U_NOM
|
||||
// ... ôàçíûé òîê, À (ampl)
|
||||
#define I_BAZ (S_BAZ*2./(U_BAZ*SQRT3)) //0.5 - ò.ê. îáìîòîê äâå
|
||||
// ... ìåõàíè÷åñêàÿ ñêîðîñòü, îá/ìèí
|
||||
#define N_BAZ N_NOM
|
||||
// ... ìåõàíè÷åñêàÿ ñêîðîñòü, ðàä/ñ
|
||||
#define WM_BAZ (N_BAZ/60.*PI2)
|
||||
// ... ýëåêòðè÷åñêàÿ ñêîðîñòü, ðàä/ñ
|
||||
#define WE_BAZ (WM_BAZ*PP)
|
||||
// ... ìîìåíò íà âàëó, Í*ì
|
||||
#define M_BAZ (S_BAZ/WM_BAZ)
|
||||
// ... ïîòîêîñöåïëåíèå ñòàòîðà, Âá
|
||||
#define PSI_BAZ (U_BAZ/(WE_BAZ*SQRT3))
|
||||
// ... èíäóêòèâíîñòü, Ãí
|
||||
#define L_BAZ (PSI_BAZ/I_BAZ)
|
||||
// ... ñîïðîòèâëåíèå, Îì
|
||||
#define R_BAZ (U_BAZ/(I_BAZ*SQRT3))
|
||||
|
||||
|
||||
// äëÿ ïåðåñ÷¸òà èç àìïëèòóäû ôàçíîãî íàïðÿæåíèÿ â åäèíèöû ñèãíàëà óïðàâëåíèÿ
|
||||
#define U_2_Y (T1_PRD*SQRT3/U_BAZ)
|
||||
|
||||
// íàïðÿæåíèå â çâåíå ïîñò. òîêà, êîòîðîå äàëî áû íà âûõîäå ÀÖÏ çíà÷. 2048, Â
|
||||
#define UDC_SENS_MAX (U_BAZ*1.15*1.3)
|
||||
// âûõîäíîé òîê, êîòîðûé äàë áû íà âûõîäå ÀÖÏ çíà÷. 2048, À (ampl)
|
||||
#define IAC_SENS_MAX (I_BAZ*1.5)
|
||||
// number of pulses per rev. (from tacho, Hall, optical sensor...etc)
|
||||
#define NOP 1024.
|
||||
// ïðèðàùåíèå ñ÷¸ò÷èêà QEP çà TY ñåê. ïðè ÷àñòîòå âðàù. WM_BAZ
|
||||
#define QEP_CNT_DEL_NOM (NOP*4.*TY*WM_BAZ/PI2)
|
||||
|
||||
|
||||
// êîýôôèöèåíòû äëÿ ïåðåâîäà èçìåðåííûõ âåëè÷èí â o.e.
|
||||
#define GAIN_UDC (UDC_SENS_MAX/(2048.*U_BAZ))
|
||||
#define GAIN_IAC (IAC_SENS_MAX/(2048.*I_BAZ))
|
||||
#define GAIN_WM (1.0/QEP_CNT_DEL_NOM)
|
||||
|
||||
|
||||
// ìèíèìàëüíàÿ ñêîðîñòü äëÿ ïåðåñ÷¸òà ìîùíîñòè â òîê, o.e.
|
||||
#define WM_MIN 0.03 //0.003 //?
|
||||
// äëÿ ïðîðåæèâàíèÿ ðåãóëÿòîðîâ ïîòîêà, ñêîðîñòè è ìîùíîñòè
|
||||
#define DECIM_PSI_WM_PM 2. //1. //5. //?
|
||||
|
||||
|
||||
// for specify the PLL
|
||||
#define PLLSTS_DIVSEL 2
|
||||
#define PLLCR_DIV 10
|
||||
|
||||
// äëÿ âûâîäà
|
||||
#define CONTROLLER_BIAS 3.2
|
||||
#define CONTROLLER_GAIN 2500.
|
||||
|
||||
// îáùåå êîëè÷åñòâî ïàðàìåòðîâ
|
||||
#define PAR_NUMBER 400
|
||||
// íîìåð ïåðâîãî ðåäàêòèðóåìîãî ïàðàìåòðà
|
||||
#define FIRST_WRITE_PAR_NUM 150
|
||||
|
||||
|
||||
|
||||
// Äèñêðåòíûå âõîäû/âûõîäû (begin)
|
||||
//-------------------------------------------------------------------------
|
||||
// âõîäû
|
||||
// ----------------------------
|
||||
#define DI_24V_SOURCE_FAULT GpioDataRegs.GPBDAT.bit.GPIO50
|
||||
|
||||
// âûõîäû
|
||||
// ----------------------------
|
||||
// ... ðàçíîå
|
||||
#define DO_GPIO00_SET GpioDataRegs.GPASET.bit.GPIO0 = 1
|
||||
#define DO_GPIO00_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO0 = 1
|
||||
#define DO_GPIO01_SET GpioDataRegs.GPASET.bit.GPIO1 = 1
|
||||
#define DO_GPIO01_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO1 = 1
|
||||
#define DO_GPIO02_SET GpioDataRegs.GPASET.bit.GPIO2 = 1
|
||||
#define DO_GPIO02_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO2 = 1
|
||||
#define DO_GPIO03_SET GpioDataRegs.GPASET.bit.GPIO3 = 1
|
||||
#define DO_GPIO03_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO3 = 1
|
||||
#define DO_GPIO04_SET GpioDataRegs.GPASET.bit.GPIO4 = 1
|
||||
#define DO_GPIO04_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO4 = 1
|
||||
#define DO_GPIO05_SET GpioDataRegs.GPASET.bit.GPIO5 = 1
|
||||
#define DO_GPIO05_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO5 = 1
|
||||
#define DO_GPIO06_SET GpioDataRegs.GPASET.bit.GPIO6 = 1
|
||||
#define DO_GPIO06_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO6 = 1
|
||||
#define DO_GPIO07_SET GpioDataRegs.GPASET.bit.GPIO7 = 1
|
||||
#define DO_GPIO07_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO7 = 1
|
||||
#define DO_GPIO08_SET GpioDataRegs.GPASET.bit.GPIO8 = 1
|
||||
#define DO_GPIO08_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO8 = 1
|
||||
#define DO_GPIO09_SET GpioDataRegs.GPASET.bit.GPIO9 = 1
|
||||
#define DO_GPIO09_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO9 = 1
|
||||
#define DO_GPIO10_SET GpioDataRegs.GPASET.bit.GPIO10 = 1
|
||||
#define DO_GPIO10_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO10 = 1
|
||||
#define DO_GPIO11_SET GpioDataRegs.GPASET.bit.GPIO11 = 1
|
||||
#define DO_GPIO11_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO11 = 1
|
||||
// ... íå èñïîëüçóþòñÿ
|
||||
#define DO_GPIO019_SET GpioDataRegs.GPASET.bit.GPIO19 = 1
|
||||
#define DO_GPIO019_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO19 = 1
|
||||
#define DO_GPIO020_SET GpioDataRegs.GPASET.bit.GPIO20 = 1
|
||||
#define DO_GPIO020_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO20 = 1
|
||||
#define DO_GPIO022_SET GpioDataRegs.GPASET.bit.GPIO22 = 1
|
||||
#define DO_GPIO022_CLEAR GpioDataRegs.GPACLEAR.bit.GPIO22 = 1
|
||||
#define DO_GPIO48_SET GpioDataRegs.GPBSET.bit.GPIO48 = 1
|
||||
#define DO_GPIO48_CLEAR GpioDataRegs.GPBCLEAR.bit.GPIO48 = 1
|
||||
#define DO_GPIO49_SET GpioDataRegs.GPBSET.bit.GPIO49 = 1
|
||||
#define DO_GPIO49_CLEAR GpioDataRegs.GPBCLEAR.bit.GPIO49 = 1
|
||||
// ... äëÿ óïðàâëåíèÿ íîæêîé CS EEPROM
|
||||
#define CS_SET GpioDataRegs.GPBSET.bit.GPIO57 = 1
|
||||
#define CS_CLEAR GpioDataRegs.GPBCLEAR.bit.GPIO57 = 1
|
||||
// ... ñâåòîäèîäû
|
||||
// (çåë¸íûé "Ãîòîâíîñòü")
|
||||
#define LED_GREEN1_ON GpioDataRegs.GPBCLEAR.bit.GPIO59 = 1
|
||||
#define LED_GREEN1_OFF GpioDataRegs.GPBSET.bit.GPIO59 = 1
|
||||
#define LED_GREEN1_TOGGLE GpioDataRegs.GPBTOGGLE.bit.GPIO59 = 1
|
||||
// (çåë¸íûé "Ðàáîòà")
|
||||
#define LED_GREEN2_ON GpioDataRegs.GPBCLEAR.bit.GPIO60 = 1
|
||||
#define LED_GREEN2_OFF GpioDataRegs.GPBSET.bit.GPIO60 = 1
|
||||
#define LED_GREEN2_TOGGLE GpioDataRegs.GPBTOGGLE.bit.GPIO60 = 1
|
||||
// (êðàñíûé "Àâàðèÿ")
|
||||
#define LED_RED_ON GpioDataRegs.GPBCLEAR.bit.GPIO61 = 1
|
||||
#define LED_RED_OFF GpioDataRegs.GPBSET.bit.GPIO61 = 1
|
||||
#define LED_RED_TOGGLE GpioDataRegs.GPBTOGGLE.bit.GPIO61 = 1
|
||||
// ... íå èñïîëüçóåòñÿ
|
||||
#define DO_GPIO63_SET GpioDataRegs.GPBSET.bit.GPIO63 = 1
|
||||
#define DO_GPIO63_CLEAR GpioDataRegs.GPBCLEAR.bit.GPIO63 = 1
|
||||
//-------------------------------------------------------------------------
|
||||
// Äèñêðåòíûå âõîäû/âûõîäû (end)
|
||||
|
||||
|
||||
#include "DSP2833x_Device.h"
|
||||
#include "math.h"
|
||||
#include "C28x_FPU_FastRTS.h"
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ ðåãóëÿòîðîâ òîêà (ñì. control_current())
|
||||
struct Cc {
|
||||
short once;
|
||||
float KpOrig;
|
||||
float KiOrig;
|
||||
float Kp;
|
||||
float Ki;
|
||||
float K1;
|
||||
float K2;
|
||||
float K3;
|
||||
float Xyff;
|
||||
float yffAux2;
|
||||
float yffAux3;
|
||||
float del;
|
||||
float kYlim;
|
||||
float yd1P;
|
||||
float yd1I;
|
||||
float yd1FF;
|
||||
float yd1;
|
||||
float yq1P;
|
||||
float yq1I;
|
||||
float yq1FF;
|
||||
float yq1;
|
||||
float y1;
|
||||
float yd2P;
|
||||
float yd2I;
|
||||
float yd2FF;
|
||||
float yd2;
|
||||
float yq2P;
|
||||
float yq2I;
|
||||
float yq2FF;
|
||||
float yq2;
|
||||
float y2;
|
||||
short y1LimFlag;
|
||||
short y2LimFlag;
|
||||
}; //Cc
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ ðåãóëÿòîðà ïîòîêà (ñì. control_flux())
|
||||
struct Cf {
|
||||
short once;
|
||||
float KpOrig;
|
||||
float KiOrig;
|
||||
float Kp;
|
||||
float Ki;
|
||||
float IdLim;
|
||||
float IdLimNeg;
|
||||
float del;
|
||||
float idP;
|
||||
float idI;
|
||||
float idFF;
|
||||
short idLimFlag;
|
||||
}; //Cf
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ ðåãóëÿòîðîâ ñêîðîñòè è ìîùíîñòè (ñì. control_speed_power())
|
||||
struct Csp {
|
||||
short once;
|
||||
float KpOrig;
|
||||
float KiOrig;
|
||||
float Kp;
|
||||
float Ki;
|
||||
float kMeNom;
|
||||
float del;
|
||||
float iqP;
|
||||
float iqI;
|
||||
float iqFF;
|
||||
float IlimIncr;
|
||||
float iqLimAux;
|
||||
float iqLimZi;
|
||||
float IqLim;
|
||||
float IqLimNeg;
|
||||
float iqLim;
|
||||
float iqLimNeg;
|
||||
float delWmAbs;
|
||||
float KizIncr;
|
||||
float pmZiRampDown;
|
||||
float wmLimZi;
|
||||
float pmLimZi;
|
||||
short iqLimFlag;
|
||||
}; //Csp
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ çàïèñè â EEPROM âñÿêîãî
|
||||
struct Eprom {
|
||||
short writeRequestNumber;
|
||||
short readFaultNo;
|
||||
}; //Eprom
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ çàïîìèíàíèÿ âåëè÷èí â ìîìåíò ñðàáàòûâàíèÿ çàùèòû
|
||||
struct Emerg {
|
||||
float udc1;
|
||||
float udc2;
|
||||
float iac1;
|
||||
float iac2;
|
||||
float me;
|
||||
float wm;
|
||||
float pm;
|
||||
}; //Emerg
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ inverse park (ñì. ipark())
|
||||
struct Ip {
|
||||
float yx1Aux;
|
||||
float yy1Aux;
|
||||
float yx2Aux;
|
||||
float yy2Aux;
|
||||
float theta;
|
||||
float sinTheta;
|
||||
float cosTheta;
|
||||
float yx1;
|
||||
float yy1;
|
||||
float yx2;
|
||||
float yy2;
|
||||
}; //Ip
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ indirect vector control (ñì. indirect_vector_control())
|
||||
struct Ivc {
|
||||
short once;
|
||||
float im;
|
||||
float wr;
|
||||
float wsNf;
|
||||
float ws;
|
||||
float sinTheta;
|
||||
float cosTheta;
|
||||
float id1;
|
||||
float iq1;
|
||||
float psi;
|
||||
float id2;
|
||||
float iq2;
|
||||
}; //Ivc
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ äàííûõ, ïîëó÷åííûõ ñ ÂÓ
|
||||
struct Mst {
|
||||
short pzMode;
|
||||
short faultReset;
|
||||
short start;
|
||||
float wmZz;
|
||||
float pmZz;
|
||||
float wmLim;
|
||||
float pmLim;
|
||||
float pIncrMaxTy;
|
||||
float pDecrMaxTy;
|
||||
}; //Mst
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ ñìåùåíèé íóëÿ äàò÷èêîâ
|
||||
struct Offset {
|
||||
short Udc1;
|
||||
short Udc2;
|
||||
short Ic1;
|
||||
short Ic2;
|
||||
short Ia1;
|
||||
short Ia2;
|
||||
short Ib1;
|
||||
short Ib2;
|
||||
}; //Offset
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ âûâîäà
|
||||
struct Out {
|
||||
float K;
|
||||
float udc1;
|
||||
float udc2;
|
||||
float iac1;
|
||||
float iac2;
|
||||
float me;
|
||||
float wm;
|
||||
float pm;
|
||||
}; //Out
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ çàùèò
|
||||
struct Protect {
|
||||
short IacMax;
|
||||
short IacMin;
|
||||
unsigned short Tdi24VSource;
|
||||
volatile unsigned short tDI24VSource;
|
||||
unsigned short TudcMin;
|
||||
volatile unsigned short tUdc1Min;
|
||||
volatile unsigned short tUdc2Min;
|
||||
unsigned short TwmMax;
|
||||
volatile unsigned short tWmMax;
|
||||
float UdcMin;
|
||||
float UdcMax;
|
||||
float WmMax;
|
||||
}; //Protect
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ ðåçóëüòàòîâ ÀÖÏ
|
||||
struct Result {
|
||||
short udc1;
|
||||
short udc2;
|
||||
short ic1;
|
||||
short ic2;
|
||||
short ia1;
|
||||
short ia2;
|
||||
short ib1;
|
||||
short ib2;
|
||||
}; //Result
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ çàäàííîãî ïîòîêà (ñì. reference_flux())
|
||||
struct Rf {
|
||||
short once;
|
||||
float PsiZ;
|
||||
float PsizIncr;
|
||||
float psiZi;
|
||||
float psiZCorr;
|
||||
float psiSub;
|
||||
float psiZCorr2;
|
||||
float psiZ;
|
||||
float KpsiSub;
|
||||
float Kpsiz;
|
||||
float WmNomPsi;
|
||||
float YlimPsi;
|
||||
float pPsiZ;
|
||||
float psiZPrev1;
|
||||
float psiZPrev2;
|
||||
float psiZPrev3;
|
||||
}; //Rf
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ çàäàííîé ìîùíîñòè (ñì. reference_power())
|
||||
struct Rp {
|
||||
short once;
|
||||
float pmZz;
|
||||
float pmZi;
|
||||
float pmZ;
|
||||
float Kpmz;
|
||||
float PlimIncr;
|
||||
float KpIncrDecr;
|
||||
volatile float pmEqv;
|
||||
}; //Rp
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ çàäàííîé ñêîðîñòè (ñì. reference_speed())
|
||||
struct Rs {
|
||||
short once;
|
||||
float wmZz;
|
||||
float wmZi;
|
||||
float wmZ;
|
||||
float Kwmz;
|
||||
float WlimIncr;
|
||||
float wzIncrNf;
|
||||
float wzIncr;
|
||||
float pWmZ;
|
||||
float wmZPrev1;
|
||||
float wmZPrev2;
|
||||
float wmZPrev3;
|
||||
short tPwmZ;
|
||||
}; //Rs
|
||||
|
||||
|
||||
// ñòðóêòóðà äëÿ ïàðàìåòðîâ ÃÝÄ
|
||||
struct SgmPar {
|
||||
float Rs;
|
||||
float Lls;
|
||||
float Rr;
|
||||
float Llr;
|
||||
float Lm;
|
||||
float Ls;
|
||||
float Lr;
|
||||
float SigmaLs;
|
||||
float LmInv;
|
||||
float LrInv;
|
||||
float Tr;
|
||||
float TrInv;
|
||||
float Kl;
|
||||
float KlInv;
|
||||
}; //SgmPar
|
||||
|
||||
#endif //DEF
|
||||
241
Inu_im_1wnd_3lvl/Inu/detcoeff.c
Normal file
241
Inu_im_1wnd_3lvl/Inu/detcoeff.c
Normal file
@@ -0,0 +1,241 @@
|
||||
/**************************************************************************
|
||||
Description: Ôóíêöèÿ âûçûâàåòñÿ îäèí ðàç â íà÷àëå âûïîëíåíèÿ
|
||||
ïðîãðàììû è ïîäãîòàâëèâàåò äàííûå íåîáõîäèìûå äëÿ å¸ ðàáîòû.
|
||||
|
||||
Àâòîð: Óëèòîâñêèé Ä.È.
|
||||
Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.11.08
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
#include "def.h"
|
||||
#include "detcoeff.h"
|
||||
|
||||
|
||||
void process_sgm_parameters(void);
|
||||
short read_eeprom(void);
|
||||
short test_param(void);
|
||||
|
||||
|
||||
void detcoeff(void) {
|
||||
float Tci;
|
||||
float Tcf;
|
||||
float Tcs;
|
||||
float Km;
|
||||
|
||||
// äëÿ ñèãíàëèçàöèè
|
||||
testParamFaultNo = 0;
|
||||
|
||||
// ÷òåíèå EEPROM
|
||||
// ( -> param[])
|
||||
eprom.readFaultNo = read_eeprom();
|
||||
if ( eprom.readFaultNo != 0 ) {
|
||||
faultNo = 1;
|
||||
state = STATE_SHUTDOWN;
|
||||
}
|
||||
else {
|
||||
// ïðîâåðÿåì ìàññèâ param[]
|
||||
testParamFaultNo = test_param();
|
||||
if ( testParamFaultNo != 0 ) {
|
||||
faultNo = 4;
|
||||
state = STATE_SHUTDOWN;
|
||||
}
|
||||
else {
|
||||
faultNo = 0;
|
||||
state = STATE_STOP;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
rf.PsiZ = (float)param[180]*0.001;//%*10 -> o.e.
|
||||
|
||||
// ñìåùåíèÿ íóëÿ äàò÷èêîâ, åä. ÀÖÏ
|
||||
offset.Ia1 = param[200];
|
||||
offset.Ib1 = param[201];
|
||||
offset.Ic1 = param[202];
|
||||
offset.Udc1 = param[203];
|
||||
offset.Ia2 = param[206];
|
||||
offset.Ib2 = param[207];
|
||||
offset.Ic2 = param[208];
|
||||
offset.Udc2 = param[209];
|
||||
|
||||
// ïàðàìåòðû ÀÄ
|
||||
sgmPar.Rs = (float)param[303]*1e-6;//ìêÎì -> Îì
|
||||
sgmPar.Lls = (float)param[304]*1e-7;//ìêÃí*10 -> Ãí
|
||||
sgmPar.Rr = (float)param[305]*1e-6;//ìêÎì -> Îì
|
||||
sgmPar.Llr = (float)param[306]*1e-7;//ìêÃí*10 -> Ãí
|
||||
sgmPar.Lm = (float)param[307]*1e-6;//ìêÃí -> Ãí
|
||||
// ïîëó÷àåì èç ïàðàìåòðîâ ÀÄ âñÿêèå âñïîìîãàòåëüíûå âåëè÷èíû
|
||||
process_sgm_parameters();
|
||||
|
||||
// êîýôôèöèåíòû ðåãóëÿòîðîâ Id è Iq
|
||||
// ... ïîñòîÿííàÿ âðåìåíè êîíòóðà òîêà, ñ
|
||||
Tci = TY*3.8;
|
||||
cc.KpOrig = 0.01*sgmPar.SigmaLs/Tci*I_BAZ*U_2_Y;
|
||||
cc.Kp = cc.KpOrig*(float)param[210];
|
||||
cc.KiOrig = 0.01*(sgmPar.Rs + sgmPar.Rr*sgmPar.Kl*sgmPar.Kl)/Tci*I_BAZ*U_2_Y*TY;
|
||||
cc.Ki = cc.KiOrig*(float)param[211];
|
||||
|
||||
// êîýôôèöèåíòû ðåãóëÿòîðà Psi
|
||||
// ... ïîñòîÿííàÿ âðåìåíè êîíòóðà ïîòîêà, ñ
|
||||
Tcf = 50e-3;
|
||||
cf.KpOrig = 0.01*sgmPar.KlInv/(sgmPar.Rr*Tcf)*PSI_BAZ/I_BAZ;
|
||||
cf.Kp = cf.KpOrig*(float)param[212];
|
||||
cf.KiOrig = 0.01/(sgmPar.Lm*Tcf)*PSI_BAZ/I_BAZ*TY*DECIM_PSI_WM_PM;
|
||||
cf.Ki = cf.KiOrig*(float)param[213];
|
||||
|
||||
// êîýôôèöèåíòû ðåãóëÿòîðà N
|
||||
// ... ïîñòîÿííàÿ âðåìåíè êîíòóðà ñêîðîñòè, ñ
|
||||
Tcs = 200e-3;
|
||||
// ... êîýôôèöèåíò äëÿ ïåðåñ÷¸òà òîêà â ìîìåíò
|
||||
Km = 1.5*PP*sgmPar.Kl*PSI_BAZ*rf.PsiZ;
|
||||
csp.KpOrig = 0.01*J/(Km*Tcs)*WM_BAZ/I_BAZ;
|
||||
csp.Kp = csp.KpOrig*(float)param[214];
|
||||
csp.KiOrig = 0.01*J/(Km*Tcs*Tcs*5.)*WM_BAZ/I_BAZ*TY*DECIM_PSI_WM_PM;
|
||||
csp.Ki = csp.KiOrig*(float)param[215];
|
||||
|
||||
// âñÿêèå óñòàâêè
|
||||
protect.IacMax = (short)(2047.*(float)param[220]*0.01);//% -> åä. ÀÖÏ
|
||||
protect.IacMin = -protect.IacMax;
|
||||
protect.UdcMax = (float)param[221]*0.01;//% -> o.e.
|
||||
IzLim = (float)param[222]*0.01;//% -> o.e.
|
||||
cf.IdLim = (float)param[223]*0.01;//% -> o.e.
|
||||
cf.IdLimNeg = cf.IdLim*(-0.4);
|
||||
csp.IqLim = (float)param[224]*0.01;//% -> o.e.
|
||||
csp.IqLimNeg = -csp.IqLim;
|
||||
protect.UdcMin = (float)param[225]*0.01;//% -> o.e.
|
||||
protect.WmMax = (float)param[226]*0.01;//% -> o.e.
|
||||
rf.WmNomPsi = (float)param[228]*0.01;//% -> o.e.
|
||||
rf.YlimPsi = (float)param[229]*0.01*Y_LIM;//% -> åä. ñ÷¸ò÷èêà òàéìåðà
|
||||
protect.TudcMin = (unsigned short)((float)param[231]*0.001/TY);
|
||||
protect.TwmMax = (unsigned short)((float)param[233]*0.001/TY);
|
||||
|
||||
// äëÿ ðàçíûõ ÇÈ
|
||||
rs.WlimIncr = 1.0*TY*DECIM_PSI_WM_PM/((float)param[244]*0.001);
|
||||
csp.IlimIncr = 1.0*TY*DECIM_PSI_WM_PM/((float)param[245]*0.001);
|
||||
rp.PlimIncr = 1.0*TY*DECIM_PSI_WM_PM/((float)param[248]*0.001);
|
||||
rf.PsizIncr = 1.0*TY*DECIM_PSI_WM_PM/2.0;
|
||||
|
||||
// äëÿ êîððåêöèè
|
||||
KmeCorr = (float)param[269]*0.0001;//%*100 -> o.e.
|
||||
|
||||
// äëÿ ðàçíûõ ôèëüòðîâ
|
||||
Kudc = (TY*10000.)/(float)param[285];
|
||||
if ( Kudc > 1.0 )
|
||||
Kudc = 1.0;
|
||||
Kwm = (TY*10000.)/(float)param[286];
|
||||
if ( Kwm > 1.0 )
|
||||
Kwm = 1.0;
|
||||
rs.Kwmz = (TY*DECIM_PSI_WM_PM*1000.)/(float)param[288];
|
||||
rf.Kpsiz = (TY*DECIM_PSI_WM_PM*1000.)/(float)param[289];
|
||||
Kme = (TY*1000.)/(float)param[290];
|
||||
rp.Kpmz = (TY*DECIM_PSI_WM_PM*1000.)/(float)param[292];
|
||||
out.K = TY/100e-3;
|
||||
|
||||
// âûäåðæêè
|
||||
protect.Tdi24VSource = (unsigned short)(5.0/TY);
|
||||
|
||||
// âñ¸ â èñõîäíîå ïîëîæåíèå
|
||||
udc1 = 0;
|
||||
udc2 = 0;
|
||||
wmNf = 0;
|
||||
wm = 0;
|
||||
me = 0;
|
||||
out.udc1 = 0;
|
||||
out.udc2 = 0;
|
||||
out.iac1 = 0;
|
||||
out.iac2 = 0;
|
||||
out.wm = 0;
|
||||
out.me = 0;
|
||||
out.pm = 0;
|
||||
protect.tWmMax = 0;
|
||||
protect.tDI24VSource = 0;
|
||||
onceShutdown = 0;
|
||||
onceFaultReset = 0;
|
||||
stopPause = 1;
|
||||
mst.pzMode = 0;
|
||||
mst.faultReset = 0;
|
||||
mst.start = 0;
|
||||
mst.wmZz = 0;
|
||||
mst.pmZz = 0;
|
||||
mst.wmLim = 0;
|
||||
mst.pmLim = 0;
|
||||
mst.pIncrMaxTy = 0;
|
||||
mst.pDecrMaxTy = 0;
|
||||
} //void detcoeff(void)
|
||||
|
||||
|
||||
|
||||
// Âû÷èñëÿåò èç ïàðàìåòðîâ ÀÄ âñÿêèå âñïîìîãàòåëüíûå âåëè÷èíû
|
||||
void process_sgm_parameters(void) {
|
||||
// ïîëíàÿ èíäóêòèâíîñòü ôàçû ñòàòîðà, Ãí
|
||||
sgmPar.Ls = sgmPar.Lm + sgmPar.Lls;
|
||||
// ïîëíàÿ èíäóêòèâíîñòü ôàçû ðîòîðà, Ãí
|
||||
sgmPar.Lr = sgmPar.Lm + sgmPar.Llr;
|
||||
// âñÿêî-ðàçíî
|
||||
sgmPar.SigmaLs = (1. - sgmPar.Lm*sgmPar.Lm/(sgmPar.Ls*sgmPar.Lr))*sgmPar.Ls;
|
||||
sgmPar.LmInv = 1.0/sgmPar.Lm;
|
||||
sgmPar.LrInv = 1.0/sgmPar.Lr;
|
||||
sgmPar.Kl = sgmPar.Lm*sgmPar.LrInv;
|
||||
sgmPar.KlInv = 1.0/sgmPar.Kl;
|
||||
sgmPar.Tr = sgmPar.Lr/sgmPar.Rr;
|
||||
sgmPar.TrInv = sgmPar.Rr*sgmPar.LrInv;
|
||||
} //void process_sgm_parameters(void)
|
||||
|
||||
|
||||
|
||||
// ×èòàåò PAR_NUMBER ïàðàìåòðîâ èç EEPROM è ñîõðàíÿåò â ìàññèâå param[]
|
||||
// ( -> param[])
|
||||
short read_eeprom(void) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// Ïðîâåðÿåò äîïóñòèìîñòü çíà÷åíèé ïàðàìåòðîâ, ïîëó÷åííûõ èç EEPROM
|
||||
// (â param.c ó ïàðàìåòðîâ ä.á. òå æå ãðàíèöû äîïóñòèìûõ çíà÷åíèé!)
|
||||
short test_param(void) {
|
||||
if ( param[180] > 2000 ) return 180;//rf.PsiZ
|
||||
|
||||
if ( (param[200]<1748) || (param[200]>2348) ) return 200;//offset.Ia1
|
||||
if ( (param[201]<1748) || (param[201]>2348) ) return 201;//offset.Ib1
|
||||
if ( (param[202]<1748) || (param[202]>2348) ) return 202;//offset.Ic1
|
||||
if ( (param[203]<1748) || (param[203]>2348) ) return 203;//offset.Udc1
|
||||
if ( (param[206]<1748) || (param[206]>2348) ) return 206;//offset.Ia2
|
||||
if ( (param[207]<1748) || (param[207]>2348) ) return 207;//offset.Ib2
|
||||
if ( (param[208]<1748) || (param[208]>2348) ) return 208;//offset.Ic2
|
||||
if ( (param[209]<1748) || (param[209]>2348) ) return 209;//offset.Udc2
|
||||
|
||||
if ( param[210] > 5000 ) return 210;//cc.Kp
|
||||
if ( param[211] > 5000 ) return 211;//cc.Ki
|
||||
if ( param[212] > 5000 ) return 212;//cf.Kp
|
||||
if ( param[213] > 5000 ) return 213;//cf.Ki
|
||||
if ( param[214] > 5000 ) return 214;//csp.Kp
|
||||
if ( param[215] > 5000 ) return 215;//csp.Ki
|
||||
|
||||
if ( param[220] > 99 ) return 220;//protect.IacMax
|
||||
if ( param[221] > 136 ) return 221;//protect.UdcMax
|
||||
if ( param[222] > 200 ) return 222;//IzLim
|
||||
if ( param[223] > 200 ) return 223;//cf.IdLim
|
||||
if ( param[224] > 200 ) return 224;//csp.IqLim
|
||||
if ( param[225] > 110 ) return 225;//protect.UdcMin
|
||||
if ( param[226] > 200 ) return 226;//protect.WmMax
|
||||
if ( param[228] > 200 ) return 228;//rf.WmNomPsi
|
||||
if ( param[229] > 101 ) return 229;//rf.YlimPsi
|
||||
if ( (param[231]<1) || (param[231]>8500) ) return 231;//protect.TudcMin
|
||||
if ( (param[233]<1) || (param[233]>8500) ) return 233;//protect.TwmMax
|
||||
|
||||
if ( param[244] < 1 ) return 244;//rs.WlimIncr
|
||||
if ( param[245] < 1 ) return 245;//csp.IlimIncr
|
||||
if ( param[248] < 1 ) return 248;//rp.PlimIncr
|
||||
|
||||
if ( (param[269]<5000) || (param[269]>20000) ) return 269;//KmeCorr
|
||||
|
||||
if ( (param[285]<1) || (param[285]>20000) ) return 285;//Kudc
|
||||
if ( (param[286]<1) || (param[286]>20000) ) return 286;//Kwm
|
||||
if ( (param[288]<1) || (param[288]>20000) ) return 288;//rs.Kwmz
|
||||
if ( (param[289]<1) || (param[289]>20000) ) return 289;//rf.Kpsiz
|
||||
if ( (param[290]<1) || (param[290]>20000) ) return 290;//Kme
|
||||
if ( (param[292]<1) || (param[292]>20000) ) return 292;//rp.Kpmz
|
||||
|
||||
return 0;
|
||||
} //short test_param(void)
|
||||
47
Inu_im_1wnd_3lvl/Inu/detcoeff.h
Normal file
47
Inu_im_1wnd_3lvl/Inu/detcoeff.h
Normal file
@@ -0,0 +1,47 @@
|
||||
#ifndef DETCOEFF
|
||||
#define DETCOEFF
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â detcoeff.c (begin)
|
||||
//#########################################################################
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â detcoeff.c (end)
|
||||
|
||||
|
||||
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â detcoeff.c (begin)
|
||||
//#########################################################################
|
||||
extern short testParamFaultNo;
|
||||
extern struct Eprom eprom;
|
||||
extern volatile short faultNo;
|
||||
extern volatile short state;
|
||||
extern unsigned short param[];
|
||||
|
||||
extern struct Rf rf;
|
||||
extern struct Offset offset;
|
||||
extern struct SgmPar sgmPar;
|
||||
extern struct Cc cc;
|
||||
extern struct Cf cf;
|
||||
extern struct Csp csp;
|
||||
extern float IzLim;
|
||||
extern struct Protect protect;
|
||||
extern struct Rs rs;
|
||||
extern struct Rp rp;
|
||||
extern float KmeCorr;
|
||||
extern float Kudc;
|
||||
extern float Kwm;
|
||||
extern float Kme;
|
||||
|
||||
extern volatile struct Out out;
|
||||
extern volatile float udc1;
|
||||
extern volatile float udc2;
|
||||
extern volatile float wmNf;
|
||||
extern volatile float wm;
|
||||
extern volatile float me;
|
||||
extern short onceShutdown;
|
||||
extern short onceFaultReset;
|
||||
extern short stopPause;
|
||||
extern struct Mst mst;
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â detcoeff.c (end)
|
||||
#endif //DETCOEFF
|
||||
581
Inu_im_1wnd_3lvl/Inu/estimate.c
Normal file
581
Inu_im_1wnd_3lvl/Inu/estimate.c
Normal file
@@ -0,0 +1,581 @@
|
||||
/*
|
||||
* Файл: estimate.c
|
||||
* Модуль идентификации параметров асинхронного двигателя
|
||||
*/
|
||||
|
||||
#include "estimate.h"
|
||||
#include "def.h"
|
||||
#include <math.h>
|
||||
#include <string.h>
|
||||
|
||||
#ifndef M_PI
|
||||
#define M_PI 3.14159265358979323846f
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Настройки эксперимента по определению активного сопротивления статора Rs
|
||||
* Метод: разностный метод с двумя уровнями постоянного тока
|
||||
*/
|
||||
float RS_IREF1 = 0.1f; /* первый уровень тока, А */
|
||||
float RS_IREF2 = 0.2f; /* второй уровень тока, А */
|
||||
float RS_SETTLE_TIME = 0.5f; /* время установления тока, с */
|
||||
float RS_THRESHOLD = 0.98f; /* относительный порог достижения тока */
|
||||
|
||||
/*
|
||||
* Настройки эксперимента по определению сопротивления ротора Rr
|
||||
* и индуктивностей рассеяния Llr, Lls
|
||||
* Метод: подача переменного тока по оси q, RMS измерения
|
||||
*/
|
||||
float RRL_IQ_AMP = 0.2f; /* амплитуда тока, А */
|
||||
float RRL_RAMP_TIME = 2.0f; /* время нарастания амплитуды, с */
|
||||
float RRL_FREQ = 1.0f; /* частота тестового сигнала, Гц (дефолт) */
|
||||
int RRL_SAMPLES = 200; /* количество выборок для RMS */
|
||||
int RRL_AVG = 10; /* количество усреднений на частоте */
|
||||
|
||||
/* Частоты для многоточечной идентификации (Гц) */
|
||||
#define RRL_FREQ_COUNT 5
|
||||
static const float RRL_FREQS[RRL_FREQ_COUNT] = { 1.0f, 2.0f, 3.0f, 5.0f, 10.0f };
|
||||
|
||||
/*
|
||||
* Настройки эксперимента по определению взаимной индуктивности Lm
|
||||
* Метод: подача постоянного тока по оси d, интегрирование ЭДС на фронте
|
||||
*/
|
||||
float LM_IDREF = 0.3f; /* заданный постоянный ток, о.е. */
|
||||
float LM_SETTLE_THRESHOLD = 0.95f; /* порог окончания переходного процесса */
|
||||
float LM_SETTLE_TIME = 0.5f; /* выдержка для усреднения Id, с */
|
||||
float LM_DEMAG_TIME = 0.3f; /* размагничивание между циклами, с */
|
||||
int LM_AVG = 5; /* количество измерений для усреднения */
|
||||
|
||||
/*
|
||||
* Настройки переключения между экспериментами
|
||||
*/
|
||||
float STEP_PAUSE_TIME = 0.5f;
|
||||
|
||||
/* Текущий шаг идентификации */
|
||||
static Estimate_Test_t test_step = ESTIMATE_TEST_IDLE;
|
||||
|
||||
/* Структура с вычисленными параметрами двигателя */
|
||||
static Params_t params = { 0 };
|
||||
|
||||
/* ============================================
|
||||
*
|
||||
* ============================================ */
|
||||
static RsState_t rs_state = {0};
|
||||
static RrlState_t rrl_state = {0};
|
||||
static LmState_t lm_state = {0};
|
||||
static int in_pause;
|
||||
static float pause_timer;
|
||||
|
||||
/* ============================================
|
||||
*
|
||||
* ============================================ */
|
||||
|
||||
/*
|
||||
* Vd/Vq
|
||||
* : v - ( )
|
||||
* :
|
||||
*/
|
||||
static inline float vdq_to_volts(float vq) {
|
||||
float vq_oe = vq / T1_PRD;
|
||||
float dt_oe = DT / T_PWM;
|
||||
if (vq_oe > dt_oe) vq_oe -= dt_oe;
|
||||
else if (vq_oe < -dt_oe) vq_oe += dt_oe;
|
||||
return vq_oe * U_BAZ / SQRT3;
|
||||
}
|
||||
|
||||
/*
|
||||
* Iq
|
||||
* : iq -
|
||||
* :
|
||||
*/
|
||||
static inline float idq_to_amps(float iq) {
|
||||
return iq * I_BAZ;
|
||||
}
|
||||
|
||||
/* ============================================
|
||||
*
|
||||
* ============================================ */
|
||||
|
||||
/*
|
||||
*
|
||||
*
|
||||
*/
|
||||
void estimate_init(void) {
|
||||
params.Rs = 0.0192f;
|
||||
params.Rr = 0.0085f;
|
||||
params.Lls = 0.0019364f;
|
||||
params.Llr = 0.0019364f;
|
||||
params.Lk = params.Llr + params.Lls;
|
||||
params.Zk = 0;
|
||||
params.Rk = params.Rs+ params.Rr;
|
||||
params.Xk = 0;
|
||||
params.Lm = 0;
|
||||
|
||||
memset(&rs_state, 0, sizeof(RsState_t));
|
||||
memset(&rrl_state, 0, sizeof(RrlState_t));
|
||||
memset(&lm_state, 0, sizeof(LmState_t));
|
||||
in_pause = 0;
|
||||
pause_timer = 0;
|
||||
}
|
||||
|
||||
void estimate_reset(void) {
|
||||
memset(&rs_state, 0, sizeof(RsState_t));
|
||||
memset(&rrl_state, 0, sizeof(RrlState_t));
|
||||
memset(&lm_state, 0, sizeof(LmState_t));
|
||||
test_step = ESTIMATE_TEST_IDLE;
|
||||
}
|
||||
|
||||
void estimate_start(Estimate_Test_t start_test) {
|
||||
estimate_reset();
|
||||
test_step = start_test;
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
*
|
||||
*/
|
||||
Estimate_Test_t estimate_get_step(void) {
|
||||
return test_step;
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
* params
|
||||
*/
|
||||
Params_t* estimate_get_params(void) {
|
||||
return ¶ms;
|
||||
}
|
||||
|
||||
/* ============================================
|
||||
*
|
||||
* ============================================ */
|
||||
|
||||
/*
|
||||
* : Rs
|
||||
*
|
||||
* :
|
||||
* step0: IREF1,
|
||||
* step1: , U1 I1
|
||||
* step2: IREF2,
|
||||
* step3: , U2 I2
|
||||
* step4: Rs = (U2-U1)/(I2-I1),
|
||||
*
|
||||
* :
|
||||
* vq, iq - (. .)
|
||||
* dt -
|
||||
* iq_ref -
|
||||
* freq_ref - (0 )
|
||||
*/
|
||||
static void process_Rs(float vq, float iq, float dt, float* iq_ref, float* freq_ref) {
|
||||
if (freq_ref)
|
||||
*freq_ref = 0;
|
||||
|
||||
switch (rs_state.step) {
|
||||
case 0:
|
||||
*iq_ref = RS_IREF1;
|
||||
rs_state.sum_v = 0;
|
||||
rs_state.sum_i = 0;
|
||||
rs_state.sample_cnt = 0;
|
||||
if (fabsf(iq) >= RS_IREF1 * RS_THRESHOLD) {
|
||||
rs_state.step = 1;
|
||||
rs_state.timer = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
*iq_ref = RS_IREF1;
|
||||
rs_state.timer += dt;
|
||||
rs_state.sum_v += vdq_to_volts(vq);
|
||||
rs_state.sum_i += idq_to_amps(iq);
|
||||
rs_state.sample_cnt++;
|
||||
if (rs_state.timer >= RS_SETTLE_TIME) {
|
||||
if (rs_state.sample_cnt > 0) {
|
||||
rs_state.meas1 = rs_state.sum_v / rs_state.sample_cnt;
|
||||
rs_state.val1 = rs_state.sum_i / rs_state.sample_cnt;
|
||||
}
|
||||
rs_state.step = 2;
|
||||
}
|
||||
break;
|
||||
|
||||
case 2:
|
||||
*iq_ref = RS_IREF2;
|
||||
rs_state.sum_v = 0;
|
||||
rs_state.sum_i = 0;
|
||||
rs_state.sample_cnt = 0;
|
||||
if (fabsf(iq) >= RS_IREF2 * RS_THRESHOLD) {
|
||||
rs_state.step = 3;
|
||||
rs_state.timer = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 3:
|
||||
*iq_ref = RS_IREF2;
|
||||
rs_state.timer += dt;
|
||||
rs_state.sum_v += vdq_to_volts(vq);
|
||||
rs_state.sum_i += idq_to_amps(iq);
|
||||
rs_state.sample_cnt++;
|
||||
if (rs_state.timer >= RS_SETTLE_TIME) {
|
||||
if (rs_state.sample_cnt > 0) {
|
||||
rs_state.meas2 = rs_state.sum_v / rs_state.sample_cnt;
|
||||
rs_state.val2 = rs_state.sum_i / rs_state.sample_cnt;
|
||||
}
|
||||
rs_state.step = 4;
|
||||
}
|
||||
break;
|
||||
|
||||
case 4:
|
||||
*iq_ref = 0;
|
||||
if (fabsf(rs_state.val2 - rs_state.val1) > 0.001f) {
|
||||
params.Rs = (rs_state.meas2 - rs_state.meas1) / (rs_state.val2 - rs_state.val1);
|
||||
if (params.Rs < 0) params.Rs = 0;
|
||||
}
|
||||
rs_state.step = 5;
|
||||
rs_state.done = 1; /* */
|
||||
break;
|
||||
|
||||
default:
|
||||
*iq_ref = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* : Rr
|
||||
*
|
||||
* :
|
||||
* - 0 RRL_IQ_AMP RRL_RAMP_TIME
|
||||
* -
|
||||
* - RRL_SAMPLES , Vq^2, Iq^2
|
||||
* - RMS , Zk Rk
|
||||
* - Rr = Rk - Rs, Xk, Lk
|
||||
* - RRL_AVG
|
||||
*
|
||||
* :
|
||||
* vq, iq - (. .)
|
||||
* dt -
|
||||
* iq_ref -
|
||||
* freq_ref -
|
||||
*/
|
||||
static void process_RrL(float vq, float iq, float dt, float* iq_ref, float* freq_ref) {
|
||||
|
||||
float f = RRL_FREQS[(rrl_state.freq_idx < RRL_FREQ_COUNT) ? rrl_state.freq_idx : (RRL_FREQ_COUNT - 1)];
|
||||
|
||||
/* (0...1) */
|
||||
float amp_k = rrl_state.ramp_timer / RRL_RAMP_TIME;
|
||||
if (amp_k > 1.0f) amp_k = 1.0f;
|
||||
|
||||
/* */
|
||||
float current_amp = RRL_IQ_AMP * amp_k;
|
||||
|
||||
/* */
|
||||
*iq_ref = current_amp * sinf(2.0f * M_PI * f * rrl_state.timer);
|
||||
if (freq_ref) *freq_ref = f;
|
||||
rrl_state.timer += dt;
|
||||
rrl_state.ramp_timer += dt;
|
||||
|
||||
/* - */
|
||||
if (amp_k < 1.0f) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* , */
|
||||
float vq_oe = vq / T1_PRD;
|
||||
float dt_oe = DT / T_PWM;
|
||||
if (vq_oe > dt_oe) vq_oe -= dt_oe;
|
||||
else if (vq_oe < -dt_oe) vq_oe += dt_oe;
|
||||
|
||||
float vq_V = vdq_to_volts(vq);
|
||||
float iq_A = idq_to_amps(iq);
|
||||
|
||||
rrl_state.sum_p += vq_V * iq_A;
|
||||
rrl_state.sum_vq2 += vq_V * vq_V;
|
||||
rrl_state.sum_iq2 += iq_A * iq_A;
|
||||
rrl_state.sample_count++;
|
||||
|
||||
if (rrl_state.sample_count >= RRL_SAMPLES) {
|
||||
float P = rrl_state.sum_p / (float)RRL_SAMPLES;
|
||||
float Vq_rms = sqrtf(rrl_state.sum_vq2 / (float)RRL_SAMPLES);
|
||||
float Iq_rms = sqrtf(rrl_state.sum_iq2 / (float)RRL_SAMPLES);
|
||||
|
||||
if (Iq_rms > 0.001f) {
|
||||
float Zk = Vq_rms / Iq_rms;
|
||||
float Rk = P / (Iq_rms * Iq_rms);
|
||||
float Rr = Rk - params.Rs;
|
||||
if (Rr < 0) Rr = 0;
|
||||
float Xk = (Zk > Rk) ? sqrtf(Zk * Zk - Rk * Rk) / 2 : 0;
|
||||
float Lk = (f > 1e-6f) ? (Xk / (2.0f * M_PI * f)) : 0.0f;
|
||||
|
||||
(void)Rr;
|
||||
rrl_state.avg_Zk += Zk;
|
||||
rrl_state.avg_Xk += Xk;
|
||||
rrl_state.avg_Lk += Lk;
|
||||
rrl_state.avg_Rk += Rk;
|
||||
rrl_state.avg_count++;
|
||||
}
|
||||
|
||||
rrl_state.sum_p = 0;
|
||||
rrl_state.sum_vq2 = 0;
|
||||
rrl_state.sum_iq2 = 0;
|
||||
rrl_state.sample_count = 0;
|
||||
}
|
||||
|
||||
if (rrl_state.avg_count >= RRL_AVG) {
|
||||
/* */
|
||||
int k = rrl_state.freq_idx;
|
||||
if (k < RRL_FREQ_COUNT) {
|
||||
rrl_state.freq_Zk[k] = rrl_state.avg_Zk / (float)RRL_AVG;
|
||||
rrl_state.freq_Xk[k] = rrl_state.avg_Xk / (float)RRL_AVG;
|
||||
rrl_state.freq_Lk[k] = rrl_state.avg_Lk / (float)RRL_AVG;
|
||||
rrl_state.freq_Rk[k] = rrl_state.avg_Rk / (float)RRL_AVG;
|
||||
rrl_state.freq_ready = k + 1;
|
||||
}
|
||||
|
||||
/* */
|
||||
rrl_state.freq_idx++;
|
||||
rrl_state.timer = 0.0f;
|
||||
rrl_state.ramp_timer = 0.0f;
|
||||
rrl_state.sum_p = 0.0f;
|
||||
rrl_state.sum_vq2 = 0.0f;
|
||||
rrl_state.sum_iq2 = 0.0f;
|
||||
rrl_state.sample_count = 0;
|
||||
rrl_state.avg_Zk = 0.0f;
|
||||
rrl_state.avg_Xk = 0.0f;
|
||||
rrl_state.avg_Lk = 0.0f;
|
||||
rrl_state.avg_Rk = 0.0f;
|
||||
rrl_state.avg_count = 0;
|
||||
|
||||
/* 0 */
|
||||
if (rrl_state.freq_idx >= RRL_FREQ_COUNT) {
|
||||
float s1 = 0.0f, sf = 0.0f, sf2 = 0.0f;
|
||||
float sR = 0.0f, sfR = 0.0f;
|
||||
float sfX = 0.0f;
|
||||
int n = rrl_state.freq_ready;
|
||||
for (int i = 0; i < n; i++) {
|
||||
float fi = RRL_FREQS[i];
|
||||
float Ri = rrl_state.freq_Rk[i];
|
||||
float Xi = rrl_state.freq_Xk[i];
|
||||
s1 += 1.0f;
|
||||
sf += fi;
|
||||
sf2 += fi * fi;
|
||||
sR += Ri;
|
||||
sfR += fi * Ri;
|
||||
sfX += fi * Xi;
|
||||
}
|
||||
|
||||
/* Rk(f) = a + b f */
|
||||
float den = (s1 * sf2 - sf * sf);
|
||||
float aR = (fabsf(den) > 1e-9f) ? ((sR * sf2 - sf * sfR) / den) : (n > 0 ? (sR / (float)n) : 0.0f);
|
||||
|
||||
/* Xk(f) = c f ( 0) */
|
||||
float cX = (sf2 > 1e-9f) ? (sfX / sf2) : 0.0f;
|
||||
|
||||
params.Rk = aR;
|
||||
params.Xk = 0.0f; /* f=0 -> 0 */
|
||||
params.Zk = params.Rk;
|
||||
params.Lk = cX / (2.0f * M_PI);
|
||||
|
||||
params.Rr = params.Rk - params.Rs;
|
||||
if (params.Rr < 0.0f) params.Rr = 0.0f;
|
||||
params.Lls = params.Lk / 2.0f;
|
||||
params.Llr = params.Lk / 2.0f;
|
||||
|
||||
rrl_state.done = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* : Lm
|
||||
*
|
||||
* :
|
||||
* - Idref
|
||||
* - Ed = Vd - Rs*Id
|
||||
* - LM_SETTLE_THRESHOLD -
|
||||
* - Ls = integral(Ed*dt) / Id_steady
|
||||
* - Lm = Ls - Lls
|
||||
*
|
||||
* :
|
||||
* vd, id - (. .)
|
||||
* dt -
|
||||
* id_ref -
|
||||
* freq_ref -
|
||||
*/
|
||||
static void process_Lm(float vd, float id, float dt, float* id_ref, float* freq_ref) {
|
||||
float vd_abs = vdq_to_volts(vd);
|
||||
float id_abs = idq_to_amps(id);
|
||||
float ed = vd_abs - params.Rs * id_abs;
|
||||
float id_pu = fabsf(id);
|
||||
float id_thresh = LM_IDREF * LM_SETTLE_THRESHOLD;
|
||||
|
||||
if (freq_ref)
|
||||
*freq_ref = 0.0f;
|
||||
|
||||
switch (lm_state.step) {
|
||||
case 0:
|
||||
*id_ref = 0.0f;
|
||||
lm_state.timer += dt;
|
||||
if (lm_state.timer >= LM_DEMAG_TIME) {
|
||||
lm_state.timer = 0.0f;
|
||||
lm_state.integral_psi = 0.0f;
|
||||
lm_state.first_sample = 0;
|
||||
lm_state.prev_ed = ed;
|
||||
lm_state.step = 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case 1:
|
||||
*id_ref = LM_IDREF;
|
||||
if (!lm_state.first_sample) {
|
||||
lm_state.prev_ed = ed;
|
||||
lm_state.first_sample = 1;
|
||||
}
|
||||
else {
|
||||
lm_state.integral_psi += (ed + lm_state.prev_ed) * 0.5f * dt;
|
||||
lm_state.prev_ed = ed;
|
||||
}
|
||||
|
||||
if (id_pu >= id_thresh) {
|
||||
lm_state.step = 2;
|
||||
lm_state.timer = 0.0f;
|
||||
lm_state.sum_id = 0.0f;
|
||||
lm_state.sample_cnt = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case 2:
|
||||
*id_ref = LM_IDREF;
|
||||
lm_state.timer += dt;
|
||||
lm_state.sum_id += id_abs;
|
||||
lm_state.sample_cnt++;
|
||||
if (lm_state.timer >= LM_SETTLE_TIME) {
|
||||
lm_state.step = 3;
|
||||
}
|
||||
break;
|
||||
|
||||
case 3: {
|
||||
*id_ref = LM_IDREF;
|
||||
int measure_ok = 0;
|
||||
if (lm_state.sample_cnt > 0 && lm_state.integral_psi > 0.0f) {
|
||||
float id_avg = lm_state.sum_id / (float)lm_state.sample_cnt;
|
||||
if (id_avg > 0.001f) {
|
||||
float Ls = lm_state.integral_psi / id_avg;
|
||||
float Lm = Ls - params.Lls;
|
||||
if (Lm > 0.0f) {
|
||||
lm_state.avg_Lm += Lm;
|
||||
lm_state.avg_count++;
|
||||
measure_ok = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (lm_state.avg_count >= LM_AVG) {
|
||||
params.Lm = lm_state.avg_Lm / (float)LM_AVG;
|
||||
lm_state.done = 1;
|
||||
lm_state.step = 4;
|
||||
}
|
||||
else if (measure_ok) {
|
||||
lm_state.timer = 0.0f;
|
||||
lm_state.step = 0;
|
||||
}
|
||||
else {
|
||||
lm_state.timer = 0.0f;
|
||||
lm_state.step = 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 4:
|
||||
*id_ref = 0.0f;
|
||||
break;
|
||||
|
||||
default:
|
||||
*id_ref = 0.0f;
|
||||
lm_state.step = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* ============================================
|
||||
*
|
||||
* ============================================ */
|
||||
|
||||
/*
|
||||
* estimate_process -
|
||||
*
|
||||
* : ,
|
||||
*
|
||||
*
|
||||
* :
|
||||
* vd, vq - d,q ( )
|
||||
* id, iq - d,q ( )
|
||||
* dt - ()
|
||||
*
|
||||
* :
|
||||
* vd_ref - d (. .)
|
||||
* vq_ref - q (. .)
|
||||
* freq_ref - ()
|
||||
*/
|
||||
void estimate_process(float vd, float vq, float id, float iq, float dt,
|
||||
float* vd_ref, float* vq_ref, float* freq_ref) {
|
||||
|
||||
*vd_ref = 0;
|
||||
*vq_ref = 0;
|
||||
if (freq_ref) *freq_ref = 0;
|
||||
|
||||
/* IDLE - */
|
||||
if (test_step == ESTIMATE_TEST_IDLE) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* */
|
||||
if (in_pause) {
|
||||
pause_timer += dt;
|
||||
if (pause_timer >= STEP_PAUSE_TIME) {
|
||||
in_pause = 0;
|
||||
/* */
|
||||
if (test_step == ESTIMATE_TEST_RS) test_step = ESTIMATE_TEST_RR_L;
|
||||
else if (test_step == ESTIMATE_TEST_RR_L) test_step = ESTIMATE_TEST_LM;
|
||||
else if (test_step == ESTIMATE_TEST_LM) test_step = ESTIMATE_TEST_DONE;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
switch (test_step) {
|
||||
case ESTIMATE_TEST_RS:
|
||||
process_Rs(vq, iq, dt, vq_ref, freq_ref);
|
||||
if (rs_state.done) {
|
||||
in_pause = 1;
|
||||
pause_timer = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case ESTIMATE_TEST_RR_L:
|
||||
process_RrL(vq, iq, dt, vq_ref, freq_ref);
|
||||
if (rrl_state.done) {
|
||||
in_pause = 1;
|
||||
pause_timer = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case ESTIMATE_TEST_LM:
|
||||
if (vq_ref)
|
||||
*vq_ref = 0.0f;
|
||||
process_Lm(vd, id, dt, vd_ref, freq_ref);
|
||||
if (lm_state.done) {
|
||||
in_pause = 1;
|
||||
pause_timer = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case ESTIMATE_TEST_DONE:
|
||||
/* */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
103
Inu_im_1wnd_3lvl/Inu/estimate.h
Normal file
103
Inu_im_1wnd_3lvl/Inu/estimate.h
Normal file
@@ -0,0 +1,103 @@
|
||||
// ============================================
|
||||
// Файл: estimate.h
|
||||
// ============================================
|
||||
#ifndef ESTIMATE_H
|
||||
#define ESTIMATE_H
|
||||
|
||||
typedef enum {
|
||||
ESTIMATE_TEST_IDLE = 0,
|
||||
ESTIMATE_TEST_RS,
|
||||
ESTIMATE_TEST_RR_L,
|
||||
ESTIMATE_TEST_LM,
|
||||
ESTIMATE_TEST_DONE
|
||||
} Estimate_Test_t;
|
||||
|
||||
typedef struct {
|
||||
float Rs; // сопротивление статора, Ом
|
||||
float Rr; // сопротивление ротора, Ом
|
||||
float Lm; // взаимная индуктивность, Гн
|
||||
float Lk; // полная индуктивность рассеяния, Гн
|
||||
float Lls; // индуктивность рассеяния статора, Гн
|
||||
float Llr; // индуктивность рассеяния ротора, Гн
|
||||
float Zk; // полное сопротивление КЗ, Ом
|
||||
float Rk; // активное сопротивление КЗ, Ом
|
||||
float Xk; // реактивное сопротивление КЗ, Ом
|
||||
} Params_t;
|
||||
|
||||
/*
|
||||
* Состояние автомата для эксперимента по измерению Rs
|
||||
* Метод: разностный метод с двумя уровнями постоянного тока
|
||||
*/
|
||||
typedef struct {
|
||||
char step; /* текущий шаг 0-5 */
|
||||
float timer; /* таймер выдержки времени */
|
||||
float meas1, meas2; /* измеренные напряжения для I1 и I2, В */
|
||||
float val1, val2; /* измеренные токи I1 и I2, А */
|
||||
float sum_v; /* сумма напряжений для усреднения */
|
||||
float sum_i; /* сумма токов для усреднения */
|
||||
int sample_cnt; /* счетчик выборок для усреднения */
|
||||
int done; /* флаг завершения эксперимента */
|
||||
} RsState_t;
|
||||
|
||||
|
||||
/*
|
||||
* Состояние автомата для эксперимента по измерению Rr и Lls, Llr
|
||||
* Метод: подача переменного тока по оси q, RMS измерения
|
||||
*/
|
||||
typedef struct {
|
||||
float timer; /* таймер фазы синусоиды, с */
|
||||
float ramp_timer; /* таймер нарастания амплитуды, с */
|
||||
float sum_p; /* сумма активной мощности, Вт */
|
||||
float sum_vq2; /* сумма квадратов напряжения Vq, В^2 */
|
||||
float sum_iq2; /* сумма квадратов тока Iq, А^2 */
|
||||
int sample_count; /* счетчик выборок */
|
||||
|
||||
/* усреднение одного измерения на текущей частоте */
|
||||
float avg_Zk; /* накопл. Zk для текущей частоты, Ом */
|
||||
float avg_Xk; /* накопл. Xk для текущей частоты, Ом */
|
||||
float avg_Lk; /* накопл. Lk для текущей частоты, Гн */
|
||||
float avg_Rk; /* накопл. Rk для текущей частоты, Ом */
|
||||
int avg_count; /* счетчик усреднений (RRL_AVG) на частоте */
|
||||
|
||||
/* буфер результатов по частотам */
|
||||
int freq_idx; /* индекс текущей частоты */
|
||||
float freq_Zk[5]; /* Zk(f), Ом */
|
||||
float freq_Rk[5]; /* Rk(f), Ом */
|
||||
float freq_Xk[5]; /* Xk(f), Ом */
|
||||
float freq_Lk[5]; /* Lk(f), Гн */
|
||||
int freq_ready; /* сколько частот заполнено */
|
||||
|
||||
int done; /* флаг завершения эксперимента */
|
||||
} RrlState_t;
|
||||
|
||||
|
||||
/*
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> Lm
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD>: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*/
|
||||
typedef struct {
|
||||
char step; /* <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: 0-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>., 1-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>., 2-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, 3-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
float timer; /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> / <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20> */
|
||||
float prev_ed; /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> Ed = Vd - Rs*Id (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>) */
|
||||
float integral_psi; /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ?Ed<45>dt, <20><> */
|
||||
float sum_id; /* <20><><EFBFBD><EFBFBD><EFBFBD> Id <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20> */
|
||||
int sample_cnt; /* <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
float avg_Lm; /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> Lm <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
int avg_count; /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
int done; /* <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
int first_sample; /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
} LmState_t;
|
||||
|
||||
|
||||
|
||||
void estimate_init(void);
|
||||
void estimate_reset(void);
|
||||
void estimate_start(Estimate_Test_t start_test);
|
||||
Estimate_Test_t estimate_get_step(void);
|
||||
Params_t* estimate_get_params(void);
|
||||
|
||||
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
void estimate_process(float vd, float vq, float id, float iq, float dt,
|
||||
float* vd_ref, float* vq_ref, float* freq_ref);
|
||||
|
||||
#endif
|
||||
1621
Inu_im_1wnd_3lvl/Inu/init28335.c
Normal file
1621
Inu_im_1wnd_3lvl/Inu/init28335.c
Normal file
@@ -0,0 +1,1621 @@
|
||||
/**************************************************************************
|
||||
Description: Ïîñëå çàãðóçêè ïðîöåññîðà ôóíêöèÿ âûçûâàåòñÿ îäèí ðàç
|
||||
è èíèöèàëèçèðóåò óïðàâëÿþùèå ðåãèñòðû ïðîöåññîðà
|
||||
TMS320F28335/TMS320F28379D.
|
||||
|
||||
Àâòîð: Óëèòîâñêèé Ä.È.
|
||||
Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.10.04
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
#include "def.h"
|
||||
#include "init28335.h"
|
||||
|
||||
|
||||
#ifndef ML
|
||||
extern void InitPll(Uint16 val, Uint16 divsel);
|
||||
extern void InitPieCtrl(void);
|
||||
extern void InitPieVectTable(void);
|
||||
extern void ADC_cal(void);
|
||||
extern void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
|
||||
extern void InitFlash(void);
|
||||
extern short CsmUnlock(void);
|
||||
void InitPeripheralClocks(void);
|
||||
void SetupGpio(void);
|
||||
extern interrupt void isr(void);
|
||||
#endif //ML
|
||||
void SetupAdc(void);
|
||||
void SetupEpwm(void);
|
||||
void SetupEqep(void);
|
||||
|
||||
|
||||
void init28335(void) {
|
||||
#ifndef ML
|
||||
// Global Disable all Interrupts
|
||||
DINT;
|
||||
// Disable CPU interrupts
|
||||
IER = 0x0000;
|
||||
// Clear all CPU interrupt flags
|
||||
IFR = 0x0000;
|
||||
|
||||
// Initialize the PLL control: PLLCR[DIV] and PLLSTS[DIVSEL]
|
||||
InitPll(PLLCR_DIV, PLLSTS_DIVSEL);
|
||||
|
||||
// Initialize interrupt controller and Vector Table
|
||||
// to defaults for now. Application ISR mapping done later.
|
||||
InitPieCtrl();
|
||||
InitPieVectTable();
|
||||
|
||||
// Initialize the peripheral clocks
|
||||
InitPeripheralClocks();
|
||||
|
||||
// Ulock the CSM
|
||||
csmSuccess = CsmUnlock();
|
||||
|
||||
/* Copy time critical code and Flash setup code to RAM
|
||||
(the RamfuncsLoadStart, RamfuncsLoadEnd, RamfuncsRunStart,
|
||||
RamfuncsLoadStart2, RamfuncsLoadEnd2 and RamfuncsRunStart2
|
||||
symbols are created by the linker) */
|
||||
MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
|
||||
MemCopy(&RamfuncsLoadStart2, &RamfuncsLoadEnd2, &RamfuncsRunStart2);
|
||||
/* Copy the .switch section */
|
||||
// (the SwitchLoadStart, SwitchLoadEnd and SwitchRunStart
|
||||
// symbols are created by the linker)
|
||||
MemCopy(&SwitchLoadStart, &SwitchLoadEnd, &SwitchRunStart);
|
||||
/* Copy the .econst section */
|
||||
// (the EconstLoadStart, EconstLoadEnd and EconstRunStart
|
||||
// symbols are created by the linker)
|
||||
MemCopy(&EconstLoadStart, &EconstLoadEnd, &EconstRunStart);
|
||||
// Call Flash Initialization to setup flash waitstates
|
||||
// (this function must reside in RAM)
|
||||
InitFlash();
|
||||
#endif //ML
|
||||
|
||||
// Setup ePWM
|
||||
SetupEpwm();
|
||||
// Setup ADC
|
||||
SetupAdc();
|
||||
// Setup eQEP
|
||||
SetupEqep();
|
||||
|
||||
#ifndef ML
|
||||
// Setup GPIO
|
||||
SetupGpio();
|
||||
|
||||
// Reassign ISR
|
||||
EALLOW;
|
||||
PieVectTable.ADCINT = &isr;
|
||||
EDIS;
|
||||
#endif //ML
|
||||
} //void init28335(void)
|
||||
|
||||
|
||||
|
||||
#ifndef ML
|
||||
/* This function initializes the clocks to the peripheral modules.
|
||||
First the high and low clock prescalers are set
|
||||
Second the clocks are enabled to each peripheral.
|
||||
To reduce power, leave clocks to unused peripherals disabled
|
||||
|
||||
Note: If a peripherals clock is not enabled then you cannot
|
||||
read or write to the registers for that peripheral */
|
||||
void InitPeripheralClocks(void) {
|
||||
EALLOW;
|
||||
|
||||
// HISPCP/LOSPCP prescale register settings, normally it will be set
|
||||
// to default values
|
||||
// High speed clock = FSYSCLKOUT/2
|
||||
SysCtrlRegs.HISPCP.all = 0x0001;
|
||||
// Low speed clock = FSYSCLKOUT/4
|
||||
SysCtrlRegs.LOSPCP.all = 0x0002;
|
||||
|
||||
/* Peripheral clock enables set for the selected peripherals.
|
||||
If you are not using a peripheral leave the clock off
|
||||
to save on power.
|
||||
|
||||
This function is not written to be an example of efficient code */
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
|
||||
|
||||
/* IMPORTANT
|
||||
The ADC_cal function, which copies the ADC calibration values from
|
||||
TI reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs
|
||||
automatically in the Boot ROM. If the boot ROM code is bypassed
|
||||
during the debug process, the following function MUST be called for
|
||||
the ADC to function according to specification. The clocks to the
|
||||
ADC MUST be enabled before calling this function.
|
||||
See the device data manual and/or the ADC Reference
|
||||
Manual for more information */
|
||||
ADC_cal();
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 0; // I2C
|
||||
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 0; // SCI-A
|
||||
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 0; // SCI-B
|
||||
SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 0; // SCI-C
|
||||
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 0; // SPI-A
|
||||
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 0;// McBSP-A
|
||||
SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 0;// McBSP-B
|
||||
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 0; // eCAN-A
|
||||
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 0; // eCAN-B
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
|
||||
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
|
||||
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 0; // eCAP3
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 0; // eCAP4
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 0; // eCAP5
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 0; // eCAP6
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 0; // eCAP1
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 0; // eCAP2
|
||||
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 0; // eQEP1
|
||||
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
|
||||
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 0; // CPU Timer 0
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 0; // CPU Timer 1
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 0; // CPU Timer 2
|
||||
|
||||
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 0; // DMA Clock
|
||||
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
|
||||
SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
|
||||
|
||||
EDIS;
|
||||
} //void InitPeripheralClocks(void)
|
||||
|
||||
|
||||
|
||||
// Íàñòðàèâàåò GPIO
|
||||
void SetupGpio(void) {
|
||||
EALLOW;
|
||||
// GPIO and Peripheral Multiplexing
|
||||
// GPIO0 ... GPIO15
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;//EPWM1A (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;//EPWM1B (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;//EPWM2A (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;//EPWM2B (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;//EPWM3A (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;//EPWM3B (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1;//EPWM4A (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1;//EPWM4B (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1;//EPWM5A (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;//EPWM5B (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;//EPWM6A (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;//EPWM6B (INU)
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0;//DI
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0;//DO
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0;//DI
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0;//DO
|
||||
// GPIO16 ... GPIO31
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0;//DI
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0;//DO
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0;//DI
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0;//DO
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0;//DO
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0;//DI
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3;//SCITXDB
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3;//SCIRXDB
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2;//EQEP2A
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2;//EQEP2B
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2;//EQEP2I
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0;//DI
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;//SCIRXDA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;//SCITXDA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0;//DO
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3;//XA17
|
||||
// GPIO32 ... GPIO47
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2;//EPWMSYNCI
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2;//EPWMSYNCO
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;//DO
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0;//DO
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3;//XZCS0
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3;//XZCS7
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3;//XWE0
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3;//XA16
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3;//XA0/XWE1
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3;//XA1
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3;//XA2
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3;//XA3
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3;//XA4
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3;//XA5
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3;//XA6
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3;//XA7
|
||||
// GPIO48 ... GPIO63
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 0;//DO
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 0;//DO
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 0;//DI (íåèñïðàâíîñòü èñòî÷íèêà ïèòàíèÿ +24 Â)
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 0;//DI
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 0;//DI
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 0;//DI
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1;//SPISIMOA
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1;//SPISOMIA
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1;//SPICLKA
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0;//DO
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0;//DO
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 0;//DO (çåëåíûé ñâåòîäèîä "Ãîòîâíîñòü")
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 0;//DO (çåëåíûé ñâåòîäèîä "Ðàáîòà")
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0;//DO (êðàñíûé ñâåòîäèîä "Àâàðèÿ")
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1;//SCIRXDC
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1;//SCITXDC
|
||||
// GPIO64 ... GPIO79
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3;//XD15
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3;//XD14
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3;//XD13
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3;//XD12
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3;//XD11
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3;//XD10
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3;//XD9
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3;//XD8
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3;//XD7
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3;//XD6
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3;//XD5
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3;//XD4
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3;//XD3
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3;//XD2
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3;//XD1
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3;//XD0
|
||||
// GPIO80 ... GPIO87
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3;//XA8
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3;//XA9
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3;//XA10
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3;//XA11
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3;//XA12
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3;//XA13
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3;//XA14
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3;//XA15
|
||||
|
||||
// âûáèðàåì ñîñòîÿíèå öèôðîâûõ âûõîäîâ
|
||||
DO_GPIO019_CLEAR;
|
||||
DO_GPIO020_CLEAR;
|
||||
DO_GPIO022_CLEAR;
|
||||
// ... ñâåòîäèîäû âûêëþ÷àåì
|
||||
LED_GREEN1_OFF;
|
||||
LED_GREEN2_OFF;
|
||||
LED_RED_OFF;
|
||||
DO_GPIO63_CLEAR;
|
||||
|
||||
// Select the direction of the GPIO pins
|
||||
// GPIO0 ... GPIO31
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO0 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO1 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO2 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO3 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO4 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO5 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO6 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO7 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO8 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO9 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO10 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO11 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO12 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO13 = 1;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO14 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO15 = 1;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO16 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO17 = 1;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO18 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO19 = 1;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO20 = 1;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO21 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO22 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO23 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO24 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO25 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO26 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO27 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO28 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO29 = 0;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO30 = 1;
|
||||
GpioCtrlRegs.GPADIR.bit.GPIO31 = 0;
|
||||
// GPIO32 ... GPIO63
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO32 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO33 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO35 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO36 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO37 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO38 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO40 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO41 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO42 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO43 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO44 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO45 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO50 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO52 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO53 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO55 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO59 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO60 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO62 = 0;
|
||||
GpioCtrlRegs.GPBDIR.bit.GPIO63 = 1;
|
||||
// GPIO64 ... GPIO87
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO65 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO68 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO69 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO70 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO71 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO72 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO73 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO74 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO75 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO76 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO77 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO78 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO79 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO80 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO81 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO82 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO84 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO85 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO86 = 0;
|
||||
GpioCtrlRegs.GPCDIR.bit.GPIO87 = 0;
|
||||
|
||||
// Each input can have different qualification:
|
||||
// 0 - Synchronize to FSYSCLKOUT only;
|
||||
// 1 - Qualification using 3 samples;
|
||||
// 2 - Qualification using 6 samples;
|
||||
// 3 - Asynchronous.
|
||||
// GPIO0 ... GPIO15
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 2;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 2;
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 0;
|
||||
// GPIO16 ... GPIO31
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 2;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 0;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 2;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 0;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 2;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 2;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 0;
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 0;
|
||||
// GPIO32 ... GPIO47
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO36 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO38 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO39 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO40 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO41 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO42 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO43 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO44 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO45 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO46 = 0;
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO47 = 0;
|
||||
// GPIO48 ... GPIO63
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 2;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 2;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 2;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 2;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 0;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 0;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 0;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 0;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 2;
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0;
|
||||
|
||||
// Qualification Control (sampling period = (1/FSYSCLKOUT)*QUALPRDx*2)
|
||||
// ( (1/150e6)*255*2 = 3.4 ìêñ )
|
||||
// Port A
|
||||
GpioCtrlRegs.GPACTRL.bit.QUALPRD0 = 255;//GPIO0 ... GPIO7
|
||||
GpioCtrlRegs.GPACTRL.bit.QUALPRD1 = 255;//GPIO8 ... GPIO15
|
||||
GpioCtrlRegs.GPACTRL.bit.QUALPRD2 = 255;//GPIO16 ... GPIO23
|
||||
GpioCtrlRegs.GPACTRL.bit.QUALPRD3 = 255;//GPIO24 ... GPIO31
|
||||
// Port B
|
||||
GpioCtrlRegs.GPBCTRL.bit.QUALPRD0 = 255;//GPIO32 ... GPIO39
|
||||
GpioCtrlRegs.GPBCTRL.bit.QUALPRD1 = 255;//GPIO40 ... GPIO47
|
||||
GpioCtrlRegs.GPBCTRL.bit.QUALPRD2 = 255;//GPIO48 ... GPIO55
|
||||
GpioCtrlRegs.GPBCTRL.bit.QUALPRD3 = 255;//GPIO56 ... GPIO63
|
||||
|
||||
// Pull-ups (the internal pullup çàïðåù¸í äëÿ ØÈÌ-âûõîäîâ)
|
||||
// GPIO0 ... GPIO31
|
||||
GpioCtrlRegs.GPAPUD.all = 0x00000FFF;
|
||||
// GPIO32 ... GPIO63
|
||||
GpioCtrlRegs.GPBPUD.all = 0x00000000;
|
||||
// GPIO64 ... GPIO87
|
||||
GpioCtrlRegs.GPCPUD.all = 0x00000000;
|
||||
EDIS;
|
||||
} //void SetupGpio(void)
|
||||
#endif //ML
|
||||
|
||||
|
||||
|
||||
// Íàñòðàèâàåò ePWM
|
||||
void SetupEpwm(void) {
|
||||
// ePWM1
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm1Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm1Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;//TBCTR==0 -> EPWMxSYNCO
|
||||
EPwm1Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm1Regs.TBCTL.bit.PHSEN = 0;//do not load TBCTR from TBPHS
|
||||
EPwm1Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm1Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm1Regs.TBPHS.half.TBPHS = 0;
|
||||
// Time-Base Counter Register
|
||||
EPwm1Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm1Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm1Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;//active CMPB load from shadow - load on CTR = Zero
|
||||
EPwm1Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm1Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm1Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm1Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
||||
EPwm1Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
||||
EPwm1Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm1Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm1Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm1Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm1Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm1Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm1Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm1Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm1Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm1Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm1Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm1Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm1Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm1Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm1Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm1Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm1Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm1Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm1Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm1Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm1Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm1Regs.ETSEL.bit.SOCBEN = 1;//enable EPWMxSOCB pulse
|
||||
EPwm1Regs.ETSEL.bit.SOCBSEL = 1;//EPWMxSOCB selection - enable event CTR == 0
|
||||
EPwm1Regs.ETSEL.bit.SOCAEN = 1;//enable EPWMxSOCA pulse
|
||||
EPwm1Regs.ETSEL.bit.SOCASEL = 2;//EPWMxSOCA selection - enable event CTR == PRD
|
||||
EPwm1Regs.ETSEL.bit.INTEN = 0;//disable EPWMx_INT generation
|
||||
EPwm1Regs.ETSEL.bit.INTSEL = 0;//reserved
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm1Regs.ETPS.bit.SOCBPRD = 1;//generate the EPWMxSOCB pulse on the first event
|
||||
EPwm1Regs.ETPS.bit.SOCAPRD = 1;//generate the EPWMxSOCA pulse on the first event
|
||||
EPwm1Regs.ETPS.bit.INTPRD = 0;//disable the interrupt event counter (no interrupt will be generated)
|
||||
|
||||
// ePWM2
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm2Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm2Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm2Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm2Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm2Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm2Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm2Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm2Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm2Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm2Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm2Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm2Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm2Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm2Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm2Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
||||
EPwm2Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
||||
EPwm2Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm2Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm2Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm2Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm2Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm2Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm2Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm2Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm2Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm2Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm2Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm2Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm2Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm2Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm2Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm2Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm2Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm2Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm2Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm2Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm2Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm2Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm2Regs.ETPS.all = 0;
|
||||
|
||||
// ePWM3
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm3Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm3Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm3Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm3Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm3Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm3Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm3Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm3Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm3Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm3Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm3Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm3Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm3Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm3Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm3Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
||||
EPwm3Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
||||
EPwm3Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm3Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm3Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm3Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm3Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm3Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm3Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm3Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm3Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm3Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm3Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm3Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm3Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm3Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm3Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm3Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm3Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm3Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm3Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm3Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm3Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm3Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm3Regs.ETPS.all = 0;
|
||||
|
||||
// ePWM4
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm4Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm4Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm4Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm4Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm4Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm4Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm4Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm4Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm4Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm4Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm4Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm4Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm4Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm4Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm4Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm4Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
||||
EPwm4Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
||||
EPwm4Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm4Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm4Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm4Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm4Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm4Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm4Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm4Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm4Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm4Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm4Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm4Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm4Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm4Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm4Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm4Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm4Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm4Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm4Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm4Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm4Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm4Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm4Regs.ETPS.all = 0;
|
||||
|
||||
// ePWM5
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm5Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm5Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm5Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm5Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm5Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm5Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm5Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm5Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm5Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm5Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm5Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm5Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm5Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm5Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm5Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm5Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm5Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
||||
EPwm5Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
||||
EPwm5Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm5Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm5Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm5Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm5Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm5Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm5Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm5Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm5Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm5Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm5Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm5Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm5Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm5Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm5Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm5Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm5Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm5Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm5Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm5Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm5Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm5Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm5Regs.ETPS.all = 0;
|
||||
|
||||
// ePWM6
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm6Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm6Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm6Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm6Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm6Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm6Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm6Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm6Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm6Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm6Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm6Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm6Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm6Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm6Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm6Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm6Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm6Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
||||
EPwm6Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
||||
EPwm6Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm6Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm6Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm6Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm6Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm6Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm6Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm6Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm6Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm6Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm6Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm6Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm6Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm6Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm6Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm6Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm6Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm6Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm6Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm6Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm6Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm6Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm6Regs.ETPS.all = 0;
|
||||
|
||||
#ifdef ML
|
||||
// ePWM7
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm7Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm7Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm7Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm7Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm7Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm7Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm7Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm7Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm7Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm7Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm7Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm7Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm7Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm7Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm7Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm7Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm7Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm7Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm7Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm7Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
||||
EPwm7Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
||||
EPwm7Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm7Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm7Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm7Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm7Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm7Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm7Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm7Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm7Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm7Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm7Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm7Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm7Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm7Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm7Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm7Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm7Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm7Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm7Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm7Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm7Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm7Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm7Regs.ETPS.all = 0;
|
||||
|
||||
// ePWM8
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm8Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm8Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm8Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm8Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm8Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm8Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm8Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm8Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm8Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm8Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm8Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm8Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm8Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm8Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm8Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm8Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm8Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm8Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm8Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm8Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
||||
EPwm8Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
||||
EPwm8Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm8Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm8Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm8Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm8Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm8Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm8Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm8Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm8Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm8Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm8Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm8Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm8Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm8Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm8Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm8Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm8Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm8Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm8Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm8Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm8Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm8Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm8Regs.ETPS.all = 0;
|
||||
|
||||
// ePWM9
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm9Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm9Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm9Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm9Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm9Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm9Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm9Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm9Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm9Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm9Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm9Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm9Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm9Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm9Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm9Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm9Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm9Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm9Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm9Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm9Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
||||
EPwm9Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
||||
EPwm9Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm9Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm9Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm9Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm9Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm9Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm9Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm9Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm9Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm9Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm9Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm9Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm9Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm9Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm9Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm9Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm9Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm9Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm9Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm9Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm9Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm9Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm9Regs.ETPS.all = 0;
|
||||
|
||||
// ePWM10
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm10Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm10Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm10Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm10Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm10Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm10Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm10Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm10Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm10Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm10Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm10Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm10Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm10Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm10Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm10Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm10Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm10Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm10Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm10Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm10Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
||||
EPwm10Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
||||
EPwm10Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm10Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm10Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm10Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm10Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm10Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm10Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm10Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm10Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm10Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm10Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm10Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm10Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm10Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm10Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm10Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm10Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm10Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm10Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm10Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm10Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm10Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm10Regs.ETPS.all = 0;
|
||||
|
||||
// ePWM11
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm11Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm11Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm11Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm11Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm11Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm11Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm11Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm11Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm11Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm11Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm11Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm11Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm11Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm11Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm11Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm11Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm11Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm11Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm11Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm11Regs.AQCTLA.bit.CAD = 2;//set - force EPWMxA output high
|
||||
EPwm11Regs.AQCTLA.bit.CAU = 1;//clear - force EPWMxA output low
|
||||
EPwm11Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm11Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm11Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm11Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm11Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm11Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm11Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm11Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm11Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm11Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm11Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm11Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm11Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm11Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm11Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm11Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm11Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm11Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm11Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm11Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm11Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm11Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm11Regs.ETPS.all = 0;
|
||||
|
||||
// ePWM12
|
||||
// ####################################################################
|
||||
// Time-Base (TB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Time-Base Control Register
|
||||
EPwm12Regs.TBCTL.bit.FREE_SOFT = 0;//emulation mode - stop after the next time-base counter increment or decrement
|
||||
EPwm12Regs.TBCTL.bit.PHSDIR = 1;//count up after the synchronization event
|
||||
EPwm12Regs.TBCTL.bit.CLKDIV = 0;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm12Regs.TBCTL.bit.HSPCLKDIV = 2;//TBCLK = SYSCLKOUT/(HSPCLKDIV*CLKDIV)
|
||||
EPwm12Regs.TBCTL.bit.SYNCOSEL = 0;//SYNCO = SYNCI
|
||||
EPwm12Regs.TBCTL.bit.PRDLD = 1;//load the TBPRD register immediately without using a shadow register
|
||||
EPwm12Regs.TBCTL.bit.PHSEN = 1;//load TBCTR with TBPHS when EPWMxSYNCI input signal occurs
|
||||
EPwm12Regs.TBCTL.bit.CTRMODE = 3;//stop-freeze counter operation
|
||||
// Time-Base Period Register
|
||||
EPwm12Regs.TBPRD = (unsigned short)T1_PRD;
|
||||
// Time-Base Phase Register
|
||||
EPwm12Regs.TBPHS.half.TBPHS = 2;
|
||||
// Time-Base Counter Register
|
||||
EPwm12Regs.TBCTR = 1;
|
||||
// Counter-Compare (CC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Counter-Compare A Register
|
||||
EPwm12Regs.CMPA.half.CMPA = 0;
|
||||
// Counter-Compare B Register
|
||||
EPwm12Regs.CMPB = 0;
|
||||
// Counter-Compare Control Register
|
||||
EPwm12Regs.CMPCTL.bit.SHDWBMODE = 0;//CMPB operating mode - shadow
|
||||
EPwm12Regs.CMPCTL.bit.SHDWAMODE = 0;//CMPA operating mode - shadow
|
||||
EPwm12Regs.CMPCTL.bit.LOADBMODE = 0;//has no effect in immediate mode
|
||||
EPwm12Regs.CMPCTL.bit.LOADAMODE = 2;//active CMPA load from shadow - load on CTR = Zero or CTR = PRD
|
||||
// Action-Qualifier (AQ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Action-Qualifier Output A Control Register
|
||||
EPwm12Regs.AQCTLA.bit.CBD = 0;//do nothing
|
||||
EPwm12Regs.AQCTLA.bit.CBU = 0;//do nothing
|
||||
EPwm12Regs.AQCTLA.bit.CAD = 1;//clear - force EPWMxA output low
|
||||
EPwm12Regs.AQCTLA.bit.CAU = 2;//set - force EPWMxA output high
|
||||
EPwm12Regs.AQCTLA.bit.PRD = 0;//do nothing
|
||||
EPwm12Regs.AQCTLA.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Output B Control Register
|
||||
EPwm12Regs.AQCTLB.bit.CBD = 0;//do nothing
|
||||
EPwm12Regs.AQCTLB.bit.CBU = 0;//do nothing
|
||||
EPwm12Regs.AQCTLB.bit.CAD = 0;//do nothing
|
||||
EPwm12Regs.AQCTLB.bit.CAU = 0;//do nothing
|
||||
EPwm12Regs.AQCTLB.bit.PRD = 0;//do nothing
|
||||
EPwm12Regs.AQCTLB.bit.ZRO = 0;//do nothing
|
||||
// Action-Qualifier Software Force Register
|
||||
EPwm12Regs.AQSFRC.all = 0;
|
||||
// Action-Qualifier Continuous Software Force Register
|
||||
EPwm12Regs.AQCSFRC.all = 0;
|
||||
// Dead-Band Generator (DB) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Dead-Band Generator Control Register
|
||||
EPwm12Regs.DBCTL.bit.IN_MODE = 0;//EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay
|
||||
EPwm12Regs.DBCTL.bit.POLSEL = 2;//active high complementary (AHC) mode
|
||||
EPwm12Regs.DBCTL.bit.OUT_MODE = 3;//dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB
|
||||
// Dead-Band Generator Rising Edge Delay Register
|
||||
EPwm12Regs.DBRED = (unsigned short)(FTBCLK*DT);
|
||||
// Dead-Band Generator Falling Edge Delay Register
|
||||
EPwm12Regs.DBFED = (unsigned short)(FTBCLK*DT);
|
||||
// PWM-Chopper (PC) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// PWM-Chopper Control Register
|
||||
EPwm12Regs.PCCTL.all = 0;
|
||||
// Trip-Zone (TZ) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
EALLOW;
|
||||
// Trip-Zone Select Register
|
||||
EPwm12Regs.TZSEL.all = 0;
|
||||
// Trip-Zone Control Register
|
||||
EPwm12Regs.TZCTL.bit.TZB = 2;//when a trip event occurs the following action is taken on output EPWMxB - force EPWMxB to a low state
|
||||
EPwm12Regs.TZCTL.bit.TZA = 2;//when a trip event occurs the following action is taken on output EPWMxA - force EPWMxA to a low state
|
||||
// Trip-Zone Enable Interrupt Register
|
||||
EPwm12Regs.TZEINT.all = 0;
|
||||
// Trip-Zone Force Register
|
||||
EPwm12Regs.TZFRC.all = 0x0004;//forces a one-shot trip event via software and sets the TZFLG[OST] bit
|
||||
EDIS;
|
||||
// Event-Trigger (ET) Submodule
|
||||
// --------------------------------------------------------------------
|
||||
// Event-Trigger Selection Register
|
||||
EPwm12Regs.ETSEL.all = 0;
|
||||
// Event-Trigger Prescale Register
|
||||
EPwm12Regs.ETPS.all = 0;
|
||||
#endif //ML
|
||||
} //void SetupEpwm(void)
|
||||
|
||||
|
||||
|
||||
// Íàñòðàèâàåò ADC
|
||||
void SetupAdc(void) {
|
||||
#ifndef ML
|
||||
unsigned short i;
|
||||
|
||||
// ADC Control Register 1
|
||||
AdcRegs.ADCTRL1.bit.SUSMOD = 0;//emulation suspend is ignored
|
||||
AdcRegs.ADCTRL1.bit.ACQ_PS = 3;//width of SOC pulse is (ACQ_PS+1) times the ADCLK period
|
||||
AdcRegs.ADCTRL1.bit.CPS = 0;//ADCCLK = HSPCLK/(2*ADCCLKPS*(CPS+1))
|
||||
AdcRegs.ADCTRL1.bit.CONT_RUN = 0;//start-stop mode
|
||||
AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0;//sequencer override disabled
|
||||
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;//cascaded mode
|
||||
|
||||
// ADC Control Register 2
|
||||
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 1;//allows SEQ to be started by ePWMx SOCB trigger
|
||||
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0;//clears a pending SOC trigger
|
||||
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;//interrupt request by INT_SEQ1 is enabled
|
||||
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0;//INT_SEQ1 is set at the end of every SEQ1 sequence
|
||||
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;//allows SEQ1/SEQ to be started by ePWMx SOCA trigger
|
||||
AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1 = 0;//disables an ADC autoconversion sequence to be started by a signal from a GPIO Port A pin
|
||||
AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 0;//clears a pending SOC trigger
|
||||
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2 = 0;//interrupt request by INT_SEQ2 is disabled
|
||||
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ2 = 0;//INT_SEQ2 is set at the end of every SEQ2 sequence
|
||||
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2 = 0;//SEQ2 cannot be started by ePWMx SOCB trigger
|
||||
|
||||
/* The ADC resets to the ADC off state. When powering up the ADC, use
|
||||
the following sequence:
|
||||
1. If external reference is desired, enable this mode using bits
|
||||
15-14 in the ADCREFSEL Register. This mode must be enabled before
|
||||
band gap is powered;
|
||||
2. Power up the reference, bandgap, and analog circuits together by
|
||||
setting bits 7-5 (ADCBGRFDN[1:0], ADCPWDN) in the ADCTRL3 register;
|
||||
3. Before performing the first conversion, a delay of 5 ms is required */
|
||||
|
||||
// ADC Reference Select Register
|
||||
AdcRegs.ADCREFSEL.bit.REF_SEL = 1;//external reference, 2.048 V on ADCREFIN
|
||||
|
||||
// ADC Control Register 3
|
||||
AdcRegs.ADCTRL3.all = 0x00E0;//power up the reference, bandgap, and analog circuits together
|
||||
AdcRegs.ADCTRL3.bit.ADCCLKPS = 5;//ADCCLK = HSPCLK/(2*ADCCLKPS*(CPS+1)) -> ADCCLK = 75e6/(2*5*(0+1)) = 7.5e6 Ãö
|
||||
AdcRegs.ADCTRL3.bit.SMODE_SEL = 1;//simultaneous sampling mode
|
||||
|
||||
// Delay before converting ADC channels
|
||||
for ( i = 0; i < 65500; i++ )
|
||||
;
|
||||
#endif //ML
|
||||
|
||||
// Maximum Conversion Channels Register
|
||||
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 5;//6 double conv's (12 total)
|
||||
// ADC Input Channel Select Sequencing Control Registers
|
||||
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0;
|
||||
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1;
|
||||
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2;
|
||||
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 3;
|
||||
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 4;
|
||||
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 5;
|
||||
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 6;
|
||||
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 7;
|
||||
AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0;
|
||||
AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0;
|
||||
AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0;
|
||||
AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0;
|
||||
AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0;
|
||||
AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0;
|
||||
AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0;
|
||||
AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0;
|
||||
} //void SetupAdc(void)
|
||||
|
||||
|
||||
|
||||
// Íàñòðàèâàåò eQEP
|
||||
void SetupEqep(void) {
|
||||
// eQEP Decoder Control Register
|
||||
EQep2Regs.QDECCTL.bit.QSRC = 0;//Position-counter source selection: Quadrature count mode (QCLK = iCLK, QDIR = iDIR)
|
||||
EQep2Regs.QDECCTL.bit.SOEN = 0;//Sync output-enable: Disable position-compare sync output
|
||||
EQep2Regs.QDECCTL.bit.SPSEL = 0;//Sync output pin selection: Index pin is used for sync output
|
||||
EQep2Regs.QDECCTL.bit.XCR = 0;//External clock rate: 2x resolution: Count the rising/falling edge
|
||||
EQep2Regs.QDECCTL.bit.SWAP = 0;//Swap quadrature clock inputs: Quadrature-clock inputs are not swapped
|
||||
EQep2Regs.QDECCTL.bit.IGATE = 0;//Index pulse gating option: Disable gating of Index pulse
|
||||
EQep2Regs.QDECCTL.bit.QAP = 0;//QEPA input polarity: No effect
|
||||
EQep2Regs.QDECCTL.bit.QBP = 0;//QEPB input polarity: No effect
|
||||
EQep2Regs.QDECCTL.bit.QIP = 0;//QEPI input polarity: No effect
|
||||
EQep2Regs.QDECCTL.bit.QSP = 0;//QEPS input polarity: No effect
|
||||
// eQEP Control Register
|
||||
EQep2Regs.QEPCTL.bit.FREE_SOFT = 0;//Emulation Control Bits: all stops immediately
|
||||
EQep2Regs.QEPCTL.bit.PCRM = 1;//Position counter reset mode: position counter reset on the maximum position
|
||||
EQep2Regs.QEPCTL.bit.SEI = 0;//Strobe event initialization of position counter: does nothing (action disabled)
|
||||
EQep2Regs.QEPCTL.bit.IEI = 0;//Index event initialization of position counter: do nothing (action disabled)
|
||||
EQep2Regs.QEPCTL.bit.SWI = 0;//Software initialization of position counter: do nothing (action disabled)
|
||||
EQep2Regs.QEPCTL.bit.SEL = 0;//Strobe event latch of position counter: the position counter is latched on the rising edge of QEPS strobe
|
||||
EQep2Regs.QEPCTL.bit.IEL = 1;//Index event latch of position counter (software index marker): latches position counter on rising edge of the index signal
|
||||
EQep2Regs.QEPCTL.bit.QPEN = 1;//Quadrature position counter enable/software reset: eQEP position counter is enabled
|
||||
EQep2Regs.QEPCTL.bit.QCLM = 0;//eQEP capture latch mode: latch on position counter read by CPU
|
||||
EQep2Regs.QEPCTL.bit.UTE = 1;//eQEP unit timer enable: Enable unit timer
|
||||
EQep2Regs.QEPCTL.bit.WDE = 0;//eQEP watchdog enable: disable the eQEP watchdog timer
|
||||
// eQEP Position-compare Control Register
|
||||
EQep2Regs.QPOSCTL.bit.PCSHDW = 0;//Position-compare shadow enable: Shadow disabled, load Immediate
|
||||
EQep2Regs.QPOSCTL.bit.PCLOAD = 0;//Position-compare shadow load mode: Load on QPOSCNT = 0
|
||||
EQep2Regs.QPOSCTL.bit.PCPOL = 0;//Polarity of sync output: Active HIGH pulse output
|
||||
EQep2Regs.QPOSCTL.bit.PCE = 0;//Position-compare enable/disable: Disable position compare unit
|
||||
EQep2Regs.QPOSCTL.bit.PCSPW = 0;//Select-position-compare sync output pulse width: 1 * 4 * SYSCLKOUT cycles
|
||||
// eQEP Capture Control Register
|
||||
EQep2Regs.QCAPCTL.bit.CEN = 1;//Enable eQEP capture: eQEP capture unit is enabled
|
||||
EQep2Regs.QCAPCTL.bit.CCPS = 2;//eQEP capture timer clock prescaler: CAPCLK = SYSCLKOUT/4
|
||||
EQep2Regs.QCAPCTL.bit.UPPS = 0;//Unit position event prescaler: UPEVNT = QCLK/1
|
||||
// eQEP Position Counter Register
|
||||
EQep2Regs.QPOSCNT = 0x00000000;
|
||||
// eQEP Maximum Position Count Register Register
|
||||
EQep2Regs.QPOSMAX = 0x7FFF;
|
||||
// eQEP Position-compare Register
|
||||
EQep2Regs.QPOSCMP = 0x00000000;
|
||||
// eQEP Unit Timer Register
|
||||
EQep2Regs.QUTMR = 0x00000000;
|
||||
// eQEP Register Unit Period Register
|
||||
EQep2Regs.QUPRD = 0x00000000;
|
||||
// eQEP Watchdog Timer Register
|
||||
EQep2Regs.QWDTMR = 0x0000;
|
||||
// eQEP Watchdog Period Register
|
||||
EQep2Regs.QWDPRD = 0x0000;
|
||||
// eQEP Interrupt Enable Register
|
||||
EQep2Regs.QEINT.all = 0x0000;
|
||||
// eQEP Capture Timer Register
|
||||
EQep2Regs.QCTMR = 0x0000;
|
||||
// eQEP Capture Period Register
|
||||
EQep2Regs.QCPRD = 0x0000;
|
||||
} //void SetupEqep(void)
|
||||
24
Inu_im_1wnd_3lvl/Inu/init28335.h
Normal file
24
Inu_im_1wnd_3lvl/Inu/init28335.h
Normal file
@@ -0,0 +1,24 @@
|
||||
#ifndef INIT28335
|
||||
#define INIT28335
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â init28335.c (begin)
|
||||
//#########################################################################
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â init28335.c (end)
|
||||
|
||||
|
||||
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â init28335.c (begin)
|
||||
//#########################################################################
|
||||
#ifndef ML
|
||||
extern Uint16 RamfuncsLoadStart, RamfuncsLoadEnd, RamfuncsRunStart;
|
||||
extern Uint16 RamfuncsLoadStart2, RamfuncsLoadEnd2, RamfuncsRunStart2;
|
||||
extern Uint16 SwitchLoadStart, SwitchLoadEnd, SwitchRunStart;
|
||||
extern Uint16 EconstLoadStart, EconstLoadEnd, EconstRunStart;
|
||||
extern short csmSuccess;
|
||||
#endif //ML
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â init28335.c (end)
|
||||
|
||||
#endif //INIT28335
|
||||
334
Inu_im_1wnd_3lvl/Inu/isr.c
Normal file
334
Inu_im_1wnd_3lvl/Inu/isr.c
Normal file
@@ -0,0 +1,334 @@
|
||||
/**************************************************************************
|
||||
Description: Ôóíêöèÿ îáñëóæèâàíèÿ ïðåðûâàíèÿ îò ÀÖÏ.
|
||||
Îïðàøèâàåò ÀÖÏ, ñîäåðæèò áëîê îáðàáîòêè âõîäíûõ âåëè÷èí
|
||||
(íàïðÿæåíèé, òîêîâ, ÷àñòîòû âðàùåíèÿ), áëîê çàùèò,
|
||||
áëîê ñ óïðàâëÿþùåé ëîãèêîé, áëîê äëÿ ðàáîòû ñ ÏÓ è EEPROM.
|
||||
|
||||
Àâòîð: Óëèòîâñêèé Ä.È.
|
||||
Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.11.08
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
#include "def.h"
|
||||
#include "isr.h"
|
||||
|
||||
|
||||
#pragma CODE_SECTION(isr, "ramfuncs");
|
||||
#pragma CODE_SECTION(make_pause_before_rerun, "ramfuncs");
|
||||
#pragma CODE_SECTION(sens_wm, "ramfuncs2");
|
||||
#pragma CODE_SECTION(snapshot_emergency, "ramfuncs");
|
||||
#pragma CODE_SECTION(stop_inu, "ramfuncs");
|
||||
|
||||
|
||||
void make_pause_before_rerun(void);
|
||||
void sens_wm(void);
|
||||
void snapshot_emergency(void);
|
||||
void stop_inu(void);
|
||||
extern short test_param(void);
|
||||
extern void upr(void);
|
||||
|
||||
|
||||
#ifndef ML
|
||||
interrupt void isr(void) {
|
||||
#else //ML
|
||||
void isr(void) {
|
||||
#endif //ML
|
||||
// ðåçóëüòàòû ÀÖÏ
|
||||
result.udc1 = AdcMirror.ADCRESULT0 - offset.Udc1;
|
||||
result.ic1 = AdcMirror.ADCRESULT2 - offset.Ic1;
|
||||
result.ia1 = AdcMirror.ADCRESULT4 - offset.Ia1;
|
||||
result.ib1 = AdcMirror.ADCRESULT6 - offset.Ib1;
|
||||
|
||||
// reset SEQ1 or the cascaded sequencer immediately to an initial
|
||||
// "pretriggered" state, i.e., waiting for a trigger at CONV00
|
||||
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
|
||||
|
||||
|
||||
// Îáðàáîòêà è âû÷èñëåíèå âñÿêîãî
|
||||
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
udc1Nf = (float)result.udc1*GAIN_UDC;//åä. ÀÖÏ -> î.å.
|
||||
ia1Nf = (float)result.ia1*GAIN_IAC;//åä. ÀÖÏ -> î.å.
|
||||
ib1Nf = (float)result.ib1*GAIN_IAC;//åä. ÀÖÏ -> î.å.
|
||||
// Udc1, o.e.
|
||||
udc1 += (udc1Nf - udc1)*Kudc;
|
||||
// ... (äëÿ âûâîäà)
|
||||
out.udc1 += (udc1Nf - out.udc1)*out.K;
|
||||
|
||||
// Iac, î.å.
|
||||
// ... ïðîåêöèè íà îñè x-y
|
||||
ix1 = ia1Nf;
|
||||
iy1 = (ia1Nf + 2.*ib1Nf)*ISQRT3;
|
||||
|
||||
// ... àìïëèòóäà
|
||||
iac1Nf = sqrt(ix1*ix1 + iy1*iy1);
|
||||
// ... (äëÿ âûâîäà)
|
||||
out.iac1 += (iac1Nf - out.iac1)*out.K;
|
||||
|
||||
// Wm, o.e. (EQep2Regs.QPOSCNT -> wmNf, wm, out.wm)
|
||||
sens_wm();
|
||||
|
||||
// Me, o.e.
|
||||
kMe = sgmPar.Kl*psi*KmeCorr;
|
||||
meNf = iq1*kMe;
|
||||
me += (meNf - me)*Kme;//äëÿ çàùèò è îãðàíè÷åíèÿ
|
||||
out.me += (meNf - out.me)*out.K;//äëÿ âûâîäà
|
||||
|
||||
// Pm, o.e.
|
||||
pm = wm*me;
|
||||
out.pm += (pm - out.pm)*out.K;//äëÿ âûâîäà
|
||||
// ... ìîùíîñòü, êîòîðóþ ìîæíî ñðàâíèâàòü ñ çàäàííîé
|
||||
if ( wm >= 0 )
|
||||
rp.pmEqv = pm;
|
||||
else
|
||||
rp.pmEqv = -pm;
|
||||
|
||||
// äëÿ âûäåðæêè ïàóçû ïåðåä ïîâòîðíûì ïóñêîì
|
||||
// (state -> stopPause)
|
||||
make_pause_before_rerun();
|
||||
|
||||
|
||||
|
||||
|
||||
// Çàùèòû
|
||||
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
// ----------------------------------------------------------------
|
||||
if ( state == STATE_WORK ) {
|
||||
// ïîâûøåíèå òîêà
|
||||
if ( (result.ia1 > protect.IacMax) || (result.ia1 < protect.IacMin) ||
|
||||
(result.ib1 > protect.IacMax) || (result.ib1 < protect.IacMin) ||
|
||||
(result.ic1 > protect.IacMax) || (result.ic1 < protect.IacMin) ) {
|
||||
faultNo = 22;
|
||||
state = STATE_SHUTDOWN;
|
||||
}
|
||||
// ïîíèæåíèå âûïðÿìëåííîãî íàïðÿæåíèÿ
|
||||
if ( udc1Nf < protect.UdcMin ) {
|
||||
if ( protect.tUdc1Min < protect.TudcMin ) {
|
||||
protect.tUdc1Min++;
|
||||
}
|
||||
else {
|
||||
faultNo = 30;
|
||||
state = STATE_SHUTDOWN;
|
||||
}
|
||||
}
|
||||
else {
|
||||
if ( protect.tUdc1Min > 0 )
|
||||
protect.tUdc1Min--;
|
||||
}
|
||||
} //if ( state == STATE_WORK )
|
||||
// ----------------------------------------------------------------
|
||||
if ( state != STATE_SHUTDOWN ) {
|
||||
// ïîâûøåíèå âûïðÿìëåííîãî íàïðÿæåíèÿ
|
||||
if ( udc1Nf > protect.UdcMax ) {
|
||||
faultNo = 24;
|
||||
state = STATE_SHUTDOWN;
|
||||
}
|
||||
// ïîâûøåíèå îáîðîòîâ
|
||||
if ( wm > protect.WmMax ) {
|
||||
if ( protect.tWmMax < protect.TwmMax ) {
|
||||
protect.tWmMax++;
|
||||
}
|
||||
else {
|
||||
faultNo = 32;
|
||||
state = STATE_SHUTDOWN;
|
||||
}
|
||||
}
|
||||
else {
|
||||
if ( protect.tWmMax > 0 )
|
||||
protect.tWmMax--;
|
||||
}
|
||||
// íåèñïðàâíîñòü èñòî÷íèêà ïèòàíèÿ +24 Â
|
||||
if ( DI_24V_SOURCE_FAULT == 1 ) {
|
||||
if ( protect.tDI24VSource < protect.Tdi24VSource ) {
|
||||
protect.tDI24VSource++;
|
||||
}
|
||||
else {
|
||||
faultNo = 7;
|
||||
state = STATE_SHUTDOWN;
|
||||
}
|
||||
}
|
||||
else {
|
||||
if ( protect.tDI24VSource > 0 ) {
|
||||
protect.tDI24VSource--;
|
||||
}
|
||||
}
|
||||
} //if ( state != STATE_SHUTDOWN )
|
||||
|
||||
|
||||
|
||||
|
||||
// Ðåæèì ðàáîòû INU
|
||||
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
switch ( state ) {
|
||||
// Àâàðèéíàÿ îñòàíîâêà
|
||||
//-------------------------------------------------------------
|
||||
case STATE_SHUTDOWN:
|
||||
stop_inu();
|
||||
// â ðåæ. STATE_SHUTDOWN âûâîäèìûå âåëè÷èíû äîëæíû îñòàâàòüñÿ
|
||||
// òàêèìè êàêèìè îíè áûëè â ìîìåíò ñðàáàò-èÿ çàùèòû
|
||||
if ( onceShutdown == 0 ) {
|
||||
onceShutdown = 1;
|
||||
snapshot_emergency();
|
||||
}
|
||||
// ïåðåõîä â ðåæèì STATE_STOP
|
||||
if ( mst.faultReset == 1 ) {
|
||||
// ÷òîáû íå ïóñòèòüñÿ ñ íåïðàâèëüíûìè ïàðàìåòðàìè
|
||||
testParamFaultNo = test_param();
|
||||
if ( testParamFaultNo == 0 )
|
||||
onceFaultReset = 1;
|
||||
else
|
||||
faultNo = 4;
|
||||
}
|
||||
if ( onceFaultReset == 1 ) {
|
||||
onceFaultReset = 0;
|
||||
state = STATE_STOP;
|
||||
faultNo = 0;
|
||||
onceShutdown = 0;
|
||||
// äëÿ çàùèò
|
||||
protect.tWmMax = 0;
|
||||
protect.tDI24VSource = 0;
|
||||
}
|
||||
break;//STATE_SHUTDOWN
|
||||
// Øòàòíàÿ îñòàíîâêà
|
||||
//-------------------------------------------------------------
|
||||
case STATE_STOP:
|
||||
stop_inu();
|
||||
// ïåðåõîä â ðåæèì STATE_WORK
|
||||
if ( (mst.start == 1) && (stopPause == 1) ) {
|
||||
state = STATE_WORK;
|
||||
onceUpr = 0;
|
||||
// äëÿ çàùèò
|
||||
protect.tUdc1Min = 0;
|
||||
}
|
||||
break;//STATE_STOP
|
||||
// Ðàáîòà
|
||||
//-------------------------------------------------------------
|
||||
case STATE_WORK:
|
||||
// ðåàëèçóåò àëãîðèòì óïðàâëåíèÿ
|
||||
upr();
|
||||
// ïåðåõîä â ðåæèì STATE_STOP
|
||||
if ( (mst.start == 0) && (inuWork == 2) ) {
|
||||
state = STATE_STOP;
|
||||
}
|
||||
break;//STATE_WORK
|
||||
} //switch ( state )
|
||||
|
||||
|
||||
|
||||
// service watchdog
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDKEY = 0x55;
|
||||
SysCtrlRegs.WDKEY = 0xAA;
|
||||
EDIS;
|
||||
|
||||
|
||||
// clear Interrupt Flag ADC Sequencer 1
|
||||
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
|
||||
// acknowledge PIE Interrupt
|
||||
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
|
||||
} //isr()
|
||||
|
||||
|
||||
|
||||
/* Óñòàíàâëèâàåò ôëàæîê, åñëè ïðîáûëè çàäàííîå âðåìÿ â âûêëþ÷åííîì
|
||||
ñîñòîÿíèè (÷òîáû ÃÝÄ ðàçìàãíèòèëñÿ ïåðåä ïîâòîðíûì ïóñêîì)
|
||||
(state -> stopPause) */
|
||||
void make_pause_before_rerun(void) {
|
||||
static unsigned short T = (unsigned short)(5.0/TY);
|
||||
static unsigned short t = 0;
|
||||
|
||||
if ( state == STATE_WORK ) {
|
||||
stopPause = 0;
|
||||
t = 0;
|
||||
}
|
||||
else {
|
||||
if ( t < T )
|
||||
t++;
|
||||
else
|
||||
stopPause = 1;
|
||||
}
|
||||
} //void make_pause_before_rerun(void)
|
||||
|
||||
|
||||
|
||||
// Âû÷èñëÿåò ÷àñòîòó âðàùåíèÿ (EQep2Regs.QPOSCNT -> wmNf, wm, out.wm)
|
||||
void sens_wm(void) {
|
||||
static short once = 0;
|
||||
static unsigned short qposmax;
|
||||
static unsigned short qepCnt;
|
||||
static unsigned short qepCntPrev = 0;
|
||||
static unsigned short QepCntDelMax = (unsigned short)(QEP_CNT_DEL_NOM*2.0);
|
||||
static short qepCntDel;
|
||||
|
||||
if ( once == 0 ) {
|
||||
once = 1;
|
||||
qposmax = (unsigned short)EQep2Regs.QPOSMAX;
|
||||
}
|
||||
|
||||
// âû÷èñëÿåì ñêîðîñòü ïî ïðèðàùåíèþ ñ÷¸ò÷èêà èìïóëüñîâ îò ÄÑ
|
||||
qepCnt = (unsigned short)EQep2Regs.QPOSCNT;
|
||||
if ( qepCnt + QepCntDelMax < qepCntPrev )
|
||||
qepCntDel = (short)(qposmax - qepCntPrev + qepCnt + 1);//overflow
|
||||
else if ( qepCntPrev + QepCntDelMax < qepCnt )
|
||||
qepCntDel = (short)(qepCnt - qposmax - qepCntPrev - 1);//underflow
|
||||
else
|
||||
qepCntDel = (short)(qepCnt - qepCntPrev);
|
||||
qepCntPrev = qepCnt;
|
||||
wmNf = (float)qepCntDel*GAIN_WM;//î.å.
|
||||
// ôèëüòðóåì
|
||||
wm += (wmNf - wm)*Kwm;
|
||||
out.wm += (wmNf - out.wm)*out.K;//äëÿ âûâîäà
|
||||
wmAbs = fabs(wm);
|
||||
} //void sens_wm(void)
|
||||
|
||||
|
||||
|
||||
// Çàïîìèíàåò âåëè÷èíû â ìîìåíò ñðàáàòûâàíèÿ çàùèòû
|
||||
void snapshot_emergency(void) {
|
||||
emerg.udc1 = udc1Nf;
|
||||
emerg.iac1 = iac1Nf;
|
||||
emerg.me = me;
|
||||
emerg.wm = wm;
|
||||
emerg.pm = pm;
|
||||
} //void snapshot_emergency(void)
|
||||
|
||||
|
||||
|
||||
// Ñíèìàåò èìïóëüñû óïðàâëåíèÿ ñ INU
|
||||
void stop_inu(void) {
|
||||
// forces a one-shot trip event
|
||||
EALLOW;
|
||||
EPwm1Regs.TZFRC.all = 0x0004;
|
||||
EPwm2Regs.TZFRC.all = 0x0004;
|
||||
EPwm3Regs.TZFRC.all = 0x0004;
|
||||
EPwm4Regs.TZFRC.all = 0x0004;
|
||||
EPwm5Regs.TZFRC.all = 0x0004;
|
||||
EPwm6Regs.TZFRC.all = 0x0004;
|
||||
#ifdef ML
|
||||
EPwm7Regs.TZFRC.all = 0x0004;
|
||||
EPwm8Regs.TZFRC.all = 0x0004;
|
||||
EPwm9Regs.TZFRC.all = 0x0004;
|
||||
EPwm10Regs.TZFRC.all = 0x0004;
|
||||
EPwm11Regs.TZFRC.all = 0x0004;
|
||||
EPwm12Regs.TZFRC.all = 0x0004;
|
||||
#endif
|
||||
EDIS;
|
||||
// íà âñÿêèé ñëó÷àé
|
||||
EPwm1Regs.CMPA.half.CMPA = 0;
|
||||
EPwm2Regs.CMPA.half.CMPA = 0;
|
||||
EPwm3Regs.CMPA.half.CMPA = 0;
|
||||
EPwm4Regs.CMPA.half.CMPA = 0;
|
||||
EPwm5Regs.CMPA.half.CMPA = 0;
|
||||
EPwm6Regs.CMPA.half.CMPA = 0;
|
||||
#ifdef ML
|
||||
EPwm7Regs.CMPA.half.CMPA = 0;
|
||||
EPwm8Regs.CMPA.half.CMPA = 0;
|
||||
EPwm9Regs.CMPA.half.CMPA = 0;
|
||||
EPwm10Regs.CMPA.half.CMPA = 0;
|
||||
EPwm11Regs.CMPA.half.CMPA = 0;
|
||||
EPwm12Regs.CMPA.half.CMPA = 0;
|
||||
#endif
|
||||
// äëÿ ïåðåäà÷è íà ÂÓ
|
||||
inuWork = 0;
|
||||
// äëÿ âû÷èñëåíèÿ meNf
|
||||
psi = 0;
|
||||
} //void stop_inu(void)
|
||||
70
Inu_im_1wnd_3lvl/Inu/isr.h
Normal file
70
Inu_im_1wnd_3lvl/Inu/isr.h
Normal file
@@ -0,0 +1,70 @@
|
||||
#ifndef ISR
|
||||
#define ISR
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â isr.c (begin)
|
||||
//#########################################################################
|
||||
struct Offset offset;
|
||||
volatile struct Result result;
|
||||
volatile short state;
|
||||
volatile short faultNo;
|
||||
volatile struct Out out;
|
||||
// Udc
|
||||
float Kudc;
|
||||
volatile float udc1Nf;
|
||||
volatile float udc1;
|
||||
volatile float udc2Nf;
|
||||
volatile float udc2;
|
||||
// Iac
|
||||
volatile float ia1Nf;
|
||||
volatile float ib1Nf;
|
||||
volatile float ix1;
|
||||
volatile float iy1;
|
||||
volatile float iac1Nf;
|
||||
volatile float ia2Nf;
|
||||
volatile float ib2Nf;
|
||||
volatile float ix2;
|
||||
volatile float iy2;
|
||||
volatile float iac2Nf;
|
||||
// Wm
|
||||
float Kwm;
|
||||
volatile float wmNf;
|
||||
volatile float wm;
|
||||
volatile float wmAbs;
|
||||
// Me
|
||||
volatile float kMe;
|
||||
float KmeCorr;
|
||||
float Kme;
|
||||
volatile float meNf;
|
||||
volatile float me;
|
||||
// Pm
|
||||
volatile float pm;
|
||||
// çàùèòû
|
||||
struct Protect protect;
|
||||
volatile struct Emerg emerg;
|
||||
short csmSuccess;
|
||||
// óïðàâëÿþùàÿ ëîãèêà
|
||||
volatile short onceShutdown;
|
||||
volatile short testParamFaultNo;
|
||||
volatile short onceFaultReset;
|
||||
volatile short stopPause;
|
||||
volatile short inuWork;
|
||||
// îáìåí
|
||||
struct Mst mst;
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â isr.c (end)
|
||||
|
||||
|
||||
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â isr.c (begin)
|
||||
//#########################################################################
|
||||
extern struct SgmPar sgmPar;
|
||||
extern unsigned short param[];
|
||||
extern volatile short onceUpr;
|
||||
extern volatile float psi;
|
||||
extern float iq1;
|
||||
extern float iq2;
|
||||
extern struct Rp rp;
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â isr.c (end)
|
||||
#endif //ISR
|
||||
136
Inu_im_1wnd_3lvl/Inu/main.c
Normal file
136
Inu_im_1wnd_3lvl/Inu/main.c
Normal file
@@ -0,0 +1,136 @@
|
||||
/**************************************************************************
|
||||
Description: Ïðîãðàììà óïðàâëåíèÿ INU.
|
||||
Âûçûâàåò ï/ï èíèöèàëèçàöèè ïðîöåññîðà è ï/ï îáìåíà.
|
||||
|
||||
Àâòîð: Óëèòîâñêèé Ä.È.
|
||||
Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.10.05
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
#include "def.h"
|
||||
#include "main.h"
|
||||
|
||||
|
||||
void control_processor_led(void);
|
||||
void talk_with_desk(void);
|
||||
void talk_with_mst(void);
|
||||
void write_eeprom(void);
|
||||
extern void detcoeff(void);
|
||||
extern void init28335(void);
|
||||
|
||||
|
||||
#ifndef ML
|
||||
void main(void) {
|
||||
// disable the watchdog
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDCR = 0x0068;
|
||||
EDIS;
|
||||
|
||||
// èíèöèàëèçàöèÿ ïðîöåññîðà
|
||||
init28335();
|
||||
|
||||
// èíèöèàëèçàöèÿ ïðîãðàììû
|
||||
detcoeff();
|
||||
|
||||
// re-enable the watchdog
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDCR = 0x00A8;
|
||||
// ... clear the WD counter
|
||||
SysCtrlRegs.WDKEY = 0x55;
|
||||
SysCtrlRegs.WDKEY = 0xAA;
|
||||
EDIS;
|
||||
|
||||
// clear Interrupt Flag ADC Sequencer 1
|
||||
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
|
||||
// clear PIEIFR1 register
|
||||
PieCtrlRegs.PIEIFR1.all = 0;
|
||||
|
||||
// before we can start we have to enable interrupt mask in the PIE unit
|
||||
PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
|
||||
// core line 1 (INT1)
|
||||
IER |= M_INT1;
|
||||
// enable global interrupts and higher priority real-time debug events
|
||||
EINT;
|
||||
ERTM;
|
||||
|
||||
// çàïóñêàåì òàéìåðû (up-down-count mode)
|
||||
EPwm1Regs.TBCTL.bit.CTRMODE = 2;
|
||||
EPwm2Regs.TBCTL.bit.CTRMODE = 2;
|
||||
EPwm3Regs.TBCTL.bit.CTRMODE = 2;
|
||||
EPwm4Regs.TBCTL.bit.CTRMODE = 2;
|
||||
EPwm5Regs.TBCTL.bit.CTRMODE = 2;
|
||||
EPwm6Regs.TBCTL.bit.CTRMODE = 2;
|
||||
|
||||
// loop forever
|
||||
while(1) {
|
||||
// îáìåí ñ ÂÓ
|
||||
// ( -> mst)
|
||||
talk_with_mst();
|
||||
// îáìåí ñ ÏÓ
|
||||
// ( -> param[], eprom.writeRequestNumber)
|
||||
talk_with_desk();
|
||||
// çàïèñü â EEPROM
|
||||
// (param[], eprom.writeRequestNumber -> eprom.writeRequestNumber)
|
||||
if ( eprom.writeRequestNumber > 0 ) {
|
||||
write_eeprom();
|
||||
}
|
||||
|
||||
// óïðàâëÿåì ñâåòîäèîäàìè íà ïðîöåññîðíîé ïëàòå
|
||||
control_processor_led();
|
||||
} //while(1)
|
||||
} //void main(void)
|
||||
|
||||
|
||||
|
||||
// Óïðàâëÿåò ñâåòîäèîäàìè íà ïðîöåññîðíîé ïëàòå
|
||||
void control_processor_led(void) {
|
||||
static unsigned short Tled = (unsigned short)(0.5/TY);
|
||||
static unsigned short tLed = 0;
|
||||
|
||||
if ( tLed < Tled ) {
|
||||
tLed++;
|
||||
}
|
||||
else {
|
||||
tLed = 1;
|
||||
// â àâàðèéíîì ðåæ. ìîðãàåì êðàñíûì ñâåòîäèîäîì
|
||||
if ( state == STATE_SHUTDOWN ) {
|
||||
LED_GREEN1_OFF;
|
||||
LED_GREEN2_OFF;
|
||||
LED_RED_TOGGLE;
|
||||
}
|
||||
// â ðåæ. îñòàíîâêè ìîðãàåì ïåðâûì çåë¸íûì ñâåòîäèîäîì
|
||||
else if ( state == STATE_STOP ) {
|
||||
LED_GREEN1_TOGGLE;
|
||||
LED_GREEN2_OFF;
|
||||
LED_RED_OFF;
|
||||
}
|
||||
// â ðàáî÷åì ðåæ. ìîðãàåì âòîðûì çåë¸íûì ñâåòîäèîäîì
|
||||
else {
|
||||
LED_GREEN1_OFF;
|
||||
LED_GREEN2_TOGGLE;
|
||||
LED_RED_OFF;
|
||||
}
|
||||
}
|
||||
} //void control_processor_led(void)
|
||||
|
||||
|
||||
|
||||
// Ïîëó÷àåò ïàðàìåòðû ñ ÏÓ
|
||||
// ( -> param[], eprom.writeRequestNumber)
|
||||
void talk_with_desk(void) {
|
||||
}
|
||||
|
||||
|
||||
|
||||
// Ïîëó÷àåò êîìàíäû ñ ÂÓ
|
||||
// ( -> mst)
|
||||
void talk_with_mst(void) {
|
||||
}
|
||||
|
||||
|
||||
|
||||
// Çàïèñûâàåò ïàðàìåòðû â EEPROM
|
||||
// (param[], eprom.writeRequestNumber -> eprom.writeRequestNumber)
|
||||
void write_eeprom(void) {
|
||||
}
|
||||
#endif //ML
|
||||
17
Inu_im_1wnd_3lvl/Inu/main.h
Normal file
17
Inu_im_1wnd_3lvl/Inu/main.h
Normal file
@@ -0,0 +1,17 @@
|
||||
#ifndef MAIN
|
||||
#define MAIN
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â main.c (begin)
|
||||
//#########################################################################
|
||||
struct Eprom eprom;
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â main.c (end)
|
||||
|
||||
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â main.c (begin)
|
||||
//#########################################################################
|
||||
extern volatile short state;
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â main.c (end)
|
||||
#endif //MAIN
|
||||
426
Inu_im_1wnd_3lvl/Inu/param.c
Normal file
426
Inu_im_1wnd_3lvl/Inu/param.c
Normal file
@@ -0,0 +1,426 @@
|
||||
/**************************************************************************
|
||||
Description: Ôóíêöèè äëÿ ïðè¸ìà è âûäà÷è ïàðàìåòðîâ.
|
||||
|
||||
Àâòîð: Óëèòîâñêèé Ä.È.
|
||||
Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.11.08
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
#include "def.h"
|
||||
#include "param.h"
|
||||
|
||||
|
||||
#pragma CODE_SECTION(input_param, "ramfuncs");
|
||||
#pragma CODE_SECTION(output_param, "ramfuncs");
|
||||
|
||||
|
||||
extern short test_param(void);
|
||||
extern void process_sgm_parameters(void);
|
||||
|
||||
|
||||
// Èçìåíÿåò çíà÷åíèå ïàðàìåòðà
|
||||
void input_param(unsigned short num, unsigned short val) {
|
||||
switch ( num ) {
|
||||
case 180://rf.PsiZ, %*10 îò PSI_BAZ
|
||||
if ( (val <= 2000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
rf.PsiZ = (float)val*0.001;//%*10 -> o.e.
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 200://offset.Ia1, åä. ÀÖÏ
|
||||
if ( (val >= 1748) && (val <= 4096) && (val != param[num]) ) {
|
||||
offset.Ia1 = param[num] = val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 201://offset.Ib1, åä. ÀÖÏ
|
||||
if ( (val >= 1748) && (val <= 4096) && (val != param[num]) ) {
|
||||
offset.Ib1 = param[num] = val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 202://offset.Ic1, åä. ÀÖÏ
|
||||
if ( (val >= 1748) && (val <= 4096) && (val != param[num]) ) {
|
||||
offset.Ic1 = param[num] = val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 203://offset.Udc1, åä. ÀÖÏ
|
||||
if ( (val >= 1748) && (val <= 4096) && (val != param[num]) ) {
|
||||
offset.Udc1 = param[num] = val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 206://offset.Ia2, åä. ÀÖÏ
|
||||
if ( (val >= 1748) && (val <= 4096) && (val != param[num]) ) {
|
||||
offset.Ia2 = param[num] = val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 207://offset.Ib2, åä. ÀÖÏ
|
||||
if ( (val >= 1748) && (val <= 4096) && (val != param[num]) ) {
|
||||
offset.Ib2 = param[num] = val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 208://offset.Ic2, åä. ÀÖÏ
|
||||
if ( (val >= 1748) && (val <= 4096) && (val != param[num]) ) {
|
||||
offset.Ic2 = param[num] = val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 209://offset.Udc2, åä. ÀÖÏ
|
||||
if ( (val >= 1748) && (val <= 4096) && (val != param[num]) ) {
|
||||
offset.Udc2 = param[num] = val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 210://cc.Kp, %
|
||||
if ( (val <= 5000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
cc.Kp = (float)val*cc.KpOrig;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 211://cc.Ki, %
|
||||
if ( (val <= 5000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
cc.Ki = (float)val*cc.KiOrig;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 212://cf.Kp, %
|
||||
if ( (val <= 5000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
cf.Kp = (float)val*cf.KpOrig;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 213://cf.Ki, %
|
||||
if ( (val <= 5000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
cf.Ki = (float)val*cf.KiOrig;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 214://csp.Kp, %
|
||||
if ( (val <= 5000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
csp.Kp = (float)val*csp.KpOrig;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 215://csp.Ki, %
|
||||
if ( (val <= 5000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
csp.Ki = (float)val*csp.KiOrig;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 220://protect.IacMax, % îò IAC_SENS_MAX
|
||||
if ( (val <= 99) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
protect.IacMax = (short)(2047.*(float)val*0.01);//% -> åä. ÀÖÏ
|
||||
protect.IacMin = -protect.IacMax;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 221://protect.UdcMax, % îò U_NOM
|
||||
if ( (val <= 136) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
protect.UdcMax = (float)val*0.01;//% -> o.e.
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 222://IzLim, % îò I_BAZ
|
||||
if ( (val <= 200) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
IzLim = (float)val*0.01;//% -> o.e.
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 223://cf.IdLim, % îò I_BAZ
|
||||
if ( (val <= 200) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
cf.IdLim = (float)val*0.01;//% -> o.e.
|
||||
cf.IdLimNeg = cf.IdLim*(-0.4);
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 224://csp.IqLim, % îò I_BAZ
|
||||
if ( (val <= 200) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
csp.IqLim = (float)val*0.01;//% -> o.e.
|
||||
csp.IqLimNeg = -csp.IqLim;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 225://protect.UdcMin, % îò U_NOM
|
||||
if ( (val <= 110) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
protect.UdcMin = (float)val*0.01;//% -> o.e.
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 226://protect.WmMax, % îò N_NOM
|
||||
if ( (val <= 200) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
protect.WmMax = (float)val*0.01;//% -> o.e.
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 228://rf.WmNomPsi, % îò N_NOM
|
||||
if ( (val <= 200) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
rf.WmNomPsi = (float)val*0.01;//% -> o.e.
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 229://rf.YlimPsi, % îò Y_LIM
|
||||
if ( (val <= 101) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
rf.YlimPsi = (float)val*0.01*Y_LIM;//% -> åä. ñ÷¸ò÷èêà òàéìåðà
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 231://protect.TudcMin, ìñ
|
||||
if ( (val >= 1) && (val <= 8500) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
protect.TudcMin = (unsigned short)((float)val*0.001/TY);
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 233://protect.TwmMax, ìñ
|
||||
if ( (val >= 1) && (val <= 8500) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
protect.TwmMax = (unsigned short)((float)val*0.001/TY);
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 244://rs.WlimIncr, ìñ
|
||||
if ( (val >= 1) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
// èçì. íà 1.0 çà ñòîëüêî-òî ìñ
|
||||
rs.WlimIncr = 1.0*TY*DECIM_PSI_WM_PM/((float)val*0.001);
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 245://csp.IlimIncr, ìñ
|
||||
if ( (val >= 1) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
// èçì. íà I_BAZ çà ñòîëüêî-òî ìñ
|
||||
csp.IlimIncr = 1.0*TY*DECIM_PSI_WM_PM/((float)val*0.001);
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 248://rp.PlimIncr, ìñ
|
||||
if ( (val >= 1) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
// èçì. íà 1.0 çà ñòîëüêî-òî ìñ
|
||||
rp.PlimIncr = 1.0*TY*DECIM_PSI_WM_PM/((float)val*0.001);
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 269://KmeCorr, %*100
|
||||
if ( (val >= 5000) && (val <= 20000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
KmeCorr = (float)val*0.0001;//%*100 -> o.e.
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 285://Kudc, ìñ*10
|
||||
if ( (val >= 1) && (val <= 20000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
Kudc = (TY*10000.)/(float)val;
|
||||
if ( Kudc > 1.0 )
|
||||
Kudc = 1.0;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 286://Kwm, ìñ*10
|
||||
if ( (val >= 1) && (val <= 20000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
Kwm = (TY*10000.)/(float)val;
|
||||
if ( Kwm > 1.0 )
|
||||
Kwm = 1.0;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 288://rs.Kwmz, ìñ
|
||||
if ( (val >= 1) && (val <= 20000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
rs.Kwmz = (TY*DECIM_PSI_WM_PM*1000.)/(float)val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 289://rf.Kpsiz, ìñ
|
||||
if ( (val >= 1) && (val <= 20000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
rf.Kpsiz = (TY*DECIM_PSI_WM_PM*1000.)/(float)val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 290://Kme, ìñ
|
||||
if ( (val >= 1) && (val <= 20000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
Kme = (TY*1000.)/(float)val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 292://rp.Kpmz, ìñ
|
||||
if ( (val >= 1) && (val <= 20000) && (val != param[num]) ) {
|
||||
param[num] = val;
|
||||
rp.Kpmz = (TY*DECIM_PSI_WM_PM*1000.)/(float)val;
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 303://sgmPar.Rs, ìêÎì
|
||||
if ( val != param[num] ) {
|
||||
param[num] = val;
|
||||
sgmPar.Rs = (float)val*1e-6;//ìêÎì -> Îì
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 304://sgmPar.Lls, ìêÃí*10
|
||||
if ( val != param[num] ) {
|
||||
param[num] = val;
|
||||
sgmPar.Lls = (float)val*1e-7;//ìêÃí*10 -> Ãí
|
||||
process_sgm_parameters();
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 305://sgmPar.Rr, ìêÎì
|
||||
if ( val != param[num] ) {
|
||||
param[num] = val;
|
||||
sgmPar.Rr = (float)val*1e-6;//ìêÎì -> Îì
|
||||
process_sgm_parameters();
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 306://sgmPar.Llr, ìêÃí*10
|
||||
if ( val != param[num] ) {
|
||||
param[num] = val;
|
||||
sgmPar.Llr = (float)val*1e-7;//ìêÃí*10 -> Ãí
|
||||
process_sgm_parameters();
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
case 307://sgmPar.Lm, ìêÃí
|
||||
if ( val != param[num] ) {
|
||||
param[num] = val;
|
||||
sgmPar.Lm = (float)val*1e-6;//ìêÃí -> Ãí
|
||||
process_sgm_parameters();
|
||||
eprom.writeRequestNumber += 1;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if ( num < PAR_NUMBER ) {
|
||||
param[num] = val;
|
||||
}
|
||||
break;
|
||||
} //switch ( num )
|
||||
} //void input_param(unsigned short num, unsigned short val)
|
||||
|
||||
|
||||
|
||||
// Âûäà¸ò çíà÷åíèå ïàðàìåòðà
|
||||
unsigned short output_param(unsigned short num) {
|
||||
static unsigned short output;
|
||||
|
||||
switch ( num ) {
|
||||
case 1: //udc1, o.e. -> o.e.*CONTROLLER_GAIN
|
||||
if ( state == STATE_SHUTDOWN ) {
|
||||
output = (unsigned short)(emerg.udc1*CONTROLLER_GAIN);
|
||||
}
|
||||
else {
|
||||
output = (unsigned short)(out.udc1*CONTROLLER_GAIN);
|
||||
}
|
||||
break;
|
||||
case 2: //udc2, o.e. -> o.e.*CONTROLLER_GAIN
|
||||
if ( state == STATE_SHUTDOWN ) {
|
||||
output = (unsigned short)(emerg.udc2*CONTROLLER_GAIN);
|
||||
}
|
||||
else {
|
||||
output = (unsigned short)(out.udc2*CONTROLLER_GAIN);
|
||||
}
|
||||
break;
|
||||
case 5: //iac1, o.e. -> o.e.*CONTROLLER_GAIN
|
||||
if ( state == STATE_SHUTDOWN ) {
|
||||
output = (unsigned short)(emerg.iac1*CONTROLLER_GAIN);
|
||||
}
|
||||
else {
|
||||
output = (unsigned short)(out.iac1*CONTROLLER_GAIN);
|
||||
}
|
||||
break;
|
||||
case 6: //iac2, o.e. -> o.e.*CONTROLLER_GAIN
|
||||
if ( state == STATE_SHUTDOWN ) {
|
||||
output = (unsigned short)(emerg.iac2*CONTROLLER_GAIN);
|
||||
}
|
||||
else {
|
||||
output = (unsigned short)(out.iac2*CONTROLLER_GAIN);
|
||||
}
|
||||
break;
|
||||
case 7: //me, o.e. -> (o.e. + CONTROLLER_BIAS)*CONTROLLER_GAIN
|
||||
if ( state == STATE_SHUTDOWN ) {
|
||||
if ( emerg.me > CONTROLLER_BIAS )
|
||||
output = (unsigned short)((CONTROLLER_BIAS + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else if ( emerg.me > -CONTROLLER_BIAS )
|
||||
output = (unsigned short)((emerg.me + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else
|
||||
output = 0;
|
||||
}
|
||||
else {
|
||||
if ( out.me > CONTROLLER_BIAS )
|
||||
output = (unsigned short)((CONTROLLER_BIAS + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else if ( out.me > -CONTROLLER_BIAS )
|
||||
output = (unsigned short)((out.me + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else
|
||||
output = 0;
|
||||
}
|
||||
break;
|
||||
case 8: //nm, o.e. -> (o.e. + CONTROLLER_BIAS)*CONTROLLER_GAIN
|
||||
if ( state == STATE_SHUTDOWN ) {
|
||||
if ( emerg.wm > CONTROLLER_BIAS )
|
||||
output = (unsigned short)((CONTROLLER_BIAS + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else if ( emerg.wm > -CONTROLLER_BIAS )
|
||||
output = (unsigned short)((emerg.wm + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else
|
||||
output = 0;
|
||||
}
|
||||
else {
|
||||
if ( out.wm > CONTROLLER_BIAS )
|
||||
output = (unsigned short)((CONTROLLER_BIAS + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else if ( out.wm > -CONTROLLER_BIAS )
|
||||
output = (unsigned short)((out.wm + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else
|
||||
output = 0;
|
||||
}
|
||||
break;
|
||||
case 9: //pm, o.e. -> (o.e. + CONTROLLER_BIAS)*CONTROLLER_GAIN
|
||||
if ( state == STATE_SHUTDOWN ) {
|
||||
if ( emerg.pm > CONTROLLER_BIAS )
|
||||
output = (unsigned short)((CONTROLLER_BIAS + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else if ( emerg.pm > -CONTROLLER_BIAS )
|
||||
output = (unsigned short)((emerg.pm + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else
|
||||
output = 0;
|
||||
}
|
||||
else {
|
||||
if ( out.pm > CONTROLLER_BIAS )
|
||||
output = (unsigned short)((CONTROLLER_BIAS + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else if ( out.pm > -CONTROLLER_BIAS )
|
||||
output = (unsigned short)((out.pm + CONTROLLER_BIAS)*CONTROLLER_GAIN);
|
||||
else
|
||||
output = 0;
|
||||
}
|
||||
break;
|
||||
case 10: //compound
|
||||
output = faultNo + (inuWork<<7);
|
||||
break;
|
||||
default:
|
||||
output = param[num];
|
||||
break;
|
||||
} //switch ( num )
|
||||
return output;
|
||||
} //unsigned short output_param(unsigned short num)
|
||||
41
Inu_im_1wnd_3lvl/Inu/param.h
Normal file
41
Inu_im_1wnd_3lvl/Inu/param.h
Normal file
@@ -0,0 +1,41 @@
|
||||
#ifndef PARAM
|
||||
#define PARAM
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â param.c (begin)
|
||||
//#########################################################################
|
||||
unsigned short param[PAR_NUMBER];
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â param.c (end)
|
||||
|
||||
|
||||
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â param.c (begin)
|
||||
//#########################################################################
|
||||
extern volatile short state;
|
||||
extern volatile short faultNo;
|
||||
extern short onceFaultReset;
|
||||
extern struct SgmPar sgmPar;
|
||||
extern struct Offset offset;
|
||||
extern float Kudc;
|
||||
extern float Kwm;
|
||||
extern short testParamFaultNo;
|
||||
extern float IzLim;
|
||||
extern float Kme;
|
||||
extern struct Protect protect;
|
||||
extern float KmeCorr;
|
||||
extern volatile struct Out out;
|
||||
extern volatile struct Emerg emerg;
|
||||
extern struct Rf rf;
|
||||
extern struct Rs rs;
|
||||
extern struct Rp rp;
|
||||
extern struct Cf cf;
|
||||
extern struct Csp csp;
|
||||
extern struct Cc cc;
|
||||
// äëÿ ïåðåäà÷è íà ÂÓ
|
||||
extern volatile short inuWork;
|
||||
// äëÿ ðàáîòû ñ EEPROM
|
||||
extern struct Eprom eprom;
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â param.c (end)
|
||||
#endif //PARAM
|
||||
734
Inu_im_1wnd_3lvl/Inu/upr.c
Normal file
734
Inu_im_1wnd_3lvl/Inu/upr.c
Normal file
@@ -0,0 +1,734 @@
|
||||
/**************************************************************************
|
||||
Description: Ôóíêöèÿ ðåàëèçóåò àëãîðèòì óïðàâëåíèÿ INU
|
||||
(îòðàáîòêà N è P).
|
||||
|
||||
Àâòîð: Óëèòîâñêèé Ä.È.
|
||||
Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.11.08
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
#include "def.h"
|
||||
#include "upr.h"
|
||||
#include "estimate.h"
|
||||
|
||||
|
||||
#pragma CODE_SECTION(control_current, "ramfuncs");
|
||||
#pragma CODE_SECTION(control_flux, "ramfuncs");
|
||||
#pragma CODE_SECTION(control_speed_power, "ramfuncs");
|
||||
#pragma CODE_SECTION(indirect_vector_control, "ramfuncs");
|
||||
#pragma CODE_SECTION(ipark, "ramfuncs");
|
||||
#pragma CODE_SECTION(limit_current, "ramfuncs2");
|
||||
#pragma CODE_SECTION(pwm, "ramfuncs2");
|
||||
#pragma CODE_SECTION(reference_flux, "ramfuncs");
|
||||
#pragma CODE_SECTION(reference_power, "ramfuncs");
|
||||
#pragma CODE_SECTION(reference_speed, "ramfuncs");
|
||||
#pragma CODE_SECTION(select_feedback, "ramfuncs");
|
||||
#pragma CODE_SECTION(upr, "ramfuncs");
|
||||
|
||||
|
||||
void control_current(void);
|
||||
void control_flux(void);
|
||||
void control_speed_power(void);
|
||||
void indirect_vector_control(void);
|
||||
void ipark(void);
|
||||
void limit_current(void);
|
||||
void pwm(float ya, float yb, float yc);
|
||||
void reference_flux(void);
|
||||
void reference_power(void);
|
||||
void reference_speed(void);
|
||||
void select_feedback(void);
|
||||
|
||||
|
||||
void upr(void) {
|
||||
static float yAux1;
|
||||
static float yAux2;
|
||||
static float ya;
|
||||
static float yb;
|
||||
static float yc;
|
||||
static short decim_psi_wm_pm;
|
||||
static Estimate_Test_t step;
|
||||
|
||||
if ( onceUpr == 0 ) {
|
||||
estimate_init();
|
||||
onceUpr = 1;
|
||||
decim_psi_wm_pm = (short)DECIM_PSI_WM_PM;
|
||||
psi = 0;
|
||||
rf.once = 0;
|
||||
rs.once = 0;
|
||||
rp.once = 0;
|
||||
cf.once = 0;
|
||||
csp.once = 0;
|
||||
ivc.once = 0;
|
||||
cc.once = 0;
|
||||
estimate_start(ESTIMATE_TEST_RR_L);
|
||||
}
|
||||
|
||||
// âíåøíèå êîíòóðû ðåãóëèðîâàíèÿ (ïî ïîòîêó, îáîðîòàì è ìîùíîñòè)
|
||||
// íå äîëæíû áûòü òàêèìè æå áûñòðûìè êàê âíóòðåííèå (ïî òîêó) (?)
|
||||
if ( decim_psi_wm_pm < (short)DECIM_PSI_WM_PM ) {
|
||||
decim_psi_wm_pm++;
|
||||
}
|
||||
else {
|
||||
decim_psi_wm_pm = 1;
|
||||
// Èçìåðåíèå Rr è Lk: ñèíóñ ïî Iq
|
||||
|
||||
estimate_process(cc.yd1, cc.yq1, id1, iq1, TY * DECIM_PSI_WM_PM,
|
||||
&idZ, &iqZ, NULL);
|
||||
|
||||
//// çàäàííîå ïîòîêîñöåïëåíèå
|
||||
//// (rf.PsiZ -> rf.psiZ, rf.pPsiZ)
|
||||
//reference_flux();
|
||||
|
||||
//// çàäàííàÿ ñêîðîñòü
|
||||
//// (mst.wmZz, mst.wmLim -> rs.wmZ, rs.pWmZ)
|
||||
//reference_speed();
|
||||
|
||||
//// çàäàííàÿ ìîùíîñòü
|
||||
//// (mst.pmZz, mst.pmLim -> rp.pmZ)
|
||||
//reference_power();
|
||||
|
||||
//// çàäàííûé òîê (idZ, iqZ)
|
||||
//// ... ðåãóëÿòîð ïîòîêîñöåïëåíèÿ
|
||||
//// (rf.psiZ, psi, rf.pPsiZ, cf.IdLim, cf.IdLimNeg -> idZ)
|
||||
//control_flux();
|
||||
//// ... ðåãóëÿòîðû ñêîðîñòè è ìîùíîñòè
|
||||
//// (rs.wmZ, wm, rs.pWmZ, rp.pmZ, mst.wmLim, mst.pmLim, csp.IqLim,
|
||||
//// csp.IqLimNeg -> iqZ, inuWork)
|
||||
//control_speed_power();
|
||||
//// ... îãðàíè÷åíèå ïîëíîãî òîêà
|
||||
//// (idZ, iqZ, IzLim -> idZ, iqZ, csp.iqLimFlag)
|
||||
//limit_current();
|
||||
} //decim_psi_wm_pm
|
||||
|
||||
// indirect vector control
|
||||
// (wmNf, wm, ix1, iy1, ix2, iy2 -> ivc.ws, ivc.sinTheta, ivc.cosTheta,
|
||||
// ivc.id1, ivc.iq1, ivc.id2, ivc.iq2, ivc.psi)
|
||||
indirect_vector_control();
|
||||
|
||||
// âûáîð ñèãíàëîâ î.ñ.
|
||||
// (... -> ws, sinTheta, cosTheta, id1, iq1, id2, iq2, psi)
|
||||
select_feedback();
|
||||
|
||||
// ðåãóëÿòîðû òîêà
|
||||
// (idZ, iqZ, id1, iq1, id2, iq2, ws, wm, psi ->
|
||||
// -> cc.yd1, cc.yq1, cc.yd2, cc.yq2)
|
||||
control_current();
|
||||
|
||||
// ïåðåâîä ñèãíàëîâ óïðàâëåíèÿ èç ñ.ê. d-q â ñ.ê. x-y
|
||||
// (cc.yd1, cc.yq1, cc.yd2, cc.yq2, sinTheta, cosTheta, ws ->
|
||||
// -> ip.yx1, ip.yy1, ip.yx2, ip.yy2)
|
||||
ipark();
|
||||
|
||||
// ØÈÌ
|
||||
// (ip.yx1, ip.yy1, ip.yx2, ip.yy2 ->
|
||||
// -> EPwm1Regs.CMPA.half.CMPA, EPwm2Regs.CMPA.half.CMPA,
|
||||
// EPwm3Regs.CMPA.half.CMPA, EPwm4Regs.CMPA.half.CMPA,
|
||||
// EPwm5Regs.CMPA.half.CMPA, EPwm6Regs.CMPA.half.CMPA,
|
||||
// EPwm7Regs.CMPA.half.CMPA, EPwm8Regs.CMPA.half.CMPA,
|
||||
// EPwm9Regs.CMPA.half.CMPA, EPwm10Regs.CMPA.half.CMPA,
|
||||
// EPwm11Regs.CMPA.half.CMPA, EPwm12Regs.CMPA.half.CMPA)
|
||||
|
||||
|
||||
|
||||
// ïåðåâîäèì èç ñ.ê. x-y â ñ.ê. a-b-c
|
||||
yAux1 = ip.yx1 * (-0.5 * ISQRT3);
|
||||
yAux2 = ip.yy1 * 0.5;
|
||||
ya = ip.yx1 * ISQRT3;
|
||||
yb = yAux1 + yAux2;
|
||||
yc = yAux1 - yAux2;
|
||||
pwm(ya, yb, yc);
|
||||
} //void upr(void)
|
||||
|
||||
|
||||
|
||||
// Ðåãóëèðóåò òîê
|
||||
// (idZ, iqZ, id1, iq1, id2, iq2, ws, wm, psi ->
|
||||
// -> cc.yd1, cc.yq1, cc.yd2, cc.yq2)
|
||||
void control_current(void) {
|
||||
if ( cc.once == 0 ) {
|
||||
cc.once = 1;
|
||||
cc.y1LimFlag = 0;
|
||||
cc.yd1I = 0;
|
||||
cc.yq1I = 0;
|
||||
cc.yd1 = 0;
|
||||
cc.yq1 = 0;
|
||||
// äëÿ ñîêðàùåíèÿ âû÷èñëåíèé
|
||||
cc.K1 = sgmPar.SigmaLs*I_BAZ*WE_BAZ*U_2_Y;
|
||||
cc.K2 = sgmPar.Rr*sgmPar.Lm/(sgmPar.Lr*sgmPar.Lr)*PSI_BAZ*U_2_Y;
|
||||
cc.K3 = sgmPar.Kl*PSI_BAZ*WE_BAZ*U_2_Y;
|
||||
}
|
||||
|
||||
// äëÿ ñîêðàùåíèÿ âû÷èñëåíèé
|
||||
cc.Xyff = ws*cc.K1;
|
||||
cc.yffAux2 = psi*cc.K2;
|
||||
cc.yffAux3 = psi*wm*cc.K3;
|
||||
|
||||
// ðåãóëÿòîð Id1
|
||||
cc.del = idZ - id1;
|
||||
cc.yd1P = cc.del*cc.Kp;
|
||||
if ( (cc.y1LimFlag == 0) || (cc.yd1*cc.del < 0) )
|
||||
cc.yd1I += cc.del*cc.Ki;
|
||||
cc.yd1FF = -iq1*cc.Xyff - cc.yffAux2;
|
||||
cc.yd1 = cc.yd1P + cc.yd1I + cc.yd1FF;
|
||||
// ðåãóëÿòîð Iq1
|
||||
cc.del = iqZ - iq1;
|
||||
cc.yq1P = cc.del*cc.Kp;
|
||||
if ( (cc.y1LimFlag == 0) || (cc.yq1*cc.del < 0) )
|
||||
cc.yq1I += cc.del*cc.Ki;
|
||||
cc.yq1FF = id1*cc.Xyff + cc.yffAux3;
|
||||
if ( estimate_get_step() == ESTIMATE_TEST_LM ) {
|
||||
cc.yd1FF = 0;
|
||||
cc.yq1FF = 0;
|
||||
}
|
||||
cc.yq1 = cc.yq1P + cc.yq1I + cc.yq1FF;
|
||||
// îãðàíè÷åíèå
|
||||
cc.y1 = sqrt(cc.yd1*cc.yd1 + cc.yq1*cc.yq1);
|
||||
if ( cc.y1 > Y_LIM ) {
|
||||
cc.kYlim = Y_LIM/cc.y1;
|
||||
cc.yd1 *= cc.kYlim;
|
||||
cc.yq1 *= cc.kYlim;
|
||||
cc.y1LimFlag = 1;
|
||||
}
|
||||
else {
|
||||
cc.y1LimFlag = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// Ðåãóëèðóåò ïîòîêîñöåïëåíèå
|
||||
// (rf.psiZ, psi, rf.pPsiZ, cf.IdLim, cf.IdLimNeg -> idZ)
|
||||
void control_flux(void) {
|
||||
if ( cf.once == 0 ) {
|
||||
cf.once = 1;
|
||||
cf.idLimFlag = 0;
|
||||
cf.idI = 0;
|
||||
idZ = 0;
|
||||
}
|
||||
|
||||
// ðåãóëÿòîð Psi
|
||||
cf.del = rf.psiZ - psi;
|
||||
cf.idP = cf.del*cf.Kp;
|
||||
if ( (cf.idLimFlag == 0) || (idZ*cf.del < 0) )
|
||||
cf.idI += cf.del*cf.Ki;
|
||||
cf.idFF = (rf.psiZ + rf.pPsiZ*sgmPar.Tr)*sgmPar.LmInv*PSI_BAZ/I_BAZ;
|
||||
idZ = cf.idP + cf.idI + cf.idFF;
|
||||
// îãðàíè÷åíèå ïîòîêîîáðàçóþùåãî òîêà
|
||||
if ( idZ > cf.IdLim ) {
|
||||
idZ = cf.IdLim;
|
||||
cf.idLimFlag = 1;
|
||||
}
|
||||
else if ( idZ < cf.IdLimNeg ) {
|
||||
idZ = cf.IdLimNeg;
|
||||
cf.idLimFlag = 1;
|
||||
}
|
||||
else {
|
||||
cf.idLimFlag = 0;
|
||||
}
|
||||
} //void control_flux(void)
|
||||
|
||||
|
||||
|
||||
// Ðåãóëèðóåò ñêîðîñòü èëè ìîùíîñòü
|
||||
// (rs.wmZ, wm, rs.pWmZ, rp.pmZ, mst.wmLim, mst.pmLim, csp.IqLim,
|
||||
// csp.IqLimNeg -> iqZ, inuWork)
|
||||
void control_speed_power(void) {
|
||||
if ( csp.once == 0 ) {
|
||||
csp.once = 1;
|
||||
csp.wmLimZi = mst.wmLim;
|
||||
csp.pmLimZi = mst.pmLim;
|
||||
csp.iqLimFlag = 0;
|
||||
csp.iqI = 0;
|
||||
iqZ = 0;
|
||||
csp.iqLimZi = csp.IqLim;
|
||||
csp.iqLim = csp.IqLim;
|
||||
csp.pmZiRampDown = 0;
|
||||
}
|
||||
|
||||
// äëÿ îãðàíè÷åíèÿ ñêîðîñòè
|
||||
if ( mst.wmLim - csp.wmLimZi > rs.WlimIncr ) {
|
||||
csp.wmLimZi += rs.WlimIncr;
|
||||
}
|
||||
else if ( csp.wmLimZi - mst.wmLim > rs.WlimIncr ) {
|
||||
csp.wmLimZi -= rs.WlimIncr;
|
||||
}
|
||||
else {
|
||||
csp.wmLimZi = mst.wmLim;
|
||||
}
|
||||
// äëÿ îãðàíè÷åíèÿ ìîùíîñòè
|
||||
if ( mst.pmLim - csp.pmLimZi > rp.PlimIncr ) {
|
||||
csp.pmLimZi += rp.PlimIncr;
|
||||
}
|
||||
else if ( csp.pmLimZi - mst.pmLim > rp.PlimIncr ) {
|
||||
csp.pmLimZi -= rp.PlimIncr;
|
||||
}
|
||||
else {
|
||||
csp.pmLimZi = mst.pmLim;
|
||||
}
|
||||
|
||||
if ( inuWork == 0 ) {
|
||||
if ( mst.start == 1 ) {
|
||||
// ÃÝÄ íàìàãíè÷åí, ìîæíî ïåðåõîäèòü ê îòðàáîòêå N èëè P
|
||||
if ( (rf.psiZ > rf.PsiZ*0.97) && (psi > rf.psiZ*0.97) )
|
||||
inuWork = 1;
|
||||
}
|
||||
else {
|
||||
// âñ¸ âûêëþ÷àåì
|
||||
inuWork = 2;
|
||||
}
|
||||
// ÷òîáû ñòàðòàíóòü áåç áðîñêîâ òîêà
|
||||
rs.wmZi = rs.wmZ = wm;
|
||||
rp.pmZi = rp.pmZ = 0;
|
||||
iqZ = 0;
|
||||
}
|
||||
else if ( inuWork == 1 ) {
|
||||
if ( mst.start == 1 ) {
|
||||
// ðåãóëÿòîð N --------------
|
||||
if ( mst.pzMode == 0 ) {
|
||||
csp.del = rs.wmZ - wm;
|
||||
csp.iqP = csp.del*csp.Kp;
|
||||
if ( (csp.iqLimFlag == 0) || (iqZ*csp.del < 0) )
|
||||
csp.iqI += csp.del*csp.Ki;
|
||||
csp.iqFF = rs.pWmZ/kMe*(WM_BAZ*J/M_BAZ);
|
||||
iqZ = csp.iqP + csp.iqI + csp.iqFF;
|
||||
// îãðàíè÷åíèå òîêà äëÿ îãðàíè÷åíèÿ ìîùíîñòè
|
||||
if ( wmAbs > WM_MIN ) {
|
||||
csp.iqLimAux = csp.pmLimZi/(wmAbs*kMe);
|
||||
}
|
||||
else {
|
||||
csp.iqLimAux = csp.pmLimZi/(WM_MIN*kMe);
|
||||
}
|
||||
if ( csp.iqLimAux < csp.IqLim ) {
|
||||
csp.iqLim = csp.iqLimAux;
|
||||
}
|
||||
else {
|
||||
csp.iqLim = csp.IqLim;
|
||||
}
|
||||
}
|
||||
// ðåãóëÿòîð P --------------
|
||||
else { //if ( mst.pzMode == 1 )
|
||||
if ( wmAbs <= WM_MIN ) {
|
||||
iqZ = rp.pmZ/(WM_MIN*kMe);
|
||||
}
|
||||
else if ( wmAbs <= rf.WmNomPsi ) {
|
||||
iqZ = rp.pmZ/(wmAbs*kMe);
|
||||
csp.kMeNom = kMe;
|
||||
}
|
||||
else {
|
||||
iqZ = rp.pmZ/(wmAbs*csp.kMeNom);
|
||||
}
|
||||
// îãðàíè÷åíèå òîêà äëÿ îãðàíè÷åíèÿ îáîðîòîâ
|
||||
if ( wmAbs < csp.wmLimZi*0.98 ) {
|
||||
csp.iqLimAux = fabs(iqZ);
|
||||
}
|
||||
else if ( wmAbs > csp.wmLimZi*1.02 ) {
|
||||
csp.iqLimAux = 0;
|
||||
}
|
||||
else {
|
||||
csp.iqLimAux = csp.iqLimZi;
|
||||
}
|
||||
// ... ìåíÿåì ñêîðîñòü èçìåíåíèÿ îãðàíè÷åíèÿ òîêà (?)
|
||||
csp.delWmAbs = fabs(wmAbs - csp.wmLimZi);
|
||||
if ( csp.delWmAbs > 0.12 )
|
||||
csp.KizIncr = 10.0;
|
||||
else if ( csp.delWmAbs < 0.02 )
|
||||
csp.KizIncr = 0.1;
|
||||
else
|
||||
csp.KizIncr = 0.1 + (csp.delWmAbs - 0.02)*(10.0 - 0.1)/(0.12 - 0.02);
|
||||
// ... ÇÈ
|
||||
if ( csp.iqLimAux - csp.iqLimZi > csp.IlimIncr*csp.KizIncr )
|
||||
csp.iqLimZi += csp.IlimIncr*csp.KizIncr;
|
||||
else if ( csp.iqLimZi - csp.iqLimAux > csp.IlimIncr*csp.KizIncr )
|
||||
csp.iqLimZi -= csp.IlimIncr*csp.KizIncr;
|
||||
else
|
||||
csp.iqLimZi = csp.iqLimAux;
|
||||
if ( csp.iqLimZi < csp.IqLim ) {
|
||||
csp.iqLim = csp.iqLimZi;
|
||||
}
|
||||
else {
|
||||
csp.iqLim = csp.IqLim;
|
||||
}
|
||||
} //mst.pzMode
|
||||
// äëÿ ïëàâíîé îñòàíîâêè
|
||||
csp.pmZiRampDown = rp.pmEqv;
|
||||
}
|
||||
else { //if ( mst.start == 0 )
|
||||
// ñíèæàåì çàäàííóþ ìîùíîñòü
|
||||
if ( 0 - csp.pmZiRampDown > mst.pDecrMaxTy ) {
|
||||
csp.pmZiRampDown += mst.pDecrMaxTy;
|
||||
}
|
||||
else if ( csp.pmZiRampDown - 0 > mst.pDecrMaxTy ) {
|
||||
csp.pmZiRampDown -= mst.pDecrMaxTy;
|
||||
}
|
||||
else {
|
||||
csp.pmZiRampDown = 0;
|
||||
// òîê ñíèæåí - çàâåðøàåì ðàáîòó
|
||||
inuWork = 2;
|
||||
}
|
||||
// ôîðìèðóåì çàäàííûé òîê
|
||||
if ( wmAbs > WM_MIN ) {
|
||||
iqZ = csp.pmZiRampDown/(wmAbs*kMe);
|
||||
}
|
||||
else {
|
||||
iqZ = csp.pmZiRampDown/(WM_MIN*kMe);
|
||||
}
|
||||
// íà ñëó÷àé, åñëè mst.start âîññòàíîâèòñÿ ðàíüøå
|
||||
// çàâåðøåíèÿ ðàáîòû (inuWork = 2)
|
||||
rs.wmZi = rs.wmZ = wm;
|
||||
csp.iqI = iqZ;
|
||||
rp.pmZi = rp.pmZ = rp.pmEqv;
|
||||
} //mst.start
|
||||
|
||||
// óñòàâêà îãðàíè÷åíèÿ ñíèçó
|
||||
if ( -csp.iqLim > csp.IqLimNeg )
|
||||
csp.iqLimNeg = -csp.iqLim;
|
||||
else
|
||||
csp.iqLimNeg = csp.IqLimNeg;
|
||||
// îãðàíè÷åíèå ìîìåíòîîáðàçóþùåãî òîêà
|
||||
if ( iqZ > csp.iqLim ) {
|
||||
iqZ = csp.iqLim;
|
||||
csp.iqLimFlag = 1;
|
||||
}
|
||||
else if ( iqZ < csp.iqLimNeg ) {
|
||||
iqZ = csp.iqLimNeg;
|
||||
csp.iqLimFlag = 1;
|
||||
}
|
||||
else {
|
||||
csp.iqLimFlag = 0;
|
||||
}
|
||||
// äëÿ ïëàâíîãî ïåðåõîäà
|
||||
if ( mst.pzMode == 0 ) {
|
||||
// ... â ðåæèì ðåãóëèðîâàíèÿ P
|
||||
rp.pmZ = iqZ*kMe*wmAbs;
|
||||
rp.pmZi = rp.pmZ;
|
||||
csp.iqLimZi = fabs(iqZ);
|
||||
}
|
||||
else {
|
||||
// ... â ðåæèì ðåãóëèðîâàíèÿ N
|
||||
csp.iqI = iqZ;
|
||||
csp.iqFF = 0;
|
||||
rs.wmZ = wm;
|
||||
rs.wmZi = rs.wmZ + csp.iqFF*0.05;
|
||||
}
|
||||
} //inuWork
|
||||
} //void control_speed_power(void)
|
||||
|
||||
|
||||
|
||||
// Ðàñ÷¸òû äëÿ indirect vector control
|
||||
// (wmNf, wm, ix1, iy1, ix2, iy2 -> ivc.ws, ivc.sinTheta, ivc.cosTheta,
|
||||
// ivc.id1, ivc.iq1, ivc.id2, ivc.iq2, ivc.psi)
|
||||
void indirect_vector_control(void) {
|
||||
static float theta;
|
||||
|
||||
if ( ivc.once == 0 ) {
|
||||
ivc.once = 1;
|
||||
ivc.im = 0;
|
||||
ivc.iq1 = 0;
|
||||
ivc.wr = 0;
|
||||
theta = 0;
|
||||
}
|
||||
|
||||
// ÷àñòîòà ðîòîðíîé ÝÄÑ, o.e.
|
||||
if ( ivc.im > 4e-3 ) {
|
||||
ivc.wr = (ivc.iq1)/ivc.im*sgmPar.TrInv*(1.0/WE_BAZ);
|
||||
}
|
||||
if ( estimate_get_step() == ESTIMATE_TEST_LM ) {
|
||||
ivc.wr = 0;
|
||||
ivc.wsNf = 0;
|
||||
ivc.ws = 0;
|
||||
}
|
||||
else {
|
||||
ivc.wsNf = wmNf + ivc.wr;
|
||||
ivc.ws = wm + ivc.wr;
|
||||
theta += ivc.wsNf*WE_BAZ*TY;
|
||||
if ( theta > PI2 )
|
||||
theta -= PI2;
|
||||
else if ( theta < 0 )
|
||||
theta += PI2;
|
||||
}
|
||||
|
||||
theta_out = theta;//Âûâîä óãëà òåòòà â Simulink
|
||||
|
||||
// äëÿ êîîðäèíàòíûõ ïðåîáðàçîâàíèé
|
||||
sincos(theta, &ivc.sinTheta, &ivc.cosTheta);
|
||||
// park transformations, î.å.
|
||||
ivc.id1 = ix1*ivc.cosTheta + iy1*ivc.sinTheta;
|
||||
ivc.iq1 = -ix1*ivc.sinTheta + iy1*ivc.cosTheta;
|
||||
// òîê íàìàãíè÷èâàíèÿ, o.e.
|
||||
ivc.im += (ivc.id1 - ivc.im)*sgmPar.TrInv*TY;
|
||||
// àìïëèòóäà ïîòîêà, o.e.
|
||||
ivc.psi = ivc.im*sgmPar.Lm*(1.0/L_BAZ);
|
||||
} //void indirect_vector_control(void)
|
||||
|
||||
|
||||
|
||||
// Ïåðåâîäèò ñèãíàëû óïðàâëåíèÿ èç ñ.ê. d-q â ñ.ê. x-y
|
||||
// (cc.yd1, cc.yq1, cc.yd2, cc.yq2, sinTheta, cosTheta, ws ->
|
||||
// -> ip.yx1, ip.yy1, ip.yx2, ip.yy2)
|
||||
void ipark(void) {
|
||||
ip.yx1Aux = cc.yd1*cosTheta - cc.yq1*sinTheta;
|
||||
ip.yy1Aux = cc.yd1*sinTheta + cc.yq1*cosTheta;
|
||||
// êîððåêöèÿ, ñâÿçàííàÿ ñ äèñêðåòíîñòüþ ÑÓ
|
||||
ip.theta = ws*WE_BAZ*TY*1.5;//ðàä.
|
||||
sincos(ip.theta, &ip.sinTheta, &ip.cosTheta);
|
||||
ip.yx1 = ip.yx1Aux*ip.cosTheta - ip.yy1Aux*ip.sinTheta;
|
||||
ip.yy1 = ip.yx1Aux*ip.sinTheta + ip.yy1Aux*ip.cosTheta;
|
||||
} //void ipark(void)
|
||||
|
||||
|
||||
|
||||
// Îãðàíè÷èâàåò ïîëíûé òîê
|
||||
// (idZ, iqZ, IzLim -> idZ, iqZ, csp.iqLimFlag)
|
||||
void limit_current(void) {
|
||||
iZ = sqrt(idZ*idZ + iqZ*iqZ);
|
||||
if ( iZ > IzLim ) {
|
||||
if ( iqZ >= 0 ) {
|
||||
iqZ = sqrt(IzLim*IzLim - idZ*idZ);
|
||||
}
|
||||
else {
|
||||
iqZ = -sqrt(IzLim*IzLim - idZ*idZ);
|
||||
}
|
||||
csp.iqLimFlag = 1;
|
||||
}
|
||||
} //void limit_current(void)
|
||||
|
||||
|
||||
|
||||
// ØÈÌ
|
||||
// (ip.yx1, ip.yy1, ip.yx2, ip.yy2 ->
|
||||
// -> EPwm1Regs.CMPA.half.CMPA, EPwm2Regs.CMPA.half.CMPA,
|
||||
// EPwm3Regs.CMPA.half.CMPA, EPwm4Regs.CMPA.half.CMPA,
|
||||
// EPwm5Regs.CMPA.half.CMPA, EPwm6Regs.CMPA.half.CMPA,
|
||||
// EPwm7Regs.CMPA.half.CMPA, EPwm8Regs.CMPA.half.CMPA,
|
||||
// EPwm9Regs.CMPA.half.CMPA, EPwm10Regs.CMPA.half.CMPA,
|
||||
// EPwm11Regs.CMPA.half.CMPA, EPwm12Regs.CMPA.half.CMPA)
|
||||
void pwm(float ya, float yb, float yc) {
|
||||
static float yPredm = 0;
|
||||
static float yaPredm;
|
||||
static float ybPredm;
|
||||
static float ycPredm;
|
||||
|
||||
// ïðåäìîäóëèðóþùåå âîçäåéñòâèå
|
||||
if ((ya >= yb) && (ya <= yc)) {
|
||||
yPredm = ya*0.5;
|
||||
}
|
||||
else if ((yc >= yb) && (yc <= ya)) {
|
||||
yPredm = yc*0.5;
|
||||
}
|
||||
else if ((yb >= yc) && (yb <= ya)) {
|
||||
yPredm = yb*0.5;
|
||||
}
|
||||
else if ((ya >= yc) && (ya <= yb)) {
|
||||
yPredm = ya*0.5;
|
||||
}
|
||||
else if ((yc >= ya) && (yc <= yb)) {
|
||||
yPredm = yc*0.5;
|
||||
}
|
||||
else if ((yb >= ya) && (yb <= yc)) {
|
||||
yPredm = yb*0.5;
|
||||
}
|
||||
yaPredm = (ya + yPredm)*2.;
|
||||
ybPredm = (yb + yPredm)*2.;
|
||||
ycPredm = (yc + yPredm)*2.;
|
||||
// full compare unit compare registers
|
||||
if (yaPredm >= 0) {
|
||||
EPwm1Regs.CMPA.half.CMPA = (unsigned short)yaPredm;
|
||||
EPwm2Regs.CMPA.half.CMPA = 0;
|
||||
}
|
||||
else {
|
||||
EPwm1Regs.CMPA.half.CMPA = 0;
|
||||
EPwm2Regs.CMPA.half.CMPA = (unsigned short)(-yaPredm);
|
||||
}
|
||||
if (ybPredm >= 0) {
|
||||
EPwm3Regs.CMPA.half.CMPA = (unsigned short)ybPredm;
|
||||
EPwm4Regs.CMPA.half.CMPA = 0;
|
||||
}
|
||||
else {
|
||||
EPwm3Regs.CMPA.half.CMPA = 0;
|
||||
EPwm4Regs.CMPA.half.CMPA = (unsigned short)(-ybPredm);
|
||||
}
|
||||
if (ycPredm >= 0) {
|
||||
EPwm5Regs.CMPA.half.CMPA = (unsigned short)ycPredm;
|
||||
EPwm6Regs.CMPA.half.CMPA = 0;
|
||||
}
|
||||
else {
|
||||
EPwm5Regs.CMPA.half.CMPA = 0;
|
||||
EPwm6Regs.CMPA.half.CMPA = (unsigned short)(-ycPredm);
|
||||
}
|
||||
|
||||
|
||||
|
||||
// ðàçðåøàåì èìïóëüñû
|
||||
EALLOW;
|
||||
EPwm1Regs.TZCLR.all = 0x0004;
|
||||
EPwm2Regs.TZCLR.all = 0x0004;
|
||||
EPwm3Regs.TZCLR.all = 0x0004;
|
||||
EPwm4Regs.TZCLR.all = 0x0004;
|
||||
EPwm5Regs.TZCLR.all = 0x0004;
|
||||
EPwm6Regs.TZCLR.all = 0x0004;
|
||||
} //void pwm(void)
|
||||
|
||||
|
||||
|
||||
// Ôîðìèðóåò çàäàííûé ïîòîê
|
||||
// (rf.PsiZ -> rf.psiZ, rf.pPsiZ)
|
||||
void reference_flux(void) {
|
||||
if ( rf.once == 0 ) {
|
||||
rf.once = 1;
|
||||
rf.KpsiSub = TY*DECIM_PSI_WM_PM/6.0;
|
||||
rf.psiZi = 0;
|
||||
cc.y1 = 0;
|
||||
rf.psiSub = 0;
|
||||
rf.psiZ = 0;
|
||||
rf.psiZPrev1 = 0;
|
||||
rf.psiZPrev2 = 0;
|
||||
rf.psiZPrev3 = 0;
|
||||
}
|
||||
|
||||
// ÇÈ
|
||||
if ( rf.PsiZ - rf.psiZi > rf.PsizIncr ) {
|
||||
rf.psiZi += rf.PsizIncr;
|
||||
}
|
||||
else if ( rf.psiZi - rf.PsiZ > rf.PsizIncr ) {
|
||||
rf.psiZi -= rf.PsizIncr;
|
||||
}
|
||||
else {
|
||||
rf.psiZi = rf.PsiZ;
|
||||
}
|
||||
// êîððåêöèÿ â ñîîòâåòñòâèè ñî ñêîðîñòüþ
|
||||
if ( wmAbs <= rf.WmNomPsi )
|
||||
rf.psiZCorr = rf.psiZi;
|
||||
else
|
||||
rf.psiZCorr = rf.psiZi*rf.WmNomPsi/wmAbs;
|
||||
// êîððåêöèÿ â ñîîòâåòñòâèè ñ ïðîòèâîÝÄÑ
|
||||
if (cc.y1 > rf.YlimPsi) {
|
||||
rf.psiSub += (rf.psiZCorr - rf.psiSub)*rf.KpsiSub;
|
||||
}
|
||||
else {
|
||||
rf.psiSub += (0 - rf.psiSub)*rf.KpsiSub;
|
||||
}
|
||||
rf.psiZCorr2 = rf.psiZCorr - rf.psiSub;
|
||||
// ÷òîáû çàäàíèå ìåíÿëîñü ÷óòü ïëàâíåå
|
||||
rf.psiZ += (rf.psiZCorr2 - rf.psiZ)*rf.Kpsiz;
|
||||
|
||||
// ïðîèçâîäíàÿ çàäàííîãî ïîòîêîñöåïëåíèÿ
|
||||
rf.pPsiZ = (rf.psiZ - rf.psiZPrev3)/(TY*DECIM_PSI_WM_PM*3.);
|
||||
rf.psiZPrev3 = rf.psiZPrev2;
|
||||
rf.psiZPrev2 = rf.psiZPrev1;
|
||||
rf.psiZPrev1 = rf.psiZ;
|
||||
} //void reference_flux(void)
|
||||
|
||||
|
||||
|
||||
// Ôîðìèðóåò çàäàííóþ ìîùíîñòü
|
||||
// (mst.pmZz, mst.pmLim -> rp.pmZ)
|
||||
void reference_power(void) {
|
||||
if ( rp.once == 0 ) {
|
||||
rp.once = 1;
|
||||
rp.pmZi = 0;
|
||||
rp.pmZ = 0;
|
||||
}
|
||||
|
||||
// îãðàíè÷åíèå
|
||||
if ( fabs(mst.pmZz) > mst.pmLim ) {
|
||||
if ( mst.pmZz >= 0 )
|
||||
rp.pmZz = mst.pmLim;
|
||||
else
|
||||
rp.pmZz = -mst.pmLim;
|
||||
}
|
||||
else {
|
||||
rp.pmZz = mst.pmZz;
|
||||
}
|
||||
// äëÿ îãðàíè÷åíèÿ ïðèðàùåíèÿ ìîùíîñòè (?)
|
||||
if ( fabs(rp.pmZi - rp.pmEqv) > 0.02 )
|
||||
rp.KpIncrDecr = 0.10;
|
||||
else
|
||||
rp.KpIncrDecr = 1.00;
|
||||
// ÇÈ
|
||||
if ( rp.pmZz - rp.pmZi > mst.pIncrMaxTy*rp.KpIncrDecr ) {
|
||||
rp.pmZi += mst.pIncrMaxTy*rp.KpIncrDecr;
|
||||
}
|
||||
else if ( rp.pmZi - rp.pmZz > mst.pDecrMaxTy*rp.KpIncrDecr ) {
|
||||
rp.pmZi -= mst.pDecrMaxTy*rp.KpIncrDecr;
|
||||
}
|
||||
else {
|
||||
rp.pmZi = rp.pmZz;
|
||||
}
|
||||
// ÷òîáû çàäàíèå ìåíÿëîñü ÷óòü ïëàâíåå
|
||||
rp.pmZ += (rp.pmZi - rp.pmZ)*rp.Kpmz;
|
||||
} //void reference_power(void)
|
||||
|
||||
|
||||
|
||||
// Ôîðìèðóåò çàäàííóþ ñêîðîñòü
|
||||
// (mst.wmZz, mst.wmLim -> rs.wmZ, rs.pWmZ)
|
||||
void reference_speed(void) {
|
||||
if ( rs.once == 0 ) {
|
||||
rs.once = 1;
|
||||
rs.wmZi = rs.wmZ = wm;
|
||||
rs.wzIncr = rs.WlimIncr;
|
||||
rs.wmZPrev1 = rs.wmZ;
|
||||
rs.wmZPrev2 = rs.wmZ;
|
||||
rs.wmZPrev3 = rs.wmZ;
|
||||
rs.tPwmZ = 0;
|
||||
}
|
||||
|
||||
// îãðàíè÷åíèå
|
||||
if ( fabs(mst.wmZz) > mst.wmLim ) {
|
||||
if ( mst.wmZz >= 0 )
|
||||
rs.wmZz = mst.wmLim;
|
||||
else
|
||||
rs.wmZz = -mst.wmLim;
|
||||
}
|
||||
else {
|
||||
rs.wmZz = mst.wmZz;
|
||||
}
|
||||
// äëÿ îãðàíè÷åíèÿ ïðèðàùåíèÿ ìîùíîñòè (?)
|
||||
if ( fabs(rs.wmZi) < 0.5 )
|
||||
rs.wzIncrNf = rs.WlimIncr*3.5;
|
||||
else if ( fabs(rs.wmZi) < 0.8 )
|
||||
rs.wzIncrNf = rs.WlimIncr*2.0;
|
||||
else
|
||||
rs.wzIncrNf = rs.WlimIncr;
|
||||
rs.wzIncr += (rs.wzIncrNf - rs.wzIncr)*(TY*DECIM_PSI_WM_PM)/0.25;
|
||||
// ÇÈ
|
||||
if ( rs.wmZz - rs.wmZi > rs.wzIncr ) {
|
||||
rs.wmZi += rs.wzIncr;
|
||||
}
|
||||
else if ( rs.wmZi - rs.wmZz > rs.wzIncr ) {
|
||||
rs.wmZi -= rs.wzIncr;
|
||||
}
|
||||
else {
|
||||
rs.wmZi = rs.wmZz;
|
||||
}
|
||||
// ÷òîáû çàäàíèå ìåíÿëîñü ÷óòü ïëàâíåå
|
||||
rs.wmZ += (rs.wmZi - rs.wmZ)*rs.Kwmz;
|
||||
|
||||
// ïðîèçâîäíàÿ çàäàííîé ñêîðîñòè
|
||||
rs.pWmZ = (rs.wmZ - rs.wmZPrev3)/(TY*DECIM_PSI_WM_PM*3.);
|
||||
rs.wmZPrev3 = rs.wmZPrev2;
|
||||
rs.wmZPrev2 = rs.wmZPrev1;
|
||||
rs.wmZPrev1 = rs.wmZ;
|
||||
// ... ÷òîáû èçáåæàòü áðîñêîâ ïðè âõîäå â ðàáî÷èé ðåæèì
|
||||
if ( (inuWork == 0) || (mst.start == 0) || (mst.pzMode == 1) )
|
||||
rs.tPwmZ = 0;
|
||||
if ( rs.tPwmZ <= 3 ) {
|
||||
rs.tPwmZ++;
|
||||
rs.pWmZ = 0;
|
||||
}
|
||||
} //void reference_speed(void)
|
||||
|
||||
|
||||
|
||||
// Âûáèðàåò î.ñ.
|
||||
// (... -> ws, sinTheta, cosTheta, id1, iq1, id2, iq2, psi)
|
||||
void select_feedback(void) {
|
||||
ws = ivc.ws;
|
||||
sinTheta = ivc.sinTheta;
|
||||
cosTheta = ivc.cosTheta;
|
||||
id1 = ivc.id1;
|
||||
iq1 = ivc.iq1;
|
||||
psi = ivc.psi;
|
||||
} //void select_feedback(void)
|
||||
54
Inu_im_1wnd_3lvl/Inu/upr.h
Normal file
54
Inu_im_1wnd_3lvl/Inu/upr.h
Normal file
@@ -0,0 +1,54 @@
|
||||
#ifndef UPR
|
||||
#define UPR
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â upr.c (begin)
|
||||
//#########################################################################
|
||||
volatile short onceUpr;
|
||||
struct SgmPar sgmPar;
|
||||
struct Rf rf;
|
||||
struct Rs rs;
|
||||
struct Rp rp;
|
||||
|
||||
float IzLim;
|
||||
volatile float psi;
|
||||
volatile float theta_out; // óãîë ? äëß âûâîäà â Simulink
|
||||
float idZ;
|
||||
float iqZ;
|
||||
float iZ;
|
||||
float ws;
|
||||
float sinTheta;
|
||||
float cosTheta;
|
||||
float id1;
|
||||
float iq1;
|
||||
float id2;
|
||||
float iq2;
|
||||
struct Cc cc;
|
||||
struct Cf cf;
|
||||
struct Csp csp;
|
||||
struct Ivc ivc;
|
||||
struct Ip ip;
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îïðåäåëåíû â upr.c (end)
|
||||
|
||||
|
||||
|
||||
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â upr.c (begin)
|
||||
//#########################################################################
|
||||
extern volatile float wmNf;
|
||||
extern volatile float wm;
|
||||
extern volatile float wmAbs;
|
||||
extern volatile float ix1;
|
||||
extern volatile float iy1;
|
||||
extern volatile float ix2;
|
||||
extern volatile float iy2;
|
||||
extern volatile float kMe;
|
||||
extern volatile short inuWork;
|
||||
extern struct Mst mst;
|
||||
extern volatile short faultNo;
|
||||
extern double iref;
|
||||
extern volatile float ia1Nf;
|
||||
extern volatile float ib1Nf;
|
||||
//#########################################################################
|
||||
// Ïåðåìåííûå, êîòîðûå îáúÿâëåíû â upr.c (end)
|
||||
#endif //UPR
|
||||
267
Inu_im_1wnd_3lvl/Inu/wrapper_inu.c
Normal file
267
Inu_im_1wnd_3lvl/Inu/wrapper_inu.c
Normal file
@@ -0,0 +1,267 @@
|
||||
/**************************************************************************
|
||||
Description: Ïðîãðàììà - óïàêîâùèê.
|
||||
|
||||
Àâòîð: Óëèòîâñêèé Ä.È.
|
||||
Äàòà ïîñëåäíåãî îáíîâëåíèÿ: 2021.09.23
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
|
||||
#define S_FUNCTION_NAME wrapper_inu
|
||||
#define S_FUNCTION_LEVEL 2
|
||||
#include "simstruc.h"
|
||||
#include "math.h"
|
||||
#include "wrapper_inu.h"
|
||||
|
||||
|
||||
|
||||
#define MDL_UPDATE
|
||||
/* Function: mdlUpdate ====================================================
|
||||
* Abstract:
|
||||
* This function is called once for every major integration time step.
|
||||
* Discrete states are typically updated here, but this function is useful
|
||||
* for performing any tasks that should only take place once per
|
||||
* integration step.
|
||||
*/
|
||||
static void mdlUpdate(SimStruct *S, int_T tid)
|
||||
{
|
||||
const real_T *u = (const real_T*) ssGetInputPortRealSignal(S,0);
|
||||
real_T *xD = ssGetDiscStates(S);
|
||||
real_T *rW = ssGetRWork(S);
|
||||
int_T *iW = ssGetIWork(S);
|
||||
|
||||
controller(S, u, xD, rW, iW);
|
||||
|
||||
}//end mdlUpdate
|
||||
|
||||
|
||||
|
||||
/* Function: mdlCheckParameters ===========================================
|
||||
* Abstract:
|
||||
* mdlCheckParameters verifies new parameter settings whenever parameter
|
||||
* change or are re-evaluated during a simulation.
|
||||
*/
|
||||
#define MDL_CHECK_PARAMETERS /* Change to #undef to remove function */
|
||||
#if defined(MDL_CHECK_PARAMETERS) && defined(MATLAB_MEX_FILE)
|
||||
static void mdlCheckParameters(SimStruct *S)
|
||||
{
|
||||
int i;
|
||||
|
||||
// Ïðîâåðÿåì è ïðèíèìàåì ïàðàìåòðû è ðàçðåøàåì èëè çàïðåùàåì èõ ìåíÿòü
|
||||
// â ïðîöåññå ìîäåëèðîâàíèÿ
|
||||
for (i=0; i<NPARAMS; i++)
|
||||
{
|
||||
// Input parameter must be scalar or vector of type double
|
||||
if (!mxIsDouble(ssGetSFcnParam(S,i)) || mxIsComplex(ssGetSFcnParam(S,i)) ||
|
||||
mxIsEmpty(ssGetSFcnParam(S,i)))
|
||||
{
|
||||
ssSetErrorStatus(S,"Input parameter must be of type double");
|
||||
return;
|
||||
}
|
||||
// Ïàðàìåòð ì.á. òîëüêî ñêàëÿðîì, âåêòîðîì èëè ìàòðèöåé
|
||||
if (mxGetNumberOfDimensions(ssGetSFcnParam(S,i)) > 2)
|
||||
{
|
||||
ssSetErrorStatus(S,"Ïàðàìåòð ì.á. òîëüêî ñêàëÿðîì, âåêòîðîì èëè ìàòðèöåé");
|
||||
return;
|
||||
}
|
||||
|
||||
// Parameter not tunable
|
||||
// ssSetSFcnParamTunable(S, i, SS_PRM_NOT_TUNABLE);
|
||||
// Parameter tunable (we must create a corresponding run-time parameter)
|
||||
ssSetSFcnParamTunable(S, i, SS_PRM_TUNABLE);
|
||||
// Parameter tunable only during simulation
|
||||
// ssSetSFcnParamTunable(S, i, SS_PRM_SIM_ONLY_TUNABLE);
|
||||
|
||||
}//for (i=0; i<NPARAMS; i++)
|
||||
|
||||
}//end mdlCheckParameters
|
||||
|
||||
#endif //MDL_CHECK_PARAMETERS
|
||||
|
||||
|
||||
#define MDL_PROCESS_PARAMETERS /* Change to #undef to remove function */
|
||||
#if defined(MDL_PROCESS_PARAMETERS) && defined(MATLAB_MEX_FILE)
|
||||
/* Function: mdlProcessParameters =========================================
|
||||
* Abstract:
|
||||
* This method will be called after mdlCheckParameters, whenever
|
||||
* parameters change or get re-evaluated. The purpose of this method is
|
||||
* to process the newly changed parameters. For example "caching" the
|
||||
* parameter changes in the work vectors. Note this method is not
|
||||
* called when it is used with the Real-Time Workshop. Therefore,
|
||||
* if you use this method in an S-function which is being used with the
|
||||
* Real-Time Workshop, you must write your S-function such that it doesn't
|
||||
* rely on this method. This can be done by inlining your S-function
|
||||
* via the Target Language Compiler.
|
||||
*/
|
||||
static void mdlProcessParameters(SimStruct *S)
|
||||
{
|
||||
int_T *iW = ssGetIWork(S);
|
||||
|
||||
iW[0] = 1;//processParameters
|
||||
}
|
||||
#endif //MDL_PROCESS_PARAMETERS
|
||||
|
||||
|
||||
|
||||
/* Function: mdlInitializeSizes ===========================================
|
||||
* Abstract:
|
||||
* The sizes information is used by Simulink to determine the S-function
|
||||
* block's characteristics (number of inputs, outputs, states, etc.).
|
||||
*/
|
||||
static void mdlInitializeSizes(SimStruct *S)
|
||||
{
|
||||
//---------------------------------------------------------------------
|
||||
// Number of expected parameters
|
||||
ssSetNumSFcnParams(S, NPARAMS);
|
||||
|
||||
// Â íîðìàëüíîì ðåæèìå ðàáîòû, äëÿ îáðàáîòêè ïàðàìåòðîâ âûçûâàåì ô-öèþ
|
||||
// mdlCheckParameters()
|
||||
#ifdef MATLAB_MEX_FILE
|
||||
// Êîë-âî îæèäàåìûõ è ôàêòè÷åñêèõ ïàðàìåòðîâ äîëæíî ñîâïàäàòü
|
||||
if(ssGetNumSFcnParams(S) == ssGetSFcnParamsCount(S))
|
||||
{
|
||||
// Ïðîâåðÿåì è ïðèíèìàåì ïàðàìåòðû
|
||||
mdlCheckParameters(S);
|
||||
}
|
||||
else
|
||||
{
|
||||
return;// Parameter mismatch will be reported by Simulink
|
||||
}
|
||||
#endif // MATLAB_MEX_FILE
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// Register the number and type of states the S-Function uses
|
||||
ssSetNumContStates(S, 0); // number of continuous states
|
||||
ssSetNumDiscStates(S, OUTPUT_0_WIDTH); // number of discrete states
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// Óñòàíàâëèâàåì êîë-âî âõ-ûõ ïîðòîâ
|
||||
if (!ssSetNumInputPorts(S, 1)) return;
|
||||
// Óñòàíàâëèâàåì êîë-âî ñèãíàëîâ âî âõ-îì ïîðòó
|
||||
ssSetInputPortWidth(S, 0, INPUT_0_WIDTH);
|
||||
|
||||
// Çàÿâëÿåì, ÷òî äëÿ íàøåãî âõ-ãî ïîðòà íåò direct feedthrough
|
||||
ssSetInputPortDirectFeedThrough(S, 0, 0);
|
||||
|
||||
// Òðåáóåì, ÷òîáû ñèãíàëû âî âõîäíîì ïîðòó øëè ïîñëåäîâàòåëüíî, à íå
|
||||
// â ðàçáðîñ
|
||||
ssSetInputPortRequiredContiguous(S, 0, 1); // direct input signal access
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// Óñòàíàâëèâàåì êîë-âî âûõ-ûõ ïîðòîâ
|
||||
if (!ssSetNumOutputPorts(S, 1)) return;
|
||||
// Óñòàíàâëèâàåì êîë-âî ñèãíàëîâ â âûõ-îì ïîðòó
|
||||
ssSetOutputPortWidth(S, 0, OUTPUT_0_WIDTH);
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// Number of sample times
|
||||
ssSetNumSampleTimes(S, 1);
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// Set size of the work vectors
|
||||
ssSetNumRWork( S, RWORK_0_WIDTH); // number of real work vector elements
|
||||
ssSetNumIWork( S, IWORK_0_WIDTH); // number of integer work vector elements
|
||||
ssSetNumPWork( S, 0); // number of pointer work vector elements
|
||||
ssSetNumModes( S, 0); // number of mode work vector elements
|
||||
ssSetNumNonsampledZCs( S, 0); // number of nonsampled zero crossings
|
||||
// ssSetNumDWork(S, 1);
|
||||
|
||||
// ssSetDWorkWidth(S, 0, 12);//Inm
|
||||
// ssSetDWorkDataType(S, 0, SS_DOUBLE);
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
/*
|
||||
* All options have the form SS_OPTION_<name> and are documented in
|
||||
* matlabroot/simulink/include/simstruc.h. The options should be
|
||||
* bitwise or'd together as in
|
||||
* ssSetOptions(S, (SS_OPTION_EXCEPTION_FREE_CODE | SS_OPTION_name2))
|
||||
*/
|
||||
// Ñ ïîìîùüþ îïöèè SS_OPTION_EXCEPTION_FREE_CODE îáåùàåì, ÷òî â
|
||||
// íàøåé ïðîãðàììå íåò "èñêëþ÷åíèé"
|
||||
ssSetOptions(S, (SS_OPTION_EXCEPTION_FREE_CODE));
|
||||
|
||||
}//end mdlInitializeSizes
|
||||
|
||||
|
||||
|
||||
/* Function: mdlInitializeSampleTimes =====================================
|
||||
* Abstract:
|
||||
* This function is used to specify the sample time(s) for your
|
||||
* S-function. You must register the same number of sample times as
|
||||
* specified in ssSetNumSampleTimes.
|
||||
*/
|
||||
static void mdlInitializeSampleTimes(SimStruct *S)
|
||||
{
|
||||
double dt;
|
||||
|
||||
// Øàã äèñêðåòèçàöèè
|
||||
dt = mxGetPr(ssGetSFcnParam(S,NPARAMS-1))[0];
|
||||
|
||||
// Register one pair for each sample time
|
||||
ssSetSampleTime(S, 0, dt);
|
||||
ssSetOffsetTime(S, 0, 0.0);
|
||||
|
||||
}//end mdlInitializeSampleTimes
|
||||
|
||||
|
||||
#define MDL_START // Change to #undef to remove function
|
||||
#if defined(MDL_START)
|
||||
/* Function: mdlStart =====================================================
|
||||
* Abstract:
|
||||
* This function is called once at start of model execution. If you
|
||||
* have states that should be initialized once, this is the place
|
||||
* to do it.
|
||||
*/
|
||||
static void mdlStart(SimStruct *S)
|
||||
{
|
||||
int_T *iW = ssGetIWork(S);
|
||||
|
||||
iW[0] = 1;//processParameters
|
||||
iW[1] = 1;//start
|
||||
}
|
||||
#endif // MDL_START
|
||||
|
||||
|
||||
|
||||
/* Function: mdlOutputs ===================================================
|
||||
* Abstract:
|
||||
* In this function, you compute the outputs of your S-function
|
||||
* block. Generally outputs are placed in the output vector(s),
|
||||
* ssGetOutputPortSignal.
|
||||
*/
|
||||
static void mdlOutputs(SimStruct *S, int_T tid)
|
||||
{
|
||||
real_T *y = ssGetOutputPortRealSignal(S,0);
|
||||
real_T *xD = ssGetDiscStates(S);
|
||||
|
||||
int i;
|
||||
|
||||
// OUTPUTS
|
||||
for (i=0; i<OUTPUT_0_WIDTH; i++)
|
||||
y[i] = xD[i];
|
||||
|
||||
}//end mdlOutputs
|
||||
|
||||
|
||||
|
||||
/* Function: mdlTerminate =================================================
|
||||
* Abstract:
|
||||
* In this function, you should perform any actions that are necessary
|
||||
* at the termination of a simulation. For example, if memory was
|
||||
* allocated in mdlStart, this is the place to free it.
|
||||
*/
|
||||
static void mdlTerminate(SimStruct *S)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*=============================*
|
||||
* Required S-function trailer *
|
||||
*=============================*/
|
||||
|
||||
#ifdef MATLAB_MEX_FILE // Is this file being compiled as a MEX-file?
|
||||
#include "simulink.c" // MEX-file interface mechanism
|
||||
#else
|
||||
#include "cg_sfun.h" // Code generation registration function
|
||||
#endif
|
||||
25
Inu_im_1wnd_3lvl/Inu/wrapper_inu.h
Normal file
25
Inu_im_1wnd_3lvl/Inu/wrapper_inu.h
Normal file
@@ -0,0 +1,25 @@
|
||||
/**************************************************************************
|
||||
Description: Задание количества входов, выходов, параметров, а также
|
||||
размера рабочих векторов S-function.
|
||||
|
||||
Автор: Улитовский Д.И.
|
||||
Дата последнего обновления: 2021.09.22
|
||||
**************************************************************************/
|
||||
|
||||
|
||||
#ifndef WRAPPER
|
||||
#define WRAPPER
|
||||
|
||||
|
||||
#define INPUT_0_WIDTH 17 //кол-во входов
|
||||
#define OUTPUT_0_WIDTH 35 //кол-во выходов
|
||||
#define NPARAMS 1 //кол-во параметров (скаляров и векторов)
|
||||
#define RWORK_0_WIDTH 5 //width of the real-work vector
|
||||
#define IWORK_0_WIDTH 5 //width of the integer-work vector
|
||||
|
||||
|
||||
void controller(SimStruct *S, const real_T *u, real_T *xD, real_T *rW,
|
||||
int_T *iW);
|
||||
|
||||
|
||||
#endif
|
||||
2
Inu_im_1wnd_3lvl/ReadMe.txt
Normal file
2
Inu_im_1wnd_3lvl/ReadMe.txt
Normal file
@@ -0,0 +1,2 @@
|
||||
Один трёхуровневый инвертор питает однообмоточный асинхронный двигатель.
|
||||
|
||||
14
Inu_im_1wnd_3lvl/allmex.asv
Normal file
14
Inu_im_1wnd_3lvl/allmex.asv
Normal file
@@ -0,0 +1,14 @@
|
||||
% Компилирует S-function
|
||||
currFolder = cd;
|
||||
cd([currFolder, '\Inu']);
|
||||
|
||||
mex -D"ML" ...
|
||||
-I"F:\Work\Projects\MATLAB\Drives_lib_new\device_support_ml\include" ...
|
||||
-outdir F:\Work\Projects\MATLAB\Drives_lib_new\Inu_im_1wnd_3lvl ...
|
||||
wrapper_inu.c controller.c init28335.c detcoeff.c isr.c main.c param.c upr.c estimate.c...
|
||||
F:\Work\Projects\MATLAB\Drives_lib_new\device_support_ml\source\C28x_FPU_FastRTS.c ...
|
||||
F:\Work\Projects\MATLAB\Drives_lib_new\device_support_ml\source\DSP2833x_GlobalVariableDefs.c ...
|
||||
-g
|
||||
|
||||
cd(currFolder);
|
||||
clear currFolder
|
||||
14
Inu_im_1wnd_3lvl/allmex.m
Normal file
14
Inu_im_1wnd_3lvl/allmex.m
Normal file
@@ -0,0 +1,14 @@
|
||||
% Êîìïèëèðóåò S-function
|
||||
currFolder = cd;
|
||||
cd([currFolder, '\Inu']);
|
||||
|
||||
mex -D"ML" ...
|
||||
-I"F:\Work\Projects\MATLAB\Drives_lib_new\device_support_ml\include" ...
|
||||
-outdir F:\Work\Projects\MATLAB\Drives_lib_new\Inu_im_1wnd_3lvl ...
|
||||
wrapper_inu.c controller.c init28335.c detcoeff.c isr.c main.c param.c upr.c estimate.c...
|
||||
F:\Work\Projects\MATLAB\Drives_lib_new\device_support_ml\source\C28x_FPU_FastRTS.c ...
|
||||
F:\Work\Projects\MATLAB\Drives_lib_new\device_support_ml\source\DSP2833x_GlobalVariableDefs.c ...
|
||||
-g
|
||||
|
||||
cd(currFolder);
|
||||
clear currFolder
|
||||
10
Inu_im_1wnd_3lvl/extra.m
Normal file
10
Inu_im_1wnd_3lvl/extra.m
Normal file
@@ -0,0 +1,10 @@
|
||||
% Данные
|
||||
x = [0.1; 0.2; 0.3; 0.4; 0.5];
|
||||
y = [0.0130993528; 0.00648460863; 0.00379571458; 0.00300260726; 0.00203630934];
|
||||
y = y + 0.0019364;
|
||||
% Экспоненциальная аппроксимация: y = a * exp(-b*x)
|
||||
logY = log(y);
|
||||
p = polyfit(x, logY, 1); % ln(y) = ln(a) - b*x
|
||||
a = exp(p(2));
|
||||
b = -p(1);
|
||||
y0 = a % при x=0: y = a
|
||||
79
Inu_im_1wnd_3lvl/init.m
Normal file
79
Inu_im_1wnd_3lvl/init.m
Normal file
@@ -0,0 +1,79 @@
|
||||
% Cкрипт для задания параметров модели
|
||||
|
||||
clear;%очищаем рабочее пространство
|
||||
|
||||
Ts = 1e-6;%шаг интегрирования
|
||||
Decim = 20;%интервал прореживания
|
||||
Limit = 2000000;%кол-во запоминаемых точек
|
||||
% Scope-ы запоминают последнии tt секунд расчёта
|
||||
tt = Ts*Decim*Limit;
|
||||
|
||||
|
||||
% для упрощения записи
|
||||
SQRT2 = sqrt(2);
|
||||
SQRT3 = sqrt(3);
|
||||
PI2 = pi*2;
|
||||
|
||||
% начальная скорость ГЭД, доля от NmNom
|
||||
w0 = 0;%0.5;%-0.75;%
|
||||
% пусковой момент, о.е.
|
||||
Mst = 0.6;
|
||||
|
||||
% разрешаем/запрещаем сбросы/набросы момента нагрузки
|
||||
changingLoadEnable = 1;%0;%
|
||||
% разрешаем/запрещаем шум в измеренном токе
|
||||
noiseEnable = 0;%0;%
|
||||
% ... мощность шума
|
||||
NP = 0.08;
|
||||
|
||||
% номинальные величины ГЭД
|
||||
% ... мощность на валу, Вт
|
||||
Pnom = 5000e3;
|
||||
% ... линейное напряжение, В (rms)
|
||||
Unom = 3000;
|
||||
% ... механическая скорость, об/мин
|
||||
NmNom = 165;
|
||||
% ... число пар полюсов
|
||||
Pp = 6;
|
||||
% ... коэффициент мощности
|
||||
CosFi = 0.89;
|
||||
% ... КПД
|
||||
Eff = 0.962;
|
||||
% ... приведенный к валу момент инерции, кг*м^2
|
||||
J = 87e3;
|
||||
% ... полная мощность, ВА
|
||||
Snom = Pnom/CosFi/Eff;
|
||||
% ... механическая скорость, рад/с
|
||||
WmNom = NmNom/60*PI2;
|
||||
% ... момент на валу, Н*м
|
||||
Mnom = Pnom/WmNom;
|
||||
% ... эл. скорость, рад/с
|
||||
WeNom = WmNom*Pp;
|
||||
% ... эл. скорость, Гц
|
||||
FeNom = WeNom/PI2;
|
||||
% ... потокосцепление статора, Вб
|
||||
PsiNom = Unom*SQRT2/(WeNom*SQRT3);
|
||||
% ... напряжение на входе инвертора, B
|
||||
UdcNom = Unom*SQRT2*1.18;
|
||||
% ... ток, А (ampl)
|
||||
Inom = Snom/(Unom*SQRT3)*SQRT2;%0.5 - т.к. обмоток две
|
||||
|
||||
% параметры ГЭД
|
||||
Rs = 19.2e-3;%Ом
|
||||
Xls = 146e-3;%Ом
|
||||
Rr = 8.5e-3*1.0;%*1.2;%*0.8;%Ом
|
||||
Xlr = 77e-3;%Ом
|
||||
Xm = 2.7;%Ом
|
||||
Fe = 12;%Гц
|
||||
Lls = Xls/(Fe*PI2);%Гн
|
||||
Llr = Xlr/(Fe*PI2);%Гн
|
||||
Lm = Xm/(Fe*PI2);%Гн
|
||||
|
||||
% ёмкость на входе INU, Ф
|
||||
Cdc = 50e-3;
|
||||
% снаберы в INU
|
||||
Csn = Pnom/(1000*WeNom*Unom^2)/10;%Ф (0.5 - т.к. преобразователей два)
|
||||
Rsn = 2*Ts/Csn*10;%Ом
|
||||
|
||||
% постоянная времени фильтра для тока ГЭД, c
|
||||
Tiac = 30e-6;
|
||||
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl.slx
Normal file
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl.slx
Normal file
Binary file not shown.
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl_r2021b.slx
Normal file
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl_r2021b.slx
Normal file
Binary file not shown.
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl_r2021b.slx.autosave
Normal file
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl_r2021b.slx.autosave
Normal file
Binary file not shown.
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl_r2021b.slx.r2021b
Normal file
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl_r2021b.slx.r2021b
Normal file
Binary file not shown.
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl_r2021b.slxc
Normal file
BIN
Inu_im_1wnd_3lvl/inu_im_1wnd_3lvl_r2021b.slxc
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because one or more lines are too long
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<MF0 version="1.1" packageUris="http://schema.mathworks.com/mf0/SlCache/19700101">
|
||||
<slcache.FileAttributes type="slcache.FileAttributes" uuid="f1912167-0913-4b6d-9506-38c4d61c99c6">
|
||||
<checksum>wrZdJ+Ol553uT0lNMzthqDDW8xNO+VCkx/iedzHt4Be+t4x350jENqrUCari3HRLZlplZxZ36xvKhE0pwumhcg==</checksum>
|
||||
</slcache.FileAttributes>
|
||||
</MF0>
|
||||
Binary file not shown.
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<MF0 version="1.1" packageUris="http://schema.mathworks.com/mf0/SlCache/19700101">
|
||||
<slcache.FileAttributes type="slcache.FileAttributes" uuid="19d3da6c-c2b0-48c9-90b1-c7a35f449e11">
|
||||
<checksum>neMqpL05OkedrfPnPBga+XXLQp7ss1fnRUrW7adcvAMs/UIHZQ42t5m2T+L/et16MytameaiJUd/5P31CoR6sA==</checksum>
|
||||
</slcache.FileAttributes>
|
||||
</MF0>
|
||||
Binary file not shown.
2
Inu_im_1wnd_3lvl/slprj/sl_proj.tmw
Normal file
2
Inu_im_1wnd_3lvl/slprj/sl_proj.tmw
Normal file
@@ -0,0 +1,2 @@
|
||||
Simulink Coder project marker file. Please don't change it.
|
||||
slprjVersion: 10.7_091
|
||||
BIN
Inu_im_1wnd_3lvl/wrapper_inu.mexw64
Normal file
BIN
Inu_im_1wnd_3lvl/wrapper_inu.mexw64
Normal file
Binary file not shown.
BIN
Inu_im_1wnd_3lvl/wrapper_inu.mexw64.pdb
Normal file
BIN
Inu_im_1wnd_3lvl/wrapper_inu.mexw64.pdb
Normal file
Binary file not shown.
BIN
Inu_im_1wnd_3lvl/Книга1.xlsx
Normal file
BIN
Inu_im_1wnd_3lvl/Книга1.xlsx
Normal file
Binary file not shown.
Reference in New Issue
Block a user