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добавил второй проект для C8T6

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andrey
2026-02-14 18:13:02 +03:00
parent 69ae4f8cf2
commit 8552d8ee90
2781 changed files with 1626381 additions and 41 deletions
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125
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32f1xx_hal_can_ex_legacy.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_can_ex_legacy.h
* @author MCD Application Team
* @brief Header file of CAN HAL Extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CAN_EX_LEGACY_H
#define __STM32F1xx_HAL_CAN_EX_LEGACY_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup CANEx CANEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief CAN filter configuration structure definition
*/
/* CAN filter banks differences over STM32F1 devices: */
/* - STM32F1 Connectivity line: 28 filter banks shared between CAN1 and CAN2 */
/* - Other STM32F10x devices: 14 filter banks */
typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
#if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
#else
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
This parameter must be a number between Min_Data = 0 and Max_Data = 13. */
#endif /* STM32F105xC || STM32F107xC */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint32_t FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE. */
uint32_t BankNumber; /*!< Select the start slave bank filter
This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
}CAN_FilterConfTypeDef;
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup CANEx_Private_Macros CAN Extended Private Macros
* @{
*/
#if defined(STM32F105xC) || defined(STM32F107xC)
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
#else
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U)
#endif /* STM32F105xC || STM32F107xC */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_CAN_EX_LEGACY_H */

776
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32f1xx_hal_can_legacy.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_can_legacy.h
* @author MCD Application Team
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CAN_LEGACY_H
#define __STM32F1xx_HAL_CAN_LEGACY_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup CAN
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
}HAL_CAN_StateTypeDef;
/**
* @brief CAN init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
uint32_t Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
uint32_t SJW; /*!< Specifies the maximum number of time quanta
the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
This parameter can be set to ENABLE or DISABLE */
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
This parameter can be set to ENABLE or DISABLE */
}CAN_InitTypeDef;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_Identifier_Type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
uint8_t Data[8]; /*!< Contains the data to be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
}CanTxMsgTypeDef;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
This parameter can be a value of @ref CAN_Identifier_Type */
uint32_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
uint8_t Data[8]; /*!< Contains the data to be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
}CanRxMsgTypeDef;
/**
* @brief CAN handle Structure definition
*/
typedef struct
{
CAN_TypeDef *Instance; /*!< Register base address */
CAN_InitTypeDef Init; /*!< CAN required parameters */
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
HAL_LockTypeDef Lock; /*!< CAN locking object */
__IO uint32_t ErrorCode; /*!< CAN Error code */
}CAN_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
/**
* @}
*/
/** @defgroup CAN_InitStatus CAN initialization Status
* @{
*/
#define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */
/**
* @}
*/
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
/**
* @}
*/
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
* @{
*/
#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
/**
* @}
*/
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
/**
* @}
*/
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
/**
* @}
*/
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
/** @defgroup CAN_Identifier_Type CAN Identifier Type
* @{
*/
#define CAN_ID_STD 0x00000000U /*!< Standard Id */
#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
/**
* @}
*/
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
/**
* @}
*/
/** @defgroup CAN_transmit_constants CAN Transmit Constants
* @{
*/
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
/**
* @}
*/
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
/**
* @}
*/
/** @defgroup CAN_flags CAN Flags
* @{
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK2_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
/* Receive Flags */
#define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
#define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
#define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */
#define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */
#define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */
/**
* @}
*/
/** @defgroup CAN_Interrupts CAN Interrupts
* @{
*/
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
/**
* @}
*/
/**
* @}
*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
/* CAN intermediate shift values used for CAN flags */
#define TSR_REGISTER_INDEX 0x5U
#define RF0R_REGISTER_INDEX 0x2U
#define RF1R_REGISTER_INDEX 0x4U
#define MSR_REGISTER_INDEX 0x1U
#define ESR_REGISTER_INDEX 0x3U
/* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR registers) */
/* Transmit Flags */
#define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
#define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
#define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
#define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
#define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
#define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
#define CAN_TSR_TME0_BIT_POSITION 0x0000001AU
#define CAN_TSR_TME1_BIT_POSITION 0x0000001BU
#define CAN_TSR_TME2_BIT_POSITION 0x0000001CU
/* Receive Flags */
#define CAN_RF0R_FF0_BIT_POSITION 0x00000003U
#define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
#define CAN_RF1R_FF1_BIT_POSITION 0x00000003U
#define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
/* Operating Mode Flags */
#define CAN_MSR_WKU_BIT_POSITION 0x00000003U
#define CAN_MSR_SLAK_BIT_POSITION 0x00000001U
#define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
/* Error Flags */
#define CAN_ESR_EWG_BIT_POSITION 0x00000000U
#define CAN_ESR_EPV_BIT_POSITION 0x00000001U
#define CAN_ESR_BOF_BIT_POSITION 0x00000002U
/* Mask used by macro to get/clear CAN flags*/
#define CAN_FLAG_MASK 0x000000FFU
/* Mailboxes definition */
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CAN_Exported_Macros CAN Exported Macros
* @{
*/
/** @brief Reset CAN handle state
* @param __HANDLE__: CAN handle.
* @retval None
*/
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/**
* @brief Enable the specified CAN interrupts
* @param __HANDLE__: CAN handle.
* @param __INTERRUPT__: CAN Interrupt.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
* @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
* @arg CAN_IT_FF0 : FIFO 0 full interrupt
* @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
* @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
* @arg CAN_IT_FF1 : FIFO 1 full interrupt
* @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
* @arg CAN_IT_WKU : Wake-up interrupt
* @arg CAN_IT_SLK : Sleep acknowledge interrupt
* @arg CAN_IT_EWG : Error warning interrupt
* @arg CAN_IT_EPV : Error passive interrupt
* @arg CAN_IT_BOF : Bus-off interrupt
* @arg CAN_IT_LEC : Last error code interrupt
* @arg CAN_IT_ERR : Error Interrupt
* @retval None.
*/
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the specified CAN interrupts
* @param __HANDLE__: CAN handle.
* @param __INTERRUPT__: CAN Interrupt.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
* @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
* @arg CAN_IT_FF0 : FIFO 0 full interrupt
* @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
* @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
* @arg CAN_IT_FF1 : FIFO 1 full interrupt
* @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
* @arg CAN_IT_WKU : Wake-up interrupt
* @arg CAN_IT_SLK : Sleep acknowledge interrupt
* @arg CAN_IT_EWG : Error warning interrupt
* @arg CAN_IT_EPV : Error passive interrupt
* @arg CAN_IT_BOF : Bus-off interrupt
* @arg CAN_IT_LEC : Last error code interrupt
* @arg CAN_IT_ERR : Error Interrupt
* @retval None.
*/
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/**
* @brief Return the number of pending received messages.
* @param __HANDLE__: CAN handle.
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval The number of pending message.
*/
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__: specifies the CAN Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
* @arg CAN_FLAG_EWG: Error Warning Flag
* @arg CAN_FLAG_EPV: Error Passive Flag
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Clear the specified CAN pending flag.
* @param __HANDLE__: specifies the CAN Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the CAN Handle.
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
* @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
* @arg CAN_IT_FF0 : FIFO 0 full interrupt
* @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
* @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
* @arg CAN_IT_FF1 : FIFO 1 full interrupt
* @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
* @arg CAN_IT_WKU : Wake-up interrupt
* @arg CAN_IT_SLK : Sleep acknowledge interrupt
* @arg CAN_IT_EWG : Error warning interrupt
* @arg CAN_IT_EPV : Error passive interrupt
* @arg CAN_IT_BOF : Bus-off interrupt
* @arg CAN_IT_LEC : Last error code interrupt
* @arg CAN_IT_ERR : Error Interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Check the transmission status of a CAN Frame.
* @param __HANDLE__: specifies the CAN Handle.
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
* @retval The new status of transmission (TRUE or FALSE).
*/
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
/**
* @brief Release the specified receive FIFO.
* @param __HANDLE__: CAN handle.
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval None.
*/
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
/**
* @brief Cancel a transmit request.
* @param __HANDLE__: specifies the CAN Handle.
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
* @retval None.
*/
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
/**
* @brief Enable or disables the DBG Freeze for CAN.
* @param __HANDLE__: specifies the CAN Handle.
* @param __NEWSTATE__: new state of the CAN peripheral.
* This parameter can be: ENABLE (CAN reception/transmission is frozen
* during debug. Reception FIFOs can still be accessed/controlled normally)
* or DISABLE (CAN is working during debug).
* @retval None
*/
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
/**
* @}
*/
/* Include CAN HAL Extension module */
#include "stm32f1xx_hal_can_ex_legacy.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CAN_Exported_Functions
* @{
*/
/** @addtogroup CAN_Exported_Functions_Group1
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group2
* @brief I/O operation functions
* @{
*/
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group3
* @brief CAN Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/**
* @}
*/
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK))
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_CAN_LEGACY_H */

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/**
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32_ASSERT_H
#define __STM32_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32_ASSERT_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_cec.h
* @author MCD Application Team
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CEC_H
#define __STM32F1xx_HAL_CEC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
#if defined (CEC)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup CEC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CEC_Exported_Types CEC Exported Types
* @{
*/
/**
* @brief CEC Init Structure definition
*/
typedef struct
{
uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
This parameter can be a value of CEC_BitTimingErrorMode */
uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
This parameter can be a value of CEC_BitPeriodErrorMode */
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
} CEC_InitTypeDef;
/**
* @brief HAL CEC State definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState
(see @ref CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7 (not used)
* x : Should be set to 0
* b6 Error information
* 0 : No Error
* 1 : Error
* b5 CEC peripheral initialization status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 CEC peripheral initialization status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
} HAL_CEC_StateTypeDef;
/**
* @brief CEC handle Structure definition
*/
typedef struct __CEC_HandleTypeDef
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
CEC_InitTypeDef Init; /*!< CEC communication parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
HAL_LockTypeDef Lock; /*!< Locking object */
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
in case error is reported */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
} CEC_HandleTypeDef;
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL CEC Callback ID enumeration definition
*/
typedef enum
{
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
} HAL_CEC_CallbackIDTypeDef;
/**
* @brief HAL CEC Callback pointer definition
*/
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
callback function */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
#define HAL_CEC_ERROR_BTE CEC_ESR_BTE /*!< Bit Timing Error */
#define HAL_CEC_ERROR_BPE CEC_ESR_BPE /*!< Bit Period Error */
#define HAL_CEC_ERROR_RBTFE CEC_ESR_RBTFE /*!< Rx Block Transfer Finished Error */
#define HAL_CEC_ERROR_SBE CEC_ESR_SBE /*!< Start Bit Error */
#define HAL_CEC_ERROR_ACKE CEC_ESR_ACKE /*!< Block Acknowledge Error */
#define HAL_CEC_ERROR_LINE CEC_ESR_LINE /*!< Line Error */
#define HAL_CEC_ERROR_TBTFE CEC_ESR_TBTFE /*!< Tx Block Transfer Finished Error */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback Error */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
* @{
*/
#define CEC_BIT_TIMING_ERROR_MODE_STANDARD 0x00000000U /*!< Bit timing error Standard Mode */
#define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
/**
* @}
*/
/** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
* @{
*/
#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U /*!< Bit period error Standard Mode */
#define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
/**
* @}
*/
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
#define CEC_INITIATOR_LSB_POS 4U
/**
* @}
*/
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
#define CEC_OWN_ADDRESS_NONE CEC_OWN_ADDRESS_0 /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0000U) /* Logical Address 0 */
#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0001U) /* Logical Address 1 */
#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0002U) /* Logical Address 2 */
#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0003U) /* Logical Address 3 */
#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0004U) /* Logical Address 4 */
#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0005U) /* Logical Address 5 */
#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0006U) /* Logical Address 6 */
#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0007U) /* Logical Address 7 */
#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0008U) /* Logical Address 8 */
#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0009U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_10 ((uint16_t)0x000AU) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_11 ((uint16_t)0x000BU) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_12 ((uint16_t)0x000CU) /* Logical Address 12 */
#define CEC_OWN_ADDRESS_13 ((uint16_t)0x000DU) /* Logical Address 13 */
#define CEC_OWN_ADDRESS_14 ((uint16_t)0x000EU) /* Logical Address 14 */
#define CEC_OWN_ADDRESS_15 ((uint16_t)0x000FU) /* Logical Address 15 */
/**
* @}
*/
/** @defgroup CEC_Interrupts_Definitions Interrupts definition
* @{
*/
#define CEC_IT_IE CEC_CFGR_IE
/**
* @}
*/
/** @defgroup CEC_Flags_Definitions Flags definition
* @{
*/
#define CEC_FLAG_TSOM CEC_CSR_TSOM
#define CEC_FLAG_TEOM CEC_CSR_TEOM
#define CEC_FLAG_TERR CEC_CSR_TERR
#define CEC_FLAG_TBTRF CEC_CSR_TBTRF
#define CEC_FLAG_RSOM CEC_CSR_RSOM
#define CEC_FLAG_REOM CEC_CSR_REOM
#define CEC_FLAG_RERR CEC_CSR_RERR
#define CEC_FLAG_RBTF CEC_CSR_RBTF
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CEC_Exported_Macros CEC Exported Macros
* @{
*/
/** @brief Reset CEC handle gstate & RxState
* @param __HANDLE__ CEC handle.
* @retval None
*/
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
} while(0)
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the flag to check.
* @arg CEC_FLAG_TERR: Tx Error
* @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
* @arg CEC_FLAG_RERR: Rx Error
* @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
* @retval ITStatus
*/
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__))
/** @brief Clears the CEC's pending flags.
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg CEC_CSR_TERR: Tx Error
* @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
* @arg CEC_CSR_RERR: Rx Error
* @arg CEC_CSR_RBTF: Rx Block Transfer Finished
* @retval none
*/
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
do { \
uint32_t tmp = 0x0U; \
tmp = (__HANDLE__)->Instance->CSR & 0x00000002U; \
(__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
} while(0U)
/** @brief Enables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
* @arg CEC_IT_IE : Interrupt Enable.
* @retval none
*/
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
* @arg CEC_IT_IE : Interrupt Enable
* @retval none
*/
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
/** @brief Checks whether or not the specified CEC interrupt is enabled.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to check.
* This parameter can be one of the following values:
* @arg CEC_IT_IE : Interrupt Enable
* @retval FlagStatus
*/
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
/** @brief Enables the CEC device
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
/** @brief Disables the CEC device
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
/** @brief Set Transmission Start flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
/** @brief Set Transmission End flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
/** @brief Get Transmission Start flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
/** @brief Get Transmission End flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
/** @brief Clear OAR register
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
/** @brief Set OAR register
* @param __HANDLE__ specifies the CEC Handle.
* @param __ADDRESS__ Own Address value.
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CEC_Exported_Functions CEC Exported Functions
* @{
*/
/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
pCEC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
* @brief CEC Transmit/Receive functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
const uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
* @brief CEC control functions
* @{
*/
/* Peripheral State functions ************************************************/
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CEC_Private_Types CEC Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CEC_Private_Variables CEC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CEC_Private_Macros CEC Private Macros
* @{
*/
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
/** @brief Check CEC message size.
* The message size is the payload size: without counting the header,
* it varies from 0 byte (ping operation, one header only, no payload) to
* 15 bytes (1 opcode and up to 14 operands following the header).
* @param __SIZE__ CEC message size.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
/** @brief Check CEC device Own Address Register (OAR) setting.
* @param __ADDRESS__ CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
* @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* CEC */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_CEC_H */

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john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_conf_template.h Normal file
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@@ -0,0 +1,398 @@
/**
******************************************************************************
* @file stm32f1xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f1xx_hal_conf.h.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CONF_H
#define __STM32F1xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
#define HAL_CEC_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
#define HAL_MMC_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#if defined(USE_STM3210C_EVAL)
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#else
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 1U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f1xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f1xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f1xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f1xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f1xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f1xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#include "Legacy/stm32f1xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f1xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f1xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f1xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f1xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f1xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f1xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f1xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f1xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f1xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f1xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f1xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f1xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f1xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f1xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f1xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f1xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f1xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f1xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f1xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f1xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f1xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f1xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f1xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f1xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f1xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f1xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_CONF_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_crc.h
* @author MCD Application Team
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_CRC_H
#define STM32F1xx_HAL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/**
* @brief CRC HAL State Structure definition
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
} HAL_CRC_StateTypeDef;
/**
* @brief CRC Handle Structure definition
*/
typedef struct
{
CRC_TypeDef *Instance; /*!< Register base address */
HAL_LockTypeDef Lock; /*!< CRC Locking object */
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
} CRC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @param __VALUE__ Value to be stored in the ID register
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_CRC_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_dac.h
* @author MCD Application Team
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_DAC_H
#define STM32F1xx_HAL_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
#if defined(DAC)
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Types DAC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
} HAL_DAC_StateTypeDef;
/**
* @brief DAC handle Structure definition
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
typedef struct __DAC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
{
DAC_TypeDef *Instance; /*!< Register base address */
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
} DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DAC Callback ID enumeration definition
*/
typedef enum
{
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
} HAL_DAC_CallbackIDTypeDef;
/**
* @brief HAL DAC Callback pointer definition
*/
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants DAC Exported Constants
* @{
*/
/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1)
/**
* @}
*/
/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
#define DAC_CHANNEL_1 0x00000000U
#define DAC_CHANNEL_2 0x00000010U
/**
* @}
*/
/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R 0x00000000U
#define DAC_ALIGN_12B_L 0x00000004U
#define DAC_ALIGN_8B_R 0x00000008U
/**
* @}
*/
/** @defgroup DAC_flags_definition DAC flags definition
* @{
*/
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
/**
* @}
*/
/** @defgroup DAC_IT_definition DAC IT definition
* @{
*/
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Macros DAC Exported Macros
* @{
*/
/** @brief Reset DAC handle state.
* @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** @brief Enable the DAC channel.
* @param __HANDLE__ specifies the DAC handle.
* @param __DAC_Channel__ specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Disable the DAC channel.
* @param __HANDLE__ specifies the DAC handle
* @param __DAC_Channel__ specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Set DHR12R1 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
/** @brief Enable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified DAC interrupt source is enabled or not.
* @param __HANDLE__ DAC handle
* @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
* @retval State of interruption (SET or RESET)
*/
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
& (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to get.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
/**
* @}
*/
/* Include DAC HAL Extended module */
#include "stm32f1xx_hal_dac_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group4
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
/**
* @}
*/
/**
* @}
*/
/** @defgroup DAC_Private_Functions DAC Private Functions
* @{
*/
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
#endif /* DAC */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_DAC_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_dac_ex.h
* @author MCD Application Team
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_DAC_EX_H
#define STM32F1xx_HAL_DAC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
#if defined(DAC)
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL State structures definition
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
/**
* @}
*/
/** @defgroup DACEx_trigger_selection DAC trigger selection
* @{
*/
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
/* For STM32F10x high-density and XL-density devices: TIM8 */
#define DAC_TRIGGER_T8_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
/* For STM32F10x connectivity line devices and STM32F100x devices: TIM3 */
#define DAC_TRIGGER_T3_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#endif /* STM32F100xB || STM32F100xE || STM32F105xC || STM32F107xC */
/* Availability of trigger from TIM5 and TIM15: */
/* - For STM32F10x value line devices STM32F100xB: */
/* trigger from TIM15 is available, TIM5 not available. */
/* - For STM32F10x value line devices STM32F100xE: */
/* trigger from TIM15 and TIM5 are both available, */
/* selection depends on remap (with TIM5 as default configuration). */
/* - Other STM32F1 devices: */
/* trigger from TIM5 is available, TIM15 not available. */
#if defined (STM32F100xB)
#define DAC_TRIGGER_T15_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#else
#define DAC_TRIGGER_T5_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#if defined (STM32F100xE)
/*!< DAC trigger availability depending on STM32F1 devices:
For STM32F100x high-density value line devices, the TIM15 TRGO event can be selected
as replacement of TIM5 TRGO if the MISC_REMAP bit in the AFIO_MAPR2 register is set.
Refer to macro "__HAL_AFIO_REMAP_MISC_ENABLE()/__HAL_AFIO_REMAP_MISC_DISABLE()".
Otherwise, TIM5 TRGO is used and TIM15 TRGO is not used (default case).
For more details please refer to the AFIO section. */
#define DAC_TRIGGER_T15_TRGO DAC_TRIGGER_T5_TRGO
#endif /* STM32F100xE */
#endif /* STM32F100xB */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
#if defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F100xE || STM32F105xC || STM32F107xC */
#if defined (STM32F100xB)
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F100xB */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Extended features functions ***********************************************/
/** @addtogroup DACEx_Exported_Functions
* @{
*/
/** @addtogroup DACEx_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DACEx_Private_Functions
* @{
*/
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
/* are called by HAL_DAC_Start_DMA */
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
#endif /* DAC */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_DAC_EX_H */

2141
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_eth.h Normal file
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@@ -0,0 +1,2141 @@
/**
******************************************************************************
* @file stm32f1xx_hal_eth.h
* @author MCD Application Team
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_ETH_H
#define __STM32F1xx_HAL_ETH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
#if defined (ETH)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup ETH
* @{
*/
/** @addtogroup ETH_Private_Macros
* @{
*/
#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
((CMD) == ETH_AUTONEGOTIATION_DISABLE))
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
((SPEED) == ETH_SPEED_100M))
#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
((MODE) == ETH_MODE_HALFDUPLEX))
#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
((MODE) == ETH_RXINTERRUPT_MODE))
#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
((MODE) == ETH_MEDIA_INTERFACE_RMII))
#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
((CMD) == ETH_WATCHDOG_DISABLE))
#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
((CMD) == ETH_JABBER_DISABLE))
#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
((GAP) == ETH_INTERFRAMEGAP_40BIT))
#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
((CMD) == ETH_CARRIERSENCE_DISABLE))
#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
((CMD) == ETH_RECEIVEOWN_DISABLE))
#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
((CMD) == ETH_LOOPBACKMODE_DISABLE))
#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
((LIMIT) == ETH_BACKOFFLIMIT_8) || \
((LIMIT) == ETH_BACKOFFLIMIT_4) || \
((LIMIT) == ETH_BACKOFFLIMIT_1))
#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
((CMD) == ETH_DEFFERRALCHECK_DISABLE))
#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
((CMD) == ETH_RECEIVEAll_DISABLE))
#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
((ADDRESS) == ETH_MAC_ADDRESS1) || \
((ADDRESS) == ETH_MAC_ADDRESS2) || \
((ADDRESS) == ETH_MAC_ADDRESS3))
#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
((ADDRESS) == ETH_MAC_ADDRESS2) || \
((ADDRESS) == ETH_MAC_ADDRESS3))
#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
((CMD) == ETH_FIXEDBURST_DISABLE))
#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
((FLAG) == ETH_DMATXDESC_IC) || \
((FLAG) == ETH_DMATXDESC_LS) || \
((FLAG) == ETH_DMATXDESC_FS) || \
((FLAG) == ETH_DMATXDESC_DC) || \
((FLAG) == ETH_DMATXDESC_DP) || \
((FLAG) == ETH_DMATXDESC_TTSE) || \
((FLAG) == ETH_DMATXDESC_TER) || \
((FLAG) == ETH_DMATXDESC_TCH) || \
((FLAG) == ETH_DMATXDESC_TTSS) || \
((FLAG) == ETH_DMATXDESC_IHE) || \
((FLAG) == ETH_DMATXDESC_ES) || \
((FLAG) == ETH_DMATXDESC_JT) || \
((FLAG) == ETH_DMATXDESC_FF) || \
((FLAG) == ETH_DMATXDESC_PCE) || \
((FLAG) == ETH_DMATXDESC_LCA) || \
((FLAG) == ETH_DMATXDESC_NC) || \
((FLAG) == ETH_DMATXDESC_LCO) || \
((FLAG) == ETH_DMATXDESC_EC) || \
((FLAG) == ETH_DMATXDESC_VF) || \
((FLAG) == ETH_DMATXDESC_CC) || \
((FLAG) == ETH_DMATXDESC_ED) || \
((FLAG) == ETH_DMATXDESC_UF) || \
((FLAG) == ETH_DMATXDESC_DB))
#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
((FLAG) == ETH_DMARXDESC_AFM) || \
((FLAG) == ETH_DMARXDESC_ES) || \
((FLAG) == ETH_DMARXDESC_DE) || \
((FLAG) == ETH_DMARXDESC_SAF) || \
((FLAG) == ETH_DMARXDESC_LE) || \
((FLAG) == ETH_DMARXDESC_OE) || \
((FLAG) == ETH_DMARXDESC_VLAN) || \
((FLAG) == ETH_DMARXDESC_FS) || \
((FLAG) == ETH_DMARXDESC_LS) || \
((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
((FLAG) == ETH_DMARXDESC_LC) || \
((FLAG) == ETH_DMARXDESC_FT) || \
((FLAG) == ETH_DMARXDESC_RWT) || \
((FLAG) == ETH_DMARXDESC_RE) || \
((FLAG) == ETH_DMARXDESC_DBE) || \
((FLAG) == ETH_DMARXDESC_CE) || \
((FLAG) == ETH_DMARXDESC_MAMPCE))
#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
((BUFFER) == ETH_DMARXDESC_BUFFER2))
#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
((FLAG) == ETH_PMT_FLAG_MPR))
#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
((FLAG) == ETH_DMA_FLAG_T))
#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
((IT) == ETH_MAC_IT_PMT))
#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
((FLAG) == ETH_MAC_FLAG_PMT))
#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
((IT) != 0x00U))
#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
/**
* @}
*/
/** @addtogroup ETH_Private_Defines
* @{
*/
/* Delay to wait when writing to some Ethernet registers */
#define ETH_REG_WRITE_DELAY 0x00000001U
/* ETHERNET Errors */
#define ETH_SUCCESS 0U
#define ETH_ERROR 1U
/* ETHERNET DMA Tx descriptors Collision Count Shift */
#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
/* ETHERNET DMA Rx descriptors Frame Length Shift */
#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
/* ETHERNET DMA Rx descriptors Frame length Shift */
#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
/* ETHERNET MAC address offsets */
#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
/* ETHERNET MACMIIAR register Mask */
#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
/* ETHERNET MACCR register Mask */
#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
/* ETHERNET MACFCR register Mask */
#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
/* ETHERNET DMAOMR register Mask */
#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
/* ETHERNET Remote Wake-up frame register length */
#define ETH_WAKEUP_REGISTER_LENGTH 8U
/* ETHERNET Missed frames counter Shift */
#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ETH_Exported_Types ETH Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
} HAL_ETH_StateTypeDef;
/**
* @brief ETH Init Structure definition
*/
typedef struct
{
uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
and the mode (half/full-duplex).
This parameter can be a value of @ref ETH_AutoNegotiation */
uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
This parameter can be a value of @ref ETH_Speed */
uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
This parameter can be a value of @ref ETH_Duplex_Mode */
uint16_t PhyAddress; /*!< Ethernet PHY address.
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
This parameter can be a value of @ref ETH_Rx_Mode */
uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
This parameter can be a value of @ref ETH_Checksum_Mode */
uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
This parameter can be a value of @ref ETH_Media_Interface */
} ETH_InitTypeDef;
/**
* @brief ETH MAC Configuration Structure definition
*/
typedef struct
{
uint32_t Watchdog; /*!< Selects or not the Watchdog timer
When enabled, the MAC allows no more then 2048 bytes to be received.
When disabled, the MAC can receive up to 16384 bytes.
This parameter can be a value of @ref ETH_Watchdog */
uint32_t Jabber; /*!< Selects or not Jabber timer
When enabled, the MAC allows no more then 2048 bytes to be sent.
When disabled, the MAC can send up to 16384 bytes.
This parameter can be a value of @ref ETH_Jabber */
uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
This parameter can be a value of @ref ETH_Inter_Frame_Gap */
uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
This parameter can be a value of @ref ETH_Carrier_Sense */
uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
in Half-Duplex mode.
This parameter can be a value of @ref ETH_Receive_Own */
uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
This parameter can be a value of @ref ETH_Loop_Back_Mode */
uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
This parameter can be a value of @ref ETH_Checksum_Offload */
uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
when a collision occurs (Half-Duplex mode).
This parameter can be a value of @ref ETH_Retry_Transmission */
uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
This parameter can be a value of @ref ETH_Back_Off_Limit */
uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
This parameter can be a value of @ref ETH_Deferral_Check */
uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
This parameter can be a value of @ref ETH_Receive_All */
uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
This parameter can be a value of @ref ETH_Source_Addr_Filter */
uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
This parameter can be a value of @ref ETH_Pass_Control_Frames */
uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
This parameter can be a value of @ref ETH_Destination_Addr_Filter */
uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
This parameter can be a value of @ref ETH_Promiscuous_Mode */
uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
automatic retransmission of PAUSE Frame.
This parameter can be a value of @ref ETH_Pause_Low_Threshold */
uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
unicast address and unique multicast address).
This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
disable its transmitter for a specified time (Pause Time)
This parameter can be a value of @ref ETH_Receive_Flow_Control */
uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
or the MAC back-pressure operation (Half-Duplex mode)
This parameter can be a value of @ref ETH_Transmit_Flow_Control */
uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
comparison and filtering.
This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
} ETH_MACInitTypeDef;
/**
* @brief ETH DMA Configuration Structure definition
*/
typedef struct
{
uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
This parameter can be a value of @ref ETH_Receive_Store_Forward */
uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
This parameter can be a value of @ref ETH_Flush_Received_Frame */
uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
This parameter can be a value of @ref ETH_Transmit_Store_Forward */
uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
This parameter can be a value of @ref ETH_Forward_Error_Frames */
uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
and length less than 64 bytes) including pad-bytes and CRC)
This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
This parameter can be a value of @ref ETH_Receive_Threshold_Control */
uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
frame of Transmit data even before obtaining the status for the first frame.
This parameter can be a value of @ref ETH_Second_Frame_Operate */
uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
This parameter can be a value of @ref ETH_Address_Aligned_Beats */
uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
This parameter can be a value of @ref ETH_Fixed_Burst */
uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
This parameter can be a value of @ref ETH_DMA_Arbitration */
} ETH_DMAInitTypeDef;
/**
* @brief ETH DMA Descriptors data structure definition
*/
typedef struct
{
__IO uint32_t Status; /*!< Status */
uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
} ETH_DMADescTypeDef;
/**
* @brief Received Frame Information structure definition
*/
typedef struct
{
ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
uint32_t SegCount; /*!< Segment count */
uint32_t length; /*!< Frame length */
uint32_t buffer; /*!< Frame buffer */
} ETH_DMARxFrameInfos;
/**
* @brief ETH Handle Structure definition
*/
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
typedef struct __ETH_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
{
ETH_TypeDef *Instance; /*!< Register base address */
ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
uint32_t LinkStatus; /*!< Ethernet link status */
ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
__IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
HAL_LockTypeDef Lock; /*!< ETH Lock */
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */
void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */
void (* DMAErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< DMA Error Callback */
void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */
void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
} ETH_HandleTypeDef;
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/**
* @brief HAL ETH Callback ID enumeration definition
*/
typedef enum
{
HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
} HAL_ETH_CallbackIDTypeDef;
/**
* @brief HAL ETH Callback pointer definition
*/
typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ETH_Exported_Constants ETH Exported Constants
* @{
*/
/** @defgroup ETH_Buffers_setting ETH Buffers setting
* @{
*/
#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define ETH_CRC 4U /*!< Ethernet CRC */
#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
/* Ethernet driver receive buffers are organized in a chained linked-list, when
an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
to the driver receive buffers memory.
Depending on the size of the received ethernet packet and the size of
each ethernet driver receive buffer, the received packet can take one or more
ethernet driver receive buffer.
In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
and the total count of the driver receive buffers ETH_RXBUFNB.
The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
example, they can be reconfigured in the application layer to fit the application
needs */
/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
packet */
#ifndef ETH_RX_BUF_SIZE
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
#endif
/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
#ifndef ETH_RXBUFNB
#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#endif
/* Ethernet driver transmit buffers are organized in a chained linked-list, when
an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
driver transmit buffers memory to the TxFIFO.
Depending on the size of the Ethernet packet to be transmitted and the size of
each ethernet driver transmit buffer, the packet to be transmitted can take
one or more ethernet driver transmit buffer.
In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
and the total count of the driver transmit buffers ETH_TXBUFNB.
The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
example, they can be reconfigured in the application layer to fit the application
needs */
/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
packet */
#ifndef ETH_TX_BUF_SIZE
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
#endif
/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
#ifndef ETH_TXBUFNB
#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#endif
/**
* @}
*/
/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
* @{
*/
/*
DMA Tx Descriptor
-----------------------------------------------------------------------------------------------
TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
-----------------------------------------------------------------------------------------------
TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
-----------------------------------------------------------------------------------------------
TDES2 | Buffer1 Address [31:0] |
-----------------------------------------------------------------------------------------------
TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
-----------------------------------------------------------------------------------------------
*/
/**
* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
*/
#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
/**
* @brief Bit definition of TDES1 register
*/
#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
/**
* @brief Bit definition of TDES2 register
*/
#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
/**
* @brief Bit definition of TDES3 register
*/
#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/**
* @}
*/
/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
* @{
*/
/*
DMA Rx Descriptor
--------------------------------------------------------------------------------------------------------------------
RDES0 | OWN(31) | Status [30:0] |
---------------------------------------------------------------------------------------------------------------------
RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
---------------------------------------------------------------------------------------------------------------------
RDES2 | Buffer1 Address [31:0] |
---------------------------------------------------------------------------------------------------------------------
RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
---------------------------------------------------------------------------------------------------------------------
*/
/**
* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
*/
#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
/**
* @brief Bit definition of RDES1 register
*/
#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
/**
* @brief Bit definition of RDES2 register
*/
#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
/**
* @brief Bit definition of RDES3 register
*/
#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/**
* @}
*/
/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
* @{
*/
#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Speed ETH Speed
* @{
*/
#define ETH_SPEED_10M 0x00000000U
#define ETH_SPEED_100M 0x00004000U
/**
* @}
*/
/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
* @{
*/
#define ETH_MODE_FULLDUPLEX 0x00000800U
#define ETH_MODE_HALFDUPLEX 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Rx_Mode ETH Rx Mode
* @{
*/
#define ETH_RXPOLLING_MODE 0x00000000U
#define ETH_RXINTERRUPT_MODE 0x00000001U
/**
* @}
*/
/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
* @{
*/
#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
/**
* @}
*/
/** @defgroup ETH_Media_Interface ETH Media Interface
* @{
*/
#define ETH_MEDIA_INTERFACE_MII 0x00000000U
#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
/**
* @}
*/
/** @defgroup ETH_Watchdog ETH Watchdog
* @{
*/
#define ETH_WATCHDOG_ENABLE 0x00000000U
#define ETH_WATCHDOG_DISABLE 0x00800000U
/**
* @}
*/
/** @defgroup ETH_Jabber ETH Jabber
* @{
*/
#define ETH_JABBER_ENABLE 0x00000000U
#define ETH_JABBER_DISABLE 0x00400000U
/**
* @}
*/
/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
* @{
*/
#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
/**
* @}
*/
/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
* @{
*/
#define ETH_CARRIERSENCE_ENABLE 0x00000000U
#define ETH_CARRIERSENCE_DISABLE 0x00010000U
/**
* @}
*/
/** @defgroup ETH_Receive_Own ETH Receive Own
* @{
*/
#define ETH_RECEIVEOWN_ENABLE 0x00000000U
#define ETH_RECEIVEOWN_DISABLE 0x00002000U
/**
* @}
*/
/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
* @{
*/
#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
* @{
*/
#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
* @{
*/
#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
/**
* @}
*/
/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
* @{
*/
#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
* @{
*/
#define ETH_BACKOFFLIMIT_10 0x00000000U
#define ETH_BACKOFFLIMIT_8 0x00000020U
#define ETH_BACKOFFLIMIT_4 0x00000040U
#define ETH_BACKOFFLIMIT_1 0x00000060U
/**
* @}
*/
/** @defgroup ETH_Deferral_Check ETH Deferral Check
* @{
*/
#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Receive_All ETH Receive All
* @{
*/
#define ETH_RECEIVEALL_ENABLE 0x80000000U
#define ETH_RECEIVEAll_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
* @{
*/
#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
* @{
*/
#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
/**
* @}
*/
/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
* @{
*/
#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
/**
* @}
*/
/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
* @{
*/
#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
/**
* @}
*/
/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
* @{
*/
#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
* @{
*/
#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
/**
* @}
*/
/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
* @{
*/
#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
* @{
*/
#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
/**
* @}
*/
/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
* @{
*/
#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
/**
* @}
*/
/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
* @{
*/
#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
* @{
*/
#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
* @{
*/
#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
* @{
*/
#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
/**
* @}
*/
/** @defgroup ETH_MAC_addresses ETH MAC addresses
* @{
*/
#define ETH_MAC_ADDRESS0 0x00000000U
#define ETH_MAC_ADDRESS1 0x00000008U
#define ETH_MAC_ADDRESS2 0x00000010U
#define ETH_MAC_ADDRESS3 0x00000018U
/**
* @}
*/
/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
* @{
*/
#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
/**
* @}
*/
/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
* @{
*/
#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
/**
* @}
*/
/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
* @{
*/
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
/**
* @}
*/
/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
* @{
*/
#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
* @{
*/
#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
/**
* @}
*/
/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
* @{
*/
#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
* @{
*/
#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
/**
* @}
*/
/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
* @{
*/
#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
* @{
*/
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
* @{
*/
#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
/**
* @}
*/
/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
* @{
*/
#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
* @{
*/
#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
* @{
*/
#define ETH_FIXEDBURST_ENABLE 0x00010000U
#define ETH_FIXEDBURST_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
* @{
*/
#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
/**
* @}
*/
/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
* @{
*/
#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
/**
* @}
*/
/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
* @{
*/
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
/**
* @}
*/
/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
* @{
*/
#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
/**
* @}
*/
/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
* @{
*/
#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
/**
* @}
*/
/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
* @{
*/
#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
/**
* @}
*/
/** @defgroup ETH_PMT_Flags ETH PMT Flags
* @{
*/
#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
/**
* @}
*/
/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
* @{
*/
#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
/**
* @}
*/
/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
* @{
*/
#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
/**
* @}
*/
/** @defgroup ETH_MAC_Flags ETH MAC Flags
* @{
*/
#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
/**
* @}
*/
/** @defgroup ETH_DMA_Flags ETH DMA Flags
* @{
*/
#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
/**
* @}
*/
/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
* @{
*/
#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
/**
* @}
*/
/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
* @{
*/
#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
/**
* @}
*/
/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
* @{
*/
#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
/**
* @}
*/
/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
* @{
*/
#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
/**
* @}
*/
/** @defgroup ETH_DMA_overflow ETH DMA overflow
* @{
*/
#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
/**
* @}
*/
/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
* @{
*/
#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ETH_Exported_Macros ETH Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/** @brief Reset ETH handle state
* @param __HANDLE__: specifies the ETH handle.
* @retval None
*/
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_ETH_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
* @param __FLAG__: specifies the flag of TDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
/**
* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
* @param __FLAG__: specifies the flag of RDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
/**
* @brief Enables the specified DMA Rx Desc receive interrupt.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
/**
* @brief Disables the specified DMA Rx Desc receive interrupt.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
/**
* @brief Set the specified DMA Rx Desc Own bit.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
/**
* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
* @param __HANDLE__: ETH Handle
* @retval The Transmit descriptor collision counter value.
*/
#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
/**
* @brief Set the specified DMA Tx Desc Own bit.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
/**
* @brief Enables the specified DMA Tx Desc Transmit interrupt.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
/**
* @brief Disables the specified DMA Tx Desc Transmit interrupt.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
/**
* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
* @param __HANDLE__: ETH Handle
* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
* This parameter can be one of the following values:
* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
/**
* @brief Enables the DMA Tx Desc CRC.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
/**
* @brief Disables the DMA Tx Desc CRC.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
/**
* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
/**
* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
/**
* @brief Enables the specified ETHERNET MAC interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
* @arg ETH_MAC_IT_PMT : PMT interrupt
* @retval None
*/
#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
/**
* @brief Disables the specified ETHERNET MAC interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
* @arg ETH_MAC_IT_PMT : PMT interrupt
* @retval None
*/
#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
/**
* @brief Initiate a Pause Control Frame (Full-duplex only).
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
/**
* @brief Checks whether the ETHERNET flow control busy bit is set or not.
* @param __HANDLE__: ETH Handle
* @retval The new state of flow control busy status bit (SET or RESET).
*/
#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
/**
* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
/**
* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
/**
* @brief Checks whether the specified ETHERNET MAC flag is set or not.
* @param __HANDLE__: ETH Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
* @arg ETH_MAC_FLAG_MMC : MMC flag
* @arg ETH_MAC_FLAG_PMT : PMT flag
* @retval The state of ETHERNET MAC flag.
*/
#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
/**
* @brief Enables the specified ETHERNET DMA interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
* enabled @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
/**
* @brief Disables the specified ETHERNET DMA interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
* disabled. @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
/**
* @brief Clears the ETHERNET DMA IT pending bit.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
* @param __HANDLE__: ETH Handle
* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
* @param __HANDLE__: ETH Handle
* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
/**
* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
* @param __HANDLE__: ETH Handle
* @param __OVERFLOW__: specifies the DMA overflow flag to check.
* This parameter can be one of the following values:
* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
*/
#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
/**
* @brief Set the DMA Receive status watchdog timer register value
* @param __HANDLE__: ETH Handle
* @param __VALUE__: DMA Receive status watchdog timer register value
* @retval None
*/
#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
/**
* @brief Enables any unicast packet filtered by the MAC address
* recognition to be a wake-up frame.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
/**
* @brief Disables any unicast packet filtered by the MAC address
* recognition to be a wake-up frame.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
/**
* @brief Enables the MAC Wake-Up Frame Detection.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
/**
* @brief Disables the MAC Wake-Up Frame Detection.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
/**
* @brief Enables the MAC Magic Packet Detection.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
/**
* @brief Disables the MAC Magic Packet Detection.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
/**
* @brief Enables the MAC Power Down.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
/**
* @brief Disables the MAC Power Down.
* @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
/**
* @brief Checks whether the specified ETHERNET PMT flag is set or not.
* @param __HANDLE__: ETH Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
* @retval The new state of ETHERNET PMT Flag (SET or RESET).
*/
#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
/**
* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
/**
* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
(__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U)
/**
* @brief Enables the MMC Counter Freeze.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
/**
* @brief Disables the MMC Counter Freeze.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
/**
* @brief Enables the MMC Reset On Read.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
/**
* @brief Disables the MMC Reset On Read.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
/**
* @brief Enables the MMC Counter Stop Rollover.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
/**
* @brief Disables the MMC Counter Stop Rollover.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
/**
* @brief Resets the MMC Counters.
* @param __HANDLE__: ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
/**
* @brief Enables the specified ETHERNET MMC Rx interrupts.
* @param __HANDLE__: ETH Handle.
* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
* @retval None
*/
#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
/**
* @brief Disables the specified ETHERNET MMC Rx interrupts.
* @param __HANDLE__: ETH Handle.
* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
* @retval None
*/
#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
/**
* @brief Enables the specified ETHERNET MMC Tx interrupts.
* @param __HANDLE__: ETH Handle.
* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
* @retval None
*/
#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
/**
* @brief Disables the specified ETHERNET MMC Tx interrupts.
* @param __HANDLE__: ETH Handle.
* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
* @retval None
*/
#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
/**
* @brief Enables the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
/**
* @brief Disables the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
/**
* @brief Enable event on ETH External event line.
* @retval None.
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
/**
* @brief Disable event on ETH External event line
* @retval None.
*/
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
/**
* @brief Get flag of the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
/**
* @brief Clear flag of the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
/**
* @brief Enables rising edge trigger to the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
/**
* @brief Disables the rising edge trigger to the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
/**
* @brief Enables falling edge trigger to the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
/**
* @brief Disables falling edge trigger to the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
/**
* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
}while(0U)
/**
* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
}while(0U)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None.
*/
#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ETH_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @addtogroup ETH_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount);
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
*/
/* IO operation functions ****************************************************/
/** @addtogroup ETH_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
/* Communication with PHY functions*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
/* Callback in non blocking modes (Interrupt) */
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup ETH_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @addtogroup ETH_Exported_Functions_Group4
* @{
*/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ETH */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_ETH_H */

324
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_hcd.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_hcd.h
* @author MCD Application Team
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_HCD_H
#define STM32F1xx_HAL_HCD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_usb.h"
#if defined (USB_OTG_FS)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup HCD HCD
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HCD_Exported_Types HCD Exported Types
* @{
*/
/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
* @{
*/
typedef enum
{
HAL_HCD_STATE_RESET = 0x00,
HAL_HCD_STATE_READY = 0x01,
HAL_HCD_STATE_ERROR = 0x02,
HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
} HCD_StateTypeDef;
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
/**
* @}
*/
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
* @{
*/
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
typedef struct __HCD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
{
HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */
HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */
__IO uint32_t ErrorCode; /*!< HCD Error code */
void *pData; /*!< Pointer Stack Handler */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
} HCD_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HCD_Exported_Constants HCD Exported Constants
* @{
*/
/** @defgroup HCD_Speed HCD Speed
* @{
*/
#define HCD_SPEED_FULL USBH_FSLS_SPEED
#define HCD_SPEED_LOW USBH_FSLS_SPEED
/**
* @}
*/
/** @defgroup HCD_Device_Speed HCD Device Speed
* @{
*/
#define HCD_DEVICE_SPEED_HIGH 0U
#define HCD_DEVICE_SPEED_FULL 1U
#define HCD_DEVICE_SPEED_LOW 2U
/**
* @}
*/
/** @defgroup HCD_PHY_Module HCD PHY Module
* @{
*/
#define HCD_PHY_ULPI 1U
#define HCD_PHY_EMBEDDED 2U
/**
* @}
*/
/** @defgroup HCD_Error_Code_definition HCD Error Code definition
* @brief HCD Error Code definition
* @{
*/
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HCD_Exported_Macros HCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
& (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \
((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
* @{
*/
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address,
uint8_t speed, uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
* @brief HAL USB OTG HCD Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
} HAL_HCD_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
* @brief HAL USB OTG HCD Callback pointer definition
* @{
*/
typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
uint8_t epnum,
HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
/**
* @}
*/
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
HAL_HCD_CallbackIDTypeDef CallbackID,
pHCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
HAL_HCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/**
* @}
*/
/* I/O operation functions ***************************************************/
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t direction, uint8_t ep_type,
uint8_t token, uint8_t *pbuff,
uint16_t length, uint8_t do_ping);
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t addr, uint8_t PortNbr);
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
/* Non-Blocking mode: Interrupt */
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
HCD_URBStateTypeDef urb_state);
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup HCD_Private_Macros HCD Private Macros
* @{
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB_OTG_FS) */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_HCD_H */

554
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_i2s.h
* @author MCD Application Team
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_I2S_H
#define STM32F1xx_HAL_I2S_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
#if defined(SPI_I2S_SUPPORT)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup I2S
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Types I2S Exported Types
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
} I2S_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
} HAL_I2S_StateTypeDef;
/**
* @brief I2S handle Structure definition
*/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
typedef struct __I2S_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
I2S_InitTypeDef Init; /*!< I2S communication parameters */
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received
NbSamplesReceived = RxBufferSize-RxBufferCount) */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code
This parameter can be a value of @ref I2S_Error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
} I2S_HandleTypeDef;
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
/**
* @brief HAL I2S Callback ID enumeration definition
*/
typedef enum
{
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
} HAL_I2S_CallbackIDTypeDef;
/**
* @brief HAL I2S Callback pointer definition
*/
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
/** @defgroup I2S_Error I2S Error
* @{
*/
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
/**
* @}
*/
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX (0x00000000U)
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
/**
* @}
*/
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS (0x00000000U)
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
/**
* @}
*/
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B (0x00000000U)
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
/**
* @}
*/
/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K (192000U)
#define I2S_AUDIOFREQ_96K (96000U)
#define I2S_AUDIOFREQ_48K (48000U)
#define I2S_AUDIOFREQ_44K (44100U)
#define I2S_AUDIOFREQ_32K (32000U)
#define I2S_AUDIOFREQ_22K (22050U)
#define I2S_AUDIOFREQ_16K (16000U)
#define I2S_AUDIOFREQ_11K (11025U)
#define I2S_AUDIOFREQ_8K (8000U)
#define I2S_AUDIOFREQ_DEFAULT (2U)
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW (0x00000000U)
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
/**
* @}
*/
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
#define I2S_IT_TXE SPI_CR2_TXEIE
#define I2S_IT_RXNE SPI_CR2_RXNEIE
#define I2S_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
#define I2S_FLAG_TXE SPI_SR_TXE
#define I2S_FLAG_RXNE SPI_SR_RXNE
#define I2S_FLAG_UDR SPI_SR_UDR
#define I2S_FLAG_OVR SPI_SR_OVR
#define I2S_FLAG_FRE SPI_SR_FRE
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define I2S_FLAG_BSY SPI_SR_BSY
#define I2S_FLAG_MASK (SPI_SR_RXNE\
| SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2S_Exported_macros I2S Exported Macros
* @{
*/
/** @brief Reset I2S handle state
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
/** @brief Disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
/** @brief Enable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
/** @brief Disable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_FRE: Frame error flag
* @arg I2S_FLAG_CHSIDE: Channel Side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2S OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
__IO uint32_t tmpreg_ovr = 0x00U; \
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
__IO uint32_t tmpreg_udr = 0x00U;\
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
UNUSED(tmpreg_udr); \
}while(0U)
/** @brief Flush the I2S DR Register.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
__IO uint32_t tmpreg_dr = 0x00U;\
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_Exported_Functions
* @{
*/
/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of I2S SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun error flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_CHSIDE: Channel side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval SET or RESET.
*/
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of I2S CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
* This parameter can be a value of @ref I2S_Mode
* @retval None
*/
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_MASTER_TX) || \
((__MODE__) == I2S_MODE_MASTER_RX))
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
((__STANDARD__) == I2S_STANDARD_MSB) || \
((__STANDARD__) == I2S_STANDARD_LSB) || \
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
((__FORMAT__) == I2S_DATAFORMAT_32B))
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
* @param __CPOL__ specifies the I2S serial clock steady state.
* This parameter can be a value of @ref I2S_Clock_Polarity
* @retval None
*/
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
((__CPOL__) == I2S_CPOL_HIGH))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* SPI_I2S_SUPPORT */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_I2S_H */

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john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_irda.h Normal file
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@@ -0,0 +1,670 @@
/**
******************************************************************************
* @file stm32f1xx_hal_irda.h
* @author MCD Application Team
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_IRDA_H
#define __STM32F1xx_HAL_IRDA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup IRDA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IRDA_Exported_Types IRDA Exported Types
* @{
*/
/**
* @brief IRDA Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref IRDA_Word_Length */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref IRDA_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Mode */
uint8_t Prescaler; /*!< Specifies the Prescaler value to be programmed
in the IrDA low-power Baud Register, for defining pulse width on which
burst acceptance/rejection will be decided. This value is used as divisor
of system clock to achieve required pulse width. */
uint32_t IrDAMode; /*!< Specifies the IrDA mode
This parameter can be a value of @ref IRDA_Low_Power */
} IRDA_InitTypeDef;
/**
* @brief HAL IRDA State structures definition
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 IP initialisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initialisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
Value is allowed for gState only */
HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
Value is allowed for gState only */
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
} HAL_IRDA_StateTypeDef;
/**
* @brief IRDA handle Structure definition
*/
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
typedef struct __IRDA_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
{
USART_TypeDef *Instance; /*!< USART registers base address */
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO uint32_t ErrorCode; /*!< IRDA Error code */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
} IRDA_HandleTypeDef;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief HAL IRDA Callback ID enumeration definition
*/
typedef enum
{
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
} HAL_IRDA_CallbackIDTypeDef;
/**
* @brief HAL IRDA Callback pointer definition
*/
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IRDA_Exported_Constants IRDA Exported constants
* @{
*/
/** @defgroup IRDA_Error_Code IRDA Error Code
* @{
*/
#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup IRDA_Word_Length IRDA Word Length
* @{
*/
#define IRDA_WORDLENGTH_8B 0x00000000U
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
#define IRDA_PARITY_NONE 0x00000000U
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
/** @defgroup IRDA_Mode IRDA Transfer Mode
* @{
*/
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
/**
* @}
*/
/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define IRDA_POWERMODE_NORMAL 0x00000000U
/**
* @}
*/
/** @defgroup IRDA_Flags IRDA Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC)
#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE)
#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE)
#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* @{
*/
#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
* @{
*/
/** @brief Reset IRDA handle gstate & RxState
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
/** @brief Flush the IRDA DR register
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
/** @brief Check whether the specified IRDA flag is set or not.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg IRDA_FLAG_TXE: Transmit data register empty flag
* @arg IRDA_FLAG_TC: Transmission Complete flag
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag
* @arg IRDA_FLAG_IDLE: Idle Line detection flag
* @arg IRDA_FLAG_ORE: OverRun Error flag
* @arg IRDA_FLAG_NE: Noise Error flag
* @arg IRDA_FLAG_FE: Framing Error flag
* @arg IRDA_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg IRDA_FLAG_TC: Transmission Complete flag.
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
*
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
* @note RXNE flag can be also cleared by a read to the USART_DR register.
* @note TC flag can be also cleared by software sequence: a read operation to
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
* @retval None
*/
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the IRDA PE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0U)
/** @brief Clear the IRDA FE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the IRDA NE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the IRDA ORE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the IRDA IDLE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
* @arg IRDA_IT_IDLE: Idle line detection interrupt
* @arg IRDA_IT_PE: Parity Error interrupt
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
(((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
* @arg IRDA_IT_IDLE: Idle line detection interrupt
* @arg IRDA_IT_PE: Parity Error interrupt
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
(((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __IT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
* @arg IRDA_IT_IDLE: Idle line detection interrupt
* @arg IRDA_IT_ERR: Error interrupt
* @arg IRDA_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
/** @brief Enable UART/USART associated to IRDA Handle
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
/** @brief Disable UART/USART associated to IRDA Handle
* @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IRDA_Exported_Functions
* @{
*/
/** @addtogroup IRDA_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup IRDA_Exported_Functions_Group2
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/** @addtogroup IRDA_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions **************************************************/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IRDA_Private_Constants IRDA Private Constants
* @{
*/
/** @brief IRDA interruptions flag mask
*
*/
#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
#define IRDA_CR1_REG_INDEX 1U
#define IRDA_CR2_REG_INDEX 2U
#define IRDA_CR3_REG_INDEX 3U
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup IRDA_Private_Macros IRDA Private Macros
* @{
*/
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
((LENGTH) == IRDA_WORDLENGTH_9B))
#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
((PARITY) == IRDA_PARITY_EVEN) || \
((PARITY) == IRDA_PARITY_ODD))
#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
((MODE) == IRDA_POWERMODE_NORMAL))
#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) ((((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup IRDA_Private_Functions IRDA Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_IRDA_H */

220
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_iwdg.h
* @author MCD Application Team
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_IWDG_H
#define STM32F1xx_HAL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup IWDG IWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types IWDG Exported Types
* @{
*/
/**
* @brief IWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
This parameter can be a value of @ref IWDG_Prescaler */
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
} IWDG_InitTypeDef;
/**
* @brief IWDG Handle Structure definition
*/
typedef struct
{
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
} IWDG_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{
*/
/**
* @brief Enable the IWDG peripheral.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
* @{
*/
/* Initialization/Start functions ********************************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Constants IWDG Private Constants
* @{
*/
/**
* @brief IWDG Key Register BitMask
*/
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macros IWDG Private Macros
* @{
*/
/**
* @brief Enable write access to IWDG_PR and IWDG_RLR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
* @brief Disable write access to IWDG_PR and IWDG_RLR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
/**
* @brief Check IWDG prescaler value.
* @param __PRESCALER__ IWDG prescaler value
* @retval None
*/
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
((__PRESCALER__) == IWDG_PRESCALER_8) || \
((__PRESCALER__) == IWDG_PRESCALER_16) || \
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/**
* @brief Check IWDG reload value.
* @param __RELOAD__ IWDG reload value
* @retval None
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_IWDG_H */

747
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_mmc.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_mmc.h
* @author MCD Application Team
* @brief Header file of MMC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_MMC_H
#define STM32F1xx_HAL_MMC_H
#if defined(SDIO)
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_sdmmc.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup MMC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup MMC_Exported_Types MMC Exported Types
* @{
*/
/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
* @{
*/
typedef enum
{
HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
}HAL_MMC_StateTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
* @{
*/
typedef uint32_t HAL_MMC_CardStateTypeDef;
#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
* @{
*/
#define MMC_InitTypeDef SDIO_InitTypeDef
#define MMC_TypeDef SDIO_TypeDef
/**
* @brief MMC Card Information Structure definition
*/
typedef struct
{
uint32_t CardType; /*!< Specifies the card Type */
uint32_t Class; /*!< Specifies the class of the card class */
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
uint32_t BlockSize; /*!< Specifies one block size in bytes */
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
}HAL_MMC_CardInfoTypeDef;
/**
* @brief MMC handle Structure definition
*/
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
typedef struct __MMC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
{
MMC_TypeDef *Instance; /*!< MMC registers base address */
MMC_InitTypeDef Init; /*!< MMC required parameters */
HAL_LockTypeDef Lock; /*!< MMC locking object */
uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
__IO uint32_t Context; /*!< MMC transfer context */
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
uint32_t CSD[4U]; /*!< MMC card specific data table */
uint32_t CID[4U]; /*!< MMC card identification number table */
uint32_t Ext_CSD[128];
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
#endif
}MMC_HandleTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
* @{
*/
typedef struct
{
__IO uint8_t CSDStruct; /*!< CSD structure */
__IO uint8_t SysSpecVersion; /*!< System specification version */
__IO uint8_t Reserved1; /*!< Reserved */
__IO uint8_t TAAC; /*!< Data read access time 1 */
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
__IO uint16_t CardComdClasses; /*!< Card command classes */
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
__IO uint8_t DSRImpl; /*!< DSR implemented */
__IO uint8_t Reserved2; /*!< Reserved */
__IO uint32_t DeviceSize; /*!< Device Size */
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
__IO uint8_t EraseGrSize; /*!< Erase group size */
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
__IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
__IO uint8_t FileFormat; /*!< File format */
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_MMC_CardCSDTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
* @{
*/
typedef struct
{
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
__IO uint32_t ProdName1; /*!< Product Name part1 */
__IO uint8_t ProdName2; /*!< Product Name part2 */
__IO uint8_t ProdRev; /*!< Product Revision */
__IO uint32_t ProdSN; /*!< Product Serial Number */
__IO uint8_t Reserved1; /*!< Reserved1 */
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_MMC_CardCIDTypeDef;
/**
* @}
*/
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */
HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */
HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */
HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */
HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
}HAL_MMC_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
* @{
*/
typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
/**
* @}
*/
#endif
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MMC_Exported_Constants Exported Constants
* @{
*/
#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
* @{
*/
#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif
/**
* @}
*/
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
* @{
*/
#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
*/
/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
* @{
*/
/**
* @brief
*/
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */
#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */
#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
/**
* @}
*/
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
* @{
*/
#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */
#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup MMC_Exported_macros MMC Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/** @brief Reset MMC handle state.
* @param __HANDLE__ : MMC handle.
* @retval None
*/
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_MMC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
#endif
/**
* @brief Enable the MMC device.
* @retval None
*/
#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
/**
* @brief Disable the MMC device.
* @retval None
*/
#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
/**
* @brief Enable the SDMMC DMA transfer.
* @retval None
*/
#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
/**
* @brief Disable the SDMMC DMA transfer.
* @retval None
*/
#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
/**
* @brief Enable the MMC device interrupt.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the MMC device interrupt.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified MMC flag is set or not.
* @param __HANDLE__: MMC Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
* @arg SDIO_FLAG_RXACT: Data receive in progress
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
* @retval The new state of MMC FLAG (SET or RESET).
*/
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the MMC's pending flags.
* @param __HANDLE__: MMC Handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
* @retval None
*/
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified MMC interrupt has occurred or not.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval The new state of MMC IT (SET or RESET).
*/
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the MMC's interrupt pending bits.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MMC_Exported_Functions MMC Exported Functions
* @{
*/
/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
/* Callback in non blocking modes (DMA) */
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/* MMC callback registering/unregistering */
HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
#endif
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
* @{
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management
* @{
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup MMC_Private_Types MMC Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup MMC_Private_Defines MMC Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup MMC_Private_Variables MMC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup MMC_Private_Constants MMC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup MMC_Private_Macros MMC Private Macros
* @{
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MMC_Private_Functions MMC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* SDIO */
#endif /* STM32F1xx_HAL_MMC_H */

379
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/**
******************************************************************************
* @file stm32f1xx_hal_nand.h
* @author MCD Application Team
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_NAND_H
#define STM32F1xx_HAL_NAND_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FSMC_BANK3)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_fsmc.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup NAND
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Types NAND Exported Types
* @{
*/
/**
* @brief HAL NAND State structures definition
*/
typedef enum
{
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
} HAL_NAND_StateTypeDef;
/**
* @brief NAND Memory electronic signature Structure definition
*/
typedef struct
{
/*<! NAND memory electronic signature maker and device IDs */
uint8_t Maker_Id;
uint8_t Device_Id;
uint8_t Third_Id;
uint8_t Fourth_Id;
} NAND_IDTypeDef;
/**
* @brief NAND Memory address Structure definition
*/
typedef struct
{
uint16_t Page; /*!< NAND memory Page address */
uint16_t Plane; /*!< NAND memory Zone address */
uint16_t Block; /*!< NAND memory Block address */
} NAND_AddressTypeDef;
/**
* @brief NAND Memory info Structure definition
*/
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
for 8 bits addressing or words for 16 bits addressing */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
for 8 bits addressing or words for 16 bits addressing */
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
uint32_t PlaneNbr; /*!< NAND memory number of planes */
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequence in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
/**
* @brief NAND handle Structure definition
*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
typedef struct __NAND_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
{
FSMC_NAND_TypeDef *Instance; /*!< Register base address */
FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NAND locking object */
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
} NAND_HandleTypeDef;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/**
* @brief HAL NAND Callback ID enumeration definition
*/
typedef enum
{
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
} HAL_NAND_CallbackIDTypeDef;
/**
* @brief HAL NAND Callback pointer definition
*/
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
* @{
*/
/** @brief Reset NAND handle state
* @param __HANDLE__ specifies the NAND handle.
* @retval None
*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_NAND_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
* @{
*/
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* NAND Control functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* NAND State functions *******************************************************/
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
#define NAND_DEVICE1 0x70000000UL
#define NAND_DEVICE2 0x80000000UL
#define NAND_WRITE_TIMEOUT 0x01000000UL
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00)
#define NAND_CMD_AREA_B ((uint8_t)0x01)
#define NAND_CMD_AREA_C ((uint8_t)0x50)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define NAND_CMD_READID ((uint8_t)0x90)
#define NAND_CMD_STATUS ((uint8_t)0x70)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS 0x00000100UL
#define NAND_INVALID_ADDRESS 0x00000200UL
#define NAND_TIMEOUT_ERROR 0x00000400UL
#define NAND_BUSY 0x00000000UL
#define NAND_ERROR 0x00000001UL
#define NAND_READY 0x00000040UL
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup NAND_Private_Macros NAND Private Macros
* @{
*/
/**
* @brief NAND memory address computation.
* @param __ADDRESS__ NAND memory address.
* @param __HANDLE__ NAND handle.
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
(((__ADDRESS__)->Block + \
(((__ADDRESS__)->Plane) * \
((__HANDLE__)->Config.PlaneSize))) * \
((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
* @param __HANDLE__ NAND handle.
* @retval NAND Raw address value
*/
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
/**
* @brief NAND memory address cycling.
* @param __ADDRESS__ NAND memory address.
* @retval NAND address cycling value.
*/
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
/**
* @brief NAND memory Columns cycling.
* @param __ADDRESS__ NAND memory address.
* @retval NAND Column address cycling value.
*/
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK3 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_NAND_H */

326
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@@ -0,0 +1,326 @@
/**
******************************************************************************
* @file stm32f1xx_hal_nor.h
* @author MCD Application Team
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_NOR_H
#define STM32F1xx_HAL_NOR_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FSMC_BANK1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_fsmc.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup NOR
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup NOR_Exported_Types NOR Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
*/
typedef enum
{
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
} HAL_NOR_StateTypeDef;
/**
* @brief FSMC NOR Status typedef
*/
typedef enum
{
HAL_NOR_STATUS_SUCCESS = 0U,
HAL_NOR_STATUS_ONGOING,
HAL_NOR_STATUS_ERROR,
HAL_NOR_STATUS_TIMEOUT
} HAL_NOR_StatusTypeDef;
/**
* @brief FSMC NOR ID typedef
*/
typedef struct
{
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
uint16_t Device_Code1;
uint16_t Device_Code2;
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
These codes can be accessed by performing read operations with specific
control signals and addresses set.They can also be accessed by issuing
an Auto Select command */
} NOR_IDTypeDef;
/**
* @brief FSMC NOR CFI typedef
*/
typedef struct
{
/*!< Defines the information stored in the memory's Common flash interface
which contains a description of various electrical and timing parameters,
density information and functions supported by the memory */
uint16_t CFI_1;
uint16_t CFI_2;
uint16_t CFI_3;
uint16_t CFI_4;
} NOR_CFITypeDef;
/**
* @brief NOR handle Structure definition
*/
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
typedef struct __NOR_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
{
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NOR locking object */
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
uint32_t CommandSet; /*!< NOR algorithm command set and control */
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
} NOR_HandleTypeDef;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/**
* @brief HAL NOR Callback ID enumeration definition
*/
typedef enum
{
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
} HAL_NOR_CallbackIDTypeDef;
/**
* @brief HAL NOR Callback pointer definition
*/
typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NOR_Exported_Macros NOR Exported Macros
* @{
*/
/** @brief Reset NOR handle state
* @param __HANDLE__ specifies the NOR handle.
* @retval None
*/
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_NOR_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup NOR_Exported_Functions NOR Exported Functions
* @{
*/
/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
FSMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/* NOR callback registering/unregistering */
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
pNOR_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
* @{
*/
/* NOR Control functions *****************************************************/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
/**
* @}
*/
/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
* @{
*/
/* NOR State functions ********************************************************/
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NOR_Private_Constants NOR Private Constants
* @{
*/
/* NOR device IDs addresses */
#define MC_ADDRESS ((uint16_t)0x0000)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
#define CFI1_ADDRESS ((uint16_t)0x0061)
#define CFI2_ADDRESS ((uint16_t)0x0062)
#define CFI3_ADDRESS ((uint16_t)0x0063)
#define CFI4_ADDRESS ((uint16_t)0x0064)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFF)
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x00)
#define NOR_MEMORY_16B ((uint8_t)0x01)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 (0x60000000U)
#define NOR_MEMORY_ADRESS2 (0x64000000U)
#define NOR_MEMORY_ADRESS3 (0x68000000U)
#define NOR_MEMORY_ADRESS4 (0x6C000000U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup NOR_Private_Macros NOR Private Macros
* @{
*/
/**
* @brief NOR memory address shifting.
* @param __NOR_ADDRESS NOR base address
* @param __NOR_MEMORY_WIDTH_ NOR memory width
* @param __ADDRESS__ NOR memory address
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
/**
* @brief NOR memory write data to specified address.
* @param __ADDRESS__ NOR memory address
* @param __DATA__ Data to write
* @retval None
*/
#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
(*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
__DSB(); \
} while(0)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK1 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_NOR_H */

282
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pccard.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_pccard.h
* @author MCD Application Team
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_PCCARD_H
#define STM32F1xx_HAL_PCCARD_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FSMC_BANK4)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_fsmc.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup PCCARD
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
* @{
*/
/**
* @brief HAL PCCARD State structures definition
*/
typedef enum
{
HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
} HAL_PCCARD_StateTypeDef;
typedef enum
{
HAL_PCCARD_STATUS_SUCCESS = 0U,
HAL_PCCARD_STATUS_ONGOING,
HAL_PCCARD_STATUS_ERROR,
HAL_PCCARD_STATUS_TIMEOUT
} HAL_PCCARD_StatusTypeDef;
/**
* @brief FSMC_PCCARD handle Structure definition
*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
typedef struct __PCCARD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
{
FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
FSMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
__IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
} PCCARD_HandleTypeDef;
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
/**
* @brief HAL PCCARD Callback ID enumeration definition
*/
typedef enum
{
HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */
HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */
HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */
} HAL_PCCARD_CallbackIDTypeDef;
/**
* @brief HAL PCCARD Callback pointer definition
*/
typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
* @{
*/
/** @brief Reset PCCARD handle state
* @param __HANDLE__ specifies the PCCARD handle.
* @retval None
*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_PCCARD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCCARD_Exported_Functions
* @{
*/
/** @addtogroup PCCARD_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
/**
* @}
*/
/** @addtogroup PCCARD_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
/* PCCARD callback registering/unregistering */
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
pPCCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
HAL_PCCARD_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup PCCARD_Exported_Functions_Group3
* @{
*/
/* PCCARD State functions *******************************************************/
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
* @{
*/
#define PCCARD_DEVICE_ADDRESS 0x90000000U
#define PCCARD_ATTRIBUTE_SPACE_ADDRESS 0x98000000U /* Attribute space size to @0x9BFF FFFF */
#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
#define PCCARD_IO_SPACE_ADDRESS 0x9C000000U /* IO space size to @0x9FFF FFFF */
#define PCCARD_IO_SPACE_PRIMARY_ADDR 0x9C0001F0U /* IO space size to @0x9FFF FFFF */
/* Flash-ATA registers description */
#define ATA_DATA ((uint8_t)0x00) /* Data register */
#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
/* Flash-ATA commands */
#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
/* PC Card/Compact Flash status */
#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
#define PCCARD_BUSY ((uint8_t)0x80)
#define PCCARD_PROGR ((uint8_t)0x01)
#define PCCARD_READY ((uint8_t)0x40)
#define PCCARD_SECTOR_SIZE 255U /* In half words */
/**
* @}
*/
/* Compact Flash redefinition */
#define HAL_CF_Init HAL_PCCARD_Init
#define HAL_CF_DeInit HAL_PCCARD_DeInit
#define HAL_CF_MspInit HAL_PCCARD_MspInit
#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit
#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
#define HAL_CF_Reset HAL_PCCARD_Reset
#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler
#define HAL_CF_ITCallback HAL_PCCARD_ITCallback
#define HAL_CF_GetState HAL_PCCARD_GetState
#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS
#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING
#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR
#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef
#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
#define CF_BUSY PCCARD_BUSY
#define CF_PROGR PCCARD_PROGR
#define CF_READY PCCARD_READY
#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
/* Private macros ------------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK4 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_PCCARD_H */

1055
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_pcd.h
* @author MCD Application Team
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_PCD_H
#define STM32F1xx_HAL_PCD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_usb.h"
#if defined (USB) || defined (USB_OTG_FS)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup PCD
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PCD_Exported_Types PCD Exported Types
* @{
*/
/**
* @brief PCD State structure definition
*/
typedef enum
{
HAL_PCD_STATE_RESET = 0x00,
HAL_PCD_STATE_READY = 0x01,
HAL_PCD_STATE_ERROR = 0x02,
HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
/* Device LPM suspend state */
typedef enum
{
LPM_L0 = 0x00, /* on */
LPM_L1 = 0x01, /* LPM L1 sleep */
LPM_L2 = 0x02, /* suspend */
LPM_L3 = 0x03, /* off */
} PCD_LPM_StateTypeDef;
typedef enum
{
PCD_LPM_L0_ACTIVE = 0x00, /* on */
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
} PCD_LPM_MsgTypeDef;
typedef enum
{
PCD_BCD_ERROR = 0xFF,
PCD_BCD_CONTACT_DETECTION = 0xFE,
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
} PCD_BCD_MsgTypeDef;
#if defined (USB)
#endif /* defined (USB) */
#if defined (USB_OTG_FS)
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
typedef USB_TypeDef PCD_TypeDef;
typedef USB_CfgTypeDef PCD_InitTypeDef;
typedef USB_EPTypeDef PCD_EPTypeDef;
#endif /* defined (USB) */
/**
* @brief PCD Handle Structure definition
*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
typedef struct __PCD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
#if defined (USB_OTG_FS)
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
#endif /* defined (USB) */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
uint32_t FrameNumber; /*!< Store Current Frame number */
void *pData; /*!< Pointer to upper stack Handler */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
} PCD_HandleTypeDef;
/**
* @}
*/
/* Include PCD HAL Extended module */
#include "stm32f1xx_hal_pcd_ex.h"
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_FULL USBD_FS_SPEED
/**
* @}
*/
/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
#define PCD_PHY_ULPI 1U
#define PCD_PHY_EMBEDDED 2U
#define PCD_PHY_UTMI 3U
/**
* @}
*/
/** @defgroup PCD_Error_Code_definition PCD Error Code definition
* @brief PCD Error Code definition
* @{
*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#if defined (USB_OTG_FS)
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
} while(0U)
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
&= (uint16_t)(~(__INTERRUPT__)))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
} while(0U)
#endif /* defined (USB) */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
* @brief HAL USB OTG PCD Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
} HAL_PCD_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
* @brief HAL USB OTG PCD Callback pointer definition
* @{
*/
typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
/**
* @}
*/
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataInStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoInIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
/* I/O operation functions ***************************************************/
/* Non-Blocking mode: Interrupt */
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PCD_Private_Constants PCD Private Constants
* @{
*/
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
* @{
*/
#if defined (USB_OTG_FS)
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#endif /* defined (USB) */
/**
* @}
*/
#if defined (USB)
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
#define PCD_EP0MPS_64 EP_MPS_64
#define PCD_EP0MPS_32 EP_MPS_32
#define PCD_EP0MPS_16 EP_MPS_16
#define PCD_EP0MPS_08 EP_MPS_8
/**
* @}
*/
/** @defgroup PCD_ENDP PCD ENDP
* @{
*/
#define PCD_ENDP0 0U
#define PCD_ENDP1 1U
#define PCD_ENDP2 2U
#define PCD_ENDP3 3U
#define PCD_ENDP4 4U
#define PCD_ENDP5 5U
#define PCD_ENDP6 6U
#define PCD_ENDP7 7U
/**
* @}
*/
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
* @{
*/
#define PCD_SNG_BUF 0U
#define PCD_DBL_BUF 1U
/**
* @}
*/
#endif /* defined (USB) */
/**
* @}
*/
#if defined (USB_OTG_FS)
#ifndef USB_OTG_DOEPINT_OTEPSPR
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
#ifndef USB_OTG_DOEPMSK_OTEPSPRM
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
#ifndef USB_OTG_DOEPINT_NAK
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
#endif /* defined USB_OTG_DOEPINT_NAK */
#ifndef USB_OTG_DOEPMSK_NAKM
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
#endif /* defined USB_OTG_DOEPMSK_NAKM */
#ifndef USB_OTG_DOEPINT_STPKTRX
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
#endif /* defined USB_OTG_DOEPINT_STPKTRX */
#ifndef USB_OTG_DOEPMSK_NYETM
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
#endif /* defined USB_OTG_DOEPMSK_NYETM */
#endif /* defined (USB_OTG_FS) */
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
#if defined (USB)
/******************** Bit definition for USB_COUNTn_RX register *************/
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
#define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
(*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wType Endpoint Type.
* @retval None
*/
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval Endpoint Type
*/
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
/**
* @brief free buffer used from the application realizing it to the line
* toggles bit SW_BUF in the double buffered endpoint register
* @param USBx USB device.
* @param bEpNum, bDir
* @retval None
*/
#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
do { \
if ((bDir) == 0U) \
{ \
/* OUT double buffered endpoint */ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
else if ((bDir) == 1U) \
{ \
/* IN double buffered endpoint */ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TX_STATUS */
/**
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_RX_STATUS */
/**
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wStaterx new state.
* @param wStatetx new state.
* @retval None
*/
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TXRX_STATUS */
/**
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
* /STAT_RX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval status
*/
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
/**
* @brief sets directly the VALID tx/rx-status into the endpoint register
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
/**
* @brief checks stall condition in an endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval TRUE = endpoint in stall condition.
*/
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
/**
* @brief set & clear EP_KIND bit.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
} while(0) /* PCD_SET_EP_KIND */
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_EP_KIND */
/**
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_RX_EP_CTR */
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
} while(0) /* PCD_CLEAR_TX_EP_CTR */
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
} while(0) /* PCD_RX_DTOG */
#define PCD_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
} while(0) /* PCD_TX_DTOG */
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
{ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0) /* PCD_CLEAR_RX_DTOG */
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
{ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
} while(0) /* PCD_CLEAR_TX_DTOG */
/**
* @brief Sets address in an endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param bAddr Address.
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_ADDRESS */
/**
* @brief Gets address in an endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
#define PCD_EP_TX_CNT(USBx, bEpNum) \
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define PCD_EP_RX_CNT(USBx, bEpNum) \
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
/**
* @brief sets address of the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wAddr address to be set (must be word aligned).
* @retval None
*/
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_RX_ADDRESS */
/**
* @brief Gets address of the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval address of the buffer.
*/
#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
/**
* @brief Sets counter of rx buffer with no. of blocks.
* @param pdwReg Register pointer
* @param wCount Counter.
* @param wNBlocks no. of Blocks.
* @retval None
*/
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 5; \
if (((wCount) & 0x1fU) == 0U) \
{ \
(wNBlocks)--; \
} \
*(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 1; \
if (((wCount) & 0x1U) != 0U) \
{ \
(wNBlocks)++; \
} \
*(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
\
*(pdwReg) &= 0x3FFU; \
\
if ((wCount) > 62U) \
{ \
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
if ((wCount) == 0U) \
{ \
*(pdwReg) |= USB_CNTRX_BLSIZE; \
} \
else \
{ \
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *pdwReg; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
} while(0)
/**
* @brief sets counter for the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wCount Counter value.
* @retval None
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
*_wRegVal = (uint16_t)(wCount); \
} while(0)
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
} while(0)
/**
* @brief gets counter of the tx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval Counter value
*/
#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
/**
* @brief Sets buffer 0/1 address in a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wBuf0Addr buffer 0 address.
* @retval Counter value
*/
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
do { \
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
do { \
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
/**
* @brief Sets addresses in a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wBuf0Addr: buffer 0 address.
* @param wBuf1Addr = buffer 1 address.
* @retval None
*/
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
do { \
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF_ADDR */
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param bDir endpoint dir EP_DBUF_OUT = OUT
* EP_DBUF_IN = IN
* @param wCount: Counter value
* @retval None
*/
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
do { \
if ((bDir) == 0U) \
/* OUT endpoint */ \
{ \
PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
} \
else \
{ \
if ((bDir) == 1U) \
{ \
/* IN endpoint */ \
PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
} \
} \
} while(0) /* SetEPDblBuf0Count*/
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
do { \
uint32_t _wBase = (uint32_t)(USBx); \
__IO uint16_t *_wEPRegVal; \
\
if ((bDir) == 0U) \
{ \
/* OUT endpoint */ \
PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
} \
else \
{ \
if ((bDir) == 1U) \
{ \
/* IN endpoint */ \
_wBase += (uint32_t)(USBx)->BTABLE; \
_wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
*_wEPRegVal = (uint16_t)(wCount); \
} \
} \
} while(0) /* SetEPDblBuf1Count */
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
do { \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
} while(0) /* PCD_SET_EP_DBUF_CNT */
/**
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
#endif /* defined (USB) */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_PCD_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_pcd_ex.h
* @author MCD Application Team
* @brief Header file of PCD HAL Extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_PCD_EX_H
#define STM32F1xx_HAL_PCD_EX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
#if defined (USB) || defined (USB_OTG_FS)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup PCDEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
#if defined (USB_OTG_FS)
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress);
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
#endif /* defined (USB) */
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32F1xx_HAL_PCD_EX_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_sd.h
* @author MCD Application Team
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_SD_H
#define STM32F1xx_HAL_SD_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(SDIO)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_sdmmc.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup SD SD
* @brief SD HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SD_Exported_Types SD Exported Types
* @{
*/
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
* @{
*/
typedef enum
{
HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
}HAL_SD_StateTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
* @{
*/
typedef uint32_t HAL_SD_CardStateTypeDef;
#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */
#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
* @{
*/
#define SD_InitTypeDef SDIO_InitTypeDef
#define SD_TypeDef SDIO_TypeDef
/**
* @brief SD Card Information Structure definition
*/
typedef struct
{
uint32_t CardType; /*!< Specifies the card Type */
uint32_t CardVersion; /*!< Specifies the card version */
uint32_t Class; /*!< Specifies the class of the card class */
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
uint32_t BlockSize; /*!< Specifies one block size in bytes */
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
}HAL_SD_CardInfoTypeDef;
/**
* @brief SD handle Structure definition
*/
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
typedef struct __SD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
{
SD_TypeDef *Instance; /*!< SD registers base address */
SD_InitTypeDef Init; /*!< SD required parameters */
HAL_LockTypeDef Lock; /*!< SD locking object */
uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */
uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint32_t RxXferSize; /*!< SD Rx Transfer size */
__IO uint32_t Context; /*!< SD transfer context */
__IO HAL_SD_StateTypeDef State; /*!< SD card State */
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
uint32_t CSD[4]; /*!< SD card specific data table */
uint32_t CID[4]; /*!< SD card identification number table */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}SD_HandleTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
* @{
*/
typedef struct
{
__IO uint8_t CSDStruct; /*!< CSD structure */
__IO uint8_t SysSpecVersion; /*!< System specification version */
__IO uint8_t Reserved1; /*!< Reserved */
__IO uint8_t TAAC; /*!< Data read access time 1 */
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
__IO uint16_t CardComdClasses; /*!< Card command classes */
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
__IO uint8_t DSRImpl; /*!< DSR implemented */
__IO uint8_t Reserved2; /*!< Reserved */
__IO uint32_t DeviceSize; /*!< Device Size */
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
__IO uint8_t EraseGrSize; /*!< Erase group size */
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
__IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
__IO uint8_t FileFormat; /*!< File format */
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_SD_CardCSDTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
* @{
*/
typedef struct
{
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
__IO uint32_t ProdName1; /*!< Product Name part1 */
__IO uint8_t ProdName2; /*!< Product Name part2 */
__IO uint8_t ProdRev; /*!< Product Revision */
__IO uint32_t ProdSN; /*!< Product Serial Number */
__IO uint8_t Reserved1; /*!< Reserved1 */
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_SD_CardCIDTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
* @{
*/
typedef struct
{
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
__IO uint16_t CardType; /*!< Carries information about card type */
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
}HAL_SD_CardStatusTypeDef;
/**
* @}
*/
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */
HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */
HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */
HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */
HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
}HAL_SD_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
* @{
*/
typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
/**
* @}
*/
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SD_Exported_Constants Exported Constants
* @{
*/
#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
* @{
*/
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
* @{
*/
#define SD_CONTEXT_NONE 0x00000000U /*!< None */
#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
*/
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
* @{
*/
#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */
#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
#define CARD_SECURED 0x00000003U
/**
* @}
*/
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
* @{
*/
#define CARD_V1_X 0x00000000U
#define CARD_V2_X 0x00000001U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SD_Exported_macros SD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/** @brief Reset SD handle state.
* @param __HANDLE__ : SD handle.
* @retval None
*/
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @brief Enable the SD device.
* @retval None
*/
#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
/**
* @brief Disable the SD device.
* @retval None
*/
#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
/**
* @brief Enable the SDMMC DMA transfer.
* @retval None
*/
#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
/**
* @brief Disable the SDMMC DMA transfer.
* @retval None
*/
#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
/**
* @brief Enable the SD device interrupt.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the SD device interrupt.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified SD flag is set or not.
* @param __HANDLE__: SD Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
* @arg SDIO_FLAG_RXACT: Data receive in progress
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SD FLAG (SET or RESET).
*/
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the SD's pending flags.
* @param __HANDLE__: SD Handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified SD interrupt has occurred or not.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SD IT (SET or RESET).
*/
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the SD's interrupt pending bits.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SD_Exported_Functions SD Exported Functions
* @{
*/
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
/* Callback in non blocking modes (DMA) */
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* SD callback registering/unregistering */
HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
* @{
*/
HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
* @{
*/
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup SD_Private_Types SD Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup SD_Private_Defines SD Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup SD_Private_Variables SD Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SD_Private_Constants SD Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SD_Private_Macros SD Private Macros
* @{
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SD_Private_Functions SD Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* SDIO */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_SD_H */

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john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_smartcard.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_smartcard.h
* @author MCD Application Team
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_SMARTCARD_H
#define __STM32F1xx_HAL_SMARTCARD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup SMARTCARD
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
* @{
*/
/**
* @brief SMARTCARD Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (hsc->Init.BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref SMARTCARD_Word_Length */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref SMARTCARD_Stop_Bits */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref SMARTCARD_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits).*/
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref SMARTCARD_Mode */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SMARTCARD_Clock_Phase */
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
to provide the smartcard clock. The value given in the register (5 significant bits)
is multiplied by 2 to give the division factor of the source clock frequency.
This parameter can be a value of @ref SMARTCARD_Prescaler */
uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
This parameter can be a value of @ref SMARTCARD_NACK_State */
}SMARTCARD_InitTypeDef;
/**
* @brief HAL SMARTCARD State structures definition
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
* - gState contains SMARTCARD state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initialization status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
Value is allowed for gState only */
HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
}HAL_SMARTCARD_StateTypeDef;
/**
* @brief SMARTCARD handle Structure definition
*/
typedef struct __SMARTCARD_HandleTypeDef
{
USART_TypeDef *Instance; /*!< USART registers base address */
SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
__IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
__IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Tx Complete Callback */
void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Rx Complete Callback */
void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Error Callback */
void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Receive Complete Callback */
void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp Init callback */
void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp DeInit callback */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
} SMARTCARD_HandleTypeDef;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SMARTCARD Callback ID enumeration definition
*/
typedef enum
{
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
} HAL_SMARTCARD_CallbackIDTypeDef;
/**
* @brief HAL SMARTCARD Callback pointer definition
*/
typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc); /*!< pointer to an SMARTCARD callback function */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
* @{
*/
/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
* @{
*/
#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< Overrun error */
#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
/**
* @}
*/
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
*/
#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
/** @defgroup SMARTCARD_Mode SMARTCARD Mode
* @{
*/
#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
/**
* @}
*/
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
#define SMARTCARD_POLARITY_LOW 0x00000000U
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
*/
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
#define SMARTCARD_PHASE_1EDGE 0x00000000U
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
/**
* @}
*/
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
/**
* @}
*/
/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
* @{
*/
#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define SMARTCARD_NACK_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
* @{
*/
#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
/**
* @}
*/
/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
* @{
*/
#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
/**
* @}
*/
/** @defgroup SmartCard_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)
#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)
#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the Y register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
* - 11: CR3 register
* @{
*/
#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
* @{
*/
/** @brief Reset SMARTCARD handle gstate & RxState
* @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/** @brief Flush the Smartcard DR register
* @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
/** @brief Check whether the specified Smartcard flag is set or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
* @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
* @arg SMARTCARD_FLAG_ORE: Overrun Error flag
* @arg SMARTCARD_FLAG_NE: Noise Error flag
* @arg SMARTCARD_FLAG_FE: Framing Error flag
* @arg SMARTCARD_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified Smartcard pending flags.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
*
* @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
* error) flags are cleared by software sequence: a read operation to
* USART_SR register followed by a read operation to USART_DR register.
* @note RXNE flag can be also cleared by a read to the USART_DR register.
* @note TC flag can be also cleared by software sequence: a read operation to
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the SMARTCARD PE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0U)
/** @brief Clear the SMARTCARD FE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD NE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD ORE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD IDLE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__ specifies the SmartCard Handle.
* @param __IT__ specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_ERR: Error interrupt
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
/** @brief Enable the USART associated to the SMARTCARD Handle
* @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable the USART associated to the SMARTCARD Handle
* @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/** @brief Macros to enable the SmartCard DMA request.
* @param __HANDLE__ specifies the SmartCard Handle.
* @param __REQUEST__ specifies the SmartCard DMA request.
* This parameter can be one of the following values:
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
* @retval None
*/
#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
/** @brief Macros to disable the SmartCard DMA request.
* @param __HANDLE__ specifies the SmartCard Handle.
* @param __REQUEST__ specifies the SmartCard DMA request.
* This parameter can be one of the following values:
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
* @retval None
*/
#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARD_Exported_Functions
* @{
*/
/** @addtogroup SMARTCARD_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SMARTCARD_Exported_Functions_Group2
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/
/** @addtogroup SMARTCARD_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions **************************************************/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc);
uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
/** @brief SMARTCARD interruptions flag mask
*
*/
#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
USART_CR1_IDLEIE | USART_CR3_EIE )
#define SMARTCARD_CR1_REG_INDEX 1U
#define SMARTCARD_CR3_REG_INDEX 3U
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
* @{
*/
#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
((STOPBITS) == SMARTCARD_STOPBITS_1_5))
#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
((PARITY) == SMARTCARD_PARITY_ODD))
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
((NACK) == SMARTCARD_NACK_DISABLE))
#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25U)/(4U*(__BAUD__)))
#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U)
/* SMARTCARD BRR = mantissa + overflow + fraction
= (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
#define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0xF0U)) + \
(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0FU))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_SMARTCARD_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_sram.h
* @author MCD Application Team
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_SRAM_H
#define STM32F1xx_HAL_SRAM_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FSMC_BANK1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_fsmc.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup SRAM
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup SRAM_Exported_Types SRAM Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
*/
typedef enum
{
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
} HAL_SRAM_StateTypeDef;
/**
* @brief SRAM handle Structure definition
*/
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
typedef struct __SRAM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
{
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
HAL_LockTypeDef Lock; /*!< SRAM locking object */
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
} SRAM_HandleTypeDef;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SRAM Callback ID enumeration definition
*/
typedef enum
{
HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
} HAL_SRAM_CallbackIDTypeDef;
/**
* @brief HAL SRAM Callback pointer definition
*/
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
* @{
*/
/** @brief Reset SRAM handle state
* @param __HANDLE__ SRAM handle
* @retval None
*/
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
FSMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/* SRAM callback registering/unregistering */
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_DmaCallbackTypeDef pCallback);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
* @{
*/
/* SRAM Control functions ****************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK1 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_SRAM_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_usart.h
* @author MCD Application Team
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_USART_H
#define __STM32F1xx_HAL_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup USART_Exported_Types USART Exported Types
* @{
*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (husart->Init.BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
} HAL_USART_StateTypeDef;
/**
* @brief USART handle Structure definition
*/
typedef struct __USART_HandleTypeDef
{
USART_TypeDef *Instance; /*!< USART registers base address */
USART_InitTypeDef Init; /*!< Usart communication parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
uint16_t TxXferSize; /*!< Usart Tx Transfer size */
__IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
uint16_t RxXferSize; /*!< Usart Rx Transfer size */
__IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
__IO uint32_t ErrorCode; /*!< USART Error code */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
} USART_HandleTypeDef;
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
/**
* @brief HAL USART Callback ID enumeration definition
*/
typedef enum
{
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
HAL_USART_MSPINIT_CB_ID = 0x07U, /*!< USART MspInit callback ID */
HAL_USART_MSPDEINIT_CB_ID = 0x08U /*!< USART MspDeInit callback ID */
} HAL_USART_CallbackIDTypeDef;
/**
* @brief HAL USART Callback pointer definition
*/
typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_Exported_Constants USART Exported Constants
* @{
*/
/** @defgroup USART_Error_Code USART Error Code
* @brief USART Error Code
* @{
*/
#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup USART_Word_Length USART Word Length
* @{
*/
#define USART_WORDLENGTH_8B 0x00000000U
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
#define USART_STOPBITS_1 0x00000000U
#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
/**
* @}
*/
/** @defgroup USART_Parity USART Parity
* @{
*/
#define USART_PARITY_NONE 0x00000000U
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
/** @defgroup USART_Mode USART Mode
* @{
*/
#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
/**
* @}
*/
/** @defgroup USART_Clock USART Clock
* @{
*/
#define USART_CLOCK_DISABLE 0x00000000U
#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
/**
* @}
*/
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
#define USART_POLARITY_LOW 0x00000000U
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
*/
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
#define USART_PHASE_1EDGE 0x00000000U
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
/**
* @}
*/
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
#define USART_LASTBIT_DISABLE 0x00000000U
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
/**
* @}
*/
/** @defgroup USART_NACK_State USART NACK State
* @{
*/
#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define USART_NACK_DISABLE 0x00000000U
/**
* @}
*/
/** @defgroup USART_Flags USART Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define USART_FLAG_TC ((uint32_t)USART_SR_TC)
#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define USART_FLAG_NE ((uint32_t)USART_SR_NE)
#define USART_FLAG_FE ((uint32_t)USART_SR_FE)
#define USART_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask in the XX register
* - Y : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* @{
*/
#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup USART_Exported_Macros USART Exported Macros
* @{
*/
/** @brief Reset USART handle state
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg USART_FLAG_TXE: Transmit data register empty flag
* @arg USART_FLAG_TC: Transmission Complete flag
* @arg USART_FLAG_RXNE: Receive data register not empty flag
* @arg USART_FLAG_IDLE: Idle Line detection flag
* @arg USART_FLAG_ORE: Overrun Error flag
* @arg USART_FLAG_NE: Noise Error flag
* @arg USART_FLAG_FE: Framing Error flag
* @arg USART_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified USART pending flags.
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg USART_FLAG_TC: Transmission Complete flag.
* @arg USART_FLAG_RXNE: Receive data register not empty flag.
*
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
* @note RXNE flag can be also cleared by a read to the USART_DR register.
* @note TC flag can be also cleared by software sequence: a read operation to
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
*
* @retval None
*/
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the USART PE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0U)
/** @brief Clear the USART FE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART NE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART ORE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART IDLE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enables or disables the specified USART interrupts.
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_PE: Parity Error interrupt
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
(((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
(((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
/** @brief Checks whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __IT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_ERR: Error interrupt
* @arg USART_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
/** @brief Macro to enable the USART's one bit sample method
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
/** @brief Macro to disable the USART's one bit sample method
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
/** @brief Enable USART
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable USART
* @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USART_Exported_Functions
* @{
*/
/** @addtogroup USART_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup USART_Exported_Functions_Group2
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
/**
* @}
*/
/** @addtogroup USART_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup USART_Private_Constants USART Private Constants
* @{
*/
/** @brief USART interruptions flag mask
*
*/
#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
#define USART_CR1_REG_INDEX 1U
#define USART_CR2_REG_INDEX 2U
#define USART_CR3_REG_INDEX 3U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup USART_Private_Macros USART Private Macros
* @{
*/
#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
((NACK) == USART_NACK_DISABLE))
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
((LASTBIT) == USART_LASTBIT_ENABLE))
#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || \
((CPHA) == USART_PHASE_2EDGE))
#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || \
((CPOL) == USART_POLARITY_HIGH))
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
((CLOCK) == USART_CLOCK_ENABLE))
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
((LENGTH) == USART_WORDLENGTH_9B))
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
((STOPBITS) == USART_STOPBITS_0_5) || \
((STOPBITS) == USART_STOPBITS_1_5) || \
((STOPBITS) == USART_STOPBITS_2))
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
((PARITY) == USART_PARITY_EVEN) || \
((PARITY) == USART_PARITY_ODD))
#define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00U))
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4500000U)
#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
#define USART_DIVFRAQ(_PCLK_, _BAUD_) ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF0) << 1) + (UART DIVFRAQ & 0x0FU) */
#define USART_BRR(_PCLK_, _BAUD_) (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U) << 1U)) + \
(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup USART_Private_Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_USART_H */

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/**
******************************************************************************
* @file stm32f1xx_hal_wwdg.h
* @author MCD Application Team
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_WWDG_H
#define STM32F1xx_HAL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Types WWDG Exported Types
* @{
*/
/**
* @brief WWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
This parameter can be a value of @ref WWDG_Prescaler */
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
/**
* @brief WWDG handle Structure definition
*/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/**
* @brief HAL WWDG common Callback ID enumeration definition
*/
typedef enum
{
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
*/
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
/** @defgroup WWDG_Flag_definition WWDG Flag definition
* @brief WWDG Flag definition
* @{
*/
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
* @{
*/
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
((__PRESCALER__) == WWDG_PRESCALER_2) || \
((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8))
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
((__MODE__) == WWDG_EWI_DISABLE))
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
* @{
*/
/**
* @brief Enable the WWDG peripheral.
* @param __HANDLE__ WWDG handle
* @retval None
*/
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
* @brief Enable the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
*/
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
/**
* @brief Check whether the selected WWDG interrupt has occurred or not.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the it to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
/** @brief Clear the WWDG interrupt pending bits.
* bits to clear the selected interrupt pending bits.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
*/
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/**
* @brief Check whether the specified WWDG flag is set or not.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the WWDG's pending flags.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval None
*/
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
* @param __HANDLE__ WWDG Handle.
* @param __INTERRUPT__ specifies the WWDG interrupt source to check.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
& (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup WWDG_Exported_Functions
* @{
*/
/** @addtogroup WWDG_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup WWDG_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_HAL_WWDG_H */

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/**
******************************************************************************
* @file stm32f1xx_ll_crc.h
* @author MCD Application Team
* @brief Header file of CRC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_CRC_H
#define STM32F1xx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(CRC)
/** @defgroup CRC_LL CRC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
* @{
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
* @{
*/
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
* @{
*/
/**
* @brief Reset the CRC calculation unit.
* @note If Programmable Initial CRC value feature
* is available, also set the Data Register to the value stored in the
* CRC_INIT register, otherwise, reset Data Register to its default value.
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
* @param CRCx CRC Instance
* @retval None
*/
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
{
SET_BIT(CRCx->CR, CRC_CR_RESET);
}
/**
* @}
*/
/** @defgroup CRC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write given 32-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData32
* @param CRCx CRC Instance
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
{
WRITE_REG(CRCx->DR, InData);
}
/**
* @brief Return current CRC calculation result. 32 bits value is returned.
* @rmtoll DR DR LL_CRC_ReadData32
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
/**
* @brief Return data stored in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one byte.
* @rmtoll IDR IDR LL_CRC_Read_IDR
* @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
*/
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->IDR));
}
/**
* @brief Store data in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one byte.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
* @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
{
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_CRC_H */

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/**
******************************************************************************
* @file stm32f1xx_ll_dac.h
* @author MCD Application Team
* @brief Header file of DAC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_DAC_H
#define STM32F1xx_LL_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(DAC)
/** @defgroup DAC_LL DAC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup DAC_LL_Private_Constants DAC Private Constants
* @{
*/
/* Internal masks for DAC channels definition */
/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
/* - channel bits position into register SWTRIG */
/* - channel register offset of data holding register DHRx */
/* - channel register offset of data output register DORx */
#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
CR, MCR, CCR, SHHR, SHRR of channel 1 */
#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
DHR12Rx channel 1 (shifted left of 20 bits) */
#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
DHR12Rx channel 1 (shifted left of 24 bits) */
#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
DHR12Rx channel 1 (shifted left of 16 bits) */
#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
DHR12Rx channel 1 (shifted left of 20 bits) */
#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
DHR12Rx channel 1 (shifted left of 24 bits) */
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
| DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
DORx channel 2 (shifted left of 28 bits) */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
to position 0 */
#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
to position 0 */
#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
channel 1 or 2 versus DHR12Rx channel 1
(shifted left of 16 bits) */
#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
channel 1 or 2 versus DHR12Rx channel 1
(shifted left of 20 bits) */
#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
channel 1 or 2 versus DHR12Rx channel 1
(shifted left of 24 bits) */
#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
channel 1 or 2 versus DORx channel 1
(shifted left of 28 bits) */
/* DAC registers bits positions */
#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
/* Miscellaneous data */
#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
bits (voltage range determined by analog voltage
references Vref+ and Vref-, refer to reference manual) */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DAC_LL_Private_Macros DAC Private Macros
* @{
*/
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
*/
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of DAC instance.
*/
typedef struct
{
uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
internal (SW start) or from external peripheral
(timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetTriggerSource(). */
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetWaveAutoGeneration(). */
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
If waveform automatic generation mode is set to noise, this parameter
can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
If waveform automatic generation mode is set to triangle,
this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
@note If waveform automatic generation mode is disabled,
this parameter is discarded.
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetWaveNoiseLFSR(),
@ref LL_DAC_SetWaveTriangleAmplitude()
depending on the wave automatic generation selected. */
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetOutputBuffer(). */
} LL_DAC_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
* @{
*/
/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
* @brief Flags defines which can be used with LL_DAC_ReadReg function
* @{
*/
/* DAC channel 1 flags */
#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
/* DAC channel 2 flags */
#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
/**
* @}
*/
/** @defgroup DAC_LL_EC_IT DAC interruptions
* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
* @{
*/
#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
/**
* @}
*/
/** @defgroup DAC_LL_EC_CHANNEL DAC channels
* @{
*/
#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
/**
* @}
*/
/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
* @{
*/
#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */
#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
/**
* @}
*/
/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
* @{
*/
#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
/**
* @}
*/
/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
* @{
*/
#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
/**
* @}
*/
/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
* @{
*/
#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
/**
* @}
*/
/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
* @{
*/
#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
/**
* @}
*/
/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
* @{
*/
#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
/**
* @}
*/
/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
* @{
*/
/* List of DAC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
/**
* @}
*/
/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
* @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Delay for DAC channel voltage settling time from DAC channel startup */
/* (transition from disable to enable). */
/* Note: DAC channel startup time depends on board application environment: */
/* impedance connected to DAC channel output. */
/* The delay below is specified under conditions: */
/* - voltage maximum transition (lowest to highest value) */
/* - until voltage reaches final value +-1LSB */
/* - DAC channel output buffer enabled */
/* - load impedance of 5kOhm (min), 50pF (max) */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
/* Delay for DAC channel voltage settling time. */
/* Note: DAC channel startup time depends on board application environment: */
/* impedance connected to DAC channel output. */
/* The delay below is specified under conditions: */
/* - voltage maximum transition (lowest to highest value) */
/* - until voltage reaches final value +-1LSB */
/* - DAC channel output buffer enabled */
/* - load impedance of 5kOhm min, 50pF max */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSETTLING"). */
/* Unit: us */
#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
* @{
*/
/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
* @{
*/
/**
* @brief Write a value in DAC register
* @param __INSTANCE__ DAC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in DAC register
* @param __INSTANCE__ DAC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
* @{
*/
/**
* @brief Helper macro to get DAC channel number in decimal format
* from literals LL_DAC_CHANNEL_x.
* Example:
* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
* will return decimal number "1".
* @note The input can be a value from functions where a channel
* number is returned.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval 1...2
*/
#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
((__CHANNEL__) & DAC_SWTR_CHX_MASK)
/**
* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
* from number in decimal format.
* Example:
* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
* will return a data equivalent to "LL_DAC_CHANNEL_1".
* @note If the input parameter does not correspond to a DAC channel,
* this macro returns value '0'.
* @param __DECIMAL_NB__ 1...2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
*/
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
(((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
/**
* @brief Helper macro to define the DAC conversion data full-scale digital
* value corresponding to the selected DAC resolution.
* @note DAC conversion data full-scale corresponds to voltage range
* determined by analog voltage references Vref+ and Vref-
* (refer to reference manual).
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_DAC_RESOLUTION_12B
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
/**
* @brief Helper macro to calculate the DAC conversion data (unit: digital
* value) corresponding to a voltage (unit: mVolt).
* @note This helper macro is intended to provide input data in voltage
* rather than digital value,
* to be used with LL DAC functions such as
* @ref LL_DAC_ConvertData12RightAligned().
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
* (unit: mVolt).
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_DAC_RESOLUTION_12B
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval DAC conversion data (unit: digital value)
*/
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
/ (__VREFANALOG_VOLTAGE__) \
)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
* @{
*/
/**
* @brief Set the conversion trigger source for the selected DAC channel.
* @note For conversion trigger source to be effective, DAC trigger
* must be enabled using function @ref LL_DAC_EnableTrigger().
* @note To set conversion trigger source, DAC channel must be disabled.
* Otherwise, the setting is discarded.
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
* CR TSEL2 LL_DAC_SetTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
{
MODIFY_REG(DACx->CR,
DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the conversion trigger source for the selected DAC channel.
* @note For conversion trigger source to be effective, DAC trigger
* must be enabled using function @ref LL_DAC_EnableTrigger().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
* CR TSEL2 LL_DAC_GetTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
*/
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the waveform automatic generation mode
* for the selected DAC channel.
* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
* CR WAVE2 LL_DAC_SetWaveAutoGeneration
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param WaveAutoGeneration This parameter can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
{
MODIFY_REG(DACx->CR,
DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the waveform automatic generation mode
* for the selected DAC channel.
* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
* CR WAVE2 LL_DAC_GetWaveAutoGeneration
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the noise waveform generation for the selected DAC channel:
* Noise mode and parameters LFSR (linear feedback shift register).
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param NoiseLFSRMask This parameter can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
{
MODIFY_REG(DACx->CR,
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the noise waveform generation for the selected DAC channel:
* Noise mode and parameters LFSR (linear feedback shift register).
* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the triangle waveform generation for the selected DAC channel:
* triangle mode and amplitude.
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param TriangleAmplitude This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
uint32_t TriangleAmplitude)
{
MODIFY_REG(DACx->CR,
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the triangle waveform generation for the selected DAC channel:
* triangle mode and amplitude.
* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the output buffer for the selected DAC channel.
* @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
* CR BOFF2 LL_DAC_SetOutputBuffer
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param OutputBuffer This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
{
MODIFY_REG(DACx->CR,
DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the output buffer state for the selected DAC channel.
* @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
* CR BOFF2 LL_DAC_GetOutputBuffer
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
*/
__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Enable DAC DMA transfer request of the selected channel.
* @note To configure DMA source address (peripheral address),
* use function @ref LL_DAC_DMA_GetRegAddr().
* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
* CR DMAEN2 LL_DAC_EnableDMAReq
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC DMA transfer request of the selected channel.
* @note To configure DMA source address (peripheral address),
* use function @ref LL_DAC_DMA_GetRegAddr().
* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
* CR DMAEN2 LL_DAC_DisableDMAReq
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC DMA transfer request state of the selected channel.
* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
* CR DMAEN2 LL_DAC_IsDMAReqEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Function to help to configure DMA transfer to DAC: retrieve the
* DAC register address from DAC instance and a list of DAC registers
* intended to be used (most commonly) with DMA transfer.
* @note These DAC registers are data holding registers:
* when DAC conversion is requested, DAC generates a DMA transfer
* request to have data available in DAC data holding registers.
* @note This macro is intended to be used with LL DMA driver, refer to
* function "LL_DMA_ConfigAddresses()".
* Example:
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* (uint32_t)&< array or variable >,
* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
* LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param Register This parameter can be one of the following values:
* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
* @retval DAC register address
*/
__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
* @{
*/
/**
* @brief Enable DAC selected channel.
* @rmtoll CR EN1 LL_DAC_Enable\n
* CR EN2 LL_DAC_Enable
* @note After enable from off state, DAC channel requires a delay
* for output voltage to reach accuracy +/- 1 LSB.
* Refer to device datasheet, parameter "tWAKEUP".
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC selected channel.
* @rmtoll CR EN1 LL_DAC_Disable\n
* CR EN2 LL_DAC_Disable
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC enable state of the selected channel.
* (0: DAC channel is disabled, 1: DAC channel is enabled)
* @rmtoll CR EN1 LL_DAC_IsEnabled\n
* CR EN2 LL_DAC_IsEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Enable DAC trigger of the selected channel.
* @note - If DAC trigger is disabled, DAC conversion is performed
* automatically once the data holding register is updated,
* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
* @ref LL_DAC_ConvertData12RightAligned(), ...
* - If DAC trigger is enabled, DAC conversion is performed
* only when a hardware of software trigger event is occurring.
* Select trigger source using
* function @ref LL_DAC_SetTriggerSource().
* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
* CR TEN2 LL_DAC_EnableTrigger
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC trigger of the selected channel.
* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
* CR TEN2 LL_DAC_DisableTrigger
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC trigger state of the selected channel.
* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
* CR TEN2 LL_DAC_IsTriggerEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Trig DAC conversion by software for the selected DAC channel.
* @note Preliminarily, DAC trigger must be set to software trigger
* using function
* @ref LL_DAC_Init()
* @ref LL_DAC_SetTriggerSource()
* with parameter "LL_DAC_TRIGGER_SOFTWARE".
* and DAC trigger must be enabled using
* function @ref LL_DAC_EnableTrigger().
* @note For devices featuring DAC with 2 channels: this function
* can perform a SW start of both DAC channels simultaneously.
* Two channels can be selected as parameter.
* Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
* @param DACx DAC instance
* @param DAC_Channel This parameter can a combination of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->SWTRIGR,
(DAC_Channel & DAC_SWTR_CHX_MASK));
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (LSB aligned on bit 0),
* for the selected DAC channel.
* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (MSB aligned on bit 15),
* for the selected DAC channel.
* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 8 bits left alignment (LSB aligned on bit 0),
* for the selected DAC channel.
* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (LSB aligned on bit 0),
* for both DAC channels.
* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
* @param DACx DAC instance
* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR12RD,
(DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (MSB aligned on bit 15),
* for both DAC channels.
* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
* @param DACx DAC instance
* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
uint32_t DataChannel2)
{
/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
/* the 4 LSB must be taken into account for the shift value. */
MODIFY_REG(DACx->DHR12LD,
(DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 8 bits left alignment (LSB aligned on bit 0),
* for both DAC channels.
* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
* @param DACx DAC instance
* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR8RD,
(DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
}
/**
* @brief Retrieve output data currently generated for the selected DAC channel.
* @note Whatever alignment and resolution settings
* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
* @ref LL_DAC_ConvertData12RightAligned(), ...),
* output data format is 12 bits right aligned (LSB aligned on bit 0).
* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
* @{
*/
#if defined(DAC_SR_DMAUDR1)
/**
* @brief Get DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
}
#endif /* DAC_SR_DMAUDR1 */
#if defined(DAC_SR_DMAUDR2)
/**
* @brief Get DAC underrun flag for DAC channel 2
* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
}
#endif /* DAC_SR_DMAUDR2 */
#if defined(DAC_SR_DMAUDR1)
/**
* @brief Clear DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
{
WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
}
#endif /* DAC_SR_DMAUDR1 */
#if defined(DAC_SR_DMAUDR2)
/**
* @brief Clear DAC underrun flag for DAC channel 2
* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
{
WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
}
#endif /* DAC_SR_DMAUDR2 */
/**
* @}
*/
/** @defgroup DAC_LL_EF_IT_Management IT management
* @{
*/
#if defined(DAC_CR_DMAUDRIE1)
/**
* @brief Enable DMA underrun interrupt for DAC channel 1
* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
{
SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
}
#endif /* DAC_CR_DMAUDRIE1 */
#if defined(DAC_CR_DMAUDRIE2)
/**
* @brief Enable DMA underrun interrupt for DAC channel 2
* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
{
SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
}
#endif /* DAC_CR_DMAUDRIE2 */
#if defined(DAC_CR_DMAUDRIE1)
/**
* @brief Disable DMA underrun interrupt for DAC channel 1
* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
{
CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
}
#endif /* DAC_CR_DMAUDRIE1 */
#if defined(DAC_CR_DMAUDRIE2)
/**
* @brief Disable DMA underrun interrupt for DAC channel 2
* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
{
CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
}
#endif /* DAC_CR_DMAUDRIE2 */
#if defined(DAC_CR_DMAUDRIE1)
/**
* @brief Get DMA underrun interrupt for DAC channel 1
* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
}
#endif /* DAC_CR_DMAUDRIE1 */
#if defined(DAC_CR_DMAUDRIE2)
/**
* @brief Get DMA underrun interrupt for DAC channel 2
* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
}
#endif /* DAC_CR_DMAUDRIE2 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* DAC */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_DAC_H */

969
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h Normal file
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@@ -0,0 +1,969 @@
/**
******************************************************************************
* @file stm32f1xx_ll_fsmc.h
* @author MCD Application Team
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_FSMC_H
#define STM32F1xx_LL_FSMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup FSMC_LL
* @{
*/
/** @addtogroup FSMC_LL_Private_Macros
* @{
*/
#if defined(FSMC_BANK1)
#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
((__BANK__) == FSMC_NORSRAM_BANK2) || \
((__BANK__) == FSMC_NORSRAM_BANK3) || \
((__BANK__) == FSMC_NORSRAM_BANK4))
#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
((__SIZE__) == FSMC_PAGE_SIZE_128) || \
((__SIZE__) == FSMC_PAGE_SIZE_256) || \
((__SIZE__) == FSMC_PAGE_SIZE_512) || \
((__SIZE__) == FSMC_PAGE_SIZE_1024))
#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
((__MODE__) == FSMC_ACCESS_MODE_B) || \
((__MODE__) == FSMC_ACCESS_MODE_C) || \
((__MODE__) == FSMC_ACCESS_MODE_D))
#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
((__MODE__) == FSMC_WRAP_MODE_ENABLE))
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FSMC_WRITE_BURST_ENABLE))
#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
((__STATE__) == FSMC_NAND_ECC_ENABLE))
#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
#endif /* FSMC_BANK4 */
/**
* @}
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
* @{
*/
#if defined(FSMC_BANK1)
#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
#endif /* FSMC_BANK4 */
#if defined(FSMC_BANK1)
#define FSMC_NORSRAM_DEVICE FSMC_Bank1
#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
#define FSMC_NAND_DEVICE FSMC_Bank2_3
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
#define FSMC_PCCARD_DEVICE FSMC_Bank4
#endif /* FSMC_BANK4 */
#if defined(FSMC_BANK1)
/**
* @brief FSMC NORSRAM Configuration Structure definition
*/
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing*/
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device
by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */
uint32_t PageSize; /*!< Specifies the memory page size.
This parameter can be a value of @ref FSMC_Page_Size */
} FSMC_NORSRAM_InitTypeDef;
/**
* @brief FSMC NORSRAM Timing parameters structure definition
*/
typedef struct
{
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and
Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17
in NOR Flash memories with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
} FSMC_NORSRAM_TimingTypeDef;
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
/**
* @brief FSMC NAND Configuration Structure definition
*/
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
This parameter can be a value of @ref FSMC_NAND_Bank */
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FSMC_NAND_Data_Width */
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FSMC_ECC */
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FSMC_ECC_Page_Size */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
} FSMC_NAND_InitTypeDef;
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK3) || defined(FSMC_BANK4)
/**
* @brief FSMC NAND Timing parameters structure definition
*/
typedef struct
{
uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
} FSMC_NAND_PCC_TimingTypeDef;
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
/**
* @brief FSMC PCCARD Configuration Structure definition
*/
typedef struct
{
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
} FSMC_PCCARD_InitTypeDef;
#endif /* FSMC_BANK4 */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
* @{
*/
#if defined(FSMC_BANK1)
/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
* @{
*/
/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
* @{
*/
#define FSMC_NORSRAM_BANK1 (0x00000000U)
#define FSMC_NORSRAM_BANK2 (0x00000002U)
#define FSMC_NORSRAM_BANK3 (0x00000004U)
#define FSMC_NORSRAM_BANK4 (0x00000006U)
/**
* @}
*/
/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
* @{
*/
#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
/**
* @}
*/
/** @defgroup FSMC_Memory_Type FSMC Memory Type
* @{
*/
#define FSMC_MEMORY_TYPE_SRAM (0x00000000U)
#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U)
#define FSMC_MEMORY_TYPE_NOR (0x00000008U)
/**
* @}
*/
/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
* @{
*/
#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
/**
* @}
*/
/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
* @{
*/
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
* @{
*/
#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
* @{
*/
#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
/**
* @}
*/
/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
* @{
*/
#define FSMC_WRAP_MODE_DISABLE (0x00000000U)
#define FSMC_WRAP_MODE_ENABLE (0x00000400U)
/**
* @}
*/
/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
* @{
*/
#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U)
/**
* @}
*/
/** @defgroup FSMC_Write_Operation FSMC Write Operation
* @{
*/
#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U)
#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U)
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
* @{
*/
#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U)
#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U)
/**
* @}
*/
/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
* @{
*/
#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U)
#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U)
/**
* @}
*/
/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
* @{
*/
#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
/**
* @}
*/
/** @defgroup FSMC_Page_Size FSMC Page Size
* @{
*/
#define FSMC_PAGE_SIZE_NONE (0x00000000U)
#define FSMC_PAGE_SIZE_128 (0x00010000U)
#define FSMC_PAGE_SIZE_256 (0x00020000U)
#define FSMC_PAGE_SIZE_512 (0x00030000U)
#define FSMC_PAGE_SIZE_1024 (0x00040000U)
/**
* @}
*/
/** @defgroup FSMC_Write_Burst FSMC Write Burst
* @{
*/
#define FSMC_WRITE_BURST_DISABLE (0x00000000U)
#define FSMC_WRITE_BURST_ENABLE (0x00080000U)
/**
* @}
*/
/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
* @{
*/
#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
/**
* @}
*/
/** @defgroup FSMC_Access_Mode FSMC Access Mode
* @{
*/
#define FSMC_ACCESS_MODE_A (0x00000000U)
#define FSMC_ACCESS_MODE_B (0x10000000U)
#define FSMC_ACCESS_MODE_C (0x20000000U)
#define FSMC_ACCESS_MODE_D (0x30000000U)
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3) || defined(FSMC_BANK4)
/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
* @{
*/
/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
* @{
*/
#define FSMC_NAND_BANK2 (0x00000010U)
#define FSMC_NAND_BANK3 (0x00000100U)
/**
* @}
*/
/** @defgroup FSMC_Wait_feature FSMC Wait feature
* @{
*/
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
/**
* @}
*/
/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
* @{
*/
#if defined(FSMC_BANK4)
#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
#endif /* FSMC_BANK4 */
#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
/**
* @}
*/
/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
* @{
*/
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
/**
* @}
*/
/** @defgroup FSMC_ECC FSMC ECC
* @{
*/
#define FSMC_NAND_ECC_DISABLE (0x00000000U)
#define FSMC_NAND_ECC_ENABLE (0x00000040U)
/**
* @}
*/
/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
* @{
*/
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK3 || FSMC_Bank4 */
/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
* @{
*/
#if defined(FSMC_BANK3) || defined(FSMC_BANK4)
#define FSMC_IT_RISING_EDGE (0x00000008U)
#define FSMC_IT_LEVEL (0x00000010U)
#define FSMC_IT_FALLING_EDGE (0x00000020U)
#endif /* FSMC_BANK3 || FSMC_Bank4 */
/**
* @}
*/
/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
* @{
*/
#if defined(FSMC_BANK3) || defined(FSMC_BANK4)
#define FSMC_FLAG_RISING_EDGE (0x00000001U)
#define FSMC_FLAG_LEVEL (0x00000002U)
#define FSMC_FLAG_FALLING_EDGE (0x00000004U)
#define FSMC_FLAG_FEMPT (0x00000040U)
#endif /* FSMC_BANK3 || FSMC_Bank4 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros
* @{
*/
#if defined(FSMC_BANK1)
/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
/**
* @brief Enable the NORSRAM device access.
* @param __INSTANCE__ FSMC_NORSRAM Instance
* @param __BANK__ FSMC_NORSRAM Bank
* @retval None
*/
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|= FSMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
* @param __INSTANCE__ FSMC_NORSRAM Instance
* @param __BANK__ FSMC_NORSRAM Bank
* @retval None
*/
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
&= ~FSMC_BCRx_MBKEN)
/**
* @}
*/
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @retval None
*/
#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN) : \
((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN))
/**
* @brief Disable the NAND device access.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @retval None
*/
#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN) : \
CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
/**
* @}
*/
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
* @brief macros to handle PCCARD read/write operations
* @{
*/
/**
* @brief Enable the PCCARD device access.
* @param __INSTANCE__ FSMC_PCCARD Instance
* @retval None
*/
#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN)
/**
* @brief Disable the PCCARD device access.
* @param __INSTANCE__ FSMC_PCCARD Instance
* @retval None
*/
#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN)
/**
* @}
*/
#endif /* FSMC_BANK4 */
#if defined(FSMC_BANK3)
/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
* @brief macros to handle NAND interrupts
* @{
*/
/**
* @brief Enable the NAND device interrupt.
* @param __INSTANCE__ FSMC_NAND instance
* @param __BANK__ FSMC_NAND Bank
* @param __INTERRUPT__ FSMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FSMC_IT_LEVEL: Interrupt level.
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \
((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
/**
* @brief Disable the NAND device interrupt.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @param __INTERRUPT__ FSMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FSMC_IT_LEVEL: Interrupt level.
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \
((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
/**
* @brief Get flag status of the NAND device.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @param __FLAG__ FSMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
(((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
/**
* @brief Clear flag status of the NAND device.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @param __FLAG__ FSMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \
((__INSTANCE__)->SR3 &= ~(__FLAG__)))
/**
* @}
*/
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
* @brief macros to handle PCCARD interrupts
* @{
*/
/**
* @brief Enable the PCCARD device interrupt.
* @param __INSTANCE__ FSMC_PCCARD instance
* @param __INTERRUPT__ FSMC_PCCARD interrupt
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FSMC_IT_LEVEL: Interrupt level.
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
/**
* @brief Disable the PCCARD device interrupt.
* @param __INSTANCE__ FSMC_PCCARD instance
* @param __INTERRUPT__ FSMC_PCCARD interrupt
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FSMC_IT_LEVEL: Interrupt level.
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
/**
* @brief Get flag status of the PCCARD device.
* @param __INSTANCE__ FSMC_PCCARD instance
* @param __FLAG__ FSMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the PCCARD device.
* @param __INSTANCE__ FSMC_PCCARD instance
* @param __FLAG__ FSMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
/**
* @}
*/
#endif /* FSMC_BANK4 */
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
* @{
*/
#if defined(FSMC_BANK1)
/** @defgroup FSMC_LL_NORSRAM NOR SRAM
* @{
*/
/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
const FSMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
uint32_t ExtendedMode);
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
* @{
*/
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
/** @defgroup FSMC_LL_NAND NAND
* @{
*/
/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
* @{
*/
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
/** @defgroup FSMC_LL_PCCARD PCCARD
* @{
*/
/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
const FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
const FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
const FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK4 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_FSMC_H */

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john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_iwdg.h Normal file
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@@ -0,0 +1,302 @@
/**
******************************************************************************
* @file stm32f1xx_ll_iwdg.h
* @author MCD Application Team
* @brief Header file of IWDG LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_IWDG_H
#define STM32F1xx_LL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(IWDG)
/** @defgroup IWDG_LL IWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
* @{
*/
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
* @{
*/
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
/**
* @}
*/
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
* @{
*/
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
* @{
*/
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Start the Independent Watchdog
* @note Except if the hardware watchdog option is selected
* @rmtoll KR KEY LL_IWDG_Enable
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* @rmtoll KR KEY LL_IWDG_ReloadCounter
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
}
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
}
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
}
/**
* @brief Select the prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_SetPrescaler
* @param IWDGx IWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
{
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
}
/**
* @brief Get the selected prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_GetPrescaler
* @param IWDGx IWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
*/
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->PR));
}
/**
* @brief Specify the IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
* @param IWDGx IWDG Instance
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
{
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
}
/**
* @brief Get the specified IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->RLR));
}
/**
* @}
*/
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if flag Prescaler Value Update is set or not
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag Reload Value Update is set or not
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flags Prescaler & Reload Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
* SR RVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* IWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_IWDG_H */

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/**
******************************************************************************
* @file stm32f1xx_ll_sdmmc.h
* @author MCD Application Team
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_SDMMC_H
#define STM32F1xx_LL_SDMMC_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(SDIO)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_Driver
* @{
*/
/** @addtogroup SDMMC_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
* @{
*/
/**
* @brief SDMMC Configuration Structure definition
*/
typedef struct
{
uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
disabled when the bus is idle.
This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
uint32_t BusWide; /*!< Specifies the SDMMC bus width.
This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
}SDIO_InitTypeDef;
/**
* @brief SDMMC Command Control structure
*/
typedef struct
{
uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
to a card as part of a command message. If a command
contains an argument, it must be loaded into this register
before writing the command to the command register. */
uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
Max_Data = 64 */
uint32_t Response; /*!< Specifies the SDMMC response type.
This parameter can be a value of @ref SDMMC_LL_Response_Type */
uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_CPSM_State */
}SDIO_CmdInitTypeDef;
/**
* @brief SDMMC Data Control structure
*/
typedef struct
{
uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
is a read or write.
This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_DPSM_State */
}SDIO_DataInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
/**
* @brief SDMMC Commands Index
*/
#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */
#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */
#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */
#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */
#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */
#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
and asks the card whether card supports voltage. */
#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */
#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */
#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */
#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */
#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */
#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands
(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
for SDHS and SDXC. */
#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by
STOP_TRANSMISSION command. */
#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */
#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */
#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */
#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */
#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */
#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */
#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */
#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */
#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command
system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased.
Reserved for each command system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */
#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
the SET_BLOCK_LEN command. */
#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather
than a standard command. */
#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card
for general purpose/application specific commands. */
#define SDMMC_CMD_NO_CMD 64U /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* SDMMC_APP_CMD should be sent before sending these commands.
*/
#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
widths are given in SCR register. */
#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */
#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
32bit+CRC data block. */
#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
send its operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */
#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */
#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */
/**
* @brief Following commands are SD Card Specific security commands.
* SDMMC_CMD_APP_CMD should be sent before sending these commands.
*/
#define SDMMC_CMD_SD_APP_GET_MKB 43U
#define SDMMC_CMD_SD_APP_GET_MID 44U
#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U
#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U
#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U
#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U
#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U
#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U
#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U
/**
* @brief Masks for errors Card Status R1 (OCR Register)
*/
#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
#define SDMMC_OCR_CC_ERROR 0x00100000U
#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
#define SDMMC_OCR_ERASE_RESET 0x00002000U
#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
/**
* @brief Masks for R6 Response
*/
#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
#define SDMMC_HIGH_CAPACITY 0x40000000U
#define SDMMC_STD_CAPACITY 0x00000000U
#define SDMMC_CHECK_PATTERN 0x000001AAU
#define SD_SWITCH_1_8V_CAPACITY 0x01000000U
#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
#define SDMMC_MAX_TRIAL 0x0000FFFFU
#define SDMMC_ALLZERO 0x00000000U
#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
#define SDMMC_CARD_LOCKED 0x02000000U
#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */
#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
#endif /* SDMMC_DATATIMEOUT */
#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */
#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT
#endif /* SDMMC_SWDATATIMEOUT */
#define SDMMC_0TO7BITS 0x000000FFU
#define SDMMC_8TO15BITS 0x0000FF00U
#define SDMMC_16TO23BITS 0x00FF0000U
#define SDMMC_24TO31BITS 0xFF000000U
#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
#define SDMMC_HALFFIFO 0x00000008U
#define SDMMC_HALFFIFOBYTES 0x00000020U
/**
* @brief Command Class supported
*/
#define SDIO_CCCC_ERASE 0x00000020U
#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
#define SDIO_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */
/** @defgroup SDIO_LL_Clock_Edge Clock Edge
* @{
*/
#define SDIO_CLOCK_EDGE_RISING 0x00000000U
#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
((EDGE) == SDIO_CLOCK_EDGE_FALLING))
/**
* @}
*/
/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
* @{
*/
#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
/**
* @}
*/
/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
* @{
*/
#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
/**
* @}
*/
/** @defgroup SDIO_LL_Bus_Wide Bus Width
* @{
*/
#define SDIO_BUS_WIDE_1B 0x00000000U
#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
((WIDE) == SDIO_BUS_WIDE_4B) || \
((WIDE) == SDIO_BUS_WIDE_8B))
/**
* @}
*/
/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
* @{
*/
#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
/**
* @}
*/
/** @defgroup SDIO_LL_Clock_Division Clock Division
* @{
*/
#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
/**
* @}
*/
/** @defgroup SDIO_LL_Command_Index Command Index
* @{
*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
/**
* @}
*/
/** @defgroup SDIO_LL_Response_Type Response Type
* @{
*/
#define SDIO_RESPONSE_NO 0x00000000U
#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
((RESPONSE) == SDIO_RESPONSE_SHORT) || \
((RESPONSE) == SDIO_RESPONSE_LONG))
/**
* @}
*/
/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
* @{
*/
#define SDIO_WAIT_NO 0x00000000U
#define SDIO_WAIT_IT SDIO_CMD_WAITINT
#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
((WAIT) == SDIO_WAIT_IT) || \
((WAIT) == SDIO_WAIT_PEND))
/**
* @}
*/
/** @defgroup SDIO_LL_CPSM_State CPSM State
* @{
*/
#define SDIO_CPSM_DISABLE 0x00000000U
#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
((CPSM) == SDIO_CPSM_ENABLE))
/**
* @}
*/
/** @defgroup SDIO_LL_Response_Registers Response Register
* @{
*/
#define SDIO_RESP1 0x00000000U
#define SDIO_RESP2 0x00000004U
#define SDIO_RESP3 0x00000008U
#define SDIO_RESP4 0x0000000CU
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
((RESP) == SDIO_RESP2) || \
((RESP) == SDIO_RESP3) || \
((RESP) == SDIO_RESP4))
/**
* @}
*/
/** @defgroup SDIO_LL_Data_Length Data Length
* @{
*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
/**
* @}
*/
/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
* @{
*/
#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
/**
* @}
*/
/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
* @{
*/
#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
/**
* @}
*/
/** @defgroup SDIO_LL_Transfer_Type Transfer Type
* @{
*/
#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
((MODE) == SDIO_TRANSFER_MODE_STREAM))
/**
* @}
*/
/** @defgroup SDIO_LL_DPSM_State DPSM State
* @{
*/
#define SDIO_DPSM_DISABLE 0x00000000U
#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
((DPSM) == SDIO_DPSM_ENABLE))
/**
* @}
*/
/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
* @{
*/
#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
((MODE) == SDIO_READ_WAIT_MODE_DATA2))
/**
* @}
*/
/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
* @{
*/
#define SDIO_IT_CCRCFAIL SDIO_MASK_CCRCFAILIE
#define SDIO_IT_DCRCFAIL SDIO_MASK_DCRCFAILIE
#define SDIO_IT_CTIMEOUT SDIO_MASK_CTIMEOUTIE
#define SDIO_IT_DTIMEOUT SDIO_MASK_DTIMEOUTIE
#define SDIO_IT_TXUNDERR SDIO_MASK_TXUNDERRIE
#define SDIO_IT_RXOVERR SDIO_MASK_RXOVERRIE
#define SDIO_IT_CMDREND SDIO_MASK_CMDRENDIE
#define SDIO_IT_CMDSENT SDIO_MASK_CMDSENTIE
#define SDIO_IT_DATAEND SDIO_MASK_DATAENDIE
#define SDIO_IT_STBITERR SDIO_MASK_STBITERRIE
#define SDIO_IT_DBCKEND SDIO_MASK_DBCKENDIE
#define SDIO_IT_CMDACT SDIO_MASK_CMDACTIE
#define SDIO_IT_TXACT SDIO_MASK_TXACTIE
#define SDIO_IT_RXACT SDIO_MASK_RXACTIE
#define SDIO_IT_TXFIFOHE SDIO_MASK_TXFIFOHEIE
#define SDIO_IT_RXFIFOHF SDIO_MASK_RXFIFOHFIE
#define SDIO_IT_TXFIFOF SDIO_MASK_TXFIFOFIE
#define SDIO_IT_RXFIFOF SDIO_MASK_RXFIFOFIE
#define SDIO_IT_TXFIFOE SDIO_MASK_TXFIFOEIE
#define SDIO_IT_RXFIFOE SDIO_MASK_RXFIFOEIE
#define SDIO_IT_TXDAVL SDIO_MASK_TXDAVLIE
#define SDIO_IT_RXDAVL SDIO_MASK_RXDAVLIE
#define SDIO_IT_SDIOIT SDIO_MASK_SDIOITIE
#define SDIO_IT_CEATAEND SDIO_MASK_CEATAENDIE
/**
* @}
*/
/** @defgroup SDIO_LL_Flags Flags
* @{
*/
#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
#define SDIO_FLAG_TXACT SDIO_STA_TXACT
#define SDIO_FLAG_RXACT SDIO_STA_RXACT
#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))
#define SDIO_STATIC_CMD_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
SDIO_FLAG_CMDSENT))
#define SDIO_STATIC_DATA_FLAGS ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
SDIO_FLAG_RXOVERR | SDIO_FLAG_DATAEND | SDIO_FLAG_DBCKEND))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
* @{
*/
/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
* @{
*/
/* ------------ SDIO registers bit address in the alias region -------------- */
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
/* --- CLKCR Register ---*/
/* Alias word address of CLKEN bit */
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
#define CLKEN_BITNUMBER 0x08U
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
/* --- CMD Register ---*/
/* Alias word address of SDIOSUSPEND bit */
#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
#define SDIOSUSPEND_BITNUMBER 0x0BU
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
/* Alias word address of ENCMDCOMPL bit */
#define ENCMDCOMPL_BITNUMBER 0x0CU
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
/* Alias word address of NIEN bit */
#define NIEN_BITNUMBER 0x0DU
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
/* Alias word address of ATACMD bit */
#define ATACMD_BITNUMBER 0x0EU
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
/* --- DCTRL Register ---*/
/* Alias word address of DMAEN bit */
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
#define DMAEN_BITNUMBER 0x03U
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
/* Alias word address of RWSTART bit */
#define RWSTART_BITNUMBER 0x08U
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
/* Alias word address of RWSTOP bit */
#define RWSTOP_BITNUMBER 0x09U
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
/* Alias word address of RWMOD bit */
#define RWMOD_BITNUMBER 0x0AU
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
/* Alias word address of SDIOEN bit */
#define SDIOEN_BITNUMBER 0x0BU
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
/**
* @}
*/
/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
* @brief SDIO_LL registers bit address in the alias region
* @{
*/
/* ---------------------- SDIO registers bit mask --------------------------- */
/* --- CLKCR Register ---*/
/* CLKCR register clear mask */
#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
/* --- DCTRL Register ---*/
/* SDIO DCTRL Clear Mask */
#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
/* --- CMD Register ---*/
/* CMD Register clear mask */
#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
/* SDIO Initialization Frequency (400KHz max) */
#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
/* SDIO Data Transfer Frequency (25MHz max) */
#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4)
/**
* @}
*/
/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/**
* @brief Enable the SDIO device.
* @param __INSTANCE__: SDIO Instance
* @retval None
*/
#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
/**
* @brief Disable the SDIO device.
* @param __INSTANCE__: SDIO Instance
* @retval None
*/
#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
/**
* @brief Enable the SDIO DMA transfer.
* @param __INSTANCE__: SDIO Instance
* @retval None
*/
#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
/**
* @brief Disable the SDIO DMA transfer.
* @param __INSTANCE__: SDIO Instance
* @retval None
*/
#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
/**
* @brief Enable the SDIO device interrupt.
* @param __INSTANCE__ : Pointer to SDIO register base
* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
/**
* @brief Disable the SDIO device interrupt.
* @param __INSTANCE__ : Pointer to SDIO register base
* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified SDIO flag is set or not.
* @param __INSTANCE__ : Pointer to SDIO register base
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
* @arg SDIO_FLAG_RXACT: Data receive in progress
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval The new state of SDIO_FLAG (SET or RESET).
*/
#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
/**
* @brief Clears the SDIO pending flags.
* @param __INSTANCE__ : Pointer to SDIO register base
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
* @retval None
*/
#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
/**
* @brief Checks whether the specified SDIO interrupt has occurred or not.
* @param __INSTANCE__ : Pointer to SDIO register base
* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval The new state of SDIO_IT (SET or RESET).
*/
#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clears the SDIO's interrupt pending bits.
* @param __INSTANCE__ : Pointer to SDIO register base
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
* @retval None
*/
#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
/**
* @brief Disable Start the SD I/O Read Wait operations.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
/**
* @brief Enable the SD I/O Mode Operation.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
/**
* @brief Disable the SD I/O Mode Operation.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
/**
* @brief Enable the SD I/O Suspend command sending.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
/**
* @brief Disable the SD I/O Suspend command sending.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
/**
* @brief Enable the command completion signal.
* @retval None
*/
#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
/**
* @brief Disable the command completion signal.
* @retval None
*/
#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
/**
* @brief Enable the CE-ATA interrupt.
* @retval None
*/
#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
/**
* @brief Disable the CE-ATA interrupt.
* @retval None
*/
#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
/**
* @brief Enable send CE-ATA command (CMD61).
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
/**
* @brief Disable send CE-ATA command (CMD61).
* @retval None
*/
#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SDMMC_LL_Exported_Functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
/** @addtogroup HAL_SDMMC_LL_Group1
* @{
*/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
/**
* @}
*/
/* I/O operation functions *****************************************************/
/** @addtogroup HAL_SDMMC_LL_Group2
* @{
*/
uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup HAL_SDMMC_LL_Group3
* @{
*/
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
/* Command path state machine (CPSM) management functions */
HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
/* Data path state machine (DPSM) management functions */
HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
/* SDMMC Cards mode management functions */
HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
/**
* @}
*/
/* SDMMC Commands management functions */
/** @addtogroup HAL_SDMMC_LL_Group4
* @{
*/
uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA);
uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
/**
* @}
*/
/* SDMMC Responses management functions *****************************************/
/** @addtogroup HAL_SDMMC_LL_Group5
* @{
*/
uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* SDIO */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_SDMMC_H */

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john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h Normal file
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@@ -0,0 +1,641 @@
/**
******************************************************************************
* @file stm32f1xx_ll_usb.h
* @author MCD Application Team
* @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_USB_H
#define STM32F1xx_LL_USB_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
#if defined (USB) || defined (USB_OTG_FS)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup USB_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
#ifndef HAL_USB_TIMEOUT
#define HAL_USB_TIMEOUT 0xF000000U
#endif /* define HAL_USB_TIMEOUT */
#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U
#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */
/**
* @brief USB Mode definition
*/
typedef enum
{
USB_DEVICE_MODE = 0,
USB_HOST_MODE = 1,
USB_DRD_MODE = 2
} USB_ModeTypeDef;
/**
* @brief URB States definition
*/
typedef enum
{
URB_IDLE = 0,
URB_DONE,
URB_NOTREADY,
URB_NYET,
URB_ERROR,
URB_STALL
} USB_URBStateTypeDef;
/**
* @brief Host channel States definition
*/
typedef enum
{
HC_IDLE = 0,
HC_XFRC,
HC_HALTED,
HC_ACK,
HC_NAK,
HC_NYET,
HC_STALL,
HC_XACTERR,
HC_BBLERR,
HC_DATATGLERR
} USB_HCStateTypeDef;
/**
* @brief USB Instance Initialization Structure definition
*/
typedef struct
{
uint8_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
#if defined (USB_OTG_FS)
uint8_t Host_channels; /*!< Host Channels number.
This parameter Depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
#endif /* defined (USB_OTG_FS) */
uint8_t dma_enable; /*!< USB DMA state.
If DMA is not supported this parameter shall be set by default to zero */
uint8_t speed; /*!< USB Core speed.
This parameter can be any value of @ref PCD_Speed/HCD_Speed
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint8_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
#if defined (USB_OTG_FS)
uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
#endif /* defined (USB_OTG_FS) */
} USB_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
#if defined (USB_OTG_FS)
uint8_t is_iso_incomplete; /*!< Endpoint isoc condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
#endif /* defined (USB_OTG_FS) */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_LL_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
#if defined (USB)
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr0; /*!< PMA Address0
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr1; /*!< PMA Address1
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint8_t doublebuffer; /*!< Double buffer enable
This parameter can be 0 or 1 */
#endif /* defined (USB) */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
#if defined (USB_OTG_FS)
uint8_t even_odd_frame; /*!< IFrame parity
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t tx_fifo_num; /*!< Transmission FIFO number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
uint32_t xfer_size; /*!< requested transfer size */
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
#endif /* defined (USB) */
} USB_EPTypeDef;
typedef struct
{
uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_num; /*!< Endpoint number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t speed; /*!< USB Host Channel speed.
This parameter can be any value of @ref HCD_Device_Speed:
(HCD_DEVICE_SPEED_xxx) */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t hub_port_nbr; /*!< USB HUB port number */
uint8_t hub_addr; /*!< USB HUB address */
uint8_t ep_type; /*!< Endpoint Type.
This parameter can be any value of @ref USB_LL_EP_Type */
uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t data_pid; /*!< Initial data PID.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
uint32_t XferSize; /*!< OTG Channel transfer size. */
uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
uint8_t toggle_in; /*!< IN transfer current toggle flag.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t toggle_out; /*!< OUT transfer current toggle flag
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
uint32_t ErrCnt; /*!< Host channel error count. */
USB_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_URBStateTypeDef */
USB_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_HCStateTypeDef */
} USB_HCTypeDef;
#if defined (USB_OTG_FS)
typedef USB_ModeTypeDef USB_OTG_ModeTypeDef;
typedef USB_CfgTypeDef USB_OTG_CfgTypeDef;
typedef USB_EPTypeDef USB_OTG_EPTypeDef;
typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef;
typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef;
typedef USB_HCTypeDef USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) */
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
#if defined (USB_OTG_FS)
/** @defgroup USB_OTG_CORE VERSION ID
* @{
*/
#define USB_OTG_CORE_ID_300A 0x4F54300AU
#define USB_OTG_CORE_ID_310A 0x4F54310AU
/**
* @}
*/
/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
#define USB_OTG_MODE_DEVICE 0U
#define USB_OTG_MODE_HOST 1U
#define USB_OTG_MODE_DRD 2U
/**
* @}
*/
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{
*/
#define USB_OTG_SPEED_FULL 3U
/**
* @}
*/
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
* @{
*/
#define USB_OTG_EMBEDDED_PHY 2U
/**
* @}
*/
/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
* @{
*/
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
*/
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
* @{
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/**
* @}
*/
/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
* @{
*/
#define DCFG_FRAME_INTERVAL_80 0U
#define DCFG_FRAME_INTERVAL_85 1U
#define DCFG_FRAME_INTERVAL_90 2U
#define DCFG_FRAME_INTERVAL_95 3U
/**
* @}
*/
#endif /* defined (USB_OTG_FS) */
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
* @{
*/
#define EP_SPEED_LOW 0U
#define EP_SPEED_FULL 1U
#define EP_SPEED_HIGH 2U
/**
* @}
*/
/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type
* @{
*/
#define HC_PID_DATA0 0U
#define HC_PID_DATA2 1U
#define HC_PID_DATA1 2U
#define HC_PID_SETUP 3U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
#define USBH_FSLS_SPEED 1U
/**
* @}
*/
#if defined (USB_OTG_FS)
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
* @{
*/
#define STS_GOUT_NAK 1U
#define STS_DATA_UPDT 2U
#define STS_XFER_COMP 3U
#define STS_SETUP_COMP 4U
#define STS_SETUP_UPDT 6U
/**
* @}
*/
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
* @{
*/
#define HCFG_30_60_MHZ 0U
#define HCFG_48_MHZ 1U
#define HCFG_6_MHZ 2U
/**
* @}
*/
/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines
* @{
*/
#define HFIR_6_MHZ 6000U
#define HFIR_60_MHZ 60000U
#define HFIR_48_MHZ 48000U
/**
* @}
*/
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0U
#define HPRT0_PRTSPD_FULL_SPEED 1U
#define HPRT0_PRTSPD_LOW_SPEED 2U
/**
* @}
*/
#define HCCHAR_CTRL 0U
#define HCCHAR_ISOC 1U
#define HCCHAR_BULK 2U
#define HCCHAR_INTR 3U
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU
#define HC_MAX_PKT_CNT 256U
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+ USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+ USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+ USB_OTG_HOST_CHANNEL_BASE\
+ ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#define EP_ADDR_MSK 0xFU
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 2U
#ifndef USB_EP_RX_STRX
#define USB_EP_RX_STRX (0x3U << 12)
#endif /* USB_EP_RX_STRX */
#define EP_ADDR_MSK 0x7U
#ifndef USE_USB_DOUBLE_BUFFER
#define USE_USB_DOUBLE_BUFFER 1U
#endif /* USE_USB_DOUBLE_BUFFER */
#endif /* defined (USB) */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
* @{
*/
#if defined (USB_OTG_FS)
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
#endif /* defined (USB_OTG_FS) */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
#if defined (USB_OTG_FS)
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, const uint8_t *psetup);
uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx);
uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
USB_OTG_HCTypeDef *hc);
uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num);
#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
#endif /* defined (USB) */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32F1xx_LL_USB_H */

316
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_wwdg.h Normal file
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/**
******************************************************************************
* @file stm32f1xx_ll_wwdg.h
* @author MCD Application Team
* @brief Header file of WWDG LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_WWDG_H
#define STM32F1xx_LL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (WWDG)
/** @defgroup WWDG_LL WWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
* @{
*/
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
/**
* @}
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
* @{
*/
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
* @{
*/
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
* @{
*/
/**
* @brief Write a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
* @{
*/
/** @defgroup WWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
* then it cannot be disabled again except by a reset.
* This bit is set by software and only cleared by hardware after a reset.
* When WDGA = 1, the watchdog can generate a reset.
* @rmtoll CR WDGA LL_WWDG_Enable
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
}
/**
* @brief Checks if Window Watchdog is enabled
* @rmtoll CR WDGA LL_WWDG_IsEnabled
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
/**
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
* @rmtoll CR T LL_WWDG_SetCounter
* @param WWDGx WWDG Instance
* @param Counter 0..0x7F (7 bit counter value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
{
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
}
/**
* @brief Return current Watchdog Counter Value (7 bits counter value)
* @rmtoll CR T LL_WWDG_GetCounter
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Counter value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
/**
* @brief Set the time base of the prescaler (WDGTB).
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
* is decremented every (4096 x 2expWDGTB) PCLK cycles
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
* @param WWDGx WWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
}
/**
* @brief Return current Watchdog Prescaler Value
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
* @param WWDGx WWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
*/
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
/**
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
* @note This window value defines when write in the WWDG_CR register
* to program Watchdog counter is allowed.
* Watchdog counter value update must occur only when the counter value
* is lower than the Watchdog window register value.
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
* (in the control register) is refreshed before the downcounter has reached
* the watchdog window register value.
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
* @rmtoll CFR W LL_WWDG_SetWindow
* @param WWDGx WWDG Instance
* @param Window 0x00..0x7F (7 bit Window value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
}
/**
* @brief Return current Watchdog Window Value (7 bits value)
* @rmtoll CFR W LL_WWDG_GetWindow
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Window value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
* @note This bit is set by hardware when the counter has reached the value 0x40.
* It must be cleared by software by writing 0.
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
/**
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable the Early Wakeup Interrupt.
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
* This interrupt is only cleared by hardware after a reset
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
}
/**
* @brief Check if Early Wakeup Interrupt is enabled
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* WWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_WWDG_H */

1009
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cec.c Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_cec.c
* @author MCD Application Team
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
* Consumer Electronics Control Peripheral (CEC).
* + Initialization and de-initialization function
* + IO operation function
* + Peripheral Control function
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The CEC HAL driver can be used as follow:
(#) Declare a CEC_HandleTypeDef handle structure.
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
(##) Enable the CEC interface clock.
(##) CEC pins configuration:
(+++) Enable the clock for the CEC GPIOs.
(+++) Configure these CEC pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
and HAL_CEC_Receive_IT() APIs):
(+++) Configure the CEC interrupt priority.
(+++) Enable the NVIC CEC IRQ handle.
(+++) The specific CEC interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
and receive process.
(#) Program the Bit Timing Error Mode and the Bit Period Error Mode in the hcec Init structure.
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
[..]
(@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_CEC_MspInit() API.
*** Callback registration ***
=============================================
The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
to register an interrupt callback.
Function HAL_CEC_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : Tx Transfer completed callback.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : CEC MspInit.
(+) MspDeInitCallback : CEC MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
HAL_CEC_RegisterRxCpltCallback().
Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default
weak function.
HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : Tx Transfer completed callback.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : CEC MspInit.
(+) MspDeInitCallback : CEC MspDeInit.
For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
HAL_CEC_UnRegisterRxCpltCallback().
By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
all callbacks are set to the corresponding weak functions :
examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand)
Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit()
or HAL_CEC_Init() function.
When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
#ifdef HAL_CEC_MODULE_ENABLED
#if defined (CEC)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup CEC CEC
* @brief HAL CEC module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
* @{
*/
#define CEC_CFGR_FIELDS (CEC_CFGR_BTEM | CEC_CFGR_BPEM )
#define CEC_FLAG_TRANSMIT_MASK (CEC_FLAG_TSOM|CEC_FLAG_TEOM|CEC_FLAG_TBTRF)
#define CEC_FLAG_RECEIVE_MASK (CEC_FLAG_RSOM|CEC_FLAG_REOM|CEC_FLAG_RBTF)
#define CEC_ESR_ALL_ERROR (CEC_ESR_BTE|CEC_ESR_BPE|CEC_ESR_RBTFE|CEC_ESR_SBE|CEC_ESR_ACKE|CEC_ESR_LINE|CEC_ESR_TBTFE)
#define CEC_RXXFERSIZE_INITIALIZE 0xFFFF /*!< Value used to initialise the RxXferSize of the handle */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
*/
static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup CEC_Exported_Functions CEC Exported Functions
* @{
*/
/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the CEC
(+) The following parameters need to be configured:
(++) TimingErrorFree
(++) PeriodErrorFree
(++) InitiatorAddress
@endverbatim
* @{
*/
/**
* @brief Initializes the CEC mode according to the specified
* parameters in the CEC_InitTypeDef and creates the associated handle .
* @param hcec CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(hcec->Init.TimingErrorFree));
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(hcec->Init.PeriodErrorFree));
assert_param(IS_CEC_ADDRESS(hcec->Init.OwnAddress));
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
if (hcec->gState == HAL_CEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak RxCpltCallback */
hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
if (hcec->MspInitCallback == NULL)
{
hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hcec->MspInitCallback(hcec);
}
#else
if (hcec->gState == HAL_CEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
HAL_CEC_MspInit(hcec);
}
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Write to CEC Control Register */
MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree | hcec->Init.PeriodErrorFree);
/* Write to CEC Own Address Register */
MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
/* Configure the prescaler to generate the required 50 microseconds time base.*/
MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50U * (HAL_RCC_GetPCLK1Freq() / 1000000U) - 1U);
/* Enable the following CEC Interrupt */
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
/* Enable the CEC Peripheral */
__HAL_CEC_ENABLE(hcec);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_READY;
hcec->RxState = HAL_CEC_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the CEC peripheral
* @param hcec CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
if (hcec == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
hcec->gState = HAL_CEC_STATE_BUSY;
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
if (hcec->MspDeInitCallback == NULL)
{
hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hcec->MspDeInitCallback(hcec);
#else
/* DeInit the low level hardware */
HAL_CEC_MspDeInit(hcec);
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
__HAL_RCC_CEC_FORCE_RESET();
__HAL_RCC_CEC_RELEASE_RESET();
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_RESET;
hcec->RxState = HAL_CEC_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hcec);
return HAL_OK;
}
/**
* @brief Initializes the Own Address of the CEC device
* @param hcec CEC handle
* @param CEC_OwnAddress The CEC own address.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
{
/* Check the parameters */
assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
{
/* Process Locked */
__HAL_LOCK(hcec);
hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
{
MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
}
else
{
CLEAR_BIT(hcec->Instance->OAR, CEC_OAR_OA);
}
hcec->gState = HAL_CEC_STATE_READY;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief CEC MSP Init
* @param hcec CEC handle
* @retval None
*/
__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspInit can be implemented in the user file
*/
}
/**
* @brief CEC MSP DeInit
* @param hcec CEC handle
* @retval None
*/
__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspDeInit can be implemented in the user file
*/
}
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User CEC Callback
* To be used instead of the weak predefined callback
* @param hcec CEC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
* @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
pCEC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hcec);
if (hcec->gState == HAL_CEC_STATE_READY)
{
switch (CallbackID)
{
case HAL_CEC_TX_CPLT_CB_ID :
hcec->TxCpltCallback = pCallback;
break;
case HAL_CEC_ERROR_CB_ID :
hcec->ErrorCallback = pCallback;
break;
case HAL_CEC_MSPINIT_CB_ID :
hcec->MspInitCallback = pCallback;
break;
case HAL_CEC_MSPDEINIT_CB_ID :
hcec->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hcec->gState == HAL_CEC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_CEC_MSPINIT_CB_ID :
hcec->MspInitCallback = pCallback;
break;
case HAL_CEC_MSPDEINIT_CB_ID :
hcec->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hcec);
return status;
}
/**
* @brief Unregister an CEC Callback
* CEC callback is redirected to the weak predefined callback
* @param hcec uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
* @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hcec);
if (hcec->gState == HAL_CEC_STATE_READY)
{
switch (CallbackID)
{
case HAL_CEC_TX_CPLT_CB_ID :
hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_CEC_ERROR_CB_ID :
hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_CEC_MSPINIT_CB_ID :
hcec->MspInitCallback = HAL_CEC_MspInit;
break;
case HAL_CEC_MSPDEINIT_CB_ID :
hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
break;
default :
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hcec->gState == HAL_CEC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_CEC_MSPINIT_CB_ID :
hcec->MspInitCallback = HAL_CEC_MspInit;
break;
case HAL_CEC_MSPDEINIT_CB_ID :
hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
break;
default :
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hcec);
return status;
}
/**
* @brief Register CEC RX complete Callback
* To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback
* @param hcec CEC handle
* @param pCallback pointer to the Rx transfer compelete Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hcec);
if (HAL_CEC_STATE_READY == hcec->RxState)
{
hcec->RxCpltCallback = pCallback;
}
else
{
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hcec);
return status;
}
/**
* @brief UnRegister CEC RX complete Callback
* CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback
* @param hcec CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hcec);
if (HAL_CEC_STATE_READY == hcec->RxState)
{
hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak CEC RxCpltCallback */
}
else
{
/* Update the error code */
hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hcec);
return status;
}
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
* @brief CEC Transmit/Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the CEC data transfers.
(#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
(#) The communication is performed using Interrupts.
These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated CEC IRQ when using Interrupt mode.
The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
will be executed respectively at the end of the transmit or Receive process
The HAL_CEC_ErrorCallback() user callback will be executed when a communication
error is detected
(#) API's with Interrupt are :
(+) HAL_CEC_Transmit_IT()
(+) HAL_CEC_IRQHandler()
(#) A set of User Callbacks are provided:
(+) HAL_CEC_TxCpltCallback()
(+) HAL_CEC_RxCpltCallback()
(+) HAL_CEC_ErrorCallback()
@endverbatim
* @{
*/
/**
* @brief Send data in interrupt mode
* @param hcec CEC handle
* @param InitiatorAddress Initiator address
* @param DestinationAddress destination logical address
* @param pData pointer to input byte data buffer
* @param Size amount of data to be sent in bytes (without counting the header).
* 0 means only the header is sent (ping operation).
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
const uint8_t *pData, uint32_t Size)
{
/* if the peripheral isn't already busy and if there is no previous transmission
already pending due to arbitration lost */
if (hcec->gState == HAL_CEC_STATE_READY)
{
if ((pData == NULL) && (Size > 0U))
{
return HAL_ERROR;
}
assert_param(IS_CEC_ADDRESS(DestinationAddress));
assert_param(IS_CEC_ADDRESS(InitiatorAddress));
assert_param(IS_CEC_MSGSIZE(Size));
/* Process Locked */
__HAL_LOCK(hcec);
hcec->pTxBuffPtr = pData;
hcec->gState = HAL_CEC_STATE_BUSY_TX;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* initialize the number of bytes to send,
* 0 means only one header is sent (ping operation) */
hcec->TxXferCount = Size;
/* send header block */
hcec->Instance->TXD = (uint8_t)((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
/* case no data to be sent, sender is only pinging the system */
if (Size != 0)
{
/* Set TX Start of Message (TXSOM) bit */
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TSOM);
}
else
{
/* Send a ping command */
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM | CEC_FLAG_TSOM);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Get size of the received frame.
* @param hcec CEC handle
* @retval Frame size
*/
uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec)
{
return hcec->RxXferSize;
}
/**
* @brief Change Rx Buffer.
* @param hcec CEC handle
* @param Rxbuffer Rx Buffer
* @note This function can be called only inside the HAL_CEC_RxCpltCallback()
* @retval Frame size
*/
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
{
hcec->Init.RxBuffer = Rxbuffer;
}
/**
* @brief This function handles CEC interrupt requests.
* @param hcec CEC handle
* @retval None
*/
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
{
/* save interrupts register for further error or interrupts handling purposes */
uint32_t itflag;
itflag = hcec->Instance->CSR;
/* Save error status register for further error handling purposes */
hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
/* Transmit error */
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TERR))
{
/* Acknowledgement of the error */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
hcec->gState = HAL_CEC_STATE_READY;
}
/* Receive error */
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RERR))
{
/* Acknowledgement of the error */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
hcec->Init.RxBuffer -= hcec->RxXferSize;
hcec->RxXferSize = 0U;
hcec->RxState = HAL_CEC_STATE_READY;
}
if ((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0U)
{
/* Error Call Back */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
hcec->ErrorCallback(hcec);
#else
HAL_CEC_ErrorCallback(hcec);
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
}
/* Transmit byte request or block transfer finished */
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TBTRF))
{
CEC_Transmit_IT(hcec);
}
/* Receive byte or block transfer finished */
if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RBTF))
{
if (hcec->RxXferSize == 0U)
{
/* reception is starting */
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
}
CEC_Receive_IT(hcec);
}
}
/**
* @brief Tx Transfer completed callback
* @param hcec CEC handle
* @retval None
*/
__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_TxCpltCallback can be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callback
* @param hcec CEC handle
* @param RxFrameSize Size of frame
* @retval None
*/
__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
UNUSED(RxFrameSize);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_RxCpltCallback can be implemented in the user file
*/
}
/**
* @brief CEC error callbacks
* @param hcec CEC handle
* @retval None
*/
__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_ErrorCallback can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
* @brief CEC control functions
*
@verbatim
===============================================================================
##### Peripheral Control function #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the CEC.
(+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
(+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
@endverbatim
* @{
*/
/**
* @brief return the CEC state
* @param hcec pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC module.
* @retval HAL state
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
{
uint32_t temp1;
uint32_t temp2;
temp1 = hcec->gState;
temp2 = hcec->RxState;
return (HAL_CEC_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the CEC error code
* @param hcec pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC.
* @retval CEC Error Code
*/
uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec)
{
return hcec->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup CEC_Private_Functions
* @{
*/
/**
* @brief Send data in interrupt mode
* @param hcec CEC handle.
* Function called under interruption only, once
* interruptions have been enabled by HAL_CEC_Transmit_IT()
* @retval HAL status
*/
static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
{
/* if the peripheral is already busy or if there is a previous transmission
already pending due to arbitration loss */
if ((hcec->gState == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
{
/* if all data have been sent */
if (hcec->TxXferCount == 0U)
{
/* Acknowledge successful completion by writing 0x00 */
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
hcec->gState = HAL_CEC_STATE_READY;
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
hcec->TxCpltCallback(hcec);
#else
HAL_CEC_TxCpltCallback(hcec);
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
return HAL_OK;
}
else
{
/* Reduce the number of bytes to transfer by one */
hcec->TxXferCount--;
/* Write data to TX buffer*/
hcec->Instance->TXD = (uint8_t) * hcec->pTxBuffPtr++;
/* If this is the last byte of the ongoing transmission */
if (hcec->TxXferCount == 0U)
{
/* Acknowledge byte request and signal end of message */
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM);
}
else
{
/* Acknowledge byte request by writing 0x00 */
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
}
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive data in interrupt mode.
* @param hcec CEC handle.
* Function called under interruption only, once
* interruptions have been enabled by HAL_CEC_Receive_IT()
* @retval HAL status
*/
static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
{
static uint32_t temp;
if (hcec->RxState == HAL_CEC_STATE_BUSY_RX)
{
temp = hcec->Instance->CSR;
/* Store received data */
hcec->RxXferSize++;
*hcec->Init.RxBuffer++ = hcec->Instance->RXD;
/* Acknowledge received byte by writing 0x00 */
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00U);
/* If the End Of Message is reached */
if (HAL_IS_BIT_SET(temp, CEC_FLAG_REOM))
{
/* Interrupts are not disabled due to transmission still ongoing */
hcec->RxState = HAL_CEC_STATE_READY;
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
hcec->RxCpltCallback(hcec, hcec->RxXferSize);
#else
HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* CEC */
#endif /* HAL_CEC_MODULE_ENABLED */
/**
* @}
*/

328
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_crc.c
* @author MCD Application Team
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(+) Initialize CRC calculator
(++) specify generating polynomial (peripheral default or non-default one)
(++) specify initialization value (peripheral default or non-default one)
(++) specify input data format
(++) specify input or output data inversion mode if any
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
input data buffer starting with the previously computed CRC as
initialization value
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
input data buffer starting with the defined initialization value
(default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup CRC CRC
* @brief CRC HAL module driver.
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
(+) Initialize the CRC MSP (MCU Specific Package)
(+) DeInitialize the CRC MSP
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the CRC peripheral.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
/* Check the CRC peripheral state */
if (hcrc->State == HAL_CRC_STATE_BUSY)
{
return HAL_BUSY;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
__HAL_CRC_SET_IDR(hcrc, 0);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions.
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) compute the 32-bit CRC value of a 32-bit data buffer
using combination of the previous CRC value and the new one.
[..] or
(+) compute the 32-bit CRC value of a 32-bit data buffer
independently of the previous CRC value.
@endverbatim
* @{
*/
/**
* @brief Compute the 32-bit CRC value of a 32-bit data buffer
* starting with the previously computed CRC as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer.
* @param BufferLength input data buffer length (number of uint32_t words).
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Enter Data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @brief Compute the 32-bit CRC value of a 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer.
* @param BufferLength input data buffer length (number of uint32_t words).
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
* written in hcrc->Instance->DR) */
__HAL_CRC_DR_RESET(hcrc);
/* Enter 32-bit input data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the CRC handle state.
* @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1418
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dac.c Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_dac.c
* @author MCD Application Team
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### DAC Peripheral features #####
==============================================================================
[..]
*** DAC Channels ***
====================
[..]
STM32F1 devices integrate two 12-bit Digital Analog Converters
The 2 converters (i.e. channel1 & channel2)
can be used independently or simultaneously (dual mode):
(#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
peripherals (ex. timers).
(#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
peripherals (ex. timers).
*** DAC Triggers ***
====================
[..]
Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
[..]
Digital to Analog conversion can be triggered by:
(#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
The used pin (GPIOx_PIN_9) must be configured in input mode.
(#) Timers TRGO: TIM2, TIM4, TIM6, TIM7
For STM32F10x connectivity line devices and STM32F100x devices: TIM3
For STM32F10x high-density and XL-density devices: TIM8
For STM32F100x high-density value line devices: TIM15 as
replacement of TIM5.
(DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
(#) Software using DAC_TRIGGER_SOFTWARE
*** DAC Buffer mode feature ***
===============================
[..]
Each DAC channel integrates an output buffer that can be used to
reduce the output impedance, and to drive external loads directly
without having to add an external operational amplifier.
To enable, the output buffer use
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
[..]
(@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
*** GPIO configurations guidelines ***
=====================
[..]
When a DAC channel is used (ex channel1 on PA4) and the other is not
(ex channel2 on PA5 is configured in Analog and disabled).
Channel1 may disturb channel2 as coupling effect.
Note that there is no coupling on channel2 as soon as channel2 is turned on.
Coupling on adjacent channel could be avoided as follows:
when unused PA5 is configured as INPUT PULL-UP or DOWN.
PA5 is configured in ANALOG just before it is turned on.
*** DAC wave generation feature ***
===================================
[..]
Both DAC channels can be used to generate
(#) Noise wave
(#) Triangle wave
*** DAC data format ***
=======================
[..]
The DAC data format can be:
(#) 8-bit right alignment using DAC_ALIGN_8B_R
(#) 12-bit left alignment using DAC_ALIGN_12B_L
(#) 12-bit right alignment using DAC_ALIGN_12B_R
*** DAC data value to voltage correspondence ***
================================================
[..]
The analog output voltage on each DAC channel pin is determined
by the following equation:
[..]
DAC_OUTx = VREF+ * DOR / 4095
(+) with DOR is the Data Output Register
[..]
VREF+ is the input voltage reference (refer to the device datasheet)
[..]
e.g. To set DAC_OUT1 to 0.7V, use
(+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
*** DMA requests ***
=====================
[..]
A DMA request can be generated when an external trigger (but not a software trigger)
occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
DMA1 requests are mapped as following:
(#) DAC channel1 mapped on DMA1 channel3
for STM32F100x low-density, medium-density, high-density with DAC
DMA remap:
(#) DAC channel2 mapped on DMA2 channel3
for STM32F100x high-density without DAC DMA remap and other
STM32F1 devices
[..]
(@) For Dual mode and specific signal (Triangle and noise) generation please
refer to Extended Features Driver description
##### How to use this driver #####
==============================================================================
[..]
(+) DAC APB clock must be enabled to get write access to DAC
registers using HAL_DAC_Init()
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
(+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
(+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
*** Polling mode IO operation ***
=================================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start()
(+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
(+) Stop the DAC peripheral using HAL_DAC_Stop()
*** DMA mode IO operation ***
==============================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
of data to be transferred at each end of conversion
First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
(+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
(+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
(+) For STM32F100x devices with specific feature: DMA underrun.
In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_DAC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
(+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
(+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
(+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
(+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
(+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
(+) MspInitCallback : DAC MspInit.
(+) MspDeInitCallback : DAC MspdeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (overridden) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
(+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
(+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
(+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
(+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
(+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
(+) MspInitCallback : DAC MspInit.
(+) MspDeInitCallback : DAC MspdeInit.
(+) All Callbacks
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (overridden) functions in the HAL_DAC_Init
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
or HAL_DAC_Init function.
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (overridden) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DAC HAL driver.
(+) __HAL_DAC_ENABLE : Enable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
(+) __HAL_DAC_DISABLE : Disable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
(+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (For STM32F100x devices with specific feature: DMA underrun)
(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status (For STM32F100x devices with specific feature: DMA underrun)
[..]
(@) You can refer to the DAC HAL driver header file for more useful macros
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
#if defined(DAC)
/** @defgroup DAC DAC
* @brief DAC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions -------------------------------------------------------*/
/** @defgroup DAC_Exported_Functions DAC Exported Functions
* @{
*/
/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DAC.
(+) De-initialize the DAC.
@endverbatim
* @{
*/
/**
* @brief Initialize the DAC peripheral according to the specified parameters
* in the DAC_InitStruct and initialize the associated handle.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
if (hdac->State == HAL_DAC_STATE_RESET)
{
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the DAC Callback settings */
hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
if (hdac->MspInitCallback == NULL)
{
hdac->MspInitCallback = HAL_DAC_MspInit;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the low level hardware */
hdac->MspInitCallback(hdac);
#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_BUSY;
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Deinitialize the DAC peripheral registers to their default reset values.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
if (hdac->MspDeInitCallback == NULL)
{
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
}
/* DeInit the low level hardware */
hdac->MspDeInitCallback(hdac);
#else
/* DeInit the low level hardware */
HAL_DAC_MspDeInit(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
/* Change DAC state */
hdac->State = HAL_DAC_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the DAC MSP.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the DAC MSP.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Start conversion.
(+) Stop conversion.
(+) Start conversion and enable DMA transfer.
(+) Stop conversion and disable DMA transfer.
(+) Get result of conversion.
@endverbatim
* @{
*/
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
if (Channel == DAC_CHANNEL_1)
{
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
{
/* Enable the selected DAC software conversion */
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
}
}
else
{
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
{
/* Enable the selected DAC software conversion*/
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
}
}
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables DAC and stop conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status;
uint32_t tmpreg;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
if (Channel == DAC_CHANNEL_1)
{
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
/* Case of use of channel 1 */
switch (Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
break;
default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
break;
}
}
else
{
/* Set the DMA transfer complete callback for channel2 */
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
/* Set the DMA half transfer complete callback for channel2 */
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
/* Set the DMA error callback for channel2 */
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
/* Enable the selected DAC channel2 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
/* Case of use of channel 2 */
switch (Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
break;
default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
break;
}
}
if (Channel == DAC_CHANNEL_1)
{
#if defined(DAC_CR_DMAUDRIE1)
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
#endif /* DAC_CR_DMAUDRIE1 */
/* Enable the DMA Stream */
status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
}
else
{
#if defined(DAC_CR_DMAUDRIE2)
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
#endif /* DAC_CR_DMAUDRIE2 */
/* Enable the DMA Stream */
status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
}
/* Process Unlocked */
__HAL_UNLOCK(hdac);
if (status == HAL_OK)
{
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
}
else
{
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
}
/* Return function status */
return status;
}
/**
* @brief Disables DAC and stop conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Disable the selected DAC channel DMA request */
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
/* Disable the DMA Stream */
/* Channel1 is used */
if (Channel == DAC_CHANNEL_1)
{
/* Disable the DMA Stream */
(void)HAL_DMA_Abort(hdac->DMA_Handle1);
#if defined(DAC_CR_DMAUDRIE1)
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
#endif /* DAC_CR_DMAUDRIE1 */
}
else /* Channel2 is used for */
{
/* Disable the DMA Stream */
(void)HAL_DMA_Abort(hdac->DMA_Handle2);
#if defined(DAC_CR_DMAUDRIE2)
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
#endif /* DAC_CR_DMAUDRIE2 */
}
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Handles DAC interrupt request
* This function uses the interruption of DMA
* underrun.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
{
#if !defined(DAC_SR_DMAUDR1) && !defined(DAC_SR_DMAUDR2)
UNUSED(hdac);
#else
uint32_t itsource = hdac->Instance->CR;
uint32_t itflag = hdac->Instance->SR;
#endif /* !DAC_SR_DMAUDR1 && !DAC_SR_DMAUDR2 */
#if defined(DAC_SR_DMAUDR1)
if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
{
/* Check underrun flag of DAC channel 1 */
if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
/* Set DAC error code to channel1 DMA underrun error */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
/* Disable the selected DAC channel1 DMA request */
__HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh1(hdac);
#else
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
#endif /* DAC_SR_DMAUDR1 */
#if defined(DAC_SR_DMAUDR2)
if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
{
/* Check underrun flag of DAC channel 2 */
if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
/* Set DAC error code to channel2 DMA underrun error */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
/* Disable the selected DAC channel2 DMA request */
__HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh2(hdac);
#else
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
#endif /* DAC_SR_DMAUDR2 */
}
/**
* @brief Set the specified data holding register value for DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Alignment Specifies the data alignment.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data Data to be loaded in the selected data holding register.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
__IO uint32_t tmp = 0UL;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)hdac->Instance;
if (Channel == DAC_CHANNEL_1)
{
tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
}
else
{
tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
}
/* Set the DAC channel selected data holding register */
*(__IO uint32_t *) tmp = Data;
/* Return function status */
return HAL_OK;
}
/**
* @brief Conversion complete callback in non-blocking mode for Channel1
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
*/
}
/**
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
*/
}
/**
* @brief Error DAC callback for Channel1.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
*/
}
/**
* @brief DMA underrun DAC callback for channel1.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure channels.
(+) Set the specified data holding register value for DAC channel.
@endverbatim
* @{
*/
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
uint32_t result;
/* Check the DAC peripheral handle */
assert_param(hdac != NULL);
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
if (Channel == DAC_CHANNEL_1)
{
result = hdac->Instance->DOR1;
}
else
{
result = hdac->Instance->DOR2;
}
/* Returns the DAC channel data output register value */
return result;
}
/**
* @brief Configures the selected DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig DAC configuration structure.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpreg1;
uint32_t tmpreg2;
/* Check the DAC peripheral handle and channel configuration struct */
if ((hdac == NULL) || (sConfig == NULL))
{
return HAL_ERROR;
}
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1))
<< (Channel & 0x10UL));
/* Configure for the selected DAC channel: buffer output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return status;
}
/**
* @}
*/
/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
==============================================================================
##### Peripheral State and Errors functions #####
==============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DAC state.
(+) Check the DAC Errors.
@endverbatim
* @{
*/
/**
* @brief return the DAC handle state
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL state
*/
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
{
/* Return DAC handle state */
return hdac->State;
}
/**
* @brief Return the DAC error code
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
{
return hdac->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
* To be used instead of the weak (overridden) predefined callback
* @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
* callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
* @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
* @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
* @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
* @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
* @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
* @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
*
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
pDAC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
if (pCallback == NULL)
{
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
{
case HAL_DAC_CH1_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh1 = pCallback;
break;
case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh1 = pCallback;
break;
case HAL_DAC_CH1_ERROR_ID :
hdac->ErrorCallbackCh1 = pCallback;
break;
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = pCallback;
break;
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = pCallback;
break;
case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh2 = pCallback;
break;
case HAL_DAC_CH2_ERROR_ID :
hdac->ErrorCallbackCh2 = pCallback;
break;
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = pCallback;
break;
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hdac->State == HAL_DAC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a User DAC Callback
* DAC Callback is redirected to the weak (overridden) predefined callback
* @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
* callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
* @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
* @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
* @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
* @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
* @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
* @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
* @retval status
*/
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
{
case HAL_DAC_CH1_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
break;
case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
break;
case HAL_DAC_CH1_ERROR_ID :
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
break;
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
break;
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
break;
case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
break;
case HAL_DAC_CH2_ERROR_ID :
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
break;
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
break;
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
case HAL_DAC_ALL_CB_ID :
hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
hdac->MspInitCallback = HAL_DAC_MspInit;
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hdac->State == HAL_DAC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DAC_Private_Functions
* @{
*/
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvCpltCallbackCh1(hdac);
#else
HAL_DAC_ConvCpltCallbackCh1(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Conversion complete callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvHalfCpltCallbackCh1(hdac);
#else
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ErrorCallbackCh1(hdac);
#else
HAL_DAC_ErrorCallbackCh1(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @}
*/
/**
* @}
*/
#endif /* DAC */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/

515
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dac_ex.c Normal file
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@@ -0,0 +1,515 @@
/**
******************************************************************************
* @file stm32f1xx_hal_dac_ex.c
* @author MCD Application Team
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Signal generation operation ***
===================================
[..]
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
#if defined(DAC)
/** @defgroup DACEx DACEx
* @brief DAC Extended HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
* @{
*/
/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
* @brief Extended IO operation functions
*
@verbatim
==============================================================================
##### Extended features functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Start conversion.
(+) Stop conversion.
(+) Start conversion and enable DMA transfer.
(+) Stop conversion and disable DMA transfer.
(+) Get result of conversion.
(+) Get result of dual mode conversion.
@endverbatim
* @{
*/
/**
* @brief Enables DAC and starts conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
{
uint32_t tmp_swtrig = 0UL;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
}
if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
}
/* Enable the selected DAC software conversion*/
SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables DAC and stop conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude Select max triangle amplitude.
* This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the triangle wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
(DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the noise wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
(DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the specified data holding register value for dual DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Alignment Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* DAC_ALIGN_8B_R: 8bit right data alignment selected
* DAC_ALIGN_12B_L: 12bit left data alignment selected
* DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
* @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
uint32_t data;
uint32_t tmp;
/* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (Alignment == DAC_ALIGN_8B_R)
{
data = ((uint32_t)Data2 << 8U) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16U) | Data1;
}
tmp = (uint32_t)hdac->Instance;
tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
/* Return function status */
return HAL_OK;
}
/**
* @brief Conversion complete callback in non-blocking mode for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Error DAC callback for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief DMA underrun DAC callback for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Set the specified data holding register value for DAC channel.
@endverbatim
* @{
*/
/**
* @brief Return the last data output value of the selected DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
{
uint32_t tmp = 0UL;
tmp |= hdac->Instance->DOR1;
tmp |= hdac->Instance->DOR2 << 16UL;
/* Returns the DAC channel data output register value */
return tmp;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DACEx_Private_Functions DACEx private functions
* @brief Extended private functions
* @{
*/
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvCpltCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Conversion complete callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvHalfCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA error callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ErrorCallbackCh2(hdac);
#else
HAL_DACEx_ErrorCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @}
*/
/**
* @}
*/
#endif /* DAC */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/

2290
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c Normal file
View File

@@ -0,0 +1,2290 @@
/**
******************************************************************************
* @file stm32f1xx_hal_eth.c
* @author MCD Application Team
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#)Declare a ETH_HandleTypeDef handle structure, for example:
ETH_HandleTypeDef heth;
(#)Fill parameters of Init structure in heth handle
(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
(##) Enable the Ethernet interface clock using
(+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
(+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
(+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
(##) Initialize the related GPIO clocks
(##) Configure Ethernet pin-out
(##) Configure Ethernet NVIC interrupt (IT mode)
(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
(##) HAL_ETH_DMATxDescListInit(); for Transmission process
(##) HAL_ETH_DMARxDescListInit(); for Reception process
(#)Enable MAC and DMA transmission and reception:
(##) HAL_ETH_Start();
(#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
the frame to MAC TX FIFO:
(##) HAL_ETH_TransmitFrame();
(#)Poll for a received frame in ETH RX DMA Descriptors and get received
frame parameters
(##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
(#) Get a received frame when an ETH RX interrupt occurs:
(##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
(#) Communicate with external PHY device:
(##) Read a specific register from the PHY
HAL_ETH_ReadPHYRegister();
(##) Write data to a specific RHY register:
HAL_ETH_WritePHYRegister();
(#) Configure the Ethernet MAC after ETH peripheral initialization
HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
(#) Configure the Ethernet DMA after ETH peripheral initialization
HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
-@- The PTP protocol and the DMA descriptors ring mode are not supported
in this driver
*** Callback registration ***
=============================================
The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) DMAErrorCallback : DMA Error Callback.
(+) MspInitCallback : MspInit Callback.
(+) MspDeInitCallback: MspDeInit Callback.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) DMAErrorCallback : DMA Error Callback.
(+) MspInitCallback : MspInit Callback.
(+) MspDeInitCallback: MspDeInit Callback.
By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
or HAL_ETH_Init function.
When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup ETH ETH
* @brief ETH HAL module driver
* @{
*/
#ifdef HAL_ETH_MODULE_ENABLED
#if defined (ETH)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup ETH_Private_Constants ETH Private Constants
* @{
*/
#define ETH_TIMEOUT_SWRESET 500U
#define ETH_TIMEOUT_LINKED_STATE 5000U
#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup ETH_Private_Functions ETH Private Functions
* @{
*/
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
static void ETH_Delay(uint32_t mdelay);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup ETH_Exported_Functions ETH Exported Functions
* @{
*/
/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the Ethernet peripheral
(+) De-initialize the Ethernet peripheral
@endverbatim
* @{
*/
/**
* @brief Initializes the Ethernet MAC and DMA according to default
* parameters.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
uint32_t tmpreg1 = 0U, phyreg = 0U;
uint32_t hclk = 60000000U;
uint32_t tickstart = 0U;
uint32_t err = ETH_SUCCESS;
/* Check the ETH peripheral state */
if (heth == NULL)
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
if (heth->State == HAL_ETH_STATE_RESET)
{
/* Allocate lock resource and initialize it */
heth->Lock = HAL_UNLOCKED;
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
ETH_InitCallbacksToDefault(heth);
if (heth->MspInitCallback == NULL)
{
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
heth->MspInitCallback = HAL_ETH_MspInit;
}
heth->MspInitCallback(heth);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/* Select MII or RMII Mode*/
AFIO->MAPR &= ~(AFIO_MAPR_MII_RMII_SEL);
AFIO->MAPR |= (uint32_t)heth->Init.MediaInterface;
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
(heth->Instance)->DMABMR |= ETH_DMABMR_SR;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for software reset */
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_SWRESET)
{
heth->State = HAL_ETH_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
not available, please check your external PHY or the IO configuration */
return HAL_TIMEOUT;
}
}
/*-------------------------------- MAC Initialization ----------------------*/
/* Get the ETHERNET MACMIIAR value */
tmpreg1 = (heth->Instance)->MACMIIAR;
/* Clear CSR Clock Range CR[2:0] bits */
tmpreg1 &= ETH_MACMIIAR_CR_MASK;
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
/* Set CR bits depending on hclk value */
if ((hclk >= 20000000U) && (hclk < 35000000U))
{
/* CSR Clock Range between 20-35 MHz */
tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV16;
}
else if ((hclk >= 35000000U) && (hclk < 60000000U))
{
/* CSR Clock Range between 35-60 MHz */
tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV26;
}
else
{
/* CSR Clock Range between 60-72 MHz */
tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42;
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
(heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
{
/* In case of write timeout */
err = ETH_ERROR;
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
/* Return HAL_ERROR */
return HAL_ERROR;
}
/* Delay to assure PHY reset */
HAL_Delay(PHY_RESET_DELAY);
if ((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
/* We wait for linked status */
do
{
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_LINKED_STATE)
{
/* In case of write timeout */
err = ETH_ERROR;
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
return HAL_TIMEOUT;
}
}
while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
/* Enable Auto-Negotiation */
if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
{
/* In case of write timeout */
err = ETH_ERROR;
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
/* Return HAL_ERROR */
return HAL_ERROR;
}
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until the auto-negotiation will be completed */
do
{
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
{
/* In case of write timeout */
err = ETH_ERROR;
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
return HAL_TIMEOUT;
}
}
while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
/* Read the result of the auto-negotiation */
if ((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
{
/* In case of write timeout */
err = ETH_ERROR;
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
/* Return HAL_ERROR */
return HAL_ERROR;
}
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if ((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
{
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
}
else
{
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
}
/* Configure the MAC with the speed fixed by the auto-negotiation process */
if ((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
{
/* Set Ethernet speed to 10M following the auto-negotiation */
(heth->Init).Speed = ETH_SPEED_10M;
}
else
{
/* Set Ethernet speed to 100M following the auto-negotiation */
(heth->Init).Speed = ETH_SPEED_100M;
}
}
else /* AutoNegotiation Disable */
{
/* Check parameters */
assert_param(IS_ETH_SPEED(heth->Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
/* Set MAC Speed and Duplex Mode */
if (HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
(uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
{
/* In case of write timeout */
err = ETH_ERROR;
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
/* Return HAL_ERROR */
return HAL_ERROR;
}
/* Delay to assure PHY configuration */
HAL_Delay(PHY_CONFIG_DELAY);
}
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief De-Initializes the ETH peripheral.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
{
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
if (heth->MspDeInitCallback == NULL)
{
heth->MspDeInitCallback = HAL_ETH_MspDeInit;
}
/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
heth->MspDeInitCallback(heth);
#else
/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspDeInit(heth);
#endif
/* Set ETH HAL state to Disabled */
heth->State = HAL_ETH_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the DMA Tx descriptors in chain mode.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param DMATxDescTab: Pointer to the first Tx desc list
* @param TxBuff: Pointer to the first TxBuffer list
* @param TxBuffCount: Number of the used Tx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
{
uint32_t i = 0U;
ETH_DMADescTypeDef *dmatxdesc;
/* Process Locked */
__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
heth->TxDesc = DMATxDescTab;
/* Fill each DMATxDesc descriptor with the right values */
for (i = 0U; i < TxBuffCount; i++)
{
/* Get the pointer on the ith member of the Tx Desc list */
dmatxdesc = DMATxDescTab + i;
/* Set Second Address Chained bit */
dmatxdesc->Status = ETH_DMATXDESC_TCH;
/* Set Buffer1 address pointer */
dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_TX_BUF_SIZE]);
if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
{
/* Set the DMA Tx descriptors checksum insertion */
dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if (i < (TxBuffCount - 1U))
{
/* Set next descriptor address register with next descriptor base address */
dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1U);
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
}
}
/* Set Transmit Descriptor List Address Register */
(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the DMA Rx descriptors in chain mode.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param DMARxDescTab: Pointer to the first Rx desc list
* @param RxBuff: Pointer to the first RxBuffer list
* @param RxBuffCount: Number of the used Rx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
{
uint32_t i = 0U;
ETH_DMADescTypeDef *DMARxDesc;
/* Process Locked */
__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
heth->RxDesc = DMARxDescTab;
/* Fill each DMARxDesc descriptor with the right values */
for (i = 0U; i < RxBuffCount; i++)
{
/* Get the pointer on the ith member of the Rx Desc list */
DMARxDesc = DMARxDescTab + i;
/* Set Own bit of the Rx descriptor Status */
DMARxDesc->Status = ETH_DMARXDESC_OWN;
/* Set Buffer1 size and Second Address Chained bit */
DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
/* Set Buffer1 address pointer */
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_RX_BUF_SIZE]);
if ((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
{
/* Enable Ethernet DMA Rx Descriptor interrupt */
DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if (i < (RxBuffCount - 1U))
{
/* Set next descriptor address register with next descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1U);
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
}
}
/* Set Receive Descriptor List Address Register */
(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the ETH MSP.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes ETH MSP.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_MspDeInit could be implemented in the user file
*/
}
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User ETH Callback
* To be used instead of the weak predefined callback
* @param heth eth handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
* @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
* @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(heth);
if (heth->State == HAL_ETH_STATE_READY)
{
switch (CallbackID)
{
case HAL_ETH_TX_COMPLETE_CB_ID :
heth->TxCpltCallback = pCallback;
break;
case HAL_ETH_RX_COMPLETE_CB_ID :
heth->RxCpltCallback = pCallback;
break;
case HAL_ETH_DMA_ERROR_CB_ID :
heth->DMAErrorCallback = pCallback;
break;
case HAL_ETH_MSPINIT_CB_ID :
heth->MspInitCallback = pCallback;
break;
case HAL_ETH_MSPDEINIT_CB_ID :
heth->MspDeInitCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (heth->State == HAL_ETH_STATE_RESET)
{
switch (CallbackID)
{
case HAL_ETH_MSPINIT_CB_ID :
heth->MspInitCallback = pCallback;
break;
case HAL_ETH_MSPDEINIT_CB_ID :
heth->MspDeInitCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(heth);
return status;
}
/**
* @brief Unregister an ETH Callback
* ETH callback is redirected to the weak predefined callback
* @param heth eth handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
* @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
* @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(heth);
if (heth->State == HAL_ETH_STATE_READY)
{
switch (CallbackID)
{
case HAL_ETH_TX_COMPLETE_CB_ID :
heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
break;
case HAL_ETH_RX_COMPLETE_CB_ID :
heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
break;
case HAL_ETH_DMA_ERROR_CB_ID :
heth->DMAErrorCallback = HAL_ETH_ErrorCallback;
break;
case HAL_ETH_MSPINIT_CB_ID :
heth->MspInitCallback = HAL_ETH_MspInit;
break;
case HAL_ETH_MSPDEINIT_CB_ID :
heth->MspDeInitCallback = HAL_ETH_MspDeInit;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (heth->State == HAL_ETH_STATE_RESET)
{
switch (CallbackID)
{
case HAL_ETH_MSPINIT_CB_ID :
heth->MspInitCallback = HAL_ETH_MspInit;
break;
case HAL_ETH_MSPDEINIT_CB_ID :
heth->MspDeInitCallback = HAL_ETH_MspDeInit;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(heth);
return status;
}
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Transmit a frame
HAL_ETH_TransmitFrame();
(+) Receive a frame
HAL_ETH_GetReceivedFrame();
HAL_ETH_GetReceivedFrame_IT();
(+) Read from an External PHY register
HAL_ETH_ReadPHYRegister();
(+) Write to an External PHY register
HAL_ETH_WritePHYRegister();
@endverbatim
* @{
*/
/**
* @brief Sends an Ethernet frame.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param FrameLength: Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
{
uint32_t bufcount = 0U, size = 0U, i = 0U;
/* Process Locked */
__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
if (FrameLength == 0U)
{
/* Set ETH HAL state to READY */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
return HAL_ERROR;
}
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if (((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
{
/* OWN bit set */
heth->State = HAL_ETH_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(heth);
return HAL_ERROR;
}
/* Get the number of needed Tx buffers for the current frame */
if (FrameLength > ETH_TX_BUF_SIZE)
{
bufcount = FrameLength / ETH_TX_BUF_SIZE;
if (FrameLength % ETH_TX_BUF_SIZE)
{
bufcount++;
}
}
else
{
bufcount = 1U;
}
if (bufcount == 1U)
{
/* Set LAST and FIRST segment */
heth->TxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
/* Set frame size */
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/* Point to next descriptor */
heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
}
else
{
for (i = 0U; i < bufcount; i++)
{
/* Clear FIRST and LAST segment bits */
heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
if (i == 0U)
{
/* Setting the first segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_FS;
}
/* Program size */
heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
if (i == (bufcount - 1U))
{
/* Setting the last segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_LS;
size = FrameLength - (bufcount - 1U) * ETH_TX_BUF_SIZE;
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
}
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/* point to next descriptor */
heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
}
}
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
{
/* Clear TBUS ETHERNET DMA flag */
(heth->Instance)->DMASR = ETH_DMASR_TBUS;
/* Resume DMA transmission*/
(heth->Instance)->DMATPDR = 0U;
}
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/**
* @brief Checks for received frames.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
{
uint32_t framelength = 0U;
/* Process Locked */
__HAL_LOCK(heth);
/* Check the ETH state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
/* Check if segment is not owned by DMA */
/* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
if (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
{
/* Check if last segment */
if (((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
{
/* increment segment count */
(heth->RxFrameInfos).SegCount++;
/* Check if last segment is first segment: one segment contains the frame */
if ((heth->RxFrameInfos).SegCount == 1U)
{
(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
}
heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
heth->RxFrameInfos.length = framelength;
/* Get the address of the buffer start address */
heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
/* point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef *)((heth->RxDesc)->Buffer2NextDescAddr);
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/* Check if first segment */
else if ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
{
(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
(heth->RxFrameInfos).LSRxDesc = NULL;
(heth->RxFrameInfos).SegCount = 1U;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
}
/* Check if intermediate segment */
else
{
(heth->RxFrameInfos).SegCount++;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
}
}
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_ERROR;
}
/**
* @brief Gets the Received frame in interrupt mode.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
{
uint32_t descriptorscancounter = 0U;
/* Process Locked */
__HAL_LOCK(heth);
/* Set ETH HAL State to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
/* Scan descriptors owned by CPU */
while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
{
/* Just for security */
descriptorscancounter++;
/* Check if first segment in frame */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
if ((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
heth->RxFrameInfos.SegCount = 1U;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
}
/* Check if intermediate segment */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
{
/* Increment segment count */
(heth->RxFrameInfos.SegCount)++;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
}
/* Should be last segment */
else
{
/* Last segment */
heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
/* Increment segment count */
(heth->RxFrameInfos.SegCount)++;
/* Check if last segment is first segment: one segment contains the frame */
if ((heth->RxFrameInfos.SegCount) == 1U)
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
}
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
/* Get the address of the buffer start address */
heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
}
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_ERROR;
}
/**
* @brief This function handles ETH interrupt request.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
{
/* Frame received */
if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
{
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/*Call registered Receive complete callback*/
heth->RxCpltCallback(heth);
#else
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Rx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
}
/* Frame transmitted */
else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
{
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/* Call resgistered Transfer complete callback*/
heth->TxCpltCallback(heth);
#else
/* Transfer complete callback */
HAL_ETH_TxCpltCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Tx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
}
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
/* ETH DMA Error */
if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
{
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
heth->DMAErrorCallback(heth);
#else
/* Ethernet Error callback */
HAL_ETH_ErrorCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
}
}
/**
* @brief Tx Transfer completed callbacks.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Ethernet transfer error callbacks
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Reads a PHY register
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
* PHY_BCR: Transceiver Basic Control Register,
* PHY_BSR: Transceiver Basic Status Register.
* More PHY register could be read depending on the used PHY
* @param RegValue: PHY register value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
uint32_t tmpreg1 = 0U;
uint32_t tickstart = 0U;
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if (heth->State == HAL_ETH_STATE_BUSY_RD)
{
return HAL_BUSY;
}
/* Set ETH HAL State to BUSY_RD */
heth->State = HAL_ETH_STATE_BUSY_RD;
/* Get the ETHERNET MACMIIAR value */
tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII address register value */
tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Write the result value into the MII Address register */
heth->Instance->MACMIIAR = tmpreg1;
/* Get tick */
tickstart = HAL_GetTick();
/* Check for the Busy flag */
while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > PHY_READ_TO)
{
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
return HAL_TIMEOUT;
}
tmpreg1 = heth->Instance->MACMIIAR;
}
/* Get MACMIIDR value */
*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
/* Set ETH HAL State to READY */
heth->State = HAL_ETH_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Writes to a PHY register.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
* PHY_BCR: Transceiver Control Register.
* More PHY register could be written depending on the used PHY
* @param RegValue: the value to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
{
uint32_t tmpreg1 = 0U;
uint32_t tickstart = 0U;
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if (heth->State == HAL_ETH_STATE_BUSY_WR)
{
return HAL_BUSY;
}
/* Set ETH HAL State to BUSY_WR */
heth->State = HAL_ETH_STATE_BUSY_WR;
/* Get the ETHERNET MACMIIAR value */
tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII register address value */
tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Give the value to the MII data register */
heth->Instance->MACMIIDR = (uint16_t)RegValue;
/* Write the result value into the MII Address register */
heth->Instance->MACMIIAR = tmpreg1;
/* Get tick */
tickstart = HAL_GetTick();
/* Check for the Busy flag */
while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > PHY_WRITE_TO)
{
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
return HAL_TIMEOUT;
}
tmpreg1 = heth->Instance->MACMIIAR;
}
/* Set ETH HAL State to READY */
heth->State = HAL_ETH_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Enable MAC and DMA transmission and reception.
HAL_ETH_Start();
(+) Disable MAC and DMA transmission and reception.
HAL_ETH_Stop();
(+) Set the MAC configuration in runtime mode
HAL_ETH_ConfigMAC();
(+) Set the DMA configuration in runtime mode
HAL_ETH_ConfigDMA();
@endverbatim
* @{
*/
/**
* @brief Enables Ethernet MAC and DMA reception/transmission
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
{
/* Process Locked */
__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
/* Enable transmit state machine of the MAC for transmission on the MII */
ETH_MACTransmissionEnable(heth);
/* Enable receive state machine of the MAC for reception from the MII */
ETH_MACReceptionEnable(heth);
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
/* Start DMA transmission */
ETH_DMATransmissionEnable(heth);
/* Start DMA reception */
ETH_DMAReceptionEnable(heth);
/* Set the ETH state to READY*/
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop Ethernet MAC and DMA reception/transmission
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
{
/* Process Locked */
__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
/* Stop DMA transmission */
ETH_DMATransmissionDisable(heth);
/* Stop DMA reception */
ETH_DMAReceptionDisable(heth);
/* Disable receive state machine of the MAC for reception from the MII */
ETH_MACReceptionDisable(heth);
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
/* Disable transmit state machine of the MAC for transmission on the MII */
ETH_MACTransmissionDisable(heth);
/* Set the ETH state*/
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/**
* @brief Set ETH MAC Configuration.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param macconf: MAC Configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
{
uint32_t tmpreg1 = 0U;
/* Process Locked */
__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
assert_param(IS_ETH_SPEED(heth->Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
if (macconf != NULL)
{
/* Check the parameters */
assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
assert_param(IS_ETH_JABBER(macconf->Jabber));
assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
tmpreg1 &= ETH_MACCR_CLEAR_MASK;
tmpreg1 |= (uint32_t)(macconf->Watchdog |
macconf->Jabber |
macconf->InterFrameGap |
macconf->CarrierSense |
(heth->Init).Speed |
macconf->ReceiveOwn |
macconf->LoopbackMode |
(heth->Init).DuplexMode |
macconf->ChecksumOffload |
macconf->RetryTransmission |
macconf->AutomaticPadCRCStrip |
macconf->BackOffLimit |
macconf->DeferralCheck);
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Write to ETHERNET MACFFR */
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
macconf->SourceAddrFilter |
macconf->PassControlFrames |
macconf->BroadcastFramesReception |
macconf->DestinationAddrFilter |
macconf->PromiscuousMode |
macconf->MulticastFramesFilter |
macconf->UnicastFramesFilter);
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
/* Write to ETHERNET MACHTHR */
(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
/* Write to ETHERNET MACHTLR */
(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
macconf->ZeroQuantaPause |
macconf->PauseLowThreshold |
macconf->UnicastPauseFrameDetect |
macconf->ReceiveFlowControl |
macconf->TransmitFlowControl);
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
macconf->VLANTagIdentifier);
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACVLANTR = tmpreg1;
}
else /* macconf == NULL : here we just configure Speed and Duplex mode */
{
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg1 = (heth->Instance)->MACCR;
/* Clear FES and DM bits */
tmpreg1 &= ~(0x00004800U);
tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;
}
/* Set the ETH state to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/**
* @brief Sets ETH DMA Configuration.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param dmaconf: DMA Configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
{
uint32_t tmpreg1 = 0U;
/* Process Locked */
__HAL_LOCK(heth);
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
/* Check parameters */
assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
/* Get the ETHERNET DMAOMR value */
tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
dmaconf->ReceiveStoreForward |
dmaconf->FlushReceivedFrame |
dmaconf->TransmitStoreForward |
dmaconf->TransmitThresholdControl |
dmaconf->ForwardErrorFrames |
dmaconf->ForwardUndersizedGoodFrames |
dmaconf->ReceiveThresholdControl |
dmaconf->SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
(heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration --------------------*/
(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
dmaconf->FixedBurst |
dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
dmaconf->TxDMABurstLength |
(dmaconf->DescriptorSkipLength << 2U) |
dmaconf->DMAArbitration |
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->DMABMR = tmpreg1;
/* Set the ETH state to Ready */
heth->State = HAL_ETH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(heth);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
(+) Get the ETH handle state:
HAL_ETH_GetState();
@endverbatim
* @{
*/
/**
* @brief Return the ETH HAL state
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL state
*/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
{
/* Return ETH state */
return heth->State;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup ETH_Private_Functions
* @{
*/
/**
* @brief Configures Ethernet MAC and DMA with default parameters.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param err: Ethernet Init error
* @retval HAL status
*/
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
{
ETH_MACInitTypeDef macinit;
ETH_DMAInitTypeDef dmainit;
uint32_t tmpreg1 = 0U;
if (err != ETH_SUCCESS) /* Auto-negotiation failed */
{
/* Set Ethernet duplex mode to Full-duplex */
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
/* Set Ethernet speed to 100M */
(heth->Init).Speed = ETH_SPEED_100M;
}
/* Ethernet MAC default initialization **************************************/
macinit.Watchdog = ETH_WATCHDOG_ENABLE;
macinit.Jabber = ETH_JABBER_ENABLE;
macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
{
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
}
else
{
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
}
macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
macinit.HashTableHigh = 0x0U;
macinit.HashTableLow = 0x0U;
macinit.PauseTime = 0x0U;
macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
macinit.VLANTagIdentifier = 0x0U;
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
tmpreg1 &= ETH_MACCR_CLEAR_MASK;
/* Set the WD bit according to ETH Watchdog value */
/* Set the JD: bit according to ETH Jabber value */
/* Set the IFG bit according to ETH InterFrameGap value */
/* Set the DCRS bit according to ETH CarrierSense value */
/* Set the FES bit according to ETH Speed value */
/* Set the DO bit according to ETH ReceiveOwn value */
/* Set the LM bit according to ETH LoopbackMode value */
/* Set the DM bit according to ETH Mode value */
/* Set the IPCO bit according to ETH ChecksumOffload value */
/* Set the DR bit according to ETH RetryTransmission value */
/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
/* Set the BL bit according to ETH BackOffLimit value */
/* Set the DC bit according to ETH DeferralCheck value */
tmpreg1 |= (uint32_t)(macinit.Watchdog |
macinit.Jabber |
macinit.InterFrameGap |
macinit.CarrierSense |
(heth->Init).Speed |
macinit.ReceiveOwn |
macinit.LoopbackMode |
(heth->Init).DuplexMode |
macinit.ChecksumOffload |
macinit.RetryTransmission |
macinit.AutomaticPadCRCStrip |
macinit.BackOffLimit |
macinit.DeferralCheck);
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Set the RA bit according to ETH ReceiveAll value */
/* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
/* Set the PCF bit according to ETH PassControlFrames value */
/* Set the DBF bit according to ETH BroadcastFramesReception value */
/* Set the DAIF bit according to ETH DestinationAddrFilter value */
/* Set the PR bit according to ETH PromiscuousMode value */
/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
/* Write to ETHERNET MACFFR */
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
macinit.SourceAddrFilter |
macinit.PassControlFrames |
macinit.BroadcastFramesReception |
macinit.DestinationAddrFilter |
macinit.PromiscuousMode |
macinit.MulticastFramesFilter |
macinit.UnicastFramesFilter);
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
/* Write to ETHERNET MACHTHR */
(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
/* Write to ETHERNET MACHTLR */
(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
/*----------------------- ETHERNET MACFCR Configuration -------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
/* Set the PT bit according to ETH PauseTime value */
/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
/* Set the PLT bit according to ETH PauseLowThreshold value */
/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
/* Set the RFE bit according to ETH ReceiveFlowControl value */
/* Set the TFE bit according to ETH TransmitFlowControl value */
tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
macinit.ZeroQuantaPause |
macinit.PauseLowThreshold |
macinit.UnicastPauseFrameDetect |
macinit.ReceiveFlowControl |
macinit.TransmitFlowControl);
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
/* Set the ETV bit according to ETH VLANTagComparison value */
/* Set the VL bit according to ETH VLANTagIdentifier value */
(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
macinit.VLANTagIdentifier);
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACVLANTR = tmpreg1;
/* Ethernet DMA default initialization ************************************/
dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
dmainit.DescriptorSkipLength = 0x0U;
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
/* Get the ETHERNET DMAOMR value */
tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
/* Set the RSF bit according to ETH ReceiveStoreForward value */
/* Set the DFF bit according to ETH FlushReceivedFrame value */
/* Set the TSF bit according to ETH TransmitStoreForward value */
/* Set the TTC bit according to ETH TransmitThresholdControl value */
/* Set the FEF bit according to ETH ForwardErrorFrames value */
/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
/* Set the RTC bit according to ETH ReceiveThresholdControl value */
/* Set the OSF bit according to ETH SecondFrameOperate value */
tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
dmainit.ReceiveStoreForward |
dmainit.FlushReceivedFrame |
dmainit.TransmitStoreForward |
dmainit.TransmitThresholdControl |
dmainit.ForwardErrorFrames |
dmainit.ForwardUndersizedGoodFrames |
dmainit.ReceiveThresholdControl |
dmainit.SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
(heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration ------------------*/
/* Set the AAL bit according to ETH AddressAlignedBeats value */
/* Set the FB bit according to ETH FixedBurst value */
/* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
/* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
/* Set the DSL bit according to ETH DesciptorSkipLength value */
/* Set the PR and DA bits according to ETH DMAArbitration value */
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
dmainit.FixedBurst |
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
dmainit.TxDMABurstLength |
(dmainit.DescriptorSkipLength << 2U) |
dmainit.DMAArbitration |
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->DMABMR = tmpreg1;
if ((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
{
/* Enable the Ethernet Rx Interrupt */
__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
}
/* Initialize MAC address in ethernet MAC */
ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
}
/**
* @brief Configures the selected MAC address.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @param MacAddr: The MAC address to configure
* This parameter can be one of the following values:
* @arg ETH_MAC_Address0: MAC Address0
* @arg ETH_MAC_Address1: MAC Address1
* @arg ETH_MAC_Address2: MAC Address2
* @arg ETH_MAC_Address3: MAC Address3
* @param Addr: Pointer to MAC address buffer data (6 bytes)
* @retval HAL status
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
uint32_t tmpreg1;
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* Check the parameters */
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Calculate the selected MAC address high register */
tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
/* Load the selected MAC address high register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
/* Calculate the selected MAC address low register */
tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
/* Load the selected MAC address low register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
}
/**
* @brief Enables the MAC transmission.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
{
__IO uint32_t tmpreg1 = 0U;
/* Enable the MAC transmission */
(heth->Instance)->MACCR |= ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
ETH_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;
}
/**
* @brief Disables the MAC transmission.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
{
__IO uint32_t tmpreg1 = 0U;
/* Disable the MAC transmission */
(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
ETH_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;
}
/**
* @brief Enables the MAC reception.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
{
__IO uint32_t tmpreg1 = 0U;
/* Enable the MAC reception */
(heth->Instance)->MACCR |= ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
ETH_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;
}
/**
* @brief Disables the MAC reception.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
{
__IO uint32_t tmpreg1 = 0U;
/* Disable the MAC reception */
(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
ETH_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->MACCR = tmpreg1;
}
/**
* @brief Enables the DMA transmission.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
{
/* Enable the DMA transmission */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
}
/**
* @brief Disables the DMA transmission.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
{
/* Disable the DMA transmission */
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
}
/**
* @brief Enables the DMA reception.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
{
/* Enable the DMA reception */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
}
/**
* @brief Disables the DMA reception.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
{
/* Disable the DMA reception */
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
}
/**
* @brief Clears the ETHERNET transmit FIFO.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
{
__IO uint32_t tmpreg1 = 0U;
/* Set the Flush Transmit FIFO bit */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->DMAOMR;
ETH_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->DMAOMR = tmpreg1;
}
/**
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void ETH_Delay(uint32_t mdelay)
{
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
do
{
__NOP();
}
while (Delay --);
}
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
{
/* Init the ETH Callback settings */
heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */
}
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
*/
#endif /* ETH */
#endif /* HAL_ETH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1738
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c Normal file
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@@ -0,0 +1,1738 @@
/**
******************************************************************************
* @file stm32f1xx_hal_hcd.c
* @author MCD Application Team
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#)Declare a HCD_HandleTypeDef handle structure, for example:
HCD_HandleTypeDef hhcd;
(#)Fill parameters of Init structure in HCD handle
(#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
(#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
(##) Enable the HCD/USB Low Level interface clock using the following macros
(+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
(##) Initialize the related GPIO clocks
(##) Configure HCD pin-out
(##) Configure HCD NVIC interrupt
(#)Associate the Upper USB Host stack to the HAL HCD Driver:
(##) hhcd.pData = phost;
(#)Enable HCD transmission and reception:
(##) HAL_HCD_Start();
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_HCD_MODULE_ENABLED
#if defined (USB_OTG_FS)
/** @defgroup HCD HCD
* @brief HCD HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup HCD_Private_Functions HCD Private Functions
* @{
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HCD_Exported_Functions HCD Exported Functions
* @{
*/
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
@endverbatim
* @{
*/
/**
* @brief Initialize the host driver.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
if (hhcd->State == HAL_HCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhcd->Lock = HAL_UNLOCKED;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->SOFCallback = HAL_HCD_SOF_Callback;
hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
if (hhcd->MspInitCallback == NULL)
{
hhcd->MspInitCallback = HAL_HCD_MspInit;
}
/* Init the low level hardware */
hhcd->MspInitCallback(hhcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_HCD_MspInit(hhcd);
#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
}
hhcd->State = HAL_HCD_STATE_BUSY;
/* Disable DMA mode for FS instance */
hhcd->Init.dma_enable = 0U;
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */
if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
{
hhcd->State = HAL_HCD_STATE_ERROR;
return HAL_ERROR;
}
/* Force Host Mode */
if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
{
hhcd->State = HAL_HCD_STATE_ERROR;
return HAL_ERROR;
}
/* Init Host */
if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
{
hhcd->State = HAL_HCD_STATE_ERROR;
return HAL_ERROR;
}
hhcd->State = HAL_HCD_STATE_READY;
return HAL_OK;
}
/**
* @brief Initialize a host channel.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @param epnum Endpoint number.
* This parameter can be a value from 1 to 15
* @param dev_address Current device address
* This parameter can be a value from 0 to 255
* @param speed Current device speed.
* This parameter can be one of these values:
* HCD_DEVICE_SPEED_FULL: Full speed mode,
* HCD_DEVICE_SPEED_LOW: Low speed mode
* @param ep_type Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type,
* EP_TYPE_ISOC: Isochronous type,
* EP_TYPE_BULK: Bulk type,
* EP_TYPE_INTR: Interrupt type
* @param mps Max Packet Size.
* This parameter can be a value from 0 to32K
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum,
uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
{
HAL_StatusTypeDef status;
uint32_t HCcharMps = mps;
__HAL_LOCK(hhcd);
hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[ch_num].dev_addr = dev_address;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].ep_type = ep_type;
hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
(void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num);
if ((epnum & 0x80U) == 0x80U)
{
hhcd->hc[ch_num].ep_is_in = 1U;
}
else
{
hhcd->hc[ch_num].ep_is_in = 0U;
}
hhcd->hc[ch_num].speed = speed;
hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps;
status = USB_HC_Init(hhcd->Instance, ch_num, epnum,
dev_address, speed, ep_type, (uint16_t)HCcharMps);
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief Halt a host channel.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
{
HAL_StatusTypeDef status = HAL_OK;
__HAL_LOCK(hhcd);
(void)USB_HC_Halt(hhcd->Instance, ch_num);
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief DeInitialize the host driver.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
{
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
return HAL_ERROR;
}
hhcd->State = HAL_HCD_STATE_BUSY;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
if (hhcd->MspDeInitCallback == NULL)
{
hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hhcd->MspDeInitCallback(hhcd);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_HCD_MspDeInit(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
__HAL_HCD_DISABLE(hhcd);
hhcd->State = HAL_HCD_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initialize the HCD MSP.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the HCD MSP.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @brief HCD IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to manage the USB Host Data
Transfer
@endverbatim
* @{
*/
/**
* @brief Submit a new URB for processing.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @param direction Channel number.
* This parameter can be one of these values:
* 0 : Output / 1 : Input
* @param ep_type Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type/
* EP_TYPE_ISOC: Isochronous type/
* EP_TYPE_BULK: Bulk type/
* EP_TYPE_INTR: Interrupt type/
* @param token Endpoint Type.
* This parameter can be one of these values:
* 0: HC_PID_SETUP / 1: HC_PID_DATA1
* @param pbuff pointer to URB data
* @param length Length of URB data
* @param do_ping activate do ping protocol (for high speed only).
* This parameter can be one of these values:
* 0 : do ping inactive / 1 : do ping active
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
uint8_t direction,
uint8_t ep_type,
uint8_t token,
uint8_t *pbuff,
uint16_t length,
uint8_t do_ping)
{
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
if (token == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
hhcd->hc[ch_num].do_ping = do_ping;
}
else
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
/* Manage Data Toggle */
switch (ep_type)
{
case EP_TYPE_CTRL:
if (token == 1U) /* send data */
{
if (direction == 0U)
{
if (length == 0U)
{
/* For Status OUT stage, Length == 0U, Status Out PID = 1 */
hhcd->hc[ch_num].toggle_out = 1U;
}
/* Set the Data Toggle bit as per the Flag */
if (hhcd->hc[ch_num].toggle_out == 0U)
{
/* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
/* Put the PID 1 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
}
break;
case EP_TYPE_BULK:
if (direction == 0U)
{
/* Set the Data Toggle bit as per the Flag */
if (hhcd->hc[ch_num].toggle_out == 0U)
{
/* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
/* Put the PID 1 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
else
{
if (hhcd->hc[ch_num].toggle_in == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
break;
case EP_TYPE_INTR:
if (direction == 0U)
{
/* Set the Data Toggle bit as per the Flag */
if (hhcd->hc[ch_num].toggle_out == 0U)
{
/* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
/* Put the PID 1 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
else
{
if (hhcd->hc[ch_num].toggle_in == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
break;
case EP_TYPE_ISOC:
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
break;
default:
break;
}
hhcd->hc[ch_num].xfer_buff = pbuff;
hhcd->hc[ch_num].xfer_len = length;
hhcd->hc[ch_num].urb_state = URB_IDLE;
hhcd->hc[ch_num].xfer_count = 0U;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].state = HC_IDLE;
return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num]);
}
/**
* @brief Handle HCD interrupt request.
* @param hhcd HCD handle
* @retval None
*/
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i;
uint32_t interrupt;
/* Ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
{
/* Avoid spurious interrupt */
if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
{
return;
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
}
/* Handle Host Disconnect Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
{
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
{
/* Flush USB Fifo */
(void)USB_FlushTxFifo(USBx, 0x10U);
(void)USB_FlushRxFifo(USBx);
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
{
/* Restore FS Clock */
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
}
/* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->DisconnectCallback(hhcd);
#else
HAL_HCD_Disconnect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
}
/* Handle Host Port Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
{
HCD_Port_IRQHandler(hhcd);
}
/* Handle Host SOF Interrupt */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
{
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->SOFCallback(hhcd);
#else
HAL_HCD_SOF_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
/* Handle Host channel Interrupt */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
for (i = 0U; i < hhcd->Init.Host_channels; i++)
{
if ((interrupt & (1UL << (i & 0xFU))) != 0U)
{
if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
{
HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
}
else
{
HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
}
}
}
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
}
/* Handle Rx Queue Level Interrupts */
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
HCD_RXQLVL_IRQHandler(hhcd);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
}
}
/**
* @brief Handles HCD Wakeup interrupt request.
* @param hhcd HCD handle
* @retval HAL status
*/
void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd)
{
UNUSED(hhcd);
}
/**
* @brief SOF callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_SOF_Callback could be implemented in the user file
*/
}
/**
* @brief Connection Event callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Connect_Callback could be implemented in the user file
*/
}
/**
* @brief Disconnection Event callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
}
/**
* @brief Port Enabled Event callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
}
/**
* @brief Port Disabled Event callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
}
/**
* @brief Notify URB state change callback.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @param urb_state:
* This parameter can be one of these values:
* URB_IDLE/
* URB_DONE/
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
* URB_STALL/
* @retval None
*/
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
UNUSED(chnum);
UNUSED(urb_state);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
*/
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User USB HCD Callback
* To be used instead of the weak predefined callback
* @param hhcd USB HCD handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
* @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
* @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
* @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
* @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
* @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
HAL_HCD_CallbackIDTypeDef CallbackID,
pHCD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hhcd);
if (hhcd->State == HAL_HCD_STATE_READY)
{
switch (CallbackID)
{
case HAL_HCD_SOF_CB_ID :
hhcd->SOFCallback = pCallback;
break;
case HAL_HCD_CONNECT_CB_ID :
hhcd->ConnectCallback = pCallback;
break;
case HAL_HCD_DISCONNECT_CB_ID :
hhcd->DisconnectCallback = pCallback;
break;
case HAL_HCD_PORT_ENABLED_CB_ID :
hhcd->PortEnabledCallback = pCallback;
break;
case HAL_HCD_PORT_DISABLED_CB_ID :
hhcd->PortDisabledCallback = pCallback;
break;
case HAL_HCD_MSPINIT_CB_ID :
hhcd->MspInitCallback = pCallback;
break;
case HAL_HCD_MSPDEINIT_CB_ID :
hhcd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hhcd->State == HAL_HCD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_HCD_MSPINIT_CB_ID :
hhcd->MspInitCallback = pCallback;
break;
case HAL_HCD_MSPDEINIT_CB_ID :
hhcd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief Unregister an USB HCD Callback
* USB HCD callback is redirected to the weak predefined callback
* @param hhcd USB HCD handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
* @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
* @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
* @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
* @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
* @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hhcd);
/* Setup Legacy weak Callbacks */
if (hhcd->State == HAL_HCD_STATE_READY)
{
switch (CallbackID)
{
case HAL_HCD_SOF_CB_ID :
hhcd->SOFCallback = HAL_HCD_SOF_Callback;
break;
case HAL_HCD_CONNECT_CB_ID :
hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
break;
case HAL_HCD_DISCONNECT_CB_ID :
hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
break;
case HAL_HCD_PORT_ENABLED_CB_ID :
hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
break;
case HAL_HCD_PORT_DISABLED_CB_ID :
hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
break;
case HAL_HCD_MSPINIT_CB_ID :
hhcd->MspInitCallback = HAL_HCD_MspInit;
break;
case HAL_HCD_MSPDEINIT_CB_ID :
hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
break;
default :
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hhcd->State == HAL_HCD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_HCD_MSPINIT_CB_ID :
hhcd->MspInitCallback = HAL_HCD_MspInit;
break;
case HAL_HCD_MSPDEINIT_CB_ID :
hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
break;
default :
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief Register USB HCD Host Channel Notify URB Change Callback
* To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
* @param hhcd HCD handle
* @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hhcd);
if (hhcd->State == HAL_HCD_STATE_READY)
{
hhcd->HC_NotifyURBChangeCallback = pCallback;
}
else
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief Unregister the USB HCD Host Channel Notify URB Change Callback
* USB HCD Host Channel Notify URB Change Callback is redirected
* to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hhcd);
if (hhcd->State == HAL_HCD_STATE_READY)
{
hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */
}
else
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhcd);
return status;
}
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @brief Management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the HCD data
transfers.
@endverbatim
* @{
*/
/**
* @brief Start the host driver.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
{
__HAL_LOCK(hhcd);
/* Enable port power */
(void)USB_DriveVbus(hhcd->Instance, 1U);
/* Enable global interrupt */
__HAL_HCD_ENABLE(hhcd);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
/**
* @brief Stop the host driver.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
{
__HAL_LOCK(hhcd);
(void)USB_StopHost(hhcd->Instance);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
/**
* @brief Reset the host port.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
{
return (USB_ResetPort(hhcd->Instance));
}
/**
* @}
*/
/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the HCD handle state.
* @param hhcd HCD handle
* @retval HAL state
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd)
{
return hhcd->State;
}
/**
* @brief Return URB state for a channel.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval URB state.
* This parameter can be one of these values:
* URB_IDLE/
* URB_DONE/
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
* URB_STALL
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].urb_state;
}
/**
* @brief Return the last host transfer size.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval last transfer size in byte
*/
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].xfer_count;
}
/**
* @brief Return the Host Channel state.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval Host channel state
* This parameter can be one of these values:
* HC_IDLE/
* HC_XFRC/
* HC_HALTED/
* HC_NYET/
* HC_NAK/
* HC_STALL/
* HC_XACTERR/
* HC_BBLERR/
* HC_DATATGLERR
*/
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].state;
}
/**
* @brief Return the current Host frame number.
* @param hhcd HCD handle
* @retval Current Host frame number
*/
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
{
return (USB_GetCurrentFrame(hhcd->Instance));
}
/**
* @brief Return the Host enumeration speed.
* @param hhcd HCD handle
* @retval Enumeration speed
*/
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
{
return (USB_GetHostSpeed(hhcd->Instance));
}
/**
* @brief Set host channel Hub information.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @param addr Hub address
* @param PortNbr Hub port number
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
uint8_t addr, uint8_t PortNbr)
{
hhcd->hc[ch_num].hub_addr = addr;
hhcd->hc[ch_num].hub_port_nbr = PortNbr;
return HAL_OK;
}
/**
* @brief Clear host channel hub information.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
{
hhcd->hc[ch_num].hub_addr = 0U;
hhcd->hc[ch_num].hub_port_nbr = 0U;
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup HCD_Private_Functions
* @{
*/
/**
* @brief Handle Host Channel IN interrupt requests.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
hhcd->hc[chnum].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR);
hhcd->hc[chnum].state = HC_BBLERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
hhcd->hc[chnum].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
hhcd->hc[chnum].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
hhcd->hc[chnum].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else
{
/* ... */
}
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
{
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
{
hhcd->hc[chnum].state = HC_XFRC;
hhcd->hc[chnum].ErrCnt = 0U;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_ISOC))
{
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[chnum].urb_state = URB_DONE;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
/* ... */
}
if (hhcd->Init.dma_enable == 1U)
{
if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U)
{
hhcd->hc[chnum].toggle_in ^= 1U;
}
}
else
{
hhcd->hc[chnum].toggle_in ^= 1U;
}
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
if (hhcd->hc[chnum].state == HC_XFRC)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_DONE;
}
else if (hhcd->hc[chnum].state == HC_STALL)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_STALL;
}
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].ErrCnt++;
if (hhcd->hc[chnum].ErrCnt > 2U)
{
hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
}
}
else if (hhcd->hc[chnum].state == HC_NYET)
{
hhcd->hc[chnum].state = HC_HALTED;
}
else if (hhcd->hc[chnum].state == HC_ACK)
{
hhcd->hc[chnum].state = HC_HALTED;
}
else if (hhcd->hc[chnum].state == HC_NAK)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
}
else if (hhcd->hc[chnum].state == HC_BBLERR)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].ErrCnt++;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
{
if (hhcd->hc[chnum].state == HC_HALTED)
{
return;
}
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
hhcd->hc[chnum].state = HC_NYET;
hhcd->hc[chnum].ErrCnt = 0U;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
{
if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
{
hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].state = HC_NAK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].state = HC_NAK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else
{
/* ... */
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
else
{
/* ... */
}
}
/**
* @brief Handle Host Channel OUT interrupt requests.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
uint32_t num_packets;
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
hhcd->hc[chnum].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
{
hhcd->hc[chnum].ErrCnt = 0U;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
hhcd->hc[chnum].state = HC_XFRC;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
hhcd->hc[chnum].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
{
hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].state = HC_NAK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
{
hhcd->hc[chnum].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
{
hhcd->hc[chnum].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
if (hhcd->hc[chnum].state == HC_XFRC)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_DONE;
if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_INTR))
{
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[chnum].toggle_out ^= 1U;
}
if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U))
{
num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet;
if ((num_packets & 1U) != 0U)
{
hhcd->hc[chnum].toggle_out ^= 1U;
}
}
}
}
else if (hhcd->hc[chnum].state == HC_ACK)
{
hhcd->hc[chnum].state = HC_HALTED;
}
else if (hhcd->hc[chnum].state == HC_NAK)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
}
else if (hhcd->hc[chnum].state == HC_STALL)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_STALL;
}
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].ErrCnt++;
if (hhcd->hc[chnum].ErrCnt > 2U)
{
hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
}
else
{
return;
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
return;
}
}
/**
* @brief Handle Rx Queue Level interrupt requests.
* @param hhcd HCD handle
* @retval none
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts;
uint32_t pktcnt;
uint32_t GrxstspReg;
uint32_t xferSizePktCnt;
uint32_t tmpreg;
uint32_t chnum;
GrxstspReg = hhcd->Instance->GRXSTSP;
chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
switch (pktsts)
{
case GRXSTS_PKTSTS_IN:
/* Read the data into the host buffer. */
if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0))
{
if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len)
{
(void)USB_ReadPacket(hhcd->Instance,
hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt);
/* manage multiple Xfer */
hhcd->hc[chnum].xfer_buff += pktcnt;
hhcd->hc[chnum].xfer_count += pktcnt;
/* get transfer size packet count */
xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U))
{
/* re-activate the channel when more packets are expected */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
hhcd->hc[chnum].toggle_in ^= 1U;
}
}
else
{
hhcd->hc[chnum].urb_state = URB_ERROR;
}
}
break;
case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
break;
case GRXSTS_PKTSTS_IN_XFER_COMP:
case GRXSTS_PKTSTS_CH_HALTED:
default:
break;
}
}
/**
* @brief Handle Host Port interrupt requests.
* @param hhcd HCD handle
* @retval None
*/
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0;
__IO uint32_t hprt0_dup;
/* Handle Host Port Interrupts */
hprt0 = USBx_HPRT0;
hprt0_dup = USBx_HPRT0;
hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
/* Check whether Port Connect detected */
if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
{
if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->ConnectCallback(hhcd);
#else
HAL_HCD_Connect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
hprt0_dup |= USB_OTG_HPRT_PCDET;
}
/* Check whether Port Enable Changed */
if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
{
hprt0_dup |= USB_OTG_HPRT_PENCHNG;
if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
{
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
{
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
{
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
}
else
{
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
}
}
else
{
if (hhcd->Init.speed == HCD_SPEED_FULL)
{
USBx_HOST->HFIR = HFIR_60_MHZ;
}
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortEnabledCallback(hhcd);
#else
HAL_HCD_PortEnabled_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortDisabledCallback(hhcd);
#else
HAL_HCD_PortDisabled_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
}
/* Check for an overcurrent */
if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
{
hprt0_dup |= USB_OTG_HPRT_POCCHNG;
}
/* Clear Port Interrupts */
USBx_HPRT0 = hprt0_dup;
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB_OTG_FS) */
#endif /* HAL_HCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1876
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c Normal file
View File

@@ -0,0 +1,1876 @@
/**
******************************************************************************
* @file stm32f1xx_hal_i2s.c
* @author MCD Application Team
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The I2S HAL driver can be used as follow:
(#) Declare a I2S_HandleTypeDef handle structure.
(#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
(##) Enable the SPIx interface clock.
(##) I2S pins configuration:
(+++) Enable the clock for the I2S GPIOs.
(+++) Configure these I2S pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
and HAL_I2S_Receive_IT() APIs).
(+++) Configure the I2Sx interrupt priority.
(+++) Enable the NVIC I2S IRQ handle.
(##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
and HAL_I2S_Receive_DMA() APIs:
(+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream/Channel.
(+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
DMA Tx/Rx Stream/Channel.
(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
using HAL_I2S_Init() function.
-@- The specific I2S interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
-@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).
For connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO (2 x PLL3CLK) clock
in order to achieve the maximum accuracy.
-@- Make sure that either:
(+@) External clock source is configured after setting correctly
the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file.
(#) Three mode of operations are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
(+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
*** Interrupt mode IO operation ***
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
*** DMA mode IO operation ***
==============================
[..]
(+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
(+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
inside DR register and avoid using DeInit/Init process for the next transfer.
*** I2S HAL driver macros list ***
===================================
[..]
Below the list of most used macros in I2S HAL driver.
(+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
(+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
[..]
(@) You can refer to the I2S HAL driver header file for more useful macros
*** I2S HAL driver macros list ***
===================================
[..]
Callback registration:
(#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
Function HAL_I2S_RegisterCallback() allows to register following callbacks:
(++) TxCpltCallback : I2S Tx Completed callback
(++) RxCpltCallback : I2S Rx Completed callback
(++) TxHalfCpltCallback : I2S Tx Half Completed callback
(++) RxHalfCpltCallback : I2S Rx Half Completed callback
(++) ErrorCallback : I2S Error callback
(++) MspInitCallback : I2S Msp Init callback
(++) MspDeInitCallback : I2S Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
weak function.
HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(++) TxCpltCallback : I2S Tx Completed callback
(++) RxCpltCallback : I2S Rx Completed callback
(++) TxHalfCpltCallback : I2S Tx Half Completed callback
(++) RxHalfCpltCallback : I2S Rx Half Completed callback
(++) ErrorCallback : I2S Error callback
(++) MspInitCallback : I2S Msp Init callback
(++) MspDeInitCallback : I2S Msp DeInit callback
[..]
By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
or HAL_I2S_Init() function.
[..]
When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
*** I2S Workarounds linked to Silicon Limitation ***
====================================================
[..]
(@) Only the 16-bit mode with no data extension can be used when the I2S
is in Master and used the PCM long synchronization mode.
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
#ifdef HAL_I2S_MODULE_ENABLED
#if defined(SPI_I2S_SUPPORT)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup I2S I2S
* @brief I2S HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup I2S_Private_Functions I2S Private Functions
* @{
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMAError(DMA_HandleTypeDef *hdma);
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
uint32_t Timeout);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup I2S_Exported_Functions I2S Exported Functions
* @{
*/
/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
de-initialize the I2Sx peripheral in simplex mode:
(+) User must Implement HAL_I2S_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
(+) Call the function HAL_I2S_Init() to configure the selected device with
the selected configuration:
(++) Mode
(++) Standard
(++) Data Format
(++) MCLK Output
(++) Audio frequency
(++) Polarity
(+) Call the function HAL_I2S_DeInit() to restore the default configuration
of the selected I2Sx peripheral.
@endverbatim
* @{
*/
/**
* @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
uint32_t i2sdiv;
uint32_t i2sodd;
uint32_t packetlength;
uint32_t tmp;
uint32_t i2sclk;
/* Check the I2S handle allocation */
if (hi2s == NULL)
{
return HAL_ERROR;
}
/* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
assert_param(IS_I2S_MODE(hi2s->Init.Mode));
assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
if (hi2s->State == HAL_I2S_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hi2s->Lock = HAL_UNLOCKED;
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
/* Init the I2S Callback settings */
hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
if (hi2s->MspInitCallback == NULL)
{
hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hi2s->MspInitCallback(hi2s);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
hi2s->State = HAL_I2S_STATE_BUSY;
/*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
hi2s->Instance->I2SPR = 0x0002U;
/*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
/* If the requested audio frequency is not the default, compute the prescaler */
if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
{
/* Check the frame length (For the Prescaler computing) ********************/
if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
{
/* Packet length is 16 bits */
packetlength = 16U;
}
else
{
/* Packet length is 32 bits */
packetlength = 32U;
}
/* I2S standard */
if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
{
/* In I2S standard packet length is multiplied by 2 */
packetlength = packetlength * 2U;
}
/* Get the source clock value **********************************************/
if (hi2s->Instance == SPI2)
{
/* Get the source clock value: based on SPI2 Instance */
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S2);
}
else if (hi2s->Instance == SPI3)
{
/* Get the source clock value: based on SPI3 Instance */
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S3);
}
else
{
/* Get the source clock value: based on System Clock value */
i2sclk = HAL_RCC_GetSysClockFreq();
}
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
{
/* MCLK output is enabled */
if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
{
tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
else
{
tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
}
else
{
/* MCLK output is disabled */
tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
/* Remove the flatting point */
tmp = tmp / 10U;
/* Check the parity of the divider */
i2sodd = (uint32_t)(tmp & (uint32_t)1U);
/* Compute the i2sdiv prescaler */
i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
i2sodd = (uint32_t)(i2sodd << 8U);
}
else
{
/* Set the default values */
i2sdiv = 2U;
i2sodd = 0U;
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
{
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
return HAL_ERROR;
}
/*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
/* Write to SPIx I2SPR register the computed value */
hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
/* And configure the I2S with the I2S_InitStruct values */
MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
hi2s->Init.Standard | hi2s->Init.DataFormat | \
hi2s->Init.CPOL));
#if defined(SPI_I2SCFGR_ASTRTEN)
if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
{
/* Write to SPIx I2SCFGR */
SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
}
#endif /* SPI_I2SCFGR_ASTRTEN */
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State = HAL_I2S_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the I2S peripheral
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
{
/* Check the I2S handle allocation */
if (hi2s == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
hi2s->State = HAL_I2S_STATE_BUSY;
/* Disable the I2S Peripheral Clock */
__HAL_I2S_DISABLE(hi2s);
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
if (hi2s->MspDeInitCallback == NULL)
{
hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
hi2s->MspDeInitCallback(hi2s);
#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_I2S_MspDeInit(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State = HAL_I2S_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
/**
* @brief I2S MSP Init
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspInit could be implemented in the user file
*/
}
/**
* @brief I2S MSP DeInit
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspDeInit could be implemented in the user file
*/
}
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User I2S Callback
* To be used instead of the weak predefined callback
* @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for the specified I2S.
* @param CallbackID ID of the callback to be registered
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
pI2S_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hi2s);
if (HAL_I2S_STATE_READY == hi2s->State)
{
switch (CallbackID)
{
case HAL_I2S_TX_COMPLETE_CB_ID :
hi2s->TxCpltCallback = pCallback;
break;
case HAL_I2S_RX_COMPLETE_CB_ID :
hi2s->RxCpltCallback = pCallback;
break;
case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
hi2s->TxHalfCpltCallback = pCallback;
break;
case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
hi2s->RxHalfCpltCallback = pCallback;
break;
case HAL_I2S_ERROR_CB_ID :
hi2s->ErrorCallback = pCallback;
break;
case HAL_I2S_MSPINIT_CB_ID :
hi2s->MspInitCallback = pCallback;
break;
case HAL_I2S_MSPDEINIT_CB_ID :
hi2s->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_I2S_STATE_RESET == hi2s->State)
{
switch (CallbackID)
{
case HAL_I2S_MSPINIT_CB_ID :
hi2s->MspInitCallback = pCallback;
break;
case HAL_I2S_MSPDEINIT_CB_ID :
hi2s->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hi2s);
return status;
}
/**
* @brief Unregister an I2S Callback
* I2S callback is redirected to the weak predefined callback
* @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for the specified I2S.
* @param CallbackID ID of the callback to be unregistered
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hi2s);
if (HAL_I2S_STATE_READY == hi2s->State)
{
switch (CallbackID)
{
case HAL_I2S_TX_COMPLETE_CB_ID :
hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_I2S_RX_COMPLETE_CB_ID :
hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_I2S_ERROR_CB_ID :
hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_I2S_MSPINIT_CB_ID :
hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
break;
case HAL_I2S_MSPDEINIT_CB_ID :
hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_I2S_STATE_RESET == hi2s->State)
{
switch (CallbackID)
{
case HAL_I2S_MSPINIT_CB_ID :
hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
break;
case HAL_I2S_MSPDEINIT_CB_ID :
hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hi2s);
return status;
}
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the I2S data
transfers.
(#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
The end of the data processing will be indicated through the
dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
(#) Blocking mode functions are :
(++) HAL_I2S_Transmit()
(++) HAL_I2S_Receive()
(#) No-Blocking mode functions with Interrupt are :
(++) HAL_I2S_Transmit_IT()
(++) HAL_I2S_Receive_IT()
(#) No-Blocking mode functions with DMA are :
(++) HAL_I2S_Transmit_DMA()
(++) HAL_I2S_Receive_DMA()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2S_TxCpltCallback()
(++) HAL_I2S_RxCpltCallback()
(++) HAL_I2S_ErrorCallback()
@endverbatim
* @{
*/
/**
* @brief Transmit an amount of data in blocking mode
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pData a 16-bit pointer to data buffer.
* @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 24-bit or 32-bit data length.
* @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tmpreg_cfgr;
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
if (hi2s->State != HAL_I2S_STATE_READY)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->pTxBuffPtr = pData;
tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = (Size << 1U);
hi2s->TxXferCount = (Size << 1U);
}
else
{
hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
}
tmpreg_cfgr = hi2s->Instance->I2SCFGR;
/* Check if the I2S is already enabled */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
/* Wait until TXE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
while (hi2s->TxXferCount > 0U)
{
hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
hi2s->pTxBuffPtr++;
hi2s->TxXferCount--;
/* Wait until TXE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
/* Check if an underrun occurs */
if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
{
/* Clear underrun flag */
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
}
}
/* Check if Slave mode is selected */
if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
|| ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
/* Wait until Busy flag is reset */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
}
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
/**
* @brief Receive an amount of data in blocking mode
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pData a 16-bit pointer to data buffer.
* @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 24-bit or 32-bit data length.
* @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
* in continuous way and as the I2S is not disabled at the end of the I2S transaction.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tmpreg_cfgr;
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
if (hi2s->State != HAL_I2S_STATE_READY)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->pRxBuffPtr = pData;
tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = (Size << 1U);
hi2s->RxXferCount = (Size << 1U);
}
else
{
hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
/* Check if the I2S is already enabled */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
/* Check if Master Receiver mode is selected */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
access to the SPI_SR register. */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
/* Receive data */
while (hi2s->RxXferCount > 0U)
{
/* Wait until RXNE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
(*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
hi2s->pRxBuffPtr++;
hi2s->RxXferCount--;
/* Check if an overrun occurs */
if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
{
/* Clear overrun flag */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
}
}
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pData a 16-bit pointer to data buffer.
* @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t tmpreg_cfgr;
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
if (hi2s->State != HAL_I2S_STATE_READY)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->pTxBuffPtr = pData;
tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = (Size << 1U);
hi2s->TxXferCount = (Size << 1U);
}
else
{
hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
}
__HAL_UNLOCK(hi2s);
/* Enable TXE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
/* Check if the I2S is already enabled */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
return HAL_OK;
}
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pData a 16-bit pointer to the Receive data buffer.
* @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
* between Master and Slave otherwise the I2S interrupt should be optimized.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t tmpreg_cfgr;
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
if (hi2s->State != HAL_I2S_STATE_READY)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->pRxBuffPtr = pData;
tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = (Size << 1U);
hi2s->RxXferCount = (Size << 1U);
}
else
{
hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
__HAL_UNLOCK(hi2s);
/* Enable RXNE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
/* Check if the I2S is already enabled */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
return HAL_OK;
}
/**
* @brief Transmit an amount of data in non-blocking mode with DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pData a 16-bit pointer to the Transmit data buffer.
* @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t tmpreg_cfgr;
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
if (hi2s->State != HAL_I2S_STATE_READY)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->pTxBuffPtr = pData;
tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = (Size << 1U);
hi2s->TxXferCount = (Size << 1U);
}
else
{
hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
}
/* Set the I2S Tx DMA Half transfer complete callback */
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
/* Set the I2S Tx DMA transfer complete callback */
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
/* Set the DMA error callback */
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
/* Enable the Tx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
(uint32_t)hi2s->pTxBuffPtr,
(uint32_t)&hi2s->Instance->DR,
hi2s->TxXferSize))
{
/* Update SPI error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
__HAL_UNLOCK(hi2s);
/* Check if the I2S Tx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
{
/* Enable Tx DMA Request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
/* Check if the I2S is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
return HAL_OK;
}
/**
* @brief Receive an amount of data in non-blocking mode with DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pData a 16-bit pointer to the Receive data buffer.
* @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t tmpreg_cfgr;
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
if (hi2s->State != HAL_I2S_STATE_READY)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set state and reset error code */
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->pRxBuffPtr = pData;
tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = (Size << 1U);
hi2s->RxXferCount = (Size << 1U);
}
else
{
hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
/* Set the I2S Rx DMA Half transfer complete callback */
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
/* Set the I2S Rx DMA transfer complete callback */
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
/* Set the DMA error callback */
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
/* Check if Master Receiver mode is selected */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
/* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
access to the SPI_SR register. */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
/* Enable the Rx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
hi2s->RxXferSize))
{
/* Update SPI error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
hi2s->State = HAL_I2S_STATE_READY;
__HAL_UNLOCK(hi2s);
return HAL_ERROR;
}
__HAL_UNLOCK(hi2s);
/* Check if the I2S Rx request is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
{
/* Enable Rx DMA Request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
/* Check if the I2S is already enabled */
if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
return HAL_OK;
}
/**
* @brief Pauses the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Disable the I2S DMA Tx request */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Disable the I2S DMA Rx request */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
else
{
/* nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
/**
* @brief Resumes the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Enable the I2S DMA Tx request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Enable the I2S DMA Rx request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
else
{
/* nothing to do */
}
/* If the I2S peripheral is still not enabled, enable it */
if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
/**
* @brief Stops the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
*/
if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
{
/* Abort the I2S DMA tx Stream/Channel */
if (hi2s->hdmatx != NULL)
{
/* Disable the I2S DMA tx Stream/Channel */
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
{
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
errorcode = HAL_ERROR;
}
}
/* Wait until TXE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
/* Wait until BSY flag is Reset */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
/* Clear UDR flag */
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
/* Disable the I2S Tx DMA requests */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
{
/* Abort the I2S DMA rx Stream/Channel */
if (hi2s->hdmarx != NULL)
{
/* Disable the I2S DMA rx Stream/Channel */
if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
{
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
errorcode = HAL_ERROR;
}
}
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
/* Clear OVR flag */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
/* Disable the I2S Rx DMA request */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
{
/* Set the error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
errorcode = HAL_ERROR;
}
else
{
/* Read DR to Flush RX Data */
READ_REG((hi2s->Instance)->DR);
}
}
hi2s->State = HAL_I2S_STATE_READY;
return errorcode;
}
/**
* @brief This function handles I2S interrupt request.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
uint32_t itsource = hi2s->Instance->CR2;
uint32_t itflag = hi2s->Instance->SR;
/* I2S in mode Receiver ------------------------------------------------*/
if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
(I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
{
I2S_Receive_IT(hi2s);
return;
}
/* I2S in mode Tramitter -----------------------------------------------*/
if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
{
I2S_Transmit_IT(hi2s);
return;
}
/* I2S interrupt error -------------------------------------------------*/
if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
{
/* I2S Overrun error interrupt occurred ---------------------------------*/
if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
}
/* I2S Underrun error interrupt occurred --------------------------------*/
if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
}
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
/* Call user error callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->ErrorCallback(hi2s);
#else
HAL_I2S_ErrorCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
/**
* @brief Tx Transfer Half completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx Transfer completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer half completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
}
/**
* @brief I2S error callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_ErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the I2S state
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL state
*/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
{
return hi2s->State;
}
/**
* @brief Return the I2S error code
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval I2S Error Code
*/
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
{
return hi2s->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup I2S_Private_Functions I2S Private Functions
* @{
*/
/**
* @brief DMA I2S transmit process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* if DMA is configured in DMA_NORMAL Mode */
if (hdma->Init.Mode == DMA_NORMAL)
{
/* Disable Tx DMA Request */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
hi2s->TxXferCount = 0U;
hi2s->State = HAL_I2S_STATE_READY;
}
/* Call user Tx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxCpltCallback(hi2s);
#else
HAL_I2S_TxCpltCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
* @brief DMA I2S transmit process half complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Call user Tx half complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxHalfCpltCallback(hi2s);
#else
HAL_I2S_TxHalfCpltCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
* @brief DMA I2S receive process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* if DMA is configured in DMA_NORMAL Mode */
if (hdma->Init.Mode == DMA_NORMAL)
{
/* Disable Rx DMA Request */
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
hi2s->RxXferCount = 0U;
hi2s->State = HAL_I2S_STATE_READY;
}
/* Call user Rx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->RxCpltCallback(hi2s);
#else
HAL_I2S_RxCpltCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
* @brief DMA I2S receive process half complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Call user Rx half complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->RxHalfCpltCallback(hi2s);
#else
HAL_I2S_RxHalfCpltCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
* @brief DMA I2S communication error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMAError(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Disable Rx and Tx DMA Request */
CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
hi2s->TxXferCount = 0U;
hi2s->RxXferCount = 0U;
hi2s->State = HAL_I2S_STATE_READY;
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
/* Call user error callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->ErrorCallback(hi2s);
#else
HAL_I2S_ErrorCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
{
/* Transmit data */
hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
hi2s->pTxBuffPtr++;
hi2s->TxXferCount--;
if (hi2s->TxXferCount == 0U)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
hi2s->State = HAL_I2S_STATE_READY;
/* Call user Tx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxCpltCallback(hi2s);
#else
HAL_I2S_TxCpltCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
{
/* Receive data */
(*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
hi2s->pRxBuffPtr++;
hi2s->RxXferCount--;
if (hi2s->RxXferCount == 0U)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
hi2s->State = HAL_I2S_STATE_READY;
/* Call user Rx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->RxCpltCallback(hi2s);
#else
HAL_I2S_RxCpltCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
/**
* @brief This function handles I2S Communication Timeout.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param Flag Flag checked
* @param State Value of the flag expected
* @param Timeout Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
uint32_t Timeout)
{
uint32_t tickstart;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until flag is set to status*/
while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
{
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* SPI_I2S_SUPPORT */
#endif /* HAL_I2S_MODULE_ENABLED */

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@@ -0,0 +1,2666 @@
/**
******************************************************************************
* @file stm32f1xx_hal_irda.c
* @author MCD Application Team
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The IRDA HAL driver can be used as follows:
(#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
(#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
(##) Enable the USARTx interface clock.
(##) IRDA pins configuration:
(+++) Enable the clock for the IRDA GPIOs.
(+++) Configure IRDA pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
and HAL_IRDA_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
(##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
and HAL_IRDA_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(+++) Configure the IRDAx interrupt priority and enable the NVIC USART IRQ handle
(used for last byte sending completion detection in DMA non circular mode)
(#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
and Mode(Receiver/Transmitter) in the hirda Init structure.
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_IRDA_MspInit() API.
-@@- The specific IRDA interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
(#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
(+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
(+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
*** Interrupt mode IO operation ***
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
(+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
(+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
(+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_IRDA_ErrorCallback
*** DMA mode IO operation ***
=============================
[..]
(+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
(+) At transmission end of half transfer HAL_IRDA_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback
(+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
(+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
(+) At reception end of half transfer HAL_IRDA_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback
(+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
(+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_IRDA_ErrorCallback
(+) Pause the DMA Transfer using HAL_IRDA_DMAPause()
(+) Resume the DMA Transfer using HAL_IRDA_DMAResume()
(+) Stop the DMA Transfer using HAL_IRDA_DMAStop()
*** IRDA HAL driver macros list ***
===================================
[..]
Below the list of most used macros in IRDA HAL driver.
(+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
(+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
(+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
(+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
(+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
(+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
(+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not
[..]
(@) You can refer to the IRDA HAL driver header file for more useful macros
##### Callback registration #####
==================================
[..]
The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function HAL_IRDA_RegisterCallback() to register a user callback.
Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
(+) AbortCpltCallback : Abort Complete Callback.
(+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
(+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
(+) MspInitCallback : IRDA MspInit.
(+) MspDeInitCallback : IRDA MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
(+) AbortCpltCallback : Abort Complete Callback.
(+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
(+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
(+) MspInitCallback : IRDA MspInit.
(+) MspDeInitCallback : IRDA MspDeInit.
[..]
By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
or HAL_IRDA_Init() function.
[..]
When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
[..]
(@) Additional remark: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
the possible IRDA frame formats are as listed in the following table:
+-------------------------------------------------------------+
| M bit | PCE bit | IRDA frame |
|---------------------|---------------------------------------|
| 0 | 0 | | SB | 8 bit data | 1 STB | |
|---------|-----------|---------------------------------------|
| 0 | 1 | | SB | 7 bit data | PB | 1 STB | |
|---------|-----------|---------------------------------------|
| 1 | 0 | | SB | 9 bit data | 1 STB | |
|---------|-----------|---------------------------------------|
| 1 | 1 | | SB | 8 bit data | PB | 1 STB | |
+-------------------------------------------------------------+
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup IRDA IRDA
* @brief HAL IRDA module driver
* @{
*/
#ifdef HAL_IRDA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup IRDA_Private_Functions
* @{
*/
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IRDA_Exported_Functions IrDA Exported Functions
* @{
*/
/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
in asynchronous IrDA mode.
(+) For the asynchronous mode only these parameters can be configured:
(++) BaudRate
(++) WordLength
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
please refer to Reference manual for possible IRDA frame formats.
(++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and
reception (IrDA is a half duplex protocol).
(++) Mode: Receiver/transmitter modes
(++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
[..]
The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
are available in reference manual).
@endverbatim
* @{
*/
/**
* @brief Initializes the IRDA mode according to the specified
* parameters in the IRDA_InitTypeDef and create the associated handle.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
if (hirda == NULL)
{
return HAL_ERROR;
}
/* Check the IRDA instance parameters */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
/* Check the IRDA mode parameter in the IRDA handle */
assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
if (hirda->gState == HAL_IRDA_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hirda->Lock = HAL_UNLOCKED;
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
IRDA_InitCallbacksToDefault(hirda);
if (hirda->MspInitCallback == NULL)
{
hirda->MspInitCallback = HAL_IRDA_MspInit;
}
/* Init the low level hardware */
hirda->MspInitCallback(hirda);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_IRDA_MspInit(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
hirda->gState = HAL_IRDA_STATE_BUSY;
/* Disable the IRDA peripheral */
__HAL_IRDA_DISABLE(hirda);
/* Set the IRDA communication parameters */
IRDA_SetConfig(hirda);
/* In IrDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.*/
CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN));
CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* Enable the IRDA peripheral */
__HAL_IRDA_ENABLE(hirda);
/* Set the prescaler */
MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
/* Configure the IrDA mode */
MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
/* Enable the IrDA mode by setting the IREN bit in the CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
/* Initialize the IRDA state*/
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the IRDA peripheral
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
if (hirda == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
hirda->gState = HAL_IRDA_STATE_BUSY;
/* Disable the Peripheral */
__HAL_IRDA_DISABLE(hirda);
/* DeInit the low level hardware */
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
if (hirda->MspDeInitCallback == NULL)
{
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
}
/* DeInit the low level hardware */
hirda->MspDeInitCallback(hirda);
#else
HAL_IRDA_MspDeInit(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_RESET;
hirda->RxState = HAL_IRDA_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
/**
* @brief IRDA MSP Init.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IRDA_MspInit can be implemented in the user file
*/
}
/**
* @brief IRDA MSP DeInit.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IRDA_MspDeInit can be implemented in the user file
*/
}
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User IRDA Callback
* To be used instead of the weak predefined callback
* @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
* to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
* @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
* @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
* @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
* @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
* @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
* @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
* @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hirda->gState == HAL_IRDA_STATE_READY)
{
switch (CallbackID)
{
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
hirda->TxHalfCpltCallback = pCallback;
break;
case HAL_IRDA_TX_COMPLETE_CB_ID :
hirda->TxCpltCallback = pCallback;
break;
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
hirda->RxHalfCpltCallback = pCallback;
break;
case HAL_IRDA_RX_COMPLETE_CB_ID :
hirda->RxCpltCallback = pCallback;
break;
case HAL_IRDA_ERROR_CB_ID :
hirda->ErrorCallback = pCallback;
break;
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
hirda->AbortCpltCallback = pCallback;
break;
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
hirda->AbortTransmitCpltCallback = pCallback;
break;
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
hirda->AbortReceiveCpltCallback = pCallback;
break;
case HAL_IRDA_MSPINIT_CB_ID :
hirda->MspInitCallback = pCallback;
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
hirda->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hirda->gState == HAL_IRDA_STATE_RESET)
{
switch (CallbackID)
{
case HAL_IRDA_MSPINIT_CB_ID :
hirda->MspInitCallback = pCallback;
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
hirda->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister an IRDA callback
* IRDA callback is redirected to the weak predefined callback
* @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
* to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
* @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
* @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
* @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
* @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
* @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
* @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
* @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (HAL_IRDA_STATE_READY == hirda->gState)
{
switch (CallbackID)
{
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_IRDA_TX_COMPLETE_CB_ID :
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_IRDA_RX_COMPLETE_CB_ID :
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_IRDA_ERROR_CB_ID :
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
break;
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
break;
case HAL_IRDA_MSPINIT_CB_ID :
hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_IRDA_STATE_RESET == hirda->gState)
{
switch (CallbackID)
{
case HAL_IRDA_MSPINIT_CB_ID :
hirda->MspInitCallback = HAL_IRDA_MspInit;
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
break;
default :
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
* @brief IRDA Transmit and Receive functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to manage the IRDA data transfers.
IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
(#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) Non-Blocking mode: The communication is performed using Interrupts
or DMA, these API's return the HAL status.
The end of the data processing will be indicated through the
dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
will be executed respectively at the end of the Transmit or Receive process
The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
(++) HAL_IRDA_Transmit()
(++) HAL_IRDA_Receive()
(#) Non Blocking mode APIs with Interrupt are :
(++) HAL_IRDA_Transmit_IT()
(++) HAL_IRDA_Receive_IT()
(++) HAL_IRDA_IRQHandler()
(#) Non Blocking mode functions with DMA are :
(++) HAL_IRDA_Transmit_DMA()
(++) HAL_IRDA_Receive_DMA()
(++) HAL_IRDA_DMAPause()
(++) HAL_IRDA_DMAResume()
(++) HAL_IRDA_DMAStop()
(#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
(++) HAL_IRDA_TxHalfCpltCallback()
(++) HAL_IRDA_TxCpltCallback()
(++) HAL_IRDA_RxHalfCpltCallback()
(++) HAL_IRDA_RxCpltCallback()
(++) HAL_IRDA_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(+) HAL_IRDA_Abort()
(+) HAL_IRDA_AbortTransmit()
(+) HAL_IRDA_AbortReceive()
(+) HAL_IRDA_Abort_IT()
(+) HAL_IRDA_AbortTransmit_IT()
(+) HAL_IRDA_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
(+) HAL_IRDA_AbortCpltCallback()
(+) HAL_IRDA_AbortTransmitCpltCallback()
(+) HAL_IRDA_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
If user wants to abort it, Abort services should be called by user.
(+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
*/
/**
* @brief Sends an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
const uint16_t *tmp;
uint32_t tickstart = 0U;
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
while (hirda->TxXferCount > 0U)
{
hirda->TxXferCount--;
if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
tmp = (const uint16_t *) pData;
hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
pData += 2U;
}
else
{
pData += 1U;
}
}
else
{
if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
}
}
if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* At end of Tx process, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t *tmp;
uint32_t tickstart = 0U;
/* Check that a Rx process is not already ongoing */
if (hirda->RxState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
/* Check the remain data to be received */
while (hirda->RxXferCount > 0U)
{
hirda->RxXferCount--;
if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
tmp = (uint16_t *) pData ;
if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
*tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
pData += 2U;
}
else
{
*tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
pData += 1U;
}
}
else
{
if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
*pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
}
else
{
*pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
}
}
}
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send an amount of data in non blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->pTxBuffPtr = pData;
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the IRDA Transmit Data Register Empty Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in non blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
if (hirda->RxState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
/* Enable the IRDA Parity Error and Data Register Not Empty Interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
else
{
/* Enable the IRDA Data Register Not Empty Interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
}
/* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
const uint32_t *tmp;
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->pTxBuffPtr = pData;
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Set the IRDA DMA transfer complete callback */
hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
/* Set the IRDA DMA half transfer complete callback */
hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
/* Set the DMA error callback */
hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
/* Set the DMA abort callback */
hirda->hdmatx->XferAbortCallback = NULL;
/* Enable the IRDA transmit DMA channel */
tmp = (const uint32_t *)&pData;
HAL_DMA_Start_IT(hirda->hdmatx, *(const uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receives an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
/* Check that a Rx process is not already ongoing */
if (hirda->RxState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Set the IRDA DMA transfer complete callback */
hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
/* Set the IRDA DMA half transfer complete callback */
hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
/* Set the DMA error callback */
hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
/* Set the DMA abort callback */
hirda->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
tmp = (uint32_t *)&pData;
HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t *)tmp, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
/* Enable the IRDA Parity Error Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
/* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Pauses the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
{
uint32_t dmarequest = 0x00U;
/* Process Locked */
__HAL_LOCK(hirda);
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
{
/* Disable the IRDA DMA Tx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
/**
* @brief Resumes the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
{
/* Process Locked */
__HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
/* Enable the IRDA DMA Tx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
/* Clear the Overrun flag before resuming the Rx transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the IRDA DMA Rx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
/**
* @brief Stops the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
{
uint32_t dmarequest = 0x00U;
/* The Lock is not implemented on this API to allow the user application
to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
*/
/* Stop IRDA DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel */
if (hirda->hdmatx != NULL)
{
HAL_DMA_Abort(hirda->hdmatx);
}
IRDA_EndTxTransfer(hirda);
}
/* Stop IRDA DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel */
if (hirda->hdmarx != NULL)
{
HAL_DMA_Abort(hirda->hdmarx);
}
IRDA_EndRxTransfer(hirda);
}
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (blocking mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(hirda->hdmatx);
}
}
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(hirda->hdmarx);
}
}
/* Reset Tx and Rx transfer counters */
hirda->TxXferCount = 0x00U;
hirda->RxXferCount = 0x00U;
/* Reset ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Restore hirda->RxState and hirda->gState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
hirda->gState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(hirda->hdmatx);
}
}
/* Reset Tx transfer counter */
hirda->TxXferCount = 0x00U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (blocking mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(hirda->hdmarx);
}
}
/* Reset Rx transfer counter */
hirda->RxXferCount = 0x00U;
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (Interrupt mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
{
uint32_t AbortCplt = 0x01U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if (hirda->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
Otherwise, set it to NULL */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
}
else
{
hirda->hdmatx->XferAbortCallback = NULL;
}
}
/* DMA Rx Handle is valid */
if (hirda->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
Otherwise, set it to NULL */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
}
else
{
hirda->hdmarx->XferAbortCallback = NULL;
}
}
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at IRDA level */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
if (hirda->hdmatx != NULL)
{
/* IRDA Tx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
hirda->hdmatx->XferAbortCallback = NULL;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
if (hirda->hdmarx != NULL)
{
/* IRDA Rx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
hirda->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if (AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
hirda->TxXferCount = 0x00U;
hirda->RxXferCount = 0x00U;
/* Reset ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort complete callback */
hirda->AbortCpltCallback(hirda);
#else
/* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
/* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
}
}
else
{
/* Reset Tx transfer counter */
hirda->TxXferCount = 0x00U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Transmit Complete Callback */
hirda->AbortTransmitCpltCallback(hirda);
#else
/* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Reset Tx transfer counter */
hirda->TxXferCount = 0x00U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Transmit Complete Callback */
hirda->AbortTransmitCpltCallback(hirda);
#else
/* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param hirda IRDA handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
}
}
else
{
/* Reset Rx transfer counter */
hirda->RxXferCount = 0x00U;
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
hirda->AbortReceiveCpltCallback(hirda);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Reset Rx transfer counter */
hirda->RxXferCount = 0x00U;
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
hirda->AbortReceiveCpltCallback(hirda);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
* @brief This function handles IRDA interrupt request.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
{
uint32_t isrflags = READ_REG(hirda->Instance->SR);
uint32_t cr1its = READ_REG(hirda->Instance->CR1);
uint32_t cr3its = READ_REG(hirda->Instance->CR3);
uint32_t errorflags = 0x00U;
uint32_t dmarequest = 0x00U;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
if (errorflags == RESET)
{
/* IRDA in mode Receiver -----------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
IRDA_Receive_IT(hirda);
return;
}
}
/* If some errors occur */
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
{
/* IRDA parity error interrupt occurred -------------------------------*/
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
{
hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
}
/* IRDA noise error interrupt occurred --------------------------------*/
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
}
/* IRDA frame error interrupt occurred --------------------------------*/
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
}
/* IRDA Over-Run interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
{
hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
}
/* Call IRDA Error Call back function if need be -----------------------*/
if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
{
/* IRDA in mode Receiver ---------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
IRDA_Receive_IT(hirda);
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
{
/* Blocking error : transfer is aborted
Set the IRDA state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
IRDA_EndRxTransfer(hirda);
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel */
if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
}
}
else
{
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
}
}
return;
} /* End if some error occurs */
/* IRDA in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
IRDA_Transmit_IT(hirda);
return;
}
/* IRDA in mode Transmitter end --------------------------------------------*/
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
IRDA_EndTransmit_IT(hirda);
return;
}
}
/**
* @brief Tx Transfer complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_TxCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Tx Half Transfer completed callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Rx Transfer complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_RxCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Rx Half Transfer complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA error callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_ErrorCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA Abort Complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA Abort Transmit Complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA Abort Receive Complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief IRDA State and Errors functions
*
@verbatim
==============================================================================
##### Peripheral State and Errors functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to return the State of IrDA
communication process and also return Peripheral Errors occurred during communication process
(+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
(+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
*/
/**
* @brief Return the IRDA state.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
{
uint32_t temp1 = 0x00U, temp2 = 0x00U;
temp1 = hirda->gState;
temp2 = hirda->RxState;
return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the IRDA error code
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA.
* @retval IRDA Error Code
*/
uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
{
return hirda->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup IRDA_Private_Functions IRDA Private Functions
* @{
*/
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief Initialize the callbacks to their default values.
* @param hirda IRDA handle.
* @retval none
*/
void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
{
/* Init the IRDA Callback settings */
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @brief DMA IRDA transmit process complete callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* DMA Normal mode */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
hirda->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the IRDA CR3 register */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Enable the IRDA Transmit Complete Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
}
/* DMA Circular mode */
else
{
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Tx complete callback */
hirda->TxCpltCallback(hirda);
#else
/* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
/**
* @brief DMA IRDA receive process half complete callback
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Tx Half complete callback */
hirda->TxHalfCpltCallback(hirda);
#else
/* Call legacy weak Tx complete callback */
HAL_IRDA_TxHalfCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA receive process complete callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* DMA Normal mode */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
hirda->RxXferCount = 0U;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the IRDA CR3 register */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
}
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Rx complete callback */
hirda->RxCpltCallback(hirda);
#else
/* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
/**
* @brief DMA IRDA receive process half complete callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/*Call registered Rx Half complete callback*/
hirda->RxHalfCpltCallback(hirda);
#else
/* Call legacy weak Rx Half complete callback */
HAL_IRDA_RxHalfCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA communication error callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA.
* @retval None
*/
static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
{
uint32_t dmarequest = 0x00U;
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Stop IRDA DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
{
hirda->TxXferCount = 0U;
IRDA_EndTxTransfer(hirda);
}
/* Stop IRDA DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
{
hirda->RxXferCount = 0U;
IRDA_EndRxTransfer(hirda);
}
hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief This function handles IRDA Communication Timeout. It waits
* until a flag is no longer in the specified status.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA.
* @param Flag specifies the IRDA flag to check.
* @param Status The actual Flag status (SET or RESET).
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
* @param hirda IRDA handle.
* @retval None
*/
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* At end of Tx process, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
}
/**
* @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
* @param hirda IRDA handle.
* @retval None
*/
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
}
/**
* @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hirda->RxXferCount = 0x00U;
hirda->TxXferCount = 0x00U;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA Tx communication abort callback, when initiated by user
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hirda->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if (hirda->hdmarx != NULL)
{
if (hirda->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hirda->TxXferCount = 0x00U;
hirda->RxXferCount = 0x00U;
/* Reset ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort complete callback */
hirda->AbortCpltCallback(hirda);
#else
/* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA Rx communication abort callback, when initiated by user
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hirda->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if (hirda->hdmatx != NULL)
{
if (hirda->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hirda->TxXferCount = 0x00U;
hirda->RxXferCount = 0x00U;
/* Reset ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort complete callback */
hirda->AbortCpltCallback(hirda);
#else
/* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
* HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
* (This callback is executed at end of DMA Tx Abort procedure following user abort request,
* and leads to user Tx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hirda->TxXferCount = 0x00U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Transmit Complete Callback */
hirda->AbortTransmitCpltCallback(hirda);
#else
/* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
* HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
* (This callback is executed at end of DMA Rx Abort procedure following user abort request,
* and leads to user Rx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hirda->RxXferCount = 0x00U;
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
hirda->AbortReceiveCpltCallback(hirda);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief Send an amount of data in non blocking mode.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
tmp = (const uint16_t *) hirda->pTxBuffPtr;
hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
hirda->pTxBuffPtr += 2U;
}
else
{
hirda->pTxBuffPtr += 1U;
}
}
else
{
hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
}
if (--hirda->TxXferCount == 0U)
{
/* Disable the IRDA Transmit Data Register Empty Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
/* Enable the IRDA Transmit Complete Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Wraps up transmission in non blocking mode.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable the IRDA Transmit Complete Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Tx process is ended, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Tx complete callback */
hirda->TxCpltCallback(hirda);
#else
/* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
return HAL_OK;
}
/**
* @brief Receives an amount of data in non blocking mode.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
{
uint16_t *tmp;
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
tmp = (uint16_t *) hirda->pRxBuffPtr;
if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
*tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
hirda->pRxBuffPtr += 2U;
}
else
{
*tmp = (uint16_t)(uhdata & (uint16_t)0x00FF);
hirda->pRxBuffPtr += 1U;
}
}
else
{
if (hirda->Init.Parity == IRDA_PARITY_NONE)
{
*hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
}
else
{
*hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F);
}
}
if (--hirda->RxXferCount == 0U)
{
/* Disable the IRDA Data Register not empty Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
/* Disable the IRDA Parity Error Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Rx complete callback */
hirda->RxCpltCallback(hirda);
#else
/* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
return HAL_OK;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configures the IRDA peripheral.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
uint32_t pclk;
/* Check the parameters */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
assert_param(IS_IRDA_MODE(hirda->Init.Mode));
assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
/*-------------------------- USART CR2 Configuration ------------------------*/
/* Clear STOP[13:12] bits */
CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
/*-------------------------- USART CR1 Configuration -----------------------*/
/* Clear M, PCE, PS, TE and RE bits */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE));
/* Configure the USART Word Length, Parity and mode:
Set the M bits according to hirda->Init.WordLength value
Set PCE and PS bits according to hirda->Init.Parity value
Set TE and RE bits according to hirda->Init.Mode value */
/* Write to USART CR1 */
SET_BIT(hirda->Instance->CR1, (hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode));
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Clear CTSE and RTSE bits */
CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
/*-------------------------- USART BRR Configuration -----------------------*/
if(hirda->Instance == USART1)
{
pclk = HAL_RCC_GetPCLK2Freq();
SET_BIT(hirda->Instance->BRR, IRDA_BRR(pclk, hirda->Init.BaudRate));
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
SET_BIT(hirda->Instance->BRR, IRDA_BRR(pclk, hirda->Init.BaudRate));
}
}
/**
* @}
*/
#endif /* HAL_IRDA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32f1xx_hal_iwdg.c
* @author MCD Application Team
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and Start functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### IWDG Generic features #####
==============================================================================
[..]
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
active even if the main clock fails.
(+) Once the IWDG is started, the LSI is forced ON and both cannot be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded into the counter and the watchdog reset
is prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode: When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI clock frequency dispersion.
STM32F1xx devices provide the capability to measure the LSI clock
frequency (LSI clock is internally connected to TIM5 CH4 input capture).
The measured value can be used to have an IWDG timeout with an
acceptable accuracy.
[..] Default timeout value (necessary for IWDG_SR status register update):
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
This frequency being subject to variations as mentioned above, the
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
below) may become too short or too long.
In such cases, this default timeout value can be tuned by redefining
the constant LSI_VALUE at user-application level (based, for instance,
on the measured LSI clock frequency as explained above).
##### How to use this driver #####
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts counting down.
(++) Enable write access to configuration registers:
IWDG_PR and IWDG_RLR.
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(++) Wait for status flags to be reset.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
*** IWDG HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IWDG HAL driver:
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
the reload register
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_IWDG_MODULE_ENABLED
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register needs up to 5 LSI clock periods divided by the clock
prescaler to be updated. The number of LSI clock periods is upper-rounded to
6 for the timeout value calculation.
The timeout value is calculated using the highest prescaler (256) and
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
The timeout value is multiplied by 1000 to be converted in milliseconds.
LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \
((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IWDG_Exported_Functions
* @{
*/
/** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Start functions.
*
@verbatim
===============================================================================
##### Initialization and Start functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters in the
IWDG_InitTypeDef of associated handle.
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
is reloaded in order to exit function with correct time base.
@endverbatim
* @{
*/
/**
* @brief Initialize the IWDG according to the specified parameters in the
* IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart;
/* Check the IWDG handle allocation */
if (hiwdg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
/* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR and IWDG_RLR registers by writing
0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the Prescaler & Reload values to work with */
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
hiwdg->Instance->RLR = hiwdg->Init.Reload;
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
{
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
{
return HAL_TIMEOUT;
}
}
}
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Refresh the IWDG.
@endverbatim
* @{
*/
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_IWDG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32f1xx_hal_mmc.c
* @author MCD Application Team
* @brief MMC card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + MMC card Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver implements a high level communication layer for read and write from/to
this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
the user in HAL_MMC_MspInit() function (MSP layer).
Basically, the MSP layer configuration should be the same as we provide in the
examples.
You can easily tailor this configuration according to hardware resources.
[..]
This driver is a generic layered driver for SDMMC memories which uses the HAL
SDMMC driver functions to interface with MMC and eMMC cards devices.
It is used as follows:
(#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
(##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
(##) SDMMC pins configuration for MMC card
(+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA()
and HAL_MMC_WriteBlocks_DMA() APIs).
(+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
(+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDMMC and DMA interrupt priorities using function HAL_NVIC_SetPriority();
DMA priority is superior to SDMMC's priority
(+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
(+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
and __HAL_MMC_DISABLE_IT() inside the communication process.
(+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
and __HAL_MMC_CLEAR_IT()
(##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
and HAL_MMC_WriteBlocks_IT() APIs).
(+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
(+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
and __HAL_MMC_DISABLE_IT() inside the communication process.
(+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
and __HAL_MMC_CLEAR_IT()
(#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
*** MMC Card Initialization and configuration ***
================================================
[..]
To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
(#) Initialize the SDMMC peripheral interface with default configuration.
The initialization process is done at 400KHz. You can change or adapt
this frequency by adjusting the "ClockDiv" field.
The MMC Card frequency (SDMMC_CK) is computed as follows:
SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
In initialization mode and according to the MMC Card standard,
make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
This phase of initialization is done through SDMMC_Init() and
SDMMC_PowerState_ON() SDMMC low level APIs.
(#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
This phase allows the card initialization and identification
and check the MMC Card type (Standard Capacity or High Capacity)
The initialization flow is compatible with MMC standard.
This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
of plug-off plug-in.
(#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
frequency is set to 24MHz. You can change or adapt this frequency by adjusting
the "ClockDiv" field.
In transfer mode and according to the MMC Card standard, make sure that the
SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
To be able to use a frequency higher than 24MHz, you should use the SDMMC
peripheral in bypass mode. Refer to the corresponding reference manual
for more details.
(#) Select the corresponding MMC Card according to the address read with the step 2.
(#) Configure the MMC Card in wide bus mode: 4-bits data.
*** MMC Card Read operation ***
==============================
[..]
(+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
(+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the DMA transfer process through the MMC Rx interrupt event.
(+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Rx interrupt event.
*** MMC Card Write operation ***
===============================
[..]
(+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
(+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
This function support only 512-bytes block length (the block size should be
chosen as 512 byte).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the DMA transfer process through the MMC Tx interrupt event.
(+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Tx interrupt event.
*** MMC card information ***
===========================
[..]
(+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
It returns useful information about the MMC card such as block size, card type,
block number ...
*** MMC card CSD register ***
============================
[..]
(+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
Some of the CSD parameters are useful for card initialization and identification.
*** MMC card CID register ***
============================
[..]
(+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
Some of the CID parameters are useful for card initialization and identification.
*** MMC HAL driver macros list ***
==================================
[..]
Below the list of most used macros in MMC HAL driver.
(+) __HAL_MMC_ENABLE : Enable the MMC device
(+) __HAL_MMC_DISABLE : Disable the MMC device
(+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer
(+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer
(+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
(+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
(+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
(+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
[..]
(@) You can refer to the MMC HAL driver header file for more useful macros
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_MMC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) MspInitCallback : MMC MspInit.
(+) MspDeInitCallback : MMC MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) MspInitCallback : MMC MspInit.
(+) MspDeInitCallback : MMC MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_MMC_Init
and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit
or HAL_MMC_Init function.
When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup MMC MMC
* @brief MMC HAL module driver
* @{
*/
#ifdef HAL_MMC_MODULE_ENABLED
#if defined(SDIO)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup MMC_Private_Defines
* @{
*/
#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 201
#define MMC_EXT_CSD_PWR_CL_52_INDEX 200
#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238
#define MMC_EXT_CSD_PWR_CL_26_POS 8
#define MMC_EXT_CSD_PWR_CL_52_POS 0
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16
#else
#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 203
#define MMC_EXT_CSD_PWR_CL_52_INDEX 202
#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239
#define MMC_EXT_CSD_PWR_CL_26_POS 24
#define MMC_EXT_CSD_PWR_CL_52_POS 16
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24
#endif
/* Frequencies used in the driver for clock divider calculation */
#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MMC_Private_Functions MMC Private Functions
* @{
*/
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout);
static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc);
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void MMC_DMAError(DMA_HandleTypeDef *hdma);
static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma);
static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma);
static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup MMC_Exported_Functions
* @{
*/
/** @addtogroup MMC_Exported_Functions_Group1
* @brief Initialization and de-initialization functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize the MMC
card device to be ready for use.
@endverbatim
* @{
*/
/**
* @brief Initializes the MMC according to the specified parameters in the
MMC_HandleTypeDef and create the associated handle.
* @param hmmc: Pointer to the MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
{
/* Check the MMC handle allocation */
if(hmmc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance));
assert_param(IS_SDIO_CLOCK_EDGE(hmmc->Init.ClockEdge));
assert_param(IS_SDIO_CLOCK_BYPASS(hmmc->Init.ClockBypass));
assert_param(IS_SDIO_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
assert_param(IS_SDIO_BUS_WIDE(hmmc->Init.BusWide));
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
assert_param(IS_SDIO_CLKDIV(hmmc->Init.ClockDiv));
if(hmmc->State == HAL_MMC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hmmc->Lock = HAL_UNLOCKED;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_MMC_STATE_RESET only */
hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
if(hmmc->MspInitCallback == NULL)
{
hmmc->MspInitCallback = HAL_MMC_MspInit;
}
/* Init the low level hardware */
hmmc->MspInitCallback(hmmc);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_MMC_MspInit(hmmc);
#endif
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize the Card parameters */
if(HAL_MMC_InitCard(hmmc) == HAL_ERROR)
{
return HAL_ERROR;
}
/* Initialize the error code */
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
/* Initialize the MMC operation */
hmmc->Context = MMC_CONTEXT_NONE;
/* Initialize the MMC state */
hmmc->State = HAL_MMC_STATE_READY;
/* Configure bus width */
if (hmmc->Init.BusWide != SDIO_BUS_WIDE_1B)
{
if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK)
{
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Initializes the MMC Card.
* @param hmmc: Pointer to MMC handle
* @note This function initializes the MMC card. It could be used when a card
re-initialization is needed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate;
MMC_InitTypeDef Init;
HAL_StatusTypeDef status;
/* Default SDIO peripheral configuration for MMC card initialization */
Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
Init.BusWide = SDIO_BUS_WIDE_1B;
Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
Init.ClockDiv = SDIO_INIT_CLK_DIV;
/* Initialize SDIO peripheral interface with default configuration */
status = SDIO_Init(hmmc->Instance, Init);
if(status == HAL_ERROR)
{
return HAL_ERROR;
}
/* Disable SDIO Clock */
__HAL_MMC_DISABLE(hmmc);
/* Set Power State to ON */
status = SDIO_PowerState_ON(hmmc->Instance);
if(status == HAL_ERROR)
{
return HAL_ERROR;
}
/* Enable MMC Clock */
__HAL_MMC_ENABLE(hmmc);
/* Required power up waiting time before starting the MMC initialization sequence */
HAL_Delay(2);
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
/* Card initialization */
errorstate = MMC_InitCard(hmmc);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief De-Initializes the MMC card.
* @param hmmc: Pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
{
/* Check the MMC handle allocation */
if(hmmc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance));
hmmc->State = HAL_MMC_STATE_BUSY;
/* Set MMC power state to off */
MMC_PowerOFF(hmmc);
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
if(hmmc->MspDeInitCallback == NULL)
{
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
}
/* DeInit the low level hardware */
hmmc->MspDeInitCallback(hmmc);
#else
/* De-Initialize the MSP layer */
HAL_MMC_MspDeInit(hmmc);
#endif
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initializes the MMC MSP.
* @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MMC_MspInit could be implemented in the user file
*/
}
/**
* @brief De-Initialize MMC MSP.
* @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MMC_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @addtogroup MMC_Exported_Functions_Group2
* @brief Data transfer functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to manage the data
transfer from/to MMC card.
@endverbatim
* @{
*/
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @param hmmc: Pointer to MMC handle
* @param pData: pointer to the buffer that will contain the received data
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of MMC blocks to read
* @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count, data, dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hmmc->Instance, &config);
/* Read block(s) in polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Poll on SDIO flags */
dataremaining = config.DataLength;
while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
{
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U))
{
/* Read data from SDIO Rx FIFO */
for(count = 0U; count < 8U; count++)
{
data = SDIO_ReadFIFO(hmmc->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
tempbuff++;
dataremaining--;
}
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
hmmc->State= HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
/* Send stop transmission command in case of multiblock read */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Get error state */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Empty FIFO if there is still any data */
while ((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U))
{
data = SDIO_ReadFIFO(hmmc->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
tempbuff++;
dataremaining--;
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
hmmc->State= HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
return HAL_OK;
}
else
{
hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
return HAL_ERROR;
}
}
/**
* @brief Allows to write block(s) to a specified address in a card. The Data
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @param hmmc: Pointer to MMC handle
* @param pData: pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of MMC blocks to write
* @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count, data, dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hmmc->Instance, &config);
/* Write block(s) in polling mode */
dataremaining = config.DataLength;
while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
{
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U))
{
/* Write data to SDIO Tx FIFO */
for(count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tempbuff);
tempbuff++;
dataremaining--;
data |= ((uint32_t)(*tempbuff) << 8U);
tempbuff++;
dataremaining--;
data |= ((uint32_t)(*tempbuff) << 16U);
tempbuff++;
dataremaining--;
data |= ((uint32_t)(*tempbuff) << 24U);
tempbuff++;
dataremaining--;
(void)SDIO_WriteFIFO(hmmc->Instance, &data);
}
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
/* Send stop transmission command in case of multiblock write */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Get error state */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
return HAL_OK;
}
else
{
hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
return HAL_ERROR;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @note You could also check the IT transfer process through the MMC Rx
* interrupt event.
* @param hmmc: Pointer to MMC handle
* @param pData: Pointer to the buffer that will contain the received data
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
hmmc->pRxBuffPtr = pData;
hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hmmc->Instance, &config);
/* Read Blocks in IT mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Writes block(s) to a specified address in a card. The Data transfer
* is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @note You could also check the IT transfer process through the MMC Tx
* interrupt event.
* @param hmmc: Pointer to MMC handle
* @param pData: Pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
hmmc->pTxBuffPtr = pData;
hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
/* Enable transfer interrupts */
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hmmc->Instance, &config);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @note You could also check the DMA transfer process through the MMC Rx
* interrupt event.
* @param hmmc: Pointer MMC handle
* @param pData: Pointer to the buffer that will contain the received data
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
/* Set the DMA transfer complete callback */
hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt;
/* Set the DMA error callback */
hmmc->hdmarx->XferErrorCallback = MMC_DMAError;
/* Set the DMA Abort callback */
hmmc->hdmarx->XferAbortCallback = NULL;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Force DMA Direction */
hmmc->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
MODIFY_REG(hmmc->hdmarx->Instance->CCR, DMA_CCR_DIR, hmmc->hdmarx->Init.Direction);
/* Enable the DMA Channel */
if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
{
__HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode = HAL_MMC_ERROR_DMA;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else
{
/* Enable MMC DMA transfer */
__HAL_MMC_DMA_ENABLE(hmmc);
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hmmc->Instance, &config);
/* Read Blocks in DMA mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
__HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
hmmc->ErrorCode = errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Writes block(s) to a specified address in a card. The Data transfer
* is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @note You could also check the DMA transfer process through the MMC Tx
* interrupt event.
* @param hmmc: Pointer to MMC handle
* @param pData: Pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
/* Enable MMC Error interrupts */
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
/* Set the DMA transfer complete callback */
hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt;
/* Set the DMA error callback */
hmmc->hdmatx->XferErrorCallback = MMC_DMAError;
/* Set the DMA Abort callback */
hmmc->hdmatx->XferAbortCallback = NULL;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
__HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Enable SDIO DMA transfer */
__HAL_MMC_DMA_ENABLE(hmmc);
/* Force DMA Direction */
hmmc->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
MODIFY_REG(hmmc->hdmatx->Instance->CCR, DMA_CCR_DIR, hmmc->hdmatx->Init.Direction);
/* Enable the DMA Channel */
if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK)
{
__HAL_MMC_DISABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND));
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else
{
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hmmc->Instance, &config);
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Erases the specified memory area of the given MMC card.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @param hmmc: Pointer to MMC handle
* @param BlockStartAdd: Start Block address
* @param BlockEndAdd: End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
uint32_t errorstate;
uint32_t start_add = BlockStartAdd;
uint32_t end_add = BlockEndAdd;
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if(end_add < start_add)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if(end_add > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check if the card command class supports erase command */
if(((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE) == 0U)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
if((SDIO_GetResponse(hmmc->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
start_add *= 512U;
end_add *= 512U;
}
/* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
hmmc->State = HAL_MMC_STATE_READY;
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief This function handles MMC card interrupt request.
* @param hmmc: Pointer to MMC handle
* @retval None
*/
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate;
uint32_t context = hmmc->Context;
/* Check for SDIO interrupt flags */
if((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Read_IT(hmmc);
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_DATAEND);
__HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
hmmc->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN);
if((context & MMC_CONTEXT_DMA) != 0U)
{
if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
}
if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
{
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the MMC DCTRL register */
hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
hmmc->State = HAL_MMC_STATE_READY;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
#else
HAL_MMC_TxCpltCallback(hmmc);
#endif
}
}
else if((context & MMC_CONTEXT_IT) != 0U)
{
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
#endif
}
else
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
#else
HAL_MMC_TxCpltCallback(hmmc);
#endif
}
}
else
{
/* Nothing to do */
}
}
else if((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Write_IT(hmmc);
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
}
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
}
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
}
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
}
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR);
/* Disable all interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
if((context & MMC_CONTEXT_IT) != 0U)
{
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
else if((context & MMC_CONTEXT_DMA) != 0U)
{
/* Abort the MMC DMA Streams */
if(hmmc->hdmatx != NULL)
{
/* Set the DMA Tx abort callback */
hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
/* Abort DMA in IT mode */
if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
{
MMC_DMATxAbort(hmmc->hdmatx);
}
}
else if(hmmc->hdmarx != NULL)
{
/* Set the DMA Rx abort callback */
hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
/* Abort DMA in IT mode */
if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
{
MMC_DMARxAbort(hmmc->hdmarx);
}
}
else
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_READY;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->AbortCpltCallback(hmmc);
#else
HAL_MMC_AbortCallback(hmmc);
#endif
}
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
}
/**
* @brief return the MMC state
* @param hmmc: Pointer to mmc handle
* @retval HAL state
*/
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
{
return hmmc->State;
}
/**
* @brief Return the MMC error code
* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval MMC Error Code
*/
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
{
return hmmc->ErrorCode;
}
/**
* @brief Tx Transfer completed callbacks
* @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_TxCpltCallback can be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks
* @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_RxCpltCallback can be implemented in the user file
*/
}
/**
* @brief MMC error callbacks
* @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_ErrorCallback can be implemented in the user file
*/
}
/**
* @brief MMC Abort callbacks
* @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_AbortCallback can be implemented in the user file
*/
}
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User MMC Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hmmc : MMC handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
* @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
* @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
* @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
* @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
* @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hmmc);
if(hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
{
case HAL_MMC_TX_CPLT_CB_ID :
hmmc->TxCpltCallback = pCallback;
break;
case HAL_MMC_RX_CPLT_CB_ID :
hmmc->RxCpltCallback = pCallback;
break;
case HAL_MMC_ERROR_CB_ID :
hmmc->ErrorCallback = pCallback;
break;
case HAL_MMC_ABORT_CB_ID :
hmmc->AbortCpltCallback = pCallback;
break;
case HAL_MMC_MSP_INIT_CB_ID :
hmmc->MspInitCallback = pCallback;
break;
case HAL_MMC_MSP_DEINIT_CB_ID :
hmmc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hmmc->State == HAL_MMC_STATE_RESET)
{
switch (CallbackId)
{
case HAL_MMC_MSP_INIT_CB_ID :
hmmc->MspInitCallback = pCallback;
break;
case HAL_MMC_MSP_DEINIT_CB_ID :
hmmc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hmmc);
return status;
}
/**
* @brief Unregister a User MMC Callback
* MMC Callback is redirected to the weak (surcharged) predefined callback
* @param hmmc : MMC handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
* @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
* @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
* @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
* @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
* @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hmmc);
if(hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
{
case HAL_MMC_TX_CPLT_CB_ID :
hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
break;
case HAL_MMC_RX_CPLT_CB_ID :
hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
break;
case HAL_MMC_ERROR_CB_ID :
hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
break;
case HAL_MMC_ABORT_CB_ID :
hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
break;
case HAL_MMC_MSP_INIT_CB_ID :
hmmc->MspInitCallback = HAL_MMC_MspInit;
break;
case HAL_MMC_MSP_DEINIT_CB_ID :
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
break;
default :
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hmmc->State == HAL_MMC_STATE_RESET)
{
switch (CallbackId)
{
case HAL_MMC_MSP_INIT_CB_ID :
hmmc->MspInitCallback = HAL_MMC_MspInit;
break;
case HAL_MMC_MSP_DEINIT_CB_ID :
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
break;
default :
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hmmc);
return status;
}
#endif
/**
* @}
*/
/** @addtogroup MMC_Exported_Functions_Group3
* @brief management functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the MMC card
operations and get the related information
@endverbatim
* @{
*/
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
* @param hmmc: Pointer to MMC handle
* @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
* contains all CID register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
{
pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U);
pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U);
pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U));
pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU);
pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U);
pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U));
pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U);
pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U);
pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U);
pCID->Reserved2 = 1U;
return HAL_OK;
}
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
* @param hmmc: Pointer to MMC handle
* @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
{
uint32_t block_nbr = 0;
pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U);
pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U);
pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U);
pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU);
pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U);
pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U);
pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U);
pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U);
pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U);
pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U);
pCSD->Reserved2 = 0U; /*!< Reserved */
pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U);
pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U);
pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U);
pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U);
pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
{
return HAL_ERROR;
}
if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
{
hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
hmmc->MmcCard.LogBlockSize = 512U;
}
else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
{
hmmc->MmcCard.BlockNbr = block_nbr;
hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
hmmc->MmcCard.BlockSize = 512U;
hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize;
}
else
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U);
pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU);
pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U);
pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U);
pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
pCSD->Reserved3 = 0;
pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U);
pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U);
pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U);
pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U);
pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U);
pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
pCSD->Reserved4 = 1;
return HAL_OK;
}
/**
* @brief Gets the MMC card info.
* @param hmmc: Pointer to MMC handle
* @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
* will contain the MMC card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
{
pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType);
pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class);
pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd);
pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr);
pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize);
pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
return HAL_OK;
}
/**
* @brief Returns information the information of the card which are stored on
* the Extended CSD register.
* @param hmmc Pointer to MMC handle
* @param pExtCSD Pointer to a memory area (512 bytes) that contains all
* Extended CSD register parameters
* @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count;
uint32_t *tmp_buf;
if(NULL == pExtCSD)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
/* Initiaize the destination pointer */
tmp_buf = pExtCSD;
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 512;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hmmc->Instance, &config);
/* Send ExtCSD Read command to Card */
errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Poll on SDMMC flags */
while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
{
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF))
{
/* Read data from SDMMC Rx FIFO */
for(count = 0U; count < 8U; count++)
{
*tmp_buf = SDIO_ReadFIFO(hmmc->Instance);
tmp_buf++;
}
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
hmmc->State= HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
/* Get error state */
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
}
return HAL_OK;
}
/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
* @param hmmc: Pointer to MMC handle
* @param WideMode: Specifies the MMC card wide bus mode
* This parameter can be one of the following values:
* @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
* @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
* @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
{
uint32_t count;
SDIO_InitTypeDef Init;
uint32_t errorstate;
uint32_t response = 0U;
/* Check the parameters */
assert_param(IS_SDIO_BUS_WIDE(WideMode));
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
errorstate = MMC_PwrClassUpdate(hmmc, WideMode);
if(errorstate == HAL_MMC_ERROR_NONE)
{
if(WideMode == SDIO_BUS_WIDE_8B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
}
else if(WideMode == SDIO_BUS_WIDE_4B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
}
else if(WideMode == SDIO_BUS_WIDE_1B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
}
else
{
/* WideMode is not a valid argument*/
errorstate = HAL_MMC_ERROR_PARAM;
}
/* Check for switch error and violation of the trial number of sending CMD 13 */
if(errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
count--;
}while(((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
}
else
{
/* Configure the SDIO peripheral */
Init = hmmc->Init;
Init.BusWide = WideMode;
(void)SDIO_Init(hmmc->Instance, Init);
}
}
else if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else
{
/* Nothing to do */
}
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Gets the current mmc card data state.
* @param hmmc: pointer to MMC handle
* @retval Card state
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
{
uint32_t cardstate;
uint32_t errorstate;
uint32_t resp1 = 0U;
errorstate = MMC_SendStatus(hmmc, &resp1);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
cardstate = ((resp1 >> 9U) & 0x0FU);
return (HAL_MMC_CardStateTypeDef)cardstate;
}
/**
* @brief Abort the current transfer and disable the MMC.
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardStateTypeDef CardState;
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
{
/* Disable the MMC DMA request */
hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
/* Abort the MMC DMA Tx Stream */
if(hmmc->hdmatx != NULL)
{
if(HAL_DMA_Abort(hmmc->hdmatx) != HAL_OK)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
}
}
/* Abort the MMC DMA Rx Stream */
if(hmmc->hdmarx != NULL)
{
if(HAL_DMA_Abort(hmmc->hdmarx) != HAL_OK)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
}
}
}
hmmc->State = HAL_MMC_STATE_READY;
/* Initialize the MMC operation */
hmmc->Context = MMC_CONTEXT_NONE;
CardState = HAL_MMC_GetCardState(hmmc);
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
}
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Abort the current transfer and disable the MMC (IT mode).
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardStateTypeDef CardState;
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
{
/* Disable the MMC DMA request */
hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
/* Abort the MMC DMA Tx Stream */
if(hmmc->hdmatx != NULL)
{
hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
{
hmmc->hdmatx = NULL;
}
}
/* Abort the MMC DMA Rx Stream */
if(hmmc->hdmarx != NULL)
{
hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
{
hmmc->hdmarx = NULL;
}
}
}
/* No transfer ongoing on both DMA channels*/
if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL))
{
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->State = HAL_MMC_STATE_READY;
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
}
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->AbortCpltCallback(hmmc);
#else
HAL_MMC_AbortCallback(hmmc);
#endif
}
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/* Private function ----------------------------------------------------------*/
/** @addtogroup MMC_Private_Functions
* @{
*/
/**
* @brief DMA MMC transmit process complete callback
* @param hdma: DMA handle
* @retval None
*/
static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
/* Enable DATAEND Interrupt */
__HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DATAEND));
}
/**
* @brief DMA MMC receive process complete callback
* @param hdma: DMA handle
* @retval None
*/
static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
uint32_t errorstate;
/* Send stop command in multiblock write */
if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
}
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the MMC DCTRL register */
hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
#endif
}
/**
* @brief DMA MMC communication error callback
* @param hdma: DMA handle
* @retval None
*/
static void MMC_DMAError(DMA_HandleTypeDef *hdma)
{
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
HAL_MMC_CardStateTypeDef CardState;
uint32_t RxErrorCode, TxErrorCode;
RxErrorCode = hmmc->hdmarx->ErrorCode;
TxErrorCode = hmmc->hdmatx->ErrorCode;
if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
{
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
/* Disable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
CardState = HAL_MMC_GetCardState(hmmc);
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
}
hmmc->State= HAL_MMC_STATE_READY;
}
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
/**
* @brief DMA MMC Tx Abort callback
* @param hdma: DMA handle
* @retval None
*/
static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
{
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
HAL_MMC_CardStateTypeDef CardState;
if(hmmc->hdmatx != NULL)
{
hmmc->hdmatx = NULL;
}
/* All DMA channels are aborted */
if(hmmc->hdmarx == NULL)
{
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_READY;
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->AbortCpltCallback(hmmc);
#else
HAL_MMC_AbortCallback(hmmc);
#endif
}
else
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
}
}
}
/**
* @brief DMA MMC Rx Abort callback
* @param hdma: DMA handle
* @retval None
*/
static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
{
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
HAL_MMC_CardStateTypeDef CardState;
if(hmmc->hdmarx != NULL)
{
hmmc->hdmarx = NULL;
}
/* All DMA channels are aborted */
if(hmmc->hdmatx == NULL)
{
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_READY;
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->AbortCpltCallback(hmmc);
#else
HAL_MMC_AbortCallback(hmmc);
#endif
}
else
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
}
}
}
/**
* @brief Initializes the mmc card.
* @param hmmc: Pointer to MMC handle
* @retval MMC Card error state
*/
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardCSDTypeDef CSD;
uint32_t errorstate;
uint16_t mmc_rca = 2U;
MMC_InitTypeDef Init;
/* Check the power State */
if(SDIO_GetPowerState(hmmc->Instance) == 0U)
{
/* Power off */
return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
}
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
else
{
/* Get Card identification number data */
hmmc->CID[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
hmmc->CID[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2);
hmmc->CID[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
hmmc->CID[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
}
/* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */
/* MMC Card publishes its RCA. */
errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca);
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
/* Get the MMC card RCA */
hmmc->MmcCard.RelCardAdd = mmc_rca;
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
else
{
/* Get Card Specific Data */
hmmc->CSD[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
hmmc->CSD[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2);
hmmc->CSD[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
hmmc->CSD[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
}
/* Get the Card Class */
hmmc->MmcCard.Class = (SDIO_GetResponse(hmmc->Instance, SDIO_RESP2) >> 20U);
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
/* Get CSD parameters */
if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK)
{
return hmmc->ErrorCode;
}
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
/* Get Extended CSD parameters */
if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK)
{
return hmmc->ErrorCode;
}
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
/* Configure the SDIO peripheral */
Init = hmmc->Init;
Init.BusWide = SDIO_BUS_WIDE_1B;
(void)SDIO_Init(hmmc->Instance, Init);
/* All cards are initialized */
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores MMC information that will be needed in future
* in the MMC handle.
* @param hmmc: Pointer to MMC handle
* @retval error state
*/
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
{
__IO uint32_t count = 0U;
uint32_t response = 0U, validvoltage = 0U;
uint32_t errorstate;
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
while(validvoltage == 0U)
{
if(count++ == SDMMC_MAX_VOLT_TRIAL)
{
return HAL_MMC_ERROR_INVALID_VOLTRANGE;
}
/* SEND CMD1 APP_CMD with voltage range as argument */
errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
}
/* Get command response */
response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
/* Get operating voltage*/
validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
}
/* When power routine is finished and command returns valid voltage */
if (((response & (0xFF000000U)) >> 24U) == 0xC0U)
{
hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD;
}
else
{
hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD;
}
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Turns the SDIO output signals off.
* @param hmmc: Pointer to MMC handle
* @retval None
*/
static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
{
/* Set Power State to OFF */
(void)SDIO_PowerState_OFF(hmmc->Instance);
}
/**
* @brief Returns the current card's status.
* @param hmmc: Pointer to MMC handle
* @param pCardStatus: pointer to the buffer that will contain the MMC card
* status (Card Status register)
* @retval error state
*/
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
{
uint32_t errorstate;
if(pCardStatus == NULL)
{
return HAL_MMC_ERROR_PARAM;
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
/* Get MMC card status */
*pCardStatus = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Reads extended CSD register to get the sectors number of the device
* @param hmmc: Pointer to MMC handle
* @param pFieldData: Pointer to the read buffer
* @param FieldIndex: Index of the field to be read
* @param Timeout: Specify timeout value
* @retval HAL status
*/
static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count;
uint32_t i = 0;
uint32_t tmp_data;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 512;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hmmc->Instance, &config);
/* Set Block Size for Card */
errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Poll on SDMMC flags */
while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
{
if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF))
{
/* Read data from SDMMC Rx FIFO */
for(count = 0U; count < 8U; count++)
{
tmp_data = SDIO_ReadFIFO(hmmc->Instance);
/* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
/* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
if ((i + count) == ((uint32_t)FieldIndex/4U))
{
*pFieldData = tmp_data;
}
}
i += 8U;
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
hmmc->State= HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
return HAL_OK;
}
/**
* @brief Wrap up reading in non-blocking mode.
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval None
*/
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count, data, dataremaining;
uint8_t* tmp;
tmp = hmmc->pRxBuffPtr;
dataremaining = hmmc->RxXferSize;
if (dataremaining > 0U)
{
/* Read data from SDIO Rx FIFO */
for(count = 0U; count < 8U; count++)
{
data = SDIO_ReadFIFO(hmmc->Instance);
*tmp = (uint8_t)(data & 0xFFU);
tmp++;
dataremaining--;
*tmp = (uint8_t)((data >> 8U) & 0xFFU);
tmp++;
dataremaining--;
*tmp = (uint8_t)((data >> 16U) & 0xFFU);
tmp++;
dataremaining--;
*tmp = (uint8_t)((data >> 24U) & 0xFFU);
tmp++;
dataremaining--;
}
hmmc->pRxBuffPtr = tmp;
hmmc->RxXferSize = dataremaining;
}
}
/**
* @brief Wrap up writing in non-blocking mode.
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval None
*/
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count, data, dataremaining;
uint8_t* tmp;
tmp = hmmc->pTxBuffPtr;
dataremaining = hmmc->TxXferSize;
if (dataremaining > 0U)
{
/* Write data to SDIO Tx FIFO */
for(count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tmp);
tmp++;
dataremaining--;
data |= ((uint32_t)(*tmp) << 8U);
tmp++;
dataremaining--;
data |= ((uint32_t)(*tmp) << 16U);
tmp++;
dataremaining--;
data |= ((uint32_t)(*tmp) << 24U);
tmp++;
dataremaining--;
(void)SDIO_WriteFIFO(hmmc->Instance, &data);
}
hmmc->pTxBuffPtr = tmp;
hmmc->TxXferSize = dataremaining;
}
}
/**
* @brief Update the power class of the device.
* @param hmmc MMC handle
* @param Wide Wide of MMC bus
* @param Speed Speed of the MMC bus
* @retval MMC Card error state
*/
static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide)
{
uint32_t count;
uint32_t response = 0U;
uint32_t errorstate = HAL_MMC_ERROR_NONE;
uint32_t power_class, supported_pwr_class;
if((Wide == SDIO_BUS_WIDE_8B) || (Wide == SDIO_BUS_WIDE_4B))
{
power_class = 0U; /* Default value after power-on or software reset */
/* Read the PowerClass field of the Extended CSD register */
if(MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */
{
errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
}
else
{
power_class = ((power_class >> 24U) & 0x000000FFU);
}
/* Get the supported PowerClass field of the Extended CSD register */
/* Field PWR_CL_26_xxx [201 or 203] */
supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & 0x000000FFU);
if(errorstate == HAL_MMC_ERROR_NONE)
{
if(Wide == SDIO_BUS_WIDE_8B)
{
/* Bit [7:4] : power class for 8-bits bus configuration - Bit [3:0] : power class for 4-bits bus configuration */
supported_pwr_class = (supported_pwr_class >> 4U);
}
if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU))
{
/* Need to change current power class */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U)));
if(errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if(errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
count--;
}while(((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
}
else if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else
{
/* Nothing to do */
}
}
}
}
}
return errorstate;
}
/**
* @}
*/
#endif /* SDIO */
#endif /* HAL_MMC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

92
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_msp_template.c Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_msp_template.c
* @author MCD Application Team
* @brief HAL BSP module.
* This file template is located in the HAL folder and should be copied
* to the user folder.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup HAL_MSP HAL_MSP
* @brief HAL MSP module.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HAL_MSP_Exported_Functions HAL MSP Exported Functions
* @{
*/
/**
* @brief Initializes the Global MSP.
* @retval None
*/
void HAL_MspInit(void)
{
}
/**
* @brief DeInitializes the Global MSP.
* @retval None
*/
void HAL_MspDeInit(void)
{
}
/**
* @brief Initializes the PPP MSP.
* @retval None
*/
void HAL_PPP_MspInit(void)
{
}
/**
* @brief DeInitializes the PPP MSP.
* @retval None
*/
void HAL_PPP_MspDeInit(void)
{
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

2315
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_nand.c
* @author MCD Application Team
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
control NAND flash memories. It uses the FSMC layer functions to interface
with NAND devices. This driver is used as follows:
(+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
with control and timing parameters for both common and attribute spaces.
(+) Read NAND flash memory maker and device IDs using the function
HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
structure declared by the function caller.
(+) Access NAND flash memory by read/write operations using the functions
HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
to read/write page(s)/spare area(s). These functions use specific device
information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
structure. The read/write address information is contained by the Nand_Address_Typedef
structure passed as parameter.
(+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
(+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
The erase block address information is contained in the Nand_Address_Typedef
structure passed as parameter.
(+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
(+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
feature or the function HAL_NAND_GetECC() to get the ECC correction code.
(+) You can monitor the NAND device HAL state by calling the function
HAL_NAND_GetState()
[..]
(@) This driver is a set of generic APIs which handle standard NAND flash operations.
If a NAND flash device contains different operations and/or implementations,
it should be implemented separately.
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_NAND_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (overridden) functions in the HAL_NAND_Init
and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
or HAL_NAND_Init function.
When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
#if defined(FSMC_BANK3)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_NAND_MODULE_ENABLED
/** @defgroup NAND NAND
* @brief NAND HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private Constants ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### NAND Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize
the NAND memory
@endverbatim
* @{
*/
/**
* @brief Perform NAND memory Initialization sequence
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param ComSpace_Timing pointer to Common space timing structure
* @param AttSpace_Timing pointer to Attribute space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
{
/* Check the NAND handle state */
if (hnand == NULL)
{
return HAL_ERROR;
}
if (hnand->State == HAL_NAND_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hnand->Lock = HAL_UNLOCKED;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
if (hnand->MspInitCallback == NULL)
{
hnand->MspInitCallback = HAL_NAND_MspInit;
}
hnand->ItCallback = HAL_NAND_ITCallback;
/* Init the low level hardware */
hnand->MspInitCallback(hnand);
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
}
/* Initialize NAND control Interface */
(void)FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
/* Initialize NAND common space timing Interface */
(void)FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
/* Initialize NAND attribute space timing Interface */
(void)FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
/* Enable the NAND device */
__FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
return HAL_OK;
}
/**
* @brief Perform NAND memory De-Initialization sequence
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
{
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
if (hnand->MspDeInitCallback == NULL)
{
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
}
/* DeInit the low level hardware */
hnand->MspDeInitCallback(hnand);
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspDeInit(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Configure the NAND registers with their reset values */
(void)FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
/* Reset the NAND controller state */
hnand->State = HAL_NAND_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief NAND MSP Init
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_MspInit could be implemented in the user file
*/
}
/**
* @brief NAND MSP DeInit
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function handles NAND device interrupt request.
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
{
/* Check NAND interrupt Rising edge flag */
if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
{
/* NAND interrupt callback*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Rising edge pending bit */
__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
}
/* Check NAND interrupt Level flag */
if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
{
/* NAND interrupt callback*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Level pending bit */
__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
}
/* Check NAND interrupt Falling edge flag */
if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
{
/* NAND interrupt callback*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Falling edge pending bit */
__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
}
/* Check NAND interrupt FIFO empty flag */
if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
{
/* NAND interrupt callback*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt FIFO empty pending bit */
__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
}
}
/**
* @brief NAND interrupt feature callback
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_ITCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
==============================================================================
##### NAND Input and Output functions #####
==============================================================================
[..]
This section provides functions allowing to use and control the NAND
memory
@endverbatim
* @{
*/
/**
* @brief Read the NAND memory electronic signature
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pNAND_ID NAND ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
{
__IO uint32_t data = 0;
__IO uint32_t data1 = 0;
uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* Send Read ID command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
__DSB();
/* Read the electronic signature from NAND flash */
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
{
data = *(__IO uint32_t *)deviceaddress;
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
}
else
{
data = *(__IO uint32_t *)deviceaddress;
data1 = *((__IO uint32_t *)deviceaddress + 4);
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief NAND memory reset
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* Send NAND reset command */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Configure the device: Enter the physical parameters of the device
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig)
{
hnand->Config.PageSize = pDeviceConfig->PageSize;
hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
hnand->Config.BlockSize = pDeviceConfig->BlockSize;
hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
return HAL_OK;
}
/**
* @brief Read Page(s) from NAND memory block (8-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to destination read buffer
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numpagesread = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToRead;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Go back to read mode */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Read Page(s) from NAND memory block (16-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numpagesread = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToRead;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Go back to read mode */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Calculate PageSize */
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
{
hnand->Config.PageSize = hnand->Config.PageSize / 2U;
}
else
{
/* Do nothing */
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Write Page(s) to NAND memory block (8-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Increment written pages number */
numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Write Page(s) to NAND memory block (16-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
/* Calculate PageSize */
if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
{
hnand->Config.PageSize = hnand->Config.PageSize / 2U;
}
else
{
/* Do nothing */
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
}
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Increment written pages number */
numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Read Spare area(s) from NAND memory (8-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numsparearearead = 0U;
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaToRead;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) read loop */
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Go back to read mode */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Read Spare area(s) from NAND memory (16-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numsparearearead = 0U;
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaToRead;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) read loop */
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Go back to read mode */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Write Spare area(s) to NAND memory (8-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numspareareawritten = 0U;
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* Page address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) write loop */
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Increment written spare areas number */
numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Write Spare area(s) to NAND memory (16-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numspareareawritten = 0U;
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) write loop */
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Increment written spare areas number */
numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief NAND memory Block erase
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
{
uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* Send Erase block command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
__DSB();
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Increment the NAND memory address
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @retval The new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t status = NAND_VALID_ADDRESS;
/* Increment page address */
pAddress->Page++;
/* Check NAND address is valid */
if (pAddress->Page == hnand->Config.BlockSize)
{
pAddress->Page = 0;
pAddress->Block++;
if (pAddress->Block == hnand->Config.PlaneSize)
{
pAddress->Block = 0;
pAddress->Plane++;
if (pAddress->Plane == (hnand->Config.PlaneNbr))
{
status = NAND_INVALID_ADDRESS;
}
}
}
return (status);
}
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NAND Callback
* To be used to override the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
* @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
pNAND_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
return HAL_ERROR;
}
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
case HAL_NAND_MSP_INIT_CB_ID :
hnand->MspInitCallback = pCallback;
break;
case HAL_NAND_MSP_DEINIT_CB_ID :
hnand->MspDeInitCallback = pCallback;
break;
case HAL_NAND_IT_CB_ID :
hnand->ItCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
case HAL_NAND_MSP_INIT_CB_ID :
hnand->MspInitCallback = pCallback;
break;
case HAL_NAND_MSP_DEINIT_CB_ID :
hnand->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a User NAND Callback
* NAND Callback is redirected to the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
* @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
case HAL_NAND_MSP_INIT_CB_ID :
hnand->MspInitCallback = HAL_NAND_MspInit;
break;
case HAL_NAND_MSP_DEINIT_CB_ID :
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
break;
case HAL_NAND_IT_CB_ID :
hnand->ItCallback = HAL_NAND_ITCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
case HAL_NAND_MSP_INIT_CB_ID :
hnand->MspInitCallback = HAL_NAND_MspInit;
break;
case HAL_NAND_MSP_DEINIT_CB_ID :
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
==============================================================================
##### NAND Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the NAND interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically NAND ECC feature.
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
{
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Enable ECC feature */
(void)FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disables dynamically FSMC_NAND ECC feature.
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
{
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Disable ECC feature */
(void)FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disables dynamically NAND ECC feature.
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param ECCval pointer to ECC value
* @param Timeout maximum timeout to wait
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
{
HAL_StatusTypeDef status;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Get NAND ECC value */
status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @}
*/
/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### NAND State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the NAND controller
and the data flow.
@endverbatim
* @{
*/
/**
* @brief return the NAND state
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL state
*/
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
{
return hnand->State;
}
/**
* @brief NAND memory read status
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval NAND status
*/
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
{
uint32_t data;
uint32_t deviceaddress;
UNUSED(hnand);
/* Identify the device address */
if (hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* Send Read status operation command */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
/* Read status register data */
data = *(__IO uint8_t *)deviceaddress;
/* Return the status */
if ((data & NAND_ERROR) == NAND_ERROR)
{
return NAND_ERROR;
}
else if ((data & NAND_READY) == NAND_READY)
{
return NAND_READY;
}
else
{
return NAND_BUSY;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_NAND_MODULE_ENABLED */
/**
* @}
*/
#endif /* FSMC_BANK3 */

1641
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c Normal file
View File

@@ -0,0 +1,1641 @@
/**
******************************************************************************
* @file stm32f1xx_hal_nor.c
* @author MCD Application Team
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
control NOR flash memories. It uses the FSMC layer functions to interface
with NOR devices. This driver is used as follows:
(+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
with control and timing parameters for both normal and extended mode.
(+) Read NOR flash memory manufacturer code and device IDs using the function
HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
structure declared by the function caller.
(+) Access NOR flash memory by read/write data unit operations using the functions
HAL_NOR_Read(), HAL_NOR_Program().
(+) Perform NOR flash erase block/chip operations using the functions
HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
(+) Read the NOR flash CFI (common flash interface) IDs using the function
HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
structure declared by the function caller.
(+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
(+) You can monitor the NOR device HAL state by calling the function
HAL_NOR_GetState()
[..]
(@) This driver is a set of generic APIs which handle standard NOR flash operations.
If a NOR flash device contains different operations and/or implementations,
it should be implemented separately.
*** NOR HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in NOR HAL driver.
(+) NOR_WRITE : NOR memory write data to specified address
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_NOR_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (overridden) functions in the HAL_NOR_Init
and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
or HAL_NOR_Init function.
When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
#if defined(FSMC_BANK1)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_NOR_MODULE_ENABLED
/** @defgroup NOR NOR
* @brief NOR driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup NOR_Private_Defines NOR Private Defines
* @{
*/
/* Constants to define address to set to write a command */
#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA
#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA
#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555
#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA
#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
/* Constants to define data to program a command */
#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define NOR_CMD_DATA_CFI (uint16_t)0x0098
#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
#define NOR_CMD_CONFIRM (uint16_t)0x00D0
#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
/* Mask on NOR STATUS REGISTER */
#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
/* Address of the primary command set */
#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup NOR_Private_Variables NOR Private Variables
* @{
*/
static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup NOR_Exported_Functions NOR Exported Functions
* @{
*/
/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### NOR Initialization and de_initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize
the NOR memory
@endverbatim
* @{
*/
/**
* @brief Perform the NOR memory Initialization sequence
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Timing pointer to NOR control timing structure
* @param ExtTiming pointer to NOR extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
FSMC_NORSRAM_TimingTypeDef *ExtTiming)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR handle parameter */
if (hnor == NULL)
{
return HAL_ERROR;
}
if (hnor->State == HAL_NOR_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hnor->Lock = HAL_UNLOCKED;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
if (hnor->MspInitCallback == NULL)
{
hnor->MspInitCallback = HAL_NOR_MspInit;
}
/* Init the low level hardware */
hnor->MspInitCallback(hnor);
#else
/* Initialize the low level hardware (MSP) */
HAL_NOR_MspInit(hnor);
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
}
/* Initialize NOR control Interface */
(void)FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
/* Initialize NOR timing Interface */
(void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
/* Initialize NOR extended mode timing Interface */
(void)FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming,
hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
/* Initialize NOR Memory Data Width*/
if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
{
uwNORMemoryDataWidth = NOR_MEMORY_8B;
}
else
{
uwNORMemoryDataWidth = NOR_MEMORY_16B;
}
/* Initialize the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
if (hnor->Init.WriteOperation == FSMC_WRITE_OPERATION_DISABLE)
{
(void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_PROTECTED;
}
else
{
/* Get the value of the command set */
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
NOR_CMD_DATA_CFI);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
}
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
status = HAL_NOR_ReturnToReadMode(hnor);
}
return status;
}
/**
* @brief Perform NOR memory De-Initialization sequence
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
{
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
if (hnor->MspDeInitCallback == NULL)
{
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
}
/* DeInit the low level hardware */
hnor->MspDeInitCallback(hnor);
#else
/* De-Initialize the low level hardware (MSP) */
HAL_NOR_MspDeInit(hnor);
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
/* Configure the NOR registers with their reset values */
(void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
/* Reset the NOR controller state */
hnor->State = HAL_NOR_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hnor);
return HAL_OK;
}
/**
* @brief NOR MSP Init
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspInit could be implemented in the user file
*/
}
/**
* @brief NOR MSP DeInit
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspDeInit could be implemented in the user file
*/
}
/**
* @brief NOR MSP Wait for Ready/Busy signal
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Timeout Maximum timeout value
* @retval None
*/
__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
UNUSED(Timeout);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspWait could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
==============================================================================
##### NOR Input and Output functions #####
==============================================================================
[..]
This section provides functions allowing to use and control the NOR memory
@endverbatim
* @{
*/
/**
* @brief Read NOR flash IDs
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param pNOR_ID pointer to NOR ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send read ID command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_AUTO_SELECT);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_AUTO_SELECT);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Read the NOR IDs */
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
DEVICE_CODE1_ADDR);
pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
DEVICE_CODE2_ADDR);
pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
DEVICE_CODE3_ADDR);
}
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Returns the NOR memory to Read mode.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Read data from NOR memory
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param pAddress pointer to Device address
* @param pData pointer to read data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_READ_RESET);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_READ_RESET);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Read the data */
*pData = (uint16_t)(*(__IO uint32_t *)pAddress);
}
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Program data to NOR memory
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param pAddress Device address
* @param pData pointer to the data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send program data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_PROGRAM);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Write the data */
NOR_WRITE(pAddress, *pData);
}
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Reads a half-word buffer from the NOR memory.
* @param hnor pointer to the NOR handle
* @param uwAddress NOR memory internal address to read from.
* @param pData pointer to the buffer that receives the data read from the
* NOR memory.
* @param uwBufferSize number of Half word to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize)
{
uint32_t deviceaddress;
uint32_t size = uwBufferSize;
uint32_t address = uwAddress;
uint16_t *data = pData;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_READ_RESET);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_READ_RESET);
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Read buffer */
while (size > 0U)
{
*data = *(__IO uint16_t *)address;
data++;
address += 2U;
size--;
}
}
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Writes a half-word buffer to the NOR memory. This function must be used
only with S29GL128P NOR memory.
* @param hnor pointer to the NOR handle
* @param uwAddress NOR memory internal start write address
* @param pData pointer to source data buffer.
* @param uwBufferSize Size of the buffer to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize)
{
uint16_t *p_currentaddress;
const uint16_t *p_endaddress;
uint16_t *data = pData;
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Initialize variables */
p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
}
else
{
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
}
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Load Data into NOR Buffer */
while (p_currentaddress <= p_endaddress)
{
NOR_WRITE(p_currentaddress, *data);
data++;
p_currentaddress ++;
}
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
}
else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
{
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
}
}
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Erase the specified block of the NOR memory
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param BlockAddress Block to erase address
* @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send block erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
}
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Erase the entire NOR chip.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
UNUSED(Address);
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send NOR chip erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH),
NOR_CMD_DATA_CHIP_ERASE);
}
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Read NOR flash CFI IDs
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param pNOR_CFI pointer to NOR CFI IDs structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send read CFI query command */
if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
NOR_CMD_DATA_CFI);
}
else
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
}
/* read the NOR CFI information */
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NOR Callback
* To be used to override the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
pNOR_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
if (pCallback == NULL)
{
return HAL_ERROR;
}
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_NOR_MSP_INIT_CB_ID :
hnor->MspInitCallback = pCallback;
break;
case HAL_NOR_MSP_DEINIT_CB_ID :
hnor->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a User NOR Callback
* NOR Callback is redirected to the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_NOR_MSP_INIT_CB_ID :
hnor->MspInitCallback = HAL_NOR_MspInit;
break;
case HAL_NOR_MSP_DEINIT_CB_ID :
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
/**
* @}
*/
/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
* @brief management functions
*
@verbatim
==============================================================================
##### NOR Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the NOR interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically NOR write operation.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Enable write operation */
(void)FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disables dynamically NOR write operation.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Disable write operation */
(void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_PROTECTED;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### NOR State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the NOR controller
and the data flow.
@endverbatim
* @{
*/
/**
* @brief return the NOR controller state
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval NOR controller state
*/
HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
{
return hnor->State;
}
/**
* @brief Returns the NOR operation status.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Address Device address
* @param Timeout NOR programming Timeout
* @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
* or HAL_NOR_STATUS_TIMEOUT
*/
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
uint16_t tmpsr1;
uint16_t tmpsr2;
uint32_t tickstart;
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
HAL_NOR_MspWait(hnor, Timeout);
/* Get the NOR memory operation status -------------------------------------*/
/* Get tick */
tickstart = HAL_GetTick();
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_NOR_STATUS_TIMEOUT;
}
}
/* Read NOR status register (DQ6 and DQ5) */
tmpsr1 = *(__IO uint16_t *)Address;
tmpsr2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS ;
}
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
status = HAL_NOR_STATUS_ONGOING;
}
tmpsr1 = *(__IO uint16_t *)Address;
tmpsr2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS;
}
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
return HAL_NOR_STATUS_ERROR;
}
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
do
{
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
tmpsr2 = *(__IO uint16_t *)(Address);
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_NOR_STATUS_TIMEOUT;
}
}
} while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
tmpsr1 = *(__IO uint16_t *)(Address);
if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
{
/* Clear the Status Register */
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
status = HAL_NOR_STATUS_ERROR;
}
else
{
status = HAL_NOR_STATUS_SUCCESS;
}
}
else
{
/* Primary command set not supported by the driver */
status = HAL_NOR_STATUS_ERROR;
}
/* Return the operation status */
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_NOR_MODULE_ENABLED */
/**
* @}
*/
#endif /* FSMC_BANK1 */

952
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pccard.c Normal file
View File

@@ -0,0 +1,952 @@
/**
******************************************************************************
* @file stm32f1xx_hal_pccard.c
* @author MCD Application Team
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
control PCCARD/compact flash memories. It uses the FSMC layer functions
to interface with PCCARD devices. This driver is used for:
(+) PCCARD/Compact Flash memory configuration sequence using the function
HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
both common and attribute spaces.
(+) Read PCCARD/Compact Flash memory maker and device IDs using the function
HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
the CompactFlash_ID structure declared by the function caller.
(+) Access PCCARD/Compact Flash memory by read/write operations using the functions
HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
(+) Perform PCCARD/Compact Flash Reset chip operation using the function
HAL_PCCARD_Reset()/HAL_CF_Reset.
(+) Perform PCCARD/Compact Flash erase sector operation using the function
HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.
(+) Read the PCCARD/Compact Flash status operation using the function
HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().
(+) You can monitor the PCCARD/Compact Flash device HAL state by calling
the function HAL_PCCARD_GetState()/HAL_CF_GetState()
[..]
(@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
operations. If a PCCARD/Compact Flash device contains different operations
and/or implementations, it should be implemented separately.
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_PCCARD_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : PCCARD MspInit.
(+) MspDeInitCallback : PCCARD MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_PCCARD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : PCCARD MspInit.
(+) MspDeInitCallback : PCCARD MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_PCCARD_Init and if the state is HAL_PCCARD_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_PCCARD_Init
and HAL_PCCARD_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_PCCARD_Init and HAL_PCCARD_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_PCCARD_RegisterCallback before calling HAL_PCCARD_DeInit
or HAL_PCCARD_Init function.
When The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
#if defined(FSMC_BANK4)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_PCCARD_MODULE_ENABLED
/** @defgroup PCCARD PCCARD
* @brief PCCARD HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PCCARD_Private_Defines PCCARD Private Defines
* @{
*/
#define PCCARD_TIMEOUT_READ_ID 0x0000FFFFU
#define PCCARD_TIMEOUT_READ_WRITE_SECTOR 0x0000FFFFU
#define PCCARD_TIMEOUT_ERASE_SECTOR 0x00000400U
#define PCCARD_TIMEOUT_STATUS 0x01000000U
#define PCCARD_STATUS_OK (uint8_t)0x58
#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function ----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
* @{
*/
/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### PCCARD Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize
the PCCARD memory
@endverbatim
* @{
*/
/**
* @brief Perform the PCCARD memory Initialization sequence
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param ComSpaceTiming Common space timing structure
* @param AttSpaceTiming Attribute space timing structure
* @param IOSpaceTiming IO space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming,
FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
{
/* Check the PCCARD controller state */
if (hpccard == NULL)
{
return HAL_ERROR;
}
if (hpccard->State == HAL_PCCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpccard->Lock = HAL_UNLOCKED;
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
if (hpccard->MspInitCallback == NULL)
{
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
}
hpccard->ItCallback = HAL_PCCARD_ITCallback;
/* Init the low level hardware */
hpccard->MspInitCallback(hpccard);
#else
/* Initialize the low level hardware (MSP) */
HAL_PCCARD_MspInit(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
}
/* Initialize the PCCARD state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize PCCARD control Interface */
FSMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
/* Init PCCARD common space timing Interface */
FSMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
/* Init PCCARD attribute space timing Interface */
FSMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
/* Init PCCARD IO space timing Interface */
FSMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
/* Enable the PCCARD device */
__FSMC_PCCARD_ENABLE(hpccard->Instance);
/* Update the PCCARD state */
hpccard->State = HAL_PCCARD_STATE_READY;
return HAL_OK;
}
/**
* @brief Perform the PCCARD memory De-initialization sequence
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
{
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
if (hpccard->MspDeInitCallback == NULL)
{
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
}
/* DeInit the low level hardware */
hpccard->MspDeInitCallback(hpccard);
#else
/* De-Initialize the low level hardware (MSP) */
HAL_PCCARD_MspDeInit(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Configure the PCCARD registers with their reset values */
FSMC_PCCARD_DeInit(hpccard->Instance);
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief PCCARD MSP Init
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpccard);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCCARD_MspInit could be implemented in the user file
*/
}
/**
* @brief PCCARD MSP DeInit
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpccard);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCCARD_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
==============================================================================
##### PCCARD Input and Output functions #####
==============================================================================
[..]
This section provides functions allowing to use and control the PCCARD memory
@endverbatim
* @{
*/
/**
* @brief Read Compact Flash's ID.
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param CompactFlash_ID Compact flash ID structure.
* @param pStatus pointer to compact flash status
* @retval HAL status
*
*/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
uint32_t timeout = 0U;
uint32_t index = 0U;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize the PCCARD status */
*pStatus = PCCARD_READY;
/* Send the Identify Command */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xECEC;
/* Read PCCARD IDs and timeout treatment */
do
{
/* Read the PCCARD status */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status != PCCARD_STATUS_OK) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
else
{
/* Read PCCARD ID bytes */
for (index = 0U; index < 16U; index++)
{
CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
}
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief Read sector from PCCARD memory
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param pBuffer pointer to destination read buffer
* @param SectorAddress Sector address to read
* @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
uint32_t timeout = 0U;
uint32_t index = 0U;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize PCCARD status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
do
{
/* wait till the Status = 0x80 */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status == 0x80U) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
do
{
/* wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status != PCCARD_STATUS_OK) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Read bytes */
for (; index < PCCARD_SECTOR_SIZE; index++)
{
*(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief Write sector to PCCARD memory
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param pBuffer pointer to source write buffer
* @param SectorAddress Sector address to write
* @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus)
{
uint32_t timeout = 0U;
uint32_t index = 0U;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize PCCARD status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
do
{
/* Wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status != PCCARD_STATUS_OK) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Write bytes */
for (; index < PCCARD_SECTOR_SIZE; index++)
{
*(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
}
do
{
/* Wait till the Status = PCCARD_STATUS_WRITE_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
} while ((status != PCCARD_STATUS_WRITE_OK) && timeout);
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief Erase sector from PCCARD memory
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param SectorAddress Sector address to erase
* @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize PCCARD status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
/* wait till the PCCARD is ready */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
while ((status != PCCARD_STATUS_WRITE_OK) && timeout)
{
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if (timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief Reset the PCCARD memory
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
{
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Provide a SW reset and Read and verify the:
- PCCard Configuration Option Register at address 0x98000200 --> 0x80
- Card Configuration and Status Register at address 0x98000202 --> 0x00
- Pin Replacement Register at address 0x98000204 --> 0x0C
- Socket and Copy Register at address 0x98000206 --> 0x00
*/
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
*(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
/* Check the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief This function handles PCCARD device interrupt request.
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
{
/* Check PCCARD interrupt Rising edge flag */
if (__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE))
{
/* PCCARD interrupt callback*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Rising edge pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
}
/* Check PCCARD interrupt Level flag */
if (__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL))
{
/* PCCARD interrupt callback*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Level pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
}
/* Check PCCARD interrupt Falling edge flag */
if (__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE))
{
/* PCCARD interrupt callback*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt Falling edge pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
}
/* Check PCCARD interrupt FIFO empty flag */
if (__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT))
{
/* PCCARD interrupt callback*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
hpccard->ItCallback(hpccard);
#else
HAL_PCCARD_ITCallback(hpccard);
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/* Clear PCCARD interrupt FIFO empty pending bit */
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
}
}
/**
* @brief PCCARD interrupt feature callback
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpccard);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCCARD_ITCallback could be implemented in the user file
*/
}
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User PCCARD Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hpccard : PCCARD handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_PCCARD_MSP_INIT_CB_ID PCCARD MspInit callback ID
* @arg @ref HAL_PCCARD_MSP_DEINIT_CB_ID PCCARD MspDeInit callback ID
* @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
pPCCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpccard);
if (hpccard->State == HAL_PCCARD_STATE_READY)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = pCallback;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = pCallback;
break;
case HAL_PCCARD_IT_CB_ID :
hpccard->ItCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hpccard->State == HAL_PCCARD_STATE_RESET)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = pCallback;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpccard);
return status;
}
/**
* @brief Unregister a User PCCARD Callback
* PCCARD Callback is redirected to the weak (surcharged) predefined callback
* @param hpccard : PCCARD handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_PCCARD_MSP_INIT_CB_ID PCCARD MspInit callback ID
* @arg @ref HAL_PCCARD_MSP_DEINIT_CB_ID PCCARD MspDeInit callback ID
* @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpccard);
if (hpccard->State == HAL_PCCARD_STATE_READY)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
break;
case HAL_PCCARD_IT_CB_ID :
hpccard->ItCallback = HAL_PCCARD_ITCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hpccard->State == HAL_PCCARD_STATE_RESET)
{
switch (CallbackId)
{
case HAL_PCCARD_MSP_INIT_CB_ID :
hpccard->MspInitCallback = HAL_PCCARD_MspInit;
break;
case HAL_PCCARD_MSP_DEINIT_CB_ID :
hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpccard);
return status;
}
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup PCCARD_Exported_Functions_Group3 State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### PCCARD State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the PCCARD controller
and the data flow.
@endverbatim
* @{
*/
/**
* @brief return the PCCARD controller state
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL state
*/
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
{
return hpccard->State;
}
/**
* @brief Get the compact flash memory status
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval New status of the PCCARD operation. This parameter can be:
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
* - CompactFlash_READY: when memory is ready for the next operation
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
uint32_t timeout = PCCARD_TIMEOUT_STATUS;
uint32_t status_pccard = 0U;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_PCCARD_STATUS_ONGOING;
}
status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
while ((status_pccard == PCCARD_BUSY) && timeout)
{
status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}
if (timeout == 0U)
{
status_pccard = PCCARD_TIMEOUT_ERROR;
}
/* Return the operation status */
return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
* @brief Reads the Compact Flash memory status using the Read status command
* @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval The status of the Compact Flash memory. This parameter can be:
* - CompactFlash_BUSY: when memory is busy
* - CompactFlash_READY: when memory is ready for the next operation
* - CompactFlash_ERROR: when the previous operation generates error
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
uint8_t data = 0U;
uint8_t status_pccard = PCCARD_BUSY;
/* Check the PCCARD controller state */
if (hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_PCCARD_STATUS_ONGOING;
}
/* Read status operation */
data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
if ((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
{
status_pccard = PCCARD_TIMEOUT_ERROR;
}
else if ((data & PCCARD_READY) == PCCARD_READY)
{
status_pccard = PCCARD_READY;
}
return (HAL_PCCARD_StatusTypeDef) status_pccard;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PCCARD_MODULE_ENABLED */
/**
* @}
*/
#endif /* FSMC_BANK4 */

2720
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c Normal file
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@@ -0,0 +1,2720 @@
/**
******************************************************************************
* @file stm32f1xx_hal_pcd.c
* @author MCD Application Team
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The PCD HAL driver can be used as follows:
(#) Declare a PCD_HandleTypeDef handle structure, for example:
PCD_HandleTypeDef hpcd;
(#) Fill parameters of Init structure in HCD handle
(#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
(+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral
(+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
(##) Configure PCD NVIC interrupt
(#)Associate the Upper USB device stack to the HAL PCD Driver:
(##) hpcd.pData = pdev;
(#)Enable PCD transmission and reception:
(##) HAL_PCD_Start();
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup PCD PCD
* @brief PCD HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined (USB) || defined (USB_OTG_FS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup PCD_Private_Functions PCD Private Functions
* @{
*/
#if defined (USB_OTG_FS)
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
#if (USE_USB_DOUBLE_BUFFER == 1U)
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
#endif /* defined (USB) */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
@endverbatim
* @{
*/
/**
* @brief Initializes the PCD according to the specified
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if (hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback = HAL_PCD_SOFCallback;
hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
hpcd->ResetCallback = HAL_PCD_ResetCallback;
hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
if (hpcd->MspInitCallback == NULL)
{
hpcd->MspInitCallback = HAL_PCD_MspInit;
}
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
/* Disable DMA mode for FS instance */
hpcd->Init.dma_enable = 0U;
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
{
hpcd->State = HAL_PCD_STATE_ERROR;
return HAL_ERROR;
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
{
hpcd->State = HAL_PCD_STATE_ERROR;
return HAL_ERROR;
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
hpcd->IN_ep[i].num = i;
#if defined (USB_OTG_FS)
hpcd->IN_ep[i].tx_fifo_num = i;
#endif /* defined (USB_OTG_FS) */
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0U;
hpcd->IN_ep[i].xfer_buff = 0U;
hpcd->IN_ep[i].xfer_len = 0U;
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
hpcd->OUT_ep[i].is_in = 0U;
hpcd->OUT_ep[i].num = i;
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
hpcd->OUT_ep[i].maxpacket = 0U;
hpcd->OUT_ep[i].xfer_buff = 0U;
hpcd->OUT_ep[i].xfer_len = 0U;
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
{
hpcd->State = HAL_PCD_STATE_ERROR;
return HAL_ERROR;
}
hpcd->USB_Address = 0U;
hpcd->State = HAL_PCD_STATE_READY;
(void)USB_DevDisconnect(hpcd->Instance);
return HAL_OK;
}
/**
* @brief DeInitializes the PCD peripheral.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
{
/* Check the PCD handle allocation */
if (hpcd == NULL)
{
return HAL_ERROR;
}
hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
if (USB_StopDevice(hpcd->Instance) != HAL_OK)
{
return HAL_ERROR;
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
if (hpcd->MspDeInitCallback == NULL)
{
hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hpcd->MspDeInitCallback(hpcd);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_PCD_MspDeInit(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
hpcd->State = HAL_PCD_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initializes the PCD MSP.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes PCD MSP.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_MspDeInit could be implemented in the user file
*/
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User USB PCD Callback
* To be used instead of the weak predefined callback
* @param hpcd USB PCD handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
* @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
* @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
* @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
switch (CallbackID)
{
case HAL_PCD_SOF_CB_ID :
hpcd->SOFCallback = pCallback;
break;
case HAL_PCD_SETUPSTAGE_CB_ID :
hpcd->SetupStageCallback = pCallback;
break;
case HAL_PCD_RESET_CB_ID :
hpcd->ResetCallback = pCallback;
break;
case HAL_PCD_SUSPEND_CB_ID :
hpcd->SuspendCallback = pCallback;
break;
case HAL_PCD_RESUME_CB_ID :
hpcd->ResumeCallback = pCallback;
break;
case HAL_PCD_CONNECT_CB_ID :
hpcd->ConnectCallback = pCallback;
break;
case HAL_PCD_DISCONNECT_CB_ID :
hpcd->DisconnectCallback = pCallback;
break;
case HAL_PCD_MSPINIT_CB_ID :
hpcd->MspInitCallback = pCallback;
break;
case HAL_PCD_MSPDEINIT_CB_ID :
hpcd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hpcd->State == HAL_PCD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_PCD_MSPINIT_CB_ID :
hpcd->MspInitCallback = pCallback;
break;
case HAL_PCD_MSPDEINIT_CB_ID :
hpcd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister an USB PCD Callback
* USB PCD callback is redirected to the weak predefined callback
* @param hpcd USB PCD handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
* @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
* @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
* @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
/* Setup Legacy weak Callbacks */
if (hpcd->State == HAL_PCD_STATE_READY)
{
switch (CallbackID)
{
case HAL_PCD_SOF_CB_ID :
hpcd->SOFCallback = HAL_PCD_SOFCallback;
break;
case HAL_PCD_SETUPSTAGE_CB_ID :
hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
break;
case HAL_PCD_RESET_CB_ID :
hpcd->ResetCallback = HAL_PCD_ResetCallback;
break;
case HAL_PCD_SUSPEND_CB_ID :
hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
break;
case HAL_PCD_RESUME_CB_ID :
hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
break;
case HAL_PCD_CONNECT_CB_ID :
hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
break;
case HAL_PCD_DISCONNECT_CB_ID :
hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
break;
case HAL_PCD_MSPINIT_CB_ID :
hpcd->MspInitCallback = HAL_PCD_MspInit;
break;
case HAL_PCD_MSPDEINIT_CB_ID :
hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
break;
default :
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hpcd->State == HAL_PCD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_PCD_MSPINIT_CB_ID :
hpcd->MspInitCallback = HAL_PCD_MspInit;
break;
case HAL_PCD_MSPDEINIT_CB_ID :
hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
break;
default :
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD Data OUT Stage Callback
* To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD Data OUT Stage Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->DataOutStageCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD Data OUT Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD Data IN Stage Callback
* To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD Data IN Stage Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataInStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->DataInStageCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD Data IN Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD Iso OUT incomplete Callback
* To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoOutIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->ISOOUTIncompleteCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD Iso OUT incomplete Callback
* USB PCD Iso OUT incomplete Callback is redirected
* to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD Iso IN incomplete Callback
* To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoInIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->ISOINIncompleteCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD Iso IN incomplete Callback
* USB PCD Iso IN incomplete Callback is redirected
* to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the PCD data
transfers.
@endverbatim
* @{
*/
/**
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
__HAL_PCD_ENABLE(hpcd);
#if defined (USB)
HAL_PCDEx_SetConnectionState(hpcd, 1U);
#endif /* defined (USB) */
(void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Stop the USB device.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
#if defined (USB)
HAL_PCDEx_SetConnectionState(hpcd, 0U);
#endif /* defined (USB) */
(void)USB_DevDisconnect(hpcd->Instance);
#if defined (USB_OTG_FS)
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
#endif /* defined (USB_OTG_FS) */
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
#if defined (USB_OTG_FS)
/**
* @brief Handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
USB_OTG_EPTypeDef *ep;
uint32_t i;
uint32_t ep_intr;
uint32_t epint;
uint32_t epnum;
uint32_t fifoemptymsk;
uint32_t RegVal;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
{
/* avoid spurious interrupt */
if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
{
return;
}
/* store current frame number */
hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
{
/* incorrect mode, acknowledge the interrupt */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
/* Handle RxQLevel Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
RegVal = USBx->GRXSTSP;
ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
{
(void)USB_ReadPacket(USBx, ep->xfer_buff,
(uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
}
}
else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
{
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
}
else
{
/* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0U;
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
while (ep_intr != 0U)
{
if ((ep_intr & 0x1U) != 0U)
{
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
}
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
/* Class B setup phase done for previous decoded setup */
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
}
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
}
/* Clear OUT Endpoint disable interrupt */
if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
{
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
}
ep = &hpcd->OUT_ep[epnum];
if (ep->is_iso_incomplete == 1U)
{
ep->is_iso_incomplete = 0U;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
}
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
/* Clear OUT NAK interrupt */
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
}
}
epnum++;
ep_intr >>= 1U;
}
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
{
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
epnum = 0U;
while (ep_intr != 0U)
{
if ((ep_intr & 0x1U) != 0U) /* In ITR */
{
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
}
if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
}
if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
}
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
{
(void)USB_FlushTxFifo(USBx, epnum);
ep = &hpcd->IN_ep[epnum];
if (ep->is_iso_incomplete == 1U)
{
ep->is_iso_incomplete = 0U;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
}
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
{
(void)PCD_WriteEmptyTxFifo(hpcd, epnum);
}
}
epnum++;
ep_intr >>= 1U;
}
}
/* Handle Resume Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
{
/* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
}
/* Handle Suspend Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
{
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
/* Handle Reset Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
}
USBx_DEVICE->DAINTMSK |= 0x10001U;
if (hpcd->Init.use_dedicated_ep1 != 0U)
{
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM;
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
else
{
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM |
USB_OTG_DOEPMSK_OTEPSPRM |
USB_OTG_DOEPMSK_NAKM;
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
/* Set Default Address to 0 */
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
/* setup EP0 to receive SETUP packets */
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
}
/* Handle Enumeration done Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
{
(void)USB_ActivateSetup(hpcd->Instance);
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
/* Set USB Turnaround time */
(void)USB_SetTurnaroundTime(hpcd->Instance,
HAL_RCC_GetHCLKFreq(),
(uint8_t)hpcd->Init.speed);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
/* Handle SOF Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
}
/* Handle Global OUT NAK effective Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
{
USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
{
if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
{
/* Abort current transaction and disable the EP */
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
}
}
}
/* Handle Incomplete ISO IN Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
{
RegVal = USBx_INEP(epnum)->DIEPCTL;
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
{
hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
/* Abort current transaction and disable the EP */
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
}
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
}
/* Handle Incomplete ISO OUT Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
{
RegVal = USBx_OUTEP(epnum)->DOEPCTL;
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U)))
{
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
break;
}
}
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
/* Handle Connection event Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ConnectCallback(hpcd);
#else
HAL_PCD_ConnectCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
}
/* Handle Disconnection event Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
{
RegVal = hpcd->Instance->GOTGINT;
if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DisconnectCallback(hpcd);
#else
HAL_PCD_DisconnectCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
hpcd->Instance->GOTGINT |= RegVal;
}
}
}
/**
* @brief Handles PCD Wakeup interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd)
{
/* Clear EXTI pending Bit */
__HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG();
}
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
/**
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
uint16_t store_ep[8];
uint8_t i;
if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
return;
}
if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
return;
}
if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
return;
}
if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
return;
}
if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
return;
}
if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
{
/* WA: To Clear Wakeup flag if raised with suspend signal */
/* Store Endpoint registers */
for (i = 0U; i < 8U; i++)
{
store_ep[i] = PCD_GET_ENDPOINT(hpcd->Instance, i);
}
/* FORCE RESET */
hpcd->Instance->CNTR |= (uint16_t)(USB_CNTR_FRES);
/* CLEAR RESET */
hpcd->Instance->CNTR &= (uint16_t)(~USB_CNTR_FRES);
/* wait for reset flag in ISTR */
while ((hpcd->Instance->ISTR & USB_ISTR_RESET) == 0U)
{
}
/* Clear Reset Flag */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
/* Restore Registre */
for (i = 0U; i < 8U; i++)
{
PCD_SET_ENDPOINT(hpcd->Instance, i, store_ep[i]);
}
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
}
if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
}
if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
return;
}
}
/**
* @brief Handles PCD Wakeup interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd)
{
/* Clear EXTI pending Bit */
__HAL_USB_WAKEUP_EXTI_CLEAR_FLAG();
}
#endif /* defined (USB) */
/**
* @brief Data OUT stage callback.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Data IN stage callback
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DataInStageCallback could be implemented in the user file
*/
}
/**
* @brief Setup stage callback
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SetupStageCallback could be implemented in the user file
*/
}
/**
* @brief USB Start Of Frame callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SOFCallback could be implemented in the user file
*/
}
/**
* @brief USB Reset callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ResetCallback could be implemented in the user file
*/
}
/**
* @brief Suspend event callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SuspendCallback could be implemented in the user file
*/
}
/**
* @brief Resume event callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ResumeCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO OUT callback.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO IN callback.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
*/
}
/**
* @brief Connection event callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ConnectCallback could be implemented in the user file
*/
}
/**
* @brief Disconnection event callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DisconnectCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the PCD data
transfers.
@endverbatim
* @{
*/
/**
* @brief Connect the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
#if defined (USB)
HAL_PCDEx_SetConnectionState(hpcd, 1U);
#endif /* defined (USB) */
(void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Disconnect the USB device.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
#if defined (USB)
HAL_PCDEx_SetConnectionState(hpcd, 0U);
#endif /* defined (USB) */
(void)USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Set the USB Device address.
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
__HAL_LOCK(hpcd);
hpcd->USB_Address = address;
(void)USB_SetDevAddress(hpcd->Instance, address);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Open and configure an endpoint.
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @param ep_mps endpoint max packet size
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
ep->num = ep_addr & EP_ADDR_MSK;
ep->maxpacket = ep_mps;
ep->type = ep_type;
#if defined (USB_OTG_FS)
if (ep->is_in != 0U)
{
/* Assign a Tx FIFO */
ep->tx_fifo_num = ep->num;
}
#endif /* defined (USB_OTG_FS) */
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
{
ep->data_pid_start = 0U;
}
__HAL_LOCK(hpcd);
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
return ret;
}
/**
* @brief Deactivate an endpoint.
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Receive an amount of data.
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 0U;
ep->num = ep_addr & EP_ADDR_MSK;
(void)USB_EPStartXfer(hpcd->Instance, ep);
return HAL_OK;
}
/**
* @brief Get Received Data Size
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval Data Size
*/
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
}
/**
* @brief Send an amount of data
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
#if defined (USB)
ep->xfer_fill_db = 1U;
ep->xfer_len_db = len;
#endif /* defined (USB) */
ep->xfer_count = 0U;
ep->is_in = 1U;
ep->num = ep_addr & EP_ADDR_MSK;
(void)USB_EPStartXfer(hpcd->Instance, ep);
return HAL_OK;
}
/**
* @brief Set a STALL condition over an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
{
return HAL_ERROR;
}
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
ep->is_in = 0U;
}
ep->is_stall = 1U;
ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_EPSetStall(hpcd->Instance, ep);
if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
}
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Clear a STALL condition over in an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
{
return HAL_ERROR;
}
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
ep->is_stall = 0U;
ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_EPClearStall(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Abort an USB EP transaction.
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
HAL_StatusTypeDef ret;
PCD_EPTypeDef *ep;
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
}
/* Stop Xfer */
ret = USB_EPStopXfer(hpcd->Instance, ep);
return ret;
}
/**
* @brief Flush an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
__HAL_LOCK(hpcd);
if ((ep_addr & 0x80U) == 0x80U)
{
(void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
}
else
{
(void)USB_FlushRxFifo(hpcd->Instance);
}
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Activate remote wakeup signalling
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
return (USB_ActivateRemoteWakeup(hpcd->Instance));
}
/**
* @brief De-activate remote wakeup signalling.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
return (USB_DeActivateRemoteWakeup(hpcd->Instance));
}
/**
* @}
*/
/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the PCD handle state.
* @param hpcd PCD handle
* @retval HAL state
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd)
{
return hpcd->State;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup PCD_Private_Functions
* @{
*/
#if defined (USB_OTG_FS)
/**
* @brief Check FIFO for the next packet to be loaded.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
USB_OTG_EPTypeDef *ep;
uint32_t len;
uint32_t len32b;
uint32_t fifoemptymsk;
ep = &hpcd->IN_ep[epnum];
if (ep->xfer_count > ep->xfer_len)
{
return HAL_ERROR;
}
len = ep->xfer_len - ep->xfer_count;
if (len > ep->maxpacket)
{
len = ep->maxpacket;
}
len32b = (len + 3U) / 4U;
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
if (len > ep->maxpacket)
{
len = ep->maxpacket;
}
len32b = (len + 3U) / 4U;
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len);
ep->xfer_buff += len;
ep->xfer_count += len;
}
if (ep->xfer_len <= ep->xfer_count)
{
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
}
return HAL_OK;
}
/**
* @brief process EP OUT transfer complete interrupt.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (gSNPSiD == USB_OTG_CORE_ID_310A)
{
/* StupPktRcvd = 1 this is a setup packet */
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
else
{
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
return HAL_OK;
}
/**
* @brief process EP OUT setup packet received interrupt.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
/* Inform the upper layer that a setup packet is available */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return HAL_OK;
}
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
/**
* @brief This function handles PCD Endpoint interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
PCD_EPTypeDef *ep;
uint16_t count;
uint16_t wIstr;
uint16_t wEPVal;
uint16_t TxPctSize;
uint8_t epindex;
#if (USE_USB_DOUBLE_BUFFER != 1U)
count = 0U;
#endif /* USE_USB_DOUBLE_BUFFER */
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
{
wIstr = hpcd->Instance->ISTR;
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
if (epindex == 0U)
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U)
{
/* DIR = 0 */
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
ep = &hpcd->IN_ep[0];
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
ep->xfer_buff += ep->xfer_count;
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, 0U);
#else
HAL_PCD_DataInStageCallback(hpcd, 0U);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
{
hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
hpcd->USB_Address = 0U;
}
}
else
{
/* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
if ((wEPVal & USB_EP_SETUP) != 0U)
{
/* Get SETUP Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
ep->pmaadress, (uint16_t)ep->xfer_count);
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
/* Process SETUP Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
/* Get Control Data OUT Packet */
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
ep->pmaadress, (uint16_t)ep->xfer_count);
ep->xfer_buff += ep->xfer_count;
/* Process Control Data OUT Packet */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, 0U);
#else
HAL_PCD_DataOutStageCallback(hpcd, 0U);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
{
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
}
}
}
}
else
{
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
ep = &hpcd->OUT_ep[epindex];
/* OUT Single Buffering */
if (ep->doublebuffer == 0U)
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
}
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* manage double buffer bulk out */
if (ep->type == EP_TYPE_BULK)
{
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
}
else /* manage double buffer iso out */
{
/* free EP OUT Buffer */
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
{
/* read from endpoint BUF0Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
}
}
else
{
/* read from endpoint BUF1Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
}
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
ep->xfer_buff += count;
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
{
/* RX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep);
}
}
if ((wEPVal & USB_EP_CTR_TX) != 0U)
{
ep = &hpcd->IN_ep[epindex];
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
if (ep->type == EP_TYPE_ISOC)
{
ep->xfer_len = 0U;
#if (USE_USB_DOUBLE_BUFFER == 1U)
if (ep->doublebuffer != 0U)
{
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
}
else
{
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
}
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Manage Single Buffer Transaction */
if ((wEPVal & USB_EP_KIND) == 0U)
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len > TxPctSize)
{
ep->xfer_len -= TxPctSize;
}
else
{
ep->xfer_len = 0U;
}
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
{
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Transfer is not yet Done */
ep->xfer_buff += TxPctSize;
ep->xfer_count += TxPctSize;
(void)USB_EPStartXfer(hpcd->Instance, ep);
}
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
}
}
}
}
return HAL_OK;
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
/**
* @brief Manage double buffer bulk out transaction from ISR
* @param hpcd PCD handle
* @param ep current endpoint handle
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
uint16_t count;
/* Manage Buffer0 OUT */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
/* Get count of received Data on buffer0 */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len >= count)
{
ep->xfer_len -= count;
}
else
{
ep->xfer_len = 0U;
}
if (ep->xfer_len == 0U)
{
/* set NAK to OUT endpoint since double buffer is enabled */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
/* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
}
}
/* Manage Buffer 1 DTOG_RX=0 */
else
{
/* Get count of received data */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len >= count)
{
ep->xfer_len -= count;
}
else
{
ep->xfer_len = 0U;
}
if (ep->xfer_len == 0U)
{
/* set NAK on the current endpoint */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
/*Need to FreeUser Buffer*/
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
}
return count;
}
/**
* @brief Manage double buffer bulk IN transaction from ISR
* @param hpcd PCD handle
* @param ep current endpoint handle
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
uint32_t len;
uint16_t TxPctSize;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len > TxPctSize)
{
ep->xfer_len -= TxPctSize;
}
else
{
ep->xfer_len = 0U;
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
ep->xfer_buff += TxPctSize;
ep->xfer_count += TxPctSize;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len_db -= len;
}
else if (ep->xfer_len_db == 0U)
{
len = TxPctSize;
ep->xfer_fill_db = 0U;
}
else
{
ep->xfer_fill_db = 0U;
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
}
/* Write remaining Data to Buffer */
/* Set the Double buffer counter for pma buffer1 */
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
/* Copy user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
}
}
}
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len >= TxPctSize)
{
ep->xfer_len -= TxPctSize;
}
else
{
ep->xfer_len = 0U;
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
ep->xfer_buff += TxPctSize;
ep->xfer_count += TxPctSize;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len_db -= len;
}
else if (ep->xfer_len_db == 0U)
{
len = TxPctSize;
ep->xfer_fill_db = 0U;
}
else
{
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
ep->xfer_fill_db = 0;
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
/* Copy the user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
}
}
}
/*enable endpoint IN*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
return HAL_OK;
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
#endif /* defined (USB) */
/**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

243
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/**
******************************************************************************
* @file stm32f1xx_hal_pcd_ex.c
* @author MCD Application Team
* @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Extended features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined (USB) || defined (USB_OTG_FS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Update FIFO configuration
@endverbatim
* @{
*/
#if defined (USB_OTG_FS)
/**
* @brief Set Tx FIFO
* @param hpcd PCD handle
* @param fifo The number of Tx fifo
* @param size Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t i;
uint32_t Tx_Offset;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txm can use the space allocated for Txn.
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txn should be configured with the minimum space of 16 words
The FIFO is used optimally when used TxFIFOs are allocated in the top
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
Tx_Offset = hpcd->Instance->GRXFSIZ;
if (fifo == 0U)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0U; i < (fifo - 1U); i++)
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
}
return HAL_OK;
}
/**
* @brief Set Rx FIFO
* @param hpcd PCD handle
* @param size Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
hpcd->Instance->GRXFSIZ = size;
return HAL_OK;
}
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
/**
* @brief Configure PMA for EP
* @param hpcd Device instance
* @param ep_addr endpoint address
* @param ep_kind endpoint Kind
* USB_SNG_BUF: Single Buffer used
* USB_DBL_BUF: Double Buffer used
* @param pmaadress: EP address in The PMA: In case of single buffer endpoint
* this parameter is 16-bit value providing the address
* in PMA allocated to endpoint.
* In case of double buffer endpoint this parameter
* is a 32-bit value providing the endpoint buffer 0 address
* in the LSB part of 32-bit value and endpoint buffer 1 address
* in the MSB part of 32-bit value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
PCD_EPTypeDef *ep;
/* initialize ep structure*/
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
}
/* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF)
{
/* Single Buffer */
ep->doublebuffer = 0U;
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
ep->doublebuffer = 1U;
/* Configure the PMA */
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
}
/**
* @brief Software Device Connection,
* this function is not required by USB OTG FS peripheral, it is used
* only by USB Device FS peripheral.
* @param hpcd PCD handle
* @param state connection state (0 : disconnected / 1: connected)
* @retval None
*/
__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(state);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCDEx_SetConnectionState could be implemented in the user file
*/
}
#endif /* defined (USB) */
/**
* @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**
* @brief Send BatteryCharging message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_BCD_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

3215
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c Normal file
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/**
******************************************************************************
* @file stm32f1xx_hal_sd.c
* @author MCD Application Team
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver implements a high level communication layer for read and write from/to
this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
the user in HAL_SD_MspInit() function (MSP layer).
Basically, the MSP layer configuration should be the same as we provide in the
examples.
You can easily tailor this configuration according to hardware resources.
[..]
This driver is a generic layered driver for SDIO memories which uses the HAL
SDIO driver functions to interface with SD and uSD cards devices.
It is used as follows:
(#)Initialize the SDIO low level resources by implementing the HAL_SD_MspInit() API:
(##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
(##) SDIO pins configuration for SD card
(+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
and HAL_SD_WriteBlocks_DMA() APIs).
(+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
(+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
(##) NVIC configuration if you need to use interrupt process when using DMA transfer.
(+++) Configure the SDIO and DMA interrupt priorities using functions
HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
(+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
(+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
and __HAL_SD_DISABLE_IT() inside the communication process.
(+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
and __HAL_SD_CLEAR_IT()
(##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
and HAL_SD_WriteBlocks_IT() APIs).
(+++) Configure the SDIO interrupt priorities using function HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
(+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
and __HAL_SD_DISABLE_IT() inside the communication process.
(+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
and __HAL_SD_CLEAR_IT()
(#) At this stage, you can perform SD read/write/erase operations after SD card initialization
*** SD Card Initialization and configuration ***
================================================
[..]
To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
SDIO Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
(#) Apply the SD Card initialization process at 400KHz and check the SD Card
type (Standard Capacity or High Capacity). You can change or adapt this
frequency by adjusting the "ClockDiv" field.
The SD Card frequency (SDIO_CK) is computed as follows:
SDIO_CK = SDIOCLK / (ClockDiv + 2)
In initialization mode and according to the SD Card standard,
make sure that the SDIO_CK frequency doesn't exceed 400KHz.
This phase of initialization is done through SDIO_Init() and
SDIO_PowerState_ON() SDIO low level APIs.
(#) Initialize the SD card. The API used is HAL_SD_InitCard().
This phase allows the card initialization and identification
and check the SD Card type (Standard Capacity or High Capacity)
The initialization flow is compatible with SD standard.
This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
of plug-off plug-in.
(#) Configure the SD Card Data transfer frequency. You can change or adapt this
frequency by adjusting the "ClockDiv" field.
In transfer mode and according to the SD Card standard, make sure that the
SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
To be able to use a frequency higher than 24MHz, you should use the SDIO
peripheral in bypass mode. Refer to the corresponding reference manual
for more details.
(#) Select the corresponding SD Card according to the address read with the step 2.
(#) Configure the SD Card in wide bus mode: 4-bits data.
*** SD Card Read operation ***
==============================
[..]
(+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
(+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the DMA transfer process through the SD Rx interrupt event.
(+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the IT transfer process through the SD Rx interrupt event.
*** SD Card Write operation ***
===============================
[..]
(+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
(+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the DMA transfer process through the SD Tx interrupt event.
(+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_SD_GetCardState() function for SD card state.
You could also check the IT transfer process through the SD Tx interrupt event.
*** SD card status ***
======================
[..]
(+) The SD Status contains status bits that are related to the SD Memory
Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
*** SD card information ***
===========================
[..]
(+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
It returns useful information about the SD card such as block size, card type,
block number ...
*** SD card CSD register ***
============================
(+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
Some of the CSD parameters are useful for card initialization and identification.
*** SD card CID register ***
============================
(+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
Some of the CSD parameters are useful for card initialization and identification.
*** SD HAL driver macros list ***
==================================
[..]
Below the list of most used macros in SD HAL driver.
(+) __HAL_SD_ENABLE : Enable the SD device
(+) __HAL_SD_DISABLE : Disable the SD device
(+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
(+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer
(+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
(+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
(+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
(+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
(@) You can refer to the SD HAL driver header file for more useful macros
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_SD_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) MspInitCallback : SD MspInit.
(+) MspDeInitCallback : SD MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) MspInitCallback : SD MspInit.
(+) MspDeInitCallback : SD MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_SD_Init
and HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_SD_RegisterCallback before calling HAL_SD_DeInit
or HAL_SD_Init function.
When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
#if defined(SDIO)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup SD
* @{
*/
#ifdef HAL_SD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup SD_Private_Defines
* @{
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SD_Private_Functions SD Private Functions
* @{
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
static void SD_PowerOFF(SD_HandleTypeDef *hsd);
static void SD_Write_IT(SD_HandleTypeDef *hsd);
static void SD_Read_IT(SD_HandleTypeDef *hsd);
static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SD_DMAError(DMA_HandleTypeDef *hdma);
static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SD_Exported_Functions
* @{
*/
/** @addtogroup SD_Exported_Functions_Group1
* @brief Initialization and de-initialization functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize the SD
card device to be ready for use.
@endverbatim
* @{
*/
/**
* @brief Initializes the SD according to the specified parameters in the
SD_HandleTypeDef and create the associated handle.
* @param hsd: Pointer to the SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
{
/* Check the SD handle allocation */
if(hsd == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge));
assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass));
assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));
if(hsd->State == HAL_SD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_SD_STATE_RESET only */
hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
hsd->ErrorCallback = HAL_SD_ErrorCallback;
hsd->AbortCpltCallback = HAL_SD_AbortCallback;
if(hsd->MspInitCallback == NULL)
{
hsd->MspInitCallback = HAL_SD_MspInit;
}
/* Init the low level hardware */
hsd->MspInitCallback(hsd);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SD_MspInit(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
hsd->State = HAL_SD_STATE_BUSY;
/* Initialize the Card parameters */
if (HAL_SD_InitCard(hsd) != HAL_OK)
{
return HAL_ERROR;
}
/* Initialize the error code */
hsd->ErrorCode = HAL_SD_ERROR_NONE;
/* Initialize the SD operation */
hsd->Context = SD_CONTEXT_NONE;
/* Initialize the SD state */
hsd->State = HAL_SD_STATE_READY;
return HAL_OK;
}
/**
* @brief Initializes the SD Card.
* @param hsd: Pointer to SD handle
* @note This function initializes the SD card. It could be used when a card
re-initialization is needed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
uint32_t errorstate;
SD_InitTypeDef Init;
/* Default SDIO peripheral configuration for SD card initialization */
Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
Init.BusWide = SDIO_BUS_WIDE_1B;
Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
Init.ClockDiv = SDIO_INIT_CLK_DIV;
/* Initialize SDIO peripheral interface with default configuration */
SDIO_Init(hsd->Instance, Init);
/* Disable SDIO Clock */
__HAL_SD_DISABLE(hsd);
/* Set Power State to ON */
(void)SDIO_PowerState_ON(hsd->Instance);
/* Enable SDIO Clock */
__HAL_SD_ENABLE(hsd);
/* Required power up waiting time before starting the SD initialization sequence */
HAL_Delay(2);
/* Identify card operating voltage */
errorstate = SD_PowerON(hsd);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
/* Card initialization */
errorstate = SD_InitCard(hsd);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->State = HAL_SD_STATE_READY;
hsd->ErrorCode |= errorstate;
return HAL_ERROR;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief De-Initializes the SD card.
* @param hsd: Pointer to SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
{
/* Check the SD handle allocation */
if(hsd == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
hsd->State = HAL_SD_STATE_BUSY;
/* Set SD power state to off */
SD_PowerOFF(hsd);
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
if(hsd->MspDeInitCallback == NULL)
{
hsd->MspDeInitCallback = HAL_SD_MspDeInit;
}
/* DeInit the low level hardware */
hsd->MspDeInitCallback(hsd);
#else
/* De-Initialize the MSP layer */
HAL_SD_MspDeInit(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initializes the SD MSP.
* @param hsd: Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_MspInit could be implemented in the user file
*/
}
/**
* @brief De-Initialize SD MSP.
* @param hsd: Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @addtogroup SD_Exported_Functions_Group2
* @brief Data transfer functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to manage the data
transfer from/to SD card.
@endverbatim
* @{
*/
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
* @param hsd: Pointer to SD handle
* @param pData: pointer to the buffer that will contain the received data
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of SD blocks to read
* @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count, data, dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hsd->State = HAL_SD_STATE_BUSY;
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hsd->Instance, &config);
/* Read block(s) in polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
/* Poll on SDIO flags */
dataremaining = config.DataLength;
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
{
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U))
{
/* Read data from SDIO Rx FIFO */
for(count = 0U; count < 8U; count++)
{
data = SDIO_ReadFIFO(hsd->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
tempbuff++;
dataremaining--;
}
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
hsd->State= HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
/* Send stop transmission command in case of multiblock read */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
}
/* Get error state */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Empty FIFO if there is still any data */
while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U))
{
data = SDIO_ReadFIFO(hsd->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
tempbuff++;
dataremaining--;
*tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
tempbuff++;
dataremaining--;
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
hsd->State= HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
hsd->State = HAL_SD_STATE_READY;
return HAL_OK;
}
else
{
hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
return HAL_ERROR;
}
}
/**
* @brief Allows to write block(s) to a specified address in a card. The Data
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
* @param hsd: Pointer to SD handle
* @param pData: pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of SD blocks to write
* @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count, data, dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hsd->State = HAL_SD_STATE_BUSY;
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hsd->Instance, &config);
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
/* Write block(s) in polling mode */
dataremaining = config.DataLength;
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
{
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U))
{
/* Write data to SDIO Tx FIFO */
for(count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tempbuff);
tempbuff++;
dataremaining--;
data |= ((uint32_t)(*tempbuff) << 8U);
tempbuff++;
dataremaining--;
data |= ((uint32_t)(*tempbuff) << 16U);
tempbuff++;
dataremaining--;
data |= ((uint32_t)(*tempbuff) << 24U);
tempbuff++;
dataremaining--;
(void)SDIO_WriteFIFO(hsd->Instance, &data);
}
}
if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_TIMEOUT;
}
}
/* Send stop transmission command in case of multiblock write */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
}
}
/* Get error state */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
hsd->State = HAL_SD_STATE_READY;
return HAL_OK;
}
else
{
hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
return HAL_ERROR;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
* @note You could also check the IT transfer process through the SD Rx
* interrupt event.
* @param hsd: Pointer to SD handle
* @param pData: Pointer to the buffer that will contain the received data
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hsd->State = HAL_SD_STATE_BUSY;
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
hsd->pRxBuffPtr = pData;
hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hsd->Instance, &config);
/* Read Blocks in IT mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Writes block(s) to a specified address in a card. The Data transfer
* is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
* @note You could also check the IT transfer process through the SD Tx
* interrupt event.
* @param hsd: Pointer to SD handle
* @param pData: Pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hsd->State = HAL_SD_STATE_BUSY;
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
hsd->pTxBuffPtr = pData;
hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
/* Enable transfer interrupts */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hsd->Instance, &config);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
* @note You could also check the DMA transfer process through the SD Rx
* interrupt event.
* @param hsd: Pointer SD handle
* @param pData: Pointer to the buffer that will contain the received data
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hsd->State = HAL_SD_STATE_BUSY;
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
/* Set the DMA transfer complete callback */
hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
/* Set the DMA error callback */
hsd->hdmarx->XferErrorCallback = SD_DMAError;
/* Set the DMA Abort callback */
hsd->hdmarx->XferAbortCallback = NULL;
/* Force DMA Direction */
hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
MODIFY_REG(hsd->hdmarx->Instance->CCR, DMA_CCR_DIR, hsd->hdmarx->Init.Direction);
/* Enable the DMA Channel */
if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
{
__HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DMA;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
else
{
/* Enable SD DMA transfer */
__HAL_SD_DMA_ENABLE(hsd);
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hsd->Instance, &config);
/* Read Blocks in DMA mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Writes block(s) to a specified address in a card. The Data transfer
* is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
* @note You could also check the DMA transfer process through the SD Tx
* interrupt event.
* @param hsd: Pointer to SD handle
* @param pData: Pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(NULL == pData)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hsd->State = HAL_SD_STATE_BUSY;
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
/* Enable SD Error interrupts */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
/* Set the DMA transfer complete callback */
hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
/* Set the DMA error callback */
hsd->hdmatx->XferErrorCallback = SD_DMAError;
/* Set the DMA Abort callback */
hsd->hdmatx->XferAbortCallback = NULL;
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
add *= 512U;
}
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
}
else
{
hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
}
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
/* Enable SDIO DMA transfer */
__HAL_SD_DMA_ENABLE(hsd);
/* Force DMA Direction */
hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
MODIFY_REG(hsd->hdmatx->Instance->CCR, DMA_CCR_DIR, hsd->hdmatx->Init.Direction);
/* Enable the DMA Channel */
if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
{
__HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_DMA;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
return HAL_ERROR;
}
else
{
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hsd->Instance, &config);
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Erases the specified memory area of the given SD card.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
* @param hsd: Pointer to SD handle
* @param BlockStartAdd: Start Block address
* @param BlockEndAdd: End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
uint32_t errorstate;
uint32_t start_add = BlockStartAdd;
uint32_t end_add = BlockEndAdd;
if(hsd->State == HAL_SD_STATE_READY)
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
if(end_add < start_add)
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
return HAL_ERROR;
}
if(end_add > (hsd->SdCard.LogBlockNbr))
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
hsd->State = HAL_SD_STATE_BUSY;
/* Check if the card command class supports erase command */
if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Get start and end block for high capacity cards */
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
{
start_add *= 512U;
end_add *= 512U;
}
/* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD32 SD_ERASE_GRP_START with argument as addr */
errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
/* Send CMD33 SD_ERASE_GRP_END with argument as addr */
errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
}
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
hsd->State = HAL_SD_STATE_READY;
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief This function handles SD card interrupt request.
* @param hsd: Pointer to SD handle
* @retval None
*/
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
{
uint32_t errorstate;
uint32_t context = hsd->Context;
/* Check for SDIO interrupt flags */
if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
SD_Read_IT(hsd);
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) != RESET)
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_TXFIFOHE |\
SDIO_IT_RXFIFOHF);
hsd->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN);
if((context & SD_CONTEXT_IT) != 0U)
{
if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->RxCpltCallback(hsd);
#else
HAL_SD_RxCpltCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
else
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
#else
HAL_SD_TxCpltCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
else if((context & SD_CONTEXT_DMA) != 0U)
{
if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
{
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the SD DCTRL register */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
hsd->State = HAL_SD_STATE_READY;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->TxCpltCallback(hsd);
#else
HAL_SD_TxCpltCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
else
{
/* Nothing to do */
}
}
else if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
{
SD_Write_IT(hsd);
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
}
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
}
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
}
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR) != RESET)
{
hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
}
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR);
/* Disable all interrupts */
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
if((context & SD_CONTEXT_IT) != 0U)
{
/* Set the SD state to ready to be able to start again the process */
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
else if((context & SD_CONTEXT_DMA) != 0U)
{
/* Abort the SD DMA channel */
if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
/* Set the DMA Tx abort callback */
hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
/* Abort DMA in IT mode */
if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
{
SD_DMATxAbort(hsd->hdmatx);
}
}
else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
/* Set the DMA Rx abort callback */
hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
/* Abort DMA in IT mode */
if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
{
SD_DMARxAbort(hsd->hdmarx);
}
}
else
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->AbortCpltCallback(hsd);
#else
HAL_SD_AbortCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
else
{
/* Nothing to do */
}
}
else
{
/* Nothing to do */
}
}
/**
* @brief return the SD state
* @param hsd: Pointer to sd handle
* @retval HAL state
*/
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
{
return hsd->State;
}
/**
* @brief Return the SD error code
* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval SD Error Code
*/
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
{
return hsd->ErrorCode;
}
/**
* @brief Tx Transfer completed callbacks
* @param hsd: Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_TxCpltCallback can be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks
* @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_RxCpltCallback can be implemented in the user file
*/
}
/**
* @brief SD error callbacks
* @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_ErrorCallback can be implemented in the user file
*/
}
/**
* @brief SD Abort callbacks
* @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_AbortCallback can be implemented in the user file
*/
}
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User SD Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hsd : SD handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
* @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
* @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
* @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
* @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
* @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hsd);
if(hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
{
case HAL_SD_TX_CPLT_CB_ID :
hsd->TxCpltCallback = pCallback;
break;
case HAL_SD_RX_CPLT_CB_ID :
hsd->RxCpltCallback = pCallback;
break;
case HAL_SD_ERROR_CB_ID :
hsd->ErrorCallback = pCallback;
break;
case HAL_SD_ABORT_CB_ID :
hsd->AbortCpltCallback = pCallback;
break;
case HAL_SD_MSP_INIT_CB_ID :
hsd->MspInitCallback = pCallback;
break;
case HAL_SD_MSP_DEINIT_CB_ID :
hsd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_SD_MSP_INIT_CB_ID :
hsd->MspInitCallback = pCallback;
break;
case HAL_SD_MSP_DEINIT_CB_ID :
hsd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hsd);
return status;
}
/**
* @brief Unregister a User SD Callback
* SD Callback is redirected to the weak (surcharged) predefined callback
* @param hsd : SD handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID
* @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID
* @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID
* @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID
* @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID
* @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hsd);
if(hsd->State == HAL_SD_STATE_READY)
{
switch (CallbackID)
{
case HAL_SD_TX_CPLT_CB_ID :
hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
break;
case HAL_SD_RX_CPLT_CB_ID :
hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
break;
case HAL_SD_ERROR_CB_ID :
hsd->ErrorCallback = HAL_SD_ErrorCallback;
break;
case HAL_SD_ABORT_CB_ID :
hsd->AbortCpltCallback = HAL_SD_AbortCallback;
break;
case HAL_SD_MSP_INIT_CB_ID :
hsd->MspInitCallback = HAL_SD_MspInit;
break;
case HAL_SD_MSP_DEINIT_CB_ID :
hsd->MspDeInitCallback = HAL_SD_MspDeInit;
break;
default :
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hsd->State == HAL_SD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_SD_MSP_INIT_CB_ID :
hsd->MspInitCallback = HAL_SD_MspInit;
break;
case HAL_SD_MSP_DEINIT_CB_ID :
hsd->MspDeInitCallback = HAL_SD_MspDeInit;
break;
default :
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hsd);
return status;
}
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SD_Exported_Functions_Group3
* @brief management functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the SD card
operations and get the related information
@endverbatim
* @{
*/
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
* @param hsd: Pointer to SD handle
* @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
* contains all CID register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
{
pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
pCID->Reserved2 = 1U;
return HAL_OK;
}
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
* @param hsd: Pointer to SD handle
* @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
{
pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
pCSD->Reserved2 = 0U; /*!< Reserved */
if(hsd->SdCard.CardType == CARD_SDSC)
{
pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
hsd->SdCard.LogBlockSize = 512U;
}
else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
{
/* Byte 7 */
pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
hsd->SdCard.BlockSize = 512U;
hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
}
else
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
hsd->State = HAL_SD_STATE_READY;
return HAL_ERROR;
}
pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
pCSD->Reserved3 = 0;
pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
pCSD->Reserved4 = 1;
return HAL_OK;
}
/**
* @brief Gets the SD status info.
* @param hsd: Pointer to SD handle
* @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
* will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
{
uint32_t sd_status[16];
uint32_t errorstate;
HAL_StatusTypeDef status = HAL_OK;
errorstate = SD_SendSDStatus(hsd, sd_status);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
status = HAL_ERROR;
}
else
{
pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) |
((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode = errorstate;
hsd->State = HAL_SD_STATE_READY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Gets the SD card info.
* @param hsd: Pointer to SD handle
* @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
* will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
{
pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType);
pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion);
pCardInfo->Class = (uint32_t)(hsd->SdCard.Class);
pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd);
pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr);
pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
return HAL_OK;
}
/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
* @param hsd: Pointer to SD handle
* @param WideMode: Specifies the SD card wide bus mode
* This parameter can be one of the following values:
* @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
* @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
* @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
{
SDIO_InitTypeDef Init;
uint32_t errorstate;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_SDIO_BUS_WIDE(WideMode));
/* Change State */
hsd->State = HAL_SD_STATE_BUSY;
if(hsd->SdCard.CardType != CARD_SECURED)
{
if(WideMode == SDIO_BUS_WIDE_8B)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
else if(WideMode == SDIO_BUS_WIDE_4B)
{
errorstate = SD_WideBus_Enable(hsd);
hsd->ErrorCode |= errorstate;
}
else if(WideMode == SDIO_BUS_WIDE_1B)
{
errorstate = SD_WideBus_Disable(hsd);
hsd->ErrorCode |= errorstate;
}
else
{
/* WideMode is not a valid argument*/
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
}
}
else
{
/* MMC Card does not support this feature */
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->State = HAL_SD_STATE_READY;
status = HAL_ERROR;
}
else
{
/* Configure the SDIO peripheral */
Init.ClockEdge = hsd->Init.ClockEdge;
Init.ClockBypass = hsd->Init.ClockBypass;
Init.ClockPowerSave = hsd->Init.ClockPowerSave;
Init.BusWide = WideMode;
Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
Init.ClockDiv = hsd->Init.ClockDiv;
(void)SDIO_Init(hsd->Instance, Init);
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
status = HAL_ERROR;
}
/* Change State */
hsd->State = HAL_SD_STATE_READY;
return status;
}
/**
* @brief Gets the current sd card data state.
* @param hsd: pointer to SD handle
* @retval Card state
*/
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
{
uint32_t cardstate;
uint32_t errorstate;
uint32_t resp1 = 0;
errorstate = SD_SendStatus(hsd, &resp1);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
}
cardstate = ((resp1 >> 9U) & 0x0FU);
return (HAL_SD_CardStateTypeDef)cardstate;
}
/**
* @brief Abort the current transfer and disable the SD.
* @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypeDef CardState;
uint32_t context = hsd->Context;
/* DIsable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
if ((context & SD_CONTEXT_DMA) != 0U)
{
/* Disable the SD DMA request */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
/* Abort the SD DMA Tx channel */
if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK)
{
hsd->ErrorCode |= HAL_SD_ERROR_DMA;
}
}
/* Abort the SD DMA Rx channel */
else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK)
{
hsd->ErrorCode |= HAL_SD_ERROR_DMA;
}
}
else
{
/* Nothing to do */
}
}
hsd->State = HAL_SD_STATE_READY;
/* Initialize the SD operation */
hsd->Context = SD_CONTEXT_NONE;
CardState = HAL_SD_GetCardState(hsd);
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
}
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Abort the current transfer and disable the SD (IT mode).
* @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
{
HAL_SD_CardStateTypeDef CardState;
uint32_t context = hsd->Context;
/* Disable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
if ((context & SD_CONTEXT_DMA) != 0U)
{
/* Disable the SD DMA request */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
/* Abort the SD DMA Tx channel */
if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
{
hsd->hdmatx = NULL;
}
}
/* Abort the SD DMA Rx channel */
else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
{
hsd->hdmarx = NULL;
}
}
else
{
/* Nothing to do */
}
}
/* No transfer ongoing on both DMA channels*/
else
{
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
}
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->AbortCpltCallback(hsd);
#else
HAL_SD_AbortCallback(hsd);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/* Private function ----------------------------------------------------------*/
/** @addtogroup SD_Private_Functions
* @{
*/
/**
* @brief DMA SD transmit process complete callback
* @param hdma: DMA handle
* @retval None
*/
static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
/* Enable DATAEND Interrupt */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
}
/**
* @brief DMA SD receive process complete callback
* @param hdma: DMA handle
* @retval None
*/
static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
uint32_t errorstate;
/* Send stop command in multiblock write */
if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= errorstate;
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
#endif
}
}
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the SD DCTRL register */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->RxCpltCallback(hsd);
#else
HAL_SD_RxCpltCallback(hsd);
#endif
}
/**
* @brief DMA SD communication error callback
* @param hdma: DMA handle
* @retval None
*/
static void SD_DMAError(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
HAL_SD_CardStateTypeDef CardState;
uint32_t RxErrorCode, TxErrorCode;
RxErrorCode = hsd->hdmarx->ErrorCode;
TxErrorCode = hsd->hdmatx->ErrorCode;
if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
{
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
/* Disable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
hsd->ErrorCode |= HAL_SD_ERROR_DMA;
CardState = HAL_SD_GetCardState(hsd);
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
}
hsd->State= HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
}
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
#endif
}
/**
* @brief DMA SD Tx Abort callback
* @param hdma: DMA handle
* @retval None
*/
static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
HAL_SD_CardStateTypeDef CardState;
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
}
if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
{
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->AbortCpltCallback(hsd);
#else
HAL_SD_AbortCallback(hsd);
#endif
}
else
{
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
#endif
}
}
/**
* @brief DMA SD Rx Abort callback
* @param hdma: DMA handle
* @retval None
*/
static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
{
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
HAL_SD_CardStateTypeDef CardState;
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
CardState = HAL_SD_GetCardState(hsd);
hsd->State = HAL_SD_STATE_READY;
hsd->Context = SD_CONTEXT_NONE;
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
}
if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
{
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->AbortCpltCallback(hsd);
#else
HAL_SD_AbortCallback(hsd);
#endif
}
else
{
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
#endif
}
}
/**
* @brief Initializes the sd card.
* @param hsd: Pointer to SD handle
* @retval SD Card error state
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
{
HAL_SD_CardCSDTypeDef CSD;
uint32_t errorstate;
uint16_t sd_rca = 1U;
/* Check the power State */
if(SDIO_GetPowerState(hsd->Instance) == 0U)
{
/* Power off */
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
else
{
/* Get Card identification number data */
hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
}
}
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
}
if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Get the SD card RCA */
hsd->SdCard.RelCardAdd = sd_rca;
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
else
{
/* Get Card Specific Data */
hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
}
}
/* Get the Card Class */
hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
/* Get CSD parameters */
if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Configure SDIO peripheral interface */
(void)SDIO_Init(hsd->Instance, hsd->Init);
/* All cards are initialized */
return HAL_SD_ERROR_NONE;
}
/**
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores SD information that will be needed in future
* in the SD handle.
* @param hsd: Pointer to SD handle
* @retval error state
*/
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
{
__IO uint32_t count = 0U;
uint32_t response = 0U, validvoltage = 0U;
uint32_t errorstate;
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
errorstate = SDMMC_CmdOperCond(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->SdCard.CardVersion = CARD_V1_X;
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
}
else
{
hsd->SdCard.CardVersion = CARD_V2_X;
}
if( hsd->SdCard.CardVersion == CARD_V2_X)
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
if(errorstate != HAL_SD_ERROR_NONE)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
}
/* SD CARD */
/* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD41 */
errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
if(errorstate != HAL_SD_ERROR_NONE)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
/* Get command response */
response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
/* Get operating voltage*/
validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
count++;
}
if(count >= SDMMC_MAX_VOLT_TRIAL)
{
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
{
hsd->SdCard.CardType = CARD_SDHC_SDXC;
}
else
{
hsd->SdCard.CardType = CARD_SDSC;
}
return HAL_SD_ERROR_NONE;
}
/**
* @brief Turns the SDIO output signals off.
* @param hsd: Pointer to SD handle
* @retval None
*/
static void SD_PowerOFF(SD_HandleTypeDef *hsd)
{
/* Set Power State to OFF */
(void)SDIO_PowerState_OFF(hsd->Instance);
}
/**
* @brief Send Status info command.
* @param hsd: pointer to SD handle
* @param pSDstatus: Pointer to the buffer that will contain the SD card status
* SD Status register)
* @retval error state
*/
static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count;
uint32_t *pData = pSDstatus;
/* Check SD response */
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Set block size for card if it is not equal to current block size for card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
/* Send CMD55 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 64U;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hsd->Instance, &config);
/* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_NONE;
return errorstate;
}
/* Get status data */
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
{
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
for(count = 0U; count < 8U; count++)
{
*pData = SDIO_ReadFIFO(hsd->Instance);
pData++;
}
}
if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
return HAL_SD_ERROR_DATA_TIMEOUT;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
return HAL_SD_ERROR_DATA_CRC_FAIL;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
{
return HAL_SD_ERROR_RX_OVERRUN;
}
else
{
/* Nothing to do */
}
while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
{
*pData = SDIO_ReadFIFO(hsd->Instance);
pData++;
if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
/* Clear all the static status flags*/
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
return HAL_SD_ERROR_NONE;
}
/**
* @brief Returns the current card's status.
* @param hsd: Pointer to SD handle
* @param pCardStatus: pointer to the buffer that will contain the SD card
* status (Card Status register)
* @retval error state
*/
static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
{
uint32_t errorstate;
if(pCardStatus == NULL)
{
return HAL_SD_ERROR_PARAM;
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Get SD card status */
*pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
return HAL_SD_ERROR_NONE;
}
/**
* @brief Enables the SDIO wide bus mode.
* @param hsd: pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
{
uint32_t scr[2U] = {0U, 0U};
uint32_t errorstate;
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* If requested card supports wide bus operation */
if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA.*/
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
return HAL_SD_ERROR_NONE;
}
else
{
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
}
/**
* @brief Disables the SDIO wide bus mode.
* @param hsd: Pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
{
uint32_t scr[2U] = {0U, 0U};
uint32_t errorstate;
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* If requested card supports 1 bit mode operation */
if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
return HAL_SD_ERROR_NONE;
}
else
{
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
}
/**
* @brief Finds the SD card SCR register value.
* @param hsd: Pointer to SD handle
* @param pSCR: pointer to the buffer that will contain the SCR value
* @retval error state
*/
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t index = 0U;
uint32_t tempscr[2U] = {0U, 0U};
uint32_t *scr = pSCR;
/* Set Block Size To 8 Bytes */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 8U;
config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
config.DPSM = SDIO_DPSM_ENABLE;
(void)SDIO_ConfigData(hsd->Instance, &config);
/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
errorstate = SDMMC_CmdSendSCR(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT))
{
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
{
*(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
index++;
}
else if(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXACT))
{
break;
}
if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) || (__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR)))
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
return HAL_SD_ERROR_DATA_TIMEOUT;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
return HAL_SD_ERROR_DATA_CRC_FAIL;
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
return HAL_SD_ERROR_RX_OVERRUN;
}
else
{
/* No error flag set */
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
*scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
scr++;
*scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
}
return HAL_SD_ERROR_NONE;
}
/**
* @brief Wrap up reading in non-blocking mode.
* @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval None
*/
static void SD_Read_IT(SD_HandleTypeDef *hsd)
{
uint32_t count, data, dataremaining;
uint8_t* tmp;
tmp = hsd->pRxBuffPtr;
dataremaining = hsd->RxXferSize;
if (dataremaining > 0U)
{
/* Read data from SDIO Rx FIFO */
for(count = 0U; count < 8U; count++)
{
data = SDIO_ReadFIFO(hsd->Instance);
*tmp = (uint8_t)(data & 0xFFU);
tmp++;
dataremaining--;
*tmp = (uint8_t)((data >> 8U) & 0xFFU);
tmp++;
dataremaining--;
*tmp = (uint8_t)((data >> 16U) & 0xFFU);
tmp++;
dataremaining--;
*tmp = (uint8_t)((data >> 24U) & 0xFFU);
tmp++;
dataremaining--;
}
hsd->pRxBuffPtr = tmp;
hsd->RxXferSize = dataremaining;
}
}
/**
* @brief Wrap up writing in non-blocking mode.
* @param hsd: pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval None
*/
static void SD_Write_IT(SD_HandleTypeDef *hsd)
{
uint32_t count, data, dataremaining;
uint8_t* tmp;
tmp = hsd->pTxBuffPtr;
dataremaining = hsd->TxXferSize;
if (dataremaining > 0U)
{
/* Write data to SDIO Tx FIFO */
for(count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tmp);
tmp++;
dataremaining--;
data |= ((uint32_t)(*tmp) << 8U);
tmp++;
dataremaining--;
data |= ((uint32_t)(*tmp) << 16U);
tmp++;
dataremaining--;
data |= ((uint32_t)(*tmp) << 24U);
tmp++;
dataremaining--;
(void)SDIO_WriteFIFO(hsd->Instance, &data);
}
hsd->pTxBuffPtr = tmp;
hsd->TxXferSize = dataremaining;
}
}
/**
* @}
*/
#endif /* HAL_SD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
#endif /* SDIO */

2348
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c Normal file
View File

@@ -0,0 +1,2348 @@
/**
******************************************************************************
* @file stm32f1xx_hal_smartcard.c
* @author MCD Application Team
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Error functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The SMARTCARD HAL driver can be used as follows:
(#) Declare a SMARTCARD_HandleTypeDef handle structure.
(#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
(##) Enable the interface clock of the USARTx associated to the SMARTCARD.
(##) SMARTCARD pins configuration:
(+++) Enable the clock for the SMARTCARD GPIOs.
(+++) Configure SMARTCARD pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
and HAL_SMARTCARD_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
(##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
and HAL_SMARTCARD_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
(used for last byte sending completion detection in DMA non circular mode)
(#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
(#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
(++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_SMARTCARD_MspInit() API.
[..]
(@) The specific SMARTCARD interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
[..]
Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
(+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
(+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
*** Interrupt mode IO operation ***
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
(+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
(+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
(+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
*** DMA mode IO operation ***
==============================
[..]
(+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
(+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
(+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
(+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
(+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
*** SMARTCARD HAL driver macros list ***
========================================
[..]
Below the list of most used macros in SMARTCARD HAL driver.
(+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
(+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
(+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
(+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
(+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
(+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
[..]
(@) You can refer to the SMARTCARD HAL driver header file for more useful macros
##### Callback registration #####
==================================
[..]
The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
(+) AbortCpltCallback : Abort Complete Callback.
(+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
(+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
(+) MspInitCallback : SMARTCARD MspInit.
(+) MspDeInitCallback : SMARTCARD MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
(+) AbortCpltCallback : Abort Complete Callback.
(+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
(+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
(+) MspInitCallback : SMARTCARD MspInit.
(+) MspDeInitCallback : SMARTCARD MspDeInit.
[..]
By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
or HAL_SMARTCARD_Init() function.
[..]
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @defgroup SMARTCARD SMARTCARD
* @brief HAL SMARTCARD module driver
* @{
*/
#ifdef HAL_SMARTCARD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup SMARTCARD_Private_Constants
* @{
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup SMARTCARD_Private_Functions
* @{
*/
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
* @{
*/
/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART
in Smartcard mode.
[..]
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard.
[..]
The USART can provide a clock to the smartcard through the SCLK output.
In smartcard mode, SCLK is not associated to the communication but is simply derived
from the internal peripheral input clock through a 5-bit prescaler.
[..]
(+) For the Smartcard mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length => Should be 9 bits (8 bits + parity)
(++) Stop Bit
(++) Parity: => Should be enabled
(++) USART polarity
(++) USART phase
(++) USART LastBit
(++) Receiver/transmitter modes
(++) Prescaler
(++) GuardTime
(++) NACKState: The Smartcard NACK state
(+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
(++) Word Length = 9 Bits
(++) 1.5 Stop Bit
(++) Even parity
(++) BaudRate = 12096 baud
(++) Tx and Rx enabled
[..]
Please refer to the ISO 7816-3 specification for more details.
[..]
(@) It is also possible to choose 0.5 stop bit for receiving but it is recommended
to use 1.5 stop bits for both transmitting and receiving to avoid switching
between the two configurations.
[..]
The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
procedures (details for the procedures are available in reference manuals
(RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
@endverbatim
The SMARTCARD frame format is given in the following table:
+-------------------------------------------------------------+
| M bit | PCE bit | SMARTCARD frame |
|---------------------|---------------------------------------|
| 1 | 1 | | SB | 8 bit data | PB | STB | |
+-------------------------------------------------------------+
* @{
*/
/**
* @brief Initializes the SmartCard mode according to the specified
* parameters in the SMARTCARD_InitTypeDef and create the associated handle.
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
{
/* Check the SMARTCARD handle allocation */
if(hsc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsc->Lock = HAL_UNLOCKED;
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
SMARTCARD_InitCallbacksToDefault(hsc);
if (hsc->MspInitCallback == NULL)
{
hsc->MspInitCallback = HAL_SMARTCARD_MspInit;
}
/* Init the low level hardware */
hsc->MspInitCallback(hsc);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_SMARTCARD_MspInit(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
}
hsc->gState = HAL_SMARTCARD_STATE_BUSY;
/* Set the Prescaler */
MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
/* Set the Guard Time */
MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8U));
/* Set the Smartcard Communication parameters */
SMARTCARD_SetConfig(hsc);
/* In SmartCard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Enable the SMARTCARD Parity Error Interrupt */
SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
/* Enable the SMARTCARD Framing Error Interrupt */
SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Enable the Peripheral */
__HAL_SMARTCARD_ENABLE(hsc);
/* Configure the Smartcard NACK state */
MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
/* Enable the SC mode by setting the SCEN bit in the CR3 register */
hsc->Instance->CR3 |= (USART_CR3_SCEN);
/* Initialize the SMARTCARD state*/
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->gState= HAL_SMARTCARD_STATE_READY;
hsc->RxState= HAL_SMARTCARD_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the USART SmartCard peripheral
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
{
/* Check the SMARTCARD handle allocation */
if(hsc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
hsc->gState = HAL_SMARTCARD_STATE_BUSY;
/* Disable the Peripheral */
__HAL_SMARTCARD_DISABLE(hsc);
/* DeInit the low level hardware */
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
if (hsc->MspDeInitCallback == NULL)
{
hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
}
/* DeInit the low level hardware */
hsc->MspDeInitCallback(hsc);
#else
HAL_SMARTCARD_MspDeInit(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->gState = HAL_SMARTCARD_STATE_RESET;
hsc->RxState = HAL_SMARTCARD_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hsc);
return HAL_OK;
}
/**
* @brief SMARTCARD MSP Init
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_MspInit can be implemented in the user file
*/
}
/**
* @brief SMARTCARD MSP DeInit
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_MspDeInit can be implemented in the user file
*/
}
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SMARTCARD Callback
* To be used instead of the weak predefined callback
* @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
* in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
* and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsc smartcard handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
* @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
* @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
* @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
* @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
* @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hsc->gState == HAL_SMARTCARD_STATE_READY)
{
switch (CallbackID)
{
case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
hsc->TxCpltCallback = pCallback;
break;
case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
hsc->RxCpltCallback = pCallback;
break;
case HAL_SMARTCARD_ERROR_CB_ID :
hsc->ErrorCallback = pCallback;
break;
case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
hsc->AbortCpltCallback = pCallback;
break;
case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
hsc->AbortTransmitCpltCallback = pCallback;
break;
case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
hsc->AbortReceiveCpltCallback = pCallback;
break;
case HAL_SMARTCARD_MSPINIT_CB_ID :
hsc->MspInitCallback = pCallback;
break;
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
hsc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hsc->gState == HAL_SMARTCARD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_SMARTCARD_MSPINIT_CB_ID :
hsc->MspInitCallback = pCallback;
break;
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
hsc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister an SMARTCARD callback
* SMARTCARD callback is redirected to the weak predefined callback
* @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init()
* in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
* and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsc smartcard handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
* @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
* @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
* @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
* @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
* @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (HAL_SMARTCARD_STATE_READY == hsc->gState)
{
switch (CallbackID)
{
case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
hsc->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
hsc->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_SMARTCARD_ERROR_CB_ID :
hsc->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
hsc->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
hsc->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
break;
case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
hsc->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
break;
case HAL_SMARTCARD_MSPINIT_CB_ID :
hsc->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
/* Update the error code */
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_SMARTCARD_STATE_RESET == hsc->gState)
{
switch (CallbackID)
{
case HAL_SMARTCARD_MSPINIT_CB_ID :
hsc->MspInitCallback = HAL_SMARTCARD_MspInit;
break;
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
break;
default :
/* Update the error code */
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
* @brief SMARTCARD Transmit and Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
[..]
(#) Smartcard is a single wire half duplex communication protocol.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard.
(#) The USART should be configured as:
(++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
(++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
(#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) Non Blocking mode: The communication is performed using Interrupts
or DMA, These APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
will be executed respectively at the end of the Transmit or Receive process
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
(++) HAL_SMARTCARD_Transmit()
(++) HAL_SMARTCARD_Receive()
(#) Non Blocking mode APIs with Interrupt are :
(++) HAL_SMARTCARD_Transmit_IT()
(++) HAL_SMARTCARD_Receive_IT()
(++) HAL_SMARTCARD_IRQHandler()
(#) Non Blocking mode functions with DMA are :
(++) HAL_SMARTCARD_Transmit_DMA()
(++) HAL_SMARTCARD_Receive_DMA()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SMARTCARD_TxCpltCallback()
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(+) HAL_SMARTCARD_Abort()
(+) HAL_SMARTCARD_AbortTransmit()
(+) HAL_SMARTCARD_AbortReceive()
(+) HAL_SMARTCARD_Abort_IT()
(+) HAL_SMARTCARD_AbortTransmit_IT()
(+) HAL_SMARTCARD_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
(+) HAL_SMARTCARD_AbortCpltCallback()
(+) HAL_SMARTCARD_AbortTransmitCpltCallback()
(+) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
If user wants to abort it, Abort services should be called by user.
(+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
*/
/**
* @brief Send an amount of data in blocking mode
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
const uint8_t *tmp = pData;
uint32_t tickstart = 0U;
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsc);
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hsc->TxXferSize = Size;
hsc->TxXferCount = Size;
while(hsc->TxXferCount > 0U)
{
hsc->TxXferCount--;
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
hsc->Instance->DR = (uint8_t)(*tmp & 0xFFU);
tmp++;
}
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* At end of Tx process, restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in blocking mode
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint8_t *tmp = pData;
uint32_t tickstart = 0U;
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsc);
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hsc->RxXferSize = Size;
hsc->RxXferCount = Size;
/* Check the remain data to be received */
while(hsc->RxXferCount > 0U)
{
hsc->RxXferCount--;
if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
*tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
tmp++;
}
/* At end of Rx process, restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send an amount of data in non blocking mode
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsc);
hsc->pTxBuffPtr = pData;
hsc->TxXferSize = Size;
hsc->TxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
/* Enable the SMARTCARD Parity Error Interrupt */
SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Enable the SMARTCARD Transmit data register empty Interrupt */
SET_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in non blocking mode
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsc);
hsc->pRxBuffPtr = pData;
hsc->RxXferSize = Size;
hsc->RxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
/* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send an amount of data in non blocking mode
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size)
{
const uint32_t *tmp;
/* Check that a Tx process is not already ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsc);
hsc->pTxBuffPtr = pData;
hsc->TxXferSize = Size;
hsc->TxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
/* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
/* Set the DMA error callback */
hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
/* Set the DMA abort callback */
hsc->hdmatx->XferAbortCallback = NULL;
/* Enable the SMARTCARD transmit DMA channel */
tmp = (const uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmatx, *(const uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
/* Process Unlocked */
__HAL_UNLOCK(hsc);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the SMARTCARD CR3 register */
SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in non blocking mode
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received
* @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
/* Check that a Rx process is not already ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsc);
hsc->pRxBuffPtr = pData;
hsc->RxXferSize = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
/* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
/* Set the DMA error callback */
hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
/* Set the DMA abort callback */
hsc->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
/* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
__HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
/* Process Unlocked */
__HAL_UNLOCK(hsc);
/* Enable the SMARTCARD Parity Error Interrupt */
SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the SMARTCARD CR3 register */
SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Abort ongoing transfers (blocking mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsc->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(hsc->hdmatx);
}
}
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsc->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(hsc->hdmarx);
}
}
/* Reset Tx and Rx transfer counters */
hsc->TxXferCount = 0x00U;
hsc->RxXferCount = 0x00U;
/* Reset ErrorCode */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Restore hsc->RxState and hsc->gState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
hsc->gState = HAL_SMARTCARD_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SMARTCARD Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsc->hdmatx->XferAbortCallback = NULL;
HAL_DMA_Abort(hsc->hdmatx);
}
}
/* Reset Tx transfer counter */
hsc->TxXferCount = 0x00U;
/* Restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (blocking mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsc->hdmarx->XferAbortCallback = NULL;
HAL_DMA_Abort(hsc->hdmarx);
}
}
/* Reset Rx transfer counter */
hsc->RxXferCount = 0x00U;
/* Restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (Interrupt mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable PPP Interrupts
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t AbortCplt = 0x01U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if(hsc->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
}
else
{
hsc->hdmatx->XferAbortCallback = NULL;
}
}
/* DMA Rx Handle is valid */
if(hsc->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
Otherwise, set it to NULL */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
}
else
{
hsc->hdmarx->XferAbortCallback = NULL;
}
}
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at SMARTCARD level */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
if(hsc->hdmatx != NULL)
{
/* SMARTCARD Tx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
{
hsc->hdmatx->XferAbortCallback = NULL;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
if(hsc->hdmarx != NULL)
{
/* SMARTCARD Rx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
{
hsc->hdmarx->XferAbortCallback = NULL;
AbortCplt = 0x01U;
}
else
{
AbortCplt = 0x00U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if(AbortCplt == 0x01U)
{
/* Reset Tx and Rx transfer counters */
hsc->TxXferCount = 0x00U;
hsc->RxXferCount = 0x00U;
/* Reset ErrorCode */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Restore hsc->gState and hsc->RxState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Abort complete callback */
hsc->AbortCpltCallback(hsc);
#else
/* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SMARTCARD Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the SMARTCARD DMA Tx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmatx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
/* Abort DMA TX */
if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
{
/* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */
hsc->hdmatx->XferAbortCallback(hsc->hdmatx);
}
}
else
{
/* Reset Tx transfer counter */
hsc->TxXferCount = 0x00U;
/* Restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Abort Transmit Complete Callback */
hsc->AbortTransmitCpltCallback(hsc);
#else
/* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
/* Reset Tx transfer counter */
hsc->TxXferCount = 0x00U;
/* Restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Abort Transmit Complete Callback */
hsc->AbortTransmitCpltCallback(hsc);
#else
/* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param hsc SMARTCARD handle.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SMARTCARD Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
if(hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
{
/* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */
hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
}
}
else
{
/* Reset Rx transfer counter */
hsc->RxXferCount = 0x00U;
/* Restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
hsc->AbortReceiveCpltCallback(hsc);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
/* Reset Rx transfer counter */
hsc->RxXferCount = 0x00U;
/* Restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
hsc->AbortReceiveCpltCallback(hsc);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
* @brief This function handles SMARTCARD interrupt request.
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t isrflags = READ_REG(hsc->Instance->SR);
uint32_t cr1its = READ_REG(hsc->Instance->CR1);
uint32_t cr3its = READ_REG(hsc->Instance->CR3);
uint32_t dmarequest = 0x00U;
uint32_t errorflags = 0x00U;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
if(errorflags == RESET)
{
/* SMARTCARD in mode Receiver -------------------------------------------------*/
if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
SMARTCARD_Receive_IT(hsc);
return;
}
}
/* If some errors occur */
if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
{
/* SMARTCARD parity error interrupt occurred ---------------------------*/
if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
}
/* SMARTCARD frame error interrupt occurred ----------------------------*/
if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
}
/* SMARTCARD noise error interrupt occurred ----------------------------*/
if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
}
/* SMARTCARD Over-Run interrupt occurred -------------------------------*/
if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
{
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
}
/* Call the Error call Back in case of Errors --------------------------*/
if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
{
/* SMARTCARD in mode Receiver ----------------------------------------*/
if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
SMARTCARD_Receive_IT(hsc);
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
{
/* Blocking error : transfer is aborted
Set the SMARTCARD state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
SMARTCARD_EndRxTransfer(hsc);
/* Disable the SMARTCARD DMA Rx request if enabled */
if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel */
if(hsc->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
}
}
else
{
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hsc->ErrorCallback(hsc);
#else
/* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hsc->ErrorCallback(hsc);
#else
/* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
/* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hsc->ErrorCallback(hsc);
#else
/* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
}
}
return;
} /* End if some error occurs */
/* SMARTCARD in mode Transmitter ------------------------------------------*/
if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
SMARTCARD_Transmit_IT(hsc);
return;
}
/* SMARTCARD in mode Transmitter (transmission end) -----------------------*/
if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
SMARTCARD_EndTransmit_IT(hsc);
return;
}
}
/**
* @brief Tx Transfer completed callbacks
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Rx Transfer completed callback
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
*/
}
/**
* @brief SMARTCARD error callback
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
*/
}
/**
* @brief SMARTCARD Abort Complete callback.
* @param hsc SMARTCARD handle.
* @retval None
*/
__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
*/
}
/**
* @brief SMARTCARD Abort Transmit Complete callback.
* @param hsc SMARTCARD handle.
* @retval None
*/
__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
*/
}
/**
* @brief SMARTCARD Abort Receive Complete callback.
* @param hsc SMARTCARD handle.
* @retval None
*/
__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief SMARTCARD State and Errors functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the SmartCard.
(+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
(+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
*/
/**
* @brief Return the SMARTCARD handle state
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL state
*/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc)
{
uint32_t temp1= 0x00U, temp2 = 0x00U;
temp1 = hsc->gState;
temp2 = hsc->RxState;
return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the SMARTCARD error code
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD.
* @retval SMARTCARD Error Code
*/
uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc)
{
return hsc->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
* @{
*/
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
* @brief Initialize the callbacks to their default values.
* @param hsc SMARTCARD handle.
* @retval none
*/
void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsc)
{
/* Init the SMARTCARD Callback settings */
hsc->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
hsc->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
hsc->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
hsc->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
hsc->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
hsc->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @brief DMA SMARTCARD transmit process complete callback
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
/* Enable the SMARTCARD Transmit Complete Interrupt */
SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
}
/**
* @brief DMA SMARTCARD receive process complete callback
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0U;
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Rx complete callback */
hsc->RxCpltCallback(hsc);
#else
/* Call legacy weak Rx complete callback */
HAL_SMARTCARD_RxCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief DMA SMARTCARD communication error callback
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
{
uint32_t dmarequest = 0x00U;
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0U;
hsc->TxXferCount = 0U;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
/* Stop SMARTCARD DMA Tx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT);
if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
{
SMARTCARD_EndTxTransfer(hsc);
}
/* Stop SMARTCARD DMA Rx request if ongoing */
dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
{
SMARTCARD_EndRxTransfer(hsc);
}
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hsc->ErrorCallback(hsc);
#else
/* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief This function handles SMARTCARD Communication Timeout. It waits
* until a flag is no longer in the specified status.
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @param Flag Specifies the SMARTCARD flag to check.
* @param Status The actual Flag status (SET or RESET).
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
{
/* Disable TXE and RXNE interrupts for the interrupt process */
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
hsc->gState= HAL_SMARTCARD_STATE_READY;
hsc->RxState= HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
{
/* At end of Tx process, restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
}
/**
* @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
{
/* At end of Rx process, restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
}
/**
* @brief Send an amount of data in non blocking mode
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
/* Check that a Tx process is ongoing */
if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr & 0xFFU);
hsc->pTxBuffPtr++;
if(--hsc->TxXferCount == 0U)
{
/* Disable the SMARTCARD Transmit data register empty Interrupt */
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
/* Enable the SMARTCARD Transmit Complete Interrupt */
SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Wraps up transmission in non blocking mode.
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
/* Disable the SMARTCARD Transmit Complete Interrupt */
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Tx process is ended, restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Tx complete callback */
hsc->TxCpltCallback(hsc);
#else
/* Call legacy weak Tx complete callback */
HAL_SMARTCARD_TxCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
return HAL_OK;
}
/**
* @brief Receive an amount of data in non blocking mode
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
{
/* Check that a Rx process is ongoing */
if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
*hsc->pRxBuffPtr = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU);
hsc->pRxBuffPtr++;
if(--hsc->RxXferCount == 0U)
{
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
/* Disable the SMARTCARD Parity Error Interrupt */
CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Rx complete callback */
hsc->RxCpltCallback(hsc);
#else
/* Call legacy weak Rx complete callback */
HAL_SMARTCARD_RxCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
return HAL_OK;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0x00U;
hsc->TxXferCount = 0x00U;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hsc->ErrorCallback(hsc);
#else
/* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(hsc->hdmarx != NULL)
{
if(hsc->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hsc->TxXferCount = 0x00U;
hsc->RxXferCount = 0x00U;
/* Reset ErrorCode */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Restore hsc->gState and hsc->RxState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Abort complete callback */
hsc->AbortCpltCallback(hsc);
#else
/* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if(hsc->hdmatx != NULL)
{
if(hsc->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hsc->TxXferCount = 0x00U;
hsc->RxXferCount = 0x00U;
/* Reset ErrorCode */
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Restore hsc->gState and hsc->RxState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
hsc->RxState = HAL_SMARTCARD_STATE_READY;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Abort complete callback */
hsc->AbortCpltCallback(hsc);
#else
/* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
* HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
* (This callback is executed at end of DMA Tx Abort procedure following user abort request,
* and leads to user Tx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->TxXferCount = 0x00U;
/* Restore hsc->gState to Ready */
hsc->gState = HAL_SMARTCARD_STATE_READY;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Abort Transmit Complete Callback */
hsc->AbortTransmitCpltCallback(hsc);
#else
/* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
* HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
* (This callback is executed at end of DMA Rx Abort procedure following user abort request,
* and leads to user Rx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsc->RxXferCount = 0x00U;
/* Restore hsc->RxState to Ready */
hsc->RxState = HAL_SMARTCARD_STATE_READY;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
hsc->AbortReceiveCpltCallback(hsc);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
* @brief Configure the SMARTCARD peripheral
* @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t tmpreg = 0x00U;
uint32_t pclk;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
/* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
/*---------------------------- USART CR2 Configuration ---------------------*/
tmpreg = hsc->Instance->CR2;
/* Clear CLKEN, CPOL, CPHA and LBCL bits */
tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL));
/* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
/* Set CPOL bit according to hsc->Init.CLKPolarity value */
/* Set CPHA bit according to hsc->Init.CLKPhase value */
/* Set LBCL bit according to hsc->Init.CLKLastBit value */
/* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity |
hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
/* Write to USART CR2 */
WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
tmpreg = hsc->Instance->CR2;
/* Clear STOP[13:12] bits */
tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
/* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
tmpreg |= (uint32_t)(hsc->Init.StopBits);
/* Write to USART CR2 */
WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
/*-------------------------- USART CR1 Configuration -----------------------*/
tmpreg = hsc->Instance->CR1;
/* Clear M, PCE, PS, TE and RE bits */
tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
USART_CR1_RE));
/* Configure the SMARTCARD Word Length, Parity and mode:
Set the M bits according to hsc->Init.WordLength value
Set PCE and PS bits according to hsc->Init.Parity value
Set TE and RE bits according to hsc->Init.Mode value */
tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
/* Write to USART CR1 */
WRITE_REG(hsc->Instance->CR1, (uint32_t)tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Clear CTSE and RTSE bits */
CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
/*-------------------------- USART BRR Configuration -----------------------*/
if(hsc->Instance == USART1)
{
pclk = HAL_RCC_GetPCLK2Freq();
hsc->Instance->BRR = SMARTCARD_BRR(pclk, hsc->Init.BaudRate);
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
hsc->Instance->BRR = SMARTCARD_BRR(pclk, hsc->Init.BaudRate);
}
}
/**
* @}
*/
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1117
john103C6T6/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c Normal file
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@@ -0,0 +1,1117 @@
/**
******************************************************************************
* @file stm32f1xx_hal_sram.c
* @author MCD Application Team
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
control SRAM memories. It uses the FSMC layer functions to interface
with SRAM devices.
The following sequence should be followed to configure the FSMC to interface
with SRAM/PSRAM memories:
(#) Declare a SRAM_HandleTypeDef handle structure, for example:
SRAM_HandleTypeDef hsram; and:
(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
values of the structure member.
(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
base register instance for NOR or SRAM device
(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
base register instance for NOR or SRAM extended mode
(#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
mode timings; for example:
FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
and fill its fields with the allowed values of the structure member.
(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
performs the following sequence:
(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
(##) Control register configuration using the FSMC NORSRAM interface function
FSMC_NORSRAM_Init()
(##) Timing register configuration using the FSMC NORSRAM interface function
FSMC_NORSRAM_Timing_Init()
(##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
FSMC_NORSRAM_Extended_Timing_Init()
(##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
(#) At this stage you can perform read/write accesses from/to the memory connected
to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
following APIs:
(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
(#) You can continuously monitor the SRAM device HAL state by calling the function
HAL_SRAM_GetState()
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : SRAM MspInit.
(+) MspDeInitCallback : SRAM MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : SRAM MspInit.
(+) MspDeInitCallback : SRAM MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
or HAL_SRAM_Init function.
When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
#if defined(FSMC_BANK1)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#ifdef HAL_SRAM_MODULE_ENABLED
/** @defgroup SRAM SRAM
* @brief SRAM driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup SRAM_Private_Functions SRAM Private Functions
* @{
*/
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### SRAM Initialization and de_initialization functions #####
==============================================================================
[..] This section provides functions allowing to initialize/de-initialize
the SRAM memory
@endverbatim
* @{
*/
/**
* @brief Performs the SRAM device initialization sequence
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param Timing Pointer to SRAM control timing structure
* @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
FSMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the SRAM handle parameter */
if ((hsram == NULL) || (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE))
{
return HAL_ERROR;
}
if (hsram->State == HAL_SRAM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsram->Lock = HAL_UNLOCKED;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
if (hsram->MspInitCallback == NULL)
{
hsram->MspInitCallback = HAL_SRAM_MspInit;
}
hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
/* Init the low level hardware */
hsram->MspInitCallback(hsram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/* Initialize SRAM control Interface */
(void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
/* Initialize SRAM timing Interface */
(void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
/* Initialize SRAM extended mode timing Interface */
(void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
/* Initialize the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
return HAL_OK;
}
/**
* @brief Performs the SRAM device De-initialization sequence.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
{
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
if (hsram->MspDeInitCallback == NULL)
{
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
}
/* DeInit the low level hardware */
hsram->MspDeInitCallback(hsram);
#else
/* De-Initialize the low level hardware (MSP) */
HAL_SRAM_MspDeInit(hsram);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/* Configure the SRAM registers with their reset values */
(void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
/* Reset the SRAM controller state */
hsram->State = HAL_SRAM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief SRAM MSP Init.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsram);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SRAM_MspInit could be implemented in the user file
*/
}
/**
* @brief SRAM MSP DeInit.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsram);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SRAM_MspDeInit could be implemented in the user file
*/
}
/**
* @brief DMA transfer complete callback.
* @param hdma pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
*/
}
/**
* @brief DMA transfer complete error callback.
* @param hdma pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
* @brief Input Output and memory control functions
*
@verbatim
==============================================================================
##### SRAM Input and Output functions #####
==============================================================================
[..]
This section provides functions allowing to use and control the SRAM memory
@endverbatim
* @{
*/
/**
* @brief Reads 8-bit buffer from SRAM memory.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress Pointer to read start address
* @param pDstBuffer Pointer to destination buffer
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
uint8_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
for (size = BufferSize; size != 0U; size--)
{
*pdestbuff = *psramaddress;
pdestbuff++;
psramaddress++;
}
/* Update the SRAM controller state */
hsram->State = state;
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Writes 8-bit buffer to SRAM memory.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress Pointer to write start address
* @param pSrcBuffer Pointer to source buffer to write
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
uint8_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
for (size = BufferSize; size != 0U; size--)
{
*psramaddress = *psrcbuff;
psrcbuff++;
psramaddress++;
}
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Reads 16-bit buffer from SRAM memory.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress Pointer to read start address
* @param pDstBuffer Pointer to destination buffer
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
uint16_t *pdestbuff = pDstBuffer;
uint8_t limit;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Check if the size is a 32-bits multiple */
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Read data from memory */
for (size = BufferSize; size != limit; size -= 2U)
{
*pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
pdestbuff++;
*pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
pdestbuff++;
psramaddress++;
}
/* Read last 16-bits if size is not 32-bits multiple */
if (limit != 0U)
{
*pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
}
/* Update the SRAM controller state */
hsram->State = state;
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Writes 16-bit buffer to SRAM memory.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress Pointer to write start address
* @param pSrcBuffer Pointer to source buffer to write
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
uint16_t *psrcbuff = pSrcBuffer;
uint8_t limit;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Check if the size is a 32-bits multiple */
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Write data to memory */
for (size = BufferSize; size != limit; size -= 2U)
{
*psramaddress = (uint32_t)(*psrcbuff);
psrcbuff++;
*psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
psrcbuff++;
psramaddress++;
}
/* Write last 16-bits if size is not 32-bits multiple */
if (limit != 0U)
{
*psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
}
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Reads 32-bit buffer from SRAM memory.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress Pointer to read start address
* @param pDstBuffer Pointer to destination buffer
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
uint32_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
for (size = BufferSize; size != 0U; size--)
{
*pdestbuff = *psramaddress;
pdestbuff++;
psramaddress++;
}
/* Update the SRAM controller state */
hsram->State = state;
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Writes 32-bit buffer to SRAM memory.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress Pointer to write start address
* @param pSrcBuffer Pointer to source buffer to write
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
uint32_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
for (size = BufferSize; size != 0U; size--)
{
*psramaddress = *psrcbuff;
psrcbuff++;
psramaddress++;
}
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Reads a Words data from the SRAM memory using DMA transfer.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress Pointer to read start address
* @param pDstBuffer Pointer to destination buffer
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize)
{
HAL_StatusTypeDef status;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Configure DMA user callbacks */
if (state == HAL_SRAM_STATE_READY)
{
hsram->hdma->XferCpltCallback = SRAM_DMACplt;
}
else
{
hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
}
hsram->hdma->XferErrorCallback = SRAM_DMAError;
/* Enable the DMA Stream */
status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress Pointer to write start address
* @param pSrcBuffer Pointer to source buffer to write
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize)
{
HAL_StatusTypeDef status;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Configure DMA user callbacks */
hsram->hdma->XferCpltCallback = SRAM_DMACplt;
hsram->hdma->XferErrorCallback = SRAM_DMAError;
/* Enable the DMA Stream */
status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
status = HAL_ERROR;
}
return status;
}
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SRAM Callback
* To be used to override the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
* @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
if (pCallback == NULL)
{
return HAL_ERROR;
}
state = hsram->State;
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_SRAM_MSP_INIT_CB_ID :
hsram->MspInitCallback = pCallback;
break;
case HAL_SRAM_MSP_DEINIT_CB_ID :
hsram->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a User SRAM Callback
* SRAM Callback is redirected to the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
* @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
* @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
state = hsram->State;
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_SRAM_MSP_INIT_CB_ID :
hsram->MspInitCallback = HAL_SRAM_MspInit;
break;
case HAL_SRAM_MSP_DEINIT_CB_ID :
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
break;
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
break;
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (state == HAL_SRAM_STATE_RESET)
{
switch (CallbackId)
{
case HAL_SRAM_MSP_INIT_CB_ID :
hsram->MspInitCallback = HAL_SRAM_MspInit;
break;
case HAL_SRAM_MSP_DEINIT_CB_ID :
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Register a User SRAM Callback for DMA transfers
* To be used to override the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_DmaCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hsram);
state = hsram->State;
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
hsram->DmaXferCpltCallback = pCallback;
break;
case HAL_SRAM_DMA_XFER_ERR_CB_ID :
hsram->DmaXferErrorCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hsram);
return status;
}
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
* @brief Control functions
*
@verbatim
==============================================================================
##### SRAM Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the SRAM interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically SRAM write operation.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Enable write operation */
(void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disables dynamically SRAM write operation.
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Disable write operation */
(void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_PROTECTED;
/* Process unlocked */
__HAL_UNLOCK(hsram);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### SRAM State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the SRAM controller
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Returns the SRAM controller state
* @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL state
*/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
{
return hsram->State;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup SRAM_Private_Functions SRAM Private Functions
* @{
*/
/**
* @brief DMA SRAM process complete callback.
* @param hdma : DMA handle
* @retval None
*/
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
hsram->DmaXferCpltCallback(hdma);
#else
HAL_SRAM_DMA_XferCpltCallback(hdma);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/**
* @brief DMA SRAM process complete callback.
* @param hdma : DMA handle
* @retval None
*/
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_PROTECTED;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
hsram->DmaXferCpltCallback(hdma);
#else
HAL_SRAM_DMA_XferCpltCallback(hdma);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/**
* @brief DMA SRAM error callback.
* @param hdma : DMA handle
* @retval None
*/
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_ERROR;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
hsram->DmaXferErrorCallback(hdma);
#else
HAL_SRAM_DMA_XferErrorCallback(hdma);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SRAM_MODULE_ENABLED */
/**
* @}
*/
#endif /* FSMC_BANK1 */

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