682 lines
18 KiB
C
682 lines
18 KiB
C
#include "dcdc.h"
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#include "app_config.h"
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#include "board.h"
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#include "stm32g474xx.h"
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#define HRTIM_TIMER_C_INDEX 2U
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#define ADC_SAMPLE_TIME_47CYCLES 5U
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#define HRTIM_DLL_READY_TIMEOUT 1000000UL
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#define DCDC_MIN_PERIOD_TICKS 100UL
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#define DCDC_MAX_PERIOD_TICKS 0xFFFFUL
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#define DCDC_MAX_PERMILLE 1000UL
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/*
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## Live configuration
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The compile-time macros in `app_config.h` only seed this object. After reset,
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edit `g_dcdc_config` in Keil Watch and the 1 ms service loop applies the new
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values to HRTIM and the control loop.
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*/
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volatile DCDC_RuntimeConfig g_dcdc_config =
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{
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#if DCDC_PWM_TEST_ENABLE
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DCDC_MODE_PWM_TEST,
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#elif DCDC_POWER_STAGE_ENABLE
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DCDC_MODE_CLOSED_LOOP,
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#else
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DCDC_MODE_MONITOR,
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#endif
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DCDC_CONNECT_USBPD_INPUT,
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{
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DCDC_PWM_FREQUENCY_HZ,
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DCDC_PWM_TEST_DUTY_PERMILLE,
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900U,
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DCDC_PWM_TEST_DEADTIME_ENABLE,
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DCDC_PWM_TEST_DEADTIME_TICKS,
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DCDC_PWM_TEST_DEADTIME_TICKS
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},
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{
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DCDC_TARGET_VOUT_MV,
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DCDC_MIN_VIN_MV,
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DCDC_MAX_VOUT_MV,
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DCDC_MAX_INPUT_CURRENT_MA,
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DCDC_HARD_INPUT_CURRENT_MA
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},
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{
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DCDC_KP_TICKS_PER_100MV,
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DCDC_KI_TICKS_PER_100MV,
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DCDC_CURRENT_LIMIT_KP
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}
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};
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static DCDC_State s_state = DCDC_STATE_STOPPED;
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static DCDC_Fault s_fault = DCDC_FAULT_NONE;
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static uint32_t s_duty_ticks = DCDC_START_DUTY_TICKS;
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static uint32_t s_period_ticks = DCDC_HRTIM_PERIOD_TICKS;
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static int32_t s_integrator_ticks;
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static bool s_hrtim_ready;
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static void gpio_init_for_dcdc(void);
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static void adc1_init(void);
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static uint16_t adc1_read_channel(uint32_t channel);
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static bool hrtim1_timer_c_init(void);
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static bool hrtim1_wait_dll_ready(void);
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static void hrtim1_outputs_enable(bool enable);
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static void hrtim1_set_duty(uint32_t duty_ticks);
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static uint32_t hrtim_period_from_frequency(uint32_t frequency_hz);
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static uint32_t permille_to_ticks(uint32_t permille);
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static void hrtim1_apply_pwm_config(void);
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static uint32_t hrtim_max_duty_ticks(void);
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static uint32_t clamp_u32(uint32_t value, uint32_t min_value, uint32_t max_value);
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static uint32_t adc_raw_to_mv(uint16_t raw);
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static uint32_t sense_mv_to_voltage_mv(uint32_t sense_mv, uint32_t scale_ppm);
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static uint32_t sense_mv_to_current_ma(uint32_t sense_mv);
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static void set_usbpd_input_switch(bool enable);
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static void set_loads_off(void);
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static void latch_fault(DCDC_Fault fault);
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void DCDC_Init(void)
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{
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gpio_init_for_dcdc();
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set_usbpd_input_switch(false);
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set_loads_off();
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adc1_init();
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s_hrtim_ready = hrtim1_timer_c_init();
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if (s_hrtim_ready)
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{
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hrtim1_outputs_enable(false);
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}
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s_state = DCDC_STATE_READY;
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s_fault = DCDC_FAULT_NONE;
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}
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void DCDC_Start(void)
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{
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if (s_fault != DCDC_FAULT_NONE)
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{
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return;
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}
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if (!s_hrtim_ready)
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{
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latch_fault(DCDC_FAULT_HRTIM);
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return;
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}
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set_usbpd_input_switch(g_dcdc_config.connect_usbpd_input != 0U);
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s_integrator_ticks = 0;
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hrtim1_apply_pwm_config();
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hrtim1_set_duty(DCDC_START_DUTY_TICKS);
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HRTIM1->sMasterRegs.MCR |= HRTIM_MCR_TCCEN;
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hrtim1_outputs_enable(true);
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s_state = DCDC_STATE_RUNNING;
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}
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void DCDC_StartPwmTest(void)
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{
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uint32_t test_duty_ticks;
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if (s_fault != DCDC_FAULT_NONE)
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{
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return;
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}
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if (!s_hrtim_ready)
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{
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latch_fault(DCDC_FAULT_HRTIM);
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return;
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}
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hrtim1_apply_pwm_config();
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test_duty_ticks = permille_to_ticks(g_dcdc_config.pwm.test_duty_permille);
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if (test_duty_ticks == 0U)
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{
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test_duty_ticks = 1U;
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}
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set_usbpd_input_switch(false);
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s_integrator_ticks = 0;
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hrtim1_set_duty(test_duty_ticks);
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HRTIM1->sMasterRegs.MCR |= HRTIM_MCR_TCCEN;
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hrtim1_outputs_enable(true);
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s_state = DCDC_STATE_PWM_TEST;
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}
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void DCDC_Stop(void)
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{
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hrtim1_outputs_enable(false);
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hrtim1_set_duty(DCDC_MIN_DUTY_TICKS);
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HRTIM1->sMasterRegs.MCR &= ~HRTIM_MCR_TCCEN;
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set_usbpd_input_switch(false);
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s_state = DCDC_STATE_STOPPED;
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}
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void DCDC_Service1ms(void)
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{
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DCDC_Mode mode = DCDC_GetMode();
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DCDC_ApplyRuntimeConfig();
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switch (mode)
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{
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case DCDC_MODE_MONITOR:
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if ((s_state == DCDC_STATE_PWM_TEST) || (s_state == DCDC_STATE_RUNNING))
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{
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DCDC_Stop();
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}
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break;
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case DCDC_MODE_PWM_TEST:
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if (s_state != DCDC_STATE_PWM_TEST)
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{
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DCDC_StartPwmTest();
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}
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break;
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case DCDC_MODE_CLOSED_LOOP:
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if (s_state != DCDC_STATE_RUNNING)
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{
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DCDC_Start();
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}
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if (s_state == DCDC_STATE_RUNNING)
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{
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DCDC_ControlStep();
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}
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break;
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default:
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break;
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}
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}
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void DCDC_ApplyRuntimeConfig(void)
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{
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if (!s_hrtim_ready)
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{
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return;
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}
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hrtim1_apply_pwm_config();
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if (s_state == DCDC_STATE_PWM_TEST)
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{
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hrtim1_set_duty(permille_to_ticks(g_dcdc_config.pwm.test_duty_permille));
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}
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}
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void DCDC_ControlStep(void)
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{
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DCDC_Measurements m;
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int32_t error_mv;
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int32_t feed_forward;
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int32_t duty;
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DCDC_ReadMeasurements(&m);
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if (s_state != DCDC_STATE_RUNNING)
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{
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return;
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}
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if (m.vin_mv < g_dcdc_config.limits.min_vin_mv)
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{
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latch_fault(DCDC_FAULT_UNDERVOLTAGE);
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return;
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}
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if (m.vout_mv > g_dcdc_config.limits.max_vout_mv)
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{
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latch_fault(DCDC_FAULT_OVERVOLTAGE);
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return;
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}
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if (m.iin_ma > g_dcdc_config.limits.hard_current_ma)
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{
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latch_fault(DCDC_FAULT_OVERCURRENT);
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return;
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}
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/*
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* Starter buck controller:
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* 1. feed-forward estimates duty from Vout/Vin,
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* 2. PI term removes static voltage error,
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* 3. current term pulls duty down before hard over-current trips.
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*
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* This is deliberately readable, not a final compensated SMPS loop.
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*/
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feed_forward = (int32_t)(((uint64_t)g_dcdc_config.limits.target_vout_mv * s_period_ticks) / m.vin_mv);
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error_mv = (int32_t)g_dcdc_config.limits.target_vout_mv - (int32_t)m.vout_mv;
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s_integrator_ticks += (error_mv * g_dcdc_config.loop.ki_ticks_per_100mv) / 100;
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if (s_integrator_ticks > 3000)
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{
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s_integrator_ticks = 3000;
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}
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else if (s_integrator_ticks < -3000)
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{
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s_integrator_ticks = -3000;
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}
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duty = feed_forward +
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((error_mv * g_dcdc_config.loop.kp_ticks_per_100mv) / 100) +
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s_integrator_ticks;
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if (m.iin_ma > g_dcdc_config.limits.current_limit_ma)
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{
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duty -= (int32_t)((m.iin_ma - g_dcdc_config.limits.current_limit_ma) *
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g_dcdc_config.loop.current_limit_kp);
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}
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if (duty < (int32_t)DCDC_MIN_DUTY_TICKS)
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{
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duty = (int32_t)DCDC_MIN_DUTY_TICKS;
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}
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else if (duty > (int32_t)hrtim_max_duty_ticks())
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{
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duty = (int32_t)hrtim_max_duty_ticks();
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}
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hrtim1_set_duty((uint32_t)duty);
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}
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void DCDC_ReadMeasurements(DCDC_Measurements *out)
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{
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uint32_t vin_sense_mv;
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uint32_t iin_sense_mv;
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uint32_t vout_sense_mv;
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out->vin_raw = adc1_read_channel(2U);
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out->iin_raw = adc1_read_channel(3U);
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out->vout_raw = adc1_read_channel(4U);
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vin_sense_mv = adc_raw_to_mv(out->vin_raw);
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iin_sense_mv = adc_raw_to_mv(out->iin_raw);
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vout_sense_mv = adc_raw_to_mv(out->vout_raw);
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out->vin_mv = sense_mv_to_voltage_mv(vin_sense_mv, DCDC_VIN_SCALE_PPM);
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out->iin_ma = sense_mv_to_current_ma(iin_sense_mv);
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out->vout_mv = sense_mv_to_voltage_mv(vout_sense_mv, DCDC_VOUT_SCALE_PPM);
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}
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DCDC_Mode DCDC_GetMode(void)
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{
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switch ((DCDC_Mode)g_dcdc_config.mode)
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{
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case DCDC_MODE_MONITOR:
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case DCDC_MODE_PWM_TEST:
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case DCDC_MODE_CLOSED_LOOP:
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return (DCDC_Mode)g_dcdc_config.mode;
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default:
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return DCDC_MODE_MONITOR;
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}
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}
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DCDC_State DCDC_GetState(void)
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{
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return s_state;
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}
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DCDC_Fault DCDC_GetFault(void)
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{
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return s_fault;
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}
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bool DCDC_IsHrtimReady(void)
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{
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return s_hrtim_ready;
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}
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uint32_t DCDC_GetDutyTicks(void)
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{
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return s_duty_ticks;
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}
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uint32_t DCDC_GetPeriodTicks(void)
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{
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return s_period_ticks;
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}
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const char *DCDC_StateText(DCDC_State state)
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{
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switch (state)
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{
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case DCDC_STATE_STOPPED: return "stopped";
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case DCDC_STATE_READY: return "ready";
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case DCDC_STATE_PWM_TEST:return "pwm-test";
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case DCDC_STATE_RUNNING: return "running";
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case DCDC_STATE_FAULT: return "fault";
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default: return "unknown";
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}
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}
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const char *DCDC_ModeText(DCDC_Mode mode)
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{
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switch (mode)
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{
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case DCDC_MODE_MONITOR: return "monitor";
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case DCDC_MODE_PWM_TEST: return "pwm-test";
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case DCDC_MODE_CLOSED_LOOP: return "closed-loop";
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default: return "unknown";
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}
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}
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const char *DCDC_FaultText(DCDC_Fault fault)
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{
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switch (fault)
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{
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case DCDC_FAULT_NONE: return "none";
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case DCDC_FAULT_UNDERVOLTAGE: return "vin undervoltage";
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case DCDC_FAULT_OVERVOLTAGE: return "vout overvoltage";
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case DCDC_FAULT_OVERCURRENT: return "input overcurrent";
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case DCDC_FAULT_HRTIM: return "hrtim dll timeout";
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default: return "unknown";
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}
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}
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static void gpio_init_for_dcdc(void)
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{
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RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN;
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(void)RCC->AHB2ENR;
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/* PA1/PA2/PA3 are analog feedback signals: VIN, input current, VOUT. */
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GPIOA->MODER |= (3UL << (1U * 2U)) | (3UL << (2U * 2U)) | (3UL << (3U * 2U));
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GPIOA->PUPDR &= ~((3UL << (1U * 2U)) | (3UL << (2U * 2U)) | (3UL << (3U * 2U)));
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/* PB12/PB13 are HRTIM1 Timer C outputs for the synchronous buck leg. */
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GPIOB->MODER &= ~((3UL << (12U * 2U)) | (3UL << (13U * 2U)));
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GPIOB->MODER |= ((2UL << (12U * 2U)) | (2UL << (13U * 2U)));
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GPIOB->OTYPER &= ~((1UL << 12U) | (1UL << 13U));
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GPIOB->OSPEEDR |= ((3UL << (12U * 2U)) | (3UL << (13U * 2U)));
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GPIOB->PUPDR &= ~((3UL << (12U * 2U)) | (3UL << (13U * 2U)));
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GPIOB->AFR[1] &= ~((0xFUL << ((12U - 8U) * 4U)) | (0xFUL << ((13U - 8U) * 4U)));
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GPIOB->AFR[1] |= ((13UL << ((12U - 8U) * 4U)) | (13UL << ((13U - 8U) * 4U)));
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/* PC3 controls USBPD_VBUS to VIN switch. PC14/PC15 switch onboard loads. */
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GPIOC->MODER &= ~((3UL << (3U * 2U)) | (3UL << (14U * 2U)) | (3UL << (15U * 2U)));
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GPIOC->MODER |= ((1UL << (3U * 2U)) | (1UL << (14U * 2U)) | (1UL << (15U * 2U)));
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GPIOC->OTYPER &= ~((1UL << 3U) | (1UL << 14U) | (1UL << 15U));
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GPIOC->OSPEEDR |= ((2UL << (3U * 2U)) | (2UL << (14U * 2U)) | (2UL << (15U * 2U)));
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GPIOC->PUPDR &= ~((3UL << (3U * 2U)) | (3UL << (14U * 2U)) | (3UL << (15U * 2U)));
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}
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static void adc1_init(void)
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{
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RCC->AHB2ENR |= RCC_AHB2ENR_ADC12EN;
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(void)RCC->AHB2ENR;
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/* Synchronous ADC clock HCLK/4 = 42.5 MHz. */
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ADC12_COMMON->CCR = (ADC12_COMMON->CCR & ~ADC_CCR_CKMODE) |
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(ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0);
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ADC1->CR &= ~ADC_CR_DEEPPWD;
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ADC1->CR |= ADC_CR_ADVREGEN;
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Board_DelayMs(1U);
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ADC1->CR |= ADC_CR_ADCAL;
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while ((ADC1->CR & ADC_CR_ADCAL) != 0U)
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{
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__NOP();
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}
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ADC1->CFGR = ADC_CFGR_OVRMOD;
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ADC1->SMPR1 =
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(ADC_SAMPLE_TIME_47CYCLES << ADC_SMPR1_SMP2_Pos) |
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(ADC_SAMPLE_TIME_47CYCLES << ADC_SMPR1_SMP3_Pos) |
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(ADC_SAMPLE_TIME_47CYCLES << ADC_SMPR1_SMP4_Pos);
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ADC1->ISR = ADC_ISR_ADRDY;
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ADC1->CR |= ADC_CR_ADEN;
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while ((ADC1->ISR & ADC_ISR_ADRDY) == 0U)
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{
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__NOP();
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}
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}
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static uint16_t adc1_read_channel(uint32_t channel)
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{
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ADC1->SQR1 = (channel << ADC_SQR1_SQ1_Pos);
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ADC1->ISR = ADC_ISR_EOC | ADC_ISR_EOS;
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ADC1->CR |= ADC_CR_ADSTART;
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while ((ADC1->ISR & ADC_ISR_EOC) == 0U)
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{
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__NOP();
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}
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return (uint16_t)(ADC1->DR & 0x0FFFU);
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}
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static bool hrtim1_timer_c_init(void)
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{
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HRTIM_Timerx_TypeDef *timer = &HRTIM1->sTimerxRegs[HRTIM_TIMER_C_INDEX];
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RCC->APB2ENR |= RCC_APB2ENR_HRTIM1EN;
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(void)RCC->APB2ENR;
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RCC->APB2RSTR |= RCC_APB2RSTR_HRTIM1RST;
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RCC->APB2RSTR &= ~RCC_APB2RSTR_HRTIM1RST;
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HRTIM1->sCommonRegs.ODISR = HRTIM_ODISR_TC1ODIS | HRTIM_ODISR_TC2ODIS;
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s_period_ticks = hrtim_period_from_frequency(g_dcdc_config.pwm.frequency_hz);
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HRTIM1->sCommonRegs.ICR = HRTIM_ICR_DLLRDYC;
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HRTIM1->sCommonRegs.DLLCR = HRTIM_DLLCR_CALEN |
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HRTIM_DLLCR_CALRTE_1 |
|
|
HRTIM_DLLCR_CAL;
|
|
/* In rescue clock mode DLLRDY may never rise; keep diagnostics alive. */
|
|
if (!hrtim1_wait_dll_ready())
|
|
{
|
|
HRTIM1->sCommonRegs.ODISR = HRTIM_ODISR_TC1ODIS | HRTIM_ODISR_TC2ODIS;
|
|
HRTIM1->sMasterRegs.MCR &= ~HRTIM_MCR_TCCEN;
|
|
return false;
|
|
}
|
|
|
|
timer->TIMxCR = HRTIM_TIMCR_CONT;
|
|
timer->PERxR = s_period_ticks;
|
|
timer->REPxR = 0U;
|
|
timer->CMP1xR = DCDC_MIN_DUTY_TICKS;
|
|
timer->CMP2xR = hrtim_max_duty_ticks();
|
|
timer->CMP3xR = 1000U;
|
|
|
|
#if DCDC_PWM_TEST_ENABLE
|
|
/*
|
|
* Complementary HRTIM test without dead-time/fault handling:
|
|
* PB12/CHC1 goes active at period and inactive at CMP1.
|
|
* PB13/CHC2 goes active at CMP1 and inactive at period.
|
|
*/
|
|
timer->SETx1R = HRTIM_SET1R_PER;
|
|
timer->RSTx1R = HRTIM_RST1R_CMP1;
|
|
timer->SETx2R = HRTIM_SET2R_CMP1;
|
|
timer->RSTx2R = HRTIM_RST2R_PER;
|
|
timer->OUTxR = 0U;
|
|
#else
|
|
/*
|
|
* Complementary buck PWM:
|
|
* CHC1 goes active at period event and inactive at CMP1.
|
|
* CHC2 goes active at CMP1 and inactive at period event.
|
|
* HRTIM dead-time block delays transitions to avoid shoot-through.
|
|
*/
|
|
timer->SETx1R = HRTIM_SET1R_PER;
|
|
timer->RSTx1R = HRTIM_RST1R_CMP1;
|
|
timer->SETx2R = HRTIM_SET2R_CMP1;
|
|
timer->RSTx2R = HRTIM_RST2R_PER;
|
|
timer->OUTxR = HRTIM_OUTR_DTEN | HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT2_1;
|
|
#endif
|
|
|
|
hrtim1_apply_pwm_config();
|
|
|
|
/* Trigger point for future synchronized ADC sampling. */
|
|
HRTIM1->sCommonRegs.ADC1R = HRTIM_ADC1R_AD1TCC3;
|
|
|
|
HRTIM1->sMasterRegs.MCR &= ~HRTIM_MCR_TCCEN;
|
|
return true;
|
|
}
|
|
|
|
static bool hrtim1_wait_dll_ready(void)
|
|
{
|
|
uint32_t timeout = HRTIM_DLL_READY_TIMEOUT;
|
|
|
|
while (((HRTIM1->sCommonRegs.ISR & HRTIM_ISR_DLLRDY) == 0U) && (timeout > 0U))
|
|
{
|
|
timeout--;
|
|
}
|
|
|
|
return timeout > 0U;
|
|
}
|
|
|
|
static void hrtim1_outputs_enable(bool enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
HRTIM1->sCommonRegs.OENR = HRTIM_OENR_TC1OEN | HRTIM_OENR_TC2OEN;
|
|
}
|
|
else
|
|
{
|
|
HRTIM1->sCommonRegs.ODISR = HRTIM_ODISR_TC1ODIS | HRTIM_ODISR_TC2ODIS;
|
|
}
|
|
}
|
|
|
|
static void hrtim1_set_duty(uint32_t duty_ticks)
|
|
{
|
|
if (duty_ticks < DCDC_MIN_DUTY_TICKS)
|
|
{
|
|
duty_ticks = DCDC_MIN_DUTY_TICKS;
|
|
}
|
|
else if (duty_ticks > hrtim_max_duty_ticks())
|
|
{
|
|
duty_ticks = hrtim_max_duty_ticks();
|
|
}
|
|
|
|
HRTIM1->sTimerxRegs[HRTIM_TIMER_C_INDEX].CMP1xR = duty_ticks;
|
|
s_duty_ticks = duty_ticks;
|
|
}
|
|
|
|
static uint32_t hrtim_period_from_frequency(uint32_t frequency_hz)
|
|
{
|
|
uint64_t ticks;
|
|
|
|
if (frequency_hz == 0U)
|
|
{
|
|
frequency_hz = DCDC_PWM_FREQUENCY_HZ;
|
|
}
|
|
|
|
ticks = (((uint64_t)SystemCoreClock * 32ULL) + (frequency_hz / 2ULL)) /
|
|
frequency_hz;
|
|
|
|
if (ticks < DCDC_MIN_PERIOD_TICKS)
|
|
{
|
|
ticks = DCDC_MIN_PERIOD_TICKS;
|
|
}
|
|
else if (ticks > DCDC_MAX_PERIOD_TICKS)
|
|
{
|
|
ticks = DCDC_MAX_PERIOD_TICKS;
|
|
}
|
|
|
|
return (uint32_t)ticks;
|
|
}
|
|
|
|
static uint32_t permille_to_ticks(uint32_t permille)
|
|
{
|
|
permille = clamp_u32(permille, 0U, DCDC_MAX_PERMILLE);
|
|
return (uint32_t)(((uint64_t)s_period_ticks * permille) / DCDC_MAX_PERMILLE);
|
|
}
|
|
|
|
static void hrtim1_apply_pwm_config(void)
|
|
{
|
|
HRTIM_Timerx_TypeDef *timer = &HRTIM1->sTimerxRegs[HRTIM_TIMER_C_INDEX];
|
|
uint32_t period_ticks = hrtim_period_from_frequency(g_dcdc_config.pwm.frequency_hz);
|
|
uint32_t rising_ticks = clamp_u32(g_dcdc_config.pwm.deadtime_rising_ticks, 0U, 0x1FFU);
|
|
uint32_t falling_ticks = clamp_u32(g_dcdc_config.pwm.deadtime_falling_ticks, 0U, 0x1FFU);
|
|
|
|
s_period_ticks = period_ticks;
|
|
timer->PERxR = period_ticks;
|
|
timer->DTxR =
|
|
(rising_ticks << HRTIM_DTR_DTR_Pos) |
|
|
(falling_ticks << HRTIM_DTR_DTF_Pos) |
|
|
(HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0);
|
|
|
|
if (g_dcdc_config.pwm.deadtime_enable != 0U)
|
|
{
|
|
timer->OUTxR |= HRTIM_OUTR_DTEN;
|
|
}
|
|
else
|
|
{
|
|
timer->OUTxR &= ~HRTIM_OUTR_DTEN;
|
|
}
|
|
}
|
|
|
|
static uint32_t hrtim_max_duty_ticks(void)
|
|
{
|
|
uint32_t max_permille = clamp_u32(g_dcdc_config.pwm.max_duty_permille, 1U, DCDC_MAX_PERMILLE);
|
|
uint32_t max_ticks = permille_to_ticks(max_permille);
|
|
|
|
if (s_period_ticks > 10U && max_ticks >= (s_period_ticks - 1U))
|
|
{
|
|
max_ticks = s_period_ticks - 1U;
|
|
}
|
|
|
|
return max_ticks;
|
|
}
|
|
|
|
static uint32_t clamp_u32(uint32_t value, uint32_t min_value, uint32_t max_value)
|
|
{
|
|
if (value < min_value)
|
|
{
|
|
return min_value;
|
|
}
|
|
|
|
if (value > max_value)
|
|
{
|
|
return max_value;
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
static uint32_t adc_raw_to_mv(uint16_t raw)
|
|
{
|
|
return ((uint32_t)raw * ADC_REFERENCE_MV) / ADC_FULL_SCALE_COUNTS;
|
|
}
|
|
|
|
static uint32_t sense_mv_to_voltage_mv(uint32_t sense_mv, uint32_t scale_ppm)
|
|
{
|
|
return (uint32_t)(((uint64_t)sense_mv * 1000000ULL) / scale_ppm);
|
|
}
|
|
|
|
static uint32_t sense_mv_to_current_ma(uint32_t sense_mv)
|
|
{
|
|
return (sense_mv * 1000UL) / DCDC_IIN_UV_PER_MA;
|
|
}
|
|
|
|
static void set_usbpd_input_switch(bool enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
GPIOC->BSRR = (1UL << 3U);
|
|
}
|
|
else
|
|
{
|
|
GPIOC->BRR = (1UL << 3U);
|
|
}
|
|
}
|
|
|
|
static void set_loads_off(void)
|
|
{
|
|
GPIOC->BRR = (1UL << 14U) | (1UL << 15U);
|
|
}
|
|
|
|
static void latch_fault(DCDC_Fault fault)
|
|
{
|
|
hrtim1_outputs_enable(false);
|
|
hrtim1_set_duty(DCDC_MIN_DUTY_TICKS);
|
|
HRTIM1->sMasterRegs.MCR &= ~HRTIM_MCR_TCCEN;
|
|
set_usbpd_input_switch(false);
|
|
|
|
s_fault = fault;
|
|
s_state = DCDC_STATE_FAULT;
|
|
}
|