392 lines
15 KiB
C
392 lines
15 KiB
C
// TI File $Revision: /main/4 $
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// Checkin $Date: November 15, 2007 09:58:53 $
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//###########################################################################
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//
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// FILE: DSP2833x_Gpio.h
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//
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// TITLE: DSP2833x General Purpose I/O Definitions.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#ifndef DSP2833x_GPIO_H
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#define DSP2833x_GPIO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//----------------------------------------------------
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// GPIO A control register bit definitions */
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struct GPACTRL_BITS { // bits description
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Uint16 QUALPRD0:8; // 7:0 Qual period
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Uint16 QUALPRD1:8; // 15:8 Qual period
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Uint16 QUALPRD2:8; // 23:16 Qual period
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Uint16 QUALPRD3:8; // 31:24 Qual period
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};
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union GPACTRL_REG {
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Uint32 all;
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struct GPACTRL_BITS bit;
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};
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//----------------------------------------------------
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// GPIO B control register bit definitions */
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struct GPBCTRL_BITS { // bits description
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Uint16 QUALPRD0:8; // 7:0 Qual period
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Uint16 QUALPRD1:8; // 15:8 Qual period
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Uint16 QUALPRD2:8; // 23:16 Qual period
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Uint16 QUALPRD3:8; // 31:24
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};
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union GPBCTRL_REG {
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Uint32 all;
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struct GPBCTRL_BITS bit;
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};
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//----------------------------------------------------
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// GPIO A Qual/MUX select register bit definitions */
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struct GPA1_BITS { // bits description
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Uint16 GPIO0:2; // 1:0 GPIO0
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Uint16 GPIO1:2; // 3:2 GPIO1
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Uint16 GPIO2:2; // 5:4 GPIO2
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Uint16 GPIO3:2; // 7:6 GPIO3
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Uint16 GPIO4:2; // 9:8 GPIO4
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Uint16 GPIO5:2; // 11:10 GPIO5
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Uint16 GPIO6:2; // 13:12 GPIO6
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Uint16 GPIO7:2; // 15:14 GPIO7
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Uint16 GPIO8:2; // 17:16 GPIO8
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Uint16 GPIO9:2; // 19:18 GPIO9
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Uint16 GPIO10:2; // 21:20 GPIO10
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Uint16 GPIO11:2; // 23:22 GPIO11
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Uint16 GPIO12:2; // 25:24 GPIO12
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Uint16 GPIO13:2; // 27:26 GPIO13
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Uint16 GPIO14:2; // 29:28 GPIO14
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Uint16 GPIO15:2; // 31:30 GPIO15
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};
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struct GPA2_BITS { // bits description
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Uint16 GPIO16:2; // 1:0 GPIO16
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Uint16 GPIO17:2; // 3:2 GPIO17
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Uint16 GPIO18:2; // 5:4 GPIO18
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Uint16 GPIO19:2; // 7:6 GPIO19
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Uint16 GPIO20:2; // 9:8 GPIO20
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Uint16 GPIO21:2; // 11:10 GPIO21
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Uint16 GPIO22:2; // 13:12 GPIO22
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Uint16 GPIO23:2; // 15:14 GPIO23
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Uint16 GPIO24:2; // 17:16 GPIO24
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Uint16 GPIO25:2; // 19:18 GPIO25
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Uint16 GPIO26:2; // 21:20 GPIO26
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Uint16 GPIO27:2; // 23:22 GPIO27
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Uint16 GPIO28:2; // 25:24 GPIO28
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Uint16 GPIO29:2; // 27:26 GPIO29
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Uint16 GPIO30:2; // 29:28 GPIO30
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Uint16 GPIO31:2; // 31:30 GPIO31
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};
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struct GPB1_BITS { // bits description
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Uint16 GPIO32:2; // 1:0 GPIO32
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Uint16 GPIO33:2; // 3:2 GPIO33
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Uint16 GPIO34:2; // 5:4 GPIO34
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Uint16 GPIO35:2; // 7:6 GPIO35
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Uint16 GPIO36:2; // 9:8 GPIO36
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Uint16 GPIO37:2; // 11:10 GPIO37
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Uint16 GPIO38:2; // 13:12 GPIO38
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Uint16 GPIO39:2; // 15:14 GPIO39
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Uint16 GPIO40:2; // 17:16 GPIO40
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Uint16 GPIO41:2; // 19:16 GPIO41
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Uint16 GPIO42:2; // 21:20 GPIO42
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Uint16 GPIO43:2; // 23:22 GPIO43
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Uint16 GPIO44:2; // 25:24 GPIO44
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Uint16 GPIO45:2; // 27:26 GPIO45
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Uint16 GPIO46:2; // 29:28 GPIO46
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Uint16 GPIO47:2; // 31:30 GPIO47
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};
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struct GPB2_BITS { // bits description
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Uint16 GPIO48:2; // 1:0 GPIO48
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Uint16 GPIO49:2; // 3:2 GPIO49
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Uint16 GPIO50:2; // 5:4 GPIO50
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Uint16 GPIO51:2; // 7:6 GPIO51
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Uint16 GPIO52:2; // 9:8 GPIO52
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Uint16 GPIO53:2; // 11:10 GPIO53
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Uint16 GPIO54:2; // 13:12 GPIO54
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Uint16 GPIO55:2; // 15:14 GPIO55
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Uint16 GPIO56:2; // 17:16 GPIO56
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Uint16 GPIO57:2; // 19:18 GPIO57
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Uint16 GPIO58:2; // 21:20 GPIO58
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Uint16 GPIO59:2; // 23:22 GPIO59
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Uint16 GPIO60:2; // 25:24 GPIO60
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Uint16 GPIO61:2; // 27:26 GPIO61
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Uint16 GPIO62:2; // 29:28 GPIO62
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Uint16 GPIO63:2; // 31:30 GPIO63
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};
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struct GPC1_BITS { // bits description
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Uint16 GPIO64:2; // 1:0 GPIO64
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Uint16 GPIO65:2; // 3:2 GPIO65
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Uint16 GPIO66:2; // 5:4 GPIO66
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Uint16 GPIO67:2; // 7:6 GPIO67
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Uint16 GPIO68:2; // 9:8 GPIO68
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Uint16 GPIO69:2; // 11:10 GPIO69
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Uint16 GPIO70:2; // 13:12 GPIO70
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Uint16 GPIO71:2; // 15:14 GPIO71
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Uint16 GPIO72:2; // 17:16 GPIO72
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Uint16 GPIO73:2; // 19:18 GPIO73
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Uint16 GPIO74:2; // 21:20 GPIO74
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Uint16 GPIO75:2; // 23:22 GPIO75
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Uint16 GPIO76:2; // 25:24 GPIO76
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Uint16 GPIO77:2; // 27:26 GPIO77
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Uint16 GPIO78:2; // 29:28 GPIO78
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Uint16 GPIO79:2; // 31:30 GPIO79
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};
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struct GPC2_BITS { // bits description
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Uint16 GPIO80:2; // 1:0 GPIO80
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Uint16 GPIO81:2; // 3:2 GPIO81
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Uint16 GPIO82:2; // 5:4 GPIO82
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Uint16 GPIO83:2; // 7:6 GPIO83
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Uint16 GPIO84:2; // 9:8 GPIO84
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Uint16 GPIO85:2; // 11:10 GPIO85
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Uint16 GPIO86:2; // 13:12 GPIO86
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Uint16 GPIO87:2; // 15:14 GPIO87
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Uint16 rsvd:16; // 31:16 reserved
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};
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union GPA1_REG {
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Uint32 all;
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struct GPA1_BITS bit;
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};
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union GPA2_REG {
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Uint32 all;
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struct GPA2_BITS bit;
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};
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union GPB1_REG {
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Uint32 all;
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struct GPB1_BITS bit;
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};
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union GPB2_REG {
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Uint32 all;
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struct GPB2_BITS bit;
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};
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union GPC1_REG {
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Uint32 all;
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struct GPC1_BITS bit;
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};
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union GPC2_REG {
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Uint32 all;
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struct GPC2_BITS bit;
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};
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//----------------------------------------------------
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// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions */
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struct GPADAT_BITS { // bits description
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Uint16 GPIO0:1; // 0 GPIO0
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Uint16 GPIO1:1; // 1 GPIO1
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Uint16 GPIO2:1; // 2 GPIO2
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Uint16 GPIO3:1; // 3 GPIO3
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Uint16 GPIO4:1; // 4 GPIO4
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Uint16 GPIO5:1; // 5 GPIO5
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Uint16 GPIO6:1; // 6 GPIO6
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Uint16 GPIO7:1; // 7 GPIO7
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Uint16 GPIO8:1; // 8 GPIO8
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Uint16 GPIO9:1; // 9 GPIO9
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Uint16 GPIO10:1; // 10 GPIO10
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Uint16 GPIO11:1; // 11 GPIO11
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Uint16 GPIO12:1; // 12 GPIO12
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Uint16 GPIO13:1; // 13 GPIO13
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Uint16 GPIO14:1; // 14 GPIO14
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Uint16 GPIO15:1; // 15 GPIO15
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Uint16 GPIO16:1; // 16 GPIO16
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Uint16 GPIO17:1; // 17 GPIO17
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Uint16 GPIO18:1; // 18 GPIO18
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Uint16 GPIO19:1; // 19 GPIO19
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Uint16 GPIO20:1; // 20 GPIO20
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Uint16 GPIO21:1; // 21 GPIO21
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Uint16 GPIO22:1; // 22 GPIO22
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Uint16 GPIO23:1; // 23 GPIO23
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Uint16 GPIO24:1; // 24 GPIO24
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Uint16 GPIO25:1; // 25 GPIO25
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Uint16 GPIO26:1; // 26 GPIO26
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Uint16 GPIO27:1; // 27 GPIO27
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Uint16 GPIO28:1; // 28 GPIO28
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Uint16 GPIO29:1; // 29 GPIO29
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Uint16 GPIO30:1; // 30 GPIO30
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Uint16 GPIO31:1; // 31 GPIO31
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};
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struct GPBDAT_BITS { // bits description
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Uint16 GPIO32:1; // 0 GPIO32
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Uint16 GPIO33:1; // 1 GPIO33
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Uint16 GPIO34:1; // 2 GPIO34
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Uint16 GPIO35:1; // 3 GPIO35
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Uint16 GPIO36:1; // 4 GPIO36
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Uint16 GPIO37:1; // 5 GPIO37
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Uint16 GPIO38:1; // 6 GPIO38
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Uint16 GPIO39:1; // 7 GPIO39
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Uint16 GPIO40:1; // 8 GPIO40
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Uint16 GPIO41:1; // 9 GPIO41
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Uint16 GPIO42:1; // 10 GPIO42
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Uint16 GPIO43:1; // 11 GPIO43
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Uint16 GPIO44:1; // 12 GPIO44
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Uint16 GPIO45:1; // 13 GPIO45
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Uint16 GPIO46:1; // 14 GPIO46
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Uint16 GPIO47:1; // 15 GPIO47
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Uint16 GPIO48:1; // 16 GPIO48
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Uint16 GPIO49:1; // 17 GPIO49
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Uint16 GPIO50:1; // 18 GPIO50
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Uint16 GPIO51:1; // 19 GPIO51
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Uint16 GPIO52:1; // 20 GPIO52
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Uint16 GPIO53:1; // 21 GPIO53
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Uint16 GPIO54:1; // 22 GPIO54
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Uint16 GPIO55:1; // 23 GPIO55
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Uint16 GPIO56:1; // 24 GPIO56
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Uint16 GPIO57:1; // 25 GPIO57
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Uint16 GPIO58:1; // 26 GPIO58
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Uint16 GPIO59:1; // 27 GPIO59
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Uint16 GPIO60:1; // 28 GPIO60
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Uint16 GPIO61:1; // 29 GPIO61
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Uint16 GPIO62:1; // 30 GPIO62
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Uint16 GPIO63:1; // 31 GPIO63
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};
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struct GPCDAT_BITS { // bits description
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Uint16 GPIO64:1; // 0 GPIO64
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Uint16 GPIO65:1; // 1 GPIO65
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Uint16 GPIO66:1; // 2 GPIO66
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Uint16 GPIO67:1; // 3 GPIO67
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Uint16 GPIO68:1; // 4 GPIO68
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Uint16 GPIO69:1; // 5 GPIO69
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Uint16 GPIO70:1; // 6 GPIO70
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Uint16 GPIO71:1; // 7 GPIO71
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Uint16 GPIO72:1; // 8 GPIO72
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Uint16 GPIO73:1; // 9 GPIO73
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Uint16 GPIO74:1; // 10 GPIO74
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Uint16 GPIO75:1; // 11 GPIO75
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Uint16 GPIO76:1; // 12 GPIO76
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Uint16 GPIO77:1; // 13 GPIO77
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Uint16 GPIO78:1; // 14 GPIO78
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Uint16 GPIO79:1; // 15 GPIO79
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Uint16 GPIO80:1; // 16 GPIO80
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Uint16 GPIO81:1; // 17 GPIO81
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Uint16 GPIO82:1; // 18 GPIO82
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Uint16 GPIO83:1; // 19 GPIO83
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Uint16 GPIO84:1; // 20 GPIO84
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Uint16 GPIO85:1; // 21 GPIO85
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Uint16 GPIO86:1; // 22 GPIO86
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Uint16 GPIO87:1; // 23 GPIO87
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Uint16 rsvd1:8; // 31:24 reserved
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};
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union GPADAT_REG {
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Uint32 all;
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struct GPADAT_BITS bit;
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};
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union GPBDAT_REG {
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Uint32 all;
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struct GPBDAT_BITS bit;
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};
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union GPCDAT_REG {
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Uint32 all;
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struct GPCDAT_BITS bit;
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};
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//----------------------------------------------------
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// GPIO Xint1/XINT2/XNMI select register bit definitions */
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struct GPIOXINT_BITS { // bits description
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Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
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Uint16 rsvd1:11; // 15:5 reserved
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};
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union GPIOXINT_REG {
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Uint16 all;
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struct GPIOXINT_BITS bit;
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};
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struct GPIO_CTRL_REGS {
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union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
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union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15)
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union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31)
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union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15)
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union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31)
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union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31)
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union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31)
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Uint32 rsvd1;
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union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
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union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47)
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union GPB2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63)
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union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47)
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union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63)
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union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63)
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union GPBDAT_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63)
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Uint16 rsvd2[8];
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union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79)
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union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95)
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union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95)
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union GPCDAT_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95)
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};
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struct GPIO_DATA_REGS {
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union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
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union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31)
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union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31)
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union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31)
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union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63)
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union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 63)
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union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63)
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union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 63)
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union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95)
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union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95)
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union GPCDAT_REG GPCCLEAR; // GPIO Data Clear Register (GPIO64 to 95)
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union GPCDAT_REG GPCTOGGLE; // GPIO Data Toggle Register (GPIO64 to 95)
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Uint16 rsvd1[8];
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};
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struct GPIO_INT_REGS {
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union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO Input Selection
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union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO Input Selection
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union GPIOXINT_REG GPIOXNMISEL; // XNMI_Xint13 GPIO Input Selection
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union GPIOXINT_REG GPIOXINT3SEL; // XINT3 GPIO Input Selection
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union GPIOXINT_REG GPIOXINT4SEL; // XINT4 GPIO Input Selection
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union GPIOXINT_REG GPIOXINT5SEL; // XINT5 GPIO Input Selection
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union GPIOXINT_REG GPIOXINT6SEL; // XINT6 GPIO Input Selection
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union GPIOXINT_REG GPIOXINT7SEL; // XINT7 GPIO Input Selection
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union GPADAT_REG GPIOLPMSEL; // Low power modes GP I/O input select
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};
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//---------------------------------------------------------------------------
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// GPI/O External References & Function Declarations:
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//
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extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
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extern volatile struct GPIO_DATA_REGS GpioDataRegs;
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extern volatile struct GPIO_INT_REGS GpioIntRegs;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_GPIO_H definition
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//===========================================================================
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// End of file.
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//===========================================================================
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