306 lines
9.4 KiB
C
306 lines
9.4 KiB
C
// TI File $Revision: /main/8 $
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// Checkin $Date: April 21, 2008 15:41:42 $
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//###########################################################################
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//
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// FILE: Example_2833xEpwmTripZone.c
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//
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// TITLE: Check PWM Trip Zone Test
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//
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// ASSUMPTIONS:
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//
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// This program requires the DSP2833x header files.
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//
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// Initially tie TZ1 (GPIO12) and TZ2 (GPIO13) high.
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//
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// During the test, monitor ePWM1 or ePWM2 outputs
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// on a scope Pull TZ1 or TZ2 low to see the effect.
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//
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// EPWM1A is on GPIO0
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// EPWM1B is on GPIO1
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// EPWM2A is on GPIO2
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// EPWM2B is on GPIO3
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//
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// ePWM1 will react as a 1 shot trip
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//
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// ePWM2 will react as a cycle by cycle trip and will be
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// cleared if TZ1 and TZ2 are both pulled back high.
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//
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//
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// As supplied, this project is configured for "boot to SARAM"
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// operation. The 2833x Boot Mode table is shown below.
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// For information on configuring the boot mode of an eZdsp,
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// please refer to the documentation included with the eZdsp,
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//
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// $Boot_Table:
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//
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// GPIO87 GPIO86 GPIO85 GPIO84
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// XA15 XA14 XA13 XA12
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// PU PU PU PU
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// ==========================================
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// 1 1 1 1 Jump to Flash
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// 1 1 1 0 SCI-A boot
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// 1 1 0 1 SPI-A boot
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// 1 1 0 0 I2C-A boot
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// 1 0 1 1 eCAN-A boot
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// 1 0 1 0 McBSP-A boot
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// 1 0 0 1 Jump to XINTF x16
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// 1 0 0 0 Jump to XINTF x32
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// 0 1 1 1 Jump to OTP
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// 0 1 1 0 Parallel GPIO I/O boot
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// 0 1 0 1 Parallel XINTF boot
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// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
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// 0 0 1 1 Branch to check boot mode
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// 0 0 1 0 Boot to flash, bypass ADC cal
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// 0 0 0 1 Boot to SARAM, bypass ADC cal
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// 0 0 0 0 Boot to SCI-A, bypass ADC cal
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// Boot_Table_End$
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//
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// DESCRIPTION:
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//
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// This example configures ePWM1 and ePWM2
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//
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// 2 Examples are included:
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// * ePWM1 has TZ1 and TZ2 as one shot trip sources
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// * ePWM2 has TZ1 and TZ2 as cycle by cycle trip sources
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//
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// Each ePWM is configured to interrupt on the 3rd zero event
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// when this happens the deadband is modified such that
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// 0 <= DB <= DB_MAX. That is, the deadband will move up and
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// down between 0 and the maximum value.
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//
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//
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// View the EPWM1A/B, EPWM2A/B waveforms
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// via an oscilloscope to see the effect of TZ1 and TZ2
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//
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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// Prototype statements for functions found within this file.
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void InitEPwm1Example(void);
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void InitEPwm2Example(void);
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interrupt void epwm1_tzint_isr(void);
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interrupt void epwm2_tzint_isr(void);
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// Global variables used in this example
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Uint32 EPwm1TZIntCount;
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Uint32 EPwm2TZIntCount;
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void main(void)
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{
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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InitSysCtrl();
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// Step 2. Initalize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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// InitGpio(); // Skipped for this example
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// For this case just init GPIO pins for ePWM1, ePWM2, and TZ pins
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InitEPwm1Gpio();
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InitEPwm2Gpio();
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InitTzGpio();
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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DINT;
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// Initialize the PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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InitPieCtrl();
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// Disable CPU interrupts and clear all CPU interrupt flags:
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IER = 0x0000;
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IFR = 0x0000;
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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InitPieVectTable();
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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EALLOW; // This is needed to write to EALLOW protected registers
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PieVectTable.EPWM1_TZINT = &epwm1_tzint_isr;
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PieVectTable.EPWM2_TZINT = &epwm2_tzint_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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// InitPeripherals(); // Not required for this example
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
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EDIS;
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InitEPwm1Example();
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InitEPwm2Example();
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
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EDIS;
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// Step 5. User specific code, enable interrupts
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// Initalize counters:
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EPwm1TZIntCount = 0;
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EPwm2TZIntCount = 0;
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// Enable CPU INT3 which is connected to EPWM1-3 INT:
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IER |= M_INT2;
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// Enable EPWM INTn in the PIE: Group 2 interrupt 1-3
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PieCtrlRegs.PIEIER2.bit.INTx1 = 1;
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PieCtrlRegs.PIEIER2.bit.INTx2 = 1;
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// Enable global Interrupts and higher priority real-time debug events:
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EINT; // Enable Global interrupt INTM
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ERTM; // Enable Global realtime interrupt DBGM
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// Step 6. IDLE loop. Just sit and loop forever (optional):
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for(;;)
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{
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asm(" NOP");
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}
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}
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interrupt void epwm1_tzint_isr(void)
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{
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EPwm1TZIntCount++;
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// Leave these flags set so we only take this
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// interrupt once
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//
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// EALLOW;
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// EPwm1Regs.TZCLR.bit.OST = 1;
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// EPwm1Regs.TZCLR.bit.INT = 1;
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// EDIS;
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// Acknowledge this interrupt to receive more interrupts from group 2
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
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}
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interrupt void epwm2_tzint_isr(void)
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{
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EPwm2TZIntCount++;
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// Clear the flags - we will continue to take
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// this interrupt until the TZ pin goes high
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//
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EALLOW;
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EPwm2Regs.TZCLR.bit.CBC = 1;
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EPwm2Regs.TZCLR.bit.INT = 1;
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EDIS;
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// Acknowledge this interrupt to receive more interrupts from group 2
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
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}
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void InitEPwm1Example()
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{
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// Enable TZ1 and TZ2 as one shot trip sources
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EALLOW;
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EPwm1Regs.TZSEL.bit.OSHT1 = 1;
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EPwm1Regs.TZSEL.bit.OSHT2 = 1;
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// What do we want the TZ1 and TZ2 to do?
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EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_HI;
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EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
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// Enable TZ interrupt
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EPwm1Regs.TZEINT.bit.OST = 1;
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EDIS;
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EPwm1Regs.TBPRD = 6000; // Set timer period
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EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
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EPwm1Regs.TBCTR = 0x0000; // Clear counter
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// Setup TBCLK
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EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
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EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
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EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
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EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;
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EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
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EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
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EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
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EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
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// Setup compare
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EPwm1Regs.CMPA.half.CMPA = 3000;
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// Set actions
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EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
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EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
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EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
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EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;
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}
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void InitEPwm2Example()
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{
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// Enable TZ1 and TZ2 as one cycle-by-cycle trip sources
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EALLOW;
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EPwm2Regs.TZSEL.bit.CBC1 = 1;
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EPwm2Regs.TZSEL.bit.CBC2 = 1;
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// What do we want the TZ1 and TZ2 to do?
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EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_HI;
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EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
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// Enable TZ interrupt
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EPwm2Regs.TZEINT.bit.CBC = 1;
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EDIS;
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EPwm2Regs.TBPRD = 6000; // Set timer period
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EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
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EPwm2Regs.TBCTR = 0x0000; // Clear counter
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// Setup TBCLK
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EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
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EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
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EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
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EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on the scope
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// Setup compare
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EPwm2Regs.CMPA.half.CMPA = 3000;
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// Set actions
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EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero
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EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
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EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
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EPwm2Regs.AQCTLB.bit.CAD = AQ_SET;
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}
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//===========================================================================
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// No more.
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//===========================================================================
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