456 lines
15 KiB
C
456 lines
15 KiB
C
//###########################################################################
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//
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// FILE: Example_2833xEPwm_DMA.c
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//
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// TITLE: DSP2833x Device DMA interface with ePWM example.
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//
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// ASSUMPTIONS:
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//
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// This program requires the DSP2833x header files.
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//
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// As supplied, this project is configured for "boot to SARAM"
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// operation. The 2833x Boot Mode table is shown below.
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// For information on configuring the boot mode of an eZdsp,
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// please refer to the documentation included with the eZdsp,
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//
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// $Boot_Table:
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//
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// GPIO87 GPIO86 GPIO85 GPIO84
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// XA15 XA14 XA13 XA12
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// PU PU PU PU
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// ==========================================
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// 1 1 1 1 Jump to Flash
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// 1 1 1 0 SCI-A boot
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// 1 1 0 1 SPI-A boot
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// 1 1 0 0 I2C-A boot
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// 1 0 1 1 eCAN-A boot
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// 1 0 1 0 McBSP-A boot
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// 1 0 0 1 Jump to XINTF x16
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// 1 0 0 0 Jump to XINTF x32
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// 0 1 1 1 Jump to OTP
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// 0 1 1 0 Parallel GPIO I/O boot
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// 0 1 0 1 Parallel XINTF boot
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// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
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// 0 0 1 1 Branch to check boot mode
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// 0 0 1 0 Boot to flash, bypass ADC cal
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// 0 0 0 1 Boot to SARAM, bypass ADC cal
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// 0 0 0 0 Boot to SCI-A, bypass ADC cal
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// Boot_Table_End$
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//
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// DESCRIPTION:
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//
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// This example demonstrates several cases where the DMA is triggered from
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// SOC signals generated by ePWM modules.
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//
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// DMA CH1 setup:
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// Trigger = ADCSOCA from ePWM1
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// Datasize = 16 bits
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// Source = VarA
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// Dest = EPwm1Regs.TBPRD
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// Burst = One word / burst
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// Transfer = One burst / transfer
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// CPU int = every transfer
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//
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// DMA CH2 setup:
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// Trigger = ADCSOCB from ePWM2
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// Datasize = 32 bits
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// Source = VarB
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// Dest = EPwm1Regs.CMPA.all
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// Burst = One 32-bit word / burst
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// Transfer = One burst / transfer
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// CPU int = none
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//
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// DMA CH3 setup:
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// Trigger = ADC SEQ1INT
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// Datasize = 32 bits
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// Source = AdcMirror.ADCRESULT[0-5]
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// Dest = ADCbuffer
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// Burst = Three 32-bit words / burst
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// Transfer = One burst / transfer
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// CPU int = none
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//
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// Watch Variables:
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//
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// EPwm1Regs.TBPRD
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// EPwm1Regs.CMPA.all
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// ADCbuffer
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// InterruptCount
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//
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//###########################################################################
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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// Prototype statements for functions found within this file.
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void delay_loop(void);
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void DMAInitialize(void);
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void DMACH1Config(void);
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void DMACH2Config(void);
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void DMACH3Config(void);
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void ConfigAdc(void);
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void config_ePWM1_to_generate_ADCSOCA(void);
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void config_ePWM2_to_generate_ADCSOCB(void);
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interrupt void local_DINTCH1_ISR(void);
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// Global Variables
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#pragma DATA_SECTION(ADCbuffer,"DMARAML4");
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volatile Uint32 ADCbuffer[3];
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Uint16 VarA;
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Uint32 VarB;
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volatile Uint16 *MAPCNF = (Uint16 *)0x00702E;
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Uint16 InterruptCount;
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void main(void)
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{
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Uint16 i;
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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InitSysCtrl();
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// Step 2. Initalize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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// InitGpio(); // Skipped for this example
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// For this example use the following configuration:
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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DINT;
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// Initialize PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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InitPieCtrl();
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// Disable CPU interrupts and clear all CPU interrupt flags:
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IER = 0x0000;
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IFR = 0x0000;
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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InitPieVectTable();
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EALLOW;
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// Initialize PIE vector for CPU interrupt:
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PieVectTable.DINTCH1 = &local_DINTCH1_ISR; // Point to DMA CH1 ISR
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PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable DMA CH1 interrupt in PIE
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EDIS;
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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// InitPeripherals(); // Not required for this example
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// Step 5. User specific code:
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InterruptCount = 0;
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EALLOW;
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GpioCtrlRegs.GPADIR.all = 0xFFFFFFFF; // All outputs
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SysCtrlRegs.MAPCNF.bit.MAPEPWM = 1; // Remap ePWMs for DMA access
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EDIS;
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GpioDataRegs.GPASET.all = 0xFFFFFFFF;
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delay_loop();
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GpioDataRegs.GPACLEAR.all = 0x00000002;
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for(i=0; i<3; i++)
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{
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ADCbuffer[i] = ((Uint32)i*0x00011000) + 0x00044000;
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}
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VarA = 75;
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VarB = 0x652000;
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// Enable and configure clocks to peripherals:
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EALLOW;
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SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // Enable SYSCLK to DMA
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EDIS;
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DMAInitialize();
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DMACH1Config();
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DMACH2Config();
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DMACH3Config();
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// Enable all interrupts:
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IER = M_INT7; // Enable INT7 (7.1 DMA Ch1)
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EINT;
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InitAdc();
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ConfigAdc();
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config_ePWM1_to_generate_ADCSOCA();
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config_ePWM2_to_generate_ADCSOCB();
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EALLOW;
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DmaRegs.CH1.CONTROL.bit.RUN = 1;
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DmaRegs.CH2.CONTROL.bit.RUN = 1;
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DmaRegs.CH3.CONTROL.bit.RUN = 1;
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asm(" NOP");
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EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Up count mode
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EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Up count mode
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EDIS;
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for(;;) {}
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}
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//===========================================================================
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// DMA Functions
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//===========================================================================
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void DMAInitialize(void)
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{
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EALLOW;
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// Perform a hard reset on DMA
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DmaRegs.DMACTRL.bit.HARDRESET = 1;
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// always perform one NOP after a HARDRESET
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asm(" NOP");
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// Stop DMA on emulation suspend
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DmaRegs.DEBUGCTRL.bit.FREE = 0;
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EDIS;
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}
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void DMACH1Config(void)
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{
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EALLOW;
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// Configure CH1:
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//
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// Reset selected channel via CONTROL Register:
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// DmaRegs.CH1.CONTROL.bit.SOFTRESET = 1; // Perform SOFT reset on channel (clears all counters)
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// Set up MODE Register:
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DmaRegs.CH1.MODE.bit.PERINTSEL = 18; // ePWM1 SOCA as peripheral interrupt source
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DmaRegs.CH1.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled
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DmaRegs.CH1.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt
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DmaRegs.CH1.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer
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DmaRegs.CH1.MODE.bit.SYNCE = 0; // No sync signal
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DmaRegs.CH1.MODE.bit.SYNCSEL = 0; // No sync signal
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DmaRegs.CH1.MODE.bit.DATASIZE = 0; // 16-bit data size transfers
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DmaRegs.CH1.MODE.bit.CHINTMODE = 0; // Generate interrupt to CPU at the beg of transfer
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DmaRegs.CH1.MODE.bit.CHINTE = 1; // Channel Interrupt to CPU enabled
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// Set up BURST registers:
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DmaRegs.CH1.BURST_SIZE.all = 0; // Number (N-1) of 16-bit words transferred in a burst
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DmaRegs.CH1.SRC_BURST_STEP = 0; // Not needed since BURST_SIZE = 0
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DmaRegs.CH1.DST_BURST_STEP = 0; // Not needed since BURST_SIZE = 0
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// Set up TRANSFER registers:
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DmaRegs.CH1.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer
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DmaRegs.CH1.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
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DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
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// Set up WRAP registers:
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DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around
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DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around
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DmaRegs.CH1.SRC_WRAP_STEP = 0;
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DmaRegs.CH1.DST_WRAP_STEP = 0;
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// Set up SOURCE address:
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DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &VarA; // Point to variable in RAM
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// Set up DESTINATION address:
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DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.TBPRD; // Point to ePWM1 TBPRD register remapped for DMA
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// need to make sure .cmd file has ePWMs remapped
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// Clear any spurious flags:
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DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
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DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
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DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
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EDIS;
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}
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void DMACH2Config(void)
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{
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EALLOW;
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// Configure CH2:
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//
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// Reset selected channel via CONTROL Register:
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// DmaRegs.CH2.CONTROL.bit.SOFTRESET = 1; // Perform SOFT reset on channel (clears all counters)
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// Set up MODE Register:
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DmaRegs.CH2.MODE.bit.PERINTSEL = 21; // ePWM2 SOCB as peripheral interrupt source
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DmaRegs.CH2.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled
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DmaRegs.CH2.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt
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DmaRegs.CH2.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer
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DmaRegs.CH2.MODE.bit.SYNCE = 0; // No sync signal
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DmaRegs.CH2.MODE.bit.SYNCSEL = 0; // No sync signal
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DmaRegs.CH2.MODE.bit.DATASIZE = 1; // 32-bit data size transfers
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DmaRegs.CH2.MODE.bit.CHINTMODE = 0;
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DmaRegs.CH2.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled
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// Set up BURST registers:
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DmaRegs.CH2.BURST_SIZE.all = 1; // Number (N-1) of 16-bit words transferred in a burst
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DmaRegs.CH2.SRC_BURST_STEP = 0x0000; // Not needed since only 1 32-bit move per burst
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DmaRegs.CH2.DST_BURST_STEP = 0x0000; // Not needed since only 1 32-bit move per burst
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// Set up TRANSFER registers:
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DmaRegs.CH2.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer
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DmaRegs.CH2.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
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DmaRegs.CH2.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
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// Set up WRAP registers:
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DmaRegs.CH2.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around
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DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around
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DmaRegs.CH2.SRC_WRAP_STEP = 0;
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DmaRegs.CH2.DST_WRAP_STEP = 0;
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// Set up SOURCE address:
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DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32) &VarB; // Point to variable in RAM
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// Set up DESTINATION address:
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DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &EPwm1Regs.CMPA.all; // Point to ePWM1 CMPAHR/CMPA registers
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// Clear any spurious flags:
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DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
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DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
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DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
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EDIS;
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}
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void DMACH3Config(void)
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{
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EALLOW;
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// Configure CH3:
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//
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// Set up MODE Register:
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DmaRegs.CH3.MODE.bit.PERINTSEL = 1; // ADC SEQ1INT as peripheral interrupt source
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DmaRegs.CH3.MODE.bit.PERINTE = 1; // Peripheral interrupt enabled
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DmaRegs.CH3.MODE.bit.ONESHOT = 0; // 1 burst per SW interrupt
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DmaRegs.CH3.MODE.bit.CONTINUOUS = 1; // Do not stop after each transfer
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DmaRegs.CH3.MODE.bit.SYNCE = 0; // No sync signal
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DmaRegs.CH3.MODE.bit.SYNCSEL = 0; // No sync signal
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DmaRegs.CH3.MODE.bit.DATASIZE = 1; // 32-bit data size transfers
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DmaRegs.CH3.MODE.bit.CHINTMODE = 0;
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DmaRegs.CH3.MODE.bit.CHINTE = 0; // Channel Interrupt to CPU disabled
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// Set up BURST registers:
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DmaRegs.CH3.BURST_SIZE.all = 5; // Number (N-1) of 16-bit words transferred in a burst
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DmaRegs.CH3.SRC_BURST_STEP = 2; // Increment source burst address by 2 (32-bit)
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DmaRegs.CH3.DST_BURST_STEP = 2; // Increment destination burst address by 2 (32-bit)
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// Set up TRANSFER registers:
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DmaRegs.CH3.TRANSFER_SIZE = 0; // Bursts (N-1) per transfer
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DmaRegs.CH3.SRC_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
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DmaRegs.CH3.DST_TRANSFER_STEP = 0; // Not needed since TRANSFER_SIZE = 0
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// Set up WRAP registers:
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DmaRegs.CH3.SRC_WRAP_SIZE = 0xFFFF; // No source wrap-around
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DmaRegs.CH3.DST_WRAP_SIZE = 0xFFFF; // No destination wrap-around
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DmaRegs.CH3.SRC_WRAP_STEP = 0;
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DmaRegs.CH3.DST_WRAP_STEP = 0;
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// Set up SOURCE address:
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DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32) &AdcMirror.ADCRESULT0; // Point to first RESULT reg
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// Set up DESTINATION address:
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DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32) &ADCbuffer[0]; // Point to beginning of ADCbuffer
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// Clear any spurious flags:
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DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
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DmaRegs.CH3.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
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DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
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EDIS;
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}
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interrupt void local_DINTCH1_ISR(void) // DMA INT7.1
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{
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GpioDataRegs.GPATOGGLE.all = 0x00000001; // Toggle GPIOA0
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InterruptCount++;
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if((DmaRegs.CH1.CONTROL.bit.OVRFLG == 1) || (DmaRegs.CH2.CONTROL.bit.OVRFLG == 1) ||
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(DmaRegs.CH3.CONTROL.bit.OVRFLG == 1))
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{
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asm(" ESTOP0");
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}
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PieCtrlRegs.PIEACK.bit.ACK7 = 1; // Clear PIEIFR bit
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}
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void ConfigAdc(void)
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{
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 7;
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0; // ADCINA0
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1; // ADCINA1
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2; // ADCINA2
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AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 3; // ADCINA3
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AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 4; // ADCINA4
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AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 5; // ADCINA5
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AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; // Enable ADC to accept ePWM_SOCA trigger
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AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
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AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear interrupt flag
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AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // Enable SEQ1 interrupt
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}
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void config_ePWM1_to_generate_ADCSOCA(void)
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{
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// Configure ePWM1 Timer
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// Interrupt triggers ADCSOCA
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EALLOW;
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EPwm1Regs.TBPRD = 74; // Setup period (one off so DMA transfer will be obvious)
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EPwm1Regs.CMPA.all = 0x501000;
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EPwm1Regs.ETSEL.bit.SOCASEL = 2; // ADCSOCA on TBCTR=TBPRD
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EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate SOCA on 1st event
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EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA generation
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EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode
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EDIS;
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}
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void config_ePWM2_to_generate_ADCSOCB(void)
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{
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// Configure ePWM2 Timer
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// Interrupt triggers ADCSOCB
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EALLOW;
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EPwm2Regs.TBPRD = 150; // Setup periodSetup period
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EPwm2Regs.CMPA.all = 0x200000;
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EPwm2Regs.ETSEL.bit.SOCBSEL = 2; // ADCSOCB on TBCTR=TBPRD
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EPwm2Regs.ETPS.bit.SOCBPRD = 1; // Generate SOCB on 1st event
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EPwm2Regs.ETSEL.bit.SOCBEN = 1; // Enable SOCB generation
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EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // /1 clock mode
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EDIS;
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}
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void delay_loop()
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{
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|
short i;
|
|
for (i = 0; i < 1000; i++) {}
|
|
}
|
|
|
|
|
|
//===========================================================================
|
|
// No more.
|
|
//===========================================================================
|
|
|