390 lines
12 KiB
C
390 lines
12 KiB
C
// TI File $Revision: /main/7 $
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// Checkin $Date: September 20, 2007 13:30:31 $
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//###########################################################################
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//
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// FILE: DSP2833x_SysCtrl.c
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//
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// TITLE: DSP2833x Device System Control Initialization & Support Functions.
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//
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// DESCRIPTION:
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//
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// Example initialization of system resources.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP2833x_Device.h" // Headerfile Include File
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#include "DSP2833x_Examples.h" // Examples Include File
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// Functions that will be run from RAM need to be assigned to
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// a different section. This section will then be mapped to a load and
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// run address using the linker cmd file.
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#pragma CODE_SECTION(InitFlash, "ramfuncs");
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//---------------------------------------------------------------------------
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// InitSysCtrl:
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//---------------------------------------------------------------------------
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// This function initializes the System Control registers to a known state.
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// - Disables the watchdog
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// - Set the PLLCR for proper SYSCLKOUT frequency
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// - Set the pre-scaler for the high and low frequency peripheral clocks
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// - Enable the clocks to the peripherals
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long SYSCLKOUT, LSPCLK, HSPCLK;
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void InitSysCtrl(void)
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{
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// Disable the watchdog
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DisableDog();
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// Initialize the PLL control: PLLCR and DIVSEL
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// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
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InitPll(DSP28_PLLCR,DSP28_DIVSEL);
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// Initialize the peripheral clocks
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InitPeripheralClocks();
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}
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//---------------------------------------------------------------------------
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// Example: InitFlash:
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//---------------------------------------------------------------------------
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// This function initializes the Flash Control registers
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// CAUTION
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// This function MUST be executed out of RAM. Executing it
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// out of OTP/Flash will yield unpredictable results
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void InitFlash(void)
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{
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EALLOW;
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//Enable Flash Pipeline mode to improve performance
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//of code executed from Flash.
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FlashRegs.FOPT.bit.ENPIPE = 1;
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// CAUTION
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//Minimum waitstates required for the flash operating
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//at a given CPU rate must be characterized by TI.
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//Refer to the datasheet for the latest information.
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#if CPU_FRQ_150MHZ
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//Set the Paged Waitstate for the Flash
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FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
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//Set the Random Waitstate for the Flash
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FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
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//Set the Waitstate for the OTP
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FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
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#endif
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#if CPU_FRQ_100MHZ
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//Set the Paged Waitstate for the Flash
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FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
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//Set the Random Waitstate for the Flash
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FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
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//Set the Waitstate for the OTP
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FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
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#endif
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// CAUTION
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//ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
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FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
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FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
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EDIS;
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//Force a pipeline flush to ensure that the write to
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//the last register configured occurs before returning.
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asm(" RPT #7 || NOP");
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}
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//---------------------------------------------------------------------------
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// Example: ServiceDog:
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//---------------------------------------------------------------------------
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// This function resets the watchdog timer.
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// Enable this function for using ServiceDog in the application
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void ServiceDog(void)
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{
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if(SysCtrlRegs.PLLCR.bit.DIV == DSP28_PLLCR)
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if(SysCtrlRegs.PLLSTS.bit.DIVSEL == DSP28_DIVSEL)
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{
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EALLOW;
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SysCtrlRegs.WDKEY = 0x0055;
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SysCtrlRegs.WDKEY = 0x00AA;
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EDIS;
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return;
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} }
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//---------------------------------------------------------------------------
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// Example: DisableDog:
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//---------------------------------------------------------------------------
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// This function disables the watchdog timer.
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void DisableDog(void)
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{
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EALLOW;
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SysCtrlRegs.WDCR= 0x0068;
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EDIS;
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}
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//---------------------------------------------------------------------------
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// Example: InitPll:
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//---------------------------------------------------------------------------
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// This function initializes the PLLCR register.
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void InitPll(Uint16 val, Uint16 divsel)
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{
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long Val;
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val = 10;
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divsel = 2;
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// Make sure the PLL is not running in limp mode
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if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
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{
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// Missing external clock has been detected
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// Replace this line with a call to an appropriate
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// SystemShutdown(); function.
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asm(" ESTOP0");
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}
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// DIVSEL MUST be 0 before PLLCR can be changed from
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// 0x0000. It is set to 0 by an external reset XRSn
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// This puts us in 1/4
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if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
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{
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EALLOW;
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SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
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EDIS;
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}
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// Change the PLLCR
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// if (SysCtrlRegs.PLLCR.bit.DIV != val)
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{
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EALLOW;
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// Before setting PLLCR turn off missing clock detect logic
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SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
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SysCtrlRegs.PLLCR.bit.DIV = val;
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EDIS;
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Val = (val)?val:1;
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Val = XCLKIN * (Val / 2);
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SYSCLKOUT = Val;
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// Optional: Wait for PLL to lock.
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// During this time the CPU will switch to OSCCLK/2 until
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// the PLL is stable. Once the PLL is stable the CPU will
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// switch to the new PLL value.
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//
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// This time-to-lock is monitored by a PLL lock counter.
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//
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// Code is not required to sit and wait for the PLL to lock.
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// However, if the code does anything that is timing critical,
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// and requires the correct clock be locked, then it is best to
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// wait until this switching has completed.
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// Wait for the PLL lock bit to be set.
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// The watchdog should be disabled before this loop, or fed within
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// the loop via ServiceDog().
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// Uncomment to disable the watchdog
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DisableDog();
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while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
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{
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// Uncomment to service the watchdog
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// ServiceDog();
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}
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EALLOW;
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SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
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EDIS;
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}
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// If switching to 1/2
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if((divsel == 1)||(divsel == 2))
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{
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EALLOW;
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SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
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EDIS;
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}
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// If switching to 1/1
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// * First go to 1/2 and let the power settle
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// The time required will depend on the system, this is only an example
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// * Then switch to 1/1
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if(divsel == 3)
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{
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EALLOW;
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SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
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DELAY_US(50L);
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// pause_us(50L);
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SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
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EDIS;
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}
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}
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//--------------------------------------------------------------------------
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// Example: InitPeripheralClocks:
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//---------------------------------------------------------------------------
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// This function initializes the clocks to the peripheral modules.
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// First the high and low clock prescalers are set
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// Second the clocks are enabled to each peripheral.
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// To reduce power, leave clocks to unused peripherals disabled
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//
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// Note: If a peripherals clock is not enabled then you cannot
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// read or write to the registers for that peripheral
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void InitPeripheralClocks(void)
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{
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long Val;
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EALLOW;
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// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
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SysCtrlRegs.HISPCP.all = 0x0003;
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SysCtrlRegs.LOSPCP.all = 0x0000;
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Val = (SysCtrlRegs.HISPCP.all)?
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SysCtrlRegs.HISPCP.all*2 : 1;
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Val = SYSCLKOUT / Val;
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HSPCLK = Val;
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Val = (SysCtrlRegs.LOSPCP.all)?
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SysCtrlRegs.LOSPCP.all*2 : 1;
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Val = SYSCLKOUT / Val;
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LSPCLK = Val;
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// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
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// XTIMCLK = SYSCLKOUT/2
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XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
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// XCLKOUT = XTIMCLK/2
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XintfRegs.XINTCNF2.bit.CLKMODE = 1;
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// Enable XCLKOUT
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XintfRegs.XINTCNF2.bit.CLKOFF = 0;
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// Peripheral clock enables set for the selected peripherals.
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// If you are not using a peripheral leave the clock off
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// to save on power.
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//
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// Note: not all peripherals are available on all 2833x derivates.
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// Refer to the datasheet for your particular device.
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//
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// This function is not written to be an example of efficient code.
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SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
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// *IMPORTANT*
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// The ADC_cal function, which copies the ADC calibration values from TI reserved
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// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
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// Boot ROM. If the boot ROM code is bypassed during the debug process, the
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// following function MUST be called for the ADC to function according
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// to specification. The clocks to the ADC MUST be enabled before calling this
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// function.
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// See the device data manual and/or the ADC Reference
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// Manual for more information.
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ADC_cal();
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SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
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SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
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SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
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SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
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SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
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SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
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SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
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SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
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SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
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SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
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SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
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SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
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SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
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SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
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SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
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SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
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SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
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SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
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SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
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SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
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SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
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SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
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SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
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SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
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SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
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SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
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SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
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SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
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SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
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EDIS;
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}
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//---------------------------------------------------------------------------
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// Example: CsmUnlock:
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//---------------------------------------------------------------------------
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// This function unlocks the CSM. User must replace 0xFFFF's with current
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// password for the DSP. Returns 1 if unlock is successful.
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#define STATUS_FAIL 0
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#define STATUS_SUCCESS 1
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Uint16 CsmUnlock()
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{
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volatile Uint16 temp;
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// Load the key registers with the current password. The 0xFFFF's are dummy
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// passwords. User should replace them with the correct password for the DSP.
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EALLOW;
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CsmRegs.KEY0 = 0xFFFF;
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CsmRegs.KEY1 = 0xFFFF;
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CsmRegs.KEY2 = 0xFFFF;
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CsmRegs.KEY3 = 0xFFFF;
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CsmRegs.KEY4 = 0xFFFF;
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CsmRegs.KEY5 = 0xFFFF;
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CsmRegs.KEY6 = 0xFFFF;
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CsmRegs.KEY7 = 0xFFFF;
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EDIS;
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// Perform a dummy read of the password locations
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// if they match the key values, the CSM will unlock
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temp = CsmPwl.PSWD0;
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temp = CsmPwl.PSWD1;
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temp = CsmPwl.PSWD2;
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temp = CsmPwl.PSWD3;
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temp = CsmPwl.PSWD4;
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temp = CsmPwl.PSWD5;
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temp = CsmPwl.PSWD6;
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temp = CsmPwl.PSWD7;
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// If the CSM unlocked, return succes, otherwise return
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// failure.
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if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS;
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else return STATUS_FAIL;
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}
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//===========================================================================
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// End of file.
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//===========================================================================
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