512 lines
10 KiB
C
512 lines
10 KiB
C
// TI File $Revision: /main/2 $
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// Checkin $Date: April 4, 2007 14:25:31 $
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//###########################################################################
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//
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// FILE: DSP2833x_SWPiroritizedPieVect.c
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//
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// TITLE: DSP2833x Devices SW Prioritized PIE Vector Table Initialization.
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//
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//###########################################################################
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//
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// Original Source by A.T.
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//
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
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#include "DSP2833x_SWPrioritizedIsrLevels.h"
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const struct PIE_VECT_TABLE PieVectTableInit = {
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PIE_RESERVED, // Reserved space
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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PIE_RESERVED, // reserved
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// Non-Peripheral Interrupts:
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#if (INT13PL != 0)
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INT13_ISR, // XINT13
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (INT14PL != 0)
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INT14_ISR, // CPU-Timer2
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (INT15PL != 0)
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DATALOG_ISR, // Datalogging interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (INT16PL != 0)
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RTOSINT_ISR, // RTOS interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR, // reserved interrupt
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NMI_ISR, // Non-maskable interrupt
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ILLEGAL_ISR, // Illegal operation TRAP
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USER1_ISR, // User Defined trap 1
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USER2_ISR, // User Defined trap 2
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USER3_ISR, // User Defined trap 3
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USER4_ISR, // User Defined trap 4
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USER5_ISR, // User Defined trap 5
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USER6_ISR, // User Defined trap 6
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USER7_ISR, // User Defined trap 7
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USER8_ISR, // User Defined trap 8
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USER9_ISR, // User Defined trap 9
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USER10_ISR, // User Defined trap 10
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USER11_ISR, // User Defined trap 11
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USER12_ISR, // User Defined trap 12
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// Group 1 PIE Vectors:
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#if (G11PL != 0)
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SEQ1INT_ISR, // ADC
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G12PL != 0)
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SEQ2INT_ISR, // ADC
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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#if (G14PL != 0)
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XINT1_ISR, // External
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G15PL != 0)
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XINT2_ISR, // External
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G16PL != 0)
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ADCINT_ISR, // ADC
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G17PL != 0)
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TINT0_ISR, // Timer 0
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G18PL != 0)
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WAKEINT_ISR, // WD & Low Power
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#else
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INT_NOTUSED_ISR,
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#endif
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// Group 2 PIE Vectors:
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#if (G21PL != 0)
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EPWM1_TZINT_ISR, // ePWM1 Trip Zone
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G22PL != 0)
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EPWM2_TZINT_ISR, // ePWM2 Trip Zone
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G23PL != 0)
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EPWM3_TZINT_ISR, // ePWM3 Trip Zone
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G24PL != 0)
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EPWM4_TZINT_ISR, // ePWM4 Trip Zone
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G25PL != 0)
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EPWM5_TZINT_ISR, // ePWM5 Trip Zone
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G26PL != 0)
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EPWM6_TZINT_ISR, // ePWM6 Trip Zone
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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rsvd_ISR,
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// Group 3 PIE Vectors:
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#if (G31PL != 0)
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EPWM1_INT_ISR, // ePWM1 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G32PL != 0)
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EPWM2_INT_ISR, // ePWM2 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G33PL != 0)
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EPWM3_INT_ISR, // ePWM3 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G34PL != 0)
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EPWM4_INT_ISR, // ePWM4 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G35PL != 0)
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EPWM5_INT_ISR, // ePWM5 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G36PL != 0)
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EPWM6_INT_ISR, // ePWM6 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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rsvd_ISR,
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// Group 4 PIE Vectors:
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#if (G41PL != 0)
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ECAP1_INT_ISR, // eCAP1 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G42PL != 0)
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ECAP2_INT_ISR, // eCAP2 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G43PL != 0)
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ECAP3_INT_ISR, // eCAP3 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G44PL != 0)
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ECAP4_INT_ISR, // eCAP4 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G45PL != 0)
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ECAP5_INT_ISR, // eCAP5 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G46PL != 0)
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ECAP6_INT_ISR, // eCAP6 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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rsvd_ISR,
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// Group 5 PIE Vectors:
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#if (G51PL != 0)
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EQEP1_INT_ISR, // eQEP1 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G52PL != 0)
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EQEP2_INT_ISR, // eQEP2 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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// Group 6 PIE Vectors:
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#if (G61PL != 0)
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SPIRXINTA_ISR, // SPI-A
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G62PL != 0)
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SPITXINTA_ISR, // SPI-A
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G63PL != 0)
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MRINTB_ISR, // McBSP-B
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G64PL != 0)
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MXINTB_ISR, // McBSP-B
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G65PL != 0)
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MRINTA_ISR, // McBSP-A
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G66PL != 0)
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MXINTA_ISR, // McBSP-A
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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rsvd_ISR,
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// Group 7 PIE Vectors:
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#if (G71PL != 0)
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DINTCH1_ISR, // DMA-Channel 1 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G72PL != 0)
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DINTCH2_ISR, // DMA-Channel 2 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G73PL != 0)
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DINTCH3_ISR, // DMA-Channel 3 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G74PL != 0)
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DINTCH4_ISR, // DMA-Channel 4 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G75PL != 0)
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DINTCH5_ISR, // DMA-Channel 5 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G76PL != 0)
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DINTCH6_ISR, // DMA-Channel 6 Interrupt
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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rsvd_ISR,
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// Group 8 PIE Vectors:
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#if (G81PL != 0)
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I2CINT1A_ISR, // I2C-A
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G82PL != 0)
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I2CINT2A_ISR, // I2C-A
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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rsvd_ISR,
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#if (G85PL != 0)
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SCIRXINTC_ISR, // SCI-C
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G86PL != 0)
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SCITXINTC_ISR, // SCI-C
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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rsvd_ISR,
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// Group 9 PIE Vectors:
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#if (G91PL != 0)
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SCIRXINTA_ISR, // SCI-A
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G92PL != 0)
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SCITXINTA_ISR, // SCI-A
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G93PL != 0)
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SCIRXINTB_ISR, // SCI-B
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G94PL != 0)
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SCITXINTB_ISR, // SCI-B
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G95PL != 0)
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ECAN0INTA_ISR, // eCAN-A
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G96PL != 0)
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ECAN1INTA_ISR, // eCAN-A
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G97PL != 0)
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ECAN0INTB_ISR, // eCAN-B
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G98PL != 0)
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ECAN1INTB_ISR, // eCAN-B
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#else
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INT_NOTUSED_ISR,
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#endif
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// Group 10 PIE Vectors
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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// Group 11 PIE Vectors
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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rsvd_ISR,
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// Group 12 PIE Vectors
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#if (G121PL != 0)
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XINT3_ISR, // External interrupt 3
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G122PL != 0)
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XINT4_ISR, // External interrupt 4
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G123PL != 0)
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XINT5_ISR, // External interrupt 5
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G124PL != 0)
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XINT6_ISR, // External interrupt 6
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G125PL != 0)
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XINT7_ISR, // External interrupt 7
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#else
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INT_NOTUSED_ISR,
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#endif
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rsvd_ISR,
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#if (G127PL != 0)
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LVF_ISR, // Latched overflow flag
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#else
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INT_NOTUSED_ISR,
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#endif
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#if (G128PL != 0)
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LUF_ISR, // Latched underflow flag
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#else
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INT_NOTUSED_ISR,
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#endif
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};
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//---------------------------------------------------------------------------
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// InitPieVectTable:
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//---------------------------------------------------------------------------
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// This function initializes the PIE vector table to a known state.
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// This function must be executed after boot time.
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//
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void InitPieVectTable(void)
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{
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int16 i;
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Uint32 *Source = (void *) &PieVectTableInit;
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Uint32 *Dest = (void *) &PieVectTable;
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EALLOW;
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for(i=0; i < 128; i++) {
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*Dest++ = *Source++;
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}
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EDIS;
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}
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//===========================================================================
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// No more.
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//===========================================================================
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