350 lines
14 KiB
C
350 lines
14 KiB
C
// TI File $Revision: /main/16 $
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// Checkin $Date: October 3, 2007 14:50:19 $
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//###########################################################################
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//
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// FILE: DSP2833x_McBSP.c
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//
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// TITLE: DSP2833x Device McBSP Initialization & Support Functions.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
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//---------------------------------------------------------------------------
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// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate
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// generator (SRG) cycles required for the Mcbsp initialization routine.
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// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock
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// generator (CLKG) cycles required for the Mcbsp initialization routine.
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// For the functions defined in Mcbsp.c, MCBSP_INIT_DELAY and MCBSP_CLKG_DELAY
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// are based off of either a 150 MHz SYSCLKOUT (default) or a 100 MHz SYSCLKOUT.
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//
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// CPU_FRQ_100MHZ and CPU_FRQ_150MHZ are defined in DSP2833x_Examples.h
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//---------------------------------------------------------------------------
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#if CPU_FRQ_150MHZ // For 150 MHz SYSCLKOUT(default)
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#define CPU_SPD 150E6
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#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples
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#endif
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#if CPU_FRQ_100MHZ // For 100 MHz SYSCLKOUT
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#define CPU_SPD 100E6
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#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) for examples
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#endif
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#define CLKGDV_VAL 1
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#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) // # of CPU cycles in 2 SRG cycles-init delay
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#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) // # of CPU cycles in 2 CLKG cycles-init delay
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//---------------------------------------------------------------------------
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// InitMcbsp:
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//---------------------------------------------------------------------------
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// This function initializes the McBSP to a known state.
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//
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void delay_loop(void); // Delay function used for SRG initialization
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void clkg_delay_loop(void); // Delay function used for CLKG initialization
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void InitMcbsp(void)
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{
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InitMcbspa();
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#if DSP28_MCBSPB
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InitMcbspb();
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#endif // end DSP28_MCBSPB
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}
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void InitMcbspa(void)
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{
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// McBSP-A register settings
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McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
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McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
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McbspaRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
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McbspaRegs.MFFINT.all=0x0; // Disable all interrupts
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McbspaRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
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McbspaRegs.RCR1.all=0x0;
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McbspaRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit)
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McbspaRegs.XCR1.all=0x0;
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McbspaRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
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McbspaRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
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McbspaRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
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McbspaRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
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McbspaRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
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McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1)
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delay_loop(); // Wait at least 2 SRG clock cycles
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McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
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clkg_delay_loop(); // Wait at least 2 CLKG cycles
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McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
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McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
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McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
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}
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#if (DSP28_MCBSPB)
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void InitMcbspb(void)
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{
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// McBSP-B register settings
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McbspbRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
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McbspbRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word
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McbspbRegs.SPCR1.bit.DLB = 1; // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
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McbspbRegs.MFFINT.all=0x0; // Disable all interrupts
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McbspbRegs.RCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Receive)
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McbspbRegs.RCR1.all=0x0;
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McbspbRegs.XCR2.all=0x0; // Single-phase frame, 1 word/frame, No companding (Transmit)
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McbspbRegs.XCR1.all=0x0;
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McbspbRegs.SRGR2.bit.CLKSM = 1; // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
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McbspbRegs.SRGR2.bit.FPER = 31; // FPER = 32 CLKG periods
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McbspbRegs.SRGR1.bit.FWID = 0; // Frame Width = 1 CLKG period
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McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; // CLKG frequency = LSPCLK/(CLKGDV+1)
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McbspbRegs.PCR.bit.FSXM = 1; // FSX generated internally, FSR derived from an external source
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McbspbRegs.PCR.bit.CLKXM = 1; // CLKX generated internally, CLKR derived from an external source
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delay_loop(); // Wait at least 2 SRG clock cycles
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McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
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clkg_delay_loop(); // Wait at least 2 CLKG cycles
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McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
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McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
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McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
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}
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#endif // end DSP28_MCBSPB
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// McBSP-A Data Lengths
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void InitMcbspa8bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1=0; // 8-bit word
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McbspaRegs.XCR1.bit.XWDLEN1=0; // 8-bit word
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}
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void InitMcbspa12bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1=1; // 12-bit word
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McbspaRegs.XCR1.bit.XWDLEN1=1; // 12-bit word
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}
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void InitMcbspa16bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
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McbspaRegs.XCR1.bit.XWDLEN1=2; // 16-bit word
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}
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void InitMcbspa20bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1=3; // 20-bit word
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McbspaRegs.XCR1.bit.XWDLEN1=3; // 20-bit word
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}
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void InitMcbspa24bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1=4; // 24-bit word
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McbspaRegs.XCR1.bit.XWDLEN1=4; // 24-bit word
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}
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void InitMcbspa32bit(void)
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{
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McbspaRegs.RCR1.bit.RWDLEN1=5; // 32-bit word
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McbspaRegs.XCR1.bit.XWDLEN1=5; // 32-bit word
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}
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// McBSP-B Data Lengths
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#if (DSP28_MCBSPB)
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void InitMcbspb8bit(void)
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{
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McbspbRegs.RCR1.bit.RWDLEN1=0; // 8-bit word
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McbspbRegs.XCR1.bit.XWDLEN1=0; // 8-bit word
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}
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void InitMcbspb12bit(void)
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{
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McbspbRegs.RCR1.bit.RWDLEN1=1; // 12-bit word
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McbspbRegs.XCR1.bit.XWDLEN1=1; // 12-bit word
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}
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void InitMcbspb16bit(void)
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{
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McbspbRegs.RCR1.bit.RWDLEN1=2; // 16-bit word
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McbspbRegs.XCR1.bit.XWDLEN1=2; // 16-bit word
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}
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void InitMcbspb20bit(void)
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{
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McbspbRegs.RCR1.bit.RWDLEN1=3; // 20-bit word
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McbspbRegs.XCR1.bit.XWDLEN1=3; // 20-bit word
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}
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void InitMcbspb24bit(void)
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{
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McbspbRegs.RCR1.bit.RWDLEN1=4; // 24-bit word
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McbspbRegs.XCR1.bit.XWDLEN1=4; // 24-bit word
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}
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void InitMcbspb32bit(void)
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{
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McbspbRegs.RCR1.bit.RWDLEN1=5; // 32-bit word
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McbspbRegs.XCR1.bit.XWDLEN1=5; // 32-bit word
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}
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#endif //end DSP28_MCBSPB
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void InitMcbspGpio(void)
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{
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InitMcbspaGpio();
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#if DSP28_MCBSPB
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InitMcbspbGpio();
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#endif // end DSP28_MCBSPB
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}
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void InitMcbspaGpio(void)
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{
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EALLOW;
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/* Configure McBSP-A pins using GPIO regs*/
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// This specifies which of the possible GPIO pins will be McBSP functional pins.
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// Comment out other unwanted lines.
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GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; // GPIO20 is MDXA pin
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GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; // GPIO21 is MDRA pin
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GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 is MCLKXA pin
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GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; // GPIO7 is MCLKRA pin (Comment as needed)
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//GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; // GPIO58 is MCLKRA pin (Comment as needed)
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GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // GPIO23 is MFSXA pin
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GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // GPIO5 is MFSRA pin (Comment as needed)
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//GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; // GPIO59 is MFSRA pin (Comment as needed)
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/* Enable internal pull-up for the selected pins */
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// Pull-ups can be enabled or disabled by the user.
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// This will enable the pullups for the specified pins.
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// Comment out other unwanted lines.
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GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (MDXA)
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GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (MDRA)
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GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (MCLKXA)
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GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (MCLKRA) (Comment as needed)
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//GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (MCLKRA) (Comment as needed)
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GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (MFSXA)
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GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (MFSRA) (Comment as needed)
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//GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (MFSRA) (Comment as needed)
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/* Set qualification for selected input pins to asynch only */
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// This will select asynch (no qualification) for the selected pins.
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// Comment out other unwanted lines.
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GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch input GPIO21 (MDRA)
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GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // Asynch input GPIO22 (MCLKXA)
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GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; // Asynch input GPIO7 (MCLKRA) (Comment as needed)
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//GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58(MCLKRA) (Comment as needed)
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GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (MFSXA)
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GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (MFSRA) (Comment as needed)
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//GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (MFSRA) (Comment as needed)
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EDIS;
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}
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#if DSP28_MCBSPB
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void InitMcbspbGpio(void)
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{
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EALLOW;
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/* Configure McBSP-A pins using GPIO regs*/
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// This specifies which of the possible GPIO pins will be McBSP functional pins.
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// Comment out other unwanted lines.
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//GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // GPIO12 is MDXB pin (Comment as needed)
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GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; // GPIO24 is MDXB pin (Comment as needed)
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//GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // GPIO13 is MDRB pin (Comment as needed)
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GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; // GPIO25 is MDRB pin (Comment as needed)
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//GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // GPIO14 is MCLKXB pin (Comment as needed)
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GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; // GPIO26 is MCLKXB pin (Comment as needed)
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GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; // GPIO3 is MCLKRB pin (Comment as needed)
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//GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; // GPIO60 is MCLKRB pin (Comment as needed)
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//GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // GPIO15 is MFSXB pin (Comment as needed)
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GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; // GPIO27 is MFSXB pin (Comment as needed)
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GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; // GPIO1 is MFSRB pin (Comment as needed)
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//GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; // GPIO61 is MFSRB pin (Comment as needed)
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/* Enable internal pull-up for the selected pins */
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// Pull-ups can be enabled or disabled by the user.
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// This will enable the pullups for the specified pins.
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// Comment out other unwanted lines.
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GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (MDXB) (Comment as needed)
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//GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (MDXB) (Comment as needed)
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GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (MDRB) (Comment as needed)
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//GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (MDRB) (Comment as needed)
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GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (MCLKXB) (Comment as needed)
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//GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (MCLKXB) (Comment as needed)
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GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (MCLKRB) (Comment as needed)
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//GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO60 (MCLKRB) (Comment as needed)
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GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (MFSXB) (Comment as needed)
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//GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (MFSXB) (Comment as needed)
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GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (MFSRB) (Comment as needed)
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//GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO61 (MFSRB) (Comment as needed)
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/* Set qualification for selected input pins to asynch only */
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// This will select asynch (no qualification) for the selected pins.
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// Comment out other unwanted lines.
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GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO25 (MDRB) (Comment as needed)
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//GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (MDRB) (Comment as needed)
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GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO26(MCLKXB) (Comment as needed)
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//GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (MCLKXB) (Comment as needed)
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GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (MCLKRB) (Comment as needed)
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//GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (MCLKRB) (Comment as needed)
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GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO27 (MFSXB) (Comment as needed)
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//GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (MFSXB) (Comment as needed)
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GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; // Asynch input GPIO1 (MFSRB) (Comment as needed)
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//GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (MFSRB) (Comment as needed)
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EDIS;
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}
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#endif // end DSP28_MCBSPB
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void delay_loop(void)
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{
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long i;
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for (i = 0; i < MCBSP_INIT_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles
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}
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void clkg_delay_loop(void)
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{
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long i;
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for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} //delay in McBsp init. must be at least 2 SRG cycles
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}
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//===========================================================================
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// No more.
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//===========================================================================
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