384 lines
13 KiB
C
384 lines
13 KiB
C
// TI File $Revision: /main/5 $
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// Checkin $Date: May 12, 2008 09:34:58 $
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//###########################################################################
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//
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// FILE: DSP2833x_SysCtrl.h
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//
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// TITLE: DSP2833x Device System Control Register Definitions.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#ifndef DSP2833x_SYS_CTRL_H
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#define DSP2833x_SYS_CTRL_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// System Control Individual Register Bit Definitions:
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//
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// PLL Status Register
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struct PLLSTS_BITS { // bits description
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Uint16 PLLLOCKS:1; // 0 PLL lock status
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Uint16 rsvd1:1; // 1 reserved
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Uint16 PLLOFF:1; // 2 PLL off bit
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Uint16 MCLKSTS:1; // 3 Missing clock status bit
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Uint16 MCLKCLR:1; // 4 Missing clock clear bit
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Uint16 OSCOFF:1; // 5 Oscillator clock off
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Uint16 MCLKOFF:1; // 6 Missing clock detect
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Uint16 DIVSEL:2; // 7 Divide Select
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Uint16 rsvd2:7; // 15:7 reserved
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};
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union PLLSTS_REG {
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Uint16 all;
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struct PLLSTS_BITS bit;
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};
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// High speed peripheral clock register bit definitions:
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struct HISPCP_BITS { // bits description
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Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
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Uint16 rsvd1:13; // 15:3 reserved
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};
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union HISPCP_REG {
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Uint16 all;
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struct HISPCP_BITS bit;
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};
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// Low speed peripheral clock register bit definitions:
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struct LOSPCP_BITS { // bits description
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Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
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Uint16 rsvd1:13; // 15:3 reserved
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};
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union LOSPCP_REG {
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Uint16 all;
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struct LOSPCP_BITS bit;
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};
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// Peripheral clock control register 0 bit definitions:
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struct PCLKCR0_BITS { // bits description
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Uint16 rsvd1:2; // 1:0 reserved
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Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync
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Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
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Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A
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Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C
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Uint16 rsvd2:2; // 7:6 reserved
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Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A
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Uint16 rsvd3:1; // 9 reserved
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Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
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Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
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Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A
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Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B
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Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A
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Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B
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};
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union PCLKCR0_REG {
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Uint16 all;
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struct PCLKCR0_BITS bit;
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};
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// Peripheral clock control register 1 bit definitions:
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struct PCLKCR1_BITS { // bits description
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Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1
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Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2
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Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3
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Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4
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Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5
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Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6
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Uint16 rsvd1:2; // 7:6 reserved
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Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1
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Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2
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Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3
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Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4
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Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5
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Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6
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Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1
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Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2
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};
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union PCLKCR1_REG {
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Uint16 all;
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struct PCLKCR1_BITS bit;
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};
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// Peripheral clock control register 2 bit definitions:
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struct PCLKCR3_BITS { // bits description
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Uint16 rsvd1:8; // 7:0 reserved
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Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0
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Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1
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Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2
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Uint16 DMAENCLK:1; // 11 Enable the DMA clock
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Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF
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Uint16 GPIOINENCLK:1; // Enable GPIO input clock
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Uint16 rsvd2:2; // 15:14 reserved
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};
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union PCLKCR3_REG {
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Uint16 all;
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struct PCLKCR3_BITS bit;
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};
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// PLL control register bit definitions:
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struct PLLCR_BITS { // bits description
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Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
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Uint16 rsvd1:12; // 15:4 reserved
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};
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union PLLCR_REG {
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Uint16 all;
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struct PLLCR_BITS bit;
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};
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// Low Power Mode 0 control register bit definitions:
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struct LPMCR0_BITS { // bits description
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Uint16 LPM:2; // 1:0 Set the low power mode
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Uint16 QUALSTDBY:6; // 7:2 Qualification
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Uint16 rsvd1:7; // 14:8 reserved
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Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY
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};
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union LPMCR0_REG {
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Uint16 all;
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struct LPMCR0_BITS bit;
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};
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// Dual-mapping configuration register bit definitions:
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struct MAPCNF_BITS { // bits description
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Uint16 MAPEPWM:1; // 0 EPWM dual-map enable
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Uint16 rsvd1:15; // 15:1 reserved
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};
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union MAPCNF_REG {
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Uint16 all;
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struct MAPCNF_BITS bit;
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};
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//---------------------------------------------------------------------------
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// System Control Register File:
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//
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struct SYS_CTRL_REGS {
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Uint16 rsvd1; // 0
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union PLLSTS_REG PLLSTS; // 1
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Uint16 rsvd2[8]; // 2-9
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union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler
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union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
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union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register
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union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register
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union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
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Uint16 rsvd3; // 15: reserved
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union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register
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union PLLCR_REG PLLCR; // 17: PLL control register
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// No bit definitions are defined for SCSR because
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// a read-modify-write instruction can clear the WDOVERRIDE bit
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Uint16 SCSR; // 18: System control and status register
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Uint16 WDCNTR; // 19: WD counter register
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Uint16 rsvd4; // 20
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Uint16 WDKEY; // 21: WD reset key register
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Uint16 rsvd5[3]; // 22-24
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// No bit definitions are defined for WDCR because
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// the proper value must be written to the WDCHK field
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// whenever writing to this register.
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Uint16 WDCR; // 25: WD timer control register
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Uint16 rsvd6[4]; // 26-29
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union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register
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Uint16 rsvd7[1]; // 31
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};
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/* --------------------------------------------------- */
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/* CSM Registers */
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/* */
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/* ----------------------------------------------------*/
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/* CSM Status & Control register bit definitions */
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struct CSMSCR_BITS { // bit description
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Uint16 SECURE:1; // 0 Secure flag
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Uint16 rsvd1:14; // 14-1 reserved
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Uint16 FORCESEC:1; // 15 Force Secure control bit
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};
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/* Allow access to the bit fields or entire register */
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union CSMSCR_REG {
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Uint16 all;
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struct CSMSCR_BITS bit;
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};
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/* CSM Register File */
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struct CSM_REGS {
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Uint16 KEY0; // KEY reg bits 15-0
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Uint16 KEY1; // KEY reg bits 31-16
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Uint16 KEY2; // KEY reg bits 47-32
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Uint16 KEY3; // KEY reg bits 63-48
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Uint16 KEY4; // KEY reg bits 79-64
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Uint16 KEY5; // KEY reg bits 95-80
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Uint16 KEY6; // KEY reg bits 111-96
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Uint16 KEY7; // KEY reg bits 127-112
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Uint16 rsvd1; // reserved
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Uint16 rsvd2; // reserved
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Uint16 rsvd3; // reserved
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Uint16 rsvd4; // reserved
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Uint16 rsvd5; // reserved
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Uint16 rsvd6; // reserved
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Uint16 rsvd7; // reserved
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union CSMSCR_REG CSMSCR; // CSM Status & Control register
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};
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/* Password locations */
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struct CSM_PWL {
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Uint16 PSWD0; // PSWD bits 15-0
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Uint16 PSWD1; // PSWD bits 31-16
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Uint16 PSWD2; // PSWD bits 47-32
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Uint16 PSWD3; // PSWD bits 63-48
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Uint16 PSWD4; // PSWD bits 79-64
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Uint16 PSWD5; // PSWD bits 95-80
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Uint16 PSWD6; // PSWD bits 111-96
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Uint16 PSWD7; // PSWD bits 127-112
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};
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/* Flash Registers */
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#define FLASH_SLEEP 0x0000;
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#define FLASH_STANDBY 0x0001;
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#define FLASH_ACTIVE 0x0003;
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/* Flash Option Register bit definitions */
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struct FOPT_BITS { // bit description
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Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
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Uint16 rsvd:15; // 1-15 reserved
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};
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/* Allow access to the bit fields or entire register */
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union FOPT_REG {
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Uint16 all;
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struct FOPT_BITS bit;
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};
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/* Flash Power Modes Register bit definitions */
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struct FPWR_BITS { // bit description
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Uint16 PWR:2; // 0-1 Power Mode bits
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Uint16 rsvd:14; // 2-15 reserved
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};
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/* Allow access to the bit fields or entire register */
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union FPWR_REG {
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Uint16 all;
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struct FPWR_BITS bit;
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};
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/* Flash Status Register bit definitions */
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struct FSTATUS_BITS { // bit description
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Uint16 PWRS:2; // 0-1 Power Mode Status bits
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Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
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Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
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Uint16 rsvd1:4; // 4-7 reserved
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Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
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Uint16 rsvd2:7; // 9-15 reserved
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};
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/* Allow access to the bit fields or entire register */
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union FSTATUS_REG {
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Uint16 all;
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struct FSTATUS_BITS bit;
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};
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/* Flash Sleep to Standby Wait Counter Register bit definitions */
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struct FSTDBYWAIT_BITS { // bit description
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Uint16 STDBYWAIT:9; // 0-8 Bank/Pump Sleep to Standby Wait Count bits
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Uint16 rsvd:7; // 9-15 reserved
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};
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/* Allow access to the bit fields or entire register */
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union FSTDBYWAIT_REG {
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Uint16 all;
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struct FSTDBYWAIT_BITS bit;
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};
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/* Flash Standby to Active Wait Counter Register bit definitions */
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struct FACTIVEWAIT_BITS { // bit description
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Uint16 ACTIVEWAIT:9; // 0-8 Bank/Pump Standby to Active Wait Count bits
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Uint16 rsvd:7; // 9-15 reserved
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};
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/* Allow access to the bit fields or entire register */
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union FACTIVEWAIT_REG {
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Uint16 all;
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struct FACTIVEWAIT_BITS bit;
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};
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/* Bank Read Access Wait State Register bit definitions */
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struct FBANKWAIT_BITS { // bit description
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Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
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Uint16 rsvd1:4; // 4-7 reserved
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Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
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Uint16 rsvd2:4; // 12-15 reserved
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};
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/* Allow access to the bit fields or entire register */
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union FBANKWAIT_REG {
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Uint16 all;
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struct FBANKWAIT_BITS bit;
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};
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/* OTP Read Access Wait State Register bit definitions */
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struct FOTPWAIT_BITS { // bit description
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Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits
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Uint16 rsvd:11; // 5-15 reserved
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};
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/* Allow access to the bit fields or entire register */
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union FOTPWAIT_REG {
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Uint16 all;
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struct FOTPWAIT_BITS bit;
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};
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struct FLASH_REGS {
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union FOPT_REG FOPT; // Option Register
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Uint16 rsvd1; // reserved
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union FPWR_REG FPWR; // Power Modes Register
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union FSTATUS_REG FSTATUS; // Status Register
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union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register
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union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register
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union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
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union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
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};
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//---------------------------------------------------------------------------
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// System Control External References & Function Declarations:
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//
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extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
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extern volatile struct CSM_REGS CsmRegs;
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extern volatile struct CSM_PWL CsmPwl;
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extern volatile struct FLASH_REGS FlashRegs;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_SYS_CTRL_H definition
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//===========================================================================
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// End of file.
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//===========================================================================
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