424 lines
16 KiB
C
424 lines
16 KiB
C
// TI File $Revision: /main/1 $
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// Checkin $Date: August 18, 2006 13:52:10 $
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//###########################################################################
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//
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// FILE: DSP2833x_EPwm.h
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//
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// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#ifndef DSP2833x_EPWM_H
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#define DSP2833x_EPWM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//----------------------------------------------------
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// Time base control register bit definitions */
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struct TBCTL_BITS { // bits description
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Uint16 CTRMODE:2; // 1:0 Counter Mode
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Uint16 PHSEN:1; // 2 Phase load enable
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Uint16 PRDLD:1; // 3 Active period load
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Uint16 SYNCOSEL:2; // 5:4 Sync output select
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Uint16 SWFSYNC:1; // 6 Software force sync pulse
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Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale
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Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale
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Uint16 PHSDIR:1; // 13 Phase Direction
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Uint16 FREE_SOFT:2; // 15:14 Emulation mode
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};
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union TBCTL_REG {
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Uint16 all;
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struct TBCTL_BITS bit;
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};
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//----------------------------------------------------
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// Time base status register bit definitions */
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struct TBSTS_BITS { // bits description
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Uint16 CTRDIR:1; // 0 Counter direction status
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Uint16 SYNCI:1; // 1 External input sync status
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Uint16 CTRMAX:1; // 2 Counter max latched status
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Uint16 rsvd1:13; // 15:3 reserved
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};
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union TBSTS_REG {
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Uint16 all;
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struct TBSTS_BITS bit;
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};
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//----------------------------------------------------
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// Compare control register bit definitions */
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struct CMPCTL_BITS { // bits description
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Uint16 LOADAMODE:2; // 0:1 Active compare A
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Uint16 LOADBMODE:2; // 3:2 Active compare B
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Uint16 SHDWAMODE:1; // 4 Compare A block operating mode
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Uint16 rsvd1:1; // 5 reserved
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Uint16 SHDWBMODE:1; // 6 Compare B block operating mode
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Uint16 rsvd2:1; // 7 reserved
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Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status
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Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status
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Uint16 rsvd3:6; // 15:10 reserved
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};
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union CMPCTL_REG {
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Uint16 all;
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struct CMPCTL_BITS bit;
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};
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//----------------------------------------------------
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// Action qualifier register bit definitions */
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struct AQCTL_BITS { // bits description
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Uint16 ZRO:2; // 1:0 Action Counter = Zero
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Uint16 PRD:2; // 3:2 Action Counter = Period
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Uint16 CAU:2; // 5:4 Action Counter = Compare A up
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Uint16 CAD:2; // 7:6 Action Counter = Compare A down
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Uint16 CBU:2; // 9:8 Action Counter = Compare B up
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Uint16 CBD:2; // 11:10 Action Counter = Compare B down
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Uint16 rsvd:4; // 15:12 reserved
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};
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union AQCTL_REG {
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Uint16 all;
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struct AQCTL_BITS bit;
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};
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//----------------------------------------------------
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// Action qualifier SW force register bit definitions */
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struct AQSFRC_BITS { // bits description
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Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked
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Uint16 OTSFA:1; // 2 One-time SW Force A output
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Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked
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Uint16 OTSFB:1; // 5 One-time SW Force A output
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Uint16 RLDCSF:2; // 7:6 Reload from Shadow options
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Uint16 rsvd1:8; // 15:8 reserved
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};
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union AQSFRC_REG {
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Uint16 all;
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struct AQSFRC_BITS bit;
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};
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//----------------------------------------------------
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// Action qualifier continuous SW force register bit definitions */
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struct AQCSFRC_BITS { // bits description
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Uint16 CSFA:2; // 1:0 Continuous Software Force on output A
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Uint16 CSFB:2; // 3:2 Continuous Software Force on output B
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Uint16 rsvd1:12; // 15:4 reserved
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};
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union AQCSFRC_REG {
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Uint16 all;
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struct AQCSFRC_BITS bit;
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};
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// As of version 1.1
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// Changed the MODE bit-field to OUT_MODE
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// Added the bit-field IN_MODE
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// This corresponds to changes in silicon as of F2833x devices
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// Rev A silicon.
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//----------------------------------------------------
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// Dead-band generator control register bit definitions
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struct DBCTL_BITS { // bits description
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Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control
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Uint16 POLSEL:2; // 3:2 Polarity Select Control
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Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control
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Uint16 rsvd1:10; // 15:4 reserved
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};
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union DBCTL_REG {
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Uint16 all;
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struct DBCTL_BITS bit;
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};
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//----------------------------------------------------
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// Trip zone select register bit definitions
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struct TZSEL_BITS { // bits description
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Uint16 CBC1:1; // 0 TZ1 CBC select
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Uint16 CBC2:1; // 1 TZ2 CBC select
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Uint16 CBC3:1; // 2 TZ3 CBC select
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Uint16 CBC4:1; // 3 TZ4 CBC select
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Uint16 CBC5:1; // 4 TZ5 CBC select
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Uint16 CBC6:1; // 5 TZ6 CBC select
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Uint16 rsvd1:2; // 7:6 reserved
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Uint16 OSHT1:1; // 8 One-shot TZ1 select
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Uint16 OSHT2:1; // 9 One-shot TZ2 select
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Uint16 OSHT3:1; // 10 One-shot TZ3 select
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Uint16 OSHT4:1; // 11 One-shot TZ4 select
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Uint16 OSHT5:1; // 12 One-shot TZ5 select
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Uint16 OSHT6:1; // 13 One-shot TZ6 select
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Uint16 rsvd2:2; // 15:14 reserved
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};
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union TZSEL_REG {
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Uint16 all;
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struct TZSEL_BITS bit;
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};
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//----------------------------------------------------
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// Trip zone control register bit definitions */
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struct TZCTL_BITS { // bits description
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Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA
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Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB
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Uint16 rsvd:12; // 15:4 reserved
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};
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union TZCTL_REG {
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Uint16 all;
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struct TZCTL_BITS bit;
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};
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//----------------------------------------------------
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// Trip zone control register bit definitions */
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struct TZEINT_BITS { // bits description
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Uint16 rsvd1:1; // 0 reserved
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Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable
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Uint16 OST:1; // 2 Trip Zones One Shot Int Enable
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Uint16 rsvd2:13; // 15:3 reserved
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};
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union TZEINT_REG {
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Uint16 all;
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struct TZEINT_BITS bit;
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};
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//----------------------------------------------------
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// Trip zone flag register bit definitions */
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struct TZFLG_BITS { // bits description
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Uint16 INT:1; // 0 Global status
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Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
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Uint16 OST:1; // 2 Trip Zones One Shot Int
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Uint16 rsvd2:13; // 15:3 reserved
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};
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union TZFLG_REG {
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Uint16 all;
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struct TZFLG_BITS bit;
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};
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//----------------------------------------------------
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// Trip zone flag clear register bit definitions */
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struct TZCLR_BITS { // bits description
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Uint16 INT:1; // 0 Global status
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Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
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Uint16 OST:1; // 2 Trip Zones One Shot Int
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Uint16 rsvd2:13; // 15:3 reserved
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};
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union TZCLR_REG {
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Uint16 all;
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struct TZCLR_BITS bit;
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};
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//----------------------------------------------------
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// Trip zone flag force register bit definitions */
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struct TZFRC_BITS { // bits description
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Uint16 rsvd1:1; // 0 reserved
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Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
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Uint16 OST:1; // 2 Trip Zones One Shot Int
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Uint16 rsvd2:13; // 15:3 reserved
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};
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union TZFRC_REG {
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Uint16 all;
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struct TZFRC_BITS bit;
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};
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//----------------------------------------------------
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// Event trigger select register bit definitions */
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struct ETSEL_BITS { // bits description
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Uint16 INTSEL:3; // 2:0 EPWMxINTn Select
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Uint16 INTEN:1; // 3 EPWMxINTn Enable
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Uint16 rsvd1:4; // 7:4 reserved
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Uint16 SOCASEL:3; // 10:8 Start of conversion A Select
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Uint16 SOCAEN:1; // 11 Start of conversion A Enable
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Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select
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Uint16 SOCBEN:1; // 15 Start of conversion B Enable
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};
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union ETSEL_REG {
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Uint16 all;
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struct ETSEL_BITS bit;
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};
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//----------------------------------------------------
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// Event trigger pre-scale register bit definitions */
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struct ETPS_BITS { // bits description
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Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select
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Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register
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Uint16 rsvd1:4; // 7:4 reserved
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Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select
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Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register
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Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select
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Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register
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};
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union ETPS_REG {
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Uint16 all;
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struct ETPS_BITS bit;
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};
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//----------------------------------------------------
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// Event trigger Flag register bit definitions */
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struct ETFLG_BITS { // bits description
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Uint16 INT:1; // 0 EPWMxINTn Flag
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Uint16 rsvd1:1; // 1 reserved
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Uint16 SOCA:1; // 2 EPWMxSOCA Flag
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Uint16 SOCB:1; // 3 EPWMxSOCB Flag
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Uint16 rsvd2:12; // 15:4 reserved
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};
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union ETFLG_REG {
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Uint16 all;
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struct ETFLG_BITS bit;
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};
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//----------------------------------------------------
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// Event trigger Clear register bit definitions */
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struct ETCLR_BITS { // bits description
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Uint16 INT:1; // 0 EPWMxINTn Clear
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Uint16 rsvd1:1; // 1 reserved
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Uint16 SOCA:1; // 2 EPWMxSOCA Clear
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Uint16 SOCB:1; // 3 EPWMxSOCB Clear
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Uint16 rsvd2:12; // 15:4 reserved
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};
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union ETCLR_REG {
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Uint16 all;
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struct ETCLR_BITS bit;
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};
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//----------------------------------------------------
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// Event trigger Force register bit definitions */
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struct ETFRC_BITS { // bits description
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Uint16 INT:1; // 0 EPWMxINTn Force
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Uint16 rsvd1:1; // 1 reserved
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Uint16 SOCA:1; // 2 EPWMxSOCA Force
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Uint16 SOCB:1; // 3 EPWMxSOCB Force
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Uint16 rsvd2:12; // 15:4 reserved
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};
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union ETFRC_REG {
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Uint16 all;
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struct ETFRC_BITS bit;
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};
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//----------------------------------------------------
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// PWM chopper control register bit definitions */
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struct PCCTL_BITS { // bits description
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Uint16 CHPEN:1; // 0 PWM chopping enable
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Uint16 OSHTWTH:4; // 4:1 One-shot pulse width
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Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency
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Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle
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Uint16 rsvd1:5; // 15:11 reserved
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};
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union PCCTL_REG {
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Uint16 all;
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struct PCCTL_BITS bit;
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};
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struct HRCNFG_BITS { // bits description
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Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits
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Uint16 CTLMODE:1; // 2 Control mode Select Bit
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Uint16 HRLOAD:1; // 3 Shadow mode Select Bit
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Uint16 rsvd1:12; // 15:4 reserved
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};
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union HRCNFG_REG {
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Uint16 all;
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struct HRCNFG_BITS bit;
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};
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struct TBPHS_HRPWM_REG { // bits description
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Uint16 TBPHSHR; // 15:0 Extension register for HRPWM Phase (8 bits)
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Uint16 TBPHS; // 31:16 Phase offset register
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};
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union TBPHS_HRPWM_GROUP {
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Uint32 all;
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struct TBPHS_HRPWM_REG half;
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};
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struct CMPA_HRPWM_REG { // bits description
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Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits)
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Uint16 CMPA; // 31:16 Compare A reg
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};
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union CMPA_HRPWM_GROUP {
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Uint32 all;
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struct CMPA_HRPWM_REG half;
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};
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struct EPWM_REGS {
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union TBCTL_REG TBCTL; //
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union TBSTS_REG TBSTS; //
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union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR
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Uint16 TBCTR; // Counter
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Uint16 TBPRD; // Period register set
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Uint16 rsvd1; //
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union CMPCTL_REG CMPCTL; // Compare control
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union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR
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Uint16 CMPB; // Compare B reg
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union AQCTL_REG AQCTLA; // Action qual output A
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union AQCTL_REG AQCTLB; // Action qual output B
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union AQSFRC_REG AQSFRC; // Action qual SW force
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union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force
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union DBCTL_REG DBCTL; // Dead-band control
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Uint16 DBRED; // Dead-band rising edge delay
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Uint16 DBFED; // Dead-band falling edge delay
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union TZSEL_REG TZSEL; // Trip zone select
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Uint16 rsvd2;
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union TZCTL_REG TZCTL; // Trip zone control
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union TZEINT_REG TZEINT; // Trip zone interrupt enable
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union TZFLG_REG TZFLG; // Trip zone interrupt flags
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union TZCLR_REG TZCLR; // Trip zone clear
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union TZFRC_REG TZFRC; // Trip zone force interrupt
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union ETSEL_REG ETSEL; // Event trigger selection
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union ETPS_REG ETPS; // Event trigger pre-scaler
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union ETFLG_REG ETFLG; // Event trigger flags
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union ETCLR_REG ETCLR; // Event trigger clear
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union ETFRC_REG ETFRC; // Event trigger force
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union PCCTL_REG PCCTL; // PWM chopper control
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Uint16 rsvd3; //
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union HRCNFG_REG HRCNFG; // HRPWM Config Reg
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};
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//---------------------------------------------------------------------------
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// External References & Function Declarations:
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//
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extern volatile struct EPWM_REGS EPwm1Regs;
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extern volatile struct EPWM_REGS EPwm2Regs;
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extern volatile struct EPWM_REGS EPwm3Regs;
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extern volatile struct EPWM_REGS EPwm4Regs;
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extern volatile struct EPWM_REGS EPwm5Regs;
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extern volatile struct EPWM_REGS EPwm6Regs;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_EPWM_H definition
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//===========================================================================
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// End of file.
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//===========================================================================
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