356 lines
9.2 KiB
C
356 lines
9.2 KiB
C
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
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#include "DSP2833x_SWPrioritizedIsrLevels.h"
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#include "filter_bat2.h"
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#include "measure.h"
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#include "package.h" // DSP281x Headerfile Include File
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#include "peripher.h" // DSP281x Headerfile Include File
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#include "ecan.h" // DSP281x Headerfile Include File
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#include "tools.h" // DSP281x Headerfile Include File
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#include "RS485.h"
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#include "message.h"
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// Prototype statements for functions found within this file.
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interrupt void CANa_handler(void);
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interrupt void CANa_reset_err(void);
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interrupt void CANb_handler(void);
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interrupt void CANb_reset_err(void);
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// Global variable for this example
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Uint32 ErrorCount;
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Uint32 MessageReceivedCount;
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Uint32 MessageTransivedCount=0;
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Uint32 TestMbox1 = 0;
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Uint32 TestMbox2 = 0;
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Uint32 TestMbox3 = 0;
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int CanTimeOutErrorTR = 0;
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int wait=0;
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void Init_Can(int Port, int DevNum)
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{
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struct ECAN_REGS ECanShadow;
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volatile struct ECAN_REGS * ECanRegs;
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volatile struct ECAN_MBOXES * ECanMboxes;
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volatile struct MOTO_REGS * ECanMOTORegs;
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long id = 0x801CE000;
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if(DevNum<0)DevNum=0;
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if(DevNum>15)DevNum=15;
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// Configure CAN pins using GPIO regs here
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EALLOW;
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if(!Port)
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{
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ECanRegs = &ECanaRegs;
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ECanMboxes = &ECanaMboxes;
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ECanMOTORegs = &ECanaMOTORegs;
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GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;
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GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;
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}
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else
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{
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ECanRegs = &ECanbRegs;
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ECanMboxes = &ECanbMboxes;
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ECanMOTORegs = &ECanbMOTORegs;
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GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;
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GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;
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}
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// Configure the eCAN RX and TX pins for eCAN transmissions
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ECanRegs->CANTIOC.all = 8; // only 3rd bit, TXFUNC, is significant
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ECanRegs->CANRIOC.all = 8; // only 3rd bit, RXFUNC, is significant
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// Specify that 8 bits will be sent/received
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ECanMboxes->MBOX0.MSGCTRL.all = 0x00000008;
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ECanMboxes->MBOX1.MSGCTRL.all = 0x00000008;
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ECanMboxes->MBOX2.MSGCTRL.all = 0x00000008;
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// Disable all Mailboxes
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// Required before writing the MSGIDs
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ECanRegs->CANME.all = 0;
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// <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> 0 <20><><EFBFBD><EFBFBD>a <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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ECanMboxes->MBOX0.MSGID.all = id + DevNum;
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// <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> 1 <20><><EFBFBD><EFBFBD>a <20><> <20><><EFBFBD><EFBFBD><EFBFBD>
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ECanMboxes->MBOX1.MSGID.all = id + 0x20 + DevNum;
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// <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> 2 <20><><EFBFBD><EFBFBD>a <20><> <20><><EFBFBD><EFBFBD><EFBFBD>
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ECanMboxes->MBOX2.MSGID.all = id + 0x30 + (DevNum&1);
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// <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>a 0 <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD>
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ECanRegs->CANMD.all = 0xFFFFFFFE;
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// <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 3 <20><><EFBFBD><EFBFBD>a <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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ECanRegs->CANME.all = 0x00000007;
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// Clear all TAn bits
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ECanRegs->CANTA.all = 0xFFFFFFFF;
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// Clear all RMPn bits
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ECanRegs->CANRMP.all = 0xFFFFFFFF;
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// Clear all interrupt flag bits
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ECanRegs->CANGIF0.all = 0xFFFFFFFF;
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ECanRegs->CANGIF1.all = 0xFFFFFFFF;
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// Clear all error and status bits
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ECanRegs->CANES.all=0xffffffff;
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// Request permission to change the configuration registers
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ECanShadow.CANMC.all = 0;
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ECanShadow.CANMC.bit.MBCC = 1; // Mailbox timestamp counter clear bit
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ECanShadow.CANMC.bit.TCC = 1; // Time stamp counter MSB clear bit
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ECanShadow.CANMC.bit.SCB = 1; // eCAN mode (reqd to access 32 mailboxes)
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ECanShadow.CANMC.bit.WUBA = 1; // Wake up on bus activity
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ECanShadow.CANMC.bit.ABO = 1; // Auto bus on
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ECanShadow.CANMC.bit.CCR = 1;
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// ECanShadow.CANMC.bit.STM = 1; // self-test loop-back
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ECanRegs->CANMC.all = ECanShadow.CANMC.all;
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while(!ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be set..
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> CAN
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ECanShadow.CANBTC.all = ECanRegs->CANBTC.all;
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ECanShadow.CANBTC.bit.BRPREG = 14;//49; // (BRPREG + 1) = 10 feeds a 15 MHz CAN clock
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ECanShadow.CANBTC.bit.TSEG2REG = 2; // to the CAN module. (150 / 10 = 15)
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ECanShadow.CANBTC.bit.TSEG1REG = 15;//10; // Bit time = 15
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ECanShadow.CANBTC.bit.SJWREG=1;
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// 14,2,15 <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>. 49 2 10 for 745
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ECanRegs->CANBTC.all = ECanShadow.CANBTC.all;
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ECanShadow.CANMC.bit.CCR = 0; // Set CCR = 0
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ECanRegs->CANMC.all = ECanShadow.CANMC.all;
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while(ECanRegs->CANES.bit.CCE); // Wait for CCE bit to be cleared..
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// <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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ECanMOTORegs->MOTO0 = 550000;
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ECanMOTORegs->MOTO1 = 550000;
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ECanRegs->CANTOC.all = 1;
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ECanRegs->CANTOS.all = 0; // clear all time-out flags
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ECanRegs->CANTSC = 0; // clear time-out counter
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ECanShadow.CANGIM.all = 0;
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ECanRegs->CANMIM.all = 2+4; // Enable interrupts of box 1
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ECanRegs->CANMIL.all = 0x00000000; // All mailbox interrupts are generated on interrupt line 0.
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ECanShadow.CANGIM.bit.I0EN = 1;
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ECanShadow.CANGIM.bit.MTOM = 1;
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ECanShadow.CANGIM.bit.I1EN = 1;
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ECanShadow.CANGIM.bit.GIL = 1;
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ECanRegs->CANGIM.all = ECanShadow.CANGIM.all;
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if(!Port)
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{
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PieVectTable.ECAN0INTA = &CANa_handler;
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PieCtrlRegs.PIEIER9.bit.INTx5=1; // PIE Group 9, INT6
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PieVectTable.ECAN1INTA = &CANa_reset_err;
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PieCtrlRegs.PIEIER9.bit.INTx6=1; // PIE Group 9, INT6
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}
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else
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{
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PieVectTable.ECAN0INTB = &CANb_handler;
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PieCtrlRegs.PIEIER9.bit.INTx7=1; // PIE Group 9, INT6
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PieVectTable.ECAN1INTB = &CANb_reset_err;
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PieCtrlRegs.PIEIER9.bit.INTx8=1; // PIE Group 9, INT6
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}
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IER |= M_INT9; // Enable CPU INT
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EDIS;
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> CAN <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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MessageReceivedCount = 0;
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ErrorCount = 0;
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CanTimeOutErrorTR=0;
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MessageTransivedCount=0;
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}
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void CAN_send(int Port, int data[], int Addr)
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{
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unsigned long hiword,loword;
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volatile struct ECAN_REGS * ECanRegs;
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volatile struct ECAN_MBOXES * ECanMboxes;
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if(!Port)
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{
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ECanRegs = &ECanaRegs;
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ECanMboxes = &ECanaMboxes;
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}
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else
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{
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#ifdef TUBER
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ECanRegs = &ECanbRegs;
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ECanMboxes = &ECanbMboxes;
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#endif
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}
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if(wait)
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if(!(ECanRegs->CANTA.all & 1))
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if(!(ECanRegs->CANAA.all & 1))
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return;
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ECanRegs->CANTA.all = 1;
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ECanRegs->CANAA.all = 1;
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hiword= ((((Uint32) Addr ) & 0xffff)<<16)| 0xE0000000 |
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((((Uint32)data[Addr ]) & 0xffff) );
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loword= ((((Uint32)data[Addr+1]) & 0xffff)<<16)|
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((((Uint32)data[Addr+2]) & 0xffff) );
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ECanMboxes->MBOX0.MDH.all = hiword;
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ECanMboxes->MBOX0.MDL.all = loword;
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EALLOW;
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ECanRegs->CANTSC = 0; // clear time-out counter
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EDIS;
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ECanRegs->CANTRS.all = 1; // <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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wait=1;
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if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO52=1;
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if(Desk==dsk_ISOL) GpioDataRegs.GPATOGGLE.bit.GPIO27=1;
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if(Desk==dsk_SHKF) GpioDataRegs.GPBTOGGLE.bit.GPIO63=1;
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// led1_toggle();
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}
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void Handlai(volatile struct MBOX * ECanMbox)
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{
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unsigned int adr;
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unsigned int bit[3];
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unsigned long hiword,loword;
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int Data[3];
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hiword = ECanMbox->MDH.all;
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loword = ECanMbox->MDL.all;
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adr = (hiword >> 16);
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bit[0] = adr & 0x8000;
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bit[1] = adr & 0x4000;
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bit[2] = adr & 0x2000;
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adr &= 0x1fff;
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Data[0] = (hiword ) & 0xffff;
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Data[1] = (loword>>16) & 0xffff;
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Data[2] = (loword ) & 0xffff;
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if(bit[0]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[0]; adr++;
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if(bit[1]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[1]; adr++;
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if(bit[2]) if(adr < ANSWER_LEN) Modbus[adr].all = Data[2];
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if(Desk==dsk_COMM) GpioDataRegs.GPBTOGGLE.bit.GPIO49=1;
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else
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led2_toggle();
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}
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interrupt void CANa_handler(void)
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{
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unsigned long mask=1;
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int box;
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
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IER |= M_INT9;
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IER &= MINT9; // Set "global" priority
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PieCtrlRegs.PIEIER9.all &= MG95; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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box = ECanaRegs.CANGIF0.bit.MIV0;
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mask <<= box;
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ECanaRegs.CANRMP.all = mask;
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Handlai(&ECanaMboxes.MBOX0 + box);
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PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER9.all = TempPIEIER;
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}
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interrupt void CANa_reset_err(void)
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{
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
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IER |= M_INT9;
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IER &= MINT9; // Set "global" priority
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PieCtrlRegs.PIEIER9.all &= MG96; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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ECanaRegs.CANTRR.all = 1;
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CanTimeOutErrorTR++;
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PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER9.all = TempPIEIER;
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}
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interrupt void CANb_handler(void)
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{
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#ifdef TUBER
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unsigned long mask=1;
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int box;
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
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IER |= M_INT9;
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IER &= MINT9; // Set "global" priority
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PieCtrlRegs.PIEIER9.all &= MG97; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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box = ECanbRegs.CANGIF0.bit.MIV0;
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mask <<= box;
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ECanbRegs.CANRMP.all = mask;
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Handlai(&ECanbMboxes.MBOX0 + box);
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PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER9.all = TempPIEIER;
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#endif
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}
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interrupt void CANb_reset_err(void)
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{
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#ifdef TUBER
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// Set interrupt priority:
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volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER9.all;
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IER |= M_INT9;
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IER &= MINT9; // Set "global" priority
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PieCtrlRegs.PIEIER9.all &= MG98; // Set "group" priority
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PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
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EINT;
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ECanbRegs.CANTRR.all = 1;
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CanTimeOutErrorTR++;
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PieCtrlRegs.PIEACK.bit.ACK9 |= 1;
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// Restore registers saved:
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DINT;
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PieCtrlRegs.PIEIER9.all = TempPIEIER;
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#endif
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}
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//===========================================================================
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// No more.
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//===========================================================================
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