#include "DSP2833x_Device.h" // DSP281x Headerfile Include File // Configure the timing paramaters for Zone 7. // Notes: // This function should not be executed from XINTF // Adjust the timing based on the data manual and // external device requirements. void init_zone7(void) { // Make sure the XINTF clock is enabled SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // Configure the GPIO for XINTF with a 16-bit data bus // This function is in DSP2833x_Xintf.c InitXintf16Gpio(); EALLOW; // All Zones--------------------------------- // Timing for all zones based on XTIMCLK = SYSCLKOUT XintfRegs.XINTCNF2.bit.XTIMCLK = 0; // Buffer up to 3 writes XintfRegs.XINTCNF2.bit.WRBUFF = 3; // XCLKOUT is enabled XintfRegs.XINTCNF2.bit.CLKOFF = 0; // XCLKOUT = XTIMCLK XintfRegs.XINTCNF2.bit.CLKMODE = 0; // Zone 7------------------------------------ // When using ready, ACTIVE must be 1 or greater // Lead must always be 1 or greater // Zone write timing XintfRegs.XTIMING7.bit.XWRLEAD = 1; XintfRegs.XTIMING7.bit.XWRACTIVE = 2; XintfRegs.XTIMING7.bit.XWRTRAIL = 1; // Zone read timing XintfRegs.XTIMING7.bit.XRDLEAD = 1; XintfRegs.XTIMING7.bit.XRDACTIVE = 3; XintfRegs.XTIMING7.bit.XRDTRAIL = 0; // don't double all Zone read/write lead/active/trail timing XintfRegs.XTIMING7.bit.X2TIMING = 0; // Zone will not sample XREADY signal XintfRegs.XTIMING7.bit.USEREADY = 0; XintfRegs.XTIMING7.bit.READYMODE = 0; // 1,1 = x16 data bus // 0,1 = x32 data bus // other values are reserved XintfRegs.XTIMING7.bit.XSIZE = 3; EDIS; //Force a pipeline flush to ensure that the write to //the last register configured occurs before returning. asm(" RPT #7 || NOP"); } void setup_leds_line() { EALLOW; GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 0; GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; GpioCtrlRegs.GPBDIR.bit.GPIO48 = 1; EDIS; } void pause_us(unsigned long t) { unsigned long i; //unsigned long powse; t = t >> 1; for (i = 0; i < t; i++) { DSP28x_usDelay(40L); // powse=40L; // for(powse=0; powse<40; powse++); } }