547 lines
20 KiB
C
547 lines
20 KiB
C
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// TI File $Revision: /main/15 $
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// Checkin $Date: May 5, 2008 15:25:56 $
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//###########################################################################
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//
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// FILE: Example_2833xHRPWM_SFO.c
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//
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// TITLE: DSP2833x Device HRPWM example
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//
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// ASSUMPTIONS:
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//
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//
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// This program requires the DSP2833x header files, which include the
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// SFO_TI_Build_fpu.lib (or SFO_TI_Build.lib for fixed-point) and SFO.h
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// files required by this example.
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//
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// !!NOTE!!
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// By default, this example project is configured for floating-point math. All
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// included libraries must be pre-compiled for floating-point math.
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//
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// Therefore, SFO_TI_Build_fpu.lib (compiled for floating-point) is included in the
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// project instead of the SFO_TI_Build.lib (compiled for fixed-point).
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//
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// To convert the example for fixed-point math, follow the instructions in sfo_readme.txt
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// in the /doc directory of the header files and peripheral examples package.
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//
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//
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// Monitor ePWM1-ePWM4 pins on an oscilloscope as described
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// below.
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//
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// EPWM1A is on GPIO0
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// EPWM2A is on GPIO2
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// EPWM3A is on GPIO4
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// EPWM4A is on GPIO6
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//
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// As supplied, this project is configured for "boot to SARAM"
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// operation. The 2833x Boot Mode table is shown below.
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// For information on configuring the boot mode of an eZdsp,
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// please refer to the documentation included with the eZdsp,
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//
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// $Boot_Table:
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//
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// GPIO87 GPIO86 GPIO85 GPIO84
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// XA15 XA14 XA13 XA12
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// PU PU PU PU
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// ==========================================
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// 1 1 1 1 Jump to Flash
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// 1 1 1 0 SCI-A boot
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// 1 1 0 1 SPI-A boot
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// 1 1 0 0 I2C-A boot
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// 1 0 1 1 eCAN-A boot
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// 1 0 1 0 McBSP-A boot
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// 1 0 0 1 Jump to XINTF x16
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// 1 0 0 0 Jump to XINTF x32
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// 0 1 1 1 Jump to OTP
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// 0 1 1 0 Parallel GPIO I/O boot
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// 0 1 0 1 Parallel XINTF boot
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// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
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// 0 0 1 1 Branch to check boot mode
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// 0 0 1 0 Boot to flash, bypass ADC cal
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// 0 0 0 1 Boot to SARAM, bypass ADC cal
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// 0 0 0 0 Boot to SCI-A, bypass ADC cal
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// Boot_Table_End$
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//
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// DESCRIPTION:
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//
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// This example modifies the MEP control registers to show edge displacement
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// due to the HRPWM control extension of the respective ePWM module.
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//
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// This example calls the following TI's MEP Scale Factor Optimizer (SFO)
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// software library functions:
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//
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// void SFO_MepEn(int i);
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// initialize MEP_Scalefactor[i] dynamically when HRPWM is in use.
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//
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// void SFO_MepDis(int i);
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// initialize MEP_Scalefactor[i] when HRPWM is not used
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//
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// Where MEP_ScaleFactor[5] is a global array variable used by the SFO library
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//
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// This example is intended to explain the HRPWM capabilities. The code can be
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// optimized for code efficiency. Refer to TI's Digital power application
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// examples and TI Digital Power Supply software libraries for details.
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//
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// All ePWM1A,2A,3A,4A channels (GPIO0, GPIO2, GPIO4, GPIO6) will have fine
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// edge movement due to the HRPWM logic
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//
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// 1. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz), ePWM1A toggle low/high with MEP control on falling edge
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//
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// 2. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM2A toggle low/high with MEP control on falling edge
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//
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// 3. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM3A toggle high/low with MEP control on falling edge
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//
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// 4. 5MHz PWM (SYSCLK=150MHz) or 3.33MHz PWM (SYSCLK=100MHz) ePWM4A toggle high/low with MEP control on falling edge
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//
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// To load and run this example:
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// 1. Run this example at 150MHz SYSCLKOUT (or 100 MHz SYSCLKOUT for 100 MHz devices)
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// 2. Load the Example_2833xHRPWM_SFO.gel and observe variables in the watch window
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// 3. Activate Real time mode
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// 4. Run the code
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// 5. Watch ePWM1A-4A waveforms on a Oscillosope
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// 6. In the watch window:
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// Set the variable UpdateFine = 1 to observe the ePWMxA output
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// with HRPWM capabilites (default)
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// Observe the duty cycle of the waveform changes in fine MEP steps
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// 7. In the watch window:
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// Change the variable UpdateFine to 0, to observe the
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// ePWMxA output without HRPWM capabilites
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// Observe the duty cycle of the waveform changes in coarse steps of 10nsec.
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//
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//
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// Watch Variables:
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// UpdateFine
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// MEP_ScaleFactor
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// EPwm1Regs.CMPA.all
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// EPwm2Regs.CMPA.all
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// EPwm3Regs.CMPA.all
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// EPwm4Regs.CMPA.all
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//
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//
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// IMPORTANT NOTE!!!!!
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//
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// THE SFO.H FUNCTIONS INCLUDED WITH THIS EXAMPLE ONLY SUPPORTS EPWM1-EPWM4. FOR
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// SUPPORT FOR MORE THAN 4 EPWMS, USE SFO_V5.H WITH THE SFO_TI_BUILD_V5.LIB LIBRARY.
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// SEE THE HRPWM REFERENCE GUIDE (SPRU924) FOR USAGE INFORMATION AND DIFFERENCES
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// BETWEEN VERSIONS.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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#include "DSP2833x_EPwm_defines.h" // useful defines for initialization
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#include "SFO.h" // SFO library headerfile
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// Declare your function prototypes here
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//---------------------------------------------------------------
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void HRPWM1_Config(int);
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void HRPWM2_Config(int);
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void HRPWM3_Config(int);
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void HRPWM4_Config(int);
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// General System nets - Useful for debug
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Uint16 j,duty, DutyFine, n, UpdateFine;
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volatile int i;
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Uint32 temp;
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// Global array used by the SFO library
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int16 MEP_ScaleFactor[5];
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volatile struct EPWM_REGS *ePWM[] =
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{ &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm5Regs, &EPwm6Regs};
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void main(void)
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{
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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InitSysCtrl();
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// Step 2. Initalize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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// InitGpio(); // Skipped for this example
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// For this case, just init GPIO for ePWM1-ePWM4
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// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4
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// These functions are in the DSP2833x_EPwm.c file
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InitEPwm1Gpio();
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InitEPwm2Gpio();
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InitEPwm3Gpio();
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InitEPwm4Gpio();
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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DINT;
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// Initialize the PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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InitPieCtrl();
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// Disable CPU interrupts and clear all CPU interrupt flags:
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IER = 0x0000;
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IFR = 0x0000;
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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InitPieVectTable();
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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// InitPeripherals(); // Not required for this example
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// For this example, only initialize the ePWM
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// Step 5. User specific code, enable interrupts:
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UpdateFine = 1;
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DutyFine = 0;
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
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EDIS;
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// MEP_ScaleFactor variables iitialization for SFO library functions
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MEP_ScaleFactor[0] = 0; //Common Variables for SFO functions
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MEP_ScaleFactor[1] = 0; //SFO for HRPWM1
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MEP_ScaleFactor[2] = 0; //SFO for HRPWM2
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MEP_ScaleFactor[3] = 0; //SFO for HRPWM3
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MEP_ScaleFactor[4] = 0; //SFO for HRPWM4
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// MEP_ScaleFactor variables initialized using function SFO_MepDis
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while ( MEP_ScaleFactor[1] == 0 ) SFO_MepDis(1); //SFO for HRPWM1
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while ( MEP_ScaleFactor[2] == 0 ) SFO_MepDis(2); //SFO for HRPWM2
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while ( MEP_ScaleFactor[3] == 0 ) SFO_MepDis(3); //SFO for HRPWM3
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while ( MEP_ScaleFactor[4] == 0 ) SFO_MepDis(4); //SFO for HRPWM4
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// Initialize a common seed variable MEP_ScaleFactor[0] required for all SFO functions
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MEP_ScaleFactor[0] = MEP_ScaleFactor[1]; //Common Variable for SFO library functions
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/// Some useful Period vs Frequency values
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// SYSCLKOUT = 150MHz 100 MHz
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// -----------------------------------------
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// Period Frequency Frequency
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// 1000 150 kHz 100 KHz
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// 800 187 kHz 125 KHz
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// 600 250 kHz 167 KHz
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// 500 300 kHz 200 KHz
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// 250 600 kHz 400 KHz
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// 200 750 kHz 500 KHz
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// 100 1.5 MHz 1.0 MHz
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// 50 3.0 MHz 2.0 MHz
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// 30 5.0 MHz 3.33 MHz
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// 25 6.0 MHz 4.0 MHz
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// 20 7.5 MHz 5.0 MHz
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// 12 12.5 MHz 8.33 MHz
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// 10 15.0 MHz 10.0 MHz
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// 9 16.7 MHz 11.1 MHz
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// 8 18.8 MHz 12.5 MHz
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// 7 21.4 MHz 14.3 MHz
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// 6 25.0 MHz 16.7 MHz
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// 5 30.0 MHz 20.0 MHz
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//====================================================================
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// ePWM and HRPWM register initializaition
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//====================================================================
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HRPWM1_Config(30); // ePWM1 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz)
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HRPWM2_Config(30); // ePWM2 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz)
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HRPWM3_Config(30); // ePWM3 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz)
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HRPWM4_Config(30); // ePWM4 target, 5 MHz PWM (SYSCLK=150MHz) or 3.33 MHz PWM (SYSCLK=100MHz)
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
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EDIS;
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for(;;)
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{
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// Sweep DutyFine as a Q15 number from 0.2 - 0.999
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for(DutyFine = 0x2300; DutyFine < 0x7000; DutyFine++)
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{
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// Variables
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int16 CMPA_reg_val, CMPAHR_reg_val;
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int32 temp;
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if(UpdateFine)
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{
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/*
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// CMPA_reg_val is calculated as a Q0.
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// Since DutyFine is a Q15 number, and the period is Q0
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// the product is Q15. So to store as a Q0, we shift right
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// 15 bits.
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CMPA_reg_val = ((long)DutyFine * EPwm1Regs.TBPRD)>>15;
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// This next step is to obtain the remainder which was
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// truncated during our 15 bit shift above.
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// compute the whole value, and then subtract CMPA_reg_val
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// shifted LEFT 15 bits:
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temp = ((long)DutyFine * EPwm1Regs.TBPRD) ;
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temp = temp - ((long)CMPA_reg_val<<15);
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// This obtains the MEP count in digits, from
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// 0,1, .... MEP_Scalefactor. Once again since this is Q15
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// convert to Q0 by shifting:
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CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15;
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// Now the lower 8 bits contain the MEP count.
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// Since the MEP count needs to be in the upper 8 bits of
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// the 16 bit CMPAHR register, shift left by 8.
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CMPAHR_reg_val = CMPAHR_reg_val << 8;
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// Add the offset and rounding
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CMPAHR_reg_val += 0x0180;
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// Write the values to the registers as one 32-bit or two 16-bits
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EPwm1Regs.CMPA.half.CMPA = CMPA_reg_val;
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EPwm1Regs.CMPA.half.CMPAHR = CMPAHR_reg_val;
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*/
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// All the above operations may be condensed into
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// the following form:
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// EPWM1 calculations
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CMPA_reg_val = ((long)DutyFine * EPwm1Regs.TBPRD)>>15;
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temp = ((long)DutyFine * EPwm1Regs.TBPRD) ;
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temp = temp - ((long)CMPA_reg_val<<15);
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CMPAHR_reg_val = (temp*MEP_ScaleFactor[1])>>15;
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CMPAHR_reg_val = CMPAHR_reg_val << 8;
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CMPAHR_reg_val += 0x0180;
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// Example for a 32 bit write to CMPA:CMPAHR
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EPwm1Regs.CMPA.all = ((long)CMPA_reg_val)<<16 | CMPAHR_reg_val;
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// EPWM2 calculations
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CMPA_reg_val = ((long)DutyFine * EPwm2Regs.TBPRD)>>15;
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temp = ((long)DutyFine * EPwm2Regs.TBPRD) ;
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temp = temp - ((long)CMPA_reg_val<<15);
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CMPAHR_reg_val = (temp*MEP_ScaleFactor[2])>>15;
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CMPAHR_reg_val = CMPAHR_reg_val << 8;
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CMPAHR_reg_val += 0x0180;
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// Example as a 16 bit write to CMPA and then a 16-bit write to CMPAHR
|
||
|
|
EPwm2Regs.CMPA.half.CMPA = CMPA_reg_val;
|
||
|
|
EPwm2Regs.CMPA.half.CMPAHR = CMPAHR_reg_val;
|
||
|
|
|
||
|
|
// EPWM3 calculations
|
||
|
|
CMPA_reg_val = ((long)DutyFine * EPwm3Regs.TBPRD)>>15;
|
||
|
|
temp = ((long)DutyFine * EPwm3Regs.TBPRD) ;
|
||
|
|
temp = temp - ((long)CMPA_reg_val<<15);
|
||
|
|
CMPAHR_reg_val = (temp*MEP_ScaleFactor[3])>>15;
|
||
|
|
CMPAHR_reg_val = CMPAHR_reg_val << 8;
|
||
|
|
CMPAHR_reg_val += 0x0180;
|
||
|
|
EPwm3Regs.CMPA.half.CMPA = CMPA_reg_val;
|
||
|
|
EPwm3Regs.CMPA.half.CMPAHR = CMPAHR_reg_val;
|
||
|
|
|
||
|
|
// EPWM4 calculations
|
||
|
|
CMPA_reg_val = ((long)DutyFine * EPwm4Regs.TBPRD)>>15;
|
||
|
|
temp = ((long)DutyFine * EPwm4Regs.TBPRD) ;
|
||
|
|
temp = temp - ((long)CMPA_reg_val<<15);
|
||
|
|
CMPAHR_reg_val = (temp*MEP_ScaleFactor[4])>>15;
|
||
|
|
CMPAHR_reg_val = CMPAHR_reg_val << 8;
|
||
|
|
CMPAHR_reg_val += 0x0180;
|
||
|
|
EPwm4Regs.CMPA.half.CMPA = CMPA_reg_val;
|
||
|
|
EPwm4Regs.CMPA.half.CMPAHR = CMPAHR_reg_val;
|
||
|
|
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
// CMPA_reg_val is calculated as a Q0.
|
||
|
|
// Since DutyFine is a Q15 number, and the period is Q0
|
||
|
|
// the product is Q15. So to store as a Q0, we shift right
|
||
|
|
// 15 bits.
|
||
|
|
|
||
|
|
EPwm1Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm1Regs.TBPRD>>15);
|
||
|
|
EPwm2Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm2Regs.TBPRD)>>15;
|
||
|
|
EPwm3Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm3Regs.TBPRD)>>15;
|
||
|
|
EPwm4Regs.CMPA.half.CMPA = ((long)DutyFine * EPwm4Regs.TBPRD)>>15;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
for (i=0;i<300;i++)
|
||
|
|
{
|
||
|
|
// Call the scale factor optimizer lib
|
||
|
|
SFO_MepEn(1);
|
||
|
|
SFO_MepEn(2);
|
||
|
|
SFO_MepEn(3);
|
||
|
|
SFO_MepEn(4);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void HRPWM1_Config(period)
|
||
|
|
{
|
||
|
|
// ePWM1 register configuration with HRPWM
|
||
|
|
// ePWM1A toggle low/high with MEP control on Rising edge
|
||
|
|
|
||
|
|
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
|
||
|
|
EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period
|
||
|
|
EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
|
||
|
|
EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
|
||
|
|
EPwm1Regs.CMPB = period / 2; // set duty 50% initially
|
||
|
|
EPwm1Regs.TBPHS.all = 0;
|
||
|
|
EPwm1Regs.TBCTR = 0;
|
||
|
|
|
||
|
|
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
|
||
|
|
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master
|
||
|
|
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
|
||
|
|
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
|
||
|
|
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
|
||
|
|
EPwm1Regs.TBCTL.bit.FREE_SOFT = 11;
|
||
|
|
|
||
|
|
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
|
||
|
|
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
|
||
|
|
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
|
||
|
|
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
|
||
|
|
|
||
|
|
|
||
|
|
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
|
||
|
|
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
|
||
|
|
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;
|
||
|
|
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
EALLOW;
|
||
|
|
EPwm1Regs.HRCNFG.all = 0x0;
|
||
|
|
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge
|
||
|
|
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
|
||
|
|
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
|
||
|
|
EDIS;
|
||
|
|
}
|
||
|
|
|
||
|
|
void HRPWM2_Config(period)
|
||
|
|
{
|
||
|
|
// ePWM2 register configuration with HRPWM
|
||
|
|
// ePWM2A toggle low/high with MEP control on Rising edge
|
||
|
|
|
||
|
|
EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
|
||
|
|
EPwm2Regs.TBPRD = period-1; // PWM frequency = 1 / period
|
||
|
|
EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
|
||
|
|
EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
|
||
|
|
EPwm2Regs.CMPB = period / 2; // set duty 50% initially
|
||
|
|
EPwm2Regs.TBPHS.all = 0;
|
||
|
|
EPwm2Regs.TBCTR = 0;
|
||
|
|
|
||
|
|
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
|
||
|
|
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master
|
||
|
|
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
|
||
|
|
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
|
||
|
|
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
|
||
|
|
EPwm2Regs.TBCTL.bit.FREE_SOFT = 11;
|
||
|
|
|
||
|
|
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
|
||
|
|
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
|
||
|
|
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
|
||
|
|
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
|
||
|
|
|
||
|
|
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
|
||
|
|
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
|
||
|
|
EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET;
|
||
|
|
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;
|
||
|
|
|
||
|
|
EALLOW;
|
||
|
|
EPwm2Regs.HRCNFG.all = 0x0;
|
||
|
|
EPwm2Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge
|
||
|
|
EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP;
|
||
|
|
EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
|
||
|
|
|
||
|
|
EDIS;
|
||
|
|
|
||
|
|
}
|
||
|
|
void HRPWM3_Config(period)
|
||
|
|
{
|
||
|
|
// ePWM3 register configuration with HRPWM
|
||
|
|
// ePWM3A toggle high/low with MEP control on falling edge
|
||
|
|
|
||
|
|
EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
|
||
|
|
EPwm3Regs.TBPRD = period-1; // PWM frequency = 1 / period
|
||
|
|
EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
|
||
|
|
EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
|
||
|
|
EPwm3Regs.TBPHS.all = 0;
|
||
|
|
EPwm3Regs.TBCTR = 0;
|
||
|
|
|
||
|
|
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
|
||
|
|
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master
|
||
|
|
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
|
||
|
|
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
|
||
|
|
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
|
||
|
|
EPwm3Regs.TBCTL.bit.FREE_SOFT = 11;
|
||
|
|
|
||
|
|
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
|
||
|
|
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
|
||
|
|
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
|
||
|
|
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
|
||
|
|
|
||
|
|
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
|
||
|
|
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
|
||
|
|
EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;
|
||
|
|
EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;
|
||
|
|
|
||
|
|
EALLOW;
|
||
|
|
EPwm3Regs.HRCNFG.all = 0x0;
|
||
|
|
EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge
|
||
|
|
EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP;
|
||
|
|
EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
|
||
|
|
EDIS;
|
||
|
|
}
|
||
|
|
|
||
|
|
void HRPWM4_Config(period)
|
||
|
|
{
|
||
|
|
// ePWM4 register configuration with HRPWM
|
||
|
|
// ePWM4A toggle high/low with MEP control on falling edge
|
||
|
|
|
||
|
|
EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
|
||
|
|
EPwm4Regs.TBPRD = period-1; // PWM frequency = 1 / period
|
||
|
|
EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
|
||
|
|
EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
|
||
|
|
EPwm4Regs.CMPB = period / 2; // set duty 50% initially
|
||
|
|
EPwm4Regs.TBPHS.all = 0;
|
||
|
|
EPwm4Regs.TBCTR = 0;
|
||
|
|
|
||
|
|
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
|
||
|
|
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master
|
||
|
|
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
|
||
|
|
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
|
||
|
|
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
|
||
|
|
EPwm4Regs.TBCTL.bit.FREE_SOFT = 11;
|
||
|
|
|
||
|
|
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
|
||
|
|
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
|
||
|
|
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
|
||
|
|
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
|
||
|
|
|
||
|
|
EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
|
||
|
|
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
|
||
|
|
EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;
|
||
|
|
EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;
|
||
|
|
|
||
|
|
EALLOW;
|
||
|
|
EPwm4Regs.HRCNFG.all = 0x0;
|
||
|
|
EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on falling edge
|
||
|
|
EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP;
|
||
|
|
EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
|
||
|
|
EDIS;
|
||
|
|
}
|
||
|
|
|
||
|
|
// No more
|