310 lines
11 KiB
C
310 lines
11 KiB
C
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// TI File $Revision: /main/11 $
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// Checkin $Date: April 21, 2008 15:41:18 $
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//###########################################################################
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//
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// FILE: Example_2833xECanBack2Back.c
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//
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// TITLE: DSP2833x eCAN Back-to-back transmission and reception in
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// SELF-TEST mode
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//
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// ASSUMPTIONS:
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//
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// This program requires the DSP2833x header files.
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//
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// This progrm uses the peripheral's self test mode.
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// Other then boot mode configuration, no other hardware configuration
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// is required.
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//
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// As supplied, this project is configured for "boot to SARAM"
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// operation. The 2833x Boot Mode table is shown below.
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// For information on configuring the boot mode of an eZdsp,
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// please refer to the documentation included with the eZdsp,
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//
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// $Boot_Table:
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//
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// GPIO87 GPIO86 GPIO85 GPIO84
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// XA15 XA14 XA13 XA12
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// PU PU PU PU
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// ==========================================
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// 1 1 1 1 Jump to Flash
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// 1 1 1 0 SCI-A boot
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// 1 1 0 1 SPI-A boot
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// 1 1 0 0 I2C-A boot
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// 1 0 1 1 eCAN-A boot
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// 1 0 1 0 McBSP-A boot
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// 1 0 0 1 Jump to XINTF x16
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// 1 0 0 0 Jump to XINTF x32
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// 0 1 1 1 Jump to OTP
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// 0 1 1 0 Parallel GPIO I/O boot
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// 0 1 0 1 Parallel XINTF boot
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// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
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// 0 0 1 1 Branch to check boot mode
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// 0 0 1 0 Boot to flash, bypass ADC cal
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// 0 0 0 1 Boot to SARAM, bypass ADC cal
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// 0 0 0 0 Boot to SCI-A, bypass ADC cal
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// Boot_Table_End$
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//
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// DESCRIPTION:
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//
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// This test transmits data back-to-back at high speed without
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// stopping.
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// The received data is verified. Any error is flagged.
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// MBX0 transmits to MBX16, MBX1 transmits to MBX17 and so on....
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// This program illustrates the use of self-test mode
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//
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//###########################################################################
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// Original Author H.J.
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//
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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// Prototype statements for functions found within this file.
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void mailbox_check(int32 T1, int32 T2, int32 T3);
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void mailbox_read(int16 i);
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// Global variable for this example
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Uint32 ErrorCount;
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Uint32 PassCount;
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Uint32 MessageReceivedCount;
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Uint32 TestMbox1 = 0;
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Uint32 TestMbox2 = 0;
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Uint32 TestMbox3 = 0;
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void main(void)
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{
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Uint16 j;
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// eCAN control registers require read/write access using 32-bits. Thus we
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// will create a set of shadow registers for this example. These shadow
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// registers will be used to make sure the access is 32-bits and not 16.
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struct ECAN_REGS ECanaShadow;
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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InitSysCtrl();
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// Step 2. Initalize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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// InitGpio(); // Skipped for this example
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// For this example, configure CAN pins using GPIO regs here
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// This function is found in DSP2833x_ECan.c
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InitECanGpio();
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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DINT;
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// Initialize PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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InitPieCtrl();
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// Disable CPU interrupts and clear all CPU interrupt flags:
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IER = 0x0000;
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IFR = 0x0000;
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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InitPieVectTable();
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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// InitPeripherals(); // Not required for this example
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// Step 5. User specific code, enable interrupts:
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MessageReceivedCount = 0;
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ErrorCount = 0;
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PassCount = 0;
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InitECana(); // Initialize eCAN-A module
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// Mailboxs can be written to 16-bits or 32-bits at a time
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// Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 15
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ECanaMboxes.MBOX0.MSGID.all = 0x9555AAA0;
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ECanaMboxes.MBOX1.MSGID.all = 0x9555AAA1;
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ECanaMboxes.MBOX2.MSGID.all = 0x9555AAA2;
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ECanaMboxes.MBOX3.MSGID.all = 0x9555AAA3;
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ECanaMboxes.MBOX4.MSGID.all = 0x9555AAA4;
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ECanaMboxes.MBOX5.MSGID.all = 0x9555AAA5;
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ECanaMboxes.MBOX6.MSGID.all = 0x9555AAA6;
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ECanaMboxes.MBOX7.MSGID.all = 0x9555AAA7;
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ECanaMboxes.MBOX8.MSGID.all = 0x9555AAA8;
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ECanaMboxes.MBOX9.MSGID.all = 0x9555AAA9;
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ECanaMboxes.MBOX10.MSGID.all = 0x9555AAAA;
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ECanaMboxes.MBOX11.MSGID.all = 0x9555AAAB;
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ECanaMboxes.MBOX12.MSGID.all = 0x9555AAAC;
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ECanaMboxes.MBOX13.MSGID.all = 0x9555AAAD;
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ECanaMboxes.MBOX14.MSGID.all = 0x9555AAAE;
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ECanaMboxes.MBOX15.MSGID.all = 0x9555AAAF;
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// Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31
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ECanaMboxes.MBOX16.MSGID.all = 0x9555AAA0;
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ECanaMboxes.MBOX17.MSGID.all = 0x9555AAA1;
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ECanaMboxes.MBOX18.MSGID.all = 0x9555AAA2;
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ECanaMboxes.MBOX19.MSGID.all = 0x9555AAA3;
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ECanaMboxes.MBOX20.MSGID.all = 0x9555AAA4;
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ECanaMboxes.MBOX21.MSGID.all = 0x9555AAA5;
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ECanaMboxes.MBOX22.MSGID.all = 0x9555AAA6;
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ECanaMboxes.MBOX23.MSGID.all = 0x9555AAA7;
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ECanaMboxes.MBOX24.MSGID.all = 0x9555AAA8;
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ECanaMboxes.MBOX25.MSGID.all = 0x9555AAA9;
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ECanaMboxes.MBOX26.MSGID.all = 0x9555AAAA;
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ECanaMboxes.MBOX27.MSGID.all = 0x9555AAAB;
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ECanaMboxes.MBOX28.MSGID.all = 0x9555AAAC;
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ECanaMboxes.MBOX29.MSGID.all = 0x9555AAAD;
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ECanaMboxes.MBOX30.MSGID.all = 0x9555AAAE;
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ECanaMboxes.MBOX31.MSGID.all = 0x9555AAAF;
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// Configure Mailboxes 0-15 as Tx, 16-31 as Rx
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// Since this write is to the entire register (instead of a bit
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// field) a shadow register is not required.
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ECanaRegs.CANMD.all = 0xFFFF0000;
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// Enable all Mailboxes */
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// Since this write is to the entire register (instead of a bit
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// field) a shadow register is not required.
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ECanaRegs.CANME.all = 0xFFFFFFFF;
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// Specify that 8 bits will be sent/received
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ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8;
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ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8;
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// Write to the mailbox RAM field of MBOX0 - 15
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ECanaMboxes.MBOX0.MDL.all = 0x9555AAA0;
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ECanaMboxes.MBOX0.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX1.MDL.all = 0x9555AAA1;
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ECanaMboxes.MBOX1.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX2.MDL.all = 0x9555AAA2;
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ECanaMboxes.MBOX2.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX3.MDL.all = 0x9555AAA3;
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ECanaMboxes.MBOX3.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX4.MDL.all = 0x9555AAA4;
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ECanaMboxes.MBOX4.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX5.MDL.all = 0x9555AAA5;
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ECanaMboxes.MBOX5.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX6.MDL.all = 0x9555AAA6;
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ECanaMboxes.MBOX6.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX7.MDL.all = 0x9555AAA7;
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ECanaMboxes.MBOX7.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX8.MDL.all = 0x9555AAA8;
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ECanaMboxes.MBOX8.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX9.MDL.all = 0x9555AAA9;
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ECanaMboxes.MBOX9.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX10.MDL.all = 0x9555AAAA;
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ECanaMboxes.MBOX10.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX11.MDL.all = 0x9555AAAB;
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ECanaMboxes.MBOX11.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX12.MDL.all = 0x9555AAAC;
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ECanaMboxes.MBOX12.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX13.MDL.all = 0x9555AAAD;
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ECanaMboxes.MBOX13.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX14.MDL.all = 0x9555AAAE;
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ECanaMboxes.MBOX14.MDH.all = 0x89ABCDEF;
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ECanaMboxes.MBOX15.MDL.all = 0x9555AAAF;
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ECanaMboxes.MBOX15.MDH.all = 0x89ABCDEF;
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// Since this write is to the entire register (instead of a bit
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// field) a shadow register is not required.
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EALLOW;
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ECanaRegs.CANMIM.all = 0xFFFFFFFF;
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// Configure the eCAN for self test mode
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// Enable the enhanced features of the eCAN.
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EALLOW;
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ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
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ECanaShadow.CANMC.bit.STM = 1; // Configure CAN for self-test mode
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ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
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EDIS;
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// Begin transmitting
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for(;;)
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{
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ECanaRegs.CANTRS.all = 0x0000FFFF; // Set TRS for all transmit mailboxes
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while(ECanaRegs.CANTA.all != 0x0000FFFF ) {} // Wait for all TAn bits to be set..
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ECanaRegs.CANTA.all = 0x0000FFFF; // Clear all TAn
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MessageReceivedCount++;
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//Read from Receive mailboxes and begin checking for data */
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for(j=0; j<16; j++) // Read & check 16 mailboxes
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{
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mailbox_read(j); // This func reads the indicated mailbox data
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mailbox_check(TestMbox1,TestMbox2,TestMbox3); // Checks the received data
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}
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}
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}
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// This function reads out the contents of the indicated
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// by the Mailbox number (MBXnbr).
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void mailbox_read(int16 MBXnbr)
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{
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volatile struct MBOX *Mailbox;
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Mailbox = &ECanaMboxes.MBOX0 + MBXnbr;
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TestMbox1 = Mailbox->MDL.all; // = 0x9555AAAn (n is the MBX number)
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TestMbox2 = Mailbox->MDH.all; // = 0x89ABCDEF (a constant)
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TestMbox3 = Mailbox->MSGID.all;// = 0x9555AAAn (n is the MBX number)
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} // MSGID of a rcv MBX is transmitted as the MDL data.
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void mailbox_check(int32 T1, int32 T2, int32 T3)
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{
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if((T1 != T3) || ( T2 != 0x89ABCDEF))
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{
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ErrorCount++;
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}
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else
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{
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PassCount++;
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}
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}
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//===========================================================================
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// No more.
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//===========================================================================
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