265 lines
10 KiB
C
265 lines
10 KiB
C
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// TI File $Revision: /main/1 $
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// Checkin $Date: August 18, 2006 13:51:50 $
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//###########################################################################
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//
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// FILE: DSP2833x_Adc.h
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//
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// TITLE: DSP2833x Device ADC Register Definitions.
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//
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//###########################################################################
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// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
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// $Release Date: August 1, 2008 $
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//###########################################################################
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#ifndef DSP2833x_ADC_H
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#define DSP2833x_ADC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//---------------------------------------------------------------------------
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// ADC Individual Register Bit Definitions:
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struct ADCTRL1_BITS { // bits description
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Uint16 rsvd1:4; // 3:0 reserved
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Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
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Uint16 SEQ_OVRD:1; // 5 Sequencer override
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Uint16 CONT_RUN:1; // 6 Continuous run
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Uint16 CPS:1; // 7 ADC core clock pre-scalar
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Uint16 ACQ_PS:4; // 11:8 Acquisition window size
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Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
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Uint16 RESET:1; // 14 ADC reset
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Uint16 rsvd2:1; // 15 reserved
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};
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union ADCTRL1_REG {
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Uint16 all;
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struct ADCTRL1_BITS bit;
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};
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struct ADCTRL2_BITS { // bits description
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Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2
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Uint16 rsvd1:1; // 1 reserved
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Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode
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Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable
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Uint16 rsvd2:1; // 4 reserved
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Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2
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Uint16 RST_SEQ2:1; // 6 Reset SEQ2
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Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1
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Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1
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Uint16 rsvd3:1; // 9 reserved
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Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode
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Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable
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Uint16 rsvd4:1; // 12 reserved
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Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1
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Uint16 RST_SEQ1:1; // 14 Restart sequencer 1
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Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable
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};
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union ADCTRL2_REG {
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Uint16 all;
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struct ADCTRL2_BITS bit;
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};
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struct ADCASEQSR_BITS { // bits description
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Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state
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Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state
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Uint16 rsvd1:1; // 7 reserved
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Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status
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Uint16 rsvd2:4; // 15:12 reserved
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};
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union ADCASEQSR_REG {
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Uint16 all;
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struct ADCASEQSR_BITS bit;
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};
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struct ADCMAXCONV_BITS { // bits description
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Uint16 MAX_CONV1:4; // 3:0 Max number of conversions
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Uint16 MAX_CONV2:3; // 6:4 Max number of conversions
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Uint16 rsvd1:9; // 15:7 reserved
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};
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union ADCMAXCONV_REG {
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Uint16 all;
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struct ADCMAXCONV_BITS bit;
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};
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struct ADCCHSELSEQ1_BITS { // bits description
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Uint16 CONV00:4; // 3:0 Conversion selection 00
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Uint16 CONV01:4; // 7:4 Conversion selection 01
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Uint16 CONV02:4; // 11:8 Conversion selection 02
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Uint16 CONV03:4; // 15:12 Conversion selection 03
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};
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union ADCCHSELSEQ1_REG{
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Uint16 all;
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struct ADCCHSELSEQ1_BITS bit;
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};
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struct ADCCHSELSEQ2_BITS { // bits description
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Uint16 CONV04:4; // 3:0 Conversion selection 04
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Uint16 CONV05:4; // 7:4 Conversion selection 05
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Uint16 CONV06:4; // 11:8 Conversion selection 06
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Uint16 CONV07:4; // 15:12 Conversion selection 07
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};
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union ADCCHSELSEQ2_REG{
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Uint16 all;
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struct ADCCHSELSEQ2_BITS bit;
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};
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struct ADCCHSELSEQ3_BITS { // bits description
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Uint16 CONV08:4; // 3:0 Conversion selection 08
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Uint16 CONV09:4; // 7:4 Conversion selection 09
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Uint16 CONV10:4; // 11:8 Conversion selection 10
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Uint16 CONV11:4; // 15:12 Conversion selection 11
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};
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union ADCCHSELSEQ3_REG{
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Uint16 all;
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struct ADCCHSELSEQ3_BITS bit;
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};
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struct ADCCHSELSEQ4_BITS { // bits description
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Uint16 CONV12:4; // 3:0 Conversion selection 12
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Uint16 CONV13:4; // 7:4 Conversion selection 13
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Uint16 CONV14:4; // 11:8 Conversion selection 14
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Uint16 CONV15:4; // 15:12 Conversion selection 15
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};
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union ADCCHSELSEQ4_REG {
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Uint16 all;
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struct ADCCHSELSEQ4_BITS bit;
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};
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struct ADCTRL3_BITS { // bits description
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Uint16 SMODE_SEL:1; // 0 Sampling mode select
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Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider
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Uint16 ADCPWDN:1; // 5 ADC powerdown
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Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down
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Uint16 rsvd1:8; // 15:8 reserved
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};
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union ADCTRL3_REG {
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Uint16 all;
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struct ADCTRL3_BITS bit;
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};
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struct ADCST_BITS { // bits description
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Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag
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Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag
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Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status
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Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status
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Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear
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Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear
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Uint16 EOS_BUF1:1; // 6 End of sequence buffer1
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Uint16 EOS_BUF2:1; // 7 End of sequence buffer2
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Uint16 rsvd1:8; // 15:8 reserved
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};
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union ADCST_REG {
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Uint16 all;
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struct ADCST_BITS bit;
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};
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struct ADCREFSEL_BITS { // bits description
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Uint16 rsvd1:14; // 13:0 reserved
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Uint16 REF_SEL:2; // 15:14 Reference select
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};
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union ADCREFSEL_REG {
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Uint16 all;
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struct ADCREFSEL_BITS bit;
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};
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struct ADCOFFTRIM_BITS{ // bits description
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int16 OFFSET_TRIM:9; // 8:0 Offset Trim
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Uint16 rsvd1:7; // 15:9 reserved
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};
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union ADCOFFTRIM_REG{
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Uint16 all;
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struct ADCOFFTRIM_BITS bit;
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};
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struct ADC_REGS {
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union ADCTRL1_REG ADCTRL1; // ADC Control 1
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union ADCTRL2_REG ADCTRL2; // ADC Control 2
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union ADCMAXCONV_REG ADCMAXCONV; // Max conversions
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union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1
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union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2
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union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3
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union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4
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union ADCASEQSR_REG ADCASEQSR; // Autosequence status register
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Uint16 ADCRESULT0; // Conversion Result Buffer 0
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Uint16 ADCRESULT1; // Conversion Result Buffer 1
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Uint16 ADCRESULT2; // Conversion Result Buffer 2
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Uint16 ADCRESULT3; // Conversion Result Buffer 3
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Uint16 ADCRESULT4; // Conversion Result Buffer 4
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Uint16 ADCRESULT5; // Conversion Result Buffer 5
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Uint16 ADCRESULT6; // Conversion Result Buffer 6
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Uint16 ADCRESULT7; // Conversion Result Buffer 7
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Uint16 ADCRESULT8; // Conversion Result Buffer 8
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Uint16 ADCRESULT9; // Conversion Result Buffer 9
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Uint16 ADCRESULT10; // Conversion Result Buffer 10
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Uint16 ADCRESULT11; // Conversion Result Buffer 11
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Uint16 ADCRESULT12; // Conversion Result Buffer 12
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Uint16 ADCRESULT13; // Conversion Result Buffer 13
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Uint16 ADCRESULT14; // Conversion Result Buffer 14
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Uint16 ADCRESULT15; // Conversion Result Buffer 15
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union ADCTRL3_REG ADCTRL3; // ADC Control 3
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union ADCST_REG ADCST; // ADC Status Register
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Uint16 rsvd1;
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Uint16 rsvd2;
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union ADCREFSEL_REG ADCREFSEL; // Reference Select Register
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union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register
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};
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struct ADC_RESULT_MIRROR_REGS
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{
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Uint16 ADCRESULT0; // Conversion Result Buffer 0
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Uint16 ADCRESULT1; // Conversion Result Buffer 1
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Uint16 ADCRESULT2; // Conversion Result Buffer 2
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Uint16 ADCRESULT3; // Conversion Result Buffer 3
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Uint16 ADCRESULT4; // Conversion Result Buffer 4
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Uint16 ADCRESULT5; // Conversion Result Buffer 5
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Uint16 ADCRESULT6; // Conversion Result Buffer 6
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Uint16 ADCRESULT7; // Conversion Result Buffer 7
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Uint16 ADCRESULT8; // Conversion Result Buffer 8
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Uint16 ADCRESULT9; // Conversion Result Buffer 9
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Uint16 ADCRESULT10; // Conversion Result Buffer 10
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Uint16 ADCRESULT11; // Conversion Result Buffer 11
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Uint16 ADCRESULT12; // Conversion Result Buffer 12
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Uint16 ADCRESULT13; // Conversion Result Buffer 13
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Uint16 ADCRESULT14; // Conversion Result Buffer 14
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Uint16 ADCRESULT15; // Conversion Result Buffer 15
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};
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//---------------------------------------------------------------------------
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// ADC External References & Function Declarations:
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//
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extern volatile struct ADC_REGS AdcRegs;
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extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_ADC_H definition
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//===========================================================================
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// End of file.
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//===========================================================================
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